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7448 nvme: performance regression when volatile write cache not present
Reviewed by: Robert Mustacchi <rm@joyent.com>
Reviewed by: Garrett D'Amore <garrett@damore.org>
Reviewed by: Hans Rosenfeld <hans.rosenfeld@nexenta.com>
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--- old/usr/src/uts/common/io/nvme/nvme.c
+++ new/usr/src/uts/common/io/nvme/nvme.c
1 1 /*
2 2 * This file and its contents are supplied under the terms of the
3 3 * Common Development and Distribution License ("CDDL"), version 1.0.
4 4 * You may only use this file in accordance with the terms of version
5 5 * 1.0 of the CDDL.
6 6 *
7 7 * A full copy of the text of the CDDL should have accompanied this
8 8 * source. A copy of the CDDL is also available via the Internet at
9 9 * http://www.illumos.org/license/CDDL.
10 10 */
11 11
12 12 /*
13 13 * Copyright 2016 Nexenta Systems, Inc. All rights reserved.
14 14 * Copyright 2016 Tegile Systems, Inc. All rights reserved.
15 15 * Copyright (c) 2016 The MathWorks, Inc. All rights reserved.
16 16 */
17 17
18 18 /*
19 19 * blkdev driver for NVMe compliant storage devices
20 20 *
21 21 * This driver was written to conform to version 1.1b of the NVMe specification.
22 22 * It may work with newer versions, but that is completely untested and disabled
23 23 * by default.
24 24 *
25 25 * The driver has only been tested on x86 systems and will not work on big-
26 26 * endian systems without changes to the code accessing registers and data
27 27 * structures used by the hardware.
28 28 *
29 29 *
30 30 * Interrupt Usage:
31 31 *
32 32 * The driver will use a FIXED interrupt while configuring the device as the
33 33 * specification requires. Later in the attach process it will switch to MSI-X
34 34 * or MSI if supported. The driver wants to have one interrupt vector per CPU,
35 35 * but it will work correctly if less are available. Interrupts can be shared
36 36 * by queues, the interrupt handler will iterate through the I/O queue array by
37 37 * steps of n_intr_cnt. Usually only the admin queue will share an interrupt
38 38 * with one I/O queue. The interrupt handler will retrieve completed commands
39 39 * from all queues sharing an interrupt vector and will post them to a taskq
40 40 * for completion processing.
41 41 *
42 42 *
43 43 * Command Processing:
44 44 *
45 45 * NVMe devices can have up to 65536 I/O queue pairs, with each queue holding up
46 46 * to 65536 I/O commands. The driver will configure one I/O queue pair per
47 47 * available interrupt vector, with the queue length usually much smaller than
48 48 * the maximum of 65536. If the hardware doesn't provide enough queues, fewer
49 49 * interrupt vectors will be used.
50 50 *
51 51 * Additionally the hardware provides a single special admin queue pair that can
52 52 * hold up to 4096 admin commands.
53 53 *
54 54 * From the hardware perspective both queues of a queue pair are independent,
55 55 * but they share some driver state: the command array (holding pointers to
56 56 * commands currently being processed by the hardware) and the active command
57 57 * counter. Access to the submission side of a queue pair and the shared state
58 58 * is protected by nq_mutex. The completion side of a queue pair does not need
59 59 * that protection apart from its access to the shared state; it is called only
60 60 * in the interrupt handler which does not run concurrently for the same
61 61 * interrupt vector.
62 62 *
63 63 * When a command is submitted to a queue pair the active command counter is
64 64 * incremented and a pointer to the command is stored in the command array. The
65 65 * array index is used as command identifier (CID) in the submission queue
66 66 * entry. Some commands may take a very long time to complete, and if the queue
67 67 * wraps around in that time a submission may find the next array slot to still
68 68 * be used by a long-running command. In this case the array is sequentially
69 69 * searched for the next free slot. The length of the command array is the same
70 70 * as the configured queue length.
71 71 *
72 72 *
73 73 * Namespace Support:
74 74 *
75 75 * NVMe devices can have multiple namespaces, each being a independent data
76 76 * store. The driver supports multiple namespaces and creates a blkdev interface
77 77 * for each namespace found. Namespaces can have various attributes to support
78 78 * thin provisioning and protection information. This driver does not support
79 79 * any of this and ignores namespaces that have these attributes.
80 80 *
81 81 * As of NVMe 1.1 namespaces can have an 64bit Extended Unique Identifier
82 82 * (EUI64). This driver uses the EUI64 if present to generate the devid and
83 83 * passes it to blkdev to use it in the device node names. As this is currently
84 84 * untested namespaces with EUI64 are ignored by default.
85 85 *
86 86 *
87 87 * Blkdev Interface:
88 88 *
89 89 * This driver uses blkdev to do all the heavy lifting involved with presenting
90 90 * a disk device to the system. As a result, the processing of I/O requests is
91 91 * relatively simple as blkdev takes care of partitioning, boundary checks, DMA
92 92 * setup, and splitting of transfers into manageable chunks.
93 93 *
94 94 * I/O requests coming in from blkdev are turned into NVM commands and posted to
95 95 * an I/O queue. The queue is selected by taking the CPU id modulo the number of
96 96 * queues. There is currently no timeout handling of I/O commands.
97 97 *
98 98 * Blkdev also supports querying device/media information and generating a
99 99 * devid. The driver reports the best block size as determined by the namespace
100 100 * format back to blkdev as physical block size to support partition and block
101 101 * alignment. The devid is either based on the namespace EUI64, if present, or
102 102 * composed using the device vendor ID, model number, serial number, and the
103 103 * namespace ID.
104 104 *
105 105 *
106 106 * Error Handling:
107 107 *
108 108 * Error handling is currently limited to detecting fatal hardware errors,
109 109 * either by asynchronous events, or synchronously through command status or
110 110 * admin command timeouts. In case of severe errors the device is fenced off,
111 111 * all further requests will return EIO. FMA is then called to fault the device.
112 112 *
113 113 * The hardware has a limit for outstanding asynchronous event requests. Before
114 114 * this limit is known the driver assumes it is at least 1 and posts a single
115 115 * asynchronous request. Later when the limit is known more asynchronous event
116 116 * requests are posted to allow quicker reception of error information. When an
117 117 * asynchronous event is posted by the hardware the driver will parse the error
118 118 * status fields and log information or fault the device, depending on the
119 119 * severity of the asynchronous event. The asynchronous event request is then
120 120 * reused and posted to the admin queue again.
121 121 *
122 122 * On command completion the command status is checked for errors. In case of
123 123 * errors indicating a driver bug the driver panics. Almost all other error
124 124 * status values just cause EIO to be returned.
125 125 *
126 126 * Command timeouts are currently detected for all admin commands except
127 127 * asynchronous event requests. If a command times out and the hardware appears
128 128 * to be healthy the driver attempts to abort the command. If this fails the
129 129 * driver assumes the device to be dead, fences it off, and calls FMA to retire
130 130 * it. In general admin commands are issued at attach time only. No timeout
131 131 * handling of normal I/O commands is presently done.
132 132 *
133 133 * In some cases it may be possible that the ABORT command times out, too. In
134 134 * that case the device is also declared dead and fenced off.
135 135 *
136 136 *
137 137 * Quiesce / Fast Reboot:
138 138 *
139 139 * The driver currently does not support fast reboot. A quiesce(9E) entry point
140 140 * is still provided which is used to send a shutdown notification to the
141 141 * device.
142 142 *
143 143 *
144 144 * Driver Configuration:
145 145 *
146 146 * The following driver properties can be changed to control some aspects of the
147 147 * drivers operation:
148 148 * - strict-version: can be set to 0 to allow devices conforming to newer
149 149 * versions or namespaces with EUI64 to be used
150 150 * - ignore-unknown-vendor-status: can be set to 1 to not handle any vendor
151 151 * specific command status as a fatal error leading device faulting
152 152 * - admin-queue-len: the maximum length of the admin queue (16-4096)
153 153 * - io-queue-len: the maximum length of the I/O queues (16-65536)
154 154 * - async-event-limit: the maximum number of asynchronous event requests to be
155 155 * posted by the driver
156 156 * - volatile-write-cache-enable: can be set to 0 to disable the volatile write
157 157 * cache
158 158 * - min-phys-block-size: the minimum physical block size to report to blkdev,
159 159 * which is among other things the basis for ZFS vdev ashift
160 160 *
161 161 *
162 162 * TODO:
163 163 * - figure out sane default for I/O queue depth reported to blkdev
164 164 * - polled I/O support to support kernel core dumping
165 165 * - FMA handling of media errors
166 166 * - support for devices supporting very large I/O requests using chained PRPs
167 167 * - support for querying log pages from user space
168 168 * - support for configuring hardware parameters like interrupt coalescing
169 169 * - support for media formatting and hard partitioning into namespaces
170 170 * - support for big-endian systems
171 171 * - support for fast reboot
172 172 * - support for firmware updates
173 173 * - support for NVMe Subsystem Reset (1.1)
174 174 * - support for Scatter/Gather lists (1.1)
175 175 * - support for Reservations (1.1)
176 176 * - support for power management
177 177 */
178 178
179 179 #include <sys/byteorder.h>
180 180 #ifdef _BIG_ENDIAN
181 181 #error nvme driver needs porting for big-endian platforms
182 182 #endif
183 183
184 184 #include <sys/modctl.h>
185 185 #include <sys/conf.h>
186 186 #include <sys/devops.h>
187 187 #include <sys/ddi.h>
188 188 #include <sys/sunddi.h>
189 189 #include <sys/bitmap.h>
190 190 #include <sys/sysmacros.h>
191 191 #include <sys/param.h>
192 192 #include <sys/varargs.h>
193 193 #include <sys/cpuvar.h>
194 194 #include <sys/disp.h>
195 195 #include <sys/blkdev.h>
196 196 #include <sys/atomic.h>
197 197 #include <sys/archsystm.h>
198 198 #include <sys/sata/sata_hba.h>
199 199
200 200 #include "nvme_reg.h"
201 201 #include "nvme_var.h"
202 202
203 203
204 204 /* NVMe spec version supported */
205 205 static const int nvme_version_major = 1;
206 206 static const int nvme_version_minor = 1;
207 207
208 208 /* tunable for admin command timeout in seconds, default is 1s */
209 209 static volatile int nvme_admin_cmd_timeout = 1;
210 210
211 211 static int nvme_attach(dev_info_t *, ddi_attach_cmd_t);
212 212 static int nvme_detach(dev_info_t *, ddi_detach_cmd_t);
213 213 static int nvme_quiesce(dev_info_t *);
214 214 static int nvme_fm_errcb(dev_info_t *, ddi_fm_error_t *, const void *);
215 215 static int nvme_setup_interrupts(nvme_t *, int, int);
216 216 static void nvme_release_interrupts(nvme_t *);
217 217 static uint_t nvme_intr(caddr_t, caddr_t);
218 218
219 219 static void nvme_shutdown(nvme_t *, int, boolean_t);
220 220 static boolean_t nvme_reset(nvme_t *, boolean_t);
221 221 static int nvme_init(nvme_t *);
222 222 static nvme_cmd_t *nvme_alloc_cmd(nvme_t *, int);
223 223 static void nvme_free_cmd(nvme_cmd_t *);
224 224 static nvme_cmd_t *nvme_create_nvm_cmd(nvme_namespace_t *, uint8_t,
225 225 bd_xfer_t *);
226 226 static int nvme_admin_cmd(nvme_cmd_t *, int);
227 227 static int nvme_submit_cmd(nvme_qpair_t *, nvme_cmd_t *);
228 228 static nvme_cmd_t *nvme_retrieve_cmd(nvme_t *, nvme_qpair_t *);
229 229 static boolean_t nvme_wait_cmd(nvme_cmd_t *, uint_t);
230 230 static void nvme_wakeup_cmd(void *);
231 231 static void nvme_async_event_task(void *);
232 232
233 233 static int nvme_check_unknown_cmd_status(nvme_cmd_t *);
234 234 static int nvme_check_vendor_cmd_status(nvme_cmd_t *);
235 235 static int nvme_check_integrity_cmd_status(nvme_cmd_t *);
236 236 static int nvme_check_specific_cmd_status(nvme_cmd_t *);
237 237 static int nvme_check_generic_cmd_status(nvme_cmd_t *);
238 238 static inline int nvme_check_cmd_status(nvme_cmd_t *);
239 239
240 240 static void nvme_abort_cmd(nvme_cmd_t *);
241 241 static int nvme_async_event(nvme_t *);
242 242 static void *nvme_get_logpage(nvme_t *, uint8_t, ...);
243 243 static void *nvme_identify(nvme_t *, uint32_t);
244 244 static boolean_t nvme_set_features(nvme_t *, uint32_t, uint8_t, uint32_t,
245 245 uint32_t *);
246 246 static boolean_t nvme_write_cache_set(nvme_t *, boolean_t);
247 247 static int nvme_set_nqueues(nvme_t *, uint16_t);
248 248
249 249 static void nvme_free_dma(nvme_dma_t *);
250 250 static int nvme_zalloc_dma(nvme_t *, size_t, uint_t, ddi_dma_attr_t *,
251 251 nvme_dma_t **);
252 252 static int nvme_zalloc_queue_dma(nvme_t *, uint32_t, uint16_t, uint_t,
253 253 nvme_dma_t **);
254 254 static void nvme_free_qpair(nvme_qpair_t *);
255 255 static int nvme_alloc_qpair(nvme_t *, uint32_t, nvme_qpair_t **, int);
256 256 static int nvme_create_io_qpair(nvme_t *, nvme_qpair_t *, uint16_t);
257 257
258 258 static inline void nvme_put64(nvme_t *, uintptr_t, uint64_t);
259 259 static inline void nvme_put32(nvme_t *, uintptr_t, uint32_t);
260 260 static inline uint64_t nvme_get64(nvme_t *, uintptr_t);
261 261 static inline uint32_t nvme_get32(nvme_t *, uintptr_t);
262 262
263 263 static boolean_t nvme_check_regs_hdl(nvme_t *);
264 264 static boolean_t nvme_check_dma_hdl(nvme_dma_t *);
265 265
266 266 static int nvme_fill_prp(nvme_cmd_t *, bd_xfer_t *);
267 267
268 268 static void nvme_bd_xfer_done(void *);
269 269 static void nvme_bd_driveinfo(void *, bd_drive_t *);
270 270 static int nvme_bd_mediainfo(void *, bd_media_t *);
271 271 static int nvme_bd_cmd(nvme_namespace_t *, bd_xfer_t *, uint8_t);
272 272 static int nvme_bd_read(void *, bd_xfer_t *);
273 273 static int nvme_bd_write(void *, bd_xfer_t *);
274 274 static int nvme_bd_sync(void *, bd_xfer_t *);
275 275 static int nvme_bd_devid(void *, dev_info_t *, ddi_devid_t *);
276 276
277 277 static int nvme_prp_dma_constructor(void *, void *, int);
278 278 static void nvme_prp_dma_destructor(void *, void *);
279 279
280 280 static void nvme_prepare_devid(nvme_t *, uint32_t);
281 281
282 282 static void *nvme_state;
283 283 static kmem_cache_t *nvme_cmd_cache;
284 284
285 285 /*
286 286 * DMA attributes for queue DMA memory
287 287 *
288 288 * Queue DMA memory must be page aligned. The maximum length of a queue is
289 289 * 65536 entries, and an entry can be 64 bytes long.
290 290 */
291 291 static ddi_dma_attr_t nvme_queue_dma_attr = {
292 292 .dma_attr_version = DMA_ATTR_V0,
293 293 .dma_attr_addr_lo = 0,
294 294 .dma_attr_addr_hi = 0xffffffffffffffffULL,
295 295 .dma_attr_count_max = (UINT16_MAX + 1) * sizeof (nvme_sqe_t) - 1,
296 296 .dma_attr_align = 0x1000,
297 297 .dma_attr_burstsizes = 0x7ff,
298 298 .dma_attr_minxfer = 0x1000,
299 299 .dma_attr_maxxfer = (UINT16_MAX + 1) * sizeof (nvme_sqe_t),
300 300 .dma_attr_seg = 0xffffffffffffffffULL,
301 301 .dma_attr_sgllen = 1,
302 302 .dma_attr_granular = 1,
303 303 .dma_attr_flags = 0,
304 304 };
305 305
306 306 /*
307 307 * DMA attributes for transfers using Physical Region Page (PRP) entries
308 308 *
309 309 * A PRP entry describes one page of DMA memory using the page size specified
310 310 * in the controller configuration's memory page size register (CC.MPS). It uses
311 311 * a 64bit base address aligned to this page size. There is no limitation on
312 312 * chaining PRPs together for arbitrarily large DMA transfers.
313 313 */
314 314 static ddi_dma_attr_t nvme_prp_dma_attr = {
315 315 .dma_attr_version = DMA_ATTR_V0,
316 316 .dma_attr_addr_lo = 0,
317 317 .dma_attr_addr_hi = 0xffffffffffffffffULL,
318 318 .dma_attr_count_max = 0xfff,
319 319 .dma_attr_align = 0x1000,
320 320 .dma_attr_burstsizes = 0x7ff,
321 321 .dma_attr_minxfer = 0x1000,
322 322 .dma_attr_maxxfer = 0x1000,
323 323 .dma_attr_seg = 0xfff,
324 324 .dma_attr_sgllen = -1,
325 325 .dma_attr_granular = 1,
326 326 .dma_attr_flags = 0,
327 327 };
328 328
329 329 /*
330 330 * DMA attributes for transfers using scatter/gather lists
331 331 *
332 332 * A SGL entry describes a chunk of DMA memory using a 64bit base address and a
333 333 * 32bit length field. SGL Segment and SGL Last Segment entries require the
334 334 * length to be a multiple of 16 bytes.
335 335 */
336 336 static ddi_dma_attr_t nvme_sgl_dma_attr = {
337 337 .dma_attr_version = DMA_ATTR_V0,
338 338 .dma_attr_addr_lo = 0,
339 339 .dma_attr_addr_hi = 0xffffffffffffffffULL,
340 340 .dma_attr_count_max = 0xffffffffUL,
341 341 .dma_attr_align = 1,
342 342 .dma_attr_burstsizes = 0x7ff,
343 343 .dma_attr_minxfer = 0x10,
344 344 .dma_attr_maxxfer = 0xfffffffffULL,
345 345 .dma_attr_seg = 0xffffffffffffffffULL,
346 346 .dma_attr_sgllen = -1,
347 347 .dma_attr_granular = 0x10,
348 348 .dma_attr_flags = 0
349 349 };
350 350
351 351 static ddi_device_acc_attr_t nvme_reg_acc_attr = {
352 352 .devacc_attr_version = DDI_DEVICE_ATTR_V0,
353 353 .devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC,
354 354 .devacc_attr_dataorder = DDI_STRICTORDER_ACC
355 355 };
356 356
357 357 static struct dev_ops nvme_dev_ops = {
358 358 .devo_rev = DEVO_REV,
359 359 .devo_refcnt = 0,
360 360 .devo_getinfo = ddi_no_info,
361 361 .devo_identify = nulldev,
362 362 .devo_probe = nulldev,
363 363 .devo_attach = nvme_attach,
364 364 .devo_detach = nvme_detach,
365 365 .devo_reset = nodev,
366 366 .devo_cb_ops = NULL,
367 367 .devo_bus_ops = NULL,
368 368 .devo_power = NULL,
369 369 .devo_quiesce = nvme_quiesce,
370 370 };
371 371
372 372 static struct modldrv nvme_modldrv = {
373 373 .drv_modops = &mod_driverops,
374 374 .drv_linkinfo = "NVMe v1.1b",
375 375 .drv_dev_ops = &nvme_dev_ops
376 376 };
377 377
378 378 static struct modlinkage nvme_modlinkage = {
379 379 .ml_rev = MODREV_1,
380 380 .ml_linkage = { &nvme_modldrv, NULL }
381 381 };
382 382
383 383 static bd_ops_t nvme_bd_ops = {
384 384 .o_version = BD_OPS_VERSION_0,
385 385 .o_drive_info = nvme_bd_driveinfo,
386 386 .o_media_info = nvme_bd_mediainfo,
387 387 .o_devid_init = nvme_bd_devid,
388 388 .o_sync_cache = nvme_bd_sync,
389 389 .o_read = nvme_bd_read,
390 390 .o_write = nvme_bd_write,
391 391 };
392 392
393 393 int
394 394 _init(void)
395 395 {
396 396 int error;
397 397
398 398 error = ddi_soft_state_init(&nvme_state, sizeof (nvme_t), 1);
399 399 if (error != DDI_SUCCESS)
400 400 return (error);
401 401
402 402 nvme_cmd_cache = kmem_cache_create("nvme_cmd_cache",
403 403 sizeof (nvme_cmd_t), 64, NULL, NULL, NULL, NULL, NULL, 0);
404 404
405 405 bd_mod_init(&nvme_dev_ops);
406 406
407 407 error = mod_install(&nvme_modlinkage);
408 408 if (error != DDI_SUCCESS) {
409 409 ddi_soft_state_fini(&nvme_state);
410 410 bd_mod_fini(&nvme_dev_ops);
411 411 }
412 412
413 413 return (error);
414 414 }
415 415
416 416 int
417 417 _fini(void)
418 418 {
419 419 int error;
420 420
421 421 error = mod_remove(&nvme_modlinkage);
422 422 if (error == DDI_SUCCESS) {
423 423 ddi_soft_state_fini(&nvme_state);
424 424 kmem_cache_destroy(nvme_cmd_cache);
425 425 bd_mod_fini(&nvme_dev_ops);
426 426 }
427 427
428 428 return (error);
429 429 }
430 430
431 431 int
432 432 _info(struct modinfo *modinfop)
433 433 {
434 434 return (mod_info(&nvme_modlinkage, modinfop));
435 435 }
436 436
437 437 static inline void
438 438 nvme_put64(nvme_t *nvme, uintptr_t reg, uint64_t val)
439 439 {
440 440 ASSERT(((uintptr_t)(nvme->n_regs + reg) & 0x7) == 0);
441 441
442 442 /*LINTED: E_BAD_PTR_CAST_ALIGN*/
443 443 ddi_put64(nvme->n_regh, (uint64_t *)(nvme->n_regs + reg), val);
444 444 }
445 445
446 446 static inline void
447 447 nvme_put32(nvme_t *nvme, uintptr_t reg, uint32_t val)
448 448 {
449 449 ASSERT(((uintptr_t)(nvme->n_regs + reg) & 0x3) == 0);
450 450
451 451 /*LINTED: E_BAD_PTR_CAST_ALIGN*/
452 452 ddi_put32(nvme->n_regh, (uint32_t *)(nvme->n_regs + reg), val);
453 453 }
454 454
455 455 static inline uint64_t
456 456 nvme_get64(nvme_t *nvme, uintptr_t reg)
457 457 {
458 458 uint64_t val;
459 459
460 460 ASSERT(((uintptr_t)(nvme->n_regs + reg) & 0x7) == 0);
461 461
462 462 /*LINTED: E_BAD_PTR_CAST_ALIGN*/
463 463 val = ddi_get64(nvme->n_regh, (uint64_t *)(nvme->n_regs + reg));
464 464
465 465 return (val);
466 466 }
467 467
468 468 static inline uint32_t
469 469 nvme_get32(nvme_t *nvme, uintptr_t reg)
470 470 {
471 471 uint32_t val;
472 472
473 473 ASSERT(((uintptr_t)(nvme->n_regs + reg) & 0x3) == 0);
474 474
475 475 /*LINTED: E_BAD_PTR_CAST_ALIGN*/
476 476 val = ddi_get32(nvme->n_regh, (uint32_t *)(nvme->n_regs + reg));
477 477
478 478 return (val);
479 479 }
480 480
481 481 static boolean_t
482 482 nvme_check_regs_hdl(nvme_t *nvme)
483 483 {
484 484 ddi_fm_error_t error;
485 485
486 486 ddi_fm_acc_err_get(nvme->n_regh, &error, DDI_FME_VERSION);
487 487
488 488 if (error.fme_status != DDI_FM_OK)
489 489 return (B_TRUE);
490 490
491 491 return (B_FALSE);
492 492 }
493 493
494 494 static boolean_t
495 495 nvme_check_dma_hdl(nvme_dma_t *dma)
496 496 {
497 497 ddi_fm_error_t error;
498 498
499 499 if (dma == NULL)
500 500 return (B_FALSE);
501 501
502 502 ddi_fm_dma_err_get(dma->nd_dmah, &error, DDI_FME_VERSION);
503 503
504 504 if (error.fme_status != DDI_FM_OK)
505 505 return (B_TRUE);
506 506
507 507 return (B_FALSE);
508 508 }
509 509
510 510 static void
511 511 nvme_free_dma_common(nvme_dma_t *dma)
512 512 {
513 513 if (dma->nd_dmah != NULL)
514 514 (void) ddi_dma_unbind_handle(dma->nd_dmah);
515 515 if (dma->nd_acch != NULL)
516 516 ddi_dma_mem_free(&dma->nd_acch);
517 517 if (dma->nd_dmah != NULL)
518 518 ddi_dma_free_handle(&dma->nd_dmah);
519 519 }
520 520
521 521 static void
522 522 nvme_free_dma(nvme_dma_t *dma)
523 523 {
524 524 nvme_free_dma_common(dma);
525 525 kmem_free(dma, sizeof (*dma));
526 526 }
527 527
528 528 /* ARGSUSED */
529 529 static void
530 530 nvme_prp_dma_destructor(void *buf, void *private)
531 531 {
532 532 nvme_dma_t *dma = (nvme_dma_t *)buf;
533 533
534 534 nvme_free_dma_common(dma);
535 535 }
536 536
537 537 static int
538 538 nvme_alloc_dma_common(nvme_t *nvme, nvme_dma_t *dma,
539 539 size_t len, uint_t flags, ddi_dma_attr_t *dma_attr)
540 540 {
541 541 if (ddi_dma_alloc_handle(nvme->n_dip, dma_attr, DDI_DMA_SLEEP, NULL,
542 542 &dma->nd_dmah) != DDI_SUCCESS) {
543 543 /*
544 544 * Due to DDI_DMA_SLEEP this can't be DDI_DMA_NORESOURCES, and
545 545 * the only other possible error is DDI_DMA_BADATTR which
546 546 * indicates a driver bug which should cause a panic.
547 547 */
548 548 dev_err(nvme->n_dip, CE_PANIC,
549 549 "!failed to get DMA handle, check DMA attributes");
550 550 return (DDI_FAILURE);
551 551 }
552 552
553 553 /*
554 554 * ddi_dma_mem_alloc() can only fail when DDI_DMA_NOSLEEP is specified
555 555 * or the flags are conflicting, which isn't the case here.
556 556 */
557 557 (void) ddi_dma_mem_alloc(dma->nd_dmah, len, &nvme->n_reg_acc_attr,
558 558 DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, NULL, &dma->nd_memp,
559 559 &dma->nd_len, &dma->nd_acch);
560 560
561 561 if (ddi_dma_addr_bind_handle(dma->nd_dmah, NULL, dma->nd_memp,
562 562 dma->nd_len, flags | DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, NULL,
563 563 &dma->nd_cookie, &dma->nd_ncookie) != DDI_DMA_MAPPED) {
564 564 dev_err(nvme->n_dip, CE_WARN,
565 565 "!failed to bind DMA memory");
566 566 atomic_inc_32(&nvme->n_dma_bind_err);
567 567 nvme_free_dma_common(dma);
568 568 return (DDI_FAILURE);
569 569 }
570 570
571 571 return (DDI_SUCCESS);
572 572 }
573 573
574 574 static int
575 575 nvme_zalloc_dma(nvme_t *nvme, size_t len, uint_t flags,
576 576 ddi_dma_attr_t *dma_attr, nvme_dma_t **ret)
577 577 {
578 578 nvme_dma_t *dma = kmem_zalloc(sizeof (nvme_dma_t), KM_SLEEP);
579 579
580 580 if (nvme_alloc_dma_common(nvme, dma, len, flags, dma_attr) !=
581 581 DDI_SUCCESS) {
582 582 *ret = NULL;
583 583 kmem_free(dma, sizeof (nvme_dma_t));
584 584 return (DDI_FAILURE);
585 585 }
586 586
587 587 bzero(dma->nd_memp, dma->nd_len);
588 588
589 589 *ret = dma;
590 590 return (DDI_SUCCESS);
591 591 }
592 592
593 593 /* ARGSUSED */
594 594 static int
595 595 nvme_prp_dma_constructor(void *buf, void *private, int flags)
596 596 {
597 597 nvme_dma_t *dma = (nvme_dma_t *)buf;
598 598 nvme_t *nvme = (nvme_t *)private;
599 599
600 600 dma->nd_dmah = NULL;
601 601 dma->nd_acch = NULL;
602 602
603 603 if (nvme_alloc_dma_common(nvme, dma, nvme->n_pagesize,
604 604 DDI_DMA_READ, &nvme->n_prp_dma_attr) != DDI_SUCCESS) {
605 605 return (-1);
606 606 }
607 607
608 608 ASSERT(dma->nd_ncookie == 1);
609 609
610 610 dma->nd_cached = B_TRUE;
611 611
612 612 return (0);
613 613 }
614 614
615 615 static int
616 616 nvme_zalloc_queue_dma(nvme_t *nvme, uint32_t nentry, uint16_t qe_len,
617 617 uint_t flags, nvme_dma_t **dma)
618 618 {
619 619 uint32_t len = nentry * qe_len;
620 620 ddi_dma_attr_t q_dma_attr = nvme->n_queue_dma_attr;
621 621
622 622 len = roundup(len, nvme->n_pagesize);
623 623
624 624 q_dma_attr.dma_attr_minxfer = len;
625 625
626 626 if (nvme_zalloc_dma(nvme, len, flags, &q_dma_attr, dma)
627 627 != DDI_SUCCESS) {
628 628 dev_err(nvme->n_dip, CE_WARN,
629 629 "!failed to get DMA memory for queue");
630 630 goto fail;
631 631 }
632 632
633 633 if ((*dma)->nd_ncookie != 1) {
634 634 dev_err(nvme->n_dip, CE_WARN,
635 635 "!got too many cookies for queue DMA");
636 636 goto fail;
637 637 }
638 638
639 639 return (DDI_SUCCESS);
640 640
641 641 fail:
642 642 if (*dma) {
643 643 nvme_free_dma(*dma);
644 644 *dma = NULL;
645 645 }
646 646
647 647 return (DDI_FAILURE);
648 648 }
649 649
650 650 static void
651 651 nvme_free_qpair(nvme_qpair_t *qp)
652 652 {
653 653 int i;
654 654
655 655 mutex_destroy(&qp->nq_mutex);
656 656
657 657 if (qp->nq_sqdma != NULL)
658 658 nvme_free_dma(qp->nq_sqdma);
659 659 if (qp->nq_cqdma != NULL)
660 660 nvme_free_dma(qp->nq_cqdma);
661 661
662 662 if (qp->nq_active_cmds > 0)
663 663 for (i = 0; i != qp->nq_nentry; i++)
664 664 if (qp->nq_cmd[i] != NULL)
665 665 nvme_free_cmd(qp->nq_cmd[i]);
666 666
667 667 if (qp->nq_cmd != NULL)
668 668 kmem_free(qp->nq_cmd, sizeof (nvme_cmd_t *) * qp->nq_nentry);
669 669
670 670 kmem_free(qp, sizeof (nvme_qpair_t));
671 671 }
672 672
673 673 static int
674 674 nvme_alloc_qpair(nvme_t *nvme, uint32_t nentry, nvme_qpair_t **nqp,
675 675 int idx)
676 676 {
677 677 nvme_qpair_t *qp = kmem_zalloc(sizeof (*qp), KM_SLEEP);
678 678
679 679 mutex_init(&qp->nq_mutex, NULL, MUTEX_DRIVER,
680 680 DDI_INTR_PRI(nvme->n_intr_pri));
681 681
682 682 if (nvme_zalloc_queue_dma(nvme, nentry, sizeof (nvme_sqe_t),
683 683 DDI_DMA_WRITE, &qp->nq_sqdma) != DDI_SUCCESS)
684 684 goto fail;
685 685
686 686 if (nvme_zalloc_queue_dma(nvme, nentry, sizeof (nvme_cqe_t),
687 687 DDI_DMA_READ, &qp->nq_cqdma) != DDI_SUCCESS)
688 688 goto fail;
689 689
690 690 qp->nq_sq = (nvme_sqe_t *)qp->nq_sqdma->nd_memp;
691 691 qp->nq_cq = (nvme_cqe_t *)qp->nq_cqdma->nd_memp;
692 692 qp->nq_nentry = nentry;
693 693
694 694 qp->nq_sqtdbl = NVME_REG_SQTDBL(nvme, idx);
695 695 qp->nq_cqhdbl = NVME_REG_CQHDBL(nvme, idx);
696 696
697 697 qp->nq_cmd = kmem_zalloc(sizeof (nvme_cmd_t *) * nentry, KM_SLEEP);
698 698 qp->nq_next_cmd = 0;
699 699
700 700 *nqp = qp;
701 701 return (DDI_SUCCESS);
702 702
703 703 fail:
704 704 nvme_free_qpair(qp);
705 705 *nqp = NULL;
706 706
707 707 return (DDI_FAILURE);
708 708 }
709 709
710 710 static nvme_cmd_t *
711 711 nvme_alloc_cmd(nvme_t *nvme, int kmflag)
712 712 {
713 713 nvme_cmd_t *cmd = kmem_cache_alloc(nvme_cmd_cache, kmflag);
714 714
715 715 if (cmd == NULL)
716 716 return (cmd);
717 717
718 718 bzero(cmd, sizeof (nvme_cmd_t));
719 719
720 720 cmd->nc_nvme = nvme;
721 721
722 722 mutex_init(&cmd->nc_mutex, NULL, MUTEX_DRIVER,
723 723 DDI_INTR_PRI(nvme->n_intr_pri));
724 724 cv_init(&cmd->nc_cv, NULL, CV_DRIVER, NULL);
725 725
726 726 return (cmd);
727 727 }
728 728
729 729 static void
730 730 nvme_free_cmd(nvme_cmd_t *cmd)
731 731 {
732 732 if (cmd->nc_dma) {
733 733 if (cmd->nc_dma->nd_cached)
734 734 kmem_cache_free(cmd->nc_nvme->n_prp_cache,
735 735 cmd->nc_dma);
736 736 else
737 737 nvme_free_dma(cmd->nc_dma);
738 738 cmd->nc_dma = NULL;
739 739 }
740 740
741 741 cv_destroy(&cmd->nc_cv);
742 742 mutex_destroy(&cmd->nc_mutex);
743 743
744 744 kmem_cache_free(nvme_cmd_cache, cmd);
745 745 }
746 746
747 747 static int
748 748 nvme_submit_cmd(nvme_qpair_t *qp, nvme_cmd_t *cmd)
749 749 {
750 750 nvme_reg_sqtdbl_t tail = { 0 };
751 751
752 752 mutex_enter(&qp->nq_mutex);
753 753
754 754 if (qp->nq_active_cmds == qp->nq_nentry) {
755 755 mutex_exit(&qp->nq_mutex);
756 756 return (DDI_FAILURE);
757 757 }
758 758
759 759 cmd->nc_completed = B_FALSE;
760 760
761 761 /*
762 762 * Try to insert the cmd into the active cmd array at the nq_next_cmd
763 763 * slot. If the slot is already occupied advance to the next slot and
764 764 * try again. This can happen for long running commands like async event
765 765 * requests.
766 766 */
767 767 while (qp->nq_cmd[qp->nq_next_cmd] != NULL)
768 768 qp->nq_next_cmd = (qp->nq_next_cmd + 1) % qp->nq_nentry;
769 769 qp->nq_cmd[qp->nq_next_cmd] = cmd;
770 770
771 771 qp->nq_active_cmds++;
772 772
773 773 cmd->nc_sqe.sqe_cid = qp->nq_next_cmd;
774 774 bcopy(&cmd->nc_sqe, &qp->nq_sq[qp->nq_sqtail], sizeof (nvme_sqe_t));
775 775 (void) ddi_dma_sync(qp->nq_sqdma->nd_dmah,
776 776 sizeof (nvme_sqe_t) * qp->nq_sqtail,
777 777 sizeof (nvme_sqe_t), DDI_DMA_SYNC_FORDEV);
778 778 qp->nq_next_cmd = (qp->nq_next_cmd + 1) % qp->nq_nentry;
779 779
780 780 tail.b.sqtdbl_sqt = qp->nq_sqtail = (qp->nq_sqtail + 1) % qp->nq_nentry;
781 781 nvme_put32(cmd->nc_nvme, qp->nq_sqtdbl, tail.r);
782 782
783 783 mutex_exit(&qp->nq_mutex);
784 784 return (DDI_SUCCESS);
785 785 }
786 786
787 787 static nvme_cmd_t *
788 788 nvme_retrieve_cmd(nvme_t *nvme, nvme_qpair_t *qp)
789 789 {
790 790 nvme_reg_cqhdbl_t head = { 0 };
791 791
792 792 nvme_cqe_t *cqe;
793 793 nvme_cmd_t *cmd;
794 794
795 795 (void) ddi_dma_sync(qp->nq_cqdma->nd_dmah, 0,
796 796 sizeof (nvme_cqe_t) * qp->nq_nentry, DDI_DMA_SYNC_FORKERNEL);
797 797
798 798 cqe = &qp->nq_cq[qp->nq_cqhead];
799 799
800 800 /* Check phase tag of CQE. Hardware inverts it for new entries. */
801 801 if (cqe->cqe_sf.sf_p == qp->nq_phase)
802 802 return (NULL);
803 803
804 804 ASSERT(nvme->n_ioq[cqe->cqe_sqid] == qp);
805 805 ASSERT(cqe->cqe_cid < qp->nq_nentry);
806 806
807 807 mutex_enter(&qp->nq_mutex);
808 808 cmd = qp->nq_cmd[cqe->cqe_cid];
809 809 qp->nq_cmd[cqe->cqe_cid] = NULL;
810 810 qp->nq_active_cmds--;
811 811 mutex_exit(&qp->nq_mutex);
812 812
813 813 ASSERT(cmd != NULL);
814 814 ASSERT(cmd->nc_nvme == nvme);
815 815 ASSERT(cmd->nc_sqid == cqe->cqe_sqid);
816 816 ASSERT(cmd->nc_sqe.sqe_cid == cqe->cqe_cid);
817 817 bcopy(cqe, &cmd->nc_cqe, sizeof (nvme_cqe_t));
818 818
819 819 qp->nq_sqhead = cqe->cqe_sqhd;
820 820
821 821 head.b.cqhdbl_cqh = qp->nq_cqhead = (qp->nq_cqhead + 1) % qp->nq_nentry;
822 822
823 823 /* Toggle phase on wrap-around. */
824 824 if (qp->nq_cqhead == 0)
825 825 qp->nq_phase = qp->nq_phase ? 0 : 1;
826 826
827 827 nvme_put32(cmd->nc_nvme, qp->nq_cqhdbl, head.r);
828 828
829 829 return (cmd);
830 830 }
831 831
832 832 static int
833 833 nvme_check_unknown_cmd_status(nvme_cmd_t *cmd)
834 834 {
835 835 nvme_cqe_t *cqe = &cmd->nc_cqe;
836 836
837 837 dev_err(cmd->nc_nvme->n_dip, CE_WARN,
838 838 "!unknown command status received: opc = %x, sqid = %d, cid = %d, "
839 839 "sc = %x, sct = %x, dnr = %d, m = %d", cmd->nc_sqe.sqe_opc,
840 840 cqe->cqe_sqid, cqe->cqe_cid, cqe->cqe_sf.sf_sc, cqe->cqe_sf.sf_sct,
841 841 cqe->cqe_sf.sf_dnr, cqe->cqe_sf.sf_m);
842 842
843 843 bd_error(cmd->nc_xfer, BD_ERR_ILLRQ);
844 844
845 845 if (cmd->nc_nvme->n_strict_version) {
846 846 cmd->nc_nvme->n_dead = B_TRUE;
847 847 ddi_fm_service_impact(cmd->nc_nvme->n_dip, DDI_SERVICE_LOST);
848 848 }
849 849
850 850 return (EIO);
851 851 }
852 852
853 853 static int
854 854 nvme_check_vendor_cmd_status(nvme_cmd_t *cmd)
855 855 {
856 856 nvme_cqe_t *cqe = &cmd->nc_cqe;
857 857
858 858 dev_err(cmd->nc_nvme->n_dip, CE_WARN,
859 859 "!unknown command status received: opc = %x, sqid = %d, cid = %d, "
860 860 "sc = %x, sct = %x, dnr = %d, m = %d", cmd->nc_sqe.sqe_opc,
861 861 cqe->cqe_sqid, cqe->cqe_cid, cqe->cqe_sf.sf_sc, cqe->cqe_sf.sf_sct,
862 862 cqe->cqe_sf.sf_dnr, cqe->cqe_sf.sf_m);
863 863 if (!cmd->nc_nvme->n_ignore_unknown_vendor_status) {
864 864 cmd->nc_nvme->n_dead = B_TRUE;
865 865 ddi_fm_service_impact(cmd->nc_nvme->n_dip, DDI_SERVICE_LOST);
866 866 }
867 867
868 868 return (EIO);
869 869 }
870 870
871 871 static int
872 872 nvme_check_integrity_cmd_status(nvme_cmd_t *cmd)
873 873 {
874 874 nvme_cqe_t *cqe = &cmd->nc_cqe;
875 875
876 876 switch (cqe->cqe_sf.sf_sc) {
877 877 case NVME_CQE_SC_INT_NVM_WRITE:
878 878 /* write fail */
879 879 /* TODO: post ereport */
880 880 bd_error(cmd->nc_xfer, BD_ERR_MEDIA);
881 881 return (EIO);
882 882
883 883 case NVME_CQE_SC_INT_NVM_READ:
884 884 /* read fail */
885 885 /* TODO: post ereport */
886 886 bd_error(cmd->nc_xfer, BD_ERR_MEDIA);
887 887 return (EIO);
888 888
889 889 default:
890 890 return (nvme_check_unknown_cmd_status(cmd));
891 891 }
892 892 }
893 893
894 894 static int
895 895 nvme_check_generic_cmd_status(nvme_cmd_t *cmd)
896 896 {
897 897 nvme_cqe_t *cqe = &cmd->nc_cqe;
898 898
899 899 switch (cqe->cqe_sf.sf_sc) {
900 900 case NVME_CQE_SC_GEN_SUCCESS:
901 901 return (0);
902 902
903 903 /*
904 904 * Errors indicating a bug in the driver should cause a panic.
905 905 */
906 906 case NVME_CQE_SC_GEN_INV_OPC:
907 907 /* Invalid Command Opcode */
908 908 dev_err(cmd->nc_nvme->n_dip, CE_PANIC, "programming error: "
909 909 "invalid opcode in cmd %p", (void *)cmd);
910 910 return (0);
911 911
912 912 case NVME_CQE_SC_GEN_INV_FLD:
913 913 /* Invalid Field in Command */
914 914 dev_err(cmd->nc_nvme->n_dip, CE_PANIC, "programming error: "
915 915 "invalid field in cmd %p", (void *)cmd);
916 916 return (0);
917 917
918 918 case NVME_CQE_SC_GEN_ID_CNFL:
919 919 /* Command ID Conflict */
920 920 dev_err(cmd->nc_nvme->n_dip, CE_PANIC, "programming error: "
921 921 "cmd ID conflict in cmd %p", (void *)cmd);
922 922 return (0);
923 923
924 924 case NVME_CQE_SC_GEN_INV_NS:
925 925 /* Invalid Namespace or Format */
926 926 dev_err(cmd->nc_nvme->n_dip, CE_PANIC, "programming error: "
927 927 "invalid NS/format in cmd %p", (void *)cmd);
928 928 return (0);
929 929
930 930 case NVME_CQE_SC_GEN_NVM_LBA_RANGE:
931 931 /* LBA Out Of Range */
932 932 dev_err(cmd->nc_nvme->n_dip, CE_PANIC, "programming error: "
933 933 "LBA out of range in cmd %p", (void *)cmd);
934 934 return (0);
935 935
936 936 /*
937 937 * Non-fatal errors, handle gracefully.
938 938 */
939 939 case NVME_CQE_SC_GEN_DATA_XFR_ERR:
940 940 /* Data Transfer Error (DMA) */
941 941 /* TODO: post ereport */
942 942 atomic_inc_32(&cmd->nc_nvme->n_data_xfr_err);
943 943 bd_error(cmd->nc_xfer, BD_ERR_NTRDY);
944 944 return (EIO);
945 945
946 946 case NVME_CQE_SC_GEN_INTERNAL_ERR:
947 947 /*
948 948 * Internal Error. The spec (v1.0, section 4.5.1.2) says
949 949 * detailed error information is returned as async event,
950 950 * so we pretty much ignore the error here and handle it
951 951 * in the async event handler.
952 952 */
953 953 atomic_inc_32(&cmd->nc_nvme->n_internal_err);
954 954 bd_error(cmd->nc_xfer, BD_ERR_NTRDY);
955 955 return (EIO);
956 956
957 957 case NVME_CQE_SC_GEN_ABORT_REQUEST:
958 958 /*
959 959 * Command Abort Requested. This normally happens only when a
960 960 * command times out.
961 961 */
962 962 /* TODO: post ereport or change blkdev to handle this? */
963 963 atomic_inc_32(&cmd->nc_nvme->n_abort_rq_err);
964 964 return (ECANCELED);
965 965
966 966 case NVME_CQE_SC_GEN_ABORT_PWRLOSS:
967 967 /* Command Aborted due to Power Loss Notification */
968 968 ddi_fm_service_impact(cmd->nc_nvme->n_dip, DDI_SERVICE_LOST);
969 969 cmd->nc_nvme->n_dead = B_TRUE;
970 970 return (EIO);
971 971
972 972 case NVME_CQE_SC_GEN_ABORT_SQ_DEL:
973 973 /* Command Aborted due to SQ Deletion */
974 974 atomic_inc_32(&cmd->nc_nvme->n_abort_sq_del);
975 975 return (EIO);
976 976
977 977 case NVME_CQE_SC_GEN_NVM_CAP_EXC:
978 978 /* Capacity Exceeded */
979 979 atomic_inc_32(&cmd->nc_nvme->n_nvm_cap_exc);
980 980 bd_error(cmd->nc_xfer, BD_ERR_MEDIA);
981 981 return (EIO);
982 982
983 983 case NVME_CQE_SC_GEN_NVM_NS_NOTRDY:
984 984 /* Namespace Not Ready */
985 985 atomic_inc_32(&cmd->nc_nvme->n_nvm_ns_notrdy);
986 986 bd_error(cmd->nc_xfer, BD_ERR_NTRDY);
987 987 return (EIO);
988 988
989 989 default:
990 990 return (nvme_check_unknown_cmd_status(cmd));
991 991 }
992 992 }
993 993
994 994 static int
995 995 nvme_check_specific_cmd_status(nvme_cmd_t *cmd)
996 996 {
997 997 nvme_cqe_t *cqe = &cmd->nc_cqe;
998 998
999 999 switch (cqe->cqe_sf.sf_sc) {
1000 1000 case NVME_CQE_SC_SPC_INV_CQ:
1001 1001 /* Completion Queue Invalid */
1002 1002 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_CREATE_SQUEUE);
1003 1003 atomic_inc_32(&cmd->nc_nvme->n_inv_cq_err);
1004 1004 return (EINVAL);
1005 1005
1006 1006 case NVME_CQE_SC_SPC_INV_QID:
1007 1007 /* Invalid Queue Identifier */
1008 1008 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_CREATE_SQUEUE ||
1009 1009 cmd->nc_sqe.sqe_opc == NVME_OPC_DELETE_SQUEUE ||
1010 1010 cmd->nc_sqe.sqe_opc == NVME_OPC_CREATE_CQUEUE ||
1011 1011 cmd->nc_sqe.sqe_opc == NVME_OPC_DELETE_CQUEUE);
1012 1012 atomic_inc_32(&cmd->nc_nvme->n_inv_qid_err);
1013 1013 return (EINVAL);
1014 1014
1015 1015 case NVME_CQE_SC_SPC_MAX_QSZ_EXC:
1016 1016 /* Max Queue Size Exceeded */
1017 1017 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_CREATE_SQUEUE ||
1018 1018 cmd->nc_sqe.sqe_opc == NVME_OPC_CREATE_CQUEUE);
1019 1019 atomic_inc_32(&cmd->nc_nvme->n_max_qsz_exc);
1020 1020 return (EINVAL);
1021 1021
1022 1022 case NVME_CQE_SC_SPC_ABRT_CMD_EXC:
1023 1023 /* Abort Command Limit Exceeded */
1024 1024 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_ABORT);
1025 1025 dev_err(cmd->nc_nvme->n_dip, CE_PANIC, "programming error: "
1026 1026 "abort command limit exceeded in cmd %p", (void *)cmd);
1027 1027 return (0);
1028 1028
1029 1029 case NVME_CQE_SC_SPC_ASYNC_EVREQ_EXC:
1030 1030 /* Async Event Request Limit Exceeded */
1031 1031 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_ASYNC_EVENT);
1032 1032 dev_err(cmd->nc_nvme->n_dip, CE_PANIC, "programming error: "
1033 1033 "async event request limit exceeded in cmd %p",
1034 1034 (void *)cmd);
1035 1035 return (0);
1036 1036
1037 1037 case NVME_CQE_SC_SPC_INV_INT_VECT:
1038 1038 /* Invalid Interrupt Vector */
1039 1039 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_CREATE_CQUEUE);
1040 1040 atomic_inc_32(&cmd->nc_nvme->n_inv_int_vect);
1041 1041 return (EINVAL);
1042 1042
1043 1043 case NVME_CQE_SC_SPC_INV_LOG_PAGE:
1044 1044 /* Invalid Log Page */
1045 1045 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_GET_LOG_PAGE);
1046 1046 atomic_inc_32(&cmd->nc_nvme->n_inv_log_page);
1047 1047 bd_error(cmd->nc_xfer, BD_ERR_ILLRQ);
1048 1048 return (EINVAL);
1049 1049
1050 1050 case NVME_CQE_SC_SPC_INV_FORMAT:
1051 1051 /* Invalid Format */
1052 1052 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_NVM_FORMAT);
1053 1053 atomic_inc_32(&cmd->nc_nvme->n_inv_format);
1054 1054 bd_error(cmd->nc_xfer, BD_ERR_ILLRQ);
1055 1055 return (EINVAL);
1056 1056
1057 1057 case NVME_CQE_SC_SPC_INV_Q_DEL:
1058 1058 /* Invalid Queue Deletion */
1059 1059 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_DELETE_CQUEUE);
1060 1060 atomic_inc_32(&cmd->nc_nvme->n_inv_q_del);
1061 1061 return (EINVAL);
1062 1062
1063 1063 case NVME_CQE_SC_SPC_NVM_CNFL_ATTR:
1064 1064 /* Conflicting Attributes */
1065 1065 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_NVM_DSET_MGMT ||
1066 1066 cmd->nc_sqe.sqe_opc == NVME_OPC_NVM_READ ||
1067 1067 cmd->nc_sqe.sqe_opc == NVME_OPC_NVM_WRITE);
1068 1068 atomic_inc_32(&cmd->nc_nvme->n_cnfl_attr);
1069 1069 bd_error(cmd->nc_xfer, BD_ERR_ILLRQ);
1070 1070 return (EINVAL);
1071 1071
1072 1072 case NVME_CQE_SC_SPC_NVM_INV_PROT:
1073 1073 /* Invalid Protection Information */
1074 1074 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_NVM_COMPARE ||
1075 1075 cmd->nc_sqe.sqe_opc == NVME_OPC_NVM_READ ||
1076 1076 cmd->nc_sqe.sqe_opc == NVME_OPC_NVM_WRITE);
1077 1077 atomic_inc_32(&cmd->nc_nvme->n_inv_prot);
1078 1078 bd_error(cmd->nc_xfer, BD_ERR_ILLRQ);
1079 1079 return (EINVAL);
1080 1080
1081 1081 case NVME_CQE_SC_SPC_NVM_READONLY:
1082 1082 /* Write to Read Only Range */
1083 1083 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_NVM_WRITE);
1084 1084 atomic_inc_32(&cmd->nc_nvme->n_readonly);
1085 1085 bd_error(cmd->nc_xfer, BD_ERR_ILLRQ);
1086 1086 return (EROFS);
1087 1087
1088 1088 default:
1089 1089 return (nvme_check_unknown_cmd_status(cmd));
1090 1090 }
1091 1091 }
1092 1092
1093 1093 static inline int
1094 1094 nvme_check_cmd_status(nvme_cmd_t *cmd)
1095 1095 {
1096 1096 nvme_cqe_t *cqe = &cmd->nc_cqe;
1097 1097
1098 1098 /* take a shortcut if everything is alright */
1099 1099 if (cqe->cqe_sf.sf_sct == NVME_CQE_SCT_GENERIC &&
1100 1100 cqe->cqe_sf.sf_sc == NVME_CQE_SC_GEN_SUCCESS)
1101 1101 return (0);
1102 1102
1103 1103 if (cqe->cqe_sf.sf_sct == NVME_CQE_SCT_GENERIC)
1104 1104 return (nvme_check_generic_cmd_status(cmd));
1105 1105 else if (cqe->cqe_sf.sf_sct == NVME_CQE_SCT_SPECIFIC)
1106 1106 return (nvme_check_specific_cmd_status(cmd));
1107 1107 else if (cqe->cqe_sf.sf_sct == NVME_CQE_SCT_INTEGRITY)
1108 1108 return (nvme_check_integrity_cmd_status(cmd));
1109 1109 else if (cqe->cqe_sf.sf_sct == NVME_CQE_SCT_VENDOR)
1110 1110 return (nvme_check_vendor_cmd_status(cmd));
1111 1111
1112 1112 return (nvme_check_unknown_cmd_status(cmd));
1113 1113 }
1114 1114
1115 1115 /*
1116 1116 * nvme_abort_cmd_cb -- replaces nc_callback of aborted commands
1117 1117 *
1118 1118 * This functions takes care of cleaning up aborted commands. The command
1119 1119 * status is checked to catch any fatal errors.
1120 1120 */
1121 1121 static void
1122 1122 nvme_abort_cmd_cb(void *arg)
1123 1123 {
1124 1124 nvme_cmd_t *cmd = arg;
1125 1125
1126 1126 /*
1127 1127 * Grab the command mutex. Once we have it we hold the last reference
1128 1128 * to the command and can safely free it.
1129 1129 */
1130 1130 mutex_enter(&cmd->nc_mutex);
1131 1131 (void) nvme_check_cmd_status(cmd);
1132 1132 mutex_exit(&cmd->nc_mutex);
1133 1133
1134 1134 nvme_free_cmd(cmd);
1135 1135 }
1136 1136
1137 1137 static void
1138 1138 nvme_abort_cmd(nvme_cmd_t *abort_cmd)
1139 1139 {
1140 1140 nvme_t *nvme = abort_cmd->nc_nvme;
1141 1141 nvme_cmd_t *cmd = nvme_alloc_cmd(nvme, KM_SLEEP);
1142 1142 nvme_abort_cmd_t ac = { 0 };
1143 1143
1144 1144 sema_p(&nvme->n_abort_sema);
1145 1145
1146 1146 ac.b.ac_cid = abort_cmd->nc_sqe.sqe_cid;
1147 1147 ac.b.ac_sqid = abort_cmd->nc_sqid;
1148 1148
1149 1149 /*
1150 1150 * Drop the mutex of the aborted command. From this point on
1151 1151 * we must assume that the abort callback has freed the command.
1152 1152 */
1153 1153 mutex_exit(&abort_cmd->nc_mutex);
1154 1154
1155 1155 cmd->nc_sqid = 0;
1156 1156 cmd->nc_sqe.sqe_opc = NVME_OPC_ABORT;
1157 1157 cmd->nc_callback = nvme_wakeup_cmd;
1158 1158 cmd->nc_sqe.sqe_cdw10 = ac.r;
1159 1159
1160 1160 /*
1161 1161 * Send the ABORT to the hardware. The ABORT command will return _after_
1162 1162 * the aborted command has completed (aborted or otherwise).
1163 1163 */
1164 1164 if (nvme_admin_cmd(cmd, nvme_admin_cmd_timeout) != DDI_SUCCESS) {
1165 1165 sema_v(&nvme->n_abort_sema);
1166 1166 dev_err(nvme->n_dip, CE_WARN,
1167 1167 "!nvme_admin_cmd failed for ABORT");
1168 1168 atomic_inc_32(&nvme->n_abort_failed);
1169 1169 return;
1170 1170 }
1171 1171 sema_v(&nvme->n_abort_sema);
1172 1172
1173 1173 if (nvme_check_cmd_status(cmd)) {
1174 1174 dev_err(nvme->n_dip, CE_WARN,
1175 1175 "!ABORT failed with sct = %x, sc = %x",
1176 1176 cmd->nc_cqe.cqe_sf.sf_sct, cmd->nc_cqe.cqe_sf.sf_sc);
1177 1177 atomic_inc_32(&nvme->n_abort_failed);
1178 1178 } else {
1179 1179 atomic_inc_32(&nvme->n_cmd_aborted);
1180 1180 }
1181 1181
1182 1182 nvme_free_cmd(cmd);
1183 1183 }
1184 1184
1185 1185 /*
1186 1186 * nvme_wait_cmd -- wait for command completion or timeout
1187 1187 *
1188 1188 * Returns B_TRUE if the command completed normally.
1189 1189 *
1190 1190 * Returns B_FALSE if the command timed out and an abort was attempted. The
1191 1191 * command mutex will be dropped and the command must be considered freed. The
1192 1192 * freeing of the command is normally done by the abort command callback.
1193 1193 *
1194 1194 * In case of a serious error or a timeout of the abort command the hardware
1195 1195 * will be declared dead and FMA will be notified.
1196 1196 */
1197 1197 static boolean_t
1198 1198 nvme_wait_cmd(nvme_cmd_t *cmd, uint_t sec)
1199 1199 {
1200 1200 clock_t timeout = ddi_get_lbolt() + drv_usectohz(sec * MICROSEC);
1201 1201 nvme_t *nvme = cmd->nc_nvme;
1202 1202 nvme_reg_csts_t csts;
1203 1203
1204 1204 ASSERT(mutex_owned(&cmd->nc_mutex));
1205 1205
1206 1206 while (!cmd->nc_completed) {
1207 1207 if (cv_timedwait(&cmd->nc_cv, &cmd->nc_mutex, timeout) == -1)
1208 1208 break;
1209 1209 }
1210 1210
1211 1211 if (cmd->nc_completed)
1212 1212 return (B_TRUE);
1213 1213
1214 1214 /*
1215 1215 * The command timed out. Change the callback to the cleanup function.
1216 1216 */
1217 1217 cmd->nc_callback = nvme_abort_cmd_cb;
1218 1218
1219 1219 /*
1220 1220 * Check controller for fatal status, any errors associated with the
1221 1221 * register or DMA handle, or for a double timeout (abort command timed
1222 1222 * out). If necessary log a warning and call FMA.
1223 1223 */
1224 1224 csts.r = nvme_get32(nvme, NVME_REG_CSTS);
1225 1225 dev_err(nvme->n_dip, CE_WARN, "!command timeout, "
1226 1226 "OPC = %x, CFS = %d", cmd->nc_sqe.sqe_opc, csts.b.csts_cfs);
1227 1227 atomic_inc_32(&nvme->n_cmd_timeout);
1228 1228
1229 1229 if (csts.b.csts_cfs ||
1230 1230 nvme_check_regs_hdl(nvme) ||
1231 1231 nvme_check_dma_hdl(cmd->nc_dma) ||
1232 1232 cmd->nc_sqe.sqe_opc == NVME_OPC_ABORT) {
1233 1233 ddi_fm_service_impact(nvme->n_dip, DDI_SERVICE_LOST);
1234 1234 nvme->n_dead = B_TRUE;
1235 1235 mutex_exit(&cmd->nc_mutex);
1236 1236 } else {
1237 1237 /*
1238 1238 * Try to abort the command. The command mutex is released by
1239 1239 * nvme_abort_cmd().
1240 1240 * If the abort succeeds it will have freed the aborted command.
1241 1241 * If the abort fails for other reasons we must assume that the
1242 1242 * command may complete at any time, and the callback will free
1243 1243 * it for us.
1244 1244 */
1245 1245 nvme_abort_cmd(cmd);
1246 1246 }
1247 1247
1248 1248 return (B_FALSE);
1249 1249 }
1250 1250
1251 1251 static void
1252 1252 nvme_wakeup_cmd(void *arg)
1253 1253 {
1254 1254 nvme_cmd_t *cmd = arg;
1255 1255
1256 1256 mutex_enter(&cmd->nc_mutex);
1257 1257 /*
1258 1258 * There is a slight chance that this command completed shortly after
1259 1259 * the timeout was hit in nvme_wait_cmd() but before the callback was
1260 1260 * changed. Catch that case here and clean up accordingly.
1261 1261 */
1262 1262 if (cmd->nc_callback == nvme_abort_cmd_cb) {
1263 1263 mutex_exit(&cmd->nc_mutex);
1264 1264 nvme_abort_cmd_cb(cmd);
1265 1265 return;
1266 1266 }
1267 1267
1268 1268 cmd->nc_completed = B_TRUE;
1269 1269 cv_signal(&cmd->nc_cv);
1270 1270 mutex_exit(&cmd->nc_mutex);
1271 1271 }
1272 1272
1273 1273 static void
1274 1274 nvme_async_event_task(void *arg)
1275 1275 {
1276 1276 nvme_cmd_t *cmd = arg;
1277 1277 nvme_t *nvme = cmd->nc_nvme;
1278 1278 nvme_error_log_entry_t *error_log = NULL;
1279 1279 nvme_health_log_t *health_log = NULL;
1280 1280 nvme_async_event_t event;
1281 1281 int ret;
1282 1282
1283 1283 /*
1284 1284 * Check for errors associated with the async request itself. The only
1285 1285 * command-specific error is "async event limit exceeded", which
1286 1286 * indicates a programming error in the driver and causes a panic in
1287 1287 * nvme_check_cmd_status().
1288 1288 *
1289 1289 * Other possible errors are various scenarios where the async request
1290 1290 * was aborted, or internal errors in the device. Internal errors are
1291 1291 * reported to FMA, the command aborts need no special handling here.
1292 1292 */
1293 1293 if (nvme_check_cmd_status(cmd)) {
1294 1294 dev_err(cmd->nc_nvme->n_dip, CE_WARN,
1295 1295 "!async event request returned failure, sct = %x, "
1296 1296 "sc = %x, dnr = %d, m = %d", cmd->nc_cqe.cqe_sf.sf_sct,
1297 1297 cmd->nc_cqe.cqe_sf.sf_sc, cmd->nc_cqe.cqe_sf.sf_dnr,
1298 1298 cmd->nc_cqe.cqe_sf.sf_m);
1299 1299
1300 1300 if (cmd->nc_cqe.cqe_sf.sf_sct == NVME_CQE_SCT_GENERIC &&
1301 1301 cmd->nc_cqe.cqe_sf.sf_sc == NVME_CQE_SC_GEN_INTERNAL_ERR) {
1302 1302 cmd->nc_nvme->n_dead = B_TRUE;
1303 1303 ddi_fm_service_impact(cmd->nc_nvme->n_dip,
1304 1304 DDI_SERVICE_LOST);
1305 1305 }
1306 1306 nvme_free_cmd(cmd);
1307 1307 return;
1308 1308 }
1309 1309
1310 1310
1311 1311 event.r = cmd->nc_cqe.cqe_dw0;
1312 1312
1313 1313 /* Clear CQE and re-submit the async request. */
1314 1314 bzero(&cmd->nc_cqe, sizeof (nvme_cqe_t));
1315 1315 ret = nvme_submit_cmd(nvme->n_adminq, cmd);
1316 1316
1317 1317 if (ret != DDI_SUCCESS) {
1318 1318 dev_err(nvme->n_dip, CE_WARN,
1319 1319 "!failed to resubmit async event request");
1320 1320 atomic_inc_32(&nvme->n_async_resubmit_failed);
1321 1321 nvme_free_cmd(cmd);
1322 1322 }
1323 1323
1324 1324 switch (event.b.ae_type) {
1325 1325 case NVME_ASYNC_TYPE_ERROR:
1326 1326 if (event.b.ae_logpage == NVME_LOGPAGE_ERROR) {
1327 1327 error_log = (nvme_error_log_entry_t *)
1328 1328 nvme_get_logpage(nvme, event.b.ae_logpage);
1329 1329 } else {
1330 1330 dev_err(nvme->n_dip, CE_WARN, "!wrong logpage in "
1331 1331 "async event reply: %d", event.b.ae_logpage);
1332 1332 atomic_inc_32(&nvme->n_wrong_logpage);
1333 1333 }
1334 1334
1335 1335 switch (event.b.ae_info) {
1336 1336 case NVME_ASYNC_ERROR_INV_SQ:
1337 1337 dev_err(nvme->n_dip, CE_PANIC, "programming error: "
1338 1338 "invalid submission queue");
1339 1339 return;
1340 1340
1341 1341 case NVME_ASYNC_ERROR_INV_DBL:
1342 1342 dev_err(nvme->n_dip, CE_PANIC, "programming error: "
1343 1343 "invalid doorbell write value");
1344 1344 return;
1345 1345
1346 1346 case NVME_ASYNC_ERROR_DIAGFAIL:
1347 1347 dev_err(nvme->n_dip, CE_WARN, "!diagnostic failure");
1348 1348 ddi_fm_service_impact(nvme->n_dip, DDI_SERVICE_LOST);
1349 1349 nvme->n_dead = B_TRUE;
1350 1350 atomic_inc_32(&nvme->n_diagfail_event);
1351 1351 break;
1352 1352
1353 1353 case NVME_ASYNC_ERROR_PERSISTENT:
1354 1354 dev_err(nvme->n_dip, CE_WARN, "!persistent internal "
1355 1355 "device error");
1356 1356 ddi_fm_service_impact(nvme->n_dip, DDI_SERVICE_LOST);
1357 1357 nvme->n_dead = B_TRUE;
1358 1358 atomic_inc_32(&nvme->n_persistent_event);
1359 1359 break;
1360 1360
1361 1361 case NVME_ASYNC_ERROR_TRANSIENT:
1362 1362 dev_err(nvme->n_dip, CE_WARN, "!transient internal "
1363 1363 "device error");
1364 1364 /* TODO: send ereport */
1365 1365 atomic_inc_32(&nvme->n_transient_event);
1366 1366 break;
1367 1367
1368 1368 case NVME_ASYNC_ERROR_FW_LOAD:
1369 1369 dev_err(nvme->n_dip, CE_WARN,
1370 1370 "!firmware image load error");
1371 1371 atomic_inc_32(&nvme->n_fw_load_event);
1372 1372 break;
1373 1373 }
1374 1374 break;
1375 1375
1376 1376 case NVME_ASYNC_TYPE_HEALTH:
1377 1377 if (event.b.ae_logpage == NVME_LOGPAGE_HEALTH) {
1378 1378 health_log = (nvme_health_log_t *)
1379 1379 nvme_get_logpage(nvme, event.b.ae_logpage, -1);
1380 1380 } else {
1381 1381 dev_err(nvme->n_dip, CE_WARN, "!wrong logpage in "
1382 1382 "async event reply: %d", event.b.ae_logpage);
1383 1383 atomic_inc_32(&nvme->n_wrong_logpage);
1384 1384 }
1385 1385
1386 1386 switch (event.b.ae_info) {
1387 1387 case NVME_ASYNC_HEALTH_RELIABILITY:
1388 1388 dev_err(nvme->n_dip, CE_WARN,
1389 1389 "!device reliability compromised");
1390 1390 /* TODO: send ereport */
1391 1391 atomic_inc_32(&nvme->n_reliability_event);
1392 1392 break;
1393 1393
1394 1394 case NVME_ASYNC_HEALTH_TEMPERATURE:
1395 1395 dev_err(nvme->n_dip, CE_WARN,
1396 1396 "!temperature above threshold");
1397 1397 /* TODO: send ereport */
1398 1398 atomic_inc_32(&nvme->n_temperature_event);
1399 1399 break;
1400 1400
1401 1401 case NVME_ASYNC_HEALTH_SPARE:
1402 1402 dev_err(nvme->n_dip, CE_WARN,
1403 1403 "!spare space below threshold");
1404 1404 /* TODO: send ereport */
1405 1405 atomic_inc_32(&nvme->n_spare_event);
1406 1406 break;
1407 1407 }
1408 1408 break;
1409 1409
1410 1410 case NVME_ASYNC_TYPE_VENDOR:
1411 1411 dev_err(nvme->n_dip, CE_WARN, "!vendor specific async event "
1412 1412 "received, info = %x, logpage = %x", event.b.ae_info,
1413 1413 event.b.ae_logpage);
1414 1414 atomic_inc_32(&nvme->n_vendor_event);
1415 1415 break;
1416 1416
1417 1417 default:
1418 1418 dev_err(nvme->n_dip, CE_WARN, "!unknown async event received, "
1419 1419 "type = %x, info = %x, logpage = %x", event.b.ae_type,
1420 1420 event.b.ae_info, event.b.ae_logpage);
1421 1421 atomic_inc_32(&nvme->n_unknown_event);
1422 1422 break;
1423 1423 }
1424 1424
1425 1425 if (error_log)
1426 1426 kmem_free(error_log, sizeof (nvme_error_log_entry_t) *
1427 1427 nvme->n_error_log_len);
1428 1428
1429 1429 if (health_log)
1430 1430 kmem_free(health_log, sizeof (nvme_health_log_t));
1431 1431 }
1432 1432
1433 1433 static int
1434 1434 nvme_admin_cmd(nvme_cmd_t *cmd, int sec)
1435 1435 {
1436 1436 int ret;
1437 1437
1438 1438 mutex_enter(&cmd->nc_mutex);
1439 1439 ret = nvme_submit_cmd(cmd->nc_nvme->n_adminq, cmd);
1440 1440
1441 1441 if (ret != DDI_SUCCESS) {
1442 1442 mutex_exit(&cmd->nc_mutex);
1443 1443 dev_err(cmd->nc_nvme->n_dip, CE_WARN,
1444 1444 "!nvme_submit_cmd failed");
1445 1445 atomic_inc_32(&cmd->nc_nvme->n_admin_queue_full);
1446 1446 nvme_free_cmd(cmd);
1447 1447 return (DDI_FAILURE);
1448 1448 }
1449 1449
1450 1450 if (nvme_wait_cmd(cmd, sec) == B_FALSE) {
1451 1451 /*
1452 1452 * The command timed out. An abort command was posted that
1453 1453 * will take care of the cleanup.
1454 1454 */
1455 1455 return (DDI_FAILURE);
1456 1456 }
1457 1457 mutex_exit(&cmd->nc_mutex);
1458 1458
1459 1459 return (DDI_SUCCESS);
1460 1460 }
1461 1461
1462 1462 static int
1463 1463 nvme_async_event(nvme_t *nvme)
1464 1464 {
1465 1465 nvme_cmd_t *cmd = nvme_alloc_cmd(nvme, KM_SLEEP);
1466 1466 int ret;
1467 1467
1468 1468 cmd->nc_sqid = 0;
1469 1469 cmd->nc_sqe.sqe_opc = NVME_OPC_ASYNC_EVENT;
1470 1470 cmd->nc_callback = nvme_async_event_task;
1471 1471
1472 1472 ret = nvme_submit_cmd(nvme->n_adminq, cmd);
1473 1473
1474 1474 if (ret != DDI_SUCCESS) {
1475 1475 dev_err(nvme->n_dip, CE_WARN,
1476 1476 "!nvme_submit_cmd failed for ASYNCHRONOUS EVENT");
1477 1477 nvme_free_cmd(cmd);
1478 1478 return (DDI_FAILURE);
1479 1479 }
1480 1480
1481 1481 return (DDI_SUCCESS);
1482 1482 }
1483 1483
1484 1484 static void *
1485 1485 nvme_get_logpage(nvme_t *nvme, uint8_t logpage, ...)
1486 1486 {
1487 1487 nvme_cmd_t *cmd = nvme_alloc_cmd(nvme, KM_SLEEP);
1488 1488 void *buf = NULL;
1489 1489 nvme_getlogpage_t getlogpage = { 0 };
1490 1490 size_t bufsize;
1491 1491 va_list ap;
1492 1492
1493 1493 va_start(ap, logpage);
1494 1494
1495 1495 cmd->nc_sqid = 0;
1496 1496 cmd->nc_callback = nvme_wakeup_cmd;
1497 1497 cmd->nc_sqe.sqe_opc = NVME_OPC_GET_LOG_PAGE;
1498 1498
1499 1499 getlogpage.b.lp_lid = logpage;
1500 1500
1501 1501 switch (logpage) {
1502 1502 case NVME_LOGPAGE_ERROR:
1503 1503 cmd->nc_sqe.sqe_nsid = (uint32_t)-1;
1504 1504 bufsize = nvme->n_error_log_len *
1505 1505 sizeof (nvme_error_log_entry_t);
1506 1506 break;
1507 1507
1508 1508 case NVME_LOGPAGE_HEALTH:
1509 1509 cmd->nc_sqe.sqe_nsid = va_arg(ap, uint32_t);
1510 1510 bufsize = sizeof (nvme_health_log_t);
1511 1511 break;
1512 1512
1513 1513 case NVME_LOGPAGE_FWSLOT:
1514 1514 cmd->nc_sqe.sqe_nsid = (uint32_t)-1;
1515 1515 bufsize = sizeof (nvme_fwslot_log_t);
1516 1516 break;
1517 1517
1518 1518 default:
1519 1519 dev_err(nvme->n_dip, CE_WARN, "!unknown log page requested: %d",
1520 1520 logpage);
1521 1521 atomic_inc_32(&nvme->n_unknown_logpage);
1522 1522 goto fail;
1523 1523 }
1524 1524
1525 1525 va_end(ap);
1526 1526
1527 1527 getlogpage.b.lp_numd = bufsize / sizeof (uint32_t) - 1;
1528 1528
1529 1529 cmd->nc_sqe.sqe_cdw10 = getlogpage.r;
1530 1530
1531 1531 if (nvme_zalloc_dma(nvme, getlogpage.b.lp_numd * sizeof (uint32_t),
1532 1532 DDI_DMA_READ, &nvme->n_prp_dma_attr, &cmd->nc_dma) != DDI_SUCCESS) {
1533 1533 dev_err(nvme->n_dip, CE_WARN,
1534 1534 "!nvme_zalloc_dma failed for GET LOG PAGE");
1535 1535 goto fail;
1536 1536 }
1537 1537
1538 1538 if (cmd->nc_dma->nd_ncookie > 2) {
1539 1539 dev_err(nvme->n_dip, CE_WARN,
1540 1540 "!too many DMA cookies for GET LOG PAGE");
1541 1541 atomic_inc_32(&nvme->n_too_many_cookies);
1542 1542 goto fail;
1543 1543 }
1544 1544
1545 1545 cmd->nc_sqe.sqe_dptr.d_prp[0] = cmd->nc_dma->nd_cookie.dmac_laddress;
1546 1546 if (cmd->nc_dma->nd_ncookie > 1) {
1547 1547 ddi_dma_nextcookie(cmd->nc_dma->nd_dmah,
1548 1548 &cmd->nc_dma->nd_cookie);
1549 1549 cmd->nc_sqe.sqe_dptr.d_prp[1] =
1550 1550 cmd->nc_dma->nd_cookie.dmac_laddress;
1551 1551 }
1552 1552
1553 1553 if (nvme_admin_cmd(cmd, nvme_admin_cmd_timeout) != DDI_SUCCESS) {
1554 1554 dev_err(nvme->n_dip, CE_WARN,
1555 1555 "!nvme_admin_cmd failed for GET LOG PAGE");
1556 1556 return (NULL);
1557 1557 }
1558 1558
1559 1559 if (nvme_check_cmd_status(cmd)) {
1560 1560 dev_err(nvme->n_dip, CE_WARN,
1561 1561 "!GET LOG PAGE failed with sct = %x, sc = %x",
1562 1562 cmd->nc_cqe.cqe_sf.sf_sct, cmd->nc_cqe.cqe_sf.sf_sc);
1563 1563 goto fail;
1564 1564 }
1565 1565
1566 1566 buf = kmem_alloc(bufsize, KM_SLEEP);
1567 1567 bcopy(cmd->nc_dma->nd_memp, buf, bufsize);
1568 1568
1569 1569 fail:
1570 1570 nvme_free_cmd(cmd);
1571 1571
1572 1572 return (buf);
1573 1573 }
1574 1574
1575 1575 static void *
1576 1576 nvme_identify(nvme_t *nvme, uint32_t nsid)
1577 1577 {
1578 1578 nvme_cmd_t *cmd = nvme_alloc_cmd(nvme, KM_SLEEP);
1579 1579 void *buf = NULL;
1580 1580
1581 1581 cmd->nc_sqid = 0;
1582 1582 cmd->nc_callback = nvme_wakeup_cmd;
1583 1583 cmd->nc_sqe.sqe_opc = NVME_OPC_IDENTIFY;
1584 1584 cmd->nc_sqe.sqe_nsid = nsid;
1585 1585 cmd->nc_sqe.sqe_cdw10 = nsid ? NVME_IDENTIFY_NSID : NVME_IDENTIFY_CTRL;
1586 1586
1587 1587 if (nvme_zalloc_dma(nvme, NVME_IDENTIFY_BUFSIZE, DDI_DMA_READ,
1588 1588 &nvme->n_prp_dma_attr, &cmd->nc_dma) != DDI_SUCCESS) {
1589 1589 dev_err(nvme->n_dip, CE_WARN,
1590 1590 "!nvme_zalloc_dma failed for IDENTIFY");
1591 1591 goto fail;
1592 1592 }
1593 1593
1594 1594 if (cmd->nc_dma->nd_ncookie > 2) {
1595 1595 dev_err(nvme->n_dip, CE_WARN,
1596 1596 "!too many DMA cookies for IDENTIFY");
1597 1597 atomic_inc_32(&nvme->n_too_many_cookies);
1598 1598 goto fail;
1599 1599 }
1600 1600
1601 1601 cmd->nc_sqe.sqe_dptr.d_prp[0] = cmd->nc_dma->nd_cookie.dmac_laddress;
1602 1602 if (cmd->nc_dma->nd_ncookie > 1) {
1603 1603 ddi_dma_nextcookie(cmd->nc_dma->nd_dmah,
1604 1604 &cmd->nc_dma->nd_cookie);
1605 1605 cmd->nc_sqe.sqe_dptr.d_prp[1] =
1606 1606 cmd->nc_dma->nd_cookie.dmac_laddress;
1607 1607 }
1608 1608
1609 1609 if (nvme_admin_cmd(cmd, nvme_admin_cmd_timeout) != DDI_SUCCESS) {
1610 1610 dev_err(nvme->n_dip, CE_WARN,
1611 1611 "!nvme_admin_cmd failed for IDENTIFY");
1612 1612 return (NULL);
1613 1613 }
1614 1614
1615 1615 if (nvme_check_cmd_status(cmd)) {
1616 1616 dev_err(nvme->n_dip, CE_WARN,
1617 1617 "!IDENTIFY failed with sct = %x, sc = %x",
1618 1618 cmd->nc_cqe.cqe_sf.sf_sct, cmd->nc_cqe.cqe_sf.sf_sc);
1619 1619 goto fail;
1620 1620 }
1621 1621
1622 1622 buf = kmem_alloc(NVME_IDENTIFY_BUFSIZE, KM_SLEEP);
1623 1623 bcopy(cmd->nc_dma->nd_memp, buf, NVME_IDENTIFY_BUFSIZE);
1624 1624
1625 1625 fail:
1626 1626 nvme_free_cmd(cmd);
1627 1627
1628 1628 return (buf);
1629 1629 }
1630 1630
1631 1631 static boolean_t
1632 1632 nvme_set_features(nvme_t *nvme, uint32_t nsid, uint8_t feature, uint32_t val,
1633 1633 uint32_t *res)
1634 1634 {
1635 1635 _NOTE(ARGUNUSED(nsid));
1636 1636 nvme_cmd_t *cmd = nvme_alloc_cmd(nvme, KM_SLEEP);
1637 1637 boolean_t ret = B_FALSE;
1638 1638
1639 1639 ASSERT(res != NULL);
1640 1640
1641 1641 cmd->nc_sqid = 0;
1642 1642 cmd->nc_callback = nvme_wakeup_cmd;
1643 1643 cmd->nc_sqe.sqe_opc = NVME_OPC_SET_FEATURES;
1644 1644 cmd->nc_sqe.sqe_cdw10 = feature;
1645 1645 cmd->nc_sqe.sqe_cdw11 = val;
1646 1646
1647 1647 switch (feature) {
1648 1648 case NVME_FEAT_WRITE_CACHE:
1649 1649 if (!nvme->n_write_cache_present)
1650 1650 goto fail;
1651 1651 break;
1652 1652
1653 1653 case NVME_FEAT_NQUEUES:
1654 1654 break;
1655 1655
1656 1656 default:
1657 1657 goto fail;
1658 1658 }
1659 1659
1660 1660 if (nvme_admin_cmd(cmd, nvme_admin_cmd_timeout) != DDI_SUCCESS) {
1661 1661 dev_err(nvme->n_dip, CE_WARN,
1662 1662 "!nvme_admin_cmd failed for SET FEATURES");
1663 1663 return (ret);
1664 1664 }
1665 1665
1666 1666 if (nvme_check_cmd_status(cmd)) {
1667 1667 dev_err(nvme->n_dip, CE_WARN,
1668 1668 "!SET FEATURES %d failed with sct = %x, sc = %x",
1669 1669 feature, cmd->nc_cqe.cqe_sf.sf_sct,
1670 1670 cmd->nc_cqe.cqe_sf.sf_sc);
1671 1671 goto fail;
1672 1672 }
1673 1673
1674 1674 *res = cmd->nc_cqe.cqe_dw0;
1675 1675 ret = B_TRUE;
1676 1676
1677 1677 fail:
1678 1678 nvme_free_cmd(cmd);
1679 1679 return (ret);
1680 1680 }
1681 1681
1682 1682 static boolean_t
1683 1683 nvme_write_cache_set(nvme_t *nvme, boolean_t enable)
1684 1684 {
1685 1685 nvme_write_cache_t nwc = { 0 };
1686 1686
1687 1687 if (enable)
1688 1688 nwc.b.wc_wce = 1;
1689 1689
1690 1690 if (!nvme_set_features(nvme, 0, NVME_FEAT_WRITE_CACHE, nwc.r, &nwc.r))
1691 1691 return (B_FALSE);
1692 1692
1693 1693 return (B_TRUE);
1694 1694 }
1695 1695
1696 1696 static int
1697 1697 nvme_set_nqueues(nvme_t *nvme, uint16_t nqueues)
1698 1698 {
1699 1699 nvme_nqueue_t nq = { 0 };
1700 1700
1701 1701 nq.b.nq_nsq = nq.b.nq_ncq = nqueues - 1;
1702 1702
1703 1703 if (!nvme_set_features(nvme, 0, NVME_FEAT_NQUEUES, nq.r, &nq.r)) {
1704 1704 return (0);
1705 1705 }
1706 1706
1707 1707 /*
1708 1708 * Always use the same number of submission and completion queues, and
1709 1709 * never use more than the requested number of queues.
1710 1710 */
1711 1711 return (MIN(nqueues, MIN(nq.b.nq_nsq, nq.b.nq_ncq) + 1));
1712 1712 }
1713 1713
1714 1714 static int
1715 1715 nvme_create_io_qpair(nvme_t *nvme, nvme_qpair_t *qp, uint16_t idx)
1716 1716 {
1717 1717 nvme_cmd_t *cmd = nvme_alloc_cmd(nvme, KM_SLEEP);
1718 1718 nvme_create_queue_dw10_t dw10 = { 0 };
1719 1719 nvme_create_cq_dw11_t c_dw11 = { 0 };
1720 1720 nvme_create_sq_dw11_t s_dw11 = { 0 };
1721 1721
1722 1722 dw10.b.q_qid = idx;
1723 1723 dw10.b.q_qsize = qp->nq_nentry - 1;
1724 1724
1725 1725 c_dw11.b.cq_pc = 1;
1726 1726 c_dw11.b.cq_ien = 1;
1727 1727 c_dw11.b.cq_iv = idx % nvme->n_intr_cnt;
1728 1728
1729 1729 cmd->nc_sqid = 0;
1730 1730 cmd->nc_callback = nvme_wakeup_cmd;
1731 1731 cmd->nc_sqe.sqe_opc = NVME_OPC_CREATE_CQUEUE;
1732 1732 cmd->nc_sqe.sqe_cdw10 = dw10.r;
1733 1733 cmd->nc_sqe.sqe_cdw11 = c_dw11.r;
1734 1734 cmd->nc_sqe.sqe_dptr.d_prp[0] = qp->nq_cqdma->nd_cookie.dmac_laddress;
1735 1735
1736 1736 if (nvme_admin_cmd(cmd, nvme_admin_cmd_timeout) != DDI_SUCCESS) {
1737 1737 dev_err(nvme->n_dip, CE_WARN,
1738 1738 "!nvme_admin_cmd failed for CREATE CQUEUE");
1739 1739 return (DDI_FAILURE);
1740 1740 }
1741 1741
1742 1742 if (nvme_check_cmd_status(cmd)) {
1743 1743 dev_err(nvme->n_dip, CE_WARN,
1744 1744 "!CREATE CQUEUE failed with sct = %x, sc = %x",
1745 1745 cmd->nc_cqe.cqe_sf.sf_sct, cmd->nc_cqe.cqe_sf.sf_sc);
1746 1746 nvme_free_cmd(cmd);
1747 1747 return (DDI_FAILURE);
1748 1748 }
1749 1749
1750 1750 nvme_free_cmd(cmd);
1751 1751
1752 1752 s_dw11.b.sq_pc = 1;
1753 1753 s_dw11.b.sq_cqid = idx;
1754 1754
1755 1755 cmd = nvme_alloc_cmd(nvme, KM_SLEEP);
1756 1756 cmd->nc_sqid = 0;
1757 1757 cmd->nc_callback = nvme_wakeup_cmd;
1758 1758 cmd->nc_sqe.sqe_opc = NVME_OPC_CREATE_SQUEUE;
1759 1759 cmd->nc_sqe.sqe_cdw10 = dw10.r;
1760 1760 cmd->nc_sqe.sqe_cdw11 = s_dw11.r;
1761 1761 cmd->nc_sqe.sqe_dptr.d_prp[0] = qp->nq_sqdma->nd_cookie.dmac_laddress;
1762 1762
1763 1763 if (nvme_admin_cmd(cmd, nvme_admin_cmd_timeout) != DDI_SUCCESS) {
1764 1764 dev_err(nvme->n_dip, CE_WARN,
1765 1765 "!nvme_admin_cmd failed for CREATE SQUEUE");
1766 1766 return (DDI_FAILURE);
1767 1767 }
1768 1768
1769 1769 if (nvme_check_cmd_status(cmd)) {
1770 1770 dev_err(nvme->n_dip, CE_WARN,
1771 1771 "!CREATE SQUEUE failed with sct = %x, sc = %x",
1772 1772 cmd->nc_cqe.cqe_sf.sf_sct, cmd->nc_cqe.cqe_sf.sf_sc);
1773 1773 nvme_free_cmd(cmd);
1774 1774 return (DDI_FAILURE);
1775 1775 }
1776 1776
1777 1777 nvme_free_cmd(cmd);
1778 1778
1779 1779 return (DDI_SUCCESS);
1780 1780 }
1781 1781
1782 1782 static boolean_t
1783 1783 nvme_reset(nvme_t *nvme, boolean_t quiesce)
1784 1784 {
1785 1785 nvme_reg_csts_t csts;
1786 1786 int i;
1787 1787
1788 1788 nvme_put32(nvme, NVME_REG_CC, 0);
1789 1789
1790 1790 csts.r = nvme_get32(nvme, NVME_REG_CSTS);
1791 1791 if (csts.b.csts_rdy == 1) {
1792 1792 nvme_put32(nvme, NVME_REG_CC, 0);
1793 1793 for (i = 0; i != nvme->n_timeout * 10; i++) {
1794 1794 csts.r = nvme_get32(nvme, NVME_REG_CSTS);
1795 1795 if (csts.b.csts_rdy == 0)
1796 1796 break;
1797 1797
1798 1798 if (quiesce)
1799 1799 drv_usecwait(50000);
1800 1800 else
1801 1801 delay(drv_usectohz(50000));
1802 1802 }
1803 1803 }
1804 1804
1805 1805 nvme_put32(nvme, NVME_REG_AQA, 0);
1806 1806 nvme_put32(nvme, NVME_REG_ASQ, 0);
1807 1807 nvme_put32(nvme, NVME_REG_ACQ, 0);
1808 1808
1809 1809 csts.r = nvme_get32(nvme, NVME_REG_CSTS);
1810 1810 return (csts.b.csts_rdy == 0 ? B_TRUE : B_FALSE);
1811 1811 }
1812 1812
1813 1813 static void
1814 1814 nvme_shutdown(nvme_t *nvme, int mode, boolean_t quiesce)
1815 1815 {
1816 1816 nvme_reg_cc_t cc;
1817 1817 nvme_reg_csts_t csts;
1818 1818 int i;
1819 1819
1820 1820 ASSERT(mode == NVME_CC_SHN_NORMAL || mode == NVME_CC_SHN_ABRUPT);
1821 1821
1822 1822 cc.r = nvme_get32(nvme, NVME_REG_CC);
1823 1823 cc.b.cc_shn = mode & 0x3;
1824 1824 nvme_put32(nvme, NVME_REG_CC, cc.r);
1825 1825
1826 1826 for (i = 0; i != 10; i++) {
1827 1827 csts.r = nvme_get32(nvme, NVME_REG_CSTS);
1828 1828 if (csts.b.csts_shst == NVME_CSTS_SHN_COMPLETE)
1829 1829 break;
1830 1830
1831 1831 if (quiesce)
1832 1832 drv_usecwait(100000);
1833 1833 else
1834 1834 delay(drv_usectohz(100000));
1835 1835 }
1836 1836 }
1837 1837
1838 1838
1839 1839 static void
1840 1840 nvme_prepare_devid(nvme_t *nvme, uint32_t nsid)
1841 1841 {
1842 1842 /*
1843 1843 * Section 7.7 of the spec describes how to get a unique ID for
1844 1844 * the controller: the vendor ID, the model name and the serial
1845 1845 * number shall be unique when combined.
1846 1846 *
1847 1847 * If a namespace has no EUI64 we use the above and add the hex
1848 1848 * namespace ID to get a unique ID for the namespace.
1849 1849 */
1850 1850 char model[sizeof (nvme->n_idctl->id_model) + 1];
1851 1851 char serial[sizeof (nvme->n_idctl->id_serial) + 1];
1852 1852
1853 1853 bcopy(nvme->n_idctl->id_model, model, sizeof (nvme->n_idctl->id_model));
1854 1854 bcopy(nvme->n_idctl->id_serial, serial,
1855 1855 sizeof (nvme->n_idctl->id_serial));
1856 1856
1857 1857 model[sizeof (nvme->n_idctl->id_model)] = '\0';
1858 1858 serial[sizeof (nvme->n_idctl->id_serial)] = '\0';
1859 1859
1860 1860 nvme->n_ns[nsid - 1].ns_devid = kmem_asprintf("%4X-%s-%s-%X",
1861 1861 nvme->n_idctl->id_vid, model, serial, nsid);
1862 1862 }
1863 1863
1864 1864 static int
1865 1865 nvme_init(nvme_t *nvme)
1866 1866 {
1867 1867 nvme_reg_cc_t cc = { 0 };
1868 1868 nvme_reg_aqa_t aqa = { 0 };
1869 1869 nvme_reg_asq_t asq = { 0 };
1870 1870 nvme_reg_acq_t acq = { 0 };
1871 1871 nvme_reg_cap_t cap;
1872 1872 nvme_reg_vs_t vs;
1873 1873 nvme_reg_csts_t csts;
1874 1874 int i = 0;
1875 1875 int nqueues;
1876 1876 char model[sizeof (nvme->n_idctl->id_model) + 1];
1877 1877 char *vendor, *product;
1878 1878
1879 1879 /* Check controller version */
1880 1880 vs.r = nvme_get32(nvme, NVME_REG_VS);
1881 1881 nvme->n_version.v_major = vs.b.vs_mjr;
1882 1882 nvme->n_version.v_minor = vs.b.vs_mnr;
1883 1883 dev_err(nvme->n_dip, CE_CONT, "?NVMe spec version %d.%d",
1884 1884 nvme->n_version.v_major, nvme->n_version.v_minor);
1885 1885
1886 1886 if (NVME_VERSION_HIGHER(&nvme->n_version,
1887 1887 nvme_version_major, nvme_version_minor)) {
1888 1888 dev_err(nvme->n_dip, CE_WARN, "!no support for version > %d.%d",
1889 1889 nvme_version_major, nvme_version_minor);
1890 1890 if (nvme->n_strict_version)
1891 1891 goto fail;
1892 1892 }
1893 1893
1894 1894 /* retrieve controller configuration */
1895 1895 cap.r = nvme_get64(nvme, NVME_REG_CAP);
1896 1896
1897 1897 if ((cap.b.cap_css & NVME_CAP_CSS_NVM) == 0) {
1898 1898 dev_err(nvme->n_dip, CE_WARN,
1899 1899 "!NVM command set not supported by hardware");
1900 1900 goto fail;
1901 1901 }
1902 1902
1903 1903 nvme->n_nssr_supported = cap.b.cap_nssrs;
1904 1904 nvme->n_doorbell_stride = 4 << cap.b.cap_dstrd;
1905 1905 nvme->n_timeout = cap.b.cap_to;
1906 1906 nvme->n_arbitration_mechanisms = cap.b.cap_ams;
1907 1907 nvme->n_cont_queues_reqd = cap.b.cap_cqr;
1908 1908 nvme->n_max_queue_entries = cap.b.cap_mqes + 1;
1909 1909
1910 1910 /*
1911 1911 * The MPSMIN and MPSMAX fields in the CAP register use 0 to specify
1912 1912 * the base page size of 4k (1<<12), so add 12 here to get the real
1913 1913 * page size value.
1914 1914 */
1915 1915 nvme->n_pageshift = MIN(MAX(cap.b.cap_mpsmin + 12, PAGESHIFT),
1916 1916 cap.b.cap_mpsmax + 12);
1917 1917 nvme->n_pagesize = 1UL << (nvme->n_pageshift);
1918 1918
1919 1919 /*
1920 1920 * Set up Queue DMA to transfer at least 1 page-aligned page at a time.
1921 1921 */
1922 1922 nvme->n_queue_dma_attr.dma_attr_align = nvme->n_pagesize;
1923 1923 nvme->n_queue_dma_attr.dma_attr_minxfer = nvme->n_pagesize;
1924 1924
1925 1925 /*
1926 1926 * Set up PRP DMA to transfer 1 page-aligned page at a time.
1927 1927 * Maxxfer may be increased after we identified the controller limits.
1928 1928 */
1929 1929 nvme->n_prp_dma_attr.dma_attr_maxxfer = nvme->n_pagesize;
1930 1930 nvme->n_prp_dma_attr.dma_attr_minxfer = nvme->n_pagesize;
1931 1931 nvme->n_prp_dma_attr.dma_attr_align = nvme->n_pagesize;
1932 1932 nvme->n_prp_dma_attr.dma_attr_seg = nvme->n_pagesize - 1;
1933 1933
1934 1934 /*
1935 1935 * Reset controller if it's still in ready state.
1936 1936 */
1937 1937 if (nvme_reset(nvme, B_FALSE) == B_FALSE) {
1938 1938 dev_err(nvme->n_dip, CE_WARN, "!unable to reset controller");
1939 1939 ddi_fm_service_impact(nvme->n_dip, DDI_SERVICE_LOST);
1940 1940 nvme->n_dead = B_TRUE;
1941 1941 goto fail;
1942 1942 }
1943 1943
1944 1944 /*
1945 1945 * Create the admin queue pair.
1946 1946 */
1947 1947 if (nvme_alloc_qpair(nvme, nvme->n_admin_queue_len, &nvme->n_adminq, 0)
1948 1948 != DDI_SUCCESS) {
1949 1949 dev_err(nvme->n_dip, CE_WARN,
1950 1950 "!unable to allocate admin qpair");
1951 1951 goto fail;
1952 1952 }
1953 1953 nvme->n_ioq = kmem_alloc(sizeof (nvme_qpair_t *), KM_SLEEP);
1954 1954 nvme->n_ioq[0] = nvme->n_adminq;
1955 1955
1956 1956 nvme->n_progress |= NVME_ADMIN_QUEUE;
1957 1957
1958 1958 (void) ddi_prop_update_int(DDI_DEV_T_NONE, nvme->n_dip,
1959 1959 "admin-queue-len", nvme->n_admin_queue_len);
1960 1960
1961 1961 aqa.b.aqa_asqs = aqa.b.aqa_acqs = nvme->n_admin_queue_len - 1;
1962 1962 asq = nvme->n_adminq->nq_sqdma->nd_cookie.dmac_laddress;
1963 1963 acq = nvme->n_adminq->nq_cqdma->nd_cookie.dmac_laddress;
1964 1964
1965 1965 ASSERT((asq & (nvme->n_pagesize - 1)) == 0);
1966 1966 ASSERT((acq & (nvme->n_pagesize - 1)) == 0);
1967 1967
1968 1968 nvme_put32(nvme, NVME_REG_AQA, aqa.r);
1969 1969 nvme_put64(nvme, NVME_REG_ASQ, asq);
1970 1970 nvme_put64(nvme, NVME_REG_ACQ, acq);
1971 1971
1972 1972 cc.b.cc_ams = 0; /* use Round-Robin arbitration */
1973 1973 cc.b.cc_css = 0; /* use NVM command set */
1974 1974 cc.b.cc_mps = nvme->n_pageshift - 12;
1975 1975 cc.b.cc_shn = 0; /* no shutdown in progress */
1976 1976 cc.b.cc_en = 1; /* enable controller */
1977 1977 cc.b.cc_iosqes = 6; /* submission queue entry is 2^6 bytes long */
1978 1978 cc.b.cc_iocqes = 4; /* completion queue entry is 2^4 bytes long */
1979 1979
1980 1980 nvme_put32(nvme, NVME_REG_CC, cc.r);
1981 1981
1982 1982 /*
1983 1983 * Wait for the controller to become ready.
1984 1984 */
1985 1985 csts.r = nvme_get32(nvme, NVME_REG_CSTS);
1986 1986 if (csts.b.csts_rdy == 0) {
1987 1987 for (i = 0; i != nvme->n_timeout * 10; i++) {
1988 1988 delay(drv_usectohz(50000));
1989 1989 csts.r = nvme_get32(nvme, NVME_REG_CSTS);
1990 1990
1991 1991 if (csts.b.csts_cfs == 1) {
1992 1992 dev_err(nvme->n_dip, CE_WARN,
1993 1993 "!controller fatal status at init");
1994 1994 ddi_fm_service_impact(nvme->n_dip,
1995 1995 DDI_SERVICE_LOST);
1996 1996 nvme->n_dead = B_TRUE;
1997 1997 goto fail;
1998 1998 }
1999 1999
2000 2000 if (csts.b.csts_rdy == 1)
2001 2001 break;
2002 2002 }
2003 2003 }
2004 2004
2005 2005 if (csts.b.csts_rdy == 0) {
2006 2006 dev_err(nvme->n_dip, CE_WARN, "!controller not ready");
2007 2007 ddi_fm_service_impact(nvme->n_dip, DDI_SERVICE_LOST);
2008 2008 nvme->n_dead = B_TRUE;
2009 2009 goto fail;
2010 2010 }
2011 2011
2012 2012 /*
2013 2013 * Assume an abort command limit of 1. We'll destroy and re-init
2014 2014 * that later when we know the true abort command limit.
2015 2015 */
2016 2016 sema_init(&nvme->n_abort_sema, 1, NULL, SEMA_DRIVER, NULL);
2017 2017
2018 2018 /*
2019 2019 * Setup initial interrupt for admin queue.
2020 2020 */
2021 2021 if ((nvme_setup_interrupts(nvme, DDI_INTR_TYPE_MSIX, 1)
2022 2022 != DDI_SUCCESS) &&
2023 2023 (nvme_setup_interrupts(nvme, DDI_INTR_TYPE_MSI, 1)
2024 2024 != DDI_SUCCESS) &&
2025 2025 (nvme_setup_interrupts(nvme, DDI_INTR_TYPE_FIXED, 1)
2026 2026 != DDI_SUCCESS)) {
2027 2027 dev_err(nvme->n_dip, CE_WARN,
2028 2028 "!failed to setup initial interrupt");
2029 2029 goto fail;
2030 2030 }
2031 2031
2032 2032 /*
2033 2033 * Post an asynchronous event command to catch errors.
2034 2034 */
2035 2035 if (nvme_async_event(nvme) != DDI_SUCCESS) {
2036 2036 dev_err(nvme->n_dip, CE_WARN,
2037 2037 "!failed to post async event");
2038 2038 goto fail;
2039 2039 }
2040 2040
2041 2041 /*
2042 2042 * Identify Controller
2043 2043 */
2044 2044 nvme->n_idctl = nvme_identify(nvme, 0);
2045 2045 if (nvme->n_idctl == NULL) {
2046 2046 dev_err(nvme->n_dip, CE_WARN,
2047 2047 "!failed to identify controller");
2048 2048 goto fail;
2049 2049 }
2050 2050
2051 2051 /*
2052 2052 * Get Vendor & Product ID
2053 2053 */
2054 2054 bcopy(nvme->n_idctl->id_model, model, sizeof (nvme->n_idctl->id_model));
2055 2055 model[sizeof (nvme->n_idctl->id_model)] = '\0';
2056 2056 sata_split_model(model, &vendor, &product);
2057 2057
2058 2058 if (vendor == NULL)
2059 2059 nvme->n_vendor = strdup("NVMe");
2060 2060 else
2061 2061 nvme->n_vendor = strdup(vendor);
2062 2062
2063 2063 nvme->n_product = strdup(product);
2064 2064
2065 2065 /*
2066 2066 * Get controller limits.
2067 2067 */
2068 2068 nvme->n_async_event_limit = MAX(NVME_MIN_ASYNC_EVENT_LIMIT,
2069 2069 MIN(nvme->n_admin_queue_len / 10,
2070 2070 MIN(nvme->n_idctl->id_aerl + 1, nvme->n_async_event_limit)));
2071 2071
2072 2072 (void) ddi_prop_update_int(DDI_DEV_T_NONE, nvme->n_dip,
2073 2073 "async-event-limit", nvme->n_async_event_limit);
2074 2074
2075 2075 nvme->n_abort_command_limit = nvme->n_idctl->id_acl + 1;
2076 2076
2077 2077 /*
2078 2078 * Reinitialize the semaphore with the true abort command limit
2079 2079 * supported by the hardware. It's not necessary to disable interrupts
2080 2080 * as only command aborts use the semaphore, and no commands are
2081 2081 * executed or aborted while we're here.
2082 2082 */
2083 2083 sema_destroy(&nvme->n_abort_sema);
2084 2084 sema_init(&nvme->n_abort_sema, nvme->n_abort_command_limit - 1, NULL,
2085 2085 SEMA_DRIVER, NULL);
2086 2086
2087 2087 nvme->n_progress |= NVME_CTRL_LIMITS;
2088 2088
2089 2089 if (nvme->n_idctl->id_mdts == 0)
2090 2090 nvme->n_max_data_transfer_size = nvme->n_pagesize * 65536;
2091 2091 else
2092 2092 nvme->n_max_data_transfer_size =
2093 2093 1ull << (nvme->n_pageshift + nvme->n_idctl->id_mdts);
2094 2094
2095 2095 nvme->n_error_log_len = nvme->n_idctl->id_elpe + 1;
2096 2096
2097 2097 /*
2098 2098 * Limit n_max_data_transfer_size to what we can handle in one PRP.
2099 2099 * Chained PRPs are currently unsupported.
2100 2100 *
2101 2101 * This is a no-op on hardware which doesn't support a transfer size
2102 2102 * big enough to require chained PRPs.
2103 2103 */
2104 2104 nvme->n_max_data_transfer_size = MIN(nvme->n_max_data_transfer_size,
2105 2105 (nvme->n_pagesize / sizeof (uint64_t) * nvme->n_pagesize));
2106 2106
2107 2107 nvme->n_prp_dma_attr.dma_attr_maxxfer = nvme->n_max_data_transfer_size;
2108 2108
2109 2109 /*
2110 2110 * Make sure the minimum/maximum queue entry sizes are not
2111 2111 * larger/smaller than the default.
2112 2112 */
2113 2113
2114 2114 if (((1 << nvme->n_idctl->id_sqes.qes_min) > sizeof (nvme_sqe_t)) ||
2115 2115 ((1 << nvme->n_idctl->id_sqes.qes_max) < sizeof (nvme_sqe_t)) ||
2116 2116 ((1 << nvme->n_idctl->id_cqes.qes_min) > sizeof (nvme_cqe_t)) ||
2117 2117 ((1 << nvme->n_idctl->id_cqes.qes_max) < sizeof (nvme_cqe_t)))
2118 2118 goto fail;
2119 2119
2120 2120 /*
2121 2121 * Check for the presence of a Volatile Write Cache. If present,
2122 2122 * enable or disable based on the value of the property
2123 2123 * volatile-write-cache-enable (default is enabled).
2124 2124 */
2125 2125 nvme->n_write_cache_present =
2126 2126 nvme->n_idctl->id_vwc.vwc_present == 0 ? B_FALSE : B_TRUE;
2127 2127
2128 2128 (void) ddi_prop_update_int(DDI_DEV_T_NONE, nvme->n_dip,
2129 2129 "volatile-write-cache-present",
2130 2130 nvme->n_write_cache_present ? 1 : 0);
2131 2131
2132 2132 if (!nvme->n_write_cache_present) {
2133 2133 nvme->n_write_cache_enabled = B_FALSE;
2134 2134 } else if (!nvme_write_cache_set(nvme, nvme->n_write_cache_enabled)) {
2135 2135 dev_err(nvme->n_dip, CE_WARN,
2136 2136 "!failed to %sable volatile write cache",
2137 2137 nvme->n_write_cache_enabled ? "en" : "dis");
2138 2138 /*
2139 2139 * Assume the cache is (still) enabled.
2140 2140 */
2141 2141 nvme->n_write_cache_enabled = B_TRUE;
2142 2142 }
2143 2143
2144 2144 (void) ddi_prop_update_int(DDI_DEV_T_NONE, nvme->n_dip,
2145 2145 "volatile-write-cache-enable",
2146 2146 nvme->n_write_cache_enabled ? 1 : 0);
2147 2147
2148 2148 /*
2149 2149 * Grab a copy of all mandatory log pages.
2150 2150 *
2151 2151 * TODO: should go away once user space tool exists to print logs
2152 2152 */
2153 2153 nvme->n_error_log = (nvme_error_log_entry_t *)
2154 2154 nvme_get_logpage(nvme, NVME_LOGPAGE_ERROR);
2155 2155 nvme->n_health_log = (nvme_health_log_t *)
2156 2156 nvme_get_logpage(nvme, NVME_LOGPAGE_HEALTH, -1);
2157 2157 nvme->n_fwslot_log = (nvme_fwslot_log_t *)
2158 2158 nvme_get_logpage(nvme, NVME_LOGPAGE_FWSLOT);
2159 2159
2160 2160 /*
2161 2161 * Identify Namespaces
2162 2162 */
2163 2163 nvme->n_namespace_count = nvme->n_idctl->id_nn;
2164 2164 nvme->n_ns = kmem_zalloc(sizeof (nvme_namespace_t) *
2165 2165 nvme->n_namespace_count, KM_SLEEP);
2166 2166
2167 2167 for (i = 0; i != nvme->n_namespace_count; i++) {
2168 2168 nvme_identify_nsid_t *idns;
2169 2169 int last_rp;
2170 2170
2171 2171 nvme->n_ns[i].ns_nvme = nvme;
2172 2172 nvme->n_ns[i].ns_idns = idns = nvme_identify(nvme, i + 1);
2173 2173
2174 2174 if (idns == NULL) {
2175 2175 dev_err(nvme->n_dip, CE_WARN,
2176 2176 "!failed to identify namespace %d", i + 1);
2177 2177 goto fail;
2178 2178 }
2179 2179
2180 2180 nvme->n_ns[i].ns_id = i + 1;
2181 2181 nvme->n_ns[i].ns_block_count = idns->id_nsize;
2182 2182 nvme->n_ns[i].ns_block_size =
2183 2183 1 << idns->id_lbaf[idns->id_flbas.lba_format].lbaf_lbads;
2184 2184 nvme->n_ns[i].ns_best_block_size = nvme->n_ns[i].ns_block_size;
2185 2185
2186 2186 /*
2187 2187 * Get the EUI64 if present. If not present prepare the devid
2188 2188 * from other device data.
2189 2189 */
2190 2190 if (NVME_VERSION_ATLEAST(&nvme->n_version, 1, 1))
2191 2191 bcopy(idns->id_eui64, nvme->n_ns[i].ns_eui64,
2192 2192 sizeof (nvme->n_ns[i].ns_eui64));
2193 2193
2194 2194 /*LINTED: E_BAD_PTR_CAST_ALIGN*/
2195 2195 if (*(uint64_t *)nvme->n_ns[i].ns_eui64 == 0) {
2196 2196 nvme_prepare_devid(nvme, nvme->n_ns[i].ns_id);
2197 2197 } else {
2198 2198 /*
2199 2199 * Until EUI64 support is tested on real hardware we
2200 2200 * will ignore namespaces with an EUI64. This can
2201 2201 * be overriden by setting strict-version=0 in nvme.conf
2202 2202 */
2203 2203 if (nvme->n_strict_version)
2204 2204 nvme->n_ns[i].ns_ignore = B_TRUE;
2205 2205 }
2206 2206
2207 2207 /*
2208 2208 * Find the LBA format with no metadata and the best relative
2209 2209 * performance. A value of 3 means "degraded", 0 is best.
2210 2210 */
2211 2211 last_rp = 3;
2212 2212 for (int j = 0; j <= idns->id_nlbaf; j++) {
2213 2213 if (idns->id_lbaf[j].lbaf_lbads == 0)
2214 2214 break;
2215 2215 if (idns->id_lbaf[j].lbaf_ms != 0)
2216 2216 continue;
2217 2217 if (idns->id_lbaf[j].lbaf_rp >= last_rp)
2218 2218 continue;
2219 2219 last_rp = idns->id_lbaf[j].lbaf_rp;
2220 2220 nvme->n_ns[i].ns_best_block_size =
2221 2221 1 << idns->id_lbaf[j].lbaf_lbads;
2222 2222 }
2223 2223
2224 2224 if (nvme->n_ns[i].ns_best_block_size < nvme->n_min_block_size)
2225 2225 nvme->n_ns[i].ns_best_block_size =
2226 2226 nvme->n_min_block_size;
2227 2227
2228 2228 /*
2229 2229 * We currently don't support namespaces that use either:
2230 2230 * - thin provisioning
2231 2231 * - protection information
2232 2232 */
2233 2233 if (idns->id_nsfeat.f_thin ||
2234 2234 idns->id_dps.dp_pinfo) {
2235 2235 dev_err(nvme->n_dip, CE_WARN,
2236 2236 "!ignoring namespace %d, unsupported features: "
2237 2237 "thin = %d, pinfo = %d", i + 1,
2238 2238 idns->id_nsfeat.f_thin, idns->id_dps.dp_pinfo);
2239 2239 nvme->n_ns[i].ns_ignore = B_TRUE;
2240 2240 }
2241 2241 }
2242 2242
2243 2243 /*
2244 2244 * Try to set up MSI/MSI-X interrupts.
2245 2245 */
2246 2246 if ((nvme->n_intr_types & (DDI_INTR_TYPE_MSI | DDI_INTR_TYPE_MSIX))
2247 2247 != 0) {
2248 2248 nvme_release_interrupts(nvme);
2249 2249
2250 2250 nqueues = MIN(UINT16_MAX, ncpus);
2251 2251
2252 2252 if ((nvme_setup_interrupts(nvme, DDI_INTR_TYPE_MSIX,
2253 2253 nqueues) != DDI_SUCCESS) &&
2254 2254 (nvme_setup_interrupts(nvme, DDI_INTR_TYPE_MSI,
2255 2255 nqueues) != DDI_SUCCESS)) {
2256 2256 dev_err(nvme->n_dip, CE_WARN,
2257 2257 "!failed to setup MSI/MSI-X interrupts");
2258 2258 goto fail;
2259 2259 }
2260 2260 }
2261 2261
2262 2262 nqueues = nvme->n_intr_cnt;
2263 2263
2264 2264 /*
2265 2265 * Create I/O queue pairs.
2266 2266 */
2267 2267 nvme->n_ioq_count = nvme_set_nqueues(nvme, nqueues);
2268 2268 if (nvme->n_ioq_count == 0) {
2269 2269 dev_err(nvme->n_dip, CE_WARN,
2270 2270 "!failed to set number of I/O queues to %d", nqueues);
2271 2271 goto fail;
2272 2272 }
2273 2273
2274 2274 /*
2275 2275 * Reallocate I/O queue array
2276 2276 */
2277 2277 kmem_free(nvme->n_ioq, sizeof (nvme_qpair_t *));
2278 2278 nvme->n_ioq = kmem_zalloc(sizeof (nvme_qpair_t *) *
2279 2279 (nvme->n_ioq_count + 1), KM_SLEEP);
2280 2280 nvme->n_ioq[0] = nvme->n_adminq;
2281 2281
2282 2282 /*
2283 2283 * If we got less queues than we asked for we might as well give
2284 2284 * some of the interrupt vectors back to the system.
2285 2285 */
2286 2286 if (nvme->n_ioq_count < nqueues) {
2287 2287 nvme_release_interrupts(nvme);
2288 2288
2289 2289 if (nvme_setup_interrupts(nvme, nvme->n_intr_type,
2290 2290 nvme->n_ioq_count) != DDI_SUCCESS) {
2291 2291 dev_err(nvme->n_dip, CE_WARN,
2292 2292 "!failed to reduce number of interrupts");
2293 2293 goto fail;
2294 2294 }
2295 2295 }
2296 2296
2297 2297 /*
2298 2298 * Alloc & register I/O queue pairs
2299 2299 */
2300 2300 nvme->n_io_queue_len =
2301 2301 MIN(nvme->n_io_queue_len, nvme->n_max_queue_entries);
2302 2302 (void) ddi_prop_update_int(DDI_DEV_T_NONE, nvme->n_dip, "io-queue-len",
2303 2303 nvme->n_io_queue_len);
2304 2304
2305 2305 for (i = 1; i != nvme->n_ioq_count + 1; i++) {
2306 2306 if (nvme_alloc_qpair(nvme, nvme->n_io_queue_len,
2307 2307 &nvme->n_ioq[i], i) != DDI_SUCCESS) {
2308 2308 dev_err(nvme->n_dip, CE_WARN,
2309 2309 "!unable to allocate I/O qpair %d", i);
2310 2310 goto fail;
2311 2311 }
2312 2312
2313 2313 if (nvme_create_io_qpair(nvme, nvme->n_ioq[i], i)
2314 2314 != DDI_SUCCESS) {
2315 2315 dev_err(nvme->n_dip, CE_WARN,
2316 2316 "!unable to create I/O qpair %d", i);
2317 2317 goto fail;
2318 2318 }
2319 2319 }
2320 2320
2321 2321 /*
2322 2322 * Post more asynchronous events commands to reduce event reporting
2323 2323 * latency as suggested by the spec.
2324 2324 */
2325 2325 for (i = 1; i != nvme->n_async_event_limit; i++) {
2326 2326 if (nvme_async_event(nvme) != DDI_SUCCESS) {
2327 2327 dev_err(nvme->n_dip, CE_WARN,
2328 2328 "!failed to post async event %d", i);
2329 2329 goto fail;
2330 2330 }
2331 2331 }
2332 2332
2333 2333 return (DDI_SUCCESS);
2334 2334
2335 2335 fail:
2336 2336 (void) nvme_reset(nvme, B_FALSE);
2337 2337 return (DDI_FAILURE);
2338 2338 }
2339 2339
2340 2340 static uint_t
2341 2341 nvme_intr(caddr_t arg1, caddr_t arg2)
2342 2342 {
2343 2343 /*LINTED: E_PTR_BAD_CAST_ALIGN*/
2344 2344 nvme_t *nvme = (nvme_t *)arg1;
2345 2345 int inum = (int)(uintptr_t)arg2;
2346 2346 int ccnt = 0;
2347 2347 int qnum;
2348 2348 nvme_cmd_t *cmd;
2349 2349
2350 2350 if (inum >= nvme->n_intr_cnt)
2351 2351 return (DDI_INTR_UNCLAIMED);
2352 2352
2353 2353 /*
2354 2354 * The interrupt vector a queue uses is calculated as queue_idx %
2355 2355 * intr_cnt in nvme_create_io_qpair(). Iterate through the queue array
2356 2356 * in steps of n_intr_cnt to process all queues using this vector.
2357 2357 */
2358 2358 for (qnum = inum;
2359 2359 qnum < nvme->n_ioq_count + 1 && nvme->n_ioq[qnum] != NULL;
2360 2360 qnum += nvme->n_intr_cnt) {
2361 2361 while ((cmd = nvme_retrieve_cmd(nvme, nvme->n_ioq[qnum]))) {
2362 2362 taskq_dispatch_ent((taskq_t *)cmd->nc_nvme->n_cmd_taskq,
2363 2363 cmd->nc_callback, cmd, TQ_NOSLEEP, &cmd->nc_tqent);
2364 2364 ccnt++;
2365 2365 }
2366 2366 }
2367 2367
2368 2368 return (ccnt > 0 ? DDI_INTR_CLAIMED : DDI_INTR_UNCLAIMED);
2369 2369 }
2370 2370
2371 2371 static void
2372 2372 nvme_release_interrupts(nvme_t *nvme)
2373 2373 {
2374 2374 int i;
2375 2375
2376 2376 for (i = 0; i < nvme->n_intr_cnt; i++) {
2377 2377 if (nvme->n_inth[i] == NULL)
2378 2378 break;
2379 2379
2380 2380 if (nvme->n_intr_cap & DDI_INTR_FLAG_BLOCK)
2381 2381 (void) ddi_intr_block_disable(&nvme->n_inth[i], 1);
2382 2382 else
2383 2383 (void) ddi_intr_disable(nvme->n_inth[i]);
2384 2384
2385 2385 (void) ddi_intr_remove_handler(nvme->n_inth[i]);
2386 2386 (void) ddi_intr_free(nvme->n_inth[i]);
2387 2387 }
2388 2388
2389 2389 kmem_free(nvme->n_inth, nvme->n_inth_sz);
2390 2390 nvme->n_inth = NULL;
2391 2391 nvme->n_inth_sz = 0;
2392 2392
2393 2393 nvme->n_progress &= ~NVME_INTERRUPTS;
2394 2394 }
2395 2395
2396 2396 static int
2397 2397 nvme_setup_interrupts(nvme_t *nvme, int intr_type, int nqpairs)
2398 2398 {
2399 2399 int nintrs, navail, count;
2400 2400 int ret;
2401 2401 int i;
2402 2402
2403 2403 if (nvme->n_intr_types == 0) {
2404 2404 ret = ddi_intr_get_supported_types(nvme->n_dip,
2405 2405 &nvme->n_intr_types);
2406 2406 if (ret != DDI_SUCCESS) {
2407 2407 dev_err(nvme->n_dip, CE_WARN,
2408 2408 "!%s: ddi_intr_get_supported types failed",
2409 2409 __func__);
2410 2410 return (ret);
2411 2411 }
2412 2412 }
2413 2413
2414 2414 if ((nvme->n_intr_types & intr_type) == 0)
2415 2415 return (DDI_FAILURE);
2416 2416
2417 2417 ret = ddi_intr_get_nintrs(nvme->n_dip, intr_type, &nintrs);
2418 2418 if (ret != DDI_SUCCESS) {
2419 2419 dev_err(nvme->n_dip, CE_WARN, "!%s: ddi_intr_get_nintrs failed",
2420 2420 __func__);
2421 2421 return (ret);
2422 2422 }
2423 2423
2424 2424 ret = ddi_intr_get_navail(nvme->n_dip, intr_type, &navail);
2425 2425 if (ret != DDI_SUCCESS) {
2426 2426 dev_err(nvme->n_dip, CE_WARN, "!%s: ddi_intr_get_navail failed",
2427 2427 __func__);
2428 2428 return (ret);
2429 2429 }
2430 2430
2431 2431 /* We want at most one interrupt per queue pair. */
2432 2432 if (navail > nqpairs)
2433 2433 navail = nqpairs;
2434 2434
2435 2435 nvme->n_inth_sz = sizeof (ddi_intr_handle_t) * navail;
2436 2436 nvme->n_inth = kmem_zalloc(nvme->n_inth_sz, KM_SLEEP);
2437 2437
2438 2438 ret = ddi_intr_alloc(nvme->n_dip, nvme->n_inth, intr_type, 0, navail,
2439 2439 &count, 0);
2440 2440 if (ret != DDI_SUCCESS) {
2441 2441 dev_err(nvme->n_dip, CE_WARN, "!%s: ddi_intr_alloc failed",
2442 2442 __func__);
2443 2443 goto fail;
2444 2444 }
2445 2445
2446 2446 nvme->n_intr_cnt = count;
2447 2447
2448 2448 ret = ddi_intr_get_pri(nvme->n_inth[0], &nvme->n_intr_pri);
2449 2449 if (ret != DDI_SUCCESS) {
2450 2450 dev_err(nvme->n_dip, CE_WARN, "!%s: ddi_intr_get_pri failed",
2451 2451 __func__);
2452 2452 goto fail;
2453 2453 }
2454 2454
2455 2455 for (i = 0; i < count; i++) {
2456 2456 ret = ddi_intr_add_handler(nvme->n_inth[i], nvme_intr,
2457 2457 (void *)nvme, (void *)(uintptr_t)i);
2458 2458 if (ret != DDI_SUCCESS) {
2459 2459 dev_err(nvme->n_dip, CE_WARN,
2460 2460 "!%s: ddi_intr_add_handler failed", __func__);
2461 2461 goto fail;
2462 2462 }
2463 2463 }
2464 2464
2465 2465 (void) ddi_intr_get_cap(nvme->n_inth[0], &nvme->n_intr_cap);
2466 2466
2467 2467 for (i = 0; i < count; i++) {
2468 2468 if (nvme->n_intr_cap & DDI_INTR_FLAG_BLOCK)
2469 2469 ret = ddi_intr_block_enable(&nvme->n_inth[i], 1);
2470 2470 else
2471 2471 ret = ddi_intr_enable(nvme->n_inth[i]);
2472 2472
2473 2473 if (ret != DDI_SUCCESS) {
2474 2474 dev_err(nvme->n_dip, CE_WARN,
2475 2475 "!%s: enabling interrupt %d failed", __func__, i);
2476 2476 goto fail;
2477 2477 }
2478 2478 }
2479 2479
2480 2480 nvme->n_intr_type = intr_type;
2481 2481
2482 2482 nvme->n_progress |= NVME_INTERRUPTS;
2483 2483
2484 2484 return (DDI_SUCCESS);
2485 2485
2486 2486 fail:
2487 2487 nvme_release_interrupts(nvme);
2488 2488
2489 2489 return (ret);
2490 2490 }
2491 2491
2492 2492 static int
2493 2493 nvme_fm_errcb(dev_info_t *dip, ddi_fm_error_t *fm_error, const void *arg)
2494 2494 {
2495 2495 _NOTE(ARGUNUSED(arg));
2496 2496
2497 2497 pci_ereport_post(dip, fm_error, NULL);
2498 2498 return (fm_error->fme_status);
2499 2499 }
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2500 2500
2501 2501 static int
2502 2502 nvme_attach(dev_info_t *dip, ddi_attach_cmd_t cmd)
2503 2503 {
2504 2504 nvme_t *nvme;
2505 2505 int instance;
2506 2506 int nregs;
2507 2507 off_t regsize;
2508 2508 int i;
2509 2509 char name[32];
2510 + bd_ops_t l_bd_ops = nvme_bd_ops;
2510 2511
2511 2512 if (cmd != DDI_ATTACH)
2512 2513 return (DDI_FAILURE);
2513 2514
2514 2515 instance = ddi_get_instance(dip);
2515 2516
2516 2517 if (ddi_soft_state_zalloc(nvme_state, instance) != DDI_SUCCESS)
2517 2518 return (DDI_FAILURE);
2518 2519
2519 2520 nvme = ddi_get_soft_state(nvme_state, instance);
2520 2521 ddi_set_driver_private(dip, nvme);
2521 2522 nvme->n_dip = dip;
2522 2523
2523 2524 nvme->n_strict_version = ddi_prop_get_int(DDI_DEV_T_ANY, dip,
2524 2525 DDI_PROP_DONTPASS, "strict-version", 1) == 1 ? B_TRUE : B_FALSE;
2525 2526 nvme->n_ignore_unknown_vendor_status = ddi_prop_get_int(DDI_DEV_T_ANY,
2526 2527 dip, DDI_PROP_DONTPASS, "ignore-unknown-vendor-status", 0) == 1 ?
2527 2528 B_TRUE : B_FALSE;
2528 2529 nvme->n_admin_queue_len = ddi_prop_get_int(DDI_DEV_T_ANY, dip,
2529 2530 DDI_PROP_DONTPASS, "admin-queue-len", NVME_DEFAULT_ADMIN_QUEUE_LEN);
2530 2531 nvme->n_io_queue_len = ddi_prop_get_int(DDI_DEV_T_ANY, dip,
2531 2532 DDI_PROP_DONTPASS, "io-queue-len", NVME_DEFAULT_IO_QUEUE_LEN);
2532 2533 nvme->n_async_event_limit = ddi_prop_get_int(DDI_DEV_T_ANY, dip,
2533 2534 DDI_PROP_DONTPASS, "async-event-limit",
2534 2535 NVME_DEFAULT_ASYNC_EVENT_LIMIT);
2535 2536 nvme->n_write_cache_enabled = ddi_prop_get_int(DDI_DEV_T_ANY, dip,
2536 2537 DDI_PROP_DONTPASS, "volatile-write-cache-enable", 1) != 0 ?
2537 2538 B_TRUE : B_FALSE;
2538 2539 nvme->n_min_block_size = ddi_prop_get_int(DDI_DEV_T_ANY, dip,
2539 2540 DDI_PROP_DONTPASS, "min-phys-block-size",
2540 2541 NVME_DEFAULT_MIN_BLOCK_SIZE);
2541 2542
2542 2543 if (!ISP2(nvme->n_min_block_size) ||
2543 2544 (nvme->n_min_block_size < NVME_DEFAULT_MIN_BLOCK_SIZE)) {
2544 2545 dev_err(dip, CE_WARN, "!min-phys-block-size %s, "
2545 2546 "using default %d", ISP2(nvme->n_min_block_size) ?
2546 2547 "too low" : "not a power of 2",
2547 2548 NVME_DEFAULT_MIN_BLOCK_SIZE);
2548 2549 nvme->n_min_block_size = NVME_DEFAULT_MIN_BLOCK_SIZE;
2549 2550 }
2550 2551
2551 2552 if (nvme->n_admin_queue_len < NVME_MIN_ADMIN_QUEUE_LEN)
2552 2553 nvme->n_admin_queue_len = NVME_MIN_ADMIN_QUEUE_LEN;
2553 2554 else if (nvme->n_admin_queue_len > NVME_MAX_ADMIN_QUEUE_LEN)
2554 2555 nvme->n_admin_queue_len = NVME_MAX_ADMIN_QUEUE_LEN;
2555 2556
2556 2557 if (nvme->n_io_queue_len < NVME_MIN_IO_QUEUE_LEN)
2557 2558 nvme->n_io_queue_len = NVME_MIN_IO_QUEUE_LEN;
2558 2559
2559 2560 if (nvme->n_async_event_limit < 1)
2560 2561 nvme->n_async_event_limit = NVME_DEFAULT_ASYNC_EVENT_LIMIT;
2561 2562
2562 2563 nvme->n_reg_acc_attr = nvme_reg_acc_attr;
2563 2564 nvme->n_queue_dma_attr = nvme_queue_dma_attr;
2564 2565 nvme->n_prp_dma_attr = nvme_prp_dma_attr;
2565 2566 nvme->n_sgl_dma_attr = nvme_sgl_dma_attr;
2566 2567
2567 2568 /*
2568 2569 * Setup FMA support.
2569 2570 */
2570 2571 nvme->n_fm_cap = ddi_getprop(DDI_DEV_T_ANY, dip,
2571 2572 DDI_PROP_CANSLEEP | DDI_PROP_DONTPASS, "fm-capable",
2572 2573 DDI_FM_EREPORT_CAPABLE | DDI_FM_ACCCHK_CAPABLE |
2573 2574 DDI_FM_DMACHK_CAPABLE | DDI_FM_ERRCB_CAPABLE);
2574 2575
2575 2576 ddi_fm_init(dip, &nvme->n_fm_cap, &nvme->n_fm_ibc);
2576 2577
2577 2578 if (nvme->n_fm_cap) {
2578 2579 if (nvme->n_fm_cap & DDI_FM_ACCCHK_CAPABLE)
2579 2580 nvme->n_reg_acc_attr.devacc_attr_access =
2580 2581 DDI_FLAGERR_ACC;
2581 2582
2582 2583 if (nvme->n_fm_cap & DDI_FM_DMACHK_CAPABLE) {
2583 2584 nvme->n_prp_dma_attr.dma_attr_flags |= DDI_DMA_FLAGERR;
2584 2585 nvme->n_sgl_dma_attr.dma_attr_flags |= DDI_DMA_FLAGERR;
2585 2586 }
2586 2587
2587 2588 if (DDI_FM_EREPORT_CAP(nvme->n_fm_cap) ||
2588 2589 DDI_FM_ERRCB_CAP(nvme->n_fm_cap))
2589 2590 pci_ereport_setup(dip);
2590 2591
2591 2592 if (DDI_FM_ERRCB_CAP(nvme->n_fm_cap))
2592 2593 ddi_fm_handler_register(dip, nvme_fm_errcb,
2593 2594 (void *)nvme);
2594 2595 }
2595 2596
2596 2597 nvme->n_progress |= NVME_FMA_INIT;
2597 2598
2598 2599 /*
2599 2600 * The spec defines several register sets. Only the controller
2600 2601 * registers (set 1) are currently used.
2601 2602 */
2602 2603 if (ddi_dev_nregs(dip, &nregs) == DDI_FAILURE ||
2603 2604 nregs < 2 ||
2604 2605 ddi_dev_regsize(dip, 1, ®size) == DDI_FAILURE)
2605 2606 goto fail;
2606 2607
2607 2608 if (ddi_regs_map_setup(dip, 1, &nvme->n_regs, 0, regsize,
2608 2609 &nvme->n_reg_acc_attr, &nvme->n_regh) != DDI_SUCCESS) {
2609 2610 dev_err(dip, CE_WARN, "!failed to map regset 1");
2610 2611 goto fail;
2611 2612 }
2612 2613
2613 2614 nvme->n_progress |= NVME_REGS_MAPPED;
2614 2615
2615 2616 /*
2616 2617 * Create taskq for command completion.
2617 2618 */
2618 2619 (void) snprintf(name, sizeof (name), "%s%d_cmd_taskq",
2619 2620 ddi_driver_name(dip), ddi_get_instance(dip));
2620 2621 nvme->n_cmd_taskq = ddi_taskq_create(dip, name, MIN(UINT16_MAX, ncpus),
2621 2622 TASKQ_DEFAULTPRI, 0);
2622 2623 if (nvme->n_cmd_taskq == NULL) {
2623 2624 dev_err(dip, CE_WARN, "!failed to create cmd taskq");
2624 2625 goto fail;
2625 2626 }
2626 2627
2627 2628 /*
2628 2629 * Create PRP DMA cache
2629 2630 */
2630 2631 (void) snprintf(name, sizeof (name), "%s%d_prp_cache",
2631 2632 ddi_driver_name(dip), ddi_get_instance(dip));
2632 2633 nvme->n_prp_cache = kmem_cache_create(name, sizeof (nvme_dma_t),
2633 2634 0, nvme_prp_dma_constructor, nvme_prp_dma_destructor,
2634 2635 NULL, (void *)nvme, NULL, 0);
2635 2636
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2636 2637 if (nvme_init(nvme) != DDI_SUCCESS)
2637 2638 goto fail;
2638 2639
2639 2640 /*
2640 2641 * Attach the blkdev driver for each namespace.
2641 2642 */
2642 2643 for (i = 0; i != nvme->n_namespace_count; i++) {
2643 2644 if (nvme->n_ns[i].ns_ignore)
2644 2645 continue;
2645 2646
2647 + if (!nvme->n_write_cache_present) {
2648 + l_bd_ops.o_sync_cache = NULL;
2649 + }
2650 +
2646 2651 nvme->n_ns[i].ns_bd_hdl = bd_alloc_handle(&nvme->n_ns[i],
2647 - &nvme_bd_ops, &nvme->n_prp_dma_attr, KM_SLEEP);
2652 + &l_bd_ops, &nvme->n_prp_dma_attr, KM_SLEEP);
2648 2653
2649 2654 if (nvme->n_ns[i].ns_bd_hdl == NULL) {
2650 2655 dev_err(dip, CE_WARN,
2651 2656 "!failed to get blkdev handle for namespace %d", i);
2652 2657 goto fail;
2653 2658 }
2654 2659
2655 2660 if (bd_attach_handle(dip, nvme->n_ns[i].ns_bd_hdl)
2656 2661 != DDI_SUCCESS) {
2657 2662 dev_err(dip, CE_WARN,
2658 2663 "!failed to attach blkdev handle for namespace %d",
2659 2664 i);
2660 2665 goto fail;
2661 2666 }
2662 2667 }
2663 2668
2664 2669 return (DDI_SUCCESS);
2665 2670
2666 2671 fail:
2667 2672 /* attach successful anyway so that FMA can retire the device */
2668 2673 if (nvme->n_dead)
2669 2674 return (DDI_SUCCESS);
2670 2675
2671 2676 (void) nvme_detach(dip, DDI_DETACH);
2672 2677
2673 2678 return (DDI_FAILURE);
2674 2679 }
2675 2680
2676 2681 static int
2677 2682 nvme_detach(dev_info_t *dip, ddi_detach_cmd_t cmd)
2678 2683 {
2679 2684 int instance, i;
2680 2685 nvme_t *nvme;
2681 2686
2682 2687 if (cmd != DDI_DETACH)
2683 2688 return (DDI_FAILURE);
2684 2689
2685 2690 instance = ddi_get_instance(dip);
2686 2691
2687 2692 nvme = ddi_get_soft_state(nvme_state, instance);
2688 2693
2689 2694 if (nvme == NULL)
2690 2695 return (DDI_FAILURE);
2691 2696
2692 2697 if (nvme->n_ns) {
2693 2698 for (i = 0; i != nvme->n_namespace_count; i++) {
2694 2699 if (nvme->n_ns[i].ns_bd_hdl) {
2695 2700 (void) bd_detach_handle(
2696 2701 nvme->n_ns[i].ns_bd_hdl);
2697 2702 bd_free_handle(nvme->n_ns[i].ns_bd_hdl);
2698 2703 }
2699 2704
2700 2705 if (nvme->n_ns[i].ns_idns)
2701 2706 kmem_free(nvme->n_ns[i].ns_idns,
2702 2707 sizeof (nvme_identify_nsid_t));
2703 2708 if (nvme->n_ns[i].ns_devid)
2704 2709 strfree(nvme->n_ns[i].ns_devid);
2705 2710 }
2706 2711
2707 2712 kmem_free(nvme->n_ns, sizeof (nvme_namespace_t) *
2708 2713 nvme->n_namespace_count);
2709 2714 }
2710 2715
2711 2716 if (nvme->n_progress & NVME_INTERRUPTS)
2712 2717 nvme_release_interrupts(nvme);
2713 2718
2714 2719 if (nvme->n_cmd_taskq)
2715 2720 ddi_taskq_wait(nvme->n_cmd_taskq);
2716 2721
2717 2722 if (nvme->n_ioq_count > 0) {
2718 2723 for (i = 1; i != nvme->n_ioq_count + 1; i++) {
2719 2724 if (nvme->n_ioq[i] != NULL) {
2720 2725 /* TODO: send destroy queue commands */
2721 2726 nvme_free_qpair(nvme->n_ioq[i]);
2722 2727 }
2723 2728 }
2724 2729
2725 2730 kmem_free(nvme->n_ioq, sizeof (nvme_qpair_t *) *
2726 2731 (nvme->n_ioq_count + 1));
2727 2732 }
2728 2733
2729 2734 if (nvme->n_prp_cache != NULL) {
2730 2735 kmem_cache_destroy(nvme->n_prp_cache);
2731 2736 }
2732 2737
2733 2738 if (nvme->n_progress & NVME_REGS_MAPPED) {
2734 2739 nvme_shutdown(nvme, NVME_CC_SHN_NORMAL, B_FALSE);
2735 2740 (void) nvme_reset(nvme, B_FALSE);
2736 2741 }
2737 2742
2738 2743 if (nvme->n_cmd_taskq)
2739 2744 ddi_taskq_destroy(nvme->n_cmd_taskq);
2740 2745
2741 2746 if (nvme->n_progress & NVME_CTRL_LIMITS)
2742 2747 sema_destroy(&nvme->n_abort_sema);
2743 2748
2744 2749 if (nvme->n_progress & NVME_ADMIN_QUEUE)
2745 2750 nvme_free_qpair(nvme->n_adminq);
2746 2751
2747 2752 if (nvme->n_idctl)
2748 2753 kmem_free(nvme->n_idctl, sizeof (nvme_identify_ctrl_t));
2749 2754
2750 2755 if (nvme->n_progress & NVME_REGS_MAPPED)
2751 2756 ddi_regs_map_free(&nvme->n_regh);
2752 2757
2753 2758 if (nvme->n_progress & NVME_FMA_INIT) {
2754 2759 if (DDI_FM_ERRCB_CAP(nvme->n_fm_cap))
2755 2760 ddi_fm_handler_unregister(nvme->n_dip);
2756 2761
2757 2762 if (DDI_FM_EREPORT_CAP(nvme->n_fm_cap) ||
2758 2763 DDI_FM_ERRCB_CAP(nvme->n_fm_cap))
2759 2764 pci_ereport_teardown(nvme->n_dip);
2760 2765
2761 2766 ddi_fm_fini(nvme->n_dip);
2762 2767 }
2763 2768
2764 2769 if (nvme->n_vendor != NULL)
2765 2770 strfree(nvme->n_vendor);
2766 2771
2767 2772 if (nvme->n_product != NULL)
2768 2773 strfree(nvme->n_product);
2769 2774
2770 2775 ddi_soft_state_free(nvme_state, instance);
2771 2776
2772 2777 return (DDI_SUCCESS);
2773 2778 }
2774 2779
2775 2780 static int
2776 2781 nvme_quiesce(dev_info_t *dip)
2777 2782 {
2778 2783 int instance;
2779 2784 nvme_t *nvme;
2780 2785
2781 2786 instance = ddi_get_instance(dip);
2782 2787
2783 2788 nvme = ddi_get_soft_state(nvme_state, instance);
2784 2789
2785 2790 if (nvme == NULL)
2786 2791 return (DDI_FAILURE);
2787 2792
2788 2793 nvme_shutdown(nvme, NVME_CC_SHN_ABRUPT, B_TRUE);
2789 2794
2790 2795 (void) nvme_reset(nvme, B_TRUE);
2791 2796
2792 2797 return (DDI_FAILURE);
2793 2798 }
2794 2799
2795 2800 static int
2796 2801 nvme_fill_prp(nvme_cmd_t *cmd, bd_xfer_t *xfer)
2797 2802 {
2798 2803 nvme_t *nvme = cmd->nc_nvme;
2799 2804 int nprp_page, nprp;
2800 2805 uint64_t *prp;
2801 2806
2802 2807 if (xfer->x_ndmac == 0)
2803 2808 return (DDI_FAILURE);
2804 2809
2805 2810 cmd->nc_sqe.sqe_dptr.d_prp[0] = xfer->x_dmac.dmac_laddress;
2806 2811 ddi_dma_nextcookie(xfer->x_dmah, &xfer->x_dmac);
2807 2812
2808 2813 if (xfer->x_ndmac == 1) {
2809 2814 cmd->nc_sqe.sqe_dptr.d_prp[1] = 0;
2810 2815 return (DDI_SUCCESS);
2811 2816 } else if (xfer->x_ndmac == 2) {
2812 2817 cmd->nc_sqe.sqe_dptr.d_prp[1] = xfer->x_dmac.dmac_laddress;
2813 2818 return (DDI_SUCCESS);
2814 2819 }
2815 2820
2816 2821 xfer->x_ndmac--;
2817 2822
2818 2823 nprp_page = nvme->n_pagesize / sizeof (uint64_t) - 1;
2819 2824 ASSERT(nprp_page > 0);
2820 2825 nprp = (xfer->x_ndmac + nprp_page - 1) / nprp_page;
2821 2826
2822 2827 /*
2823 2828 * We currently don't support chained PRPs and set up our DMA
2824 2829 * attributes to reflect that. If we still get an I/O request
2825 2830 * that needs a chained PRP something is very wrong.
2826 2831 */
2827 2832 VERIFY(nprp == 1);
2828 2833
2829 2834 cmd->nc_dma = kmem_cache_alloc(nvme->n_prp_cache, KM_SLEEP);
2830 2835 bzero(cmd->nc_dma->nd_memp, cmd->nc_dma->nd_len);
2831 2836
2832 2837 cmd->nc_sqe.sqe_dptr.d_prp[1] = cmd->nc_dma->nd_cookie.dmac_laddress;
2833 2838
2834 2839 /*LINTED: E_PTR_BAD_CAST_ALIGN*/
2835 2840 for (prp = (uint64_t *)cmd->nc_dma->nd_memp;
2836 2841 xfer->x_ndmac > 0;
2837 2842 prp++, xfer->x_ndmac--) {
2838 2843 *prp = xfer->x_dmac.dmac_laddress;
2839 2844 ddi_dma_nextcookie(xfer->x_dmah, &xfer->x_dmac);
2840 2845 }
2841 2846
2842 2847 (void) ddi_dma_sync(cmd->nc_dma->nd_dmah, 0, cmd->nc_dma->nd_len,
2843 2848 DDI_DMA_SYNC_FORDEV);
2844 2849 return (DDI_SUCCESS);
2845 2850 }
2846 2851
2847 2852 static nvme_cmd_t *
2848 2853 nvme_create_nvm_cmd(nvme_namespace_t *ns, uint8_t opc, bd_xfer_t *xfer)
2849 2854 {
2850 2855 nvme_t *nvme = ns->ns_nvme;
2851 2856 nvme_cmd_t *cmd;
2852 2857
2853 2858 /*
2854 2859 * Blkdev only sets BD_XFER_POLL when dumping, so don't sleep.
2855 2860 */
2856 2861 cmd = nvme_alloc_cmd(nvme, (xfer->x_flags & BD_XFER_POLL) ?
2857 2862 KM_NOSLEEP : KM_SLEEP);
2858 2863
2859 2864 if (cmd == NULL)
2860 2865 return (NULL);
2861 2866
2862 2867 cmd->nc_sqe.sqe_opc = opc;
2863 2868 cmd->nc_callback = nvme_bd_xfer_done;
2864 2869 cmd->nc_xfer = xfer;
2865 2870
2866 2871 switch (opc) {
2867 2872 case NVME_OPC_NVM_WRITE:
2868 2873 case NVME_OPC_NVM_READ:
2869 2874 VERIFY(xfer->x_nblks <= 0x10000);
2870 2875
2871 2876 cmd->nc_sqe.sqe_nsid = ns->ns_id;
2872 2877
2873 2878 cmd->nc_sqe.sqe_cdw10 = xfer->x_blkno & 0xffffffffu;
2874 2879 cmd->nc_sqe.sqe_cdw11 = (xfer->x_blkno >> 32);
2875 2880 cmd->nc_sqe.sqe_cdw12 = (uint16_t)(xfer->x_nblks - 1);
2876 2881
2877 2882 if (nvme_fill_prp(cmd, xfer) != DDI_SUCCESS)
2878 2883 goto fail;
2879 2884 break;
2880 2885
2881 2886 case NVME_OPC_NVM_FLUSH:
2882 2887 cmd->nc_sqe.sqe_nsid = ns->ns_id;
2883 2888 break;
2884 2889
2885 2890 default:
2886 2891 goto fail;
2887 2892 }
2888 2893
2889 2894 return (cmd);
2890 2895
2891 2896 fail:
2892 2897 nvme_free_cmd(cmd);
2893 2898 return (NULL);
2894 2899 }
2895 2900
2896 2901 static void
2897 2902 nvme_bd_xfer_done(void *arg)
2898 2903 {
2899 2904 nvme_cmd_t *cmd = arg;
2900 2905 bd_xfer_t *xfer = cmd->nc_xfer;
2901 2906 int error = 0;
2902 2907
2903 2908 error = nvme_check_cmd_status(cmd);
2904 2909 nvme_free_cmd(cmd);
2905 2910
2906 2911 bd_xfer_done(xfer, error);
2907 2912 }
2908 2913
2909 2914 static void
2910 2915 nvme_bd_driveinfo(void *arg, bd_drive_t *drive)
2911 2916 {
2912 2917 nvme_namespace_t *ns = arg;
2913 2918 nvme_t *nvme = ns->ns_nvme;
2914 2919
2915 2920 /*
2916 2921 * blkdev maintains one queue size per instance (namespace),
2917 2922 * but all namespace share the I/O queues.
2918 2923 * TODO: need to figure out a sane default, or use per-NS I/O queues,
2919 2924 * or change blkdev to handle EAGAIN
2920 2925 */
2921 2926 drive->d_qsize = nvme->n_ioq_count * nvme->n_io_queue_len
2922 2927 / nvme->n_namespace_count;
2923 2928
2924 2929 /*
2925 2930 * d_maxxfer is not set, which means the value is taken from the DMA
2926 2931 * attributes specified to bd_alloc_handle.
2927 2932 */
2928 2933
2929 2934 drive->d_removable = B_FALSE;
2930 2935 drive->d_hotpluggable = B_FALSE;
2931 2936
2932 2937 bcopy(ns->ns_eui64, drive->d_eui64, sizeof (drive->d_eui64));
2933 2938 drive->d_target = ns->ns_id;
2934 2939 drive->d_lun = 0;
2935 2940
2936 2941 drive->d_model = nvme->n_idctl->id_model;
2937 2942 drive->d_model_len = sizeof (nvme->n_idctl->id_model);
2938 2943 drive->d_vendor = nvme->n_vendor;
2939 2944 drive->d_vendor_len = strlen(nvme->n_vendor);
2940 2945 drive->d_product = nvme->n_product;
2941 2946 drive->d_product_len = strlen(nvme->n_product);
2942 2947 drive->d_serial = nvme->n_idctl->id_serial;
2943 2948 drive->d_serial_len = sizeof (nvme->n_idctl->id_serial);
2944 2949 drive->d_revision = nvme->n_idctl->id_fwrev;
2945 2950 drive->d_revision_len = sizeof (nvme->n_idctl->id_fwrev);
2946 2951 }
2947 2952
2948 2953 static int
2949 2954 nvme_bd_mediainfo(void *arg, bd_media_t *media)
2950 2955 {
2951 2956 nvme_namespace_t *ns = arg;
2952 2957
2953 2958 media->m_nblks = ns->ns_block_count;
2954 2959 media->m_blksize = ns->ns_block_size;
2955 2960 media->m_readonly = B_FALSE;
2956 2961 media->m_solidstate = B_TRUE;
2957 2962
2958 2963 media->m_pblksize = ns->ns_best_block_size;
2959 2964
2960 2965 return (0);
2961 2966 }
2962 2967
2963 2968 static int
2964 2969 nvme_bd_cmd(nvme_namespace_t *ns, bd_xfer_t *xfer, uint8_t opc)
2965 2970 {
2966 2971 nvme_t *nvme = ns->ns_nvme;
2967 2972 nvme_cmd_t *cmd;
2968 2973
2969 2974 if (nvme->n_dead)
2970 2975 return (EIO);
2971 2976
2972 2977 /* No polling for now */
2973 2978 if (xfer->x_flags & BD_XFER_POLL)
2974 2979 return (EIO);
2975 2980
2976 2981 cmd = nvme_create_nvm_cmd(ns, opc, xfer);
2977 2982 if (cmd == NULL)
2978 2983 return (ENOMEM);
2979 2984
2980 2985 cmd->nc_sqid = (CPU->cpu_id % nvme->n_ioq_count) + 1;
2981 2986 ASSERT(cmd->nc_sqid <= nvme->n_ioq_count);
2982 2987
2983 2988 if (nvme_submit_cmd(nvme->n_ioq[cmd->nc_sqid], cmd)
2984 2989 != DDI_SUCCESS)
2985 2990 return (EAGAIN);
2986 2991
2987 2992 return (0);
2988 2993 }
2989 2994
2990 2995 static int
2991 2996 nvme_bd_read(void *arg, bd_xfer_t *xfer)
2992 2997 {
2993 2998 nvme_namespace_t *ns = arg;
2994 2999
2995 3000 return (nvme_bd_cmd(ns, xfer, NVME_OPC_NVM_READ));
2996 3001 }
2997 3002
2998 3003 static int
2999 3004 nvme_bd_write(void *arg, bd_xfer_t *xfer)
3000 3005 {
3001 3006 nvme_namespace_t *ns = arg;
3002 3007
3003 3008 return (nvme_bd_cmd(ns, xfer, NVME_OPC_NVM_WRITE));
3004 3009 }
3005 3010
3006 3011 static int
3007 3012 nvme_bd_sync(void *arg, bd_xfer_t *xfer)
3008 3013 {
3009 3014 nvme_namespace_t *ns = arg;
3010 3015
3011 3016 if (ns->ns_nvme->n_dead)
3012 3017 return (EIO);
3013 3018
3014 3019 /*
3015 3020 * If the volatile write cache is not present or not enabled the FLUSH
3016 3021 * command is a no-op, so we can take a shortcut here.
3017 3022 */
3018 3023 if (!ns->ns_nvme->n_write_cache_present) {
3019 3024 bd_xfer_done(xfer, ENOTSUP);
3020 3025 return (0);
3021 3026 }
3022 3027
3023 3028 if (!ns->ns_nvme->n_write_cache_enabled) {
3024 3029 bd_xfer_done(xfer, 0);
3025 3030 return (0);
3026 3031 }
3027 3032
3028 3033 return (nvme_bd_cmd(ns, xfer, NVME_OPC_NVM_FLUSH));
3029 3034 }
3030 3035
3031 3036 static int
3032 3037 nvme_bd_devid(void *arg, dev_info_t *devinfo, ddi_devid_t *devid)
3033 3038 {
3034 3039 nvme_namespace_t *ns = arg;
3035 3040
3036 3041 /*LINTED: E_BAD_PTR_CAST_ALIGN*/
3037 3042 if (*(uint64_t *)ns->ns_eui64 != 0) {
3038 3043 return (ddi_devid_init(devinfo, DEVID_SCSI3_WWN,
3039 3044 sizeof (ns->ns_eui64), ns->ns_eui64, devid));
3040 3045 } else {
3041 3046 return (ddi_devid_init(devinfo, DEVID_ENCAP,
3042 3047 strlen(ns->ns_devid), ns->ns_devid, devid));
3043 3048 }
3044 3049 }
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