1 /*
2 * This file and its contents are supplied under the terms of the
3 * Common Development and Distribution License ("CDDL"), version 1.0.
4 * You may only use this file in accordance with the terms of version
5 * 1.0 of the CDDL.
6 *
7 * A full copy of the text of the CDDL should have accompanied this
8 * source. A copy of the CDDL is also available via the Internet at
9 * http://www.illumos.org/license/CDDL.
10 */
11
12 /*
13 * Copyright 2016 Nexenta Systems, Inc. All rights reserved.
14 */
15
16 #ifndef _NVME_VAR_H
17 #define _NVME_VAR_H
18
19 #include <sys/ddi.h>
20 #include <sys/sunddi.h>
21 #include <sys/blkdev.h>
22 #include <sys/taskq_impl.h>
23
24 /*
25 * NVMe driver state
26 */
27
28 #ifdef __cplusplus
29 /* extern "C" { */
30 #endif
31
32 #define NVME_FMA_INIT 0x1
33 #define NVME_REGS_MAPPED 0x2
40 #define NVME_DEFAULT_ADMIN_QUEUE_LEN 256
41 #define NVME_DEFAULT_IO_QUEUE_LEN 1024
42 #define NVME_DEFAULT_ASYNC_EVENT_LIMIT 10
43 #define NVME_MIN_ASYNC_EVENT_LIMIT 1
44
45
46 typedef struct nvme nvme_t;
47 typedef struct nvme_namespace nvme_namespace_t;
48 typedef struct nvme_dma nvme_dma_t;
49 typedef struct nvme_cmd nvme_cmd_t;
50 typedef struct nvme_qpair nvme_qpair_t;
51 typedef struct nvme_task_arg nvme_task_arg_t;
52
53 struct nvme_dma {
54 ddi_dma_handle_t nd_dmah;
55 ddi_acc_handle_t nd_acch;
56 ddi_dma_cookie_t nd_cookie;
57 uint_t nd_ncookie;
58 caddr_t nd_memp;
59 size_t nd_len;
60 };
61
62 struct nvme_cmd {
63 nvme_sqe_t nc_sqe;
64 nvme_cqe_t nc_cqe;
65
66 void (*nc_callback)(void *);
67 bd_xfer_t *nc_xfer;
68 boolean_t nc_completed;
69 uint16_t nc_sqid;
70
71 nvme_dma_t *nc_dma;
72
73 kmutex_t nc_mutex;
74 kcondvar_t nc_cv;
75
76 taskq_ent_t nc_tqent;
77 nvme_t *nc_nvme;
78 };
79
91 uint_t nq_cqhead;
92 uint_t nq_cqtail;
93 uintptr_t nq_cqhdbl;
94
95 nvme_cmd_t **nq_cmd;
96 uint16_t nq_next_cmd;
97 uint_t nq_active_cmds;
98 int nq_phase;
99
100 kmutex_t nq_mutex;
101 };
102
103 struct nvme {
104 dev_info_t *n_dip;
105 int n_progress;
106
107 caddr_t n_regs;
108 ddi_acc_handle_t n_regh;
109
110 kmem_cache_t *n_cmd_cache;
111
112 size_t n_inth_sz;
113 ddi_intr_handle_t *n_inth;
114 int n_intr_cnt;
115 uint_t n_intr_pri;
116 int n_intr_cap;
117 int n_intr_type;
118 int n_intr_types;
119
120 char *n_product;
121 char *n_vendor;
122
123 boolean_t n_dead;
124 boolean_t n_strict_version;
125 boolean_t n_ignore_unknown_vendor_status;
126 uint32_t n_admin_queue_len;
127 uint32_t n_io_queue_len;
128 uint16_t n_async_event_limit;
129 uint16_t n_abort_command_limit;
130 uint64_t n_max_data_transfer_size;
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1 /*
2 * This file and its contents are supplied under the terms of the
3 * Common Development and Distribution License ("CDDL"), version 1.0.
4 * You may only use this file in accordance with the terms of version
5 * 1.0 of the CDDL.
6 *
7 * A full copy of the text of the CDDL should have accompanied this
8 * source. A copy of the CDDL is also available via the Internet at
9 * http://www.illumos.org/license/CDDL.
10 */
11
12 /*
13 * Copyright 2016 Nexenta Systems, Inc. All rights reserved.
14 * Copyright 2016 The MathWorks, Inc. All rights reserved.
15 */
16
17 #ifndef _NVME_VAR_H
18 #define _NVME_VAR_H
19
20 #include <sys/ddi.h>
21 #include <sys/sunddi.h>
22 #include <sys/blkdev.h>
23 #include <sys/taskq_impl.h>
24
25 /*
26 * NVMe driver state
27 */
28
29 #ifdef __cplusplus
30 /* extern "C" { */
31 #endif
32
33 #define NVME_FMA_INIT 0x1
34 #define NVME_REGS_MAPPED 0x2
41 #define NVME_DEFAULT_ADMIN_QUEUE_LEN 256
42 #define NVME_DEFAULT_IO_QUEUE_LEN 1024
43 #define NVME_DEFAULT_ASYNC_EVENT_LIMIT 10
44 #define NVME_MIN_ASYNC_EVENT_LIMIT 1
45
46
47 typedef struct nvme nvme_t;
48 typedef struct nvme_namespace nvme_namespace_t;
49 typedef struct nvme_dma nvme_dma_t;
50 typedef struct nvme_cmd nvme_cmd_t;
51 typedef struct nvme_qpair nvme_qpair_t;
52 typedef struct nvme_task_arg nvme_task_arg_t;
53
54 struct nvme_dma {
55 ddi_dma_handle_t nd_dmah;
56 ddi_acc_handle_t nd_acch;
57 ddi_dma_cookie_t nd_cookie;
58 uint_t nd_ncookie;
59 caddr_t nd_memp;
60 size_t nd_len;
61 boolean_t nd_cached;
62 };
63
64 struct nvme_cmd {
65 nvme_sqe_t nc_sqe;
66 nvme_cqe_t nc_cqe;
67
68 void (*nc_callback)(void *);
69 bd_xfer_t *nc_xfer;
70 boolean_t nc_completed;
71 uint16_t nc_sqid;
72
73 nvme_dma_t *nc_dma;
74
75 kmutex_t nc_mutex;
76 kcondvar_t nc_cv;
77
78 taskq_ent_t nc_tqent;
79 nvme_t *nc_nvme;
80 };
81
93 uint_t nq_cqhead;
94 uint_t nq_cqtail;
95 uintptr_t nq_cqhdbl;
96
97 nvme_cmd_t **nq_cmd;
98 uint16_t nq_next_cmd;
99 uint_t nq_active_cmds;
100 int nq_phase;
101
102 kmutex_t nq_mutex;
103 };
104
105 struct nvme {
106 dev_info_t *n_dip;
107 int n_progress;
108
109 caddr_t n_regs;
110 ddi_acc_handle_t n_regh;
111
112 kmem_cache_t *n_cmd_cache;
113 kmem_cache_t *n_prp_cache;
114
115 size_t n_inth_sz;
116 ddi_intr_handle_t *n_inth;
117 int n_intr_cnt;
118 uint_t n_intr_pri;
119 int n_intr_cap;
120 int n_intr_type;
121 int n_intr_types;
122
123 char *n_product;
124 char *n_vendor;
125
126 boolean_t n_dead;
127 boolean_t n_strict_version;
128 boolean_t n_ignore_unknown_vendor_status;
129 uint32_t n_admin_queue_len;
130 uint32_t n_io_queue_len;
131 uint16_t n_async_event_limit;
132 uint16_t n_abort_command_limit;
133 uint64_t n_max_data_transfer_size;
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