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7364 NVMe driver performance can be improved by caching nvme_dma_t structs for PRPL.
Reviewed by: Hans Rosenfeld <hans.rosenfeld@nexenta.com>
Reviewed by: Robert Mustacchi <rm@joyent.com>
Reviewed by: Garrett D'Amore <garrett@lucera.com>
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--- old/usr/src/uts/common/io/nvme/nvme.c
+++ new/usr/src/uts/common/io/nvme/nvme.c
1 1 /*
2 2 * This file and its contents are supplied under the terms of the
3 3 * Common Development and Distribution License ("CDDL"), version 1.0.
4 4 * You may only use this file in accordance with the terms of version
5 5 * 1.0 of the CDDL.
6 6 *
7 7 * A full copy of the text of the CDDL should have accompanied this
8 8 * source. A copy of the CDDL is also available via the Internet at
9 9 * http://www.illumos.org/license/CDDL.
10 10 */
11 11
12 12 /*
13 13 * Copyright 2016 Nexenta Systems, Inc. All rights reserved.
14 14 * Copyright 2016 Tegile Systems, Inc. All rights reserved.
15 15 * Copyright (c) 2016 The MathWorks, Inc. All rights reserved.
16 16 */
17 17
18 18 /*
19 19 * blkdev driver for NVMe compliant storage devices
20 20 *
21 21 * This driver was written to conform to version 1.0e of the NVMe specification.
22 22 * It may work with newer versions, but that is completely untested and disabled
23 23 * by default.
24 24 *
25 25 * The driver has only been tested on x86 systems and will not work on big-
26 26 * endian systems without changes to the code accessing registers and data
27 27 * structures used by the hardware.
28 28 *
29 29 *
30 30 * Interrupt Usage:
31 31 *
32 32 * The driver will use a FIXED interrupt while configuring the device as the
33 33 * specification requires. Later in the attach process it will switch to MSI-X
34 34 * or MSI if supported. The driver wants to have one interrupt vector per CPU,
35 35 * but it will work correctly if less are available. Interrupts can be shared
36 36 * by queues, the interrupt handler will iterate through the I/O queue array by
37 37 * steps of n_intr_cnt. Usually only the admin queue will share an interrupt
38 38 * with one I/O queue. The interrupt handler will retrieve completed commands
39 39 * from all queues sharing an interrupt vector and will post them to a taskq
40 40 * for completion processing.
41 41 *
42 42 *
43 43 * Command Processing:
44 44 *
45 45 * NVMe devices can have up to 65536 I/O queue pairs, with each queue holding up
46 46 * to 65536 I/O commands. The driver will configure one I/O queue pair per
47 47 * available interrupt vector, with the queue length usually much smaller than
48 48 * the maximum of 65536. If the hardware doesn't provide enough queues, fewer
49 49 * interrupt vectors will be used.
50 50 *
51 51 * Additionally the hardware provides a single special admin queue pair that can
52 52 * hold up to 4096 admin commands.
53 53 *
54 54 * From the hardware perspective both queues of a queue pair are independent,
55 55 * but they share some driver state: the command array (holding pointers to
56 56 * commands currently being processed by the hardware) and the active command
57 57 * counter. Access to the submission side of a queue pair and the shared state
58 58 * is protected by nq_mutex. The completion side of a queue pair does not need
59 59 * that protection apart from its access to the shared state; it is called only
60 60 * in the interrupt handler which does not run concurrently for the same
61 61 * interrupt vector.
62 62 *
63 63 * When a command is submitted to a queue pair the active command counter is
64 64 * incremented and a pointer to the command is stored in the command array. The
65 65 * array index is used as command identifier (CID) in the submission queue
66 66 * entry. Some commands may take a very long time to complete, and if the queue
67 67 * wraps around in that time a submission may find the next array slot to still
68 68 * be used by a long-running command. In this case the array is sequentially
69 69 * searched for the next free slot. The length of the command array is the same
70 70 * as the configured queue length.
71 71 *
72 72 *
73 73 * Namespace Support:
74 74 *
75 75 * NVMe devices can have multiple namespaces, each being a independent data
76 76 * store. The driver supports multiple namespaces and creates a blkdev interface
77 77 * for each namespace found. Namespaces can have various attributes to support
78 78 * thin provisioning and protection information. This driver does not support
79 79 * any of this and ignores namespaces that have these attributes.
80 80 *
81 81 *
82 82 * Blkdev Interface:
83 83 *
84 84 * This driver uses blkdev to do all the heavy lifting involved with presenting
85 85 * a disk device to the system. As a result, the processing of I/O requests is
86 86 * relatively simple as blkdev takes care of partitioning, boundary checks, DMA
87 87 * setup, and splitting of transfers into manageable chunks.
88 88 *
89 89 * I/O requests coming in from blkdev are turned into NVM commands and posted to
90 90 * an I/O queue. The queue is selected by taking the CPU id modulo the number of
91 91 * queues. There is currently no timeout handling of I/O commands.
92 92 *
93 93 * Blkdev also supports querying device/media information and generating a
94 94 * devid. The driver reports the best block size as determined by the namespace
95 95 * format back to blkdev as physical block size to support partition and block
96 96 * alignment. The devid is composed using the device vendor ID, model number,
97 97 * serial number, and the namespace ID.
98 98 *
99 99 *
100 100 * Error Handling:
101 101 *
102 102 * Error handling is currently limited to detecting fatal hardware errors,
103 103 * either by asynchronous events, or synchronously through command status or
104 104 * admin command timeouts. In case of severe errors the device is fenced off,
105 105 * all further requests will return EIO. FMA is then called to fault the device.
106 106 *
107 107 * The hardware has a limit for outstanding asynchronous event requests. Before
108 108 * this limit is known the driver assumes it is at least 1 and posts a single
109 109 * asynchronous request. Later when the limit is known more asynchronous event
110 110 * requests are posted to allow quicker reception of error information. When an
111 111 * asynchronous event is posted by the hardware the driver will parse the error
112 112 * status fields and log information or fault the device, depending on the
113 113 * severity of the asynchronous event. The asynchronous event request is then
114 114 * reused and posted to the admin queue again.
115 115 *
116 116 * On command completion the command status is checked for errors. In case of
117 117 * errors indicating a driver bug the driver panics. Almost all other error
118 118 * status values just cause EIO to be returned.
119 119 *
120 120 * Command timeouts are currently detected for all admin commands except
121 121 * asynchronous event requests. If a command times out and the hardware appears
122 122 * to be healthy the driver attempts to abort the command. If this fails the
123 123 * driver assumes the device to be dead, fences it off, and calls FMA to retire
124 124 * it. In general admin commands are issued at attach time only. No timeout
125 125 * handling of normal I/O commands is presently done.
126 126 *
127 127 * In some cases it may be possible that the ABORT command times out, too. In
128 128 * that case the device is also declared dead and fenced off.
129 129 *
130 130 *
131 131 * Quiesce / Fast Reboot:
132 132 *
133 133 * The driver currently does not support fast reboot. A quiesce(9E) entry point
134 134 * is still provided which is used to send a shutdown notification to the
135 135 * device.
136 136 *
137 137 *
138 138 * Driver Configuration:
139 139 *
140 140 * The following driver properties can be changed to control some aspects of the
141 141 * drivers operation:
142 142 * - strict-version: can be set to 0 to allow devices conforming to newer
143 143 * versions to be used
144 144 * - ignore-unknown-vendor-status: can be set to 1 to not handle any vendor
145 145 * specific command status as a fatal error leading device faulting
146 146 * - admin-queue-len: the maximum length of the admin queue (16-4096)
147 147 * - io-queue-len: the maximum length of the I/O queues (16-65536)
148 148 * - async-event-limit: the maximum number of asynchronous event requests to be
149 149 * posted by the driver
150 150 *
151 151 *
152 152 * TODO:
153 153 * - figure out sane default for I/O queue depth reported to blkdev
154 154 * - polled I/O support to support kernel core dumping
155 155 * - FMA handling of media errors
156 156 * - support for the Volatile Write Cache
157 157 * - support for devices supporting very large I/O requests using chained PRPs
158 158 * - support for querying log pages from user space
159 159 * - support for configuring hardware parameters like interrupt coalescing
160 160 * - support for media formatting and hard partitioning into namespaces
161 161 * - support for big-endian systems
162 162 * - support for fast reboot
163 163 */
164 164
165 165 #include <sys/byteorder.h>
166 166 #ifdef _BIG_ENDIAN
167 167 #error nvme driver needs porting for big-endian platforms
168 168 #endif
169 169
170 170 #include <sys/modctl.h>
171 171 #include <sys/conf.h>
172 172 #include <sys/devops.h>
173 173 #include <sys/ddi.h>
174 174 #include <sys/sunddi.h>
175 175 #include <sys/bitmap.h>
176 176 #include <sys/sysmacros.h>
177 177 #include <sys/param.h>
178 178 #include <sys/varargs.h>
179 179 #include <sys/cpuvar.h>
180 180 #include <sys/disp.h>
181 181 #include <sys/blkdev.h>
182 182 #include <sys/atomic.h>
183 183 #include <sys/archsystm.h>
184 184 #include <sys/sata/sata_hba.h>
185 185
186 186 #include "nvme_reg.h"
187 187 #include "nvme_var.h"
188 188
189 189
190 190 /* NVMe spec version supported */
191 191 static const int nvme_version_major = 1;
192 192 static const int nvme_version_minor = 0;
193 193
194 194 /* tunable for admin command timeout in seconds, default is 1s */
195 195 static volatile int nvme_admin_cmd_timeout = 1;
196 196
197 197 static int nvme_attach(dev_info_t *, ddi_attach_cmd_t);
198 198 static int nvme_detach(dev_info_t *, ddi_detach_cmd_t);
199 199 static int nvme_quiesce(dev_info_t *);
200 200 static int nvme_fm_errcb(dev_info_t *, ddi_fm_error_t *, const void *);
201 201 static int nvme_setup_interrupts(nvme_t *, int, int);
202 202 static void nvme_release_interrupts(nvme_t *);
203 203 static uint_t nvme_intr(caddr_t, caddr_t);
204 204
205 205 static void nvme_shutdown(nvme_t *, int, boolean_t);
206 206 static boolean_t nvme_reset(nvme_t *, boolean_t);
207 207 static int nvme_init(nvme_t *);
208 208 static nvme_cmd_t *nvme_alloc_cmd(nvme_t *, int);
209 209 static void nvme_free_cmd(nvme_cmd_t *);
210 210 static nvme_cmd_t *nvme_create_nvm_cmd(nvme_namespace_t *, uint8_t,
211 211 bd_xfer_t *);
212 212 static int nvme_admin_cmd(nvme_cmd_t *, int);
213 213 static int nvme_submit_cmd(nvme_qpair_t *, nvme_cmd_t *);
214 214 static nvme_cmd_t *nvme_retrieve_cmd(nvme_t *, nvme_qpair_t *);
215 215 static boolean_t nvme_wait_cmd(nvme_cmd_t *, uint_t);
216 216 static void nvme_wakeup_cmd(void *);
217 217 static void nvme_async_event_task(void *);
218 218
219 219 static int nvme_check_unknown_cmd_status(nvme_cmd_t *);
220 220 static int nvme_check_vendor_cmd_status(nvme_cmd_t *);
221 221 static int nvme_check_integrity_cmd_status(nvme_cmd_t *);
222 222 static int nvme_check_specific_cmd_status(nvme_cmd_t *);
223 223 static int nvme_check_generic_cmd_status(nvme_cmd_t *);
224 224 static inline int nvme_check_cmd_status(nvme_cmd_t *);
225 225
226 226 static void nvme_abort_cmd(nvme_cmd_t *);
227 227 static int nvme_async_event(nvme_t *);
228 228 static void *nvme_get_logpage(nvme_t *, uint8_t, ...);
229 229 static void *nvme_identify(nvme_t *, uint32_t);
230 230 static int nvme_set_nqueues(nvme_t *, uint16_t);
231 231
232 232 static void nvme_free_dma(nvme_dma_t *);
233 233 static int nvme_zalloc_dma(nvme_t *, size_t, uint_t, ddi_dma_attr_t *,
234 234 nvme_dma_t **);
235 235 static int nvme_zalloc_queue_dma(nvme_t *, uint32_t, uint16_t, uint_t,
236 236 nvme_dma_t **);
237 237 static void nvme_free_qpair(nvme_qpair_t *);
238 238 static int nvme_alloc_qpair(nvme_t *, uint32_t, nvme_qpair_t **, int);
239 239 static int nvme_create_io_qpair(nvme_t *, nvme_qpair_t *, uint16_t);
240 240
241 241 static inline void nvme_put64(nvme_t *, uintptr_t, uint64_t);
242 242 static inline void nvme_put32(nvme_t *, uintptr_t, uint32_t);
243 243 static inline uint64_t nvme_get64(nvme_t *, uintptr_t);
244 244 static inline uint32_t nvme_get32(nvme_t *, uintptr_t);
245 245
246 246 static boolean_t nvme_check_regs_hdl(nvme_t *);
247 247 static boolean_t nvme_check_dma_hdl(nvme_dma_t *);
248 248
249 249 static int nvme_fill_prp(nvme_cmd_t *, bd_xfer_t *);
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250 250
251 251 static void nvme_bd_xfer_done(void *);
252 252 static void nvme_bd_driveinfo(void *, bd_drive_t *);
253 253 static int nvme_bd_mediainfo(void *, bd_media_t *);
254 254 static int nvme_bd_cmd(nvme_namespace_t *, bd_xfer_t *, uint8_t);
255 255 static int nvme_bd_read(void *, bd_xfer_t *);
256 256 static int nvme_bd_write(void *, bd_xfer_t *);
257 257 static int nvme_bd_sync(void *, bd_xfer_t *);
258 258 static int nvme_bd_devid(void *, dev_info_t *, ddi_devid_t *);
259 259
260 +static int nvme_prp_dma_constructor(void *, void *, int);
261 +static void nvme_prp_dma_destructor(void *, void *);
262 +
260 263 static void nvme_prepare_devid(nvme_t *, uint32_t);
261 264
262 265 static void *nvme_state;
263 266 static kmem_cache_t *nvme_cmd_cache;
264 267
265 268 /*
266 269 * DMA attributes for queue DMA memory
267 270 *
268 271 * Queue DMA memory must be page aligned. The maximum length of a queue is
269 272 * 65536 entries, and an entry can be 64 bytes long.
270 273 */
271 274 static ddi_dma_attr_t nvme_queue_dma_attr = {
272 275 .dma_attr_version = DMA_ATTR_V0,
273 276 .dma_attr_addr_lo = 0,
274 277 .dma_attr_addr_hi = 0xffffffffffffffffULL,
275 278 .dma_attr_count_max = (UINT16_MAX + 1) * sizeof (nvme_sqe_t) - 1,
276 279 .dma_attr_align = 0x1000,
277 280 .dma_attr_burstsizes = 0x7ff,
278 281 .dma_attr_minxfer = 0x1000,
279 282 .dma_attr_maxxfer = (UINT16_MAX + 1) * sizeof (nvme_sqe_t),
280 283 .dma_attr_seg = 0xffffffffffffffffULL,
281 284 .dma_attr_sgllen = 1,
282 285 .dma_attr_granular = 1,
283 286 .dma_attr_flags = 0,
284 287 };
285 288
286 289 /*
287 290 * DMA attributes for transfers using Physical Region Page (PRP) entries
288 291 *
289 292 * A PRP entry describes one page of DMA memory using the page size specified
290 293 * in the controller configuration's memory page size register (CC.MPS). It uses
291 294 * a 64bit base address aligned to this page size. There is no limitation on
292 295 * chaining PRPs together for arbitrarily large DMA transfers.
293 296 */
294 297 static ddi_dma_attr_t nvme_prp_dma_attr = {
295 298 .dma_attr_version = DMA_ATTR_V0,
296 299 .dma_attr_addr_lo = 0,
297 300 .dma_attr_addr_hi = 0xffffffffffffffffULL,
298 301 .dma_attr_count_max = 0xfff,
299 302 .dma_attr_align = 0x1000,
300 303 .dma_attr_burstsizes = 0x7ff,
301 304 .dma_attr_minxfer = 0x1000,
302 305 .dma_attr_maxxfer = 0x1000,
303 306 .dma_attr_seg = 0xfff,
304 307 .dma_attr_sgllen = -1,
305 308 .dma_attr_granular = 1,
306 309 .dma_attr_flags = 0,
307 310 };
308 311
309 312 /*
310 313 * DMA attributes for transfers using scatter/gather lists
311 314 *
312 315 * A SGL entry describes a chunk of DMA memory using a 64bit base address and a
313 316 * 32bit length field. SGL Segment and SGL Last Segment entries require the
314 317 * length to be a multiple of 16 bytes.
315 318 */
316 319 static ddi_dma_attr_t nvme_sgl_dma_attr = {
317 320 .dma_attr_version = DMA_ATTR_V0,
318 321 .dma_attr_addr_lo = 0,
319 322 .dma_attr_addr_hi = 0xffffffffffffffffULL,
320 323 .dma_attr_count_max = 0xffffffffUL,
321 324 .dma_attr_align = 1,
322 325 .dma_attr_burstsizes = 0x7ff,
323 326 .dma_attr_minxfer = 0x10,
324 327 .dma_attr_maxxfer = 0xfffffffffULL,
325 328 .dma_attr_seg = 0xffffffffffffffffULL,
326 329 .dma_attr_sgllen = -1,
327 330 .dma_attr_granular = 0x10,
328 331 .dma_attr_flags = 0
329 332 };
330 333
331 334 static ddi_device_acc_attr_t nvme_reg_acc_attr = {
332 335 .devacc_attr_version = DDI_DEVICE_ATTR_V0,
333 336 .devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC,
334 337 .devacc_attr_dataorder = DDI_STRICTORDER_ACC
335 338 };
336 339
337 340 static struct dev_ops nvme_dev_ops = {
338 341 .devo_rev = DEVO_REV,
339 342 .devo_refcnt = 0,
340 343 .devo_getinfo = ddi_no_info,
341 344 .devo_identify = nulldev,
342 345 .devo_probe = nulldev,
343 346 .devo_attach = nvme_attach,
344 347 .devo_detach = nvme_detach,
345 348 .devo_reset = nodev,
346 349 .devo_cb_ops = NULL,
347 350 .devo_bus_ops = NULL,
348 351 .devo_power = NULL,
349 352 .devo_quiesce = nvme_quiesce,
350 353 };
351 354
352 355 static struct modldrv nvme_modldrv = {
353 356 .drv_modops = &mod_driverops,
354 357 .drv_linkinfo = "NVMe v1.0e",
355 358 .drv_dev_ops = &nvme_dev_ops
356 359 };
357 360
358 361 static struct modlinkage nvme_modlinkage = {
359 362 .ml_rev = MODREV_1,
360 363 .ml_linkage = { &nvme_modldrv, NULL }
361 364 };
362 365
363 366 static bd_ops_t nvme_bd_ops = {
364 367 .o_version = BD_OPS_VERSION_0,
365 368 .o_drive_info = nvme_bd_driveinfo,
366 369 .o_media_info = nvme_bd_mediainfo,
367 370 .o_devid_init = nvme_bd_devid,
368 371 .o_sync_cache = nvme_bd_sync,
369 372 .o_read = nvme_bd_read,
370 373 .o_write = nvme_bd_write,
371 374 };
372 375
373 376 int
374 377 _init(void)
375 378 {
376 379 int error;
377 380
378 381 error = ddi_soft_state_init(&nvme_state, sizeof (nvme_t), 1);
379 382 if (error != DDI_SUCCESS)
380 383 return (error);
381 384
382 385 nvme_cmd_cache = kmem_cache_create("nvme_cmd_cache",
383 386 sizeof (nvme_cmd_t), 64, NULL, NULL, NULL, NULL, NULL, 0);
384 387
385 388 bd_mod_init(&nvme_dev_ops);
386 389
387 390 error = mod_install(&nvme_modlinkage);
388 391 if (error != DDI_SUCCESS) {
389 392 ddi_soft_state_fini(&nvme_state);
390 393 bd_mod_fini(&nvme_dev_ops);
391 394 }
392 395
393 396 return (error);
394 397 }
395 398
396 399 int
397 400 _fini(void)
398 401 {
399 402 int error;
400 403
401 404 error = mod_remove(&nvme_modlinkage);
402 405 if (error == DDI_SUCCESS) {
403 406 ddi_soft_state_fini(&nvme_state);
404 407 kmem_cache_destroy(nvme_cmd_cache);
405 408 bd_mod_fini(&nvme_dev_ops);
406 409 }
407 410
408 411 return (error);
409 412 }
410 413
411 414 int
412 415 _info(struct modinfo *modinfop)
413 416 {
414 417 return (mod_info(&nvme_modlinkage, modinfop));
415 418 }
416 419
417 420 static inline void
418 421 nvme_put64(nvme_t *nvme, uintptr_t reg, uint64_t val)
419 422 {
420 423 ASSERT(((uintptr_t)(nvme->n_regs + reg) & 0x7) == 0);
421 424
422 425 /*LINTED: E_BAD_PTR_CAST_ALIGN*/
423 426 ddi_put64(nvme->n_regh, (uint64_t *)(nvme->n_regs + reg), val);
424 427 }
425 428
426 429 static inline void
427 430 nvme_put32(nvme_t *nvme, uintptr_t reg, uint32_t val)
428 431 {
429 432 ASSERT(((uintptr_t)(nvme->n_regs + reg) & 0x3) == 0);
430 433
431 434 /*LINTED: E_BAD_PTR_CAST_ALIGN*/
432 435 ddi_put32(nvme->n_regh, (uint32_t *)(nvme->n_regs + reg), val);
433 436 }
434 437
435 438 static inline uint64_t
436 439 nvme_get64(nvme_t *nvme, uintptr_t reg)
437 440 {
438 441 uint64_t val;
439 442
440 443 ASSERT(((uintptr_t)(nvme->n_regs + reg) & 0x7) == 0);
441 444
442 445 /*LINTED: E_BAD_PTR_CAST_ALIGN*/
443 446 val = ddi_get64(nvme->n_regh, (uint64_t *)(nvme->n_regs + reg));
444 447
445 448 return (val);
446 449 }
447 450
448 451 static inline uint32_t
449 452 nvme_get32(nvme_t *nvme, uintptr_t reg)
450 453 {
451 454 uint32_t val;
452 455
453 456 ASSERT(((uintptr_t)(nvme->n_regs + reg) & 0x3) == 0);
454 457
455 458 /*LINTED: E_BAD_PTR_CAST_ALIGN*/
456 459 val = ddi_get32(nvme->n_regh, (uint32_t *)(nvme->n_regs + reg));
457 460
458 461 return (val);
459 462 }
460 463
461 464 static boolean_t
462 465 nvme_check_regs_hdl(nvme_t *nvme)
463 466 {
464 467 ddi_fm_error_t error;
465 468
466 469 ddi_fm_acc_err_get(nvme->n_regh, &error, DDI_FME_VERSION);
467 470
468 471 if (error.fme_status != DDI_FM_OK)
469 472 return (B_TRUE);
470 473
471 474 return (B_FALSE);
472 475 }
473 476
474 477 static boolean_t
475 478 nvme_check_dma_hdl(nvme_dma_t *dma)
476 479 {
477 480 ddi_fm_error_t error;
478 481
479 482 if (dma == NULL)
480 483 return (B_FALSE);
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481 484
482 485 ddi_fm_dma_err_get(dma->nd_dmah, &error, DDI_FME_VERSION);
483 486
484 487 if (error.fme_status != DDI_FM_OK)
485 488 return (B_TRUE);
486 489
487 490 return (B_FALSE);
488 491 }
489 492
490 493 static void
491 -nvme_free_dma(nvme_dma_t *dma)
494 +nvme_free_dma_common(nvme_dma_t *dma)
492 495 {
493 496 if (dma->nd_dmah != NULL)
494 497 (void) ddi_dma_unbind_handle(dma->nd_dmah);
495 498 if (dma->nd_acch != NULL)
496 499 ddi_dma_mem_free(&dma->nd_acch);
497 500 if (dma->nd_dmah != NULL)
498 501 ddi_dma_free_handle(&dma->nd_dmah);
499 - kmem_free(dma, sizeof (nvme_dma_t));
500 502 }
501 503
502 -static int
503 -nvme_zalloc_dma(nvme_t *nvme, size_t len, uint_t flags,
504 - ddi_dma_attr_t *dma_attr, nvme_dma_t **ret)
504 +static void
505 +nvme_free_dma(nvme_dma_t *dma)
505 506 {
506 - nvme_dma_t *dma = kmem_zalloc(sizeof (nvme_dma_t), KM_SLEEP);
507 + nvme_free_dma_common(dma);
508 + kmem_free(dma, sizeof (*dma));
509 +}
510 +
511 +static void
512 +nvme_prp_dma_destructor(void *buf, void *private)
513 +{
514 + nvme_dma_t *dma = (nvme_dma_t *)buf;
507 515
516 + nvme_free_dma_common(dma);
517 +}
518 +
519 +static int
520 +nvme_alloc_dma_common(nvme_t *nvme, nvme_dma_t *dma,
521 + size_t len, uint_t flags, ddi_dma_attr_t *dma_attr)
522 +{
508 523 if (ddi_dma_alloc_handle(nvme->n_dip, dma_attr, DDI_DMA_SLEEP, NULL,
509 524 &dma->nd_dmah) != DDI_SUCCESS) {
510 525 /*
511 526 * Due to DDI_DMA_SLEEP this can't be DDI_DMA_NORESOURCES, and
512 527 * the only other possible error is DDI_DMA_BADATTR which
513 528 * indicates a driver bug which should cause a panic.
514 529 */
515 530 dev_err(nvme->n_dip, CE_PANIC,
516 531 "!failed to get DMA handle, check DMA attributes");
517 532 return (DDI_FAILURE);
518 533 }
519 534
520 535 /*
521 536 * ddi_dma_mem_alloc() can only fail when DDI_DMA_NOSLEEP is specified
522 537 * or the flags are conflicting, which isn't the case here.
523 538 */
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524 539 (void) ddi_dma_mem_alloc(dma->nd_dmah, len, &nvme->n_reg_acc_attr,
525 540 DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, NULL, &dma->nd_memp,
526 541 &dma->nd_len, &dma->nd_acch);
527 542
528 543 if (ddi_dma_addr_bind_handle(dma->nd_dmah, NULL, dma->nd_memp,
529 544 dma->nd_len, flags | DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, NULL,
530 545 &dma->nd_cookie, &dma->nd_ncookie) != DDI_DMA_MAPPED) {
531 546 dev_err(nvme->n_dip, CE_WARN,
532 547 "!failed to bind DMA memory");
533 548 atomic_inc_32(&nvme->n_dma_bind_err);
549 + nvme_free_dma_common(dma);
550 + return (DDI_FAILURE);
551 + }
552 +
553 + return (DDI_SUCCESS);
554 +}
555 +
556 +static int
557 +nvme_zalloc_dma(nvme_t *nvme, size_t len, uint_t flags,
558 + ddi_dma_attr_t *dma_attr, nvme_dma_t **ret)
559 +{
560 + nvme_dma_t *dma = kmem_zalloc(sizeof (nvme_dma_t), KM_SLEEP);
561 +
562 + if (nvme_alloc_dma_common(nvme, dma, len, flags, dma_attr) !=
563 + DDI_SUCCESS) {
534 564 *ret = NULL;
535 - nvme_free_dma(dma);
565 + kmem_free(dma, sizeof (nvme_dma_t));
536 566 return (DDI_FAILURE);
537 567 }
538 568
539 569 bzero(dma->nd_memp, dma->nd_len);
540 570
541 571 *ret = dma;
542 572 return (DDI_SUCCESS);
543 573 }
544 574
545 575 static int
576 +nvme_prp_dma_constructor(void *buf, void *private, int flags)
577 +{
578 + nvme_dma_t *dma = (nvme_dma_t *)buf;
579 + nvme_t *nvme = (nvme_t *)private;
580 +
581 + dma->nd_dmah = NULL;
582 + dma->nd_acch = NULL;
583 +
584 + if (nvme_alloc_dma_common(nvme, dma, nvme->n_pagesize,
585 + DDI_DMA_READ, &nvme->n_prp_dma_attr) != DDI_SUCCESS) {
586 + return (-1);
587 + }
588 +
589 + ASSERT(dma->nd_ncookie == 1);
590 +
591 + dma->nd_cached = B_TRUE;
592 +
593 + return (0);
594 +}
595 +
596 +static int
546 597 nvme_zalloc_queue_dma(nvme_t *nvme, uint32_t nentry, uint16_t qe_len,
547 598 uint_t flags, nvme_dma_t **dma)
548 599 {
549 600 uint32_t len = nentry * qe_len;
550 601 ddi_dma_attr_t q_dma_attr = nvme->n_queue_dma_attr;
551 602
552 603 len = roundup(len, nvme->n_pagesize);
553 604
554 605 q_dma_attr.dma_attr_minxfer = len;
555 606
556 607 if (nvme_zalloc_dma(nvme, len, flags, &q_dma_attr, dma)
557 608 != DDI_SUCCESS) {
558 609 dev_err(nvme->n_dip, CE_WARN,
559 610 "!failed to get DMA memory for queue");
560 611 goto fail;
561 612 }
562 613
563 614 if ((*dma)->nd_ncookie != 1) {
564 615 dev_err(nvme->n_dip, CE_WARN,
565 616 "!got too many cookies for queue DMA");
566 617 goto fail;
567 618 }
568 619
569 620 return (DDI_SUCCESS);
570 621
571 622 fail:
572 623 if (*dma) {
573 624 nvme_free_dma(*dma);
574 625 *dma = NULL;
575 626 }
576 627
577 628 return (DDI_FAILURE);
578 629 }
579 630
580 631 static void
581 632 nvme_free_qpair(nvme_qpair_t *qp)
582 633 {
583 634 int i;
584 635
585 636 mutex_destroy(&qp->nq_mutex);
586 637
587 638 if (qp->nq_sqdma != NULL)
588 639 nvme_free_dma(qp->nq_sqdma);
589 640 if (qp->nq_cqdma != NULL)
590 641 nvme_free_dma(qp->nq_cqdma);
591 642
592 643 if (qp->nq_active_cmds > 0)
593 644 for (i = 0; i != qp->nq_nentry; i++)
594 645 if (qp->nq_cmd[i] != NULL)
595 646 nvme_free_cmd(qp->nq_cmd[i]);
596 647
597 648 if (qp->nq_cmd != NULL)
598 649 kmem_free(qp->nq_cmd, sizeof (nvme_cmd_t *) * qp->nq_nentry);
599 650
600 651 kmem_free(qp, sizeof (nvme_qpair_t));
601 652 }
602 653
603 654 static int
604 655 nvme_alloc_qpair(nvme_t *nvme, uint32_t nentry, nvme_qpair_t **nqp,
605 656 int idx)
606 657 {
607 658 nvme_qpair_t *qp = kmem_zalloc(sizeof (*qp), KM_SLEEP);
608 659
609 660 mutex_init(&qp->nq_mutex, NULL, MUTEX_DRIVER,
610 661 DDI_INTR_PRI(nvme->n_intr_pri));
611 662
612 663 if (nvme_zalloc_queue_dma(nvme, nentry, sizeof (nvme_sqe_t),
613 664 DDI_DMA_WRITE, &qp->nq_sqdma) != DDI_SUCCESS)
614 665 goto fail;
615 666
616 667 if (nvme_zalloc_queue_dma(nvme, nentry, sizeof (nvme_cqe_t),
617 668 DDI_DMA_READ, &qp->nq_cqdma) != DDI_SUCCESS)
618 669 goto fail;
619 670
620 671 qp->nq_sq = (nvme_sqe_t *)qp->nq_sqdma->nd_memp;
621 672 qp->nq_cq = (nvme_cqe_t *)qp->nq_cqdma->nd_memp;
622 673 qp->nq_nentry = nentry;
623 674
624 675 qp->nq_sqtdbl = NVME_REG_SQTDBL(nvme, idx);
625 676 qp->nq_cqhdbl = NVME_REG_CQHDBL(nvme, idx);
626 677
627 678 qp->nq_cmd = kmem_zalloc(sizeof (nvme_cmd_t *) * nentry, KM_SLEEP);
628 679 qp->nq_next_cmd = 0;
629 680
630 681 *nqp = qp;
631 682 return (DDI_SUCCESS);
632 683
633 684 fail:
634 685 nvme_free_qpair(qp);
635 686 *nqp = NULL;
636 687
637 688 return (DDI_FAILURE);
638 689 }
639 690
640 691 static nvme_cmd_t *
641 692 nvme_alloc_cmd(nvme_t *nvme, int kmflag)
642 693 {
643 694 nvme_cmd_t *cmd = kmem_cache_alloc(nvme_cmd_cache, kmflag);
644 695
645 696 if (cmd == NULL)
646 697 return (cmd);
647 698
648 699 bzero(cmd, sizeof (nvme_cmd_t));
649 700
650 701 cmd->nc_nvme = nvme;
651 702
652 703 mutex_init(&cmd->nc_mutex, NULL, MUTEX_DRIVER,
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653 704 DDI_INTR_PRI(nvme->n_intr_pri));
654 705 cv_init(&cmd->nc_cv, NULL, CV_DRIVER, NULL);
655 706
656 707 return (cmd);
657 708 }
658 709
659 710 static void
660 711 nvme_free_cmd(nvme_cmd_t *cmd)
661 712 {
662 713 if (cmd->nc_dma) {
663 - nvme_free_dma(cmd->nc_dma);
714 + if (cmd->nc_dma->nd_cached)
715 + kmem_cache_free(cmd->nc_nvme->n_prp_cache,
716 + cmd->nc_dma);
717 + else
718 + nvme_free_dma(cmd->nc_dma);
664 719 cmd->nc_dma = NULL;
665 720 }
666 721
667 722 cv_destroy(&cmd->nc_cv);
668 723 mutex_destroy(&cmd->nc_mutex);
669 724
670 725 kmem_cache_free(nvme_cmd_cache, cmd);
671 726 }
672 727
673 728 static int
674 729 nvme_submit_cmd(nvme_qpair_t *qp, nvme_cmd_t *cmd)
675 730 {
676 731 nvme_reg_sqtdbl_t tail = { 0 };
677 732
678 733 mutex_enter(&qp->nq_mutex);
679 734
680 735 if (qp->nq_active_cmds == qp->nq_nentry) {
681 736 mutex_exit(&qp->nq_mutex);
682 737 return (DDI_FAILURE);
683 738 }
684 739
685 740 cmd->nc_completed = B_FALSE;
686 741
687 742 /*
688 743 * Try to insert the cmd into the active cmd array at the nq_next_cmd
689 744 * slot. If the slot is already occupied advance to the next slot and
690 745 * try again. This can happen for long running commands like async event
691 746 * requests.
692 747 */
693 748 while (qp->nq_cmd[qp->nq_next_cmd] != NULL)
694 749 qp->nq_next_cmd = (qp->nq_next_cmd + 1) % qp->nq_nentry;
695 750 qp->nq_cmd[qp->nq_next_cmd] = cmd;
696 751
697 752 qp->nq_active_cmds++;
698 753
699 754 cmd->nc_sqe.sqe_cid = qp->nq_next_cmd;
700 755 bcopy(&cmd->nc_sqe, &qp->nq_sq[qp->nq_sqtail], sizeof (nvme_sqe_t));
701 756 (void) ddi_dma_sync(qp->nq_sqdma->nd_dmah,
702 757 sizeof (nvme_sqe_t) * qp->nq_sqtail,
703 758 sizeof (nvme_sqe_t), DDI_DMA_SYNC_FORDEV);
704 759 qp->nq_next_cmd = (qp->nq_next_cmd + 1) % qp->nq_nentry;
705 760
706 761 tail.b.sqtdbl_sqt = qp->nq_sqtail = (qp->nq_sqtail + 1) % qp->nq_nentry;
707 762 nvme_put32(cmd->nc_nvme, qp->nq_sqtdbl, tail.r);
708 763
709 764 mutex_exit(&qp->nq_mutex);
710 765 return (DDI_SUCCESS);
711 766 }
712 767
713 768 static nvme_cmd_t *
714 769 nvme_retrieve_cmd(nvme_t *nvme, nvme_qpair_t *qp)
715 770 {
716 771 nvme_reg_cqhdbl_t head = { 0 };
717 772
718 773 nvme_cqe_t *cqe;
719 774 nvme_cmd_t *cmd;
720 775
721 776 (void) ddi_dma_sync(qp->nq_cqdma->nd_dmah, 0,
722 777 sizeof (nvme_cqe_t) * qp->nq_nentry, DDI_DMA_SYNC_FORKERNEL);
723 778
724 779 cqe = &qp->nq_cq[qp->nq_cqhead];
725 780
726 781 /* Check phase tag of CQE. Hardware inverts it for new entries. */
727 782 if (cqe->cqe_sf.sf_p == qp->nq_phase)
728 783 return (NULL);
729 784
730 785 ASSERT(nvme->n_ioq[cqe->cqe_sqid] == qp);
731 786 ASSERT(cqe->cqe_cid < qp->nq_nentry);
732 787
733 788 mutex_enter(&qp->nq_mutex);
734 789 cmd = qp->nq_cmd[cqe->cqe_cid];
735 790 qp->nq_cmd[cqe->cqe_cid] = NULL;
736 791 qp->nq_active_cmds--;
737 792 mutex_exit(&qp->nq_mutex);
738 793
739 794 ASSERT(cmd != NULL);
740 795 ASSERT(cmd->nc_nvme == nvme);
741 796 ASSERT(cmd->nc_sqid == cqe->cqe_sqid);
742 797 ASSERT(cmd->nc_sqe.sqe_cid == cqe->cqe_cid);
743 798 bcopy(cqe, &cmd->nc_cqe, sizeof (nvme_cqe_t));
744 799
745 800 qp->nq_sqhead = cqe->cqe_sqhd;
746 801
747 802 head.b.cqhdbl_cqh = qp->nq_cqhead = (qp->nq_cqhead + 1) % qp->nq_nentry;
748 803
749 804 /* Toggle phase on wrap-around. */
750 805 if (qp->nq_cqhead == 0)
751 806 qp->nq_phase = qp->nq_phase ? 0 : 1;
752 807
753 808 nvme_put32(cmd->nc_nvme, qp->nq_cqhdbl, head.r);
754 809
755 810 return (cmd);
756 811 }
757 812
758 813 static int
759 814 nvme_check_unknown_cmd_status(nvme_cmd_t *cmd)
760 815 {
761 816 nvme_cqe_t *cqe = &cmd->nc_cqe;
762 817
763 818 dev_err(cmd->nc_nvme->n_dip, CE_WARN,
764 819 "!unknown command status received: opc = %x, sqid = %d, cid = %d, "
765 820 "sc = %x, sct = %x, dnr = %d, m = %d", cmd->nc_sqe.sqe_opc,
766 821 cqe->cqe_sqid, cqe->cqe_cid, cqe->cqe_sf.sf_sc, cqe->cqe_sf.sf_sct,
767 822 cqe->cqe_sf.sf_dnr, cqe->cqe_sf.sf_m);
768 823
769 824 bd_error(cmd->nc_xfer, BD_ERR_ILLRQ);
770 825
771 826 if (cmd->nc_nvme->n_strict_version) {
772 827 cmd->nc_nvme->n_dead = B_TRUE;
773 828 ddi_fm_service_impact(cmd->nc_nvme->n_dip, DDI_SERVICE_LOST);
774 829 }
775 830
776 831 return (EIO);
777 832 }
778 833
779 834 static int
780 835 nvme_check_vendor_cmd_status(nvme_cmd_t *cmd)
781 836 {
782 837 nvme_cqe_t *cqe = &cmd->nc_cqe;
783 838
784 839 dev_err(cmd->nc_nvme->n_dip, CE_WARN,
785 840 "!unknown command status received: opc = %x, sqid = %d, cid = %d, "
786 841 "sc = %x, sct = %x, dnr = %d, m = %d", cmd->nc_sqe.sqe_opc,
787 842 cqe->cqe_sqid, cqe->cqe_cid, cqe->cqe_sf.sf_sc, cqe->cqe_sf.sf_sct,
788 843 cqe->cqe_sf.sf_dnr, cqe->cqe_sf.sf_m);
789 844 if (!cmd->nc_nvme->n_ignore_unknown_vendor_status) {
790 845 cmd->nc_nvme->n_dead = B_TRUE;
791 846 ddi_fm_service_impact(cmd->nc_nvme->n_dip, DDI_SERVICE_LOST);
792 847 }
793 848
794 849 return (EIO);
795 850 }
796 851
797 852 static int
798 853 nvme_check_integrity_cmd_status(nvme_cmd_t *cmd)
799 854 {
800 855 nvme_cqe_t *cqe = &cmd->nc_cqe;
801 856
802 857 switch (cqe->cqe_sf.sf_sc) {
803 858 case NVME_CQE_SC_INT_NVM_WRITE:
804 859 /* write fail */
805 860 /* TODO: post ereport */
806 861 bd_error(cmd->nc_xfer, BD_ERR_MEDIA);
807 862 return (EIO);
808 863
809 864 case NVME_CQE_SC_INT_NVM_READ:
810 865 /* read fail */
811 866 /* TODO: post ereport */
812 867 bd_error(cmd->nc_xfer, BD_ERR_MEDIA);
813 868 return (EIO);
814 869
815 870 default:
816 871 return (nvme_check_unknown_cmd_status(cmd));
817 872 }
818 873 }
819 874
820 875 static int
821 876 nvme_check_generic_cmd_status(nvme_cmd_t *cmd)
822 877 {
823 878 nvme_cqe_t *cqe = &cmd->nc_cqe;
824 879
825 880 switch (cqe->cqe_sf.sf_sc) {
826 881 case NVME_CQE_SC_GEN_SUCCESS:
827 882 return (0);
828 883
829 884 /*
830 885 * Errors indicating a bug in the driver should cause a panic.
831 886 */
832 887 case NVME_CQE_SC_GEN_INV_OPC:
833 888 /* Invalid Command Opcode */
834 889 dev_err(cmd->nc_nvme->n_dip, CE_PANIC, "programming error: "
835 890 "invalid opcode in cmd %p", (void *)cmd);
836 891 return (0);
837 892
838 893 case NVME_CQE_SC_GEN_INV_FLD:
839 894 /* Invalid Field in Command */
840 895 dev_err(cmd->nc_nvme->n_dip, CE_PANIC, "programming error: "
841 896 "invalid field in cmd %p", (void *)cmd);
842 897 return (0);
843 898
844 899 case NVME_CQE_SC_GEN_ID_CNFL:
845 900 /* Command ID Conflict */
846 901 dev_err(cmd->nc_nvme->n_dip, CE_PANIC, "programming error: "
847 902 "cmd ID conflict in cmd %p", (void *)cmd);
848 903 return (0);
849 904
850 905 case NVME_CQE_SC_GEN_INV_NS:
851 906 /* Invalid Namespace or Format */
852 907 dev_err(cmd->nc_nvme->n_dip, CE_PANIC, "programming error: "
853 908 "invalid NS/format in cmd %p", (void *)cmd);
854 909 return (0);
855 910
856 911 case NVME_CQE_SC_GEN_NVM_LBA_RANGE:
857 912 /* LBA Out Of Range */
858 913 dev_err(cmd->nc_nvme->n_dip, CE_PANIC, "programming error: "
859 914 "LBA out of range in cmd %p", (void *)cmd);
860 915 return (0);
861 916
862 917 /*
863 918 * Non-fatal errors, handle gracefully.
864 919 */
865 920 case NVME_CQE_SC_GEN_DATA_XFR_ERR:
866 921 /* Data Transfer Error (DMA) */
867 922 /* TODO: post ereport */
868 923 atomic_inc_32(&cmd->nc_nvme->n_data_xfr_err);
869 924 bd_error(cmd->nc_xfer, BD_ERR_NTRDY);
870 925 return (EIO);
871 926
872 927 case NVME_CQE_SC_GEN_INTERNAL_ERR:
873 928 /*
874 929 * Internal Error. The spec (v1.0, section 4.5.1.2) says
875 930 * detailed error information is returned as async event,
876 931 * so we pretty much ignore the error here and handle it
877 932 * in the async event handler.
878 933 */
879 934 atomic_inc_32(&cmd->nc_nvme->n_internal_err);
880 935 bd_error(cmd->nc_xfer, BD_ERR_NTRDY);
881 936 return (EIO);
882 937
883 938 case NVME_CQE_SC_GEN_ABORT_REQUEST:
884 939 /*
885 940 * Command Abort Requested. This normally happens only when a
886 941 * command times out.
887 942 */
888 943 /* TODO: post ereport or change blkdev to handle this? */
889 944 atomic_inc_32(&cmd->nc_nvme->n_abort_rq_err);
890 945 return (ECANCELED);
891 946
892 947 case NVME_CQE_SC_GEN_ABORT_PWRLOSS:
893 948 /* Command Aborted due to Power Loss Notification */
894 949 ddi_fm_service_impact(cmd->nc_nvme->n_dip, DDI_SERVICE_LOST);
895 950 cmd->nc_nvme->n_dead = B_TRUE;
896 951 return (EIO);
897 952
898 953 case NVME_CQE_SC_GEN_ABORT_SQ_DEL:
899 954 /* Command Aborted due to SQ Deletion */
900 955 atomic_inc_32(&cmd->nc_nvme->n_abort_sq_del);
901 956 return (EIO);
902 957
903 958 case NVME_CQE_SC_GEN_NVM_CAP_EXC:
904 959 /* Capacity Exceeded */
905 960 atomic_inc_32(&cmd->nc_nvme->n_nvm_cap_exc);
906 961 bd_error(cmd->nc_xfer, BD_ERR_MEDIA);
907 962 return (EIO);
908 963
909 964 case NVME_CQE_SC_GEN_NVM_NS_NOTRDY:
910 965 /* Namespace Not Ready */
911 966 atomic_inc_32(&cmd->nc_nvme->n_nvm_ns_notrdy);
912 967 bd_error(cmd->nc_xfer, BD_ERR_NTRDY);
913 968 return (EIO);
914 969
915 970 default:
916 971 return (nvme_check_unknown_cmd_status(cmd));
917 972 }
918 973 }
919 974
920 975 static int
921 976 nvme_check_specific_cmd_status(nvme_cmd_t *cmd)
922 977 {
923 978 nvme_cqe_t *cqe = &cmd->nc_cqe;
924 979
925 980 switch (cqe->cqe_sf.sf_sc) {
926 981 case NVME_CQE_SC_SPC_INV_CQ:
927 982 /* Completion Queue Invalid */
928 983 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_CREATE_SQUEUE);
929 984 atomic_inc_32(&cmd->nc_nvme->n_inv_cq_err);
930 985 return (EINVAL);
931 986
932 987 case NVME_CQE_SC_SPC_INV_QID:
933 988 /* Invalid Queue Identifier */
934 989 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_CREATE_SQUEUE ||
935 990 cmd->nc_sqe.sqe_opc == NVME_OPC_DELETE_SQUEUE ||
936 991 cmd->nc_sqe.sqe_opc == NVME_OPC_CREATE_CQUEUE ||
937 992 cmd->nc_sqe.sqe_opc == NVME_OPC_DELETE_CQUEUE);
938 993 atomic_inc_32(&cmd->nc_nvme->n_inv_qid_err);
939 994 return (EINVAL);
940 995
941 996 case NVME_CQE_SC_SPC_MAX_QSZ_EXC:
942 997 /* Max Queue Size Exceeded */
943 998 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_CREATE_SQUEUE ||
944 999 cmd->nc_sqe.sqe_opc == NVME_OPC_CREATE_CQUEUE);
945 1000 atomic_inc_32(&cmd->nc_nvme->n_max_qsz_exc);
946 1001 return (EINVAL);
947 1002
948 1003 case NVME_CQE_SC_SPC_ABRT_CMD_EXC:
949 1004 /* Abort Command Limit Exceeded */
950 1005 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_ABORT);
951 1006 dev_err(cmd->nc_nvme->n_dip, CE_PANIC, "programming error: "
952 1007 "abort command limit exceeded in cmd %p", (void *)cmd);
953 1008 return (0);
954 1009
955 1010 case NVME_CQE_SC_SPC_ASYNC_EVREQ_EXC:
956 1011 /* Async Event Request Limit Exceeded */
957 1012 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_ASYNC_EVENT);
958 1013 dev_err(cmd->nc_nvme->n_dip, CE_PANIC, "programming error: "
959 1014 "async event request limit exceeded in cmd %p",
960 1015 (void *)cmd);
961 1016 return (0);
962 1017
963 1018 case NVME_CQE_SC_SPC_INV_INT_VECT:
964 1019 /* Invalid Interrupt Vector */
965 1020 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_CREATE_CQUEUE);
966 1021 atomic_inc_32(&cmd->nc_nvme->n_inv_int_vect);
967 1022 return (EINVAL);
968 1023
969 1024 case NVME_CQE_SC_SPC_INV_LOG_PAGE:
970 1025 /* Invalid Log Page */
971 1026 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_GET_LOG_PAGE);
972 1027 atomic_inc_32(&cmd->nc_nvme->n_inv_log_page);
973 1028 bd_error(cmd->nc_xfer, BD_ERR_ILLRQ);
974 1029 return (EINVAL);
975 1030
976 1031 case NVME_CQE_SC_SPC_INV_FORMAT:
977 1032 /* Invalid Format */
978 1033 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_NVM_FORMAT);
979 1034 atomic_inc_32(&cmd->nc_nvme->n_inv_format);
980 1035 bd_error(cmd->nc_xfer, BD_ERR_ILLRQ);
981 1036 return (EINVAL);
982 1037
983 1038 case NVME_CQE_SC_SPC_INV_Q_DEL:
984 1039 /* Invalid Queue Deletion */
985 1040 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_DELETE_CQUEUE);
986 1041 atomic_inc_32(&cmd->nc_nvme->n_inv_q_del);
987 1042 return (EINVAL);
988 1043
989 1044 case NVME_CQE_SC_SPC_NVM_CNFL_ATTR:
990 1045 /* Conflicting Attributes */
991 1046 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_NVM_DSET_MGMT ||
992 1047 cmd->nc_sqe.sqe_opc == NVME_OPC_NVM_READ ||
993 1048 cmd->nc_sqe.sqe_opc == NVME_OPC_NVM_WRITE);
994 1049 atomic_inc_32(&cmd->nc_nvme->n_cnfl_attr);
995 1050 bd_error(cmd->nc_xfer, BD_ERR_ILLRQ);
996 1051 return (EINVAL);
997 1052
998 1053 case NVME_CQE_SC_SPC_NVM_INV_PROT:
999 1054 /* Invalid Protection Information */
1000 1055 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_NVM_COMPARE ||
1001 1056 cmd->nc_sqe.sqe_opc == NVME_OPC_NVM_READ ||
1002 1057 cmd->nc_sqe.sqe_opc == NVME_OPC_NVM_WRITE);
1003 1058 atomic_inc_32(&cmd->nc_nvme->n_inv_prot);
1004 1059 bd_error(cmd->nc_xfer, BD_ERR_ILLRQ);
1005 1060 return (EINVAL);
1006 1061
1007 1062 case NVME_CQE_SC_SPC_NVM_READONLY:
1008 1063 /* Write to Read Only Range */
1009 1064 ASSERT(cmd->nc_sqe.sqe_opc == NVME_OPC_NVM_WRITE);
1010 1065 atomic_inc_32(&cmd->nc_nvme->n_readonly);
1011 1066 bd_error(cmd->nc_xfer, BD_ERR_ILLRQ);
1012 1067 return (EROFS);
1013 1068
1014 1069 default:
1015 1070 return (nvme_check_unknown_cmd_status(cmd));
1016 1071 }
1017 1072 }
1018 1073
1019 1074 static inline int
1020 1075 nvme_check_cmd_status(nvme_cmd_t *cmd)
1021 1076 {
1022 1077 nvme_cqe_t *cqe = &cmd->nc_cqe;
1023 1078
1024 1079 /* take a shortcut if everything is alright */
1025 1080 if (cqe->cqe_sf.sf_sct == NVME_CQE_SCT_GENERIC &&
1026 1081 cqe->cqe_sf.sf_sc == NVME_CQE_SC_GEN_SUCCESS)
1027 1082 return (0);
1028 1083
1029 1084 if (cqe->cqe_sf.sf_sct == NVME_CQE_SCT_GENERIC)
1030 1085 return (nvme_check_generic_cmd_status(cmd));
1031 1086 else if (cqe->cqe_sf.sf_sct == NVME_CQE_SCT_SPECIFIC)
1032 1087 return (nvme_check_specific_cmd_status(cmd));
1033 1088 else if (cqe->cqe_sf.sf_sct == NVME_CQE_SCT_INTEGRITY)
1034 1089 return (nvme_check_integrity_cmd_status(cmd));
1035 1090 else if (cqe->cqe_sf.sf_sct == NVME_CQE_SCT_VENDOR)
1036 1091 return (nvme_check_vendor_cmd_status(cmd));
1037 1092
1038 1093 return (nvme_check_unknown_cmd_status(cmd));
1039 1094 }
1040 1095
1041 1096 /*
1042 1097 * nvme_abort_cmd_cb -- replaces nc_callback of aborted commands
1043 1098 *
1044 1099 * This functions takes care of cleaning up aborted commands. The command
1045 1100 * status is checked to catch any fatal errors.
1046 1101 */
1047 1102 static void
1048 1103 nvme_abort_cmd_cb(void *arg)
1049 1104 {
1050 1105 nvme_cmd_t *cmd = arg;
1051 1106
1052 1107 /*
1053 1108 * Grab the command mutex. Once we have it we hold the last reference
1054 1109 * to the command and can safely free it.
1055 1110 */
1056 1111 mutex_enter(&cmd->nc_mutex);
1057 1112 (void) nvme_check_cmd_status(cmd);
1058 1113 mutex_exit(&cmd->nc_mutex);
1059 1114
1060 1115 nvme_free_cmd(cmd);
1061 1116 }
1062 1117
1063 1118 static void
1064 1119 nvme_abort_cmd(nvme_cmd_t *abort_cmd)
1065 1120 {
1066 1121 nvme_t *nvme = abort_cmd->nc_nvme;
1067 1122 nvme_cmd_t *cmd = nvme_alloc_cmd(nvme, KM_SLEEP);
1068 1123 nvme_abort_cmd_t ac = { 0 };
1069 1124
1070 1125 sema_p(&nvme->n_abort_sema);
1071 1126
1072 1127 ac.b.ac_cid = abort_cmd->nc_sqe.sqe_cid;
1073 1128 ac.b.ac_sqid = abort_cmd->nc_sqid;
1074 1129
1075 1130 /*
1076 1131 * Drop the mutex of the aborted command. From this point on
1077 1132 * we must assume that the abort callback has freed the command.
1078 1133 */
1079 1134 mutex_exit(&abort_cmd->nc_mutex);
1080 1135
1081 1136 cmd->nc_sqid = 0;
1082 1137 cmd->nc_sqe.sqe_opc = NVME_OPC_ABORT;
1083 1138 cmd->nc_callback = nvme_wakeup_cmd;
1084 1139 cmd->nc_sqe.sqe_cdw10 = ac.r;
1085 1140
1086 1141 /*
1087 1142 * Send the ABORT to the hardware. The ABORT command will return _after_
1088 1143 * the aborted command has completed (aborted or otherwise).
1089 1144 */
1090 1145 if (nvme_admin_cmd(cmd, nvme_admin_cmd_timeout) != DDI_SUCCESS) {
1091 1146 sema_v(&nvme->n_abort_sema);
1092 1147 dev_err(nvme->n_dip, CE_WARN,
1093 1148 "!nvme_admin_cmd failed for ABORT");
1094 1149 atomic_inc_32(&nvme->n_abort_failed);
1095 1150 return;
1096 1151 }
1097 1152 sema_v(&nvme->n_abort_sema);
1098 1153
1099 1154 if (nvme_check_cmd_status(cmd)) {
1100 1155 dev_err(nvme->n_dip, CE_WARN,
1101 1156 "!ABORT failed with sct = %x, sc = %x",
1102 1157 cmd->nc_cqe.cqe_sf.sf_sct, cmd->nc_cqe.cqe_sf.sf_sc);
1103 1158 atomic_inc_32(&nvme->n_abort_failed);
1104 1159 } else {
1105 1160 atomic_inc_32(&nvme->n_cmd_aborted);
1106 1161 }
1107 1162
1108 1163 nvme_free_cmd(cmd);
1109 1164 }
1110 1165
1111 1166 /*
1112 1167 * nvme_wait_cmd -- wait for command completion or timeout
1113 1168 *
1114 1169 * Returns B_TRUE if the command completed normally.
1115 1170 *
1116 1171 * Returns B_FALSE if the command timed out and an abort was attempted. The
1117 1172 * command mutex will be dropped and the command must be considered freed. The
1118 1173 * freeing of the command is normally done by the abort command callback.
1119 1174 *
1120 1175 * In case of a serious error or a timeout of the abort command the hardware
1121 1176 * will be declared dead and FMA will be notified.
1122 1177 */
1123 1178 static boolean_t
1124 1179 nvme_wait_cmd(nvme_cmd_t *cmd, uint_t sec)
1125 1180 {
1126 1181 clock_t timeout = ddi_get_lbolt() + drv_usectohz(sec * MICROSEC);
1127 1182 nvme_t *nvme = cmd->nc_nvme;
1128 1183 nvme_reg_csts_t csts;
1129 1184
1130 1185 ASSERT(mutex_owned(&cmd->nc_mutex));
1131 1186
1132 1187 while (!cmd->nc_completed) {
1133 1188 if (cv_timedwait(&cmd->nc_cv, &cmd->nc_mutex, timeout) == -1)
1134 1189 break;
1135 1190 }
1136 1191
1137 1192 if (cmd->nc_completed)
1138 1193 return (B_TRUE);
1139 1194
1140 1195 /*
1141 1196 * The command timed out. Change the callback to the cleanup function.
1142 1197 */
1143 1198 cmd->nc_callback = nvme_abort_cmd_cb;
1144 1199
1145 1200 /*
1146 1201 * Check controller for fatal status, any errors associated with the
1147 1202 * register or DMA handle, or for a double timeout (abort command timed
1148 1203 * out). If necessary log a warning and call FMA.
1149 1204 */
1150 1205 csts.r = nvme_get32(nvme, NVME_REG_CSTS);
1151 1206 dev_err(nvme->n_dip, CE_WARN, "!command timeout, "
1152 1207 "OPC = %x, CFS = %d", cmd->nc_sqe.sqe_opc, csts.b.csts_cfs);
1153 1208 atomic_inc_32(&nvme->n_cmd_timeout);
1154 1209
1155 1210 if (csts.b.csts_cfs ||
1156 1211 nvme_check_regs_hdl(nvme) ||
1157 1212 nvme_check_dma_hdl(cmd->nc_dma) ||
1158 1213 cmd->nc_sqe.sqe_opc == NVME_OPC_ABORT) {
1159 1214 ddi_fm_service_impact(nvme->n_dip, DDI_SERVICE_LOST);
1160 1215 nvme->n_dead = B_TRUE;
1161 1216 mutex_exit(&cmd->nc_mutex);
1162 1217 } else {
1163 1218 /*
1164 1219 * Try to abort the command. The command mutex is released by
1165 1220 * nvme_abort_cmd().
1166 1221 * If the abort succeeds it will have freed the aborted command.
1167 1222 * If the abort fails for other reasons we must assume that the
1168 1223 * command may complete at any time, and the callback will free
1169 1224 * it for us.
1170 1225 */
1171 1226 nvme_abort_cmd(cmd);
1172 1227 }
1173 1228
1174 1229 return (B_FALSE);
1175 1230 }
1176 1231
1177 1232 static void
1178 1233 nvme_wakeup_cmd(void *arg)
1179 1234 {
1180 1235 nvme_cmd_t *cmd = arg;
1181 1236
1182 1237 mutex_enter(&cmd->nc_mutex);
1183 1238 /*
1184 1239 * There is a slight chance that this command completed shortly after
1185 1240 * the timeout was hit in nvme_wait_cmd() but before the callback was
1186 1241 * changed. Catch that case here and clean up accordingly.
1187 1242 */
1188 1243 if (cmd->nc_callback == nvme_abort_cmd_cb) {
1189 1244 mutex_exit(&cmd->nc_mutex);
1190 1245 nvme_abort_cmd_cb(cmd);
1191 1246 return;
1192 1247 }
1193 1248
1194 1249 cmd->nc_completed = B_TRUE;
1195 1250 cv_signal(&cmd->nc_cv);
1196 1251 mutex_exit(&cmd->nc_mutex);
1197 1252 }
1198 1253
1199 1254 static void
1200 1255 nvme_async_event_task(void *arg)
1201 1256 {
1202 1257 nvme_cmd_t *cmd = arg;
1203 1258 nvme_t *nvme = cmd->nc_nvme;
1204 1259 nvme_error_log_entry_t *error_log = NULL;
1205 1260 nvme_health_log_t *health_log = NULL;
1206 1261 nvme_async_event_t event;
1207 1262 int ret;
1208 1263
1209 1264 /*
1210 1265 * Check for errors associated with the async request itself. The only
1211 1266 * command-specific error is "async event limit exceeded", which
1212 1267 * indicates a programming error in the driver and causes a panic in
1213 1268 * nvme_check_cmd_status().
1214 1269 *
1215 1270 * Other possible errors are various scenarios where the async request
1216 1271 * was aborted, or internal errors in the device. Internal errors are
1217 1272 * reported to FMA, the command aborts need no special handling here.
1218 1273 */
1219 1274 if (nvme_check_cmd_status(cmd)) {
1220 1275 dev_err(cmd->nc_nvme->n_dip, CE_WARN,
1221 1276 "!async event request returned failure, sct = %x, "
1222 1277 "sc = %x, dnr = %d, m = %d", cmd->nc_cqe.cqe_sf.sf_sct,
1223 1278 cmd->nc_cqe.cqe_sf.sf_sc, cmd->nc_cqe.cqe_sf.sf_dnr,
1224 1279 cmd->nc_cqe.cqe_sf.sf_m);
1225 1280
1226 1281 if (cmd->nc_cqe.cqe_sf.sf_sct == NVME_CQE_SCT_GENERIC &&
1227 1282 cmd->nc_cqe.cqe_sf.sf_sc == NVME_CQE_SC_GEN_INTERNAL_ERR) {
1228 1283 cmd->nc_nvme->n_dead = B_TRUE;
1229 1284 ddi_fm_service_impact(cmd->nc_nvme->n_dip,
1230 1285 DDI_SERVICE_LOST);
1231 1286 }
1232 1287 nvme_free_cmd(cmd);
1233 1288 return;
1234 1289 }
1235 1290
1236 1291
1237 1292 event.r = cmd->nc_cqe.cqe_dw0;
1238 1293
1239 1294 /* Clear CQE and re-submit the async request. */
1240 1295 bzero(&cmd->nc_cqe, sizeof (nvme_cqe_t));
1241 1296 ret = nvme_submit_cmd(nvme->n_adminq, cmd);
1242 1297
1243 1298 if (ret != DDI_SUCCESS) {
1244 1299 dev_err(nvme->n_dip, CE_WARN,
1245 1300 "!failed to resubmit async event request");
1246 1301 atomic_inc_32(&nvme->n_async_resubmit_failed);
1247 1302 nvme_free_cmd(cmd);
1248 1303 }
1249 1304
1250 1305 switch (event.b.ae_type) {
1251 1306 case NVME_ASYNC_TYPE_ERROR:
1252 1307 if (event.b.ae_logpage == NVME_LOGPAGE_ERROR) {
1253 1308 error_log = (nvme_error_log_entry_t *)
1254 1309 nvme_get_logpage(nvme, event.b.ae_logpage);
1255 1310 } else {
1256 1311 dev_err(nvme->n_dip, CE_WARN, "!wrong logpage in "
1257 1312 "async event reply: %d", event.b.ae_logpage);
1258 1313 atomic_inc_32(&nvme->n_wrong_logpage);
1259 1314 }
1260 1315
1261 1316 switch (event.b.ae_info) {
1262 1317 case NVME_ASYNC_ERROR_INV_SQ:
1263 1318 dev_err(nvme->n_dip, CE_PANIC, "programming error: "
1264 1319 "invalid submission queue");
1265 1320 return;
1266 1321
1267 1322 case NVME_ASYNC_ERROR_INV_DBL:
1268 1323 dev_err(nvme->n_dip, CE_PANIC, "programming error: "
1269 1324 "invalid doorbell write value");
1270 1325 return;
1271 1326
1272 1327 case NVME_ASYNC_ERROR_DIAGFAIL:
1273 1328 dev_err(nvme->n_dip, CE_WARN, "!diagnostic failure");
1274 1329 ddi_fm_service_impact(nvme->n_dip, DDI_SERVICE_LOST);
1275 1330 nvme->n_dead = B_TRUE;
1276 1331 atomic_inc_32(&nvme->n_diagfail_event);
1277 1332 break;
1278 1333
1279 1334 case NVME_ASYNC_ERROR_PERSISTENT:
1280 1335 dev_err(nvme->n_dip, CE_WARN, "!persistent internal "
1281 1336 "device error");
1282 1337 ddi_fm_service_impact(nvme->n_dip, DDI_SERVICE_LOST);
1283 1338 nvme->n_dead = B_TRUE;
1284 1339 atomic_inc_32(&nvme->n_persistent_event);
1285 1340 break;
1286 1341
1287 1342 case NVME_ASYNC_ERROR_TRANSIENT:
1288 1343 dev_err(nvme->n_dip, CE_WARN, "!transient internal "
1289 1344 "device error");
1290 1345 /* TODO: send ereport */
1291 1346 atomic_inc_32(&nvme->n_transient_event);
1292 1347 break;
1293 1348
1294 1349 case NVME_ASYNC_ERROR_FW_LOAD:
1295 1350 dev_err(nvme->n_dip, CE_WARN,
1296 1351 "!firmware image load error");
1297 1352 atomic_inc_32(&nvme->n_fw_load_event);
1298 1353 break;
1299 1354 }
1300 1355 break;
1301 1356
1302 1357 case NVME_ASYNC_TYPE_HEALTH:
1303 1358 if (event.b.ae_logpage == NVME_LOGPAGE_HEALTH) {
1304 1359 health_log = (nvme_health_log_t *)
1305 1360 nvme_get_logpage(nvme, event.b.ae_logpage, -1);
1306 1361 } else {
1307 1362 dev_err(nvme->n_dip, CE_WARN, "!wrong logpage in "
1308 1363 "async event reply: %d", event.b.ae_logpage);
1309 1364 atomic_inc_32(&nvme->n_wrong_logpage);
1310 1365 }
1311 1366
1312 1367 switch (event.b.ae_info) {
1313 1368 case NVME_ASYNC_HEALTH_RELIABILITY:
1314 1369 dev_err(nvme->n_dip, CE_WARN,
1315 1370 "!device reliability compromised");
1316 1371 /* TODO: send ereport */
1317 1372 atomic_inc_32(&nvme->n_reliability_event);
1318 1373 break;
1319 1374
1320 1375 case NVME_ASYNC_HEALTH_TEMPERATURE:
1321 1376 dev_err(nvme->n_dip, CE_WARN,
1322 1377 "!temperature above threshold");
1323 1378 /* TODO: send ereport */
1324 1379 atomic_inc_32(&nvme->n_temperature_event);
1325 1380 break;
1326 1381
1327 1382 case NVME_ASYNC_HEALTH_SPARE:
1328 1383 dev_err(nvme->n_dip, CE_WARN,
1329 1384 "!spare space below threshold");
1330 1385 /* TODO: send ereport */
1331 1386 atomic_inc_32(&nvme->n_spare_event);
1332 1387 break;
1333 1388 }
1334 1389 break;
1335 1390
1336 1391 case NVME_ASYNC_TYPE_VENDOR:
1337 1392 dev_err(nvme->n_dip, CE_WARN, "!vendor specific async event "
1338 1393 "received, info = %x, logpage = %x", event.b.ae_info,
1339 1394 event.b.ae_logpage);
1340 1395 atomic_inc_32(&nvme->n_vendor_event);
1341 1396 break;
1342 1397
1343 1398 default:
1344 1399 dev_err(nvme->n_dip, CE_WARN, "!unknown async event received, "
1345 1400 "type = %x, info = %x, logpage = %x", event.b.ae_type,
1346 1401 event.b.ae_info, event.b.ae_logpage);
1347 1402 atomic_inc_32(&nvme->n_unknown_event);
1348 1403 break;
1349 1404 }
1350 1405
1351 1406 if (error_log)
1352 1407 kmem_free(error_log, sizeof (nvme_error_log_entry_t) *
1353 1408 nvme->n_error_log_len);
1354 1409
1355 1410 if (health_log)
1356 1411 kmem_free(health_log, sizeof (nvme_health_log_t));
1357 1412 }
1358 1413
1359 1414 static int
1360 1415 nvme_admin_cmd(nvme_cmd_t *cmd, int sec)
1361 1416 {
1362 1417 int ret;
1363 1418
1364 1419 mutex_enter(&cmd->nc_mutex);
1365 1420 ret = nvme_submit_cmd(cmd->nc_nvme->n_adminq, cmd);
1366 1421
1367 1422 if (ret != DDI_SUCCESS) {
1368 1423 mutex_exit(&cmd->nc_mutex);
1369 1424 dev_err(cmd->nc_nvme->n_dip, CE_WARN,
1370 1425 "!nvme_submit_cmd failed");
1371 1426 atomic_inc_32(&cmd->nc_nvme->n_admin_queue_full);
1372 1427 nvme_free_cmd(cmd);
1373 1428 return (DDI_FAILURE);
1374 1429 }
1375 1430
1376 1431 if (nvme_wait_cmd(cmd, sec) == B_FALSE) {
1377 1432 /*
1378 1433 * The command timed out. An abort command was posted that
1379 1434 * will take care of the cleanup.
1380 1435 */
1381 1436 return (DDI_FAILURE);
1382 1437 }
1383 1438 mutex_exit(&cmd->nc_mutex);
1384 1439
1385 1440 return (DDI_SUCCESS);
1386 1441 }
1387 1442
1388 1443 static int
1389 1444 nvme_async_event(nvme_t *nvme)
1390 1445 {
1391 1446 nvme_cmd_t *cmd = nvme_alloc_cmd(nvme, KM_SLEEP);
1392 1447 int ret;
1393 1448
1394 1449 cmd->nc_sqid = 0;
1395 1450 cmd->nc_sqe.sqe_opc = NVME_OPC_ASYNC_EVENT;
1396 1451 cmd->nc_callback = nvme_async_event_task;
1397 1452
1398 1453 ret = nvme_submit_cmd(nvme->n_adminq, cmd);
1399 1454
1400 1455 if (ret != DDI_SUCCESS) {
1401 1456 dev_err(nvme->n_dip, CE_WARN,
1402 1457 "!nvme_submit_cmd failed for ASYNCHRONOUS EVENT");
1403 1458 nvme_free_cmd(cmd);
1404 1459 return (DDI_FAILURE);
1405 1460 }
1406 1461
1407 1462 return (DDI_SUCCESS);
1408 1463 }
1409 1464
1410 1465 static void *
1411 1466 nvme_get_logpage(nvme_t *nvme, uint8_t logpage, ...)
1412 1467 {
1413 1468 nvme_cmd_t *cmd = nvme_alloc_cmd(nvme, KM_SLEEP);
1414 1469 void *buf = NULL;
1415 1470 nvme_getlogpage_t getlogpage = { 0 };
1416 1471 size_t bufsize;
1417 1472 va_list ap;
1418 1473
1419 1474 va_start(ap, logpage);
1420 1475
1421 1476 cmd->nc_sqid = 0;
1422 1477 cmd->nc_callback = nvme_wakeup_cmd;
1423 1478 cmd->nc_sqe.sqe_opc = NVME_OPC_GET_LOG_PAGE;
1424 1479
1425 1480 getlogpage.b.lp_lid = logpage;
1426 1481
1427 1482 switch (logpage) {
1428 1483 case NVME_LOGPAGE_ERROR:
1429 1484 cmd->nc_sqe.sqe_nsid = (uint32_t)-1;
1430 1485 bufsize = nvme->n_error_log_len *
1431 1486 sizeof (nvme_error_log_entry_t);
1432 1487 break;
1433 1488
1434 1489 case NVME_LOGPAGE_HEALTH:
1435 1490 cmd->nc_sqe.sqe_nsid = va_arg(ap, uint32_t);
1436 1491 bufsize = sizeof (nvme_health_log_t);
1437 1492 break;
1438 1493
1439 1494 case NVME_LOGPAGE_FWSLOT:
1440 1495 cmd->nc_sqe.sqe_nsid = (uint32_t)-1;
1441 1496 bufsize = sizeof (nvme_fwslot_log_t);
1442 1497 break;
1443 1498
1444 1499 default:
1445 1500 dev_err(nvme->n_dip, CE_WARN, "!unknown log page requested: %d",
1446 1501 logpage);
1447 1502 atomic_inc_32(&nvme->n_unknown_logpage);
1448 1503 goto fail;
1449 1504 }
1450 1505
1451 1506 va_end(ap);
1452 1507
1453 1508 getlogpage.b.lp_numd = bufsize / sizeof (uint32_t) - 1;
1454 1509
1455 1510 cmd->nc_sqe.sqe_cdw10 = getlogpage.r;
1456 1511
1457 1512 if (nvme_zalloc_dma(nvme, getlogpage.b.lp_numd * sizeof (uint32_t),
1458 1513 DDI_DMA_READ, &nvme->n_prp_dma_attr, &cmd->nc_dma) != DDI_SUCCESS) {
1459 1514 dev_err(nvme->n_dip, CE_WARN,
1460 1515 "!nvme_zalloc_dma failed for GET LOG PAGE");
1461 1516 goto fail;
1462 1517 }
1463 1518
1464 1519 if (cmd->nc_dma->nd_ncookie > 2) {
1465 1520 dev_err(nvme->n_dip, CE_WARN,
1466 1521 "!too many DMA cookies for GET LOG PAGE");
1467 1522 atomic_inc_32(&nvme->n_too_many_cookies);
1468 1523 goto fail;
1469 1524 }
1470 1525
1471 1526 cmd->nc_sqe.sqe_dptr.d_prp[0] = cmd->nc_dma->nd_cookie.dmac_laddress;
1472 1527 if (cmd->nc_dma->nd_ncookie > 1) {
1473 1528 ddi_dma_nextcookie(cmd->nc_dma->nd_dmah,
1474 1529 &cmd->nc_dma->nd_cookie);
1475 1530 cmd->nc_sqe.sqe_dptr.d_prp[1] =
1476 1531 cmd->nc_dma->nd_cookie.dmac_laddress;
1477 1532 }
1478 1533
1479 1534 if (nvme_admin_cmd(cmd, nvme_admin_cmd_timeout) != DDI_SUCCESS) {
1480 1535 dev_err(nvme->n_dip, CE_WARN,
1481 1536 "!nvme_admin_cmd failed for GET LOG PAGE");
1482 1537 return (NULL);
1483 1538 }
1484 1539
1485 1540 if (nvme_check_cmd_status(cmd)) {
1486 1541 dev_err(nvme->n_dip, CE_WARN,
1487 1542 "!GET LOG PAGE failed with sct = %x, sc = %x",
1488 1543 cmd->nc_cqe.cqe_sf.sf_sct, cmd->nc_cqe.cqe_sf.sf_sc);
1489 1544 goto fail;
1490 1545 }
1491 1546
1492 1547 buf = kmem_alloc(bufsize, KM_SLEEP);
1493 1548 bcopy(cmd->nc_dma->nd_memp, buf, bufsize);
1494 1549
1495 1550 fail:
1496 1551 nvme_free_cmd(cmd);
1497 1552
1498 1553 return (buf);
1499 1554 }
1500 1555
1501 1556 static void *
1502 1557 nvme_identify(nvme_t *nvme, uint32_t nsid)
1503 1558 {
1504 1559 nvme_cmd_t *cmd = nvme_alloc_cmd(nvme, KM_SLEEP);
1505 1560 void *buf = NULL;
1506 1561
1507 1562 cmd->nc_sqid = 0;
1508 1563 cmd->nc_callback = nvme_wakeup_cmd;
1509 1564 cmd->nc_sqe.sqe_opc = NVME_OPC_IDENTIFY;
1510 1565 cmd->nc_sqe.sqe_nsid = nsid;
1511 1566 cmd->nc_sqe.sqe_cdw10 = nsid ? NVME_IDENTIFY_NSID : NVME_IDENTIFY_CTRL;
1512 1567
1513 1568 if (nvme_zalloc_dma(nvme, NVME_IDENTIFY_BUFSIZE, DDI_DMA_READ,
1514 1569 &nvme->n_prp_dma_attr, &cmd->nc_dma) != DDI_SUCCESS) {
1515 1570 dev_err(nvme->n_dip, CE_WARN,
1516 1571 "!nvme_zalloc_dma failed for IDENTIFY");
1517 1572 goto fail;
1518 1573 }
1519 1574
1520 1575 if (cmd->nc_dma->nd_ncookie > 2) {
1521 1576 dev_err(nvme->n_dip, CE_WARN,
1522 1577 "!too many DMA cookies for IDENTIFY");
1523 1578 atomic_inc_32(&nvme->n_too_many_cookies);
1524 1579 goto fail;
1525 1580 }
1526 1581
1527 1582 cmd->nc_sqe.sqe_dptr.d_prp[0] = cmd->nc_dma->nd_cookie.dmac_laddress;
1528 1583 if (cmd->nc_dma->nd_ncookie > 1) {
1529 1584 ddi_dma_nextcookie(cmd->nc_dma->nd_dmah,
1530 1585 &cmd->nc_dma->nd_cookie);
1531 1586 cmd->nc_sqe.sqe_dptr.d_prp[1] =
1532 1587 cmd->nc_dma->nd_cookie.dmac_laddress;
1533 1588 }
1534 1589
1535 1590 if (nvme_admin_cmd(cmd, nvme_admin_cmd_timeout) != DDI_SUCCESS) {
1536 1591 dev_err(nvme->n_dip, CE_WARN,
1537 1592 "!nvme_admin_cmd failed for IDENTIFY");
1538 1593 return (NULL);
1539 1594 }
1540 1595
1541 1596 if (nvme_check_cmd_status(cmd)) {
1542 1597 dev_err(nvme->n_dip, CE_WARN,
1543 1598 "!IDENTIFY failed with sct = %x, sc = %x",
1544 1599 cmd->nc_cqe.cqe_sf.sf_sct, cmd->nc_cqe.cqe_sf.sf_sc);
1545 1600 goto fail;
1546 1601 }
1547 1602
1548 1603 buf = kmem_alloc(NVME_IDENTIFY_BUFSIZE, KM_SLEEP);
1549 1604 bcopy(cmd->nc_dma->nd_memp, buf, NVME_IDENTIFY_BUFSIZE);
1550 1605
1551 1606 fail:
1552 1607 nvme_free_cmd(cmd);
1553 1608
1554 1609 return (buf);
1555 1610 }
1556 1611
1557 1612 static int
1558 1613 nvme_set_nqueues(nvme_t *nvme, uint16_t nqueues)
1559 1614 {
1560 1615 nvme_cmd_t *cmd = nvme_alloc_cmd(nvme, KM_SLEEP);
1561 1616 nvme_nqueue_t nq = { 0 };
1562 1617
1563 1618 nq.b.nq_nsq = nq.b.nq_ncq = nqueues - 1;
1564 1619
1565 1620 cmd->nc_sqid = 0;
1566 1621 cmd->nc_callback = nvme_wakeup_cmd;
1567 1622 cmd->nc_sqe.sqe_opc = NVME_OPC_SET_FEATURES;
1568 1623 cmd->nc_sqe.sqe_cdw10 = NVME_FEAT_NQUEUES;
1569 1624 cmd->nc_sqe.sqe_cdw11 = nq.r;
1570 1625
1571 1626 if (nvme_admin_cmd(cmd, nvme_admin_cmd_timeout) != DDI_SUCCESS) {
1572 1627 dev_err(nvme->n_dip, CE_WARN,
1573 1628 "!nvme_admin_cmd failed for SET FEATURES (NQUEUES)");
1574 1629 return (0);
1575 1630 }
1576 1631
1577 1632 if (nvme_check_cmd_status(cmd)) {
1578 1633 dev_err(nvme->n_dip, CE_WARN,
1579 1634 "!SET FEATURES (NQUEUES) failed with sct = %x, sc = %x",
1580 1635 cmd->nc_cqe.cqe_sf.sf_sct, cmd->nc_cqe.cqe_sf.sf_sc);
1581 1636 nvme_free_cmd(cmd);
1582 1637 return (0);
1583 1638 }
1584 1639
1585 1640 nq.r = cmd->nc_cqe.cqe_dw0;
1586 1641 nvme_free_cmd(cmd);
1587 1642
1588 1643 /*
1589 1644 * Always use the same number of submission and completion queues, and
1590 1645 * never use more than the requested number of queues.
1591 1646 */
1592 1647 return (MIN(nqueues, MIN(nq.b.nq_nsq, nq.b.nq_ncq) + 1));
1593 1648 }
1594 1649
1595 1650 static int
1596 1651 nvme_create_io_qpair(nvme_t *nvme, nvme_qpair_t *qp, uint16_t idx)
1597 1652 {
1598 1653 nvme_cmd_t *cmd = nvme_alloc_cmd(nvme, KM_SLEEP);
1599 1654 nvme_create_queue_dw10_t dw10 = { 0 };
1600 1655 nvme_create_cq_dw11_t c_dw11 = { 0 };
1601 1656 nvme_create_sq_dw11_t s_dw11 = { 0 };
1602 1657
1603 1658 dw10.b.q_qid = idx;
1604 1659 dw10.b.q_qsize = qp->nq_nentry - 1;
1605 1660
1606 1661 c_dw11.b.cq_pc = 1;
1607 1662 c_dw11.b.cq_ien = 1;
1608 1663 c_dw11.b.cq_iv = idx % nvme->n_intr_cnt;
1609 1664
1610 1665 cmd->nc_sqid = 0;
1611 1666 cmd->nc_callback = nvme_wakeup_cmd;
1612 1667 cmd->nc_sqe.sqe_opc = NVME_OPC_CREATE_CQUEUE;
1613 1668 cmd->nc_sqe.sqe_cdw10 = dw10.r;
1614 1669 cmd->nc_sqe.sqe_cdw11 = c_dw11.r;
1615 1670 cmd->nc_sqe.sqe_dptr.d_prp[0] = qp->nq_cqdma->nd_cookie.dmac_laddress;
1616 1671
1617 1672 if (nvme_admin_cmd(cmd, nvme_admin_cmd_timeout) != DDI_SUCCESS) {
1618 1673 dev_err(nvme->n_dip, CE_WARN,
1619 1674 "!nvme_admin_cmd failed for CREATE CQUEUE");
1620 1675 return (DDI_FAILURE);
1621 1676 }
1622 1677
1623 1678 if (nvme_check_cmd_status(cmd)) {
1624 1679 dev_err(nvme->n_dip, CE_WARN,
1625 1680 "!CREATE CQUEUE failed with sct = %x, sc = %x",
1626 1681 cmd->nc_cqe.cqe_sf.sf_sct, cmd->nc_cqe.cqe_sf.sf_sc);
1627 1682 nvme_free_cmd(cmd);
1628 1683 return (DDI_FAILURE);
1629 1684 }
1630 1685
1631 1686 nvme_free_cmd(cmd);
1632 1687
1633 1688 s_dw11.b.sq_pc = 1;
1634 1689 s_dw11.b.sq_cqid = idx;
1635 1690
1636 1691 cmd = nvme_alloc_cmd(nvme, KM_SLEEP);
1637 1692 cmd->nc_sqid = 0;
1638 1693 cmd->nc_callback = nvme_wakeup_cmd;
1639 1694 cmd->nc_sqe.sqe_opc = NVME_OPC_CREATE_SQUEUE;
1640 1695 cmd->nc_sqe.sqe_cdw10 = dw10.r;
1641 1696 cmd->nc_sqe.sqe_cdw11 = s_dw11.r;
1642 1697 cmd->nc_sqe.sqe_dptr.d_prp[0] = qp->nq_sqdma->nd_cookie.dmac_laddress;
1643 1698
1644 1699 if (nvme_admin_cmd(cmd, nvme_admin_cmd_timeout) != DDI_SUCCESS) {
1645 1700 dev_err(nvme->n_dip, CE_WARN,
1646 1701 "!nvme_admin_cmd failed for CREATE SQUEUE");
1647 1702 return (DDI_FAILURE);
1648 1703 }
1649 1704
1650 1705 if (nvme_check_cmd_status(cmd)) {
1651 1706 dev_err(nvme->n_dip, CE_WARN,
1652 1707 "!CREATE SQUEUE failed with sct = %x, sc = %x",
1653 1708 cmd->nc_cqe.cqe_sf.sf_sct, cmd->nc_cqe.cqe_sf.sf_sc);
1654 1709 nvme_free_cmd(cmd);
1655 1710 return (DDI_FAILURE);
1656 1711 }
1657 1712
1658 1713 nvme_free_cmd(cmd);
1659 1714
1660 1715 return (DDI_SUCCESS);
1661 1716 }
1662 1717
1663 1718 static boolean_t
1664 1719 nvme_reset(nvme_t *nvme, boolean_t quiesce)
1665 1720 {
1666 1721 nvme_reg_csts_t csts;
1667 1722 int i;
1668 1723
1669 1724 nvme_put32(nvme, NVME_REG_CC, 0);
1670 1725
1671 1726 csts.r = nvme_get32(nvme, NVME_REG_CSTS);
1672 1727 if (csts.b.csts_rdy == 1) {
1673 1728 nvme_put32(nvme, NVME_REG_CC, 0);
1674 1729 for (i = 0; i != nvme->n_timeout * 10; i++) {
1675 1730 csts.r = nvme_get32(nvme, NVME_REG_CSTS);
1676 1731 if (csts.b.csts_rdy == 0)
1677 1732 break;
1678 1733
1679 1734 if (quiesce)
1680 1735 drv_usecwait(50000);
1681 1736 else
1682 1737 delay(drv_usectohz(50000));
1683 1738 }
1684 1739 }
1685 1740
1686 1741 nvme_put32(nvme, NVME_REG_AQA, 0);
1687 1742 nvme_put32(nvme, NVME_REG_ASQ, 0);
1688 1743 nvme_put32(nvme, NVME_REG_ACQ, 0);
1689 1744
1690 1745 csts.r = nvme_get32(nvme, NVME_REG_CSTS);
1691 1746 return (csts.b.csts_rdy == 0 ? B_TRUE : B_FALSE);
1692 1747 }
1693 1748
1694 1749 static void
1695 1750 nvme_shutdown(nvme_t *nvme, int mode, boolean_t quiesce)
1696 1751 {
1697 1752 nvme_reg_cc_t cc;
1698 1753 nvme_reg_csts_t csts;
1699 1754 int i;
1700 1755
1701 1756 ASSERT(mode == NVME_CC_SHN_NORMAL || mode == NVME_CC_SHN_ABRUPT);
1702 1757
1703 1758 cc.r = nvme_get32(nvme, NVME_REG_CC);
1704 1759 cc.b.cc_shn = mode & 0x3;
1705 1760 nvme_put32(nvme, NVME_REG_CC, cc.r);
1706 1761
1707 1762 for (i = 0; i != 10; i++) {
1708 1763 csts.r = nvme_get32(nvme, NVME_REG_CSTS);
1709 1764 if (csts.b.csts_shst == NVME_CSTS_SHN_COMPLETE)
1710 1765 break;
1711 1766
1712 1767 if (quiesce)
1713 1768 drv_usecwait(100000);
1714 1769 else
1715 1770 delay(drv_usectohz(100000));
1716 1771 }
1717 1772 }
1718 1773
1719 1774
1720 1775 static void
1721 1776 nvme_prepare_devid(nvme_t *nvme, uint32_t nsid)
1722 1777 {
1723 1778 char model[sizeof (nvme->n_idctl->id_model) + 1];
1724 1779 char serial[sizeof (nvme->n_idctl->id_serial) + 1];
1725 1780
1726 1781 bcopy(nvme->n_idctl->id_model, model, sizeof (nvme->n_idctl->id_model));
1727 1782 bcopy(nvme->n_idctl->id_serial, serial,
1728 1783 sizeof (nvme->n_idctl->id_serial));
1729 1784
1730 1785 model[sizeof (nvme->n_idctl->id_model)] = '\0';
1731 1786 serial[sizeof (nvme->n_idctl->id_serial)] = '\0';
1732 1787
1733 1788 (void) snprintf(nvme->n_ns[nsid - 1].ns_devid,
1734 1789 sizeof (nvme->n_ns[0].ns_devid), "%4X-%s-%s-%X",
1735 1790 nvme->n_idctl->id_vid, model, serial, nsid);
1736 1791 }
1737 1792
1738 1793 static int
1739 1794 nvme_init(nvme_t *nvme)
1740 1795 {
1741 1796 nvme_reg_cc_t cc = { 0 };
1742 1797 nvme_reg_aqa_t aqa = { 0 };
1743 1798 nvme_reg_asq_t asq = { 0 };
1744 1799 nvme_reg_acq_t acq = { 0 };
1745 1800 nvme_reg_cap_t cap;
1746 1801 nvme_reg_vs_t vs;
1747 1802 nvme_reg_csts_t csts;
1748 1803 int i = 0;
1749 1804 int nqueues;
1750 1805 char model[sizeof (nvme->n_idctl->id_model) + 1];
1751 1806 char *vendor, *product;
1752 1807
1753 1808 /* Check controller version */
1754 1809 vs.r = nvme_get32(nvme, NVME_REG_VS);
1755 1810 dev_err(nvme->n_dip, CE_CONT, "?NVMe spec version %d.%d",
1756 1811 vs.b.vs_mjr, vs.b.vs_mnr);
1757 1812
1758 1813 if (nvme_version_major < vs.b.vs_mjr ||
1759 1814 (nvme_version_major == vs.b.vs_mjr &&
1760 1815 nvme_version_minor < vs.b.vs_mnr)) {
1761 1816 dev_err(nvme->n_dip, CE_WARN, "!no support for version > %d.%d",
1762 1817 nvme_version_major, nvme_version_minor);
1763 1818 if (nvme->n_strict_version)
1764 1819 goto fail;
1765 1820 }
1766 1821
1767 1822 /* retrieve controller configuration */
1768 1823 cap.r = nvme_get64(nvme, NVME_REG_CAP);
1769 1824
1770 1825 if ((cap.b.cap_css & NVME_CAP_CSS_NVM) == 0) {
1771 1826 dev_err(nvme->n_dip, CE_WARN,
1772 1827 "!NVM command set not supported by hardware");
1773 1828 goto fail;
1774 1829 }
1775 1830
1776 1831 nvme->n_nssr_supported = cap.b.cap_nssrs;
1777 1832 nvme->n_doorbell_stride = 4 << cap.b.cap_dstrd;
1778 1833 nvme->n_timeout = cap.b.cap_to;
1779 1834 nvme->n_arbitration_mechanisms = cap.b.cap_ams;
1780 1835 nvme->n_cont_queues_reqd = cap.b.cap_cqr;
1781 1836 nvme->n_max_queue_entries = cap.b.cap_mqes + 1;
1782 1837
1783 1838 /*
1784 1839 * The MPSMIN and MPSMAX fields in the CAP register use 0 to specify
1785 1840 * the base page size of 4k (1<<12), so add 12 here to get the real
1786 1841 * page size value.
1787 1842 */
1788 1843 nvme->n_pageshift = MIN(MAX(cap.b.cap_mpsmin + 12, PAGESHIFT),
1789 1844 cap.b.cap_mpsmax + 12);
1790 1845 nvme->n_pagesize = 1UL << (nvme->n_pageshift);
1791 1846
1792 1847 /*
1793 1848 * Set up Queue DMA to transfer at least 1 page-aligned page at a time.
1794 1849 */
1795 1850 nvme->n_queue_dma_attr.dma_attr_align = nvme->n_pagesize;
1796 1851 nvme->n_queue_dma_attr.dma_attr_minxfer = nvme->n_pagesize;
1797 1852
1798 1853 /*
1799 1854 * Set up PRP DMA to transfer 1 page-aligned page at a time.
1800 1855 * Maxxfer may be increased after we identified the controller limits.
1801 1856 */
1802 1857 nvme->n_prp_dma_attr.dma_attr_maxxfer = nvme->n_pagesize;
1803 1858 nvme->n_prp_dma_attr.dma_attr_minxfer = nvme->n_pagesize;
1804 1859 nvme->n_prp_dma_attr.dma_attr_align = nvme->n_pagesize;
1805 1860 nvme->n_prp_dma_attr.dma_attr_seg = nvme->n_pagesize - 1;
1806 1861
1807 1862 /*
1808 1863 * Reset controller if it's still in ready state.
1809 1864 */
1810 1865 if (nvme_reset(nvme, B_FALSE) == B_FALSE) {
1811 1866 dev_err(nvme->n_dip, CE_WARN, "!unable to reset controller");
1812 1867 ddi_fm_service_impact(nvme->n_dip, DDI_SERVICE_LOST);
1813 1868 nvme->n_dead = B_TRUE;
1814 1869 goto fail;
1815 1870 }
1816 1871
1817 1872 /*
1818 1873 * Create the admin queue pair.
1819 1874 */
1820 1875 if (nvme_alloc_qpair(nvme, nvme->n_admin_queue_len, &nvme->n_adminq, 0)
1821 1876 != DDI_SUCCESS) {
1822 1877 dev_err(nvme->n_dip, CE_WARN,
1823 1878 "!unable to allocate admin qpair");
1824 1879 goto fail;
1825 1880 }
1826 1881 nvme->n_ioq = kmem_alloc(sizeof (nvme_qpair_t *), KM_SLEEP);
1827 1882 nvme->n_ioq[0] = nvme->n_adminq;
1828 1883
1829 1884 nvme->n_progress |= NVME_ADMIN_QUEUE;
1830 1885
1831 1886 (void) ddi_prop_update_int(DDI_DEV_T_NONE, nvme->n_dip,
1832 1887 "admin-queue-len", nvme->n_admin_queue_len);
1833 1888
1834 1889 aqa.b.aqa_asqs = aqa.b.aqa_acqs = nvme->n_admin_queue_len - 1;
1835 1890 asq = nvme->n_adminq->nq_sqdma->nd_cookie.dmac_laddress;
1836 1891 acq = nvme->n_adminq->nq_cqdma->nd_cookie.dmac_laddress;
1837 1892
1838 1893 ASSERT((asq & (nvme->n_pagesize - 1)) == 0);
1839 1894 ASSERT((acq & (nvme->n_pagesize - 1)) == 0);
1840 1895
1841 1896 nvme_put32(nvme, NVME_REG_AQA, aqa.r);
1842 1897 nvme_put64(nvme, NVME_REG_ASQ, asq);
1843 1898 nvme_put64(nvme, NVME_REG_ACQ, acq);
1844 1899
1845 1900 cc.b.cc_ams = 0; /* use Round-Robin arbitration */
1846 1901 cc.b.cc_css = 0; /* use NVM command set */
1847 1902 cc.b.cc_mps = nvme->n_pageshift - 12;
1848 1903 cc.b.cc_shn = 0; /* no shutdown in progress */
1849 1904 cc.b.cc_en = 1; /* enable controller */
1850 1905 cc.b.cc_iosqes = 6; /* submission queue entry is 2^6 bytes long */
1851 1906 cc.b.cc_iocqes = 4; /* completion queue entry is 2^4 bytes long */
1852 1907
1853 1908 nvme_put32(nvme, NVME_REG_CC, cc.r);
1854 1909
1855 1910 /*
1856 1911 * Wait for the controller to become ready.
1857 1912 */
1858 1913 csts.r = nvme_get32(nvme, NVME_REG_CSTS);
1859 1914 if (csts.b.csts_rdy == 0) {
1860 1915 for (i = 0; i != nvme->n_timeout * 10; i++) {
1861 1916 delay(drv_usectohz(50000));
1862 1917 csts.r = nvme_get32(nvme, NVME_REG_CSTS);
1863 1918
1864 1919 if (csts.b.csts_cfs == 1) {
1865 1920 dev_err(nvme->n_dip, CE_WARN,
1866 1921 "!controller fatal status at init");
1867 1922 ddi_fm_service_impact(nvme->n_dip,
1868 1923 DDI_SERVICE_LOST);
1869 1924 nvme->n_dead = B_TRUE;
1870 1925 goto fail;
1871 1926 }
1872 1927
1873 1928 if (csts.b.csts_rdy == 1)
1874 1929 break;
1875 1930 }
1876 1931 }
1877 1932
1878 1933 if (csts.b.csts_rdy == 0) {
1879 1934 dev_err(nvme->n_dip, CE_WARN, "!controller not ready");
1880 1935 ddi_fm_service_impact(nvme->n_dip, DDI_SERVICE_LOST);
1881 1936 nvme->n_dead = B_TRUE;
1882 1937 goto fail;
1883 1938 }
1884 1939
1885 1940 /*
1886 1941 * Assume an abort command limit of 1. We'll destroy and re-init
1887 1942 * that later when we know the true abort command limit.
1888 1943 */
1889 1944 sema_init(&nvme->n_abort_sema, 1, NULL, SEMA_DRIVER, NULL);
1890 1945
1891 1946 /*
1892 1947 * Setup initial interrupt for admin queue.
1893 1948 */
1894 1949 if ((nvme_setup_interrupts(nvme, DDI_INTR_TYPE_MSIX, 1)
1895 1950 != DDI_SUCCESS) &&
1896 1951 (nvme_setup_interrupts(nvme, DDI_INTR_TYPE_MSI, 1)
1897 1952 != DDI_SUCCESS) &&
1898 1953 (nvme_setup_interrupts(nvme, DDI_INTR_TYPE_FIXED, 1)
1899 1954 != DDI_SUCCESS)) {
1900 1955 dev_err(nvme->n_dip, CE_WARN,
1901 1956 "!failed to setup initial interrupt");
1902 1957 goto fail;
1903 1958 }
1904 1959
1905 1960 /*
1906 1961 * Post an asynchronous event command to catch errors.
1907 1962 */
1908 1963 if (nvme_async_event(nvme) != DDI_SUCCESS) {
1909 1964 dev_err(nvme->n_dip, CE_WARN,
1910 1965 "!failed to post async event");
1911 1966 goto fail;
1912 1967 }
1913 1968
1914 1969 /*
1915 1970 * Identify Controller
1916 1971 */
1917 1972 nvme->n_idctl = nvme_identify(nvme, 0);
1918 1973 if (nvme->n_idctl == NULL) {
1919 1974 dev_err(nvme->n_dip, CE_WARN,
1920 1975 "!failed to identify controller");
1921 1976 goto fail;
1922 1977 }
1923 1978
1924 1979 /*
1925 1980 * Get Vendor & Product ID
1926 1981 */
1927 1982 bcopy(nvme->n_idctl->id_model, model, sizeof (nvme->n_idctl->id_model));
1928 1983 model[sizeof (nvme->n_idctl->id_model)] = '\0';
1929 1984 sata_split_model(model, &vendor, &product);
1930 1985
1931 1986 if (vendor == NULL)
1932 1987 nvme->n_vendor = strdup("NVMe");
1933 1988 else
1934 1989 nvme->n_vendor = strdup(vendor);
1935 1990
1936 1991 nvme->n_product = strdup(product);
1937 1992
1938 1993 /*
1939 1994 * Get controller limits.
1940 1995 */
1941 1996 nvme->n_async_event_limit = MAX(NVME_MIN_ASYNC_EVENT_LIMIT,
1942 1997 MIN(nvme->n_admin_queue_len / 10,
1943 1998 MIN(nvme->n_idctl->id_aerl + 1, nvme->n_async_event_limit)));
1944 1999
1945 2000 (void) ddi_prop_update_int(DDI_DEV_T_NONE, nvme->n_dip,
1946 2001 "async-event-limit", nvme->n_async_event_limit);
1947 2002
1948 2003 nvme->n_abort_command_limit = nvme->n_idctl->id_acl + 1;
1949 2004
1950 2005 /*
1951 2006 * Reinitialize the semaphore with the true abort command limit
1952 2007 * supported by the hardware. It's not necessary to disable interrupts
1953 2008 * as only command aborts use the semaphore, and no commands are
1954 2009 * executed or aborted while we're here.
1955 2010 */
1956 2011 sema_destroy(&nvme->n_abort_sema);
1957 2012 sema_init(&nvme->n_abort_sema, nvme->n_abort_command_limit - 1, NULL,
1958 2013 SEMA_DRIVER, NULL);
1959 2014
1960 2015 nvme->n_progress |= NVME_CTRL_LIMITS;
1961 2016
1962 2017 if (nvme->n_idctl->id_mdts == 0)
1963 2018 nvme->n_max_data_transfer_size = nvme->n_pagesize * 65536;
1964 2019 else
1965 2020 nvme->n_max_data_transfer_size =
1966 2021 1ull << (nvme->n_pageshift + nvme->n_idctl->id_mdts);
1967 2022
1968 2023 nvme->n_error_log_len = nvme->n_idctl->id_elpe + 1;
1969 2024
1970 2025 /*
1971 2026 * Limit n_max_data_transfer_size to what we can handle in one PRP.
1972 2027 * Chained PRPs are currently unsupported.
1973 2028 *
1974 2029 * This is a no-op on hardware which doesn't support a transfer size
1975 2030 * big enough to require chained PRPs.
1976 2031 */
1977 2032 nvme->n_max_data_transfer_size = MIN(nvme->n_max_data_transfer_size,
1978 2033 (nvme->n_pagesize / sizeof (uint64_t) * nvme->n_pagesize));
1979 2034
1980 2035 nvme->n_prp_dma_attr.dma_attr_maxxfer = nvme->n_max_data_transfer_size;
1981 2036
1982 2037 /*
1983 2038 * Make sure the minimum/maximum queue entry sizes are not
1984 2039 * larger/smaller than the default.
1985 2040 */
1986 2041
1987 2042 if (((1 << nvme->n_idctl->id_sqes.qes_min) > sizeof (nvme_sqe_t)) ||
1988 2043 ((1 << nvme->n_idctl->id_sqes.qes_max) < sizeof (nvme_sqe_t)) ||
1989 2044 ((1 << nvme->n_idctl->id_cqes.qes_min) > sizeof (nvme_cqe_t)) ||
1990 2045 ((1 << nvme->n_idctl->id_cqes.qes_max) < sizeof (nvme_cqe_t)))
1991 2046 goto fail;
1992 2047
1993 2048 /*
1994 2049 * Check for the presence of a Volatile Write Cache. If present,
1995 2050 * enable it by default.
1996 2051 */
1997 2052 if (nvme->n_idctl->id_vwc.vwc_present == 0) {
1998 2053 nvme->n_volatile_write_cache_enabled = B_FALSE;
1999 2054 nvme_bd_ops.o_sync_cache = NULL;
2000 2055 } else {
2001 2056 /*
2002 2057 * TODO: send SET FEATURES to enable VWC
2003 2058 * (have no hardware to test this)
2004 2059 */
2005 2060 nvme->n_volatile_write_cache_enabled = B_FALSE;
2006 2061 nvme_bd_ops.o_sync_cache = NULL;
2007 2062 }
2008 2063
2009 2064 /*
2010 2065 * Grab a copy of all mandatory log pages.
2011 2066 *
2012 2067 * TODO: should go away once user space tool exists to print logs
2013 2068 */
2014 2069 nvme->n_error_log = (nvme_error_log_entry_t *)
2015 2070 nvme_get_logpage(nvme, NVME_LOGPAGE_ERROR);
2016 2071 nvme->n_health_log = (nvme_health_log_t *)
2017 2072 nvme_get_logpage(nvme, NVME_LOGPAGE_HEALTH, -1);
2018 2073 nvme->n_fwslot_log = (nvme_fwslot_log_t *)
2019 2074 nvme_get_logpage(nvme, NVME_LOGPAGE_FWSLOT);
2020 2075
2021 2076 /*
2022 2077 * Identify Namespaces
2023 2078 */
2024 2079 nvme->n_namespace_count = nvme->n_idctl->id_nn;
2025 2080 nvme->n_ns = kmem_zalloc(sizeof (nvme_namespace_t) *
2026 2081 nvme->n_namespace_count, KM_SLEEP);
2027 2082
2028 2083 for (i = 0; i != nvme->n_namespace_count; i++) {
2029 2084 nvme_identify_nsid_t *idns;
2030 2085 int last_rp;
2031 2086
2032 2087 nvme->n_ns[i].ns_nvme = nvme;
2033 2088 nvme->n_ns[i].ns_idns = idns = nvme_identify(nvme, i + 1);
2034 2089
2035 2090 if (idns == NULL) {
2036 2091 dev_err(nvme->n_dip, CE_WARN,
2037 2092 "!failed to identify namespace %d", i + 1);
2038 2093 goto fail;
2039 2094 }
2040 2095
2041 2096 nvme->n_ns[i].ns_id = i + 1;
2042 2097 nvme->n_ns[i].ns_block_count = idns->id_nsize;
2043 2098 nvme->n_ns[i].ns_block_size =
2044 2099 1 << idns->id_lbaf[idns->id_flbas.lba_format].lbaf_lbads;
2045 2100 nvme->n_ns[i].ns_best_block_size = nvme->n_ns[i].ns_block_size;
2046 2101
2047 2102 nvme_prepare_devid(nvme, nvme->n_ns[i].ns_id);
2048 2103
2049 2104 /*
2050 2105 * Find the LBA format with no metadata and the best relative
2051 2106 * performance. A value of 3 means "degraded", 0 is best.
2052 2107 */
2053 2108 last_rp = 3;
2054 2109 for (int j = 0; j <= idns->id_nlbaf; j++) {
2055 2110 if (idns->id_lbaf[j].lbaf_lbads == 0)
2056 2111 break;
2057 2112 if (idns->id_lbaf[j].lbaf_ms != 0)
2058 2113 continue;
2059 2114 if (idns->id_lbaf[j].lbaf_rp >= last_rp)
2060 2115 continue;
2061 2116 last_rp = idns->id_lbaf[j].lbaf_rp;
2062 2117 nvme->n_ns[i].ns_best_block_size =
2063 2118 1 << idns->id_lbaf[j].lbaf_lbads;
2064 2119 }
2065 2120
2066 2121 /*
2067 2122 * We currently don't support namespaces that use either:
2068 2123 * - thin provisioning
2069 2124 * - protection information
2070 2125 */
2071 2126 if (idns->id_nsfeat.f_thin ||
2072 2127 idns->id_dps.dp_pinfo) {
2073 2128 dev_err(nvme->n_dip, CE_WARN,
2074 2129 "!ignoring namespace %d, unsupported features: "
2075 2130 "thin = %d, pinfo = %d", i + 1,
2076 2131 idns->id_nsfeat.f_thin, idns->id_dps.dp_pinfo);
2077 2132 nvme->n_ns[i].ns_ignore = B_TRUE;
2078 2133 }
2079 2134 }
2080 2135
2081 2136 /*
2082 2137 * Try to set up MSI/MSI-X interrupts.
2083 2138 */
2084 2139 if ((nvme->n_intr_types & (DDI_INTR_TYPE_MSI | DDI_INTR_TYPE_MSIX))
2085 2140 != 0) {
2086 2141 nvme_release_interrupts(nvme);
2087 2142
2088 2143 nqueues = MIN(UINT16_MAX, ncpus);
2089 2144
2090 2145 if ((nvme_setup_interrupts(nvme, DDI_INTR_TYPE_MSIX,
2091 2146 nqueues) != DDI_SUCCESS) &&
2092 2147 (nvme_setup_interrupts(nvme, DDI_INTR_TYPE_MSI,
2093 2148 nqueues) != DDI_SUCCESS)) {
2094 2149 dev_err(nvme->n_dip, CE_WARN,
2095 2150 "!failed to setup MSI/MSI-X interrupts");
2096 2151 goto fail;
2097 2152 }
2098 2153 }
2099 2154
2100 2155 nqueues = nvme->n_intr_cnt;
2101 2156
2102 2157 /*
2103 2158 * Create I/O queue pairs.
2104 2159 */
2105 2160 nvme->n_ioq_count = nvme_set_nqueues(nvme, nqueues);
2106 2161 if (nvme->n_ioq_count == 0) {
2107 2162 dev_err(nvme->n_dip, CE_WARN,
2108 2163 "!failed to set number of I/O queues to %d", nqueues);
2109 2164 goto fail;
2110 2165 }
2111 2166
2112 2167 /*
2113 2168 * Reallocate I/O queue array
2114 2169 */
2115 2170 kmem_free(nvme->n_ioq, sizeof (nvme_qpair_t *));
2116 2171 nvme->n_ioq = kmem_zalloc(sizeof (nvme_qpair_t *) *
2117 2172 (nvme->n_ioq_count + 1), KM_SLEEP);
2118 2173 nvme->n_ioq[0] = nvme->n_adminq;
2119 2174
2120 2175 /*
2121 2176 * If we got less queues than we asked for we might as well give
2122 2177 * some of the interrupt vectors back to the system.
2123 2178 */
2124 2179 if (nvme->n_ioq_count < nqueues) {
2125 2180 nvme_release_interrupts(nvme);
2126 2181
2127 2182 if (nvme_setup_interrupts(nvme, nvme->n_intr_type,
2128 2183 nvme->n_ioq_count) != DDI_SUCCESS) {
2129 2184 dev_err(nvme->n_dip, CE_WARN,
2130 2185 "!failed to reduce number of interrupts");
2131 2186 goto fail;
2132 2187 }
2133 2188 }
2134 2189
2135 2190 /*
2136 2191 * Alloc & register I/O queue pairs
2137 2192 */
2138 2193 nvme->n_io_queue_len =
2139 2194 MIN(nvme->n_io_queue_len, nvme->n_max_queue_entries);
2140 2195 (void) ddi_prop_update_int(DDI_DEV_T_NONE, nvme->n_dip, "io-queue-len",
2141 2196 nvme->n_io_queue_len);
2142 2197
2143 2198 for (i = 1; i != nvme->n_ioq_count + 1; i++) {
2144 2199 if (nvme_alloc_qpair(nvme, nvme->n_io_queue_len,
2145 2200 &nvme->n_ioq[i], i) != DDI_SUCCESS) {
2146 2201 dev_err(nvme->n_dip, CE_WARN,
2147 2202 "!unable to allocate I/O qpair %d", i);
2148 2203 goto fail;
2149 2204 }
2150 2205
2151 2206 if (nvme_create_io_qpair(nvme, nvme->n_ioq[i], i)
2152 2207 != DDI_SUCCESS) {
2153 2208 dev_err(nvme->n_dip, CE_WARN,
2154 2209 "!unable to create I/O qpair %d", i);
2155 2210 goto fail;
2156 2211 }
2157 2212 }
2158 2213
2159 2214 /*
2160 2215 * Post more asynchronous events commands to reduce event reporting
2161 2216 * latency as suggested by the spec.
2162 2217 */
2163 2218 for (i = 1; i != nvme->n_async_event_limit; i++) {
2164 2219 if (nvme_async_event(nvme) != DDI_SUCCESS) {
2165 2220 dev_err(nvme->n_dip, CE_WARN,
2166 2221 "!failed to post async event %d", i);
2167 2222 goto fail;
2168 2223 }
2169 2224 }
2170 2225
2171 2226 return (DDI_SUCCESS);
2172 2227
2173 2228 fail:
2174 2229 (void) nvme_reset(nvme, B_FALSE);
2175 2230 return (DDI_FAILURE);
2176 2231 }
2177 2232
2178 2233 static uint_t
2179 2234 nvme_intr(caddr_t arg1, caddr_t arg2)
2180 2235 {
2181 2236 /*LINTED: E_PTR_BAD_CAST_ALIGN*/
2182 2237 nvme_t *nvme = (nvme_t *)arg1;
2183 2238 int inum = (int)(uintptr_t)arg2;
2184 2239 int ccnt = 0;
2185 2240 int qnum;
2186 2241 nvme_cmd_t *cmd;
2187 2242
2188 2243 if (inum >= nvme->n_intr_cnt)
2189 2244 return (DDI_INTR_UNCLAIMED);
2190 2245
2191 2246 /*
2192 2247 * The interrupt vector a queue uses is calculated as queue_idx %
2193 2248 * intr_cnt in nvme_create_io_qpair(). Iterate through the queue array
2194 2249 * in steps of n_intr_cnt to process all queues using this vector.
2195 2250 */
2196 2251 for (qnum = inum;
2197 2252 qnum < nvme->n_ioq_count + 1 && nvme->n_ioq[qnum] != NULL;
2198 2253 qnum += nvme->n_intr_cnt) {
2199 2254 while ((cmd = nvme_retrieve_cmd(nvme, nvme->n_ioq[qnum]))) {
2200 2255 taskq_dispatch_ent((taskq_t *)cmd->nc_nvme->n_cmd_taskq,
2201 2256 cmd->nc_callback, cmd, TQ_NOSLEEP, &cmd->nc_tqent);
2202 2257 ccnt++;
2203 2258 }
2204 2259 }
2205 2260
2206 2261 return (ccnt > 0 ? DDI_INTR_CLAIMED : DDI_INTR_UNCLAIMED);
2207 2262 }
2208 2263
2209 2264 static void
2210 2265 nvme_release_interrupts(nvme_t *nvme)
2211 2266 {
2212 2267 int i;
2213 2268
2214 2269 for (i = 0; i < nvme->n_intr_cnt; i++) {
2215 2270 if (nvme->n_inth[i] == NULL)
2216 2271 break;
2217 2272
2218 2273 if (nvme->n_intr_cap & DDI_INTR_FLAG_BLOCK)
2219 2274 (void) ddi_intr_block_disable(&nvme->n_inth[i], 1);
2220 2275 else
2221 2276 (void) ddi_intr_disable(nvme->n_inth[i]);
2222 2277
2223 2278 (void) ddi_intr_remove_handler(nvme->n_inth[i]);
2224 2279 (void) ddi_intr_free(nvme->n_inth[i]);
2225 2280 }
2226 2281
2227 2282 kmem_free(nvme->n_inth, nvme->n_inth_sz);
2228 2283 nvme->n_inth = NULL;
2229 2284 nvme->n_inth_sz = 0;
2230 2285
2231 2286 nvme->n_progress &= ~NVME_INTERRUPTS;
2232 2287 }
2233 2288
2234 2289 static int
2235 2290 nvme_setup_interrupts(nvme_t *nvme, int intr_type, int nqpairs)
2236 2291 {
2237 2292 int nintrs, navail, count;
2238 2293 int ret;
2239 2294 int i;
2240 2295
2241 2296 if (nvme->n_intr_types == 0) {
2242 2297 ret = ddi_intr_get_supported_types(nvme->n_dip,
2243 2298 &nvme->n_intr_types);
2244 2299 if (ret != DDI_SUCCESS) {
2245 2300 dev_err(nvme->n_dip, CE_WARN,
2246 2301 "!%s: ddi_intr_get_supported types failed",
2247 2302 __func__);
2248 2303 return (ret);
2249 2304 }
2250 2305 }
2251 2306
2252 2307 if ((nvme->n_intr_types & intr_type) == 0)
2253 2308 return (DDI_FAILURE);
2254 2309
2255 2310 ret = ddi_intr_get_nintrs(nvme->n_dip, intr_type, &nintrs);
2256 2311 if (ret != DDI_SUCCESS) {
2257 2312 dev_err(nvme->n_dip, CE_WARN, "!%s: ddi_intr_get_nintrs failed",
2258 2313 __func__);
2259 2314 return (ret);
2260 2315 }
2261 2316
2262 2317 ret = ddi_intr_get_navail(nvme->n_dip, intr_type, &navail);
2263 2318 if (ret != DDI_SUCCESS) {
2264 2319 dev_err(nvme->n_dip, CE_WARN, "!%s: ddi_intr_get_navail failed",
2265 2320 __func__);
2266 2321 return (ret);
2267 2322 }
2268 2323
2269 2324 /* We want at most one interrupt per queue pair. */
2270 2325 if (navail > nqpairs)
2271 2326 navail = nqpairs;
2272 2327
2273 2328 nvme->n_inth_sz = sizeof (ddi_intr_handle_t) * navail;
2274 2329 nvme->n_inth = kmem_zalloc(nvme->n_inth_sz, KM_SLEEP);
2275 2330
2276 2331 ret = ddi_intr_alloc(nvme->n_dip, nvme->n_inth, intr_type, 0, navail,
2277 2332 &count, 0);
2278 2333 if (ret != DDI_SUCCESS) {
2279 2334 dev_err(nvme->n_dip, CE_WARN, "!%s: ddi_intr_alloc failed",
2280 2335 __func__);
2281 2336 goto fail;
2282 2337 }
2283 2338
2284 2339 nvme->n_intr_cnt = count;
2285 2340
2286 2341 ret = ddi_intr_get_pri(nvme->n_inth[0], &nvme->n_intr_pri);
2287 2342 if (ret != DDI_SUCCESS) {
2288 2343 dev_err(nvme->n_dip, CE_WARN, "!%s: ddi_intr_get_pri failed",
2289 2344 __func__);
2290 2345 goto fail;
2291 2346 }
2292 2347
2293 2348 for (i = 0; i < count; i++) {
2294 2349 ret = ddi_intr_add_handler(nvme->n_inth[i], nvme_intr,
2295 2350 (void *)nvme, (void *)(uintptr_t)i);
2296 2351 if (ret != DDI_SUCCESS) {
2297 2352 dev_err(nvme->n_dip, CE_WARN,
2298 2353 "!%s: ddi_intr_add_handler failed", __func__);
2299 2354 goto fail;
2300 2355 }
2301 2356 }
2302 2357
2303 2358 (void) ddi_intr_get_cap(nvme->n_inth[0], &nvme->n_intr_cap);
2304 2359
2305 2360 for (i = 0; i < count; i++) {
2306 2361 if (nvme->n_intr_cap & DDI_INTR_FLAG_BLOCK)
2307 2362 ret = ddi_intr_block_enable(&nvme->n_inth[i], 1);
2308 2363 else
2309 2364 ret = ddi_intr_enable(nvme->n_inth[i]);
2310 2365
2311 2366 if (ret != DDI_SUCCESS) {
2312 2367 dev_err(nvme->n_dip, CE_WARN,
2313 2368 "!%s: enabling interrupt %d failed", __func__, i);
2314 2369 goto fail;
2315 2370 }
2316 2371 }
2317 2372
2318 2373 nvme->n_intr_type = intr_type;
2319 2374
2320 2375 nvme->n_progress |= NVME_INTERRUPTS;
2321 2376
2322 2377 return (DDI_SUCCESS);
2323 2378
2324 2379 fail:
2325 2380 nvme_release_interrupts(nvme);
2326 2381
2327 2382 return (ret);
2328 2383 }
2329 2384
2330 2385 static int
2331 2386 nvme_fm_errcb(dev_info_t *dip, ddi_fm_error_t *fm_error, const void *arg)
2332 2387 {
2333 2388 _NOTE(ARGUNUSED(arg));
2334 2389
2335 2390 pci_ereport_post(dip, fm_error, NULL);
2336 2391 return (fm_error->fme_status);
2337 2392 }
2338 2393
2339 2394 static int
2340 2395 nvme_attach(dev_info_t *dip, ddi_attach_cmd_t cmd)
2341 2396 {
2342 2397 nvme_t *nvme;
2343 2398 int instance;
2344 2399 int nregs;
2345 2400 off_t regsize;
2346 2401 int i;
2347 2402 char name[32];
2348 2403
2349 2404 if (cmd != DDI_ATTACH)
2350 2405 return (DDI_FAILURE);
2351 2406
2352 2407 instance = ddi_get_instance(dip);
2353 2408
2354 2409 if (ddi_soft_state_zalloc(nvme_state, instance) != DDI_SUCCESS)
2355 2410 return (DDI_FAILURE);
2356 2411
2357 2412 nvme = ddi_get_soft_state(nvme_state, instance);
2358 2413 ddi_set_driver_private(dip, nvme);
2359 2414 nvme->n_dip = dip;
2360 2415
2361 2416 nvme->n_strict_version = ddi_prop_get_int(DDI_DEV_T_ANY, dip,
2362 2417 DDI_PROP_DONTPASS, "strict-version", 1) == 1 ? B_TRUE : B_FALSE;
2363 2418 nvme->n_ignore_unknown_vendor_status = ddi_prop_get_int(DDI_DEV_T_ANY,
2364 2419 dip, DDI_PROP_DONTPASS, "ignore-unknown-vendor-status", 0) == 1 ?
2365 2420 B_TRUE : B_FALSE;
2366 2421 nvme->n_admin_queue_len = ddi_prop_get_int(DDI_DEV_T_ANY, dip,
2367 2422 DDI_PROP_DONTPASS, "admin-queue-len", NVME_DEFAULT_ADMIN_QUEUE_LEN);
2368 2423 nvme->n_io_queue_len = ddi_prop_get_int(DDI_DEV_T_ANY, dip,
2369 2424 DDI_PROP_DONTPASS, "io-queue-len", NVME_DEFAULT_IO_QUEUE_LEN);
2370 2425 nvme->n_async_event_limit = ddi_prop_get_int(DDI_DEV_T_ANY, dip,
2371 2426 DDI_PROP_DONTPASS, "async-event-limit",
2372 2427 NVME_DEFAULT_ASYNC_EVENT_LIMIT);
2373 2428
2374 2429 if (nvme->n_admin_queue_len < NVME_MIN_ADMIN_QUEUE_LEN)
2375 2430 nvme->n_admin_queue_len = NVME_MIN_ADMIN_QUEUE_LEN;
2376 2431 else if (nvme->n_admin_queue_len > NVME_MAX_ADMIN_QUEUE_LEN)
2377 2432 nvme->n_admin_queue_len = NVME_MAX_ADMIN_QUEUE_LEN;
2378 2433
2379 2434 if (nvme->n_io_queue_len < NVME_MIN_IO_QUEUE_LEN)
2380 2435 nvme->n_io_queue_len = NVME_MIN_IO_QUEUE_LEN;
2381 2436
2382 2437 if (nvme->n_async_event_limit < 1)
2383 2438 nvme->n_async_event_limit = NVME_DEFAULT_ASYNC_EVENT_LIMIT;
2384 2439
2385 2440 nvme->n_reg_acc_attr = nvme_reg_acc_attr;
2386 2441 nvme->n_queue_dma_attr = nvme_queue_dma_attr;
2387 2442 nvme->n_prp_dma_attr = nvme_prp_dma_attr;
2388 2443 nvme->n_sgl_dma_attr = nvme_sgl_dma_attr;
2389 2444
2390 2445 /*
2391 2446 * Setup FMA support.
2392 2447 */
2393 2448 nvme->n_fm_cap = ddi_getprop(DDI_DEV_T_ANY, dip,
2394 2449 DDI_PROP_CANSLEEP | DDI_PROP_DONTPASS, "fm-capable",
2395 2450 DDI_FM_EREPORT_CAPABLE | DDI_FM_ACCCHK_CAPABLE |
2396 2451 DDI_FM_DMACHK_CAPABLE | DDI_FM_ERRCB_CAPABLE);
2397 2452
2398 2453 ddi_fm_init(dip, &nvme->n_fm_cap, &nvme->n_fm_ibc);
2399 2454
2400 2455 if (nvme->n_fm_cap) {
2401 2456 if (nvme->n_fm_cap & DDI_FM_ACCCHK_CAPABLE)
2402 2457 nvme->n_reg_acc_attr.devacc_attr_access =
2403 2458 DDI_FLAGERR_ACC;
2404 2459
2405 2460 if (nvme->n_fm_cap & DDI_FM_DMACHK_CAPABLE) {
2406 2461 nvme->n_prp_dma_attr.dma_attr_flags |= DDI_DMA_FLAGERR;
2407 2462 nvme->n_sgl_dma_attr.dma_attr_flags |= DDI_DMA_FLAGERR;
2408 2463 }
2409 2464
2410 2465 if (DDI_FM_EREPORT_CAP(nvme->n_fm_cap) ||
2411 2466 DDI_FM_ERRCB_CAP(nvme->n_fm_cap))
2412 2467 pci_ereport_setup(dip);
2413 2468
2414 2469 if (DDI_FM_ERRCB_CAP(nvme->n_fm_cap))
2415 2470 ddi_fm_handler_register(dip, nvme_fm_errcb,
2416 2471 (void *)nvme);
2417 2472 }
2418 2473
2419 2474 nvme->n_progress |= NVME_FMA_INIT;
2420 2475
2421 2476 /*
2422 2477 * The spec defines several register sets. Only the controller
2423 2478 * registers (set 1) are currently used.
2424 2479 */
2425 2480 if (ddi_dev_nregs(dip, &nregs) == DDI_FAILURE ||
2426 2481 nregs < 2 ||
2427 2482 ddi_dev_regsize(dip, 1, ®size) == DDI_FAILURE)
2428 2483 goto fail;
2429 2484
2430 2485 if (ddi_regs_map_setup(dip, 1, &nvme->n_regs, 0, regsize,
2431 2486 &nvme->n_reg_acc_attr, &nvme->n_regh) != DDI_SUCCESS) {
2432 2487 dev_err(dip, CE_WARN, "!failed to map regset 1");
2433 2488 goto fail;
2434 2489 }
2435 2490
2436 2491 nvme->n_progress |= NVME_REGS_MAPPED;
2437 2492
2438 2493 /*
2439 2494 * Create taskq for command completion.
↓ open down ↓ |
1766 lines elided |
↑ open up ↑ |
2440 2495 */
2441 2496 (void) snprintf(name, sizeof (name), "%s%d_cmd_taskq",
2442 2497 ddi_driver_name(dip), ddi_get_instance(dip));
2443 2498 nvme->n_cmd_taskq = ddi_taskq_create(dip, name, MIN(UINT16_MAX, ncpus),
2444 2499 TASKQ_DEFAULTPRI, 0);
2445 2500 if (nvme->n_cmd_taskq == NULL) {
2446 2501 dev_err(dip, CE_WARN, "!failed to create cmd taskq");
2447 2502 goto fail;
2448 2503 }
2449 2504
2505 + /*
2506 + * Create PRP DMA cache
2507 + */
2508 + (void) snprintf(name, sizeof (name), "%s%d_prp_cache",
2509 + ddi_driver_name(dip), ddi_get_instance(dip));
2510 + nvme->n_prp_cache = kmem_cache_create(name, sizeof (nvme_dma_t),
2511 + 0, nvme_prp_dma_constructor, nvme_prp_dma_destructor,
2512 + NULL, (void *)nvme, NULL, 0);
2450 2513
2451 2514 if (nvme_init(nvme) != DDI_SUCCESS)
2452 2515 goto fail;
2453 2516
2454 2517 /*
2455 2518 * Attach the blkdev driver for each namespace.
2456 2519 */
2457 2520 for (i = 0; i != nvme->n_namespace_count; i++) {
2458 2521 if (nvme->n_ns[i].ns_ignore)
2459 2522 continue;
2460 2523
2461 2524 nvme->n_ns[i].ns_bd_hdl = bd_alloc_handle(&nvme->n_ns[i],
2462 2525 &nvme_bd_ops, &nvme->n_prp_dma_attr, KM_SLEEP);
2463 2526
2464 2527 if (nvme->n_ns[i].ns_bd_hdl == NULL) {
2465 2528 dev_err(dip, CE_WARN,
2466 2529 "!failed to get blkdev handle for namespace %d", i);
2467 2530 goto fail;
2468 2531 }
2469 2532
2470 2533 if (bd_attach_handle(dip, nvme->n_ns[i].ns_bd_hdl)
2471 2534 != DDI_SUCCESS) {
2472 2535 dev_err(dip, CE_WARN,
2473 2536 "!failed to attach blkdev handle for namespace %d",
2474 2537 i);
2475 2538 goto fail;
2476 2539 }
2477 2540 }
2478 2541
2479 2542 return (DDI_SUCCESS);
2480 2543
2481 2544 fail:
2482 2545 /* attach successful anyway so that FMA can retire the device */
2483 2546 if (nvme->n_dead)
2484 2547 return (DDI_SUCCESS);
2485 2548
2486 2549 (void) nvme_detach(dip, DDI_DETACH);
2487 2550
2488 2551 return (DDI_FAILURE);
2489 2552 }
2490 2553
2491 2554 static int
2492 2555 nvme_detach(dev_info_t *dip, ddi_detach_cmd_t cmd)
2493 2556 {
2494 2557 int instance, i;
2495 2558 nvme_t *nvme;
2496 2559
2497 2560 if (cmd != DDI_DETACH)
2498 2561 return (DDI_FAILURE);
2499 2562
2500 2563 instance = ddi_get_instance(dip);
2501 2564
2502 2565 nvme = ddi_get_soft_state(nvme_state, instance);
2503 2566
2504 2567 if (nvme == NULL)
2505 2568 return (DDI_FAILURE);
2506 2569
2507 2570 if (nvme->n_ns) {
2508 2571 for (i = 0; i != nvme->n_namespace_count; i++) {
2509 2572 if (nvme->n_ns[i].ns_bd_hdl) {
2510 2573 (void) bd_detach_handle(
2511 2574 nvme->n_ns[i].ns_bd_hdl);
2512 2575 bd_free_handle(nvme->n_ns[i].ns_bd_hdl);
2513 2576 }
2514 2577
2515 2578 if (nvme->n_ns[i].ns_idns)
2516 2579 kmem_free(nvme->n_ns[i].ns_idns,
2517 2580 sizeof (nvme_identify_nsid_t));
2518 2581 }
2519 2582
2520 2583 kmem_free(nvme->n_ns, sizeof (nvme_namespace_t) *
2521 2584 nvme->n_namespace_count);
2522 2585 }
2523 2586
2524 2587 if (nvme->n_progress & NVME_INTERRUPTS)
2525 2588 nvme_release_interrupts(nvme);
2526 2589
2527 2590 if (nvme->n_cmd_taskq)
2528 2591 ddi_taskq_wait(nvme->n_cmd_taskq);
2529 2592
2530 2593 if (nvme->n_ioq_count > 0) {
2531 2594 for (i = 1; i != nvme->n_ioq_count + 1; i++) {
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2532 2595 if (nvme->n_ioq[i] != NULL) {
2533 2596 /* TODO: send destroy queue commands */
2534 2597 nvme_free_qpair(nvme->n_ioq[i]);
2535 2598 }
2536 2599 }
2537 2600
2538 2601 kmem_free(nvme->n_ioq, sizeof (nvme_qpair_t *) *
2539 2602 (nvme->n_ioq_count + 1));
2540 2603 }
2541 2604
2605 + if (nvme->n_prp_cache != NULL) {
2606 + kmem_cache_destroy(nvme->n_prp_cache);
2607 + }
2608 +
2542 2609 if (nvme->n_progress & NVME_REGS_MAPPED) {
2543 2610 nvme_shutdown(nvme, NVME_CC_SHN_NORMAL, B_FALSE);
2544 2611 (void) nvme_reset(nvme, B_FALSE);
2545 2612 }
2546 2613
2547 2614 if (nvme->n_cmd_taskq)
2548 2615 ddi_taskq_destroy(nvme->n_cmd_taskq);
2549 2616
2550 2617 if (nvme->n_progress & NVME_CTRL_LIMITS)
2551 2618 sema_destroy(&nvme->n_abort_sema);
2552 2619
2553 2620 if (nvme->n_progress & NVME_ADMIN_QUEUE)
2554 2621 nvme_free_qpair(nvme->n_adminq);
2555 2622
2556 2623 if (nvme->n_idctl)
2557 2624 kmem_free(nvme->n_idctl, sizeof (nvme_identify_ctrl_t));
2558 2625
2559 2626 if (nvme->n_progress & NVME_REGS_MAPPED)
2560 2627 ddi_regs_map_free(&nvme->n_regh);
2561 2628
2562 2629 if (nvme->n_progress & NVME_FMA_INIT) {
2563 2630 if (DDI_FM_ERRCB_CAP(nvme->n_fm_cap))
2564 2631 ddi_fm_handler_unregister(nvme->n_dip);
2565 2632
2566 2633 if (DDI_FM_EREPORT_CAP(nvme->n_fm_cap) ||
2567 2634 DDI_FM_ERRCB_CAP(nvme->n_fm_cap))
2568 2635 pci_ereport_teardown(nvme->n_dip);
2569 2636
2570 2637 ddi_fm_fini(nvme->n_dip);
2571 2638 }
2572 2639
2573 2640 if (nvme->n_vendor != NULL)
2574 2641 strfree(nvme->n_vendor);
2575 2642
2576 2643 if (nvme->n_product != NULL)
2577 2644 strfree(nvme->n_product);
2578 2645
2579 2646 ddi_soft_state_free(nvme_state, instance);
2580 2647
2581 2648 return (DDI_SUCCESS);
2582 2649 }
2583 2650
2584 2651 static int
2585 2652 nvme_quiesce(dev_info_t *dip)
2586 2653 {
2587 2654 int instance;
2588 2655 nvme_t *nvme;
2589 2656
2590 2657 instance = ddi_get_instance(dip);
2591 2658
2592 2659 nvme = ddi_get_soft_state(nvme_state, instance);
2593 2660
2594 2661 if (nvme == NULL)
2595 2662 return (DDI_FAILURE);
2596 2663
2597 2664 nvme_shutdown(nvme, NVME_CC_SHN_ABRUPT, B_TRUE);
2598 2665
2599 2666 (void) nvme_reset(nvme, B_TRUE);
2600 2667
2601 2668 return (DDI_FAILURE);
2602 2669 }
2603 2670
2604 2671 static int
2605 2672 nvme_fill_prp(nvme_cmd_t *cmd, bd_xfer_t *xfer)
2606 2673 {
2607 2674 nvme_t *nvme = cmd->nc_nvme;
2608 2675 int nprp_page, nprp;
2609 2676 uint64_t *prp;
2610 2677
2611 2678 if (xfer->x_ndmac == 0)
2612 2679 return (DDI_FAILURE);
2613 2680
2614 2681 cmd->nc_sqe.sqe_dptr.d_prp[0] = xfer->x_dmac.dmac_laddress;
2615 2682 ddi_dma_nextcookie(xfer->x_dmah, &xfer->x_dmac);
2616 2683
2617 2684 if (xfer->x_ndmac == 1) {
2618 2685 cmd->nc_sqe.sqe_dptr.d_prp[1] = 0;
2619 2686 return (DDI_SUCCESS);
2620 2687 } else if (xfer->x_ndmac == 2) {
2621 2688 cmd->nc_sqe.sqe_dptr.d_prp[1] = xfer->x_dmac.dmac_laddress;
2622 2689 return (DDI_SUCCESS);
2623 2690 }
2624 2691
2625 2692 xfer->x_ndmac--;
2626 2693
2627 2694 nprp_page = nvme->n_pagesize / sizeof (uint64_t) - 1;
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2628 2695 ASSERT(nprp_page > 0);
2629 2696 nprp = (xfer->x_ndmac + nprp_page - 1) / nprp_page;
2630 2697
2631 2698 /*
2632 2699 * We currently don't support chained PRPs and set up our DMA
2633 2700 * attributes to reflect that. If we still get an I/O request
2634 2701 * that needs a chained PRP something is very wrong.
2635 2702 */
2636 2703 VERIFY(nprp == 1);
2637 2704
2638 - if (nvme_zalloc_dma(nvme, nvme->n_pagesize * nprp, DDI_DMA_READ,
2639 - &nvme->n_prp_dma_attr, &cmd->nc_dma) != DDI_SUCCESS) {
2640 - dev_err(nvme->n_dip, CE_WARN, "!%s: nvme_zalloc_dma failed",
2641 - __func__);
2642 - return (DDI_FAILURE);
2643 - }
2705 + cmd->nc_dma = kmem_cache_alloc(nvme->n_prp_cache, KM_SLEEP);
2706 + bzero(cmd->nc_dma->nd_memp, cmd->nc_dma->nd_len);
2644 2707
2645 2708 cmd->nc_sqe.sqe_dptr.d_prp[1] = cmd->nc_dma->nd_cookie.dmac_laddress;
2646 - ddi_dma_nextcookie(cmd->nc_dma->nd_dmah, &cmd->nc_dma->nd_cookie);
2647 2709
2648 2710 /*LINTED: E_PTR_BAD_CAST_ALIGN*/
2649 2711 for (prp = (uint64_t *)cmd->nc_dma->nd_memp;
2650 2712 xfer->x_ndmac > 0;
2651 2713 prp++, xfer->x_ndmac--) {
2652 2714 *prp = xfer->x_dmac.dmac_laddress;
2653 2715 ddi_dma_nextcookie(xfer->x_dmah, &xfer->x_dmac);
2654 2716 }
2655 2717
2656 2718 (void) ddi_dma_sync(cmd->nc_dma->nd_dmah, 0, cmd->nc_dma->nd_len,
2657 2719 DDI_DMA_SYNC_FORDEV);
2658 2720 return (DDI_SUCCESS);
2659 2721 }
2660 2722
2661 2723 static nvme_cmd_t *
2662 2724 nvme_create_nvm_cmd(nvme_namespace_t *ns, uint8_t opc, bd_xfer_t *xfer)
2663 2725 {
2664 2726 nvme_t *nvme = ns->ns_nvme;
2665 2727 nvme_cmd_t *cmd;
2666 2728
2667 2729 /*
2668 2730 * Blkdev only sets BD_XFER_POLL when dumping, so don't sleep.
2669 2731 */
2670 2732 cmd = nvme_alloc_cmd(nvme, (xfer->x_flags & BD_XFER_POLL) ?
2671 2733 KM_NOSLEEP : KM_SLEEP);
2672 2734
2673 2735 if (cmd == NULL)
2674 2736 return (NULL);
2675 2737
2676 2738 cmd->nc_sqe.sqe_opc = opc;
2677 2739 cmd->nc_callback = nvme_bd_xfer_done;
2678 2740 cmd->nc_xfer = xfer;
2679 2741
2680 2742 switch (opc) {
2681 2743 case NVME_OPC_NVM_WRITE:
2682 2744 case NVME_OPC_NVM_READ:
2683 2745 VERIFY(xfer->x_nblks <= 0x10000);
2684 2746
2685 2747 cmd->nc_sqe.sqe_nsid = ns->ns_id;
2686 2748
2687 2749 cmd->nc_sqe.sqe_cdw10 = xfer->x_blkno & 0xffffffffu;
2688 2750 cmd->nc_sqe.sqe_cdw11 = (xfer->x_blkno >> 32);
2689 2751 cmd->nc_sqe.sqe_cdw12 = (uint16_t)(xfer->x_nblks - 1);
2690 2752
2691 2753 if (nvme_fill_prp(cmd, xfer) != DDI_SUCCESS)
2692 2754 goto fail;
2693 2755 break;
2694 2756
2695 2757 case NVME_OPC_NVM_FLUSH:
2696 2758 cmd->nc_sqe.sqe_nsid = ns->ns_id;
2697 2759 break;
2698 2760
2699 2761 default:
2700 2762 goto fail;
2701 2763 }
2702 2764
2703 2765 return (cmd);
2704 2766
2705 2767 fail:
2706 2768 nvme_free_cmd(cmd);
2707 2769 return (NULL);
2708 2770 }
2709 2771
2710 2772 static void
2711 2773 nvme_bd_xfer_done(void *arg)
2712 2774 {
2713 2775 nvme_cmd_t *cmd = arg;
2714 2776 bd_xfer_t *xfer = cmd->nc_xfer;
2715 2777 int error = 0;
2716 2778
2717 2779 error = nvme_check_cmd_status(cmd);
2718 2780 nvme_free_cmd(cmd);
2719 2781
2720 2782 bd_xfer_done(xfer, error);
2721 2783 }
2722 2784
2723 2785 static void
2724 2786 nvme_bd_driveinfo(void *arg, bd_drive_t *drive)
2725 2787 {
2726 2788 nvme_namespace_t *ns = arg;
2727 2789 nvme_t *nvme = ns->ns_nvme;
2728 2790
2729 2791 /*
2730 2792 * blkdev maintains one queue size per instance (namespace),
2731 2793 * but all namespace share the I/O queues.
2732 2794 * TODO: need to figure out a sane default, or use per-NS I/O queues,
2733 2795 * or change blkdev to handle EAGAIN
2734 2796 */
2735 2797 drive->d_qsize = nvme->n_ioq_count * nvme->n_io_queue_len
2736 2798 / nvme->n_namespace_count;
2737 2799
2738 2800 /*
2739 2801 * d_maxxfer is not set, which means the value is taken from the DMA
2740 2802 * attributes specified to bd_alloc_handle.
2741 2803 */
2742 2804
2743 2805 drive->d_removable = B_FALSE;
2744 2806 drive->d_hotpluggable = B_FALSE;
2745 2807
2746 2808 drive->d_target = ns->ns_id;
2747 2809 drive->d_lun = 0;
2748 2810
2749 2811 drive->d_model = nvme->n_idctl->id_model;
2750 2812 drive->d_model_len = sizeof (nvme->n_idctl->id_model);
2751 2813 drive->d_vendor = nvme->n_vendor;
2752 2814 drive->d_vendor_len = strlen(nvme->n_vendor);
2753 2815 drive->d_product = nvme->n_product;
2754 2816 drive->d_product_len = strlen(nvme->n_product);
2755 2817 drive->d_serial = nvme->n_idctl->id_serial;
2756 2818 drive->d_serial_len = sizeof (nvme->n_idctl->id_serial);
2757 2819 drive->d_revision = nvme->n_idctl->id_fwrev;
2758 2820 drive->d_revision_len = sizeof (nvme->n_idctl->id_fwrev);
2759 2821 }
2760 2822
2761 2823 static int
2762 2824 nvme_bd_mediainfo(void *arg, bd_media_t *media)
2763 2825 {
2764 2826 nvme_namespace_t *ns = arg;
2765 2827
2766 2828 media->m_nblks = ns->ns_block_count;
2767 2829 media->m_blksize = ns->ns_block_size;
2768 2830 media->m_readonly = B_FALSE;
2769 2831 media->m_solidstate = B_TRUE;
2770 2832
2771 2833 media->m_pblksize = ns->ns_best_block_size;
2772 2834
2773 2835 return (0);
2774 2836 }
2775 2837
2776 2838 static int
2777 2839 nvme_bd_cmd(nvme_namespace_t *ns, bd_xfer_t *xfer, uint8_t opc)
2778 2840 {
2779 2841 nvme_t *nvme = ns->ns_nvme;
2780 2842 nvme_cmd_t *cmd;
2781 2843
2782 2844 if (nvme->n_dead)
2783 2845 return (EIO);
2784 2846
2785 2847 /* No polling for now */
2786 2848 if (xfer->x_flags & BD_XFER_POLL)
2787 2849 return (EIO);
2788 2850
2789 2851 cmd = nvme_create_nvm_cmd(ns, opc, xfer);
2790 2852 if (cmd == NULL)
2791 2853 return (ENOMEM);
2792 2854
2793 2855 cmd->nc_sqid = (CPU->cpu_id % nvme->n_ioq_count) + 1;
2794 2856 ASSERT(cmd->nc_sqid <= nvme->n_ioq_count);
2795 2857
2796 2858 if (nvme_submit_cmd(nvme->n_ioq[cmd->nc_sqid], cmd)
2797 2859 != DDI_SUCCESS)
2798 2860 return (EAGAIN);
2799 2861
2800 2862 return (0);
2801 2863 }
2802 2864
2803 2865 static int
2804 2866 nvme_bd_read(void *arg, bd_xfer_t *xfer)
2805 2867 {
2806 2868 nvme_namespace_t *ns = arg;
2807 2869
2808 2870 return (nvme_bd_cmd(ns, xfer, NVME_OPC_NVM_READ));
2809 2871 }
2810 2872
2811 2873 static int
2812 2874 nvme_bd_write(void *arg, bd_xfer_t *xfer)
2813 2875 {
2814 2876 nvme_namespace_t *ns = arg;
2815 2877
2816 2878 return (nvme_bd_cmd(ns, xfer, NVME_OPC_NVM_WRITE));
2817 2879 }
2818 2880
2819 2881 static int
2820 2882 nvme_bd_sync(void *arg, bd_xfer_t *xfer)
2821 2883 {
2822 2884 nvme_namespace_t *ns = arg;
2823 2885
2824 2886 if (ns->ns_nvme->n_dead)
2825 2887 return (EIO);
2826 2888
2827 2889 /*
2828 2890 * If the volatile write cache isn't enabled the FLUSH command is a
2829 2891 * no-op, so we can take a shortcut here.
2830 2892 */
2831 2893 if (ns->ns_nvme->n_volatile_write_cache_enabled == B_FALSE) {
2832 2894 bd_xfer_done(xfer, ENOTSUP);
2833 2895 return (0);
2834 2896 }
2835 2897
2836 2898 return (nvme_bd_cmd(ns, xfer, NVME_OPC_NVM_FLUSH));
2837 2899 }
2838 2900
2839 2901 static int
2840 2902 nvme_bd_devid(void *arg, dev_info_t *devinfo, ddi_devid_t *devid)
2841 2903 {
2842 2904 nvme_namespace_t *ns = arg;
2843 2905
2844 2906 return (ddi_devid_init(devinfo, DEVID_ENCAP, strlen(ns->ns_devid),
2845 2907 ns->ns_devid, devid));
2846 2908 }
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