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7351 NVMe driver sporadically lost track of completed I/O request, which
leads to zpool hanging and machine panic.
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--- old/usr/src/uts/common/io/nvme/nvme_var.h
+++ new/usr/src/uts/common/io/nvme/nvme_var.h
1 1 /*
2 2 * This file and its contents are supplied under the terms of the
3 3 * Common Development and Distribution License ("CDDL"), version 1.0.
4 4 * You may only use this file in accordance with the terms of version
5 5 * 1.0 of the CDDL.
6 6 *
7 7 * A full copy of the text of the CDDL should have accompanied this
8 8 * source. A copy of the CDDL is also available via the Internet at
9 9 * http://www.illumos.org/license/CDDL.
10 10 */
11 11
12 12 /*
13 13 * Copyright 2016 Nexenta Systems, Inc. All rights reserved.
14 14 */
15 15
16 16 #ifndef _NVME_VAR_H
17 17 #define _NVME_VAR_H
18 18
19 19 #include <sys/ddi.h>
20 20 #include <sys/sunddi.h>
21 21 #include <sys/blkdev.h>
22 22 #include <sys/taskq_impl.h>
23 23
24 24 /*
25 25 * NVMe driver state
26 26 */
27 27
28 28 #ifdef __cplusplus
29 29 /* extern "C" { */
30 30 #endif
31 31
32 32 #define NVME_FMA_INIT 0x1
33 33 #define NVME_REGS_MAPPED 0x2
34 34 #define NVME_ADMIN_QUEUE 0x4
35 35 #define NVME_CTRL_LIMITS 0x8
36 36 #define NVME_INTERRUPTS 0x10
37 37
38 38 #define NVME_MIN_ADMIN_QUEUE_LEN 16
39 39 #define NVME_MIN_IO_QUEUE_LEN 16
40 40 #define NVME_DEFAULT_ADMIN_QUEUE_LEN 256
41 41 #define NVME_DEFAULT_IO_QUEUE_LEN 1024
42 42 #define NVME_DEFAULT_ASYNC_EVENT_LIMIT 10
43 43 #define NVME_MIN_ASYNC_EVENT_LIMIT 1
44 44
45 45
46 46 typedef struct nvme nvme_t;
47 47 typedef struct nvme_namespace nvme_namespace_t;
48 48 typedef struct nvme_dma nvme_dma_t;
49 49 typedef struct nvme_cmd nvme_cmd_t;
50 50 typedef struct nvme_qpair nvme_qpair_t;
51 51 typedef struct nvme_task_arg nvme_task_arg_t;
52 52
53 53 struct nvme_dma {
54 54 ddi_dma_handle_t nd_dmah;
55 55 ddi_acc_handle_t nd_acch;
56 56 ddi_dma_cookie_t nd_cookie;
57 57 uint_t nd_ncookie;
58 58 caddr_t nd_memp;
59 59 size_t nd_len;
60 60 };
61 61
62 62 struct nvme_cmd {
63 63 nvme_sqe_t nc_sqe;
64 64 nvme_cqe_t nc_cqe;
65 65
66 66 void (*nc_callback)(void *);
67 67 bd_xfer_t *nc_xfer;
68 68 boolean_t nc_completed;
69 69 uint16_t nc_sqid;
70 70
71 71 nvme_dma_t *nc_dma;
72 72
73 73 kmutex_t nc_mutex;
74 74 kcondvar_t nc_cv;
75 75
76 76 taskq_ent_t nc_tqent;
77 77 nvme_t *nc_nvme;
78 78 };
79 79
80 80 struct nvme_qpair {
81 81 size_t nq_nentry;
82 82
83 83 nvme_dma_t *nq_sqdma;
84 84 nvme_sqe_t *nq_sq;
85 85 uint_t nq_sqhead;
86 86 uint_t nq_sqtail;
87 87 uintptr_t nq_sqtdbl;
88 88
89 89 nvme_dma_t *nq_cqdma;
90 90 nvme_cqe_t *nq_cq;
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91 91 uint_t nq_cqhead;
92 92 uint_t nq_cqtail;
93 93 uintptr_t nq_cqhdbl;
94 94
95 95 nvme_cmd_t **nq_cmd;
96 96 uint16_t nq_next_cmd;
97 97 uint_t nq_active_cmds;
98 98 int nq_phase;
99 99
100 100 kmutex_t nq_mutex;
101 + hrtime_t nq_ts;
102 + list_node_t nq_list_node;
103 + nvme_t *nq_nvme;
101 104 };
102 105
103 106 struct nvme {
104 107 dev_info_t *n_dip;
105 108 int n_progress;
106 109
107 110 caddr_t n_regs;
108 111 ddi_acc_handle_t n_regh;
109 112
110 113 kmem_cache_t *n_cmd_cache;
111 114
112 115 size_t n_inth_sz;
113 116 ddi_intr_handle_t *n_inth;
114 117 int n_intr_cnt;
115 118 uint_t n_intr_pri;
116 119 int n_intr_cap;
117 120 int n_intr_type;
118 121 int n_intr_types;
122 + int n_intr_timeouts;
119 123
120 124 char *n_product;
121 125 char *n_vendor;
122 126
123 127 boolean_t n_dead;
124 128 boolean_t n_strict_version;
125 129 boolean_t n_ignore_unknown_vendor_status;
126 130 uint32_t n_admin_queue_len;
127 131 uint32_t n_io_queue_len;
128 132 uint16_t n_async_event_limit;
129 133 uint16_t n_abort_command_limit;
130 134 uint64_t n_max_data_transfer_size;
131 135 boolean_t n_volatile_write_cache_enabled;
132 136 int n_error_log_len;
133 137
134 138 int n_nssr_supported;
135 139 int n_doorbell_stride;
136 140 int n_timeout;
137 141 int n_arbitration_mechanisms;
138 142 int n_cont_queues_reqd;
139 143 int n_max_queue_entries;
140 144 int n_pageshift;
141 145 int n_pagesize;
142 146
143 147 int n_namespace_count;
144 148 int n_ioq_count;
145 149
146 150 nvme_identify_ctrl_t *n_idctl;
147 151
148 152 nvme_qpair_t *n_adminq;
149 153 nvme_qpair_t **n_ioq;
150 154
151 155 nvme_namespace_t *n_ns;
152 156
153 157 ddi_dma_attr_t n_queue_dma_attr;
154 158 ddi_dma_attr_t n_prp_dma_attr;
155 159 ddi_dma_attr_t n_sgl_dma_attr;
156 160 ddi_device_acc_attr_t n_reg_acc_attr;
157 161 ddi_iblock_cookie_t n_fm_ibc;
158 162 int n_fm_cap;
159 163
160 164 ksema_t n_abort_sema;
161 165
162 166 ddi_taskq_t *n_cmd_taskq;
163 167
164 168 nvme_error_log_entry_t *n_error_log;
165 169 nvme_health_log_t *n_health_log;
166 170 nvme_fwslot_log_t *n_fwslot_log;
167 171
168 172 /* errors detected by driver */
169 173 uint32_t n_dma_bind_err;
170 174 uint32_t n_abort_failed;
171 175 uint32_t n_cmd_timeout;
172 176 uint32_t n_cmd_aborted;
173 177 uint32_t n_async_resubmit_failed;
174 178 uint32_t n_wrong_logpage;
175 179 uint32_t n_unknown_logpage;
176 180 uint32_t n_too_many_cookies;
177 181 uint32_t n_admin_queue_full;
178 182
179 183 /* errors detected by hardware */
180 184 uint32_t n_data_xfr_err;
181 185 uint32_t n_internal_err;
182 186 uint32_t n_abort_rq_err;
183 187 uint32_t n_abort_sq_del;
184 188 uint32_t n_nvm_cap_exc;
185 189 uint32_t n_nvm_ns_notrdy;
186 190 uint32_t n_inv_cq_err;
187 191 uint32_t n_inv_qid_err;
188 192 uint32_t n_max_qsz_exc;
189 193 uint32_t n_inv_int_vect;
190 194 uint32_t n_inv_log_page;
191 195 uint32_t n_inv_format;
192 196 uint32_t n_inv_q_del;
193 197 uint32_t n_cnfl_attr;
194 198 uint32_t n_inv_prot;
195 199 uint32_t n_readonly;
196 200
197 201 /* errors reported by asynchronous events */
198 202 uint32_t n_diagfail_event;
199 203 uint32_t n_persistent_event;
200 204 uint32_t n_transient_event;
201 205 uint32_t n_fw_load_event;
202 206 uint32_t n_reliability_event;
203 207 uint32_t n_temperature_event;
204 208 uint32_t n_spare_event;
205 209 uint32_t n_vendor_event;
206 210 uint32_t n_unknown_event;
207 211
208 212 };
209 213
210 214 struct nvme_namespace {
211 215 nvme_t *ns_nvme;
212 216 bd_handle_t ns_bd_hdl;
213 217
214 218 uint32_t ns_id;
215 219 size_t ns_block_count;
216 220 size_t ns_block_size;
217 221 size_t ns_best_block_size;
218 222
219 223 boolean_t ns_ignore;
220 224
221 225 nvme_identify_nsid_t *ns_idns;
222 226
223 227 /*
224 228 * Section 7.7 of the spec describes how to get a unique ID for
225 229 * the controller: the vendor ID, the model name and the serial
226 230 * number shall be unique when combined.
227 231 *
228 232 * We add the hex namespace ID to get a unique ID for the namespace.
229 233 */
230 234 char ns_devid[4 + 1 + 20 + 1 + 40 + 1 + 8 + 1];
231 235 };
232 236
233 237 struct nvme_task_arg {
234 238 nvme_t *nt_nvme;
235 239 nvme_cmd_t *nt_cmd;
236 240 };
237 241
238 242 #ifdef __cplusplus
239 243 /* } */
240 244 #endif
241 245
242 246 #endif /* _NVME_VAR_H */
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