1 /*
2 * This file and its contents are supplied under the terms of the
3 * Common Development and Distribution License ("CDDL"), version 1.0.
4 * You may only use this file in accordance with the terms of version
5 * 1.0 of the CDDL.
6 *
7 * A full copy of the text of the CDDL should have accompanied this
8 * source. A copy of the CDDL is also available via the Internet at
9 * http://www.illumos.org/license/CDDL.
10 */
11
12 /*
13 * Copyright 2016 Nexenta Systems, Inc. All rights reserved.
14 */
15
16 #ifndef _NVME_VAR_H
17 #define _NVME_VAR_H
18
19 #include <sys/ddi.h>
20 #include <sys/sunddi.h>
21 #include <sys/blkdev.h>
22 #include <sys/taskq_impl.h>
23
24 /*
25 * NVMe driver state
26 */
27
28 #ifdef __cplusplus
29 /* extern "C" { */
30 #endif
31
32 #define NVME_FMA_INIT 0x1
33 #define NVME_REGS_MAPPED 0x2
34 #define NVME_ADMIN_QUEUE 0x4
35 #define NVME_CTRL_LIMITS 0x8
36 #define NVME_INTERRUPTS 0x10
37
38 #define NVME_MIN_ADMIN_QUEUE_LEN 16
39 #define NVME_MIN_IO_QUEUE_LEN 16
40 #define NVME_DEFAULT_ADMIN_QUEUE_LEN 256
41 #define NVME_DEFAULT_IO_QUEUE_LEN 1024
42 #define NVME_DEFAULT_ASYNC_EVENT_LIMIT 10
43 #define NVME_MIN_ASYNC_EVENT_LIMIT 1
44
45
46 typedef struct nvme nvme_t;
47 typedef struct nvme_namespace nvme_namespace_t;
48 typedef struct nvme_dma nvme_dma_t;
49 typedef struct nvme_cmd nvme_cmd_t;
50 typedef struct nvme_qpair nvme_qpair_t;
51 typedef struct nvme_task_arg nvme_task_arg_t;
52
53 struct nvme_dma {
54 ddi_dma_handle_t nd_dmah;
55 ddi_acc_handle_t nd_acch;
56 ddi_dma_cookie_t nd_cookie;
57 uint_t nd_ncookie;
58 caddr_t nd_memp;
59 size_t nd_len;
60 };
61
62 struct nvme_cmd {
63 nvme_sqe_t nc_sqe;
64 nvme_cqe_t nc_cqe;
65
66 void (*nc_callback)(void *);
67 bd_xfer_t *nc_xfer;
68 boolean_t nc_completed;
69 uint16_t nc_sqid;
70
71 nvme_dma_t *nc_dma;
72
73 kmutex_t nc_mutex;
74 kcondvar_t nc_cv;
75
76 taskq_ent_t nc_tqent;
77 nvme_t *nc_nvme;
78 };
79
80 struct nvme_qpair {
81 size_t nq_nentry;
82
83 nvme_dma_t *nq_sqdma;
84 nvme_sqe_t *nq_sq;
85 uint_t nq_sqhead;
86 uint_t nq_sqtail;
87 uintptr_t nq_sqtdbl;
88
89 nvme_dma_t *nq_cqdma;
90 nvme_cqe_t *nq_cq;
91 uint_t nq_cqhead;
92 uint_t nq_cqtail;
93 uintptr_t nq_cqhdbl;
94
95 nvme_cmd_t **nq_cmd;
96 uint16_t nq_next_cmd;
97 uint_t nq_active_cmds;
98 int nq_phase;
99
100 kmutex_t nq_mutex;
101 };
102
103 struct nvme {
104 dev_info_t *n_dip;
105 int n_progress;
106
107 caddr_t n_regs;
108 ddi_acc_handle_t n_regh;
109
110 kmem_cache_t *n_cmd_cache;
111
112 size_t n_inth_sz;
113 ddi_intr_handle_t *n_inth;
114 int n_intr_cnt;
115 uint_t n_intr_pri;
116 int n_intr_cap;
117 int n_intr_type;
118 int n_intr_types;
119
120 char *n_product;
121 char *n_vendor;
122
123 boolean_t n_dead;
124 boolean_t n_strict_version;
125 boolean_t n_ignore_unknown_vendor_status;
126 uint32_t n_admin_queue_len;
127 uint32_t n_io_queue_len;
128 uint16_t n_async_event_limit;
129 uint16_t n_abort_command_limit;
130 uint64_t n_max_data_transfer_size;
131 boolean_t n_volatile_write_cache_enabled;
132 int n_error_log_len;
133
134 int n_nssr_supported;
135 int n_doorbell_stride;
136 int n_timeout;
137 int n_arbitration_mechanisms;
138 int n_cont_queues_reqd;
139 int n_max_queue_entries;
140 int n_pageshift;
141 int n_pagesize;
142
143 int n_namespace_count;
144 int n_ioq_count;
145
146 nvme_identify_ctrl_t *n_idctl;
147
148 nvme_qpair_t *n_adminq;
149 nvme_qpair_t **n_ioq;
150
151 nvme_namespace_t *n_ns;
152
153 ddi_dma_attr_t n_queue_dma_attr;
154 ddi_dma_attr_t n_prp_dma_attr;
155 ddi_dma_attr_t n_sgl_dma_attr;
156 ddi_device_acc_attr_t n_reg_acc_attr;
157 ddi_iblock_cookie_t n_fm_ibc;
158 int n_fm_cap;
159
160 ksema_t n_abort_sema;
161
162 ddi_taskq_t *n_cmd_taskq;
163
164 nvme_error_log_entry_t *n_error_log;
165 nvme_health_log_t *n_health_log;
166 nvme_fwslot_log_t *n_fwslot_log;
167
168 /* errors detected by driver */
169 uint32_t n_dma_bind_err;
170 uint32_t n_abort_failed;
171 uint32_t n_cmd_timeout;
172 uint32_t n_cmd_aborted;
173 uint32_t n_async_resubmit_failed;
174 uint32_t n_wrong_logpage;
175 uint32_t n_unknown_logpage;
176 uint32_t n_too_many_cookies;
177 uint32_t n_admin_queue_full;
178
179 /* errors detected by hardware */
180 uint32_t n_data_xfr_err;
181 uint32_t n_internal_err;
182 uint32_t n_abort_rq_err;
183 uint32_t n_abort_sq_del;
184 uint32_t n_nvm_cap_exc;
185 uint32_t n_nvm_ns_notrdy;
186 uint32_t n_inv_cq_err;
187 uint32_t n_inv_qid_err;
188 uint32_t n_max_qsz_exc;
189 uint32_t n_inv_int_vect;
190 uint32_t n_inv_log_page;
191 uint32_t n_inv_format;
192 uint32_t n_inv_q_del;
193 uint32_t n_cnfl_attr;
194 uint32_t n_inv_prot;
195 uint32_t n_readonly;
196
197 /* errors reported by asynchronous events */
198 uint32_t n_diagfail_event;
199 uint32_t n_persistent_event;
200 uint32_t n_transient_event;
201 uint32_t n_fw_load_event;
202 uint32_t n_reliability_event;
203 uint32_t n_temperature_event;
204 uint32_t n_spare_event;
205 uint32_t n_vendor_event;
206 uint32_t n_unknown_event;
207
208 };
209
210 struct nvme_namespace {
211 nvme_t *ns_nvme;
212 bd_handle_t ns_bd_hdl;
213
214 uint32_t ns_id;
215 size_t ns_block_count;
216 size_t ns_block_size;
217 size_t ns_best_block_size;
218
219 boolean_t ns_ignore;
220
221 nvme_identify_nsid_t *ns_idns;
222
223 /*
224 * Section 7.7 of the spec describes how to get a unique ID for
225 * the controller: the vendor ID, the model name and the serial
226 * number shall be unique when combined.
227 *
228 * We add the hex namespace ID to get a unique ID for the namespace.
229 */
230 char ns_devid[4 + 1 + 20 + 1 + 40 + 1 + 8 + 1];
231 };
232
233 struct nvme_task_arg {
234 nvme_t *nt_nvme;
235 nvme_cmd_t *nt_cmd;
236 };
237
238 #ifdef __cplusplus
239 /* } */
240 #endif
241
242 #endif /* _NVME_VAR_H */