1 /*
2 * mr_sas.c: source for mr_sas driver
3 *
4 * Solaris MegaRAID device driver for SAS2.0 controllers
5 * Copyright (c) 2008-2012, LSI Logic Corporation.
6 * All rights reserved.
7 *
8 * Version:
9 * Author:
10 * Swaminathan K S
11 * Arun Chandrashekhar
12 * Manju R
13 * Rasheed
14 * Shakeel Bukhari
15 *
16 * Redistribution and use in source and binary forms, with or without
17 * modification, are permitted provided that the following conditions are met:
18 *
19 * 1. Redistributions of source code must retain the above copyright notice,
20 * this list of conditions and the following disclaimer.
21 *
22 * 2. Redistributions in binary form must reproduce the above copyright notice,
23 * this list of conditions and the following disclaimer in the documentation
24 * and/or other materials provided with the distribution.
25 *
26 * 3. Neither the name of the author nor the names of its contributors may be
27 * used to endorse or promote products derived from this software without
28 * specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
33 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
34 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
35 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
36 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
37 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
38 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
39 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
40 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
41 * DAMAGE.
42 */
43
44 /*
45 * Copyright (c) 2009, 2010, Oracle and/or its affiliates. All rights reserved.
46 * Copyright (c) 2011 Bayard G. Bell. All rights reserved.
47 * Copyright 2018 Nexenta Systems, Inc.
48 * Copyright 2015, 2017 Citrus IT Limited. All rights reserved.
49 * Copyright 2015 Garrett D'Amore <garrett@damore.org>
50 */
51
52 #include <sys/types.h>
53 #include <sys/param.h>
54 #include <sys/file.h>
55 #include <sys/errno.h>
56 #include <sys/open.h>
57 #include <sys/cred.h>
58 #include <sys/modctl.h>
59 #include <sys/conf.h>
60 #include <sys/devops.h>
61 #include <sys/cmn_err.h>
62 #include <sys/kmem.h>
63 #include <sys/stat.h>
64 #include <sys/mkdev.h>
65 #include <sys/pci.h>
66 #include <sys/scsi/scsi.h>
67 #include <sys/ddi.h>
68 #include <sys/sunddi.h>
69 #include <sys/atomic.h>
70 #include <sys/signal.h>
71 #include <sys/byteorder.h>
72 #include <sys/sdt.h>
73
74 #include "mr_sas.h"
75
76 /*
77 * FMA header files
78 */
79 #include <sys/ddifm.h>
80 #include <sys/fm/protocol.h>
81 #include <sys/fm/util.h>
82 #include <sys/fm/io/ddi.h>
83
84 /* Macros to help Skinny and stock 2108/MFI live together. */
85 #define WR_IB_PICK_QPORT(addr, instance) \
86 if ((instance)->skinny) { \
87 WR_IB_LOW_QPORT((addr), (instance)); \
88 WR_IB_HIGH_QPORT(0, (instance)); \
89 } else { \
90 WR_IB_QPORT((addr), (instance)); \
91 }
92
93 /*
94 * Local static data
95 */
96 static void *mrsas_state = NULL;
97 static volatile boolean_t mrsas_relaxed_ordering = B_TRUE;
98 volatile int debug_level_g = CL_NONE;
99 static volatile int msi_enable = 1;
100 static volatile int ctio_enable = 1;
101
102 /* Default Timeout value to issue online controller reset */
103 volatile int debug_timeout_g = 0xF0; /* 0xB4; */
104 /* Simulate consecutive firmware fault */
105 static volatile int debug_fw_faults_after_ocr_g = 0;
106 #ifdef OCRDEBUG
107 /* Simulate three consecutive timeout for an IO */
108 static volatile int debug_consecutive_timeout_after_ocr_g = 0;
109 #endif
110
111 #pragma weak scsi_hba_open
112 #pragma weak scsi_hba_close
113 #pragma weak scsi_hba_ioctl
114
115 /* Local static prototypes. */
116 static int mrsas_getinfo(dev_info_t *, ddi_info_cmd_t, void *, void **);
117 static int mrsas_attach(dev_info_t *, ddi_attach_cmd_t);
118 #ifdef __sparc
119 static int mrsas_reset(dev_info_t *, ddi_reset_cmd_t);
120 #else
121 static int mrsas_quiesce(dev_info_t *);
122 #endif
123 static int mrsas_detach(dev_info_t *, ddi_detach_cmd_t);
124 static int mrsas_open(dev_t *, int, int, cred_t *);
125 static int mrsas_close(dev_t, int, int, cred_t *);
126 static int mrsas_ioctl(dev_t, int, intptr_t, int, cred_t *, int *);
127
128 static int mrsas_tran_tgt_init(dev_info_t *, dev_info_t *,
129 scsi_hba_tran_t *, struct scsi_device *);
130 static struct scsi_pkt *mrsas_tran_init_pkt(struct scsi_address *, register
131 struct scsi_pkt *, struct buf *, int, int, int, int,
132 int (*)(), caddr_t);
133 static int mrsas_tran_start(struct scsi_address *,
134 register struct scsi_pkt *);
135 static int mrsas_tran_abort(struct scsi_address *, struct scsi_pkt *);
136 static int mrsas_tran_reset(struct scsi_address *, int);
137 static int mrsas_tran_getcap(struct scsi_address *, char *, int);
138 static int mrsas_tran_setcap(struct scsi_address *, char *, int, int);
139 static void mrsas_tran_destroy_pkt(struct scsi_address *,
140 struct scsi_pkt *);
141 static void mrsas_tran_dmafree(struct scsi_address *, struct scsi_pkt *);
142 static void mrsas_tran_sync_pkt(struct scsi_address *, struct scsi_pkt *);
143 static int mrsas_tran_quiesce(dev_info_t *dip);
144 static int mrsas_tran_unquiesce(dev_info_t *dip);
145 static uint_t mrsas_isr();
146 static uint_t mrsas_softintr();
147 static void mrsas_undo_resources(dev_info_t *, struct mrsas_instance *);
148
149 static void free_space_for_mfi(struct mrsas_instance *);
150 static uint32_t read_fw_status_reg_ppc(struct mrsas_instance *);
151 static void issue_cmd_ppc(struct mrsas_cmd *, struct mrsas_instance *);
152 static int issue_cmd_in_poll_mode_ppc(struct mrsas_instance *,
153 struct mrsas_cmd *);
154 static int issue_cmd_in_sync_mode_ppc(struct mrsas_instance *,
155 struct mrsas_cmd *);
156 static void enable_intr_ppc(struct mrsas_instance *);
157 static void disable_intr_ppc(struct mrsas_instance *);
158 static int intr_ack_ppc(struct mrsas_instance *);
159 static void flush_cache(struct mrsas_instance *instance);
160 void display_scsi_inquiry(caddr_t);
161 static int start_mfi_aen(struct mrsas_instance *instance);
162 static int handle_drv_ioctl(struct mrsas_instance *instance,
163 struct mrsas_ioctl *ioctl, int mode);
164 static int handle_mfi_ioctl(struct mrsas_instance *instance,
165 struct mrsas_ioctl *ioctl, int mode);
166 static int handle_mfi_aen(struct mrsas_instance *instance,
167 struct mrsas_aen *aen);
168 static struct mrsas_cmd *build_cmd(struct mrsas_instance *,
169 struct scsi_address *, struct scsi_pkt *, uchar_t *);
170 static int alloc_additional_dma_buffer(struct mrsas_instance *);
171 static void complete_cmd_in_sync_mode(struct mrsas_instance *,
172 struct mrsas_cmd *);
173 static int mrsas_kill_adapter(struct mrsas_instance *);
174 static int mrsas_issue_init_mfi(struct mrsas_instance *);
175 static int mrsas_reset_ppc(struct mrsas_instance *);
176 static uint32_t mrsas_initiate_ocr_if_fw_is_faulty(struct mrsas_instance *);
177 static int wait_for_outstanding(struct mrsas_instance *instance);
178 static int register_mfi_aen(struct mrsas_instance *instance,
179 uint32_t seq_num, uint32_t class_locale_word);
180 static int issue_mfi_pthru(struct mrsas_instance *instance, struct
181 mrsas_ioctl *ioctl, struct mrsas_cmd *cmd, int mode);
182 static int issue_mfi_dcmd(struct mrsas_instance *instance, struct
183 mrsas_ioctl *ioctl, struct mrsas_cmd *cmd, int mode);
184 static int issue_mfi_smp(struct mrsas_instance *instance, struct
185 mrsas_ioctl *ioctl, struct mrsas_cmd *cmd, int mode);
186 static int issue_mfi_stp(struct mrsas_instance *instance, struct
187 mrsas_ioctl *ioctl, struct mrsas_cmd *cmd, int mode);
188 static int abort_aen_cmd(struct mrsas_instance *instance,
189 struct mrsas_cmd *cmd_to_abort);
190
191 static void mrsas_rem_intrs(struct mrsas_instance *instance);
192 static int mrsas_add_intrs(struct mrsas_instance *instance, int intr_type);
193
194 static void mrsas_tran_tgt_free(dev_info_t *, dev_info_t *,
195 scsi_hba_tran_t *, struct scsi_device *);
196 static int mrsas_tran_bus_config(dev_info_t *, uint_t,
197 ddi_bus_config_op_t, void *, dev_info_t **);
198 static int mrsas_parse_devname(char *, int *, int *);
199 static int mrsas_config_all_devices(struct mrsas_instance *);
200 static int mrsas_config_ld(struct mrsas_instance *, uint16_t,
201 uint8_t, dev_info_t **);
202 static int mrsas_name_node(dev_info_t *, char *, int);
203 static void mrsas_issue_evt_taskq(struct mrsas_eventinfo *);
204 static void free_additional_dma_buffer(struct mrsas_instance *);
205 static void io_timeout_checker(void *);
206 static void mrsas_fm_init(struct mrsas_instance *);
207 static void mrsas_fm_fini(struct mrsas_instance *);
208
209 static struct mrsas_function_template mrsas_function_template_ppc = {
210 .read_fw_status_reg = read_fw_status_reg_ppc,
211 .issue_cmd = issue_cmd_ppc,
212 .issue_cmd_in_sync_mode = issue_cmd_in_sync_mode_ppc,
213 .issue_cmd_in_poll_mode = issue_cmd_in_poll_mode_ppc,
214 .enable_intr = enable_intr_ppc,
215 .disable_intr = disable_intr_ppc,
216 .intr_ack = intr_ack_ppc,
217 .init_adapter = mrsas_init_adapter_ppc
218 };
219
220
221 static struct mrsas_function_template mrsas_function_template_fusion = {
222 .read_fw_status_reg = tbolt_read_fw_status_reg,
223 .issue_cmd = tbolt_issue_cmd,
224 .issue_cmd_in_sync_mode = tbolt_issue_cmd_in_sync_mode,
225 .issue_cmd_in_poll_mode = tbolt_issue_cmd_in_poll_mode,
226 .enable_intr = tbolt_enable_intr,
227 .disable_intr = tbolt_disable_intr,
228 .intr_ack = tbolt_intr_ack,
229 .init_adapter = mrsas_init_adapter_tbolt
230 };
231
232
233 ddi_dma_attr_t mrsas_generic_dma_attr = {
234 DMA_ATTR_V0, /* dma_attr_version */
235 0, /* low DMA address range */
236 0xFFFFFFFFU, /* high DMA address range */
237 0xFFFFFFFFU, /* DMA counter register */
238 8, /* DMA address alignment */
239 0x07, /* DMA burstsizes */
240 1, /* min DMA size */
241 0xFFFFFFFFU, /* max DMA size */
242 0xFFFFFFFFU, /* segment boundary */
243 MRSAS_MAX_SGE_CNT, /* dma_attr_sglen */
244 512, /* granularity of device */
245 0 /* bus specific DMA flags */
246 };
247
248 int32_t mrsas_max_cap_maxxfer = 0x1000000;
249
250 /*
251 * Fix for: Thunderbolt controller IO timeout when IO write size is 1MEG,
252 * Limit size to 256K
253 */
254 uint32_t mrsas_tbolt_max_cap_maxxfer = (512 * 512);
255
256 /*
257 * cb_ops contains base level routines
258 */
259 static struct cb_ops mrsas_cb_ops = {
260 mrsas_open, /* open */
261 mrsas_close, /* close */
262 nodev, /* strategy */
263 nodev, /* print */
264 nodev, /* dump */
265 nodev, /* read */
266 nodev, /* write */
267 mrsas_ioctl, /* ioctl */
268 nodev, /* devmap */
269 nodev, /* mmap */
270 nodev, /* segmap */
271 nochpoll, /* poll */
272 nodev, /* cb_prop_op */
273 0, /* streamtab */
274 D_NEW | D_HOTPLUG, /* cb_flag */
275 CB_REV, /* cb_rev */
276 nodev, /* cb_aread */
277 nodev /* cb_awrite */
278 };
279
280 /*
281 * dev_ops contains configuration routines
282 */
283 static struct dev_ops mrsas_ops = {
284 DEVO_REV, /* rev, */
285 0, /* refcnt */
286 mrsas_getinfo, /* getinfo */
287 nulldev, /* identify */
288 nulldev, /* probe */
289 mrsas_attach, /* attach */
290 mrsas_detach, /* detach */
291 #ifdef __sparc
292 mrsas_reset, /* reset */
293 #else /* __sparc */
294 nodev,
295 #endif /* __sparc */
296 &mrsas_cb_ops, /* char/block ops */
297 NULL, /* bus ops */
298 NULL, /* power */
299 #ifdef __sparc
300 ddi_quiesce_not_needed
301 #else /* __sparc */
302 mrsas_quiesce /* quiesce */
303 #endif /* __sparc */
304 };
305
306 static struct modldrv modldrv = {
307 &mod_driverops, /* module type - driver */
308 MRSAS_VERSION,
309 &mrsas_ops, /* driver ops */
310 };
311
312 static struct modlinkage modlinkage = {
313 MODREV_1, /* ml_rev - must be MODREV_1 */
314 &modldrv, /* ml_linkage */
315 NULL /* end of driver linkage */
316 };
317
318 static struct ddi_device_acc_attr endian_attr = {
319 DDI_DEVICE_ATTR_V1,
320 DDI_STRUCTURE_LE_ACC,
321 DDI_STRICTORDER_ACC,
322 DDI_DEFAULT_ACC
323 };
324
325 /* Use the LSI Fast Path for the 2208 (tbolt) commands. */
326 unsigned int enable_fp = 1;
327
328
329 /*
330 * ************************************************************************** *
331 * *
332 * common entry points - for loadable kernel modules *
333 * *
334 * ************************************************************************** *
335 */
336
337 /*
338 * _init - initialize a loadable module
339 * @void
340 *
341 * The driver should perform any one-time resource allocation or data
342 * initialization during driver loading in _init(). For example, the driver
343 * should initialize any mutexes global to the driver in this routine.
344 * The driver should not, however, use _init() to allocate or initialize
345 * anything that has to do with a particular instance of the device.
346 * Per-instance initialization must be done in attach().
347 */
348 int
349 _init(void)
350 {
351 int ret;
352
353 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__));
354
355 ret = ddi_soft_state_init(&mrsas_state,
356 sizeof (struct mrsas_instance), 0);
357
358 if (ret != DDI_SUCCESS) {
359 cmn_err(CE_WARN, "mr_sas: could not init state");
360 return (ret);
361 }
362
363 if ((ret = scsi_hba_init(&modlinkage)) != DDI_SUCCESS) {
364 cmn_err(CE_WARN, "mr_sas: could not init scsi hba");
365 ddi_soft_state_fini(&mrsas_state);
366 return (ret);
367 }
368
369 ret = mod_install(&modlinkage);
370
371 if (ret != DDI_SUCCESS) {
372 cmn_err(CE_WARN, "mr_sas: mod_install failed");
373 scsi_hba_fini(&modlinkage);
374 ddi_soft_state_fini(&mrsas_state);
375 }
376
377 return (ret);
378 }
379
380 /*
381 * _info - returns information about a loadable module.
382 * @void
383 *
384 * _info() is called to return module information. This is a typical entry
385 * point that does predefined role. It simply calls mod_info().
386 */
387 int
388 _info(struct modinfo *modinfop)
389 {
390 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__));
391
392 return (mod_info(&modlinkage, modinfop));
393 }
394
395 /*
396 * _fini - prepare a loadable module for unloading
397 * @void
398 *
399 * In _fini(), the driver should release any resources that were allocated in
400 * _init(). The driver must remove itself from the system module list.
401 */
402 int
403 _fini(void)
404 {
405 int ret;
406
407 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__));
408
409 if ((ret = mod_remove(&modlinkage)) != DDI_SUCCESS) {
410 con_log(CL_ANN1,
411 (CE_WARN, "_fini: mod_remove() failed, error 0x%X", ret));
412 return (ret);
413 }
414
415 scsi_hba_fini(&modlinkage);
416 con_log(CL_DLEVEL1, (CE_NOTE, "_fini: scsi_hba_fini() done."));
417
418 ddi_soft_state_fini(&mrsas_state);
419 con_log(CL_DLEVEL1, (CE_NOTE, "_fini: ddi_soft_state_fini() done."));
420
421 return (ret);
422 }
423
424
425 /*
426 * ************************************************************************** *
427 * *
428 * common entry points - for autoconfiguration *
429 * *
430 * ************************************************************************** *
431 */
432 /*
433 * attach - adds a device to the system as part of initialization
434 * @dip:
435 * @cmd:
436 *
437 * The kernel calls a driver's attach() entry point to attach an instance of
438 * a device (for MegaRAID, it is instance of a controller) or to resume
439 * operation for an instance of a device that has been suspended or has been
440 * shut down by the power management framework
441 * The attach() entry point typically includes the following types of
442 * processing:
443 * - allocate a soft-state structure for the device instance (for MegaRAID,
444 * controller instance)
445 * - initialize per-instance mutexes
446 * - initialize condition variables
447 * - register the device's interrupts (for MegaRAID, controller's interrupts)
448 * - map the registers and memory of the device instance (for MegaRAID,
449 * controller instance)
450 * - create minor device nodes for the device instance (for MegaRAID,
451 * controller instance)
452 * - report that the device instance (for MegaRAID, controller instance) has
453 * attached
454 */
455 static int
456 mrsas_attach(dev_info_t *dip, ddi_attach_cmd_t cmd)
457 {
458 int instance_no;
459 int nregs;
460 int i = 0;
461 uint8_t irq;
462 uint16_t vendor_id;
463 uint16_t device_id;
464 uint16_t subsysvid;
465 uint16_t subsysid;
466 uint16_t command;
467 off_t reglength = 0;
468 int intr_types = 0;
469 char *data;
470
471 scsi_hba_tran_t *tran;
472 ddi_dma_attr_t tran_dma_attr;
473 struct mrsas_instance *instance;
474
475 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__));
476
477 /* CONSTCOND */
478 ASSERT(NO_COMPETING_THREADS);
479
480 instance_no = ddi_get_instance(dip);
481
482 /*
483 * check to see whether this device is in a DMA-capable slot.
484 */
485 if (ddi_slaveonly(dip) == DDI_SUCCESS) {
486 dev_err(dip, CE_WARN, "Device in slave-only slot, unused");
487 return (DDI_FAILURE);
488 }
489
490 switch (cmd) {
491 case DDI_ATTACH:
492 /* allocate the soft state for the instance */
493 if (ddi_soft_state_zalloc(mrsas_state, instance_no)
494 != DDI_SUCCESS) {
495 dev_err(dip, CE_WARN, "Failed to allocate soft state");
496 return (DDI_FAILURE);
497 }
498
499 instance = (struct mrsas_instance *)ddi_get_soft_state
500 (mrsas_state, instance_no);
501
502 if (instance == NULL) {
503 dev_err(dip, CE_WARN, "Bad soft state");
504 ddi_soft_state_free(mrsas_state, instance_no);
505 return (DDI_FAILURE);
506 }
507
508 instance->unroll.softs = 1;
509
510 /* Setup the PCI configuration space handles */
511 if (pci_config_setup(dip, &instance->pci_handle) !=
512 DDI_SUCCESS) {
513 dev_err(dip, CE_WARN, "pci config setup failed");
514
515 ddi_soft_state_free(mrsas_state, instance_no);
516 return (DDI_FAILURE);
517 }
518
519 if (ddi_dev_nregs(dip, &nregs) != DDI_SUCCESS) {
520 dev_err(dip, CE_WARN, "Failed to get registers");
521
522 pci_config_teardown(&instance->pci_handle);
523 ddi_soft_state_free(mrsas_state, instance_no);
524 return (DDI_FAILURE);
525 }
526
527 vendor_id = pci_config_get16(instance->pci_handle,
528 PCI_CONF_VENID);
529 device_id = pci_config_get16(instance->pci_handle,
530 PCI_CONF_DEVID);
531
532 subsysvid = pci_config_get16(instance->pci_handle,
533 PCI_CONF_SUBVENID);
534 subsysid = pci_config_get16(instance->pci_handle,
535 PCI_CONF_SUBSYSID);
536
537 pci_config_put16(instance->pci_handle, PCI_CONF_COMM,
538 (pci_config_get16(instance->pci_handle,
539 PCI_CONF_COMM) | PCI_COMM_ME));
540 irq = pci_config_get8(instance->pci_handle,
541 PCI_CONF_ILINE);
542
543 dev_err(dip, CE_CONT,
544 "?0x%x:0x%x 0x%x:0x%x, irq:%d drv-ver:%s\n",
545 vendor_id, device_id, subsysvid,
546 subsysid, irq, MRSAS_VERSION);
547
548 /* enable bus-mastering */
549 command = pci_config_get16(instance->pci_handle,
550 PCI_CONF_COMM);
551
552 if (!(command & PCI_COMM_ME)) {
553 command |= PCI_COMM_ME;
554
555 pci_config_put16(instance->pci_handle,
556 PCI_CONF_COMM, command);
557
558 con_log(CL_ANN, (CE_CONT, "mr_sas%d: "
559 "enable bus-mastering", instance_no));
560 } else {
561 con_log(CL_DLEVEL1, (CE_CONT, "mr_sas%d: "
562 "bus-mastering already set", instance_no));
563 }
564
565 /* initialize function pointers */
566 switch (device_id) {
567 case PCI_DEVICE_ID_LSI_INVADER:
568 case PCI_DEVICE_ID_LSI_FURY:
569 case PCI_DEVICE_ID_LSI_INTRUDER:
570 case PCI_DEVICE_ID_LSI_INTRUDER_24:
571 case PCI_DEVICE_ID_LSI_CUTLASS_52:
572 case PCI_DEVICE_ID_LSI_CUTLASS_53:
573 dev_err(dip, CE_CONT, "?Gen3 device detected\n");
574 instance->gen3 = 1;
575 /* FALLTHROUGH */
576 case PCI_DEVICE_ID_LSI_TBOLT:
577 dev_err(dip, CE_CONT, "?TBOLT device detected\n");
578
579 instance->func_ptr =
580 &mrsas_function_template_fusion;
581 instance->tbolt = 1;
582 break;
583
584 case PCI_DEVICE_ID_LSI_SKINNY:
585 case PCI_DEVICE_ID_LSI_SKINNY_NEW:
586 /*
587 * FALLTHRU to PPC-style functions, but mark this
588 * instance as Skinny, because the register set is
589 * slightly different (See WR_IB_PICK_QPORT), and
590 * certain other features are available to a Skinny
591 * HBA.
592 */
593 dev_err(dip, CE_CONT, "?Skinny device detected\n");
594 instance->skinny = 1;
595 /* FALLTHRU */
596
597 case PCI_DEVICE_ID_LSI_2108VDE:
598 case PCI_DEVICE_ID_LSI_2108V:
599 dev_err(dip, CE_CONT,
600 "?2108 Liberator device detected\n");
601
602 instance->func_ptr =
603 &mrsas_function_template_ppc;
604 break;
605
606 default:
607 dev_err(dip, CE_WARN, "Invalid device detected");
608
609 pci_config_teardown(&instance->pci_handle);
610 ddi_soft_state_free(mrsas_state, instance_no);
611 return (DDI_FAILURE);
612 }
613
614 instance->baseaddress = pci_config_get32(
615 instance->pci_handle, PCI_CONF_BASE0);
616 instance->baseaddress &= 0x0fffc;
617
618 instance->dip = dip;
619 instance->vendor_id = vendor_id;
620 instance->device_id = device_id;
621 instance->subsysvid = subsysvid;
622 instance->subsysid = subsysid;
623 instance->instance = instance_no;
624
625 /* Initialize FMA */
626 instance->fm_capabilities = ddi_prop_get_int(
627 DDI_DEV_T_ANY, instance->dip, DDI_PROP_DONTPASS,
628 "fm-capable", DDI_FM_EREPORT_CAPABLE |
629 DDI_FM_ACCCHK_CAPABLE | DDI_FM_DMACHK_CAPABLE
630 | DDI_FM_ERRCB_CAPABLE);
631
632 mrsas_fm_init(instance);
633
634 /* Setup register map */
635 if ((ddi_dev_regsize(instance->dip,
636 REGISTER_SET_IO_2108, ®length) != DDI_SUCCESS) ||
637 reglength < MINIMUM_MFI_MEM_SZ) {
638 goto fail_attach;
639 }
640 if (reglength > DEFAULT_MFI_MEM_SZ) {
641 reglength = DEFAULT_MFI_MEM_SZ;
642 con_log(CL_DLEVEL1, (CE_NOTE,
643 "mr_sas: register length to map is 0x%lx bytes",
644 reglength));
645 }
646 if (ddi_regs_map_setup(instance->dip,
647 REGISTER_SET_IO_2108, &instance->regmap, 0,
648 reglength, &endian_attr, &instance->regmap_handle)
649 != DDI_SUCCESS) {
650 dev_err(dip, CE_WARN, "couldn't map control registers");
651 goto fail_attach;
652 }
653
654 instance->unroll.regs = 1;
655
656 /*
657 * Disable Interrupt Now.
658 * Setup Software interrupt
659 */
660 instance->func_ptr->disable_intr(instance);
661
662 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, dip, 0,
663 "mrsas-enable-msi", &data) == DDI_SUCCESS) {
664 if (strncmp(data, "no", 3) == 0) {
665 msi_enable = 0;
666 con_log(CL_ANN1, (CE_WARN,
667 "msi_enable = %d disabled", msi_enable));
668 }
669 ddi_prop_free(data);
670 }
671
672 dev_err(dip, CE_CONT, "?msi_enable = %d\n", msi_enable);
673
674 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, dip, 0,
675 "mrsas-enable-fp", &data) == DDI_SUCCESS) {
676 if (strncmp(data, "no", 3) == 0) {
677 enable_fp = 0;
678 dev_err(dip, CE_NOTE,
679 "enable_fp = %d, Fast-Path disabled.\n",
680 enable_fp);
681 }
682
683 ddi_prop_free(data);
684 }
685
686 dev_err(dip, CE_CONT, "?enable_fp = %d\n", enable_fp);
687
688 /* Check for all supported interrupt types */
689 if (ddi_intr_get_supported_types(
690 dip, &intr_types) != DDI_SUCCESS) {
691 dev_err(dip, CE_WARN,
692 "ddi_intr_get_supported_types() failed");
693 goto fail_attach;
694 }
695
696 con_log(CL_DLEVEL1, (CE_NOTE,
697 "ddi_intr_get_supported_types() ret: 0x%x", intr_types));
698
699 /* Initialize and Setup Interrupt handler */
700 if (msi_enable && (intr_types & DDI_INTR_TYPE_MSIX)) {
701 if (mrsas_add_intrs(instance, DDI_INTR_TYPE_MSIX) !=
702 DDI_SUCCESS) {
703 dev_err(dip, CE_WARN,
704 "MSIX interrupt query failed");
705 goto fail_attach;
706 }
707 instance->intr_type = DDI_INTR_TYPE_MSIX;
708 } else if (msi_enable && (intr_types & DDI_INTR_TYPE_MSI)) {
709 if (mrsas_add_intrs(instance, DDI_INTR_TYPE_MSI) !=
710 DDI_SUCCESS) {
711 dev_err(dip, CE_WARN,
712 "MSI interrupt query failed");
713 goto fail_attach;
714 }
715 instance->intr_type = DDI_INTR_TYPE_MSI;
716 } else if (intr_types & DDI_INTR_TYPE_FIXED) {
717 msi_enable = 0;
718 if (mrsas_add_intrs(instance, DDI_INTR_TYPE_FIXED) !=
719 DDI_SUCCESS) {
720 dev_err(dip, CE_WARN,
721 "FIXED interrupt query failed");
722 goto fail_attach;
723 }
724 instance->intr_type = DDI_INTR_TYPE_FIXED;
725 } else {
726 dev_err(dip, CE_WARN, "Device cannot "
727 "suppport either FIXED or MSI/X "
728 "interrupts");
729 goto fail_attach;
730 }
731
732 instance->unroll.intr = 1;
733
734 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, dip, 0,
735 "mrsas-enable-ctio", &data) == DDI_SUCCESS) {
736 if (strncmp(data, "no", 3) == 0) {
737 ctio_enable = 0;
738 con_log(CL_ANN1, (CE_WARN,
739 "ctio_enable = %d disabled", ctio_enable));
740 }
741 ddi_prop_free(data);
742 }
743
744 dev_err(dip, CE_CONT, "?ctio_enable = %d\n", ctio_enable);
745
746 /* setup the mfi based low level driver */
747 if (mrsas_init_adapter(instance) != DDI_SUCCESS) {
748 dev_err(dip, CE_WARN,
749 "could not initialize the low level driver");
750
751 goto fail_attach;
752 }
753
754 /* Initialize all Mutex */
755 INIT_LIST_HEAD(&instance->completed_pool_list);
756 mutex_init(&instance->completed_pool_mtx, NULL,
757 MUTEX_DRIVER, DDI_INTR_PRI(instance->intr_pri));
758
759 mutex_init(&instance->sync_map_mtx, NULL,
760 MUTEX_DRIVER, DDI_INTR_PRI(instance->intr_pri));
761
762 mutex_init(&instance->app_cmd_pool_mtx, NULL,
763 MUTEX_DRIVER, DDI_INTR_PRI(instance->intr_pri));
764
765 mutex_init(&instance->config_dev_mtx, NULL,
766 MUTEX_DRIVER, DDI_INTR_PRI(instance->intr_pri));
767
768 mutex_init(&instance->cmd_pend_mtx, NULL,
769 MUTEX_DRIVER, DDI_INTR_PRI(instance->intr_pri));
770
771 mutex_init(&instance->ocr_flags_mtx, NULL,
772 MUTEX_DRIVER, DDI_INTR_PRI(instance->intr_pri));
773
774 mutex_init(&instance->int_cmd_mtx, NULL,
775 MUTEX_DRIVER, DDI_INTR_PRI(instance->intr_pri));
776 cv_init(&instance->int_cmd_cv, NULL, CV_DRIVER, NULL);
777
778 mutex_init(&instance->cmd_pool_mtx, NULL,
779 MUTEX_DRIVER, DDI_INTR_PRI(instance->intr_pri));
780
781 mutex_init(&instance->reg_write_mtx, NULL,
782 MUTEX_DRIVER, DDI_INTR_PRI(instance->intr_pri));
783
784 if (instance->tbolt) {
785 mutex_init(&instance->cmd_app_pool_mtx, NULL,
786 MUTEX_DRIVER, DDI_INTR_PRI(instance->intr_pri));
787
788 mutex_init(&instance->chip_mtx, NULL,
789 MUTEX_DRIVER, DDI_INTR_PRI(instance->intr_pri));
790
791 }
792
793 instance->unroll.mutexs = 1;
794
795 instance->timeout_id = (timeout_id_t)-1;
796
797 /* Register our soft-isr for highlevel interrupts. */
798 instance->isr_level = instance->intr_pri;
799 if (!(instance->tbolt)) {
800 if (instance->isr_level == HIGH_LEVEL_INTR) {
801 if (ddi_add_softintr(dip,
802 DDI_SOFTINT_HIGH,
803 &instance->soft_intr_id, NULL, NULL,
804 mrsas_softintr, (caddr_t)instance) !=
805 DDI_SUCCESS) {
806 dev_err(dip, CE_WARN,
807 "Software ISR did not register");
808
809 goto fail_attach;
810 }
811
812 instance->unroll.soft_isr = 1;
813
814 }
815 }
816
817 instance->softint_running = 0;
818
819 /* Allocate a transport structure */
820 tran = scsi_hba_tran_alloc(dip, SCSI_HBA_CANSLEEP);
821
822 if (tran == NULL) {
823 dev_err(dip, CE_WARN,
824 "scsi_hba_tran_alloc failed");
825 goto fail_attach;
826 }
827
828 instance->tran = tran;
829 instance->unroll.tran = 1;
830
831 tran->tran_hba_private = instance;
832 tran->tran_tgt_init = mrsas_tran_tgt_init;
833 tran->tran_tgt_probe = scsi_hba_probe;
834 tran->tran_tgt_free = mrsas_tran_tgt_free;
835 tran->tran_init_pkt = mrsas_tran_init_pkt;
836 if (instance->tbolt)
837 tran->tran_start = mrsas_tbolt_tran_start;
838 else
839 tran->tran_start = mrsas_tran_start;
840 tran->tran_abort = mrsas_tran_abort;
841 tran->tran_reset = mrsas_tran_reset;
842 tran->tran_getcap = mrsas_tran_getcap;
843 tran->tran_setcap = mrsas_tran_setcap;
844 tran->tran_destroy_pkt = mrsas_tran_destroy_pkt;
845 tran->tran_dmafree = mrsas_tran_dmafree;
846 tran->tran_sync_pkt = mrsas_tran_sync_pkt;
847 tran->tran_quiesce = mrsas_tran_quiesce;
848 tran->tran_unquiesce = mrsas_tran_unquiesce;
849 tran->tran_bus_config = mrsas_tran_bus_config;
850
851 if (mrsas_relaxed_ordering)
852 mrsas_generic_dma_attr.dma_attr_flags |=
853 DDI_DMA_RELAXED_ORDERING;
854
855
856 tran_dma_attr = mrsas_generic_dma_attr;
857 tran_dma_attr.dma_attr_sgllen = instance->max_num_sge;
858
859 /* Attach this instance of the hba */
860 if (scsi_hba_attach_setup(dip, &tran_dma_attr, tran, 0)
861 != DDI_SUCCESS) {
862 dev_err(dip, CE_WARN,
863 "scsi_hba_attach failed");
864
865 goto fail_attach;
866 }
867 instance->unroll.tranSetup = 1;
868 con_log(CL_ANN1,
869 (CE_CONT, "scsi_hba_attach_setup() done."));
870
871 /* create devctl node for cfgadm command */
872 if (ddi_create_minor_node(dip, "devctl",
873 S_IFCHR, INST2DEVCTL(instance_no),
874 DDI_NT_SCSI_NEXUS, 0) == DDI_FAILURE) {
875 dev_err(dip, CE_WARN, "failed to create devctl node.");
876
877 goto fail_attach;
878 }
879
880 instance->unroll.devctl = 1;
881
882 /* create scsi node for cfgadm command */
883 if (ddi_create_minor_node(dip, "scsi", S_IFCHR,
884 INST2SCSI(instance_no), DDI_NT_SCSI_ATTACHMENT_POINT, 0) ==
885 DDI_FAILURE) {
886 dev_err(dip, CE_WARN, "failed to create scsi node.");
887
888 goto fail_attach;
889 }
890
891 instance->unroll.scsictl = 1;
892
893 (void) snprintf(instance->iocnode, sizeof (instance->iocnode),
894 "%d:lsirdctl", instance_no);
895
896 /*
897 * Create a node for applications
898 * for issuing ioctl to the driver.
899 */
900 if (ddi_create_minor_node(dip, instance->iocnode,
901 S_IFCHR, INST2LSIRDCTL(instance_no), DDI_PSEUDO, 0) ==
902 DDI_FAILURE) {
903 dev_err(dip, CE_WARN, "failed to create ioctl node.");
904
905 goto fail_attach;
906 }
907
908 instance->unroll.ioctl = 1;
909
910 /* Create a taskq to handle dr events */
911 if ((instance->taskq = ddi_taskq_create(dip,
912 "mrsas_dr_taskq", 1, TASKQ_DEFAULTPRI, 0)) == NULL) {
913 dev_err(dip, CE_WARN, "failed to create taskq.");
914 instance->taskq = NULL;
915 goto fail_attach;
916 }
917 instance->unroll.taskq = 1;
918 con_log(CL_ANN1, (CE_CONT, "ddi_taskq_create() done."));
919
920 /* enable interrupt */
921 instance->func_ptr->enable_intr(instance);
922
923 /* initiate AEN */
924 if (start_mfi_aen(instance)) {
925 dev_err(dip, CE_WARN, "failed to initiate AEN.");
926 goto fail_attach;
927 }
928 instance->unroll.aenPend = 1;
929 con_log(CL_ANN1,
930 (CE_CONT, "AEN started for instance %d.", instance_no));
931
932 /* Finally! We are on the air. */
933 ddi_report_dev(dip);
934
935 /* FMA handle checking. */
936 if (mrsas_check_acc_handle(instance->regmap_handle) !=
937 DDI_SUCCESS) {
938 goto fail_attach;
939 }
940 if (mrsas_check_acc_handle(instance->pci_handle) !=
941 DDI_SUCCESS) {
942 goto fail_attach;
943 }
944
945 instance->mr_ld_list =
946 kmem_zalloc(MRDRV_MAX_LD * sizeof (struct mrsas_ld),
947 KM_SLEEP);
948 instance->unroll.ldlist_buff = 1;
949
950 if (instance->tbolt || instance->skinny) {
951 instance->mr_tbolt_pd_max = MRSAS_TBOLT_PD_TGT_MAX;
952 instance->mr_tbolt_pd_list =
953 kmem_zalloc(MRSAS_TBOLT_GET_PD_MAX(instance) *
954 sizeof (struct mrsas_tbolt_pd), KM_SLEEP);
955 ASSERT(instance->mr_tbolt_pd_list);
956 for (i = 0; i < instance->mr_tbolt_pd_max; i++) {
957 instance->mr_tbolt_pd_list[i].lun_type =
958 MRSAS_TBOLT_PD_LUN;
959 instance->mr_tbolt_pd_list[i].dev_id =
960 (uint8_t)i;
961 }
962
963 instance->unroll.pdlist_buff = 1;
964 }
965 break;
966 case DDI_PM_RESUME:
967 con_log(CL_ANN, (CE_NOTE, "mr_sas: DDI_PM_RESUME"));
968 break;
969 case DDI_RESUME:
970 con_log(CL_ANN, (CE_NOTE, "mr_sas: DDI_RESUME"));
971 break;
972 default:
973 con_log(CL_ANN,
974 (CE_WARN, "mr_sas: invalid attach cmd=%x", cmd));
975 return (DDI_FAILURE);
976 }
977
978
979 con_log(CL_DLEVEL1,
980 (CE_NOTE, "mrsas_attach() return SUCCESS instance_num %d",
981 instance_no));
982 return (DDI_SUCCESS);
983
984 fail_attach:
985
986 mrsas_undo_resources(dip, instance);
987
988 mrsas_fm_ereport(instance, DDI_FM_DEVICE_NO_RESPONSE);
989 ddi_fm_service_impact(instance->dip, DDI_SERVICE_LOST);
990
991 mrsas_fm_fini(instance);
992
993 pci_config_teardown(&instance->pci_handle);
994 ddi_soft_state_free(mrsas_state, instance_no);
995
996 return (DDI_FAILURE);
997 }
998
999 /*
1000 * getinfo - gets device information
1001 * @dip:
1002 * @cmd:
1003 * @arg:
1004 * @resultp:
1005 *
1006 * The system calls getinfo() to obtain configuration information that only
1007 * the driver knows. The mapping of minor numbers to device instance is
1008 * entirely under the control of the driver. The system sometimes needs to ask
1009 * the driver which device a particular dev_t represents.
1010 * Given the device number return the devinfo pointer from the scsi_device
1011 * structure.
1012 */
1013 /*ARGSUSED*/
1014 static int
1015 mrsas_getinfo(dev_info_t *dip, ddi_info_cmd_t cmd, void *arg, void **resultp)
1016 {
1017 int rval;
1018 int mrsas_minor = getminor((dev_t)arg);
1019
1020 struct mrsas_instance *instance;
1021
1022 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__));
1023
1024 switch (cmd) {
1025 case DDI_INFO_DEVT2DEVINFO:
1026 instance = (struct mrsas_instance *)
1027 ddi_get_soft_state(mrsas_state,
1028 MINOR2INST(mrsas_minor));
1029
1030 if (instance == NULL) {
1031 *resultp = NULL;
1032 rval = DDI_FAILURE;
1033 } else {
1034 *resultp = instance->dip;
1035 rval = DDI_SUCCESS;
1036 }
1037 break;
1038 case DDI_INFO_DEVT2INSTANCE:
1039 *resultp = (void *)(intptr_t)
1040 (MINOR2INST(getminor((dev_t)arg)));
1041 rval = DDI_SUCCESS;
1042 break;
1043 default:
1044 *resultp = NULL;
1045 rval = DDI_FAILURE;
1046 }
1047
1048 return (rval);
1049 }
1050
1051 /*
1052 * detach - detaches a device from the system
1053 * @dip: pointer to the device's dev_info structure
1054 * @cmd: type of detach
1055 *
1056 * A driver's detach() entry point is called to detach an instance of a device
1057 * that is bound to the driver. The entry point is called with the instance of
1058 * the device node to be detached and with DDI_DETACH, which is specified as
1059 * the cmd argument to the entry point.
1060 * This routine is called during driver unload. We free all the allocated
1061 * resources and call the corresponding LLD so that it can also release all
1062 * its resources.
1063 */
1064 static int
1065 mrsas_detach(dev_info_t *dip, ddi_detach_cmd_t cmd)
1066 {
1067 int instance_no;
1068
1069 struct mrsas_instance *instance;
1070
1071 con_log(CL_ANN, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__));
1072
1073
1074 /* CONSTCOND */
1075 ASSERT(NO_COMPETING_THREADS);
1076
1077 instance_no = ddi_get_instance(dip);
1078
1079 instance = (struct mrsas_instance *)ddi_get_soft_state(mrsas_state,
1080 instance_no);
1081
1082 if (!instance) {
1083 dev_err(dip, CE_WARN, "could not get instance in detach");
1084
1085 return (DDI_FAILURE);
1086 }
1087
1088 switch (cmd) {
1089 case DDI_DETACH:
1090 con_log(CL_ANN, (CE_NOTE,
1091 "mrsas_detach: DDI_DETACH"));
1092
1093 mutex_enter(&instance->config_dev_mtx);
1094 if (instance->timeout_id != (timeout_id_t)-1) {
1095 mutex_exit(&instance->config_dev_mtx);
1096 (void) untimeout(instance->timeout_id);
1097 instance->timeout_id = (timeout_id_t)-1;
1098 mutex_enter(&instance->config_dev_mtx);
1099 instance->unroll.timer = 0;
1100 }
1101 mutex_exit(&instance->config_dev_mtx);
1102
1103 if (instance->unroll.tranSetup == 1) {
1104 if (scsi_hba_detach(dip) != DDI_SUCCESS) {
1105 dev_err(dip, CE_WARN,
1106 "failed to detach");
1107 return (DDI_FAILURE);
1108 }
1109 instance->unroll.tranSetup = 0;
1110 con_log(CL_ANN1,
1111 (CE_CONT, "scsi_hba_dettach() done."));
1112 }
1113
1114 flush_cache(instance);
1115
1116 mrsas_undo_resources(dip, instance);
1117
1118 mrsas_fm_fini(instance);
1119
1120 pci_config_teardown(&instance->pci_handle);
1121 ddi_soft_state_free(mrsas_state, instance_no);
1122 break;
1123
1124 case DDI_PM_SUSPEND:
1125 con_log(CL_ANN, (CE_NOTE,
1126 "mrsas_detach: DDI_PM_SUSPEND"));
1127
1128 break;
1129 case DDI_SUSPEND:
1130 con_log(CL_ANN, (CE_NOTE,
1131 "mrsas_detach: DDI_SUSPEND"));
1132
1133 break;
1134 default:
1135 con_log(CL_ANN, (CE_WARN,
1136 "invalid detach command:0x%x", cmd));
1137 return (DDI_FAILURE);
1138 }
1139
1140 return (DDI_SUCCESS);
1141 }
1142
1143
1144 static void
1145 mrsas_undo_resources(dev_info_t *dip, struct mrsas_instance *instance)
1146 {
1147 con_log(CL_ANN, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__));
1148
1149 if (instance->unroll.ioctl == 1) {
1150 ddi_remove_minor_node(dip, instance->iocnode);
1151 instance->unroll.ioctl = 0;
1152 }
1153
1154 if (instance->unroll.scsictl == 1) {
1155 ddi_remove_minor_node(dip, "scsi");
1156 instance->unroll.scsictl = 0;
1157 }
1158
1159 if (instance->unroll.devctl == 1) {
1160 ddi_remove_minor_node(dip, "devctl");
1161 instance->unroll.devctl = 0;
1162 }
1163
1164 if (instance->unroll.tranSetup == 1) {
1165 if (scsi_hba_detach(dip) != DDI_SUCCESS) {
1166 dev_err(dip, CE_WARN, "failed to detach");
1167 return; /* DDI_FAILURE */
1168 }
1169 instance->unroll.tranSetup = 0;
1170 con_log(CL_ANN1, (CE_CONT, "scsi_hba_dettach() done."));
1171 }
1172
1173 if (instance->unroll.tran == 1) {
1174 scsi_hba_tran_free(instance->tran);
1175 instance->unroll.tran = 0;
1176 con_log(CL_ANN1, (CE_CONT, "scsi_hba_tran_free() done."));
1177 }
1178
1179 if (instance->unroll.syncCmd == 1) {
1180 if (instance->tbolt) {
1181 if (abort_syncmap_cmd(instance,
1182 instance->map_update_cmd)) {
1183 dev_err(dip, CE_WARN, "mrsas_detach: "
1184 "failed to abort previous syncmap command");
1185 }
1186
1187 instance->unroll.syncCmd = 0;
1188 con_log(CL_ANN1, (CE_CONT, "sync cmd aborted, done."));
1189 }
1190 }
1191
1192 if (instance->unroll.aenPend == 1) {
1193 if (abort_aen_cmd(instance, instance->aen_cmd))
1194 dev_err(dip, CE_WARN, "mrsas_detach: "
1195 "failed to abort prevous AEN command");
1196
1197 instance->unroll.aenPend = 0;
1198 con_log(CL_ANN1, (CE_CONT, "aen cmd aborted, done."));
1199 /* This means the controller is fully initialized and running */
1200 /* Shutdown should be a last command to controller. */
1201 /* shutdown_controller(); */
1202 }
1203
1204
1205 if (instance->unroll.timer == 1) {
1206 if (instance->timeout_id != (timeout_id_t)-1) {
1207 (void) untimeout(instance->timeout_id);
1208 instance->timeout_id = (timeout_id_t)-1;
1209
1210 instance->unroll.timer = 0;
1211 }
1212 }
1213
1214 instance->func_ptr->disable_intr(instance);
1215
1216
1217 if (instance->unroll.mutexs == 1) {
1218 mutex_destroy(&instance->cmd_pool_mtx);
1219 mutex_destroy(&instance->app_cmd_pool_mtx);
1220 mutex_destroy(&instance->cmd_pend_mtx);
1221 mutex_destroy(&instance->completed_pool_mtx);
1222 mutex_destroy(&instance->sync_map_mtx);
1223 mutex_destroy(&instance->int_cmd_mtx);
1224 cv_destroy(&instance->int_cmd_cv);
1225 mutex_destroy(&instance->config_dev_mtx);
1226 mutex_destroy(&instance->ocr_flags_mtx);
1227 mutex_destroy(&instance->reg_write_mtx);
1228
1229 if (instance->tbolt) {
1230 mutex_destroy(&instance->cmd_app_pool_mtx);
1231 mutex_destroy(&instance->chip_mtx);
1232 }
1233
1234 instance->unroll.mutexs = 0;
1235 con_log(CL_ANN1, (CE_CONT, "Destroy mutex & cv, done."));
1236 }
1237
1238
1239 if (instance->unroll.soft_isr == 1) {
1240 ddi_remove_softintr(instance->soft_intr_id);
1241 instance->unroll.soft_isr = 0;
1242 }
1243
1244 if (instance->unroll.intr == 1) {
1245 mrsas_rem_intrs(instance);
1246 instance->unroll.intr = 0;
1247 }
1248
1249
1250 if (instance->unroll.taskq == 1) {
1251 if (instance->taskq) {
1252 ddi_taskq_destroy(instance->taskq);
1253 instance->unroll.taskq = 0;
1254 }
1255
1256 }
1257
1258 /*
1259 * free dma memory allocated for
1260 * cmds/frames/queues/driver version etc
1261 */
1262 if (instance->unroll.verBuff == 1) {
1263 (void) mrsas_free_dma_obj(instance, instance->drv_ver_dma_obj);
1264 instance->unroll.verBuff = 0;
1265 }
1266
1267 if (instance->unroll.pdlist_buff == 1) {
1268 if (instance->mr_tbolt_pd_list != NULL) {
1269 kmem_free(instance->mr_tbolt_pd_list,
1270 MRSAS_TBOLT_GET_PD_MAX(instance) *
1271 sizeof (struct mrsas_tbolt_pd));
1272 }
1273
1274 instance->mr_tbolt_pd_list = NULL;
1275 instance->unroll.pdlist_buff = 0;
1276 }
1277
1278 if (instance->unroll.ldlist_buff == 1) {
1279 if (instance->mr_ld_list != NULL) {
1280 kmem_free(instance->mr_ld_list, MRDRV_MAX_LD
1281 * sizeof (struct mrsas_ld));
1282 }
1283
1284 instance->mr_ld_list = NULL;
1285 instance->unroll.ldlist_buff = 0;
1286 }
1287
1288 if (instance->tbolt) {
1289 if (instance->unroll.alloc_space_mpi2 == 1) {
1290 free_space_for_mpi2(instance);
1291 instance->unroll.alloc_space_mpi2 = 0;
1292 }
1293 } else {
1294 if (instance->unroll.alloc_space_mfi == 1) {
1295 free_space_for_mfi(instance);
1296 instance->unroll.alloc_space_mfi = 0;
1297 }
1298 }
1299
1300 if (instance->unroll.regs == 1) {
1301 ddi_regs_map_free(&instance->regmap_handle);
1302 instance->unroll.regs = 0;
1303 con_log(CL_ANN1, (CE_CONT, "ddi_regs_map_free() done."));
1304 }
1305 }
1306
1307
1308
1309 /*
1310 * ************************************************************************** *
1311 * *
1312 * common entry points - for character driver types *
1313 * *
1314 * ************************************************************************** *
1315 */
1316 /*
1317 * open - gets access to a device
1318 * @dev:
1319 * @openflags:
1320 * @otyp:
1321 * @credp:
1322 *
1323 * Access to a device by one or more application programs is controlled
1324 * through the open() and close() entry points. The primary function of
1325 * open() is to verify that the open request is allowed.
1326 */
1327 static int
1328 mrsas_open(dev_t *dev, int openflags, int otyp, cred_t *credp)
1329 {
1330 int rval = 0;
1331
1332 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__));
1333
1334 /* Check root permissions */
1335 if (drv_priv(credp) != 0) {
1336 con_log(CL_ANN, (CE_WARN,
1337 "mr_sas: Non-root ioctl access denied!"));
1338 return (EPERM);
1339 }
1340
1341 /* Verify we are being opened as a character device */
1342 if (otyp != OTYP_CHR) {
1343 con_log(CL_ANN, (CE_WARN,
1344 "mr_sas: ioctl node must be a char node"));
1345 return (EINVAL);
1346 }
1347
1348 if (ddi_get_soft_state(mrsas_state, MINOR2INST(getminor(*dev)))
1349 == NULL) {
1350 return (ENXIO);
1351 }
1352
1353 if (scsi_hba_open) {
1354 rval = scsi_hba_open(dev, openflags, otyp, credp);
1355 }
1356
1357 return (rval);
1358 }
1359
1360 /*
1361 * close - gives up access to a device
1362 * @dev:
1363 * @openflags:
1364 * @otyp:
1365 * @credp:
1366 *
1367 * close() should perform any cleanup necessary to finish using the minor
1368 * device, and prepare the device (and driver) to be opened again.
1369 */
1370 static int
1371 mrsas_close(dev_t dev, int openflags, int otyp, cred_t *credp)
1372 {
1373 int rval = 0;
1374
1375 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__));
1376
1377 /* no need for locks! */
1378
1379 if (scsi_hba_close) {
1380 rval = scsi_hba_close(dev, openflags, otyp, credp);
1381 }
1382
1383 return (rval);
1384 }
1385
1386 /*
1387 * ioctl - performs a range of I/O commands for character drivers
1388 * @dev:
1389 * @cmd:
1390 * @arg:
1391 * @mode:
1392 * @credp:
1393 * @rvalp:
1394 *
1395 * ioctl() routine must make sure that user data is copied into or out of the
1396 * kernel address space explicitly using copyin(), copyout(), ddi_copyin(),
1397 * and ddi_copyout(), as appropriate.
1398 * This is a wrapper routine to serialize access to the actual ioctl routine.
1399 * ioctl() should return 0 on success, or the appropriate error number. The
1400 * driver may also set the value returned to the calling process through rvalp.
1401 */
1402
1403 static int
1404 mrsas_ioctl(dev_t dev, int cmd, intptr_t arg, int mode, cred_t *credp,
1405 int *rvalp)
1406 {
1407 int rval = 0;
1408
1409 struct mrsas_instance *instance;
1410 struct mrsas_ioctl *ioctl;
1411 struct mrsas_aen aen;
1412 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__));
1413
1414 instance = ddi_get_soft_state(mrsas_state, MINOR2INST(getminor(dev)));
1415
1416 if (instance == NULL) {
1417 /* invalid minor number */
1418 con_log(CL_ANN, (CE_WARN, "mr_sas: adapter not found."));
1419 return (ENXIO);
1420 }
1421
1422 ioctl = (struct mrsas_ioctl *)kmem_zalloc(sizeof (struct mrsas_ioctl),
1423 KM_SLEEP);
1424 ASSERT(ioctl);
1425
1426 switch ((uint_t)cmd) {
1427 case MRSAS_IOCTL_FIRMWARE:
1428 if (ddi_copyin((void *)arg, ioctl,
1429 sizeof (struct mrsas_ioctl), mode)) {
1430 con_log(CL_ANN, (CE_WARN, "mrsas_ioctl: "
1431 "ERROR IOCTL copyin"));
1432 kmem_free(ioctl, sizeof (struct mrsas_ioctl));
1433 return (EFAULT);
1434 }
1435
1436 if (ioctl->control_code == MRSAS_DRIVER_IOCTL_COMMON) {
1437 rval = handle_drv_ioctl(instance, ioctl, mode);
1438 } else {
1439 rval = handle_mfi_ioctl(instance, ioctl, mode);
1440 }
1441
1442 if (ddi_copyout((void *)ioctl, (void *)arg,
1443 (sizeof (struct mrsas_ioctl) - 1), mode)) {
1444 con_log(CL_ANN, (CE_WARN,
1445 "mrsas_ioctl: copy_to_user failed"));
1446 rval = 1;
1447 }
1448
1449 break;
1450 case MRSAS_IOCTL_AEN:
1451 if (ddi_copyin((void *) arg, &aen,
1452 sizeof (struct mrsas_aen), mode)) {
1453 con_log(CL_ANN, (CE_WARN,
1454 "mrsas_ioctl: ERROR AEN copyin"));
1455 kmem_free(ioctl, sizeof (struct mrsas_ioctl));
1456 return (EFAULT);
1457 }
1458
1459 rval = handle_mfi_aen(instance, &aen);
1460
1461 if (ddi_copyout((void *) &aen, (void *)arg,
1462 sizeof (struct mrsas_aen), mode)) {
1463 con_log(CL_ANN, (CE_WARN,
1464 "mrsas_ioctl: copy_to_user failed"));
1465 rval = 1;
1466 }
1467
1468 break;
1469 default:
1470 rval = scsi_hba_ioctl(dev, cmd, arg,
1471 mode, credp, rvalp);
1472
1473 con_log(CL_DLEVEL1, (CE_NOTE, "mrsas_ioctl: "
1474 "scsi_hba_ioctl called, ret = %x.", rval));
1475 }
1476
1477 kmem_free(ioctl, sizeof (struct mrsas_ioctl));
1478 return (rval);
1479 }
1480
1481 /*
1482 * ************************************************************************** *
1483 * *
1484 * common entry points - for block driver types *
1485 * *
1486 * ************************************************************************** *
1487 */
1488 #ifdef __sparc
1489 /*
1490 * reset - TBD
1491 * @dip:
1492 * @cmd:
1493 *
1494 * TBD
1495 */
1496 /*ARGSUSED*/
1497 static int
1498 mrsas_reset(dev_info_t *dip, ddi_reset_cmd_t cmd)
1499 {
1500 int instance_no;
1501
1502 struct mrsas_instance *instance;
1503
1504 instance_no = ddi_get_instance(dip);
1505 instance = (struct mrsas_instance *)ddi_get_soft_state
1506 (mrsas_state, instance_no);
1507
1508 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__));
1509
1510 if (!instance) {
1511 con_log(CL_ANN, (CE_WARN, "mr_sas:%d could not get adapter "
1512 "in reset", instance_no));
1513 return (DDI_FAILURE);
1514 }
1515
1516 instance->func_ptr->disable_intr(instance);
1517
1518 con_log(CL_ANN1, (CE_CONT, "flushing cache for instance %d",
1519 instance_no));
1520
1521 flush_cache(instance);
1522
1523 return (DDI_SUCCESS);
1524 }
1525 #else /* __sparc */
1526 /*ARGSUSED*/
1527 static int
1528 mrsas_quiesce(dev_info_t *dip)
1529 {
1530 int instance_no;
1531
1532 struct mrsas_instance *instance;
1533
1534 instance_no = ddi_get_instance(dip);
1535 instance = (struct mrsas_instance *)ddi_get_soft_state
1536 (mrsas_state, instance_no);
1537
1538 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__));
1539
1540 if (!instance) {
1541 con_log(CL_ANN1, (CE_WARN, "mr_sas:%d could not get adapter "
1542 "in quiesce", instance_no));
1543 return (DDI_FAILURE);
1544 }
1545 if (instance->deadadapter || instance->adapterresetinprogress) {
1546 con_log(CL_ANN1, (CE_WARN, "mr_sas:%d adapter is not in "
1547 "healthy state", instance_no));
1548 return (DDI_FAILURE);
1549 }
1550
1551 if (abort_aen_cmd(instance, instance->aen_cmd)) {
1552 con_log(CL_ANN1, (CE_WARN, "mrsas_quiesce: "
1553 "failed to abort prevous AEN command QUIESCE"));
1554 }
1555
1556 if (instance->tbolt) {
1557 if (abort_syncmap_cmd(instance,
1558 instance->map_update_cmd)) {
1559 dev_err(dip, CE_WARN,
1560 "mrsas_detach: failed to abort "
1561 "previous syncmap command");
1562 return (DDI_FAILURE);
1563 }
1564 }
1565
1566 instance->func_ptr->disable_intr(instance);
1567
1568 con_log(CL_ANN1, (CE_CONT, "flushing cache for instance %d",
1569 instance_no));
1570
1571 flush_cache(instance);
1572
1573 if (wait_for_outstanding(instance)) {
1574 con_log(CL_ANN1,
1575 (CE_CONT, "wait_for_outstanding: return FAIL.\n"));
1576 return (DDI_FAILURE);
1577 }
1578 return (DDI_SUCCESS);
1579 }
1580 #endif /* __sparc */
1581
1582 /*
1583 * ************************************************************************** *
1584 * *
1585 * entry points (SCSI HBA) *
1586 * *
1587 * ************************************************************************** *
1588 */
1589 /*
1590 * tran_tgt_init - initialize a target device instance
1591 * @hba_dip:
1592 * @tgt_dip:
1593 * @tran:
1594 * @sd:
1595 *
1596 * The tran_tgt_init() entry point enables the HBA to allocate and initialize
1597 * any per-target resources. tran_tgt_init() also enables the HBA to qualify
1598 * the device's address as valid and supportable for that particular HBA.
1599 * By returning DDI_FAILURE, the instance of the target driver for that device
1600 * is not probed or attached.
1601 */
1602 /*ARGSUSED*/
1603 static int
1604 mrsas_tran_tgt_init(dev_info_t *hba_dip, dev_info_t *tgt_dip,
1605 scsi_hba_tran_t *tran, struct scsi_device *sd)
1606 {
1607 struct mrsas_instance *instance;
1608 uint16_t tgt = sd->sd_address.a_target;
1609 uint8_t lun = sd->sd_address.a_lun;
1610 dev_info_t *child = NULL;
1611
1612 con_log(CL_DLEVEL2, (CE_NOTE, "mrsas_tgt_init target %d lun %d",
1613 tgt, lun));
1614
1615 instance = ADDR2MR(&sd->sd_address);
1616
1617 if (ndi_dev_is_persistent_node(tgt_dip) == 0) {
1618 /*
1619 * If no persistent node exists, we don't allow .conf node
1620 * to be created.
1621 */
1622 if ((child = mrsas_find_child(instance, tgt, lun)) != NULL) {
1623 con_log(CL_DLEVEL2,
1624 (CE_NOTE, "mrsas_tgt_init find child ="
1625 " %p t = %d l = %d", (void *)child, tgt, lun));
1626 if (ndi_merge_node(tgt_dip, mrsas_name_node) !=
1627 DDI_SUCCESS)
1628 /* Create this .conf node */
1629 return (DDI_SUCCESS);
1630 }
1631 con_log(CL_DLEVEL2, (CE_NOTE, "mrsas_tgt_init in ndi_per "
1632 "DDI_FAILURE t = %d l = %d", tgt, lun));
1633 return (DDI_FAILURE);
1634
1635 }
1636
1637 con_log(CL_DLEVEL2, (CE_NOTE, "mrsas_tgt_init dev_dip %p tgt_dip %p",
1638 (void *)instance->mr_ld_list[tgt].dip, (void *)tgt_dip));
1639
1640 if (tgt < MRDRV_MAX_LD && lun == 0) {
1641 if (instance->mr_ld_list[tgt].dip == NULL &&
1642 strcmp(ddi_driver_name(sd->sd_dev), "sd") == 0) {
1643 mutex_enter(&instance->config_dev_mtx);
1644 instance->mr_ld_list[tgt].dip = tgt_dip;
1645 instance->mr_ld_list[tgt].lun_type = MRSAS_LD_LUN;
1646 instance->mr_ld_list[tgt].flag = MRDRV_TGT_VALID;
1647 mutex_exit(&instance->config_dev_mtx);
1648 }
1649 } else if (instance->tbolt || instance->skinny) {
1650 if (instance->mr_tbolt_pd_list[tgt].dip == NULL) {
1651 mutex_enter(&instance->config_dev_mtx);
1652 instance->mr_tbolt_pd_list[tgt].dip = tgt_dip;
1653 instance->mr_tbolt_pd_list[tgt].flag =
1654 MRDRV_TGT_VALID;
1655 mutex_exit(&instance->config_dev_mtx);
1656 con_log(CL_ANN1, (CE_NOTE, "mrsas_tran_tgt_init:"
1657 "t%xl%x", tgt, lun));
1658 }
1659 }
1660
1661 return (DDI_SUCCESS);
1662 }
1663
1664 /*ARGSUSED*/
1665 static void
1666 mrsas_tran_tgt_free(dev_info_t *hba_dip, dev_info_t *tgt_dip,
1667 scsi_hba_tran_t *hba_tran, struct scsi_device *sd)
1668 {
1669 struct mrsas_instance *instance;
1670 int tgt = sd->sd_address.a_target;
1671 int lun = sd->sd_address.a_lun;
1672
1673 instance = ADDR2MR(&sd->sd_address);
1674
1675 con_log(CL_DLEVEL2, (CE_NOTE, "tgt_free t = %d l = %d", tgt, lun));
1676
1677 if (tgt < MRDRV_MAX_LD && lun == 0) {
1678 if (instance->mr_ld_list[tgt].dip == tgt_dip) {
1679 mutex_enter(&instance->config_dev_mtx);
1680 instance->mr_ld_list[tgt].dip = NULL;
1681 mutex_exit(&instance->config_dev_mtx);
1682 }
1683 } else if (instance->tbolt || instance->skinny) {
1684 mutex_enter(&instance->config_dev_mtx);
1685 instance->mr_tbolt_pd_list[tgt].dip = NULL;
1686 mutex_exit(&instance->config_dev_mtx);
1687 con_log(CL_ANN1, (CE_NOTE, "tgt_free: Setting dip = NULL"
1688 "for tgt:%x", tgt));
1689 }
1690 }
1691
1692 dev_info_t *
1693 mrsas_find_child(struct mrsas_instance *instance, uint16_t tgt, uint8_t lun)
1694 {
1695 dev_info_t *child = NULL;
1696 char addr[SCSI_MAXNAMELEN];
1697 char tmp[MAXNAMELEN];
1698
1699 (void) snprintf(addr, sizeof (addr), "%x,%x", tgt, lun);
1700 for (child = ddi_get_child(instance->dip); child;
1701 child = ddi_get_next_sibling(child)) {
1702
1703 if (ndi_dev_is_persistent_node(child) == 0) {
1704 continue;
1705 }
1706
1707 if (mrsas_name_node(child, tmp, MAXNAMELEN) !=
1708 DDI_SUCCESS) {
1709 continue;
1710 }
1711
1712 if (strcmp(addr, tmp) == 0) {
1713 break;
1714 }
1715 }
1716 con_log(CL_DLEVEL2, (CE_NOTE, "mrsas_find_child: return child = %p",
1717 (void *)child));
1718 return (child);
1719 }
1720
1721 /*
1722 * mrsas_name_node -
1723 * @dip:
1724 * @name:
1725 * @len:
1726 */
1727 static int
1728 mrsas_name_node(dev_info_t *dip, char *name, int len)
1729 {
1730 int tgt, lun;
1731
1732 tgt = ddi_prop_get_int(DDI_DEV_T_ANY, dip,
1733 DDI_PROP_DONTPASS, "target", -1);
1734 con_log(CL_DLEVEL2, (CE_NOTE,
1735 "mrsas_name_node: dip %p tgt %d", (void *)dip, tgt));
1736 if (tgt == -1) {
1737 return (DDI_FAILURE);
1738 }
1739 lun = ddi_prop_get_int(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS,
1740 "lun", -1);
1741 con_log(CL_DLEVEL2,
1742 (CE_NOTE, "mrsas_name_node: tgt %d lun %d", tgt, lun));
1743 if (lun == -1) {
1744 return (DDI_FAILURE);
1745 }
1746 (void) snprintf(name, len, "%x,%x", tgt, lun);
1747 return (DDI_SUCCESS);
1748 }
1749
1750 /*
1751 * tran_init_pkt - allocate & initialize a scsi_pkt structure
1752 * @ap:
1753 * @pkt:
1754 * @bp:
1755 * @cmdlen:
1756 * @statuslen:
1757 * @tgtlen:
1758 * @flags:
1759 * @callback:
1760 *
1761 * The tran_init_pkt() entry point allocates and initializes a scsi_pkt
1762 * structure and DMA resources for a target driver request. The
1763 * tran_init_pkt() entry point is called when the target driver calls the
1764 * SCSA function scsi_init_pkt(). Each call of the tran_init_pkt() entry point
1765 * is a request to perform one or more of three possible services:
1766 * - allocation and initialization of a scsi_pkt structure
1767 * - allocation of DMA resources for data transfer
1768 * - reallocation of DMA resources for the next portion of the data transfer
1769 */
1770 static struct scsi_pkt *
1771 mrsas_tran_init_pkt(struct scsi_address *ap, register struct scsi_pkt *pkt,
1772 struct buf *bp, int cmdlen, int statuslen, int tgtlen,
1773 int flags, int (*callback)(), caddr_t arg)
1774 {
1775 struct scsa_cmd *acmd;
1776 struct mrsas_instance *instance;
1777 struct scsi_pkt *new_pkt;
1778
1779 con_log(CL_DLEVEL1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__));
1780
1781 instance = ADDR2MR(ap);
1782
1783 /* step #1 : pkt allocation */
1784 if (pkt == NULL) {
1785 pkt = scsi_hba_pkt_alloc(instance->dip, ap, cmdlen, statuslen,
1786 tgtlen, sizeof (struct scsa_cmd), callback, arg);
1787 if (pkt == NULL) {
1788 return (NULL);
1789 }
1790
1791 acmd = PKT2CMD(pkt);
1792
1793 /*
1794 * Initialize the new pkt - we redundantly initialize
1795 * all the fields for illustrative purposes.
1796 */
1797 acmd->cmd_pkt = pkt;
1798 acmd->cmd_flags = 0;
1799 acmd->cmd_scblen = statuslen;
1800 acmd->cmd_cdblen = cmdlen;
1801 acmd->cmd_dmahandle = NULL;
1802 acmd->cmd_ncookies = 0;
1803 acmd->cmd_cookie = 0;
1804 acmd->cmd_cookiecnt = 0;
1805 acmd->cmd_nwin = 0;
1806
1807 pkt->pkt_address = *ap;
1808 pkt->pkt_comp = (void (*)())NULL;
1809 pkt->pkt_flags = 0;
1810 pkt->pkt_time = 0;
1811 pkt->pkt_resid = 0;
1812 pkt->pkt_state = 0;
1813 pkt->pkt_statistics = 0;
1814 pkt->pkt_reason = 0;
1815 new_pkt = pkt;
1816 } else {
1817 acmd = PKT2CMD(pkt);
1818 new_pkt = NULL;
1819 }
1820
1821 /* step #2 : dma allocation/move */
1822 if (bp && bp->b_bcount != 0) {
1823 if (acmd->cmd_dmahandle == NULL) {
1824 if (mrsas_dma_alloc(instance, pkt, bp, flags,
1825 callback) == DDI_FAILURE) {
1826 if (new_pkt) {
1827 scsi_hba_pkt_free(ap, new_pkt);
1828 }
1829 return ((struct scsi_pkt *)NULL);
1830 }
1831 } else {
1832 if (mrsas_dma_move(instance, pkt, bp) == DDI_FAILURE) {
1833 return ((struct scsi_pkt *)NULL);
1834 }
1835 }
1836 }
1837
1838 return (pkt);
1839 }
1840
1841 /*
1842 * tran_start - transport a SCSI command to the addressed target
1843 * @ap:
1844 * @pkt:
1845 *
1846 * The tran_start() entry point for a SCSI HBA driver is called to transport a
1847 * SCSI command to the addressed target. The SCSI command is described
1848 * entirely within the scsi_pkt structure, which the target driver allocated
1849 * through the HBA driver's tran_init_pkt() entry point. If the command
1850 * involves a data transfer, DMA resources must also have been allocated for
1851 * the scsi_pkt structure.
1852 *
1853 * Return Values :
1854 * TRAN_BUSY - request queue is full, no more free scbs
1855 * TRAN_ACCEPT - pkt has been submitted to the instance
1856 */
1857 static int
1858 mrsas_tran_start(struct scsi_address *ap, register struct scsi_pkt *pkt)
1859 {
1860 uchar_t cmd_done = 0;
1861
1862 struct mrsas_instance *instance = ADDR2MR(ap);
1863 struct mrsas_cmd *cmd;
1864
1865 con_log(CL_DLEVEL1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__));
1866 if (instance->deadadapter == 1) {
1867 con_log(CL_ANN1, (CE_WARN,
1868 "mrsas_tran_start: return TRAN_FATAL_ERROR "
1869 "for IO, as the HBA doesnt take any more IOs"));
1870 if (pkt) {
1871 pkt->pkt_reason = CMD_DEV_GONE;
1872 pkt->pkt_statistics = STAT_DISCON;
1873 }
1874 return (TRAN_FATAL_ERROR);
1875 }
1876
1877 if (instance->adapterresetinprogress) {
1878 con_log(CL_ANN1, (CE_NOTE, "mrsas_tran_start: Reset flag set, "
1879 "returning mfi_pkt and setting TRAN_BUSY\n"));
1880 return (TRAN_BUSY);
1881 }
1882
1883 con_log(CL_ANN1, (CE_CONT, "chkpnt:%s:%d:SCSI CDB[0]=0x%x time:%x",
1884 __func__, __LINE__, pkt->pkt_cdbp[0], pkt->pkt_time));
1885
1886 pkt->pkt_reason = CMD_CMPLT;
1887 *pkt->pkt_scbp = STATUS_GOOD; /* clear arq scsi_status */
1888
1889 cmd = build_cmd(instance, ap, pkt, &cmd_done);
1890
1891 /*
1892 * Check if the command is already completed by the mrsas_build_cmd()
1893 * routine. In which case the busy_flag would be clear and scb will be
1894 * NULL and appropriate reason provided in pkt_reason field
1895 */
1896 if (cmd_done) {
1897 pkt->pkt_reason = CMD_CMPLT;
1898 pkt->pkt_scbp[0] = STATUS_GOOD;
1899 pkt->pkt_state |= STATE_GOT_BUS | STATE_GOT_TARGET
1900 | STATE_SENT_CMD;
1901 if (((pkt->pkt_flags & FLAG_NOINTR) == 0) && pkt->pkt_comp) {
1902 (*pkt->pkt_comp)(pkt);
1903 }
1904
1905 return (TRAN_ACCEPT);
1906 }
1907
1908 if (cmd == NULL) {
1909 return (TRAN_BUSY);
1910 }
1911
1912 if ((pkt->pkt_flags & FLAG_NOINTR) == 0) {
1913 if (instance->fw_outstanding > instance->max_fw_cmds) {
1914 con_log(CL_ANN, (CE_CONT, "mr_sas:Firmware busy"));
1915 DTRACE_PROBE2(start_tran_err,
1916 uint16_t, instance->fw_outstanding,
1917 uint16_t, instance->max_fw_cmds);
1918 mrsas_return_mfi_pkt(instance, cmd);
1919 return (TRAN_BUSY);
1920 }
1921
1922 /* Synchronize the Cmd frame for the controller */
1923 (void) ddi_dma_sync(cmd->frame_dma_obj.dma_handle, 0, 0,
1924 DDI_DMA_SYNC_FORDEV);
1925 con_log(CL_ANN, (CE_CONT, "issue_cmd_ppc: SCSI CDB[0]=0x%x"
1926 "cmd->index:%x\n", pkt->pkt_cdbp[0], cmd->index));
1927 instance->func_ptr->issue_cmd(cmd, instance);
1928
1929 } else {
1930 struct mrsas_header *hdr = &cmd->frame->hdr;
1931
1932 instance->func_ptr->issue_cmd_in_poll_mode(instance, cmd);
1933
1934 pkt->pkt_reason = CMD_CMPLT;
1935 pkt->pkt_statistics = 0;
1936 pkt->pkt_state |= STATE_XFERRED_DATA | STATE_GOT_STATUS;
1937
1938 switch (ddi_get8(cmd->frame_dma_obj.acc_handle,
1939 &hdr->cmd_status)) {
1940 case MFI_STAT_OK:
1941 pkt->pkt_scbp[0] = STATUS_GOOD;
1942 break;
1943
1944 case MFI_STAT_SCSI_DONE_WITH_ERROR:
1945 con_log(CL_ANN, (CE_CONT,
1946 "mrsas_tran_start: scsi done with error"));
1947 pkt->pkt_reason = CMD_CMPLT;
1948 pkt->pkt_statistics = 0;
1949
1950 ((struct scsi_status *)pkt->pkt_scbp)->sts_chk = 1;
1951 break;
1952
1953 case MFI_STAT_DEVICE_NOT_FOUND:
1954 con_log(CL_ANN, (CE_CONT,
1955 "mrsas_tran_start: device not found error"));
1956 pkt->pkt_reason = CMD_DEV_GONE;
1957 pkt->pkt_statistics = STAT_DISCON;
1958 break;
1959
1960 default:
1961 ((struct scsi_status *)pkt->pkt_scbp)->sts_busy = 1;
1962 }
1963
1964 (void) mrsas_common_check(instance, cmd);
1965 DTRACE_PROBE2(start_nointr_done, uint8_t, hdr->cmd,
1966 uint8_t, hdr->cmd_status);
1967 mrsas_return_mfi_pkt(instance, cmd);
1968
1969 if (pkt->pkt_comp) {
1970 (*pkt->pkt_comp)(pkt);
1971 }
1972
1973 }
1974
1975 return (TRAN_ACCEPT);
1976 }
1977
1978 /*
1979 * tran_abort - Abort any commands that are currently in transport
1980 * @ap:
1981 * @pkt:
1982 *
1983 * The tran_abort() entry point for a SCSI HBA driver is called to abort any
1984 * commands that are currently in transport for a particular target. This entry
1985 * point is called when a target driver calls scsi_abort(). The tran_abort()
1986 * entry point should attempt to abort the command denoted by the pkt
1987 * parameter. If the pkt parameter is NULL, tran_abort() should attempt to
1988 * abort all outstanding commands in the transport layer for the particular
1989 * target or logical unit.
1990 */
1991 /*ARGSUSED*/
1992 static int
1993 mrsas_tran_abort(struct scsi_address *ap, struct scsi_pkt *pkt)
1994 {
1995 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__));
1996
1997 /* abort command not supported by H/W */
1998
1999 return (DDI_FAILURE);
2000 }
2001
2002 /*
2003 * tran_reset - reset either the SCSI bus or target
2004 * @ap:
2005 * @level:
2006 *
2007 * The tran_reset() entry point for a SCSI HBA driver is called to reset either
2008 * the SCSI bus or a particular SCSI target device. This entry point is called
2009 * when a target driver calls scsi_reset(). The tran_reset() entry point must
2010 * reset the SCSI bus if level is RESET_ALL. If level is RESET_TARGET, just the
2011 * particular target or logical unit must be reset.
2012 */
2013 /*ARGSUSED*/
2014 static int
2015 mrsas_tran_reset(struct scsi_address *ap, int level)
2016 {
2017 struct mrsas_instance *instance = ADDR2MR(ap);
2018
2019 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__));
2020
2021 if (wait_for_outstanding(instance)) {
2022 con_log(CL_ANN1,
2023 (CE_CONT, "wait_for_outstanding: return FAIL.\n"));
2024 return (DDI_FAILURE);
2025 } else {
2026 return (DDI_SUCCESS);
2027 }
2028 }
2029
2030 /*
2031 * tran_getcap - get one of a set of SCSA-defined capabilities
2032 * @ap:
2033 * @cap:
2034 * @whom:
2035 *
2036 * The target driver can request the current setting of the capability for a
2037 * particular target by setting the whom parameter to nonzero. A whom value of
2038 * zero indicates a request for the current setting of the general capability
2039 * for the SCSI bus or for adapter hardware. The tran_getcap() should return -1
2040 * for undefined capabilities or the current value of the requested capability.
2041 */
2042 /*ARGSUSED*/
2043 static int
2044 mrsas_tran_getcap(struct scsi_address *ap, char *cap, int whom)
2045 {
2046 int rval = 0;
2047
2048 struct mrsas_instance *instance = ADDR2MR(ap);
2049
2050 con_log(CL_DLEVEL2, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__));
2051
2052 /* we do allow inquiring about capabilities for other targets */
2053 if (cap == NULL) {
2054 return (-1);
2055 }
2056
2057 switch (scsi_hba_lookup_capstr(cap)) {
2058 case SCSI_CAP_DMA_MAX:
2059 if (instance->tbolt) {
2060 /* Limit to 256k max transfer */
2061 rval = mrsas_tbolt_max_cap_maxxfer;
2062 } else {
2063 /* Limit to 16MB max transfer */
2064 rval = mrsas_max_cap_maxxfer;
2065 }
2066 break;
2067 case SCSI_CAP_MSG_OUT:
2068 rval = 1;
2069 break;
2070 case SCSI_CAP_DISCONNECT:
2071 rval = 0;
2072 break;
2073 case SCSI_CAP_SYNCHRONOUS:
2074 rval = 0;
2075 break;
2076 case SCSI_CAP_WIDE_XFER:
2077 rval = 1;
2078 break;
2079 case SCSI_CAP_TAGGED_QING:
2080 rval = 1;
2081 break;
2082 case SCSI_CAP_UNTAGGED_QING:
2083 rval = 1;
2084 break;
2085 case SCSI_CAP_PARITY:
2086 rval = 1;
2087 break;
2088 case SCSI_CAP_INITIATOR_ID:
2089 rval = instance->init_id;
2090 break;
2091 case SCSI_CAP_ARQ:
2092 rval = 1;
2093 break;
2094 case SCSI_CAP_LINKED_CMDS:
2095 rval = 0;
2096 break;
2097 case SCSI_CAP_RESET_NOTIFICATION:
2098 rval = 1;
2099 break;
2100 case SCSI_CAP_GEOMETRY:
2101 rval = -1;
2102
2103 break;
2104 default:
2105 con_log(CL_DLEVEL2, (CE_NOTE, "Default cap coming 0x%x",
2106 scsi_hba_lookup_capstr(cap)));
2107 rval = -1;
2108 break;
2109 }
2110
2111 return (rval);
2112 }
2113
2114 /*
2115 * tran_setcap - set one of a set of SCSA-defined capabilities
2116 * @ap:
2117 * @cap:
2118 * @value:
2119 * @whom:
2120 *
2121 * The target driver might request that the new value be set for a particular
2122 * target by setting the whom parameter to nonzero. A whom value of zero
2123 * means that request is to set the new value for the SCSI bus or for adapter
2124 * hardware in general.
2125 * The tran_setcap() should return the following values as appropriate:
2126 * - -1 for undefined capabilities
2127 * - 0 if the HBA driver cannot set the capability to the requested value
2128 * - 1 if the HBA driver is able to set the capability to the requested value
2129 */
2130 /*ARGSUSED*/
2131 static int
2132 mrsas_tran_setcap(struct scsi_address *ap, char *cap, int value, int whom)
2133 {
2134 int rval = 1;
2135
2136 con_log(CL_DLEVEL2, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__));
2137
2138 /* We don't allow setting capabilities for other targets */
2139 if (cap == NULL || whom == 0) {
2140 return (-1);
2141 }
2142
2143 switch (scsi_hba_lookup_capstr(cap)) {
2144 case SCSI_CAP_DMA_MAX:
2145 case SCSI_CAP_MSG_OUT:
2146 case SCSI_CAP_PARITY:
2147 case SCSI_CAP_LINKED_CMDS:
2148 case SCSI_CAP_RESET_NOTIFICATION:
2149 case SCSI_CAP_DISCONNECT:
2150 case SCSI_CAP_SYNCHRONOUS:
2151 case SCSI_CAP_UNTAGGED_QING:
2152 case SCSI_CAP_WIDE_XFER:
2153 case SCSI_CAP_INITIATOR_ID:
2154 case SCSI_CAP_ARQ:
2155 /*
2156 * None of these are settable via
2157 * the capability interface.
2158 */
2159 break;
2160 case SCSI_CAP_TAGGED_QING:
2161 rval = 1;
2162 break;
2163 case SCSI_CAP_SECTOR_SIZE:
2164 rval = 1;
2165 break;
2166
2167 case SCSI_CAP_TOTAL_SECTORS:
2168 rval = 1;
2169 break;
2170 default:
2171 rval = -1;
2172 break;
2173 }
2174
2175 return (rval);
2176 }
2177
2178 /*
2179 * tran_destroy_pkt - deallocate scsi_pkt structure
2180 * @ap:
2181 * @pkt:
2182 *
2183 * The tran_destroy_pkt() entry point is the HBA driver function that
2184 * deallocates scsi_pkt structures. The tran_destroy_pkt() entry point is
2185 * called when the target driver calls scsi_destroy_pkt(). The
2186 * tran_destroy_pkt() entry point must free any DMA resources that have been
2187 * allocated for the packet. An implicit DMA synchronization occurs if the
2188 * DMA resources are freed and any cached data remains after the completion
2189 * of the transfer.
2190 */
2191 static void
2192 mrsas_tran_destroy_pkt(struct scsi_address *ap, struct scsi_pkt *pkt)
2193 {
2194 struct scsa_cmd *acmd = PKT2CMD(pkt);
2195
2196 con_log(CL_DLEVEL2, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__));
2197
2198 if (acmd->cmd_flags & CFLAG_DMAVALID) {
2199 acmd->cmd_flags &= ~CFLAG_DMAVALID;
2200
2201 (void) ddi_dma_unbind_handle(acmd->cmd_dmahandle);
2202
2203 ddi_dma_free_handle(&acmd->cmd_dmahandle);
2204
2205 acmd->cmd_dmahandle = NULL;
2206 }
2207
2208 /* free the pkt */
2209 scsi_hba_pkt_free(ap, pkt);
2210 }
2211
2212 /*
2213 * tran_dmafree - deallocates DMA resources
2214 * @ap:
2215 * @pkt:
2216 *
2217 * The tran_dmafree() entry point deallocates DMAQ resources that have been
2218 * allocated for a scsi_pkt structure. The tran_dmafree() entry point is
2219 * called when the target driver calls scsi_dmafree(). The tran_dmafree() must
2220 * free only DMA resources allocated for a scsi_pkt structure, not the
2221 * scsi_pkt itself. When DMA resources are freed, a DMA synchronization is
2222 * implicitly performed.
2223 */
2224 /*ARGSUSED*/
2225 static void
2226 mrsas_tran_dmafree(struct scsi_address *ap, struct scsi_pkt *pkt)
2227 {
2228 register struct scsa_cmd *acmd = PKT2CMD(pkt);
2229
2230 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__));
2231
2232 if (acmd->cmd_flags & CFLAG_DMAVALID) {
2233 acmd->cmd_flags &= ~CFLAG_DMAVALID;
2234
2235 (void) ddi_dma_unbind_handle(acmd->cmd_dmahandle);
2236
2237 ddi_dma_free_handle(&acmd->cmd_dmahandle);
2238
2239 acmd->cmd_dmahandle = NULL;
2240 }
2241 }
2242
2243 /*
2244 * tran_sync_pkt - synchronize the DMA object allocated
2245 * @ap:
2246 * @pkt:
2247 *
2248 * The tran_sync_pkt() entry point synchronizes the DMA object allocated for
2249 * the scsi_pkt structure before or after a DMA transfer. The tran_sync_pkt()
2250 * entry point is called when the target driver calls scsi_sync_pkt(). If the
2251 * data transfer direction is a DMA read from device to memory, tran_sync_pkt()
2252 * must synchronize the CPU's view of the data. If the data transfer direction
2253 * is a DMA write from memory to device, tran_sync_pkt() must synchronize the
2254 * device's view of the data.
2255 */
2256 /*ARGSUSED*/
2257 static void
2258 mrsas_tran_sync_pkt(struct scsi_address *ap, struct scsi_pkt *pkt)
2259 {
2260 register struct scsa_cmd *acmd = PKT2CMD(pkt);
2261
2262 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__));
2263
2264 if (acmd->cmd_flags & CFLAG_DMAVALID) {
2265 (void) ddi_dma_sync(acmd->cmd_dmahandle, acmd->cmd_dma_offset,
2266 acmd->cmd_dma_len, (acmd->cmd_flags & CFLAG_DMASEND) ?
2267 DDI_DMA_SYNC_FORDEV : DDI_DMA_SYNC_FORCPU);
2268 }
2269 }
2270
2271 /*ARGSUSED*/
2272 static int
2273 mrsas_tran_quiesce(dev_info_t *dip)
2274 {
2275 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__));
2276
2277 return (1);
2278 }
2279
2280 /*ARGSUSED*/
2281 static int
2282 mrsas_tran_unquiesce(dev_info_t *dip)
2283 {
2284 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__));
2285
2286 return (1);
2287 }
2288
2289
2290 /*
2291 * mrsas_isr(caddr_t)
2292 *
2293 * The Interrupt Service Routine
2294 *
2295 * Collect status for all completed commands and do callback
2296 *
2297 */
2298 static uint_t
2299 mrsas_isr(struct mrsas_instance *instance)
2300 {
2301 int need_softintr;
2302 uint32_t producer;
2303 uint32_t consumer;
2304 uint32_t context;
2305 int retval;
2306
2307 struct mrsas_cmd *cmd;
2308 struct mrsas_header *hdr;
2309 struct scsi_pkt *pkt;
2310
2311 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__));
2312 ASSERT(instance);
2313 if (instance->tbolt) {
2314 mutex_enter(&instance->chip_mtx);
2315 if ((instance->intr_type == DDI_INTR_TYPE_FIXED) &&
2316 !(instance->func_ptr->intr_ack(instance))) {
2317 mutex_exit(&instance->chip_mtx);
2318 return (DDI_INTR_UNCLAIMED);
2319 }
2320 retval = mr_sas_tbolt_process_outstanding_cmd(instance);
2321 mutex_exit(&instance->chip_mtx);
2322 return (retval);
2323 } else {
2324 if ((instance->intr_type == DDI_INTR_TYPE_FIXED) &&
2325 !instance->func_ptr->intr_ack(instance)) {
2326 return (DDI_INTR_UNCLAIMED);
2327 }
2328 }
2329
2330 (void) ddi_dma_sync(instance->mfi_internal_dma_obj.dma_handle,
2331 0, 0, DDI_DMA_SYNC_FORCPU);
2332
2333 if (mrsas_check_dma_handle(instance->mfi_internal_dma_obj.dma_handle)
2334 != DDI_SUCCESS) {
2335 mrsas_fm_ereport(instance, DDI_FM_DEVICE_NO_RESPONSE);
2336 ddi_fm_service_impact(instance->dip, DDI_SERVICE_LOST);
2337 con_log(CL_ANN1, (CE_WARN,
2338 "mr_sas_isr(): FMA check, returning DDI_INTR_UNCLAIMED"));
2339 return (DDI_INTR_CLAIMED);
2340 }
2341 con_log(CL_ANN1, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__));
2342
2343 #ifdef OCRDEBUG
2344 if (debug_consecutive_timeout_after_ocr_g == 1) {
2345 con_log(CL_ANN1, (CE_NOTE,
2346 "simulating consecutive timeout after ocr"));
2347 return (DDI_INTR_CLAIMED);
2348 }
2349 #endif
2350
2351 mutex_enter(&instance->completed_pool_mtx);
2352 mutex_enter(&instance->cmd_pend_mtx);
2353
2354 producer = ddi_get32(instance->mfi_internal_dma_obj.acc_handle,
2355 instance->producer);
2356 consumer = ddi_get32(instance->mfi_internal_dma_obj.acc_handle,
2357 instance->consumer);
2358
2359 con_log(CL_ANN, (CE_CONT, " producer %x consumer %x ",
2360 producer, consumer));
2361 if (producer == consumer) {
2362 con_log(CL_ANN, (CE_WARN, "producer == consumer case"));
2363 DTRACE_PROBE2(isr_pc_err, uint32_t, producer,
2364 uint32_t, consumer);
2365 mutex_exit(&instance->cmd_pend_mtx);
2366 mutex_exit(&instance->completed_pool_mtx);
2367 return (DDI_INTR_CLAIMED);
2368 }
2369
2370 while (consumer != producer) {
2371 context = ddi_get32(instance->mfi_internal_dma_obj.acc_handle,
2372 &instance->reply_queue[consumer]);
2373 cmd = instance->cmd_list[context];
2374
2375 if (cmd->sync_cmd == MRSAS_TRUE) {
2376 hdr = (struct mrsas_header *)&cmd->frame->hdr;
2377 if (hdr) {
2378 mlist_del_init(&cmd->list);
2379 }
2380 } else {
2381 pkt = cmd->pkt;
2382 if (pkt) {
2383 mlist_del_init(&cmd->list);
2384 }
2385 }
2386
2387 mlist_add_tail(&cmd->list, &instance->completed_pool_list);
2388
2389 consumer++;
2390 if (consumer == (instance->max_fw_cmds + 1)) {
2391 consumer = 0;
2392 }
2393 }
2394 ddi_put32(instance->mfi_internal_dma_obj.acc_handle,
2395 instance->consumer, consumer);
2396 mutex_exit(&instance->cmd_pend_mtx);
2397 mutex_exit(&instance->completed_pool_mtx);
2398
2399 (void) ddi_dma_sync(instance->mfi_internal_dma_obj.dma_handle,
2400 0, 0, DDI_DMA_SYNC_FORDEV);
2401
2402 if (instance->softint_running) {
2403 need_softintr = 0;
2404 } else {
2405 need_softintr = 1;
2406 }
2407
2408 if (instance->isr_level == HIGH_LEVEL_INTR) {
2409 if (need_softintr) {
2410 ddi_trigger_softintr(instance->soft_intr_id);
2411 }
2412 } else {
2413 /*
2414 * Not a high-level interrupt, therefore call the soft level
2415 * interrupt explicitly
2416 */
2417 (void) mrsas_softintr(instance);
2418 }
2419
2420 return (DDI_INTR_CLAIMED);
2421 }
2422
2423
2424 /*
2425 * ************************************************************************** *
2426 * *
2427 * libraries *
2428 * *
2429 * ************************************************************************** *
2430 */
2431 /*
2432 * get_mfi_pkt : Get a command from the free pool
2433 * After successful allocation, the caller of this routine
2434 * must clear the frame buffer (memset to zero) before
2435 * using the packet further.
2436 *
2437 * ***** Note *****
2438 * After clearing the frame buffer the context id of the
2439 * frame buffer SHOULD be restored back.
2440 */
2441 struct mrsas_cmd *
2442 mrsas_get_mfi_pkt(struct mrsas_instance *instance)
2443 {
2444 mlist_t *head = &instance->cmd_pool_list;
2445 struct mrsas_cmd *cmd = NULL;
2446
2447 mutex_enter(&instance->cmd_pool_mtx);
2448
2449 if (!mlist_empty(head)) {
2450 cmd = mlist_entry(head->next, struct mrsas_cmd, list);
2451 mlist_del_init(head->next);
2452 }
2453 if (cmd != NULL) {
2454 cmd->pkt = NULL;
2455 cmd->retry_count_for_ocr = 0;
2456 cmd->drv_pkt_time = 0;
2457
2458 }
2459 mutex_exit(&instance->cmd_pool_mtx);
2460
2461 return (cmd);
2462 }
2463
2464 static struct mrsas_cmd *
2465 get_mfi_app_pkt(struct mrsas_instance *instance)
2466 {
2467 mlist_t *head = &instance->app_cmd_pool_list;
2468 struct mrsas_cmd *cmd = NULL;
2469
2470 mutex_enter(&instance->app_cmd_pool_mtx);
2471
2472 if (!mlist_empty(head)) {
2473 cmd = mlist_entry(head->next, struct mrsas_cmd, list);
2474 mlist_del_init(head->next);
2475 }
2476 if (cmd != NULL) {
2477 cmd->pkt = NULL;
2478 cmd->retry_count_for_ocr = 0;
2479 cmd->drv_pkt_time = 0;
2480 }
2481
2482 mutex_exit(&instance->app_cmd_pool_mtx);
2483
2484 return (cmd);
2485 }
2486 /*
2487 * return_mfi_pkt : Return a cmd to free command pool
2488 */
2489 void
2490 mrsas_return_mfi_pkt(struct mrsas_instance *instance, struct mrsas_cmd *cmd)
2491 {
2492 mutex_enter(&instance->cmd_pool_mtx);
2493 /* use mlist_add_tail for debug assistance */
2494 mlist_add_tail(&cmd->list, &instance->cmd_pool_list);
2495
2496 mutex_exit(&instance->cmd_pool_mtx);
2497 }
2498
2499 static void
2500 return_mfi_app_pkt(struct mrsas_instance *instance, struct mrsas_cmd *cmd)
2501 {
2502 mutex_enter(&instance->app_cmd_pool_mtx);
2503
2504 mlist_add(&cmd->list, &instance->app_cmd_pool_list);
2505
2506 mutex_exit(&instance->app_cmd_pool_mtx);
2507 }
2508 void
2509 push_pending_mfi_pkt(struct mrsas_instance *instance, struct mrsas_cmd *cmd)
2510 {
2511 struct scsi_pkt *pkt;
2512 struct mrsas_header *hdr;
2513 con_log(CL_DLEVEL2, (CE_NOTE, "push_pending_pkt(): Called\n"));
2514 mutex_enter(&instance->cmd_pend_mtx);
2515 mlist_del_init(&cmd->list);
2516 mlist_add_tail(&cmd->list, &instance->cmd_pend_list);
2517 if (cmd->sync_cmd == MRSAS_TRUE) {
2518 hdr = (struct mrsas_header *)&cmd->frame->hdr;
2519 if (hdr) {
2520 con_log(CL_ANN1, (CE_CONT,
2521 "push_pending_mfi_pkt: "
2522 "cmd %p index %x "
2523 "time %llx",
2524 (void *)cmd, cmd->index,
2525 gethrtime()));
2526 /* Wait for specified interval */
2527 cmd->drv_pkt_time = ddi_get16(
2528 cmd->frame_dma_obj.acc_handle, &hdr->timeout);
2529 if (cmd->drv_pkt_time < debug_timeout_g)
2530 cmd->drv_pkt_time = (uint16_t)debug_timeout_g;
2531 con_log(CL_ANN1, (CE_CONT,
2532 "push_pending_pkt(): "
2533 "Called IO Timeout Value %x\n",
2534 cmd->drv_pkt_time));
2535 }
2536 if (hdr && instance->timeout_id == (timeout_id_t)-1) {
2537 instance->timeout_id = timeout(io_timeout_checker,
2538 (void *) instance, drv_usectohz(MRSAS_1_SECOND));
2539 }
2540 } else {
2541 pkt = cmd->pkt;
2542 if (pkt) {
2543 con_log(CL_ANN1, (CE_CONT,
2544 "push_pending_mfi_pkt: "
2545 "cmd %p index %x pkt %p, "
2546 "time %llx",
2547 (void *)cmd, cmd->index, (void *)pkt,
2548 gethrtime()));
2549 cmd->drv_pkt_time = (uint16_t)debug_timeout_g;
2550 }
2551 if (pkt && instance->timeout_id == (timeout_id_t)-1) {
2552 instance->timeout_id = timeout(io_timeout_checker,
2553 (void *) instance, drv_usectohz(MRSAS_1_SECOND));
2554 }
2555 }
2556
2557 mutex_exit(&instance->cmd_pend_mtx);
2558
2559 }
2560
2561 int
2562 mrsas_print_pending_cmds(struct mrsas_instance *instance)
2563 {
2564 mlist_t *head = &instance->cmd_pend_list;
2565 mlist_t *tmp = head;
2566 struct mrsas_cmd *cmd = NULL;
2567 struct mrsas_header *hdr;
2568 unsigned int flag = 1;
2569 struct scsi_pkt *pkt;
2570 int saved_level;
2571 int cmd_count = 0;
2572
2573 saved_level = debug_level_g;
2574 debug_level_g = CL_ANN1;
2575
2576 dev_err(instance->dip, CE_NOTE,
2577 "mrsas_print_pending_cmds(): Called");
2578
2579 while (flag) {
2580 mutex_enter(&instance->cmd_pend_mtx);
2581 tmp = tmp->next;
2582 if (tmp == head) {
2583 mutex_exit(&instance->cmd_pend_mtx);
2584 flag = 0;
2585 con_log(CL_ANN1, (CE_CONT, "mrsas_print_pending_cmds():"
2586 " NO MORE CMDS PENDING....\n"));
2587 break;
2588 } else {
2589 cmd = mlist_entry(tmp, struct mrsas_cmd, list);
2590 mutex_exit(&instance->cmd_pend_mtx);
2591 if (cmd) {
2592 if (cmd->sync_cmd == MRSAS_TRUE) {
2593 hdr = (struct mrsas_header *)
2594 &cmd->frame->hdr;
2595 if (hdr) {
2596 con_log(CL_ANN1, (CE_CONT,
2597 "print: cmd %p index 0x%x "
2598 "drv_pkt_time 0x%x (NO-PKT)"
2599 " hdr %p\n", (void *)cmd,
2600 cmd->index,
2601 cmd->drv_pkt_time,
2602 (void *)hdr));
2603 }
2604 } else {
2605 pkt = cmd->pkt;
2606 if (pkt) {
2607 con_log(CL_ANN1, (CE_CONT,
2608 "print: cmd %p index 0x%x "
2609 "drv_pkt_time 0x%x pkt %p \n",
2610 (void *)cmd, cmd->index,
2611 cmd->drv_pkt_time, (void *)pkt));
2612 }
2613 }
2614
2615 if (++cmd_count == 1) {
2616 mrsas_print_cmd_details(instance, cmd,
2617 0xDD);
2618 } else {
2619 mrsas_print_cmd_details(instance, cmd,
2620 1);
2621 }
2622
2623 }
2624 }
2625 }
2626 con_log(CL_ANN1, (CE_CONT, "mrsas_print_pending_cmds(): Done\n"));
2627
2628
2629 debug_level_g = saved_level;
2630
2631 return (DDI_SUCCESS);
2632 }
2633
2634
2635 int
2636 mrsas_complete_pending_cmds(struct mrsas_instance *instance)
2637 {
2638
2639 struct mrsas_cmd *cmd = NULL;
2640 struct scsi_pkt *pkt;
2641 struct mrsas_header *hdr;
2642
2643 struct mlist_head *pos, *next;
2644
2645 con_log(CL_ANN1, (CE_NOTE,
2646 "mrsas_complete_pending_cmds(): Called"));
2647
2648 mutex_enter(&instance->cmd_pend_mtx);
2649 mlist_for_each_safe(pos, next, &instance->cmd_pend_list) {
2650 cmd = mlist_entry(pos, struct mrsas_cmd, list);
2651 if (cmd) {
2652 pkt = cmd->pkt;
2653 if (pkt) { /* for IO */
2654 if (((pkt->pkt_flags & FLAG_NOINTR)
2655 == 0) && pkt->pkt_comp) {
2656 pkt->pkt_reason
2657 = CMD_DEV_GONE;
2658 pkt->pkt_statistics
2659 = STAT_DISCON;
2660 con_log(CL_ANN1, (CE_CONT,
2661 "fail and posting to scsa "
2662 "cmd %p index %x"
2663 " pkt %p "
2664 "time : %llx",
2665 (void *)cmd, cmd->index,
2666 (void *)pkt, gethrtime()));
2667 (*pkt->pkt_comp)(pkt);
2668 }
2669 } else { /* for DCMDS */
2670 if (cmd->sync_cmd == MRSAS_TRUE) {
2671 hdr = (struct mrsas_header *)&cmd->frame->hdr;
2672 con_log(CL_ANN1, (CE_CONT,
2673 "posting invalid status to application "
2674 "cmd %p index %x"
2675 " hdr %p "
2676 "time : %llx",
2677 (void *)cmd, cmd->index,
2678 (void *)hdr, gethrtime()));
2679 hdr->cmd_status = MFI_STAT_INVALID_STATUS;
2680 complete_cmd_in_sync_mode(instance, cmd);
2681 }
2682 }
2683 mlist_del_init(&cmd->list);
2684 } else {
2685 con_log(CL_ANN1, (CE_CONT,
2686 "mrsas_complete_pending_cmds:"
2687 "NULL command\n"));
2688 }
2689 con_log(CL_ANN1, (CE_CONT,
2690 "mrsas_complete_pending_cmds:"
2691 "looping for more commands\n"));
2692 }
2693 mutex_exit(&instance->cmd_pend_mtx);
2694
2695 con_log(CL_ANN1, (CE_CONT, "mrsas_complete_pending_cmds(): DONE\n"));
2696 return (DDI_SUCCESS);
2697 }
2698
2699 void
2700 mrsas_print_cmd_details(struct mrsas_instance *instance, struct mrsas_cmd *cmd,
2701 int detail)
2702 {
2703 struct scsi_pkt *pkt = cmd->pkt;
2704 Mpi2RaidSCSIIORequest_t *scsi_io = cmd->scsi_io_request;
2705 int i;
2706 int saved_level;
2707 ddi_acc_handle_t acc_handle =
2708 instance->mpi2_frame_pool_dma_obj.acc_handle;
2709
2710 if (detail == 0xDD) {
2711 saved_level = debug_level_g;
2712 debug_level_g = CL_ANN1;
2713 }
2714
2715
2716 if (instance->tbolt) {
2717 con_log(CL_ANN1, (CE_CONT, "print_cmd_details: cmd %p "
2718 "cmd->index 0x%x SMID 0x%x timer 0x%x sec\n",
2719 (void *)cmd, cmd->index, cmd->SMID, cmd->drv_pkt_time));
2720 } else {
2721 con_log(CL_ANN1, (CE_CONT, "print_cmd_details: cmd %p "
2722 "cmd->index 0x%x timer 0x%x sec\n",
2723 (void *)cmd, cmd->index, cmd->drv_pkt_time));
2724 }
2725
2726 if (pkt) {
2727 con_log(CL_ANN1, (CE_CONT, "scsi_pkt CDB[0]=0x%x",
2728 pkt->pkt_cdbp[0]));
2729 } else {
2730 con_log(CL_ANN1, (CE_CONT, "NO-PKT"));
2731 }
2732
2733 if ((detail == 0xDD) && instance->tbolt) {
2734 con_log(CL_ANN1, (CE_CONT, "RAID_SCSI_IO_REQUEST\n"));
2735 con_log(CL_ANN1, (CE_CONT, "DevHandle=0x%X Function=0x%X "
2736 "IoFlags=0x%X SGLFlags=0x%X DataLength=0x%X\n",
2737 ddi_get16(acc_handle, &scsi_io->DevHandle),
2738 ddi_get8(acc_handle, &scsi_io->Function),
2739 ddi_get16(acc_handle, &scsi_io->IoFlags),
2740 ddi_get16(acc_handle, &scsi_io->SGLFlags),
2741 ddi_get32(acc_handle, &scsi_io->DataLength)));
2742
2743 for (i = 0; i < 32; i++) {
2744 con_log(CL_ANN1, (CE_CONT, "CDB[%d]=0x%x ", i,
2745 ddi_get8(acc_handle, &scsi_io->CDB.CDB32[i])));
2746 }
2747
2748 con_log(CL_ANN1, (CE_CONT, "RAID-CONTEXT\n"));
2749 con_log(CL_ANN1, (CE_CONT, "status=0x%X extStatus=0x%X "
2750 "ldTargetId=0x%X timeoutValue=0x%X regLockFlags=0x%X "
2751 "RAIDFlags=0x%X regLockRowLBA=0x%" PRIu64
2752 " regLockLength=0x%X spanArm=0x%X\n",
2753 ddi_get8(acc_handle, &scsi_io->RaidContext.status),
2754 ddi_get8(acc_handle, &scsi_io->RaidContext.extStatus),
2755 ddi_get16(acc_handle, &scsi_io->RaidContext.ldTargetId),
2756 ddi_get16(acc_handle, &scsi_io->RaidContext.timeoutValue),
2757 ddi_get8(acc_handle, &scsi_io->RaidContext.regLockFlags),
2758 ddi_get8(acc_handle, &scsi_io->RaidContext.RAIDFlags),
2759 ddi_get64(acc_handle, &scsi_io->RaidContext.regLockRowLBA),
2760 ddi_get32(acc_handle, &scsi_io->RaidContext.regLockLength),
2761 ddi_get8(acc_handle, &scsi_io->RaidContext.spanArm)));
2762 }
2763
2764 if (detail == 0xDD) {
2765 debug_level_g = saved_level;
2766 }
2767 }
2768
2769
2770 int
2771 mrsas_issue_pending_cmds(struct mrsas_instance *instance)
2772 {
2773 mlist_t *head = &instance->cmd_pend_list;
2774 mlist_t *tmp = head->next;
2775 struct mrsas_cmd *cmd = NULL;
2776 struct scsi_pkt *pkt;
2777
2778 con_log(CL_ANN1, (CE_NOTE, "mrsas_issue_pending_cmds(): Called"));
2779 while (tmp != head) {
2780 mutex_enter(&instance->cmd_pend_mtx);
2781 cmd = mlist_entry(tmp, struct mrsas_cmd, list);
2782 tmp = tmp->next;
2783 mutex_exit(&instance->cmd_pend_mtx);
2784 if (cmd) {
2785 con_log(CL_ANN1, (CE_CONT,
2786 "mrsas_issue_pending_cmds(): "
2787 "Got a cmd: cmd %p index 0x%x drv_pkt_time 0x%x ",
2788 (void *)cmd, cmd->index, cmd->drv_pkt_time));
2789
2790 /* Reset command timeout value */
2791 if (cmd->drv_pkt_time < debug_timeout_g)
2792 cmd->drv_pkt_time = (uint16_t)debug_timeout_g;
2793
2794 cmd->retry_count_for_ocr++;
2795
2796 dev_err(instance->dip, CE_CONT,
2797 "cmd retry count = %d\n",
2798 cmd->retry_count_for_ocr);
2799
2800 if (cmd->retry_count_for_ocr > IO_RETRY_COUNT) {
2801 dev_err(instance->dip,
2802 CE_WARN, "mrsas_issue_pending_cmds(): "
2803 "cmd->retry_count exceeded limit >%d\n",
2804 IO_RETRY_COUNT);
2805 mrsas_print_cmd_details(instance, cmd, 0xDD);
2806
2807 dev_err(instance->dip, CE_WARN,
2808 "mrsas_issue_pending_cmds():"
2809 "Calling KILL Adapter");
2810 if (instance->tbolt)
2811 mrsas_tbolt_kill_adapter(instance);
2812 else
2813 (void) mrsas_kill_adapter(instance);
2814 return (DDI_FAILURE);
2815 }
2816
2817 pkt = cmd->pkt;
2818 if (pkt) {
2819 con_log(CL_ANN1, (CE_CONT,
2820 "PENDING PKT-CMD ISSUE: cmd %p index %x "
2821 "pkt %p time %llx",
2822 (void *)cmd, cmd->index,
2823 (void *)pkt,
2824 gethrtime()));
2825
2826 } else {
2827 dev_err(instance->dip, CE_CONT,
2828 "mrsas_issue_pending_cmds(): NO-PKT, "
2829 "cmd %p index 0x%x drv_pkt_time 0x%x",
2830 (void *)cmd, cmd->index, cmd->drv_pkt_time);
2831 }
2832
2833
2834 if (cmd->sync_cmd == MRSAS_TRUE) {
2835 dev_err(instance->dip, CE_CONT,
2836 "mrsas_issue_pending_cmds(): "
2837 "SYNC_CMD == TRUE \n");
2838 instance->func_ptr->issue_cmd_in_sync_mode(
2839 instance, cmd);
2840 } else {
2841 instance->func_ptr->issue_cmd(cmd, instance);
2842 }
2843 } else {
2844 con_log(CL_ANN1, (CE_CONT,
2845 "mrsas_issue_pending_cmds: NULL command\n"));
2846 }
2847 con_log(CL_ANN1, (CE_CONT,
2848 "mrsas_issue_pending_cmds:"
2849 "looping for more commands"));
2850 }
2851 con_log(CL_ANN1, (CE_CONT, "mrsas_issue_pending_cmds(): DONE\n"));
2852 return (DDI_SUCCESS);
2853 }
2854
2855
2856
2857 /*
2858 * destroy_mfi_frame_pool
2859 */
2860 void
2861 destroy_mfi_frame_pool(struct mrsas_instance *instance)
2862 {
2863 int i;
2864 uint32_t max_cmd = instance->max_fw_cmds;
2865
2866 struct mrsas_cmd *cmd;
2867
2868 /* return all frames to pool */
2869
2870 for (i = 0; i < max_cmd; i++) {
2871
2872 cmd = instance->cmd_list[i];
2873
2874 if (cmd->frame_dma_obj_status == DMA_OBJ_ALLOCATED)
2875 (void) mrsas_free_dma_obj(instance, cmd->frame_dma_obj);
2876
2877 cmd->frame_dma_obj_status = DMA_OBJ_FREED;
2878 }
2879
2880 }
2881
2882 /*
2883 * create_mfi_frame_pool
2884 */
2885 int
2886 create_mfi_frame_pool(struct mrsas_instance *instance)
2887 {
2888 int i = 0;
2889 int cookie_cnt;
2890 uint16_t max_cmd;
2891 uint16_t sge_sz;
2892 uint32_t sgl_sz;
2893 uint32_t tot_frame_size;
2894 struct mrsas_cmd *cmd;
2895 int retval = DDI_SUCCESS;
2896
2897 max_cmd = instance->max_fw_cmds;
2898 sge_sz = sizeof (struct mrsas_sge_ieee);
2899 /* calculated the number of 64byte frames required for SGL */
2900 sgl_sz = sge_sz * instance->max_num_sge;
2901 tot_frame_size = sgl_sz + MRMFI_FRAME_SIZE + SENSE_LENGTH;
2902
2903 con_log(CL_DLEVEL3, (CE_NOTE, "create_mfi_frame_pool: "
2904 "sgl_sz %x tot_frame_size %x", sgl_sz, tot_frame_size));
2905
2906 while (i < max_cmd) {
2907 cmd = instance->cmd_list[i];
2908
2909 cmd->frame_dma_obj.size = tot_frame_size;
2910 cmd->frame_dma_obj.dma_attr = mrsas_generic_dma_attr;
2911 cmd->frame_dma_obj.dma_attr.dma_attr_addr_hi = 0xFFFFFFFFU;
2912 cmd->frame_dma_obj.dma_attr.dma_attr_count_max = 0xFFFFFFFFU;
2913 cmd->frame_dma_obj.dma_attr.dma_attr_sgllen = 1;
2914 cmd->frame_dma_obj.dma_attr.dma_attr_align = 64;
2915
2916 cookie_cnt = mrsas_alloc_dma_obj(instance, &cmd->frame_dma_obj,
2917 (uchar_t)DDI_STRUCTURE_LE_ACC);
2918
2919 if (cookie_cnt == -1 || cookie_cnt > 1) {
2920 dev_err(instance->dip, CE_WARN,
2921 "create_mfi_frame_pool: could not alloc.");
2922 retval = DDI_FAILURE;
2923 goto mrsas_undo_frame_pool;
2924 }
2925
2926 bzero(cmd->frame_dma_obj.buffer, tot_frame_size);
2927
2928 cmd->frame_dma_obj_status = DMA_OBJ_ALLOCATED;
2929 cmd->frame = (union mrsas_frame *)cmd->frame_dma_obj.buffer;
2930 cmd->frame_phys_addr =
2931 cmd->frame_dma_obj.dma_cookie[0].dmac_address;
2932
2933 cmd->sense = (uint8_t *)(((unsigned long)
2934 cmd->frame_dma_obj.buffer) +
2935 tot_frame_size - SENSE_LENGTH);
2936 cmd->sense_phys_addr =
2937 cmd->frame_dma_obj.dma_cookie[0].dmac_address +
2938 tot_frame_size - SENSE_LENGTH;
2939
2940 if (!cmd->frame || !cmd->sense) {
2941 dev_err(instance->dip, CE_WARN,
2942 "pci_pool_alloc failed");
2943 retval = ENOMEM;
2944 goto mrsas_undo_frame_pool;
2945 }
2946
2947 ddi_put32(cmd->frame_dma_obj.acc_handle,
2948 &cmd->frame->io.context, cmd->index);
2949 i++;
2950
2951 con_log(CL_DLEVEL3, (CE_NOTE, "[%x]-%x",
2952 cmd->index, cmd->frame_phys_addr));
2953 }
2954
2955 return (DDI_SUCCESS);
2956
2957 mrsas_undo_frame_pool:
2958 if (i > 0)
2959 destroy_mfi_frame_pool(instance);
2960
2961 return (retval);
2962 }
2963
2964 /*
2965 * free_additional_dma_buffer
2966 */
2967 static void
2968 free_additional_dma_buffer(struct mrsas_instance *instance)
2969 {
2970 if (instance->mfi_internal_dma_obj.status == DMA_OBJ_ALLOCATED) {
2971 (void) mrsas_free_dma_obj(instance,
2972 instance->mfi_internal_dma_obj);
2973 instance->mfi_internal_dma_obj.status = DMA_OBJ_FREED;
2974 }
2975
2976 if (instance->mfi_evt_detail_obj.status == DMA_OBJ_ALLOCATED) {
2977 (void) mrsas_free_dma_obj(instance,
2978 instance->mfi_evt_detail_obj);
2979 instance->mfi_evt_detail_obj.status = DMA_OBJ_FREED;
2980 }
2981 }
2982
2983 /*
2984 * alloc_additional_dma_buffer
2985 */
2986 static int
2987 alloc_additional_dma_buffer(struct mrsas_instance *instance)
2988 {
2989 uint32_t reply_q_sz;
2990 uint32_t internal_buf_size = PAGESIZE*2;
2991
2992 /* max cmds plus 1 + producer & consumer */
2993 reply_q_sz = sizeof (uint32_t) * (instance->max_fw_cmds + 1 + 2);
2994
2995 instance->mfi_internal_dma_obj.size = internal_buf_size;
2996 instance->mfi_internal_dma_obj.dma_attr = mrsas_generic_dma_attr;
2997 instance->mfi_internal_dma_obj.dma_attr.dma_attr_addr_hi = 0xFFFFFFFFU;
2998 instance->mfi_internal_dma_obj.dma_attr.dma_attr_count_max =
2999 0xFFFFFFFFU;
3000 instance->mfi_internal_dma_obj.dma_attr.dma_attr_sgllen = 1;
3001
3002 if (mrsas_alloc_dma_obj(instance, &instance->mfi_internal_dma_obj,
3003 (uchar_t)DDI_STRUCTURE_LE_ACC) != 1) {
3004 dev_err(instance->dip, CE_WARN,
3005 "could not alloc reply queue");
3006 return (DDI_FAILURE);
3007 }
3008
3009 bzero(instance->mfi_internal_dma_obj.buffer, internal_buf_size);
3010
3011 instance->mfi_internal_dma_obj.status |= DMA_OBJ_ALLOCATED;
3012
3013 instance->producer = (uint32_t *)((unsigned long)
3014 instance->mfi_internal_dma_obj.buffer);
3015 instance->consumer = (uint32_t *)((unsigned long)
3016 instance->mfi_internal_dma_obj.buffer + 4);
3017 instance->reply_queue = (uint32_t *)((unsigned long)
3018 instance->mfi_internal_dma_obj.buffer + 8);
3019 instance->internal_buf = (caddr_t)(((unsigned long)
3020 instance->mfi_internal_dma_obj.buffer) + reply_q_sz + 8);
3021 instance->internal_buf_dmac_add =
3022 instance->mfi_internal_dma_obj.dma_cookie[0].dmac_address +
3023 (reply_q_sz + 8);
3024 instance->internal_buf_size = internal_buf_size -
3025 (reply_q_sz + 8);
3026
3027 /* allocate evt_detail */
3028 instance->mfi_evt_detail_obj.size = sizeof (struct mrsas_evt_detail);
3029 instance->mfi_evt_detail_obj.dma_attr = mrsas_generic_dma_attr;
3030 instance->mfi_evt_detail_obj.dma_attr.dma_attr_addr_hi = 0xFFFFFFFFU;
3031 instance->mfi_evt_detail_obj.dma_attr.dma_attr_count_max = 0xFFFFFFFFU;
3032 instance->mfi_evt_detail_obj.dma_attr.dma_attr_sgllen = 1;
3033 instance->mfi_evt_detail_obj.dma_attr.dma_attr_align = 1;
3034
3035 if (mrsas_alloc_dma_obj(instance, &instance->mfi_evt_detail_obj,
3036 (uchar_t)DDI_STRUCTURE_LE_ACC) != 1) {
3037 dev_err(instance->dip, CE_WARN, "alloc_additional_dma_buffer: "
3038 "could not allocate data transfer buffer.");
3039 goto mrsas_undo_internal_buff;
3040 }
3041
3042 bzero(instance->mfi_evt_detail_obj.buffer,
3043 sizeof (struct mrsas_evt_detail));
3044
3045 instance->mfi_evt_detail_obj.status |= DMA_OBJ_ALLOCATED;
3046
3047 return (DDI_SUCCESS);
3048
3049 mrsas_undo_internal_buff:
3050 if (instance->mfi_internal_dma_obj.status == DMA_OBJ_ALLOCATED) {
3051 (void) mrsas_free_dma_obj(instance,
3052 instance->mfi_internal_dma_obj);
3053 instance->mfi_internal_dma_obj.status = DMA_OBJ_FREED;
3054 }
3055
3056 return (DDI_FAILURE);
3057 }
3058
3059
3060 void
3061 mrsas_free_cmd_pool(struct mrsas_instance *instance)
3062 {
3063 int i;
3064 uint32_t max_cmd;
3065 size_t sz;
3066
3067 /* already freed */
3068 if (instance->cmd_list == NULL) {
3069 return;
3070 }
3071
3072 max_cmd = instance->max_fw_cmds;
3073
3074 /* size of cmd_list array */
3075 sz = sizeof (struct mrsas_cmd *) * max_cmd;
3076
3077 /* First free each cmd */
3078 for (i = 0; i < max_cmd; i++) {
3079 if (instance->cmd_list[i] != NULL) {
3080 kmem_free(instance->cmd_list[i],
3081 sizeof (struct mrsas_cmd));
3082 }
3083
3084 instance->cmd_list[i] = NULL;
3085 }
3086
3087 /* Now, free cmd_list array */
3088 if (instance->cmd_list != NULL)
3089 kmem_free(instance->cmd_list, sz);
3090
3091 instance->cmd_list = NULL;
3092
3093 INIT_LIST_HEAD(&instance->cmd_pool_list);
3094 INIT_LIST_HEAD(&instance->cmd_pend_list);
3095 if (instance->tbolt) {
3096 INIT_LIST_HEAD(&instance->cmd_app_pool_list);
3097 } else {
3098 INIT_LIST_HEAD(&instance->app_cmd_pool_list);
3099 }
3100
3101 }
3102
3103
3104 /*
3105 * mrsas_alloc_cmd_pool
3106 */
3107 int
3108 mrsas_alloc_cmd_pool(struct mrsas_instance *instance)
3109 {
3110 int i;
3111 int count;
3112 uint32_t max_cmd;
3113 uint32_t reserve_cmd;
3114 size_t sz;
3115
3116 struct mrsas_cmd *cmd;
3117
3118 max_cmd = instance->max_fw_cmds;
3119 con_log(CL_ANN1, (CE_NOTE, "mrsas_alloc_cmd_pool: "
3120 "max_cmd %x", max_cmd));
3121
3122
3123 sz = sizeof (struct mrsas_cmd *) * max_cmd;
3124
3125 /*
3126 * instance->cmd_list is an array of struct mrsas_cmd pointers.
3127 * Allocate the dynamic array first and then allocate individual
3128 * commands.
3129 */
3130 instance->cmd_list = kmem_zalloc(sz, KM_SLEEP);
3131 ASSERT(instance->cmd_list);
3132
3133 /* create a frame pool and assign one frame to each cmd */
3134 for (count = 0; count < max_cmd; count++) {
3135 instance->cmd_list[count] =
3136 kmem_zalloc(sizeof (struct mrsas_cmd), KM_SLEEP);
3137 ASSERT(instance->cmd_list[count]);
3138 }
3139
3140 /* add all the commands to command pool */
3141
3142 INIT_LIST_HEAD(&instance->cmd_pool_list);
3143 INIT_LIST_HEAD(&instance->cmd_pend_list);
3144 INIT_LIST_HEAD(&instance->app_cmd_pool_list);
3145
3146 /*
3147 * When max_cmd is lower than MRSAS_APP_RESERVED_CMDS, how do I split
3148 * into app_cmd and regular cmd? For now, just take
3149 * max(1/8th of max, 4);
3150 */
3151 reserve_cmd = min(MRSAS_APP_RESERVED_CMDS,
3152 max(max_cmd >> 3, MRSAS_APP_MIN_RESERVED_CMDS));
3153
3154 for (i = 0; i < reserve_cmd; i++) {
3155 cmd = instance->cmd_list[i];
3156 cmd->index = i;
3157 mlist_add_tail(&cmd->list, &instance->app_cmd_pool_list);
3158 }
3159
3160
3161 for (i = reserve_cmd; i < max_cmd; i++) {
3162 cmd = instance->cmd_list[i];
3163 cmd->index = i;
3164 mlist_add_tail(&cmd->list, &instance->cmd_pool_list);
3165 }
3166
3167 return (DDI_SUCCESS);
3168
3169 mrsas_undo_cmds:
3170 if (count > 0) {
3171 /* free each cmd */
3172 for (i = 0; i < count; i++) {
3173 if (instance->cmd_list[i] != NULL) {
3174 kmem_free(instance->cmd_list[i],
3175 sizeof (struct mrsas_cmd));
3176 }
3177 instance->cmd_list[i] = NULL;
3178 }
3179 }
3180
3181 mrsas_undo_cmd_list:
3182 if (instance->cmd_list != NULL)
3183 kmem_free(instance->cmd_list, sz);
3184 instance->cmd_list = NULL;
3185
3186 return (DDI_FAILURE);
3187 }
3188
3189
3190 /*
3191 * free_space_for_mfi
3192 */
3193 static void
3194 free_space_for_mfi(struct mrsas_instance *instance)
3195 {
3196
3197 /* already freed */
3198 if (instance->cmd_list == NULL) {
3199 return;
3200 }
3201
3202 /* Free additional dma buffer */
3203 free_additional_dma_buffer(instance);
3204
3205 /* Free the MFI frame pool */
3206 destroy_mfi_frame_pool(instance);
3207
3208 /* Free all the commands in the cmd_list */
3209 /* Free the cmd_list buffer itself */
3210 mrsas_free_cmd_pool(instance);
3211 }
3212
3213 /*
3214 * alloc_space_for_mfi
3215 */
3216 static int
3217 alloc_space_for_mfi(struct mrsas_instance *instance)
3218 {
3219 /* Allocate command pool (memory for cmd_list & individual commands) */
3220 if (mrsas_alloc_cmd_pool(instance)) {
3221 dev_err(instance->dip, CE_WARN, "error creating cmd pool");
3222 return (DDI_FAILURE);
3223 }
3224
3225 /* Allocate MFI Frame pool */
3226 if (create_mfi_frame_pool(instance)) {
3227 dev_err(instance->dip, CE_WARN,
3228 "error creating frame DMA pool");
3229 goto mfi_undo_cmd_pool;
3230 }
3231
3232 /* Allocate additional DMA buffer */
3233 if (alloc_additional_dma_buffer(instance)) {
3234 dev_err(instance->dip, CE_WARN,
3235 "error creating frame DMA pool");
3236 goto mfi_undo_frame_pool;
3237 }
3238
3239 return (DDI_SUCCESS);
3240
3241 mfi_undo_frame_pool:
3242 destroy_mfi_frame_pool(instance);
3243
3244 mfi_undo_cmd_pool:
3245 mrsas_free_cmd_pool(instance);
3246
3247 return (DDI_FAILURE);
3248 }
3249
3250
3251
3252 /*
3253 * get_ctrl_info
3254 */
3255 static int
3256 get_ctrl_info(struct mrsas_instance *instance,
3257 struct mrsas_ctrl_info *ctrl_info)
3258 {
3259 int ret = 0;
3260
3261 struct mrsas_cmd *cmd;
3262 struct mrsas_dcmd_frame *dcmd;
3263 struct mrsas_ctrl_info *ci;
3264
3265 if (instance->tbolt) {
3266 cmd = get_raid_msg_mfi_pkt(instance);
3267 } else {
3268 cmd = mrsas_get_mfi_pkt(instance);
3269 }
3270
3271 if (!cmd) {
3272 con_log(CL_ANN, (CE_WARN,
3273 "Failed to get a cmd for ctrl info"));
3274 DTRACE_PROBE2(info_mfi_err, uint16_t, instance->fw_outstanding,
3275 uint16_t, instance->max_fw_cmds);
3276 return (DDI_FAILURE);
3277 }
3278
3279 /* Clear the frame buffer and assign back the context id */
3280 (void) memset((char *)&cmd->frame[0], 0, sizeof (union mrsas_frame));
3281 ddi_put32(cmd->frame_dma_obj.acc_handle, &cmd->frame->hdr.context,
3282 cmd->index);
3283
3284 dcmd = &cmd->frame->dcmd;
3285
3286 ci = (struct mrsas_ctrl_info *)instance->internal_buf;
3287
3288 if (!ci) {
3289 dev_err(instance->dip, CE_WARN,
3290 "Failed to alloc mem for ctrl info");
3291 mrsas_return_mfi_pkt(instance, cmd);
3292 return (DDI_FAILURE);
3293 }
3294
3295 (void) memset(ci, 0, sizeof (struct mrsas_ctrl_info));
3296
3297 /* for( i = 0; i < DCMD_MBOX_SZ; i++ ) dcmd->mbox.b[i] = 0; */
3298 (void) memset(dcmd->mbox.b, 0, DCMD_MBOX_SZ);
3299
3300 ddi_put8(cmd->frame_dma_obj.acc_handle, &dcmd->cmd, MFI_CMD_OP_DCMD);
3301 ddi_put8(cmd->frame_dma_obj.acc_handle, &dcmd->cmd_status,
3302 MFI_CMD_STATUS_POLL_MODE);
3303 ddi_put8(cmd->frame_dma_obj.acc_handle, &dcmd->sge_count, 1);
3304 ddi_put16(cmd->frame_dma_obj.acc_handle, &dcmd->flags,
3305 MFI_FRAME_DIR_READ);
3306 ddi_put16(cmd->frame_dma_obj.acc_handle, &dcmd->timeout, 0);
3307 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->data_xfer_len,
3308 sizeof (struct mrsas_ctrl_info));
3309 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->opcode,
3310 MR_DCMD_CTRL_GET_INFO);
3311 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->sgl.sge32[0].phys_addr,
3312 instance->internal_buf_dmac_add);
3313 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->sgl.sge32[0].length,
3314 sizeof (struct mrsas_ctrl_info));
3315
3316 cmd->frame_count = 1;
3317
3318 if (instance->tbolt) {
3319 mr_sas_tbolt_build_mfi_cmd(instance, cmd);
3320 }
3321
3322 if (!instance->func_ptr->issue_cmd_in_poll_mode(instance, cmd)) {
3323 ret = 0;
3324
3325 ctrl_info->max_request_size = ddi_get32(
3326 cmd->frame_dma_obj.acc_handle, &ci->max_request_size);
3327
3328 ctrl_info->ld_present_count = ddi_get16(
3329 cmd->frame_dma_obj.acc_handle, &ci->ld_present_count);
3330
3331 ctrl_info->properties.on_off_properties = ddi_get32(
3332 cmd->frame_dma_obj.acc_handle,
3333 &ci->properties.on_off_properties);
3334 ddi_rep_get8(cmd->frame_dma_obj.acc_handle,
3335 (uint8_t *)(ctrl_info->product_name),
3336 (uint8_t *)(ci->product_name), 80 * sizeof (char),
3337 DDI_DEV_AUTOINCR);
3338 /* should get more members of ci with ddi_get when needed */
3339 } else {
3340 dev_err(instance->dip, CE_WARN,
3341 "get_ctrl_info: Ctrl info failed");
3342 ret = -1;
3343 }
3344
3345 if (mrsas_common_check(instance, cmd) != DDI_SUCCESS) {
3346 ret = -1;
3347 }
3348 if (instance->tbolt) {
3349 return_raid_msg_mfi_pkt(instance, cmd);
3350 } else {
3351 mrsas_return_mfi_pkt(instance, cmd);
3352 }
3353
3354 return (ret);
3355 }
3356
3357 /*
3358 * abort_aen_cmd
3359 */
3360 static int
3361 abort_aen_cmd(struct mrsas_instance *instance,
3362 struct mrsas_cmd *cmd_to_abort)
3363 {
3364 int ret = 0;
3365
3366 struct mrsas_cmd *cmd;
3367 struct mrsas_abort_frame *abort_fr;
3368
3369 con_log(CL_ANN1, (CE_NOTE, "chkpnt: abort_aen:%d", __LINE__));
3370
3371 if (instance->tbolt) {
3372 cmd = get_raid_msg_mfi_pkt(instance);
3373 } else {
3374 cmd = mrsas_get_mfi_pkt(instance);
3375 }
3376
3377 if (!cmd) {
3378 con_log(CL_ANN1, (CE_WARN,
3379 "abort_aen_cmd():Failed to get a cmd for abort_aen_cmd"));
3380 DTRACE_PROBE2(abort_mfi_err, uint16_t, instance->fw_outstanding,
3381 uint16_t, instance->max_fw_cmds);
3382 return (DDI_FAILURE);
3383 }
3384
3385 /* Clear the frame buffer and assign back the context id */
3386 (void) memset((char *)&cmd->frame[0], 0, sizeof (union mrsas_frame));
3387 ddi_put32(cmd->frame_dma_obj.acc_handle, &cmd->frame->hdr.context,
3388 cmd->index);
3389
3390 abort_fr = &cmd->frame->abort;
3391
3392 /* prepare and issue the abort frame */
3393 ddi_put8(cmd->frame_dma_obj.acc_handle,
3394 &abort_fr->cmd, MFI_CMD_OP_ABORT);
3395 ddi_put8(cmd->frame_dma_obj.acc_handle, &abort_fr->cmd_status,
3396 MFI_CMD_STATUS_SYNC_MODE);
3397 ddi_put16(cmd->frame_dma_obj.acc_handle, &abort_fr->flags, 0);
3398 ddi_put32(cmd->frame_dma_obj.acc_handle, &abort_fr->abort_context,
3399 cmd_to_abort->index);
3400 ddi_put32(cmd->frame_dma_obj.acc_handle,
3401 &abort_fr->abort_mfi_phys_addr_lo, cmd_to_abort->frame_phys_addr);
3402 ddi_put32(cmd->frame_dma_obj.acc_handle,
3403 &abort_fr->abort_mfi_phys_addr_hi, 0);
3404
3405 instance->aen_cmd->abort_aen = 1;
3406
3407 cmd->frame_count = 1;
3408
3409 if (instance->tbolt) {
3410 mr_sas_tbolt_build_mfi_cmd(instance, cmd);
3411 }
3412
3413 if (instance->func_ptr->issue_cmd_in_poll_mode(instance, cmd)) {
3414 con_log(CL_ANN1, (CE_WARN,
3415 "abort_aen_cmd: issue_cmd_in_poll_mode failed"));
3416 ret = -1;
3417 } else {
3418 ret = 0;
3419 }
3420
3421 instance->aen_cmd->abort_aen = 1;
3422 instance->aen_cmd = 0;
3423
3424 if (instance->tbolt) {
3425 return_raid_msg_mfi_pkt(instance, cmd);
3426 } else {
3427 mrsas_return_mfi_pkt(instance, cmd);
3428 }
3429
3430 atomic_add_16(&instance->fw_outstanding, (-1));
3431
3432 return (ret);
3433 }
3434
3435
3436 static int
3437 mrsas_build_init_cmd(struct mrsas_instance *instance,
3438 struct mrsas_cmd **cmd_ptr)
3439 {
3440 struct mrsas_cmd *cmd;
3441 struct mrsas_init_frame *init_frame;
3442 struct mrsas_init_queue_info *initq_info;
3443 struct mrsas_drv_ver drv_ver_info;
3444
3445
3446 /*
3447 * Prepare a init frame. Note the init frame points to queue info
3448 * structure. Each frame has SGL allocated after first 64 bytes. For
3449 * this frame - since we don't need any SGL - we use SGL's space as
3450 * queue info structure
3451 */
3452 cmd = *cmd_ptr;
3453
3454
3455 /* Clear the frame buffer and assign back the context id */
3456 (void) memset((char *)&cmd->frame[0], 0, sizeof (union mrsas_frame));
3457 ddi_put32(cmd->frame_dma_obj.acc_handle, &cmd->frame->hdr.context,
3458 cmd->index);
3459
3460 init_frame = (struct mrsas_init_frame *)cmd->frame;
3461 initq_info = (struct mrsas_init_queue_info *)
3462 ((unsigned long)init_frame + 64);
3463
3464 (void) memset(init_frame, 0, MRMFI_FRAME_SIZE);
3465 (void) memset(initq_info, 0, sizeof (struct mrsas_init_queue_info));
3466
3467 ddi_put32(cmd->frame_dma_obj.acc_handle, &initq_info->init_flags, 0);
3468
3469 ddi_put32(cmd->frame_dma_obj.acc_handle,
3470 &initq_info->reply_queue_entries, instance->max_fw_cmds + 1);
3471
3472 ddi_put32(cmd->frame_dma_obj.acc_handle,
3473 &initq_info->producer_index_phys_addr_hi, 0);
3474 ddi_put32(cmd->frame_dma_obj.acc_handle,
3475 &initq_info->producer_index_phys_addr_lo,
3476 instance->mfi_internal_dma_obj.dma_cookie[0].dmac_address);
3477
3478 ddi_put32(cmd->frame_dma_obj.acc_handle,
3479 &initq_info->consumer_index_phys_addr_hi, 0);
3480 ddi_put32(cmd->frame_dma_obj.acc_handle,
3481 &initq_info->consumer_index_phys_addr_lo,
3482 instance->mfi_internal_dma_obj.dma_cookie[0].dmac_address + 4);
3483
3484 ddi_put32(cmd->frame_dma_obj.acc_handle,
3485 &initq_info->reply_queue_start_phys_addr_hi, 0);
3486 ddi_put32(cmd->frame_dma_obj.acc_handle,
3487 &initq_info->reply_queue_start_phys_addr_lo,
3488 instance->mfi_internal_dma_obj.dma_cookie[0].dmac_address + 8);
3489
3490 ddi_put8(cmd->frame_dma_obj.acc_handle,
3491 &init_frame->cmd, MFI_CMD_OP_INIT);
3492 ddi_put8(cmd->frame_dma_obj.acc_handle, &init_frame->cmd_status,
3493 MFI_CMD_STATUS_POLL_MODE);
3494 ddi_put16(cmd->frame_dma_obj.acc_handle, &init_frame->flags, 0);
3495 ddi_put32(cmd->frame_dma_obj.acc_handle,
3496 &init_frame->queue_info_new_phys_addr_lo,
3497 cmd->frame_phys_addr + 64);
3498 ddi_put32(cmd->frame_dma_obj.acc_handle,
3499 &init_frame->queue_info_new_phys_addr_hi, 0);
3500
3501
3502 /* fill driver version information */
3503 fill_up_drv_ver(&drv_ver_info);
3504
3505 /* allocate the driver version data transfer buffer */
3506 instance->drv_ver_dma_obj.size = sizeof (drv_ver_info.drv_ver);
3507 instance->drv_ver_dma_obj.dma_attr = mrsas_generic_dma_attr;
3508 instance->drv_ver_dma_obj.dma_attr.dma_attr_addr_hi = 0xFFFFFFFFU;
3509 instance->drv_ver_dma_obj.dma_attr.dma_attr_count_max = 0xFFFFFFFFU;
3510 instance->drv_ver_dma_obj.dma_attr.dma_attr_sgllen = 1;
3511 instance->drv_ver_dma_obj.dma_attr.dma_attr_align = 1;
3512
3513 if (mrsas_alloc_dma_obj(instance, &instance->drv_ver_dma_obj,
3514 (uchar_t)DDI_STRUCTURE_LE_ACC) != 1) {
3515 con_log(CL_ANN, (CE_WARN,
3516 "init_mfi : Could not allocate driver version buffer."));
3517 return (DDI_FAILURE);
3518 }
3519 /* copy driver version to dma buffer */
3520 (void) memset(instance->drv_ver_dma_obj.buffer, 0,
3521 sizeof (drv_ver_info.drv_ver));
3522 ddi_rep_put8(cmd->frame_dma_obj.acc_handle,
3523 (uint8_t *)drv_ver_info.drv_ver,
3524 (uint8_t *)instance->drv_ver_dma_obj.buffer,
3525 sizeof (drv_ver_info.drv_ver), DDI_DEV_AUTOINCR);
3526
3527
3528 /* copy driver version physical address to init frame */
3529 ddi_put64(cmd->frame_dma_obj.acc_handle, &init_frame->driverversion,
3530 instance->drv_ver_dma_obj.dma_cookie[0].dmac_address);
3531
3532 ddi_put32(cmd->frame_dma_obj.acc_handle, &init_frame->data_xfer_len,
3533 sizeof (struct mrsas_init_queue_info));
3534
3535 cmd->frame_count = 1;
3536
3537 *cmd_ptr = cmd;
3538
3539 return (DDI_SUCCESS);
3540 }
3541
3542
3543 /*
3544 * mrsas_init_adapter_ppc - Initialize MFI interface adapter.
3545 */
3546 int
3547 mrsas_init_adapter_ppc(struct mrsas_instance *instance)
3548 {
3549 struct mrsas_cmd *cmd;
3550
3551 /*
3552 * allocate memory for mfi adapter(cmd pool, individual commands, mfi
3553 * frames etc
3554 */
3555 if (alloc_space_for_mfi(instance) != DDI_SUCCESS) {
3556 con_log(CL_ANN, (CE_NOTE,
3557 "Error, failed to allocate memory for MFI adapter"));
3558 return (DDI_FAILURE);
3559 }
3560
3561 /* Build INIT command */
3562 cmd = mrsas_get_mfi_pkt(instance);
3563 if (cmd == NULL) {
3564 DTRACE_PROBE2(init_adapter_mfi_err, uint16_t,
3565 instance->fw_outstanding, uint16_t, instance->max_fw_cmds);
3566 return (DDI_FAILURE);
3567 }
3568
3569 if (mrsas_build_init_cmd(instance, &cmd) != DDI_SUCCESS) {
3570 con_log(CL_ANN,
3571 (CE_NOTE, "Error, failed to build INIT command"));
3572
3573 goto fail_undo_alloc_mfi_space;
3574 }
3575
3576 /*
3577 * Disable interrupt before sending init frame ( see linux driver code)
3578 * send INIT MFI frame in polled mode
3579 */
3580 if (instance->func_ptr->issue_cmd_in_poll_mode(instance, cmd)) {
3581 con_log(CL_ANN, (CE_WARN, "failed to init firmware"));
3582 goto fail_fw_init;
3583 }
3584
3585 if (mrsas_common_check(instance, cmd) != DDI_SUCCESS)
3586 goto fail_fw_init;
3587 mrsas_return_mfi_pkt(instance, cmd);
3588
3589 if (ctio_enable &&
3590 (instance->func_ptr->read_fw_status_reg(instance) & 0x04000000)) {
3591 con_log(CL_ANN, (CE_NOTE, "mr_sas: IEEE SGL's supported"));
3592 instance->flag_ieee = 1;
3593 } else {
3594 instance->flag_ieee = 0;
3595 }
3596
3597 ASSERT(!instance->skinny || instance->flag_ieee);
3598
3599 instance->unroll.alloc_space_mfi = 1;
3600 instance->unroll.verBuff = 1;
3601
3602 return (DDI_SUCCESS);
3603
3604
3605 fail_fw_init:
3606 (void) mrsas_free_dma_obj(instance, instance->drv_ver_dma_obj);
3607
3608 fail_undo_alloc_mfi_space:
3609 mrsas_return_mfi_pkt(instance, cmd);
3610 free_space_for_mfi(instance);
3611
3612 return (DDI_FAILURE);
3613
3614 }
3615
3616 /*
3617 * mrsas_init_adapter - Initialize adapter.
3618 */
3619 int
3620 mrsas_init_adapter(struct mrsas_instance *instance)
3621 {
3622 struct mrsas_ctrl_info ctrl_info;
3623
3624
3625 /* we expect the FW state to be READY */
3626 if (mfi_state_transition_to_ready(instance)) {
3627 con_log(CL_ANN, (CE_WARN, "mr_sas: F/W is not ready"));
3628 return (DDI_FAILURE);
3629 }
3630
3631 /* get various operational parameters from status register */
3632 instance->max_num_sge =
3633 (instance->func_ptr->read_fw_status_reg(instance) &
3634 0xFF0000) >> 0x10;
3635 instance->max_num_sge =
3636 (instance->max_num_sge > MRSAS_MAX_SGE_CNT) ?
3637 MRSAS_MAX_SGE_CNT : instance->max_num_sge;
3638
3639 /*
3640 * Reduce the max supported cmds by 1. This is to ensure that the
3641 * reply_q_sz (1 more than the max cmd that driver may send)
3642 * does not exceed max cmds that the FW can support
3643 */
3644 instance->max_fw_cmds =
3645 instance->func_ptr->read_fw_status_reg(instance) & 0xFFFF;
3646 instance->max_fw_cmds = instance->max_fw_cmds - 1;
3647
3648
3649
3650 /* Initialize adapter */
3651 if (instance->func_ptr->init_adapter(instance) != DDI_SUCCESS) {
3652 con_log(CL_ANN,
3653 (CE_WARN, "mr_sas: could not initialize adapter"));
3654 return (DDI_FAILURE);
3655 }
3656
3657 /* gather misc FW related information */
3658 instance->disable_online_ctrl_reset = 0;
3659
3660 if (!get_ctrl_info(instance, &ctrl_info)) {
3661 instance->max_sectors_per_req = ctrl_info.max_request_size;
3662 con_log(CL_ANN1, (CE_NOTE,
3663 "product name %s ld present %d",
3664 ctrl_info.product_name, ctrl_info.ld_present_count));
3665 } else {
3666 instance->max_sectors_per_req = instance->max_num_sge *
3667 PAGESIZE / 512;
3668 }
3669
3670 if (ctrl_info.properties.on_off_properties & DISABLE_OCR_PROP_FLAG)
3671 instance->disable_online_ctrl_reset = 1;
3672
3673 return (DDI_SUCCESS);
3674
3675 }
3676
3677
3678
3679 static int
3680 mrsas_issue_init_mfi(struct mrsas_instance *instance)
3681 {
3682 struct mrsas_cmd *cmd;
3683 struct mrsas_init_frame *init_frame;
3684 struct mrsas_init_queue_info *initq_info;
3685
3686 /*
3687 * Prepare a init frame. Note the init frame points to queue info
3688 * structure. Each frame has SGL allocated after first 64 bytes. For
3689 * this frame - since we don't need any SGL - we use SGL's space as
3690 * queue info structure
3691 */
3692 con_log(CL_ANN1, (CE_NOTE,
3693 "mrsas_issue_init_mfi: entry\n"));
3694 cmd = get_mfi_app_pkt(instance);
3695
3696 if (!cmd) {
3697 con_log(CL_ANN1, (CE_WARN,
3698 "mrsas_issue_init_mfi: get_pkt failed\n"));
3699 return (DDI_FAILURE);
3700 }
3701
3702 /* Clear the frame buffer and assign back the context id */
3703 (void) memset((char *)&cmd->frame[0], 0, sizeof (union mrsas_frame));
3704 ddi_put32(cmd->frame_dma_obj.acc_handle, &cmd->frame->hdr.context,
3705 cmd->index);
3706
3707 init_frame = (struct mrsas_init_frame *)cmd->frame;
3708 initq_info = (struct mrsas_init_queue_info *)
3709 ((unsigned long)init_frame + 64);
3710
3711 (void) memset(init_frame, 0, MRMFI_FRAME_SIZE);
3712 (void) memset(initq_info, 0, sizeof (struct mrsas_init_queue_info));
3713
3714 ddi_put32(cmd->frame_dma_obj.acc_handle, &initq_info->init_flags, 0);
3715
3716 ddi_put32(cmd->frame_dma_obj.acc_handle,
3717 &initq_info->reply_queue_entries, instance->max_fw_cmds + 1);
3718 ddi_put32(cmd->frame_dma_obj.acc_handle,
3719 &initq_info->producer_index_phys_addr_hi, 0);
3720 ddi_put32(cmd->frame_dma_obj.acc_handle,
3721 &initq_info->producer_index_phys_addr_lo,
3722 instance->mfi_internal_dma_obj.dma_cookie[0].dmac_address);
3723 ddi_put32(cmd->frame_dma_obj.acc_handle,
3724 &initq_info->consumer_index_phys_addr_hi, 0);
3725 ddi_put32(cmd->frame_dma_obj.acc_handle,
3726 &initq_info->consumer_index_phys_addr_lo,
3727 instance->mfi_internal_dma_obj.dma_cookie[0].dmac_address + 4);
3728
3729 ddi_put32(cmd->frame_dma_obj.acc_handle,
3730 &initq_info->reply_queue_start_phys_addr_hi, 0);
3731 ddi_put32(cmd->frame_dma_obj.acc_handle,
3732 &initq_info->reply_queue_start_phys_addr_lo,
3733 instance->mfi_internal_dma_obj.dma_cookie[0].dmac_address + 8);
3734
3735 ddi_put8(cmd->frame_dma_obj.acc_handle,
3736 &init_frame->cmd, MFI_CMD_OP_INIT);
3737 ddi_put8(cmd->frame_dma_obj.acc_handle, &init_frame->cmd_status,
3738 MFI_CMD_STATUS_POLL_MODE);
3739 ddi_put16(cmd->frame_dma_obj.acc_handle, &init_frame->flags, 0);
3740 ddi_put32(cmd->frame_dma_obj.acc_handle,
3741 &init_frame->queue_info_new_phys_addr_lo,
3742 cmd->frame_phys_addr + 64);
3743 ddi_put32(cmd->frame_dma_obj.acc_handle,
3744 &init_frame->queue_info_new_phys_addr_hi, 0);
3745
3746 ddi_put32(cmd->frame_dma_obj.acc_handle, &init_frame->data_xfer_len,
3747 sizeof (struct mrsas_init_queue_info));
3748
3749 cmd->frame_count = 1;
3750
3751 /* issue the init frame in polled mode */
3752 if (instance->func_ptr->issue_cmd_in_poll_mode(instance, cmd)) {
3753 con_log(CL_ANN1, (CE_WARN,
3754 "mrsas_issue_init_mfi():failed to "
3755 "init firmware"));
3756 return_mfi_app_pkt(instance, cmd);
3757 return (DDI_FAILURE);
3758 }
3759
3760 if (mrsas_common_check(instance, cmd) != DDI_SUCCESS) {
3761 return_mfi_app_pkt(instance, cmd);
3762 return (DDI_FAILURE);
3763 }
3764
3765 return_mfi_app_pkt(instance, cmd);
3766 con_log(CL_ANN1, (CE_CONT, "mrsas_issue_init_mfi: Done"));
3767
3768 return (DDI_SUCCESS);
3769 }
3770 /*
3771 * mfi_state_transition_to_ready : Move the FW to READY state
3772 *
3773 * @reg_set : MFI register set
3774 */
3775 int
3776 mfi_state_transition_to_ready(struct mrsas_instance *instance)
3777 {
3778 int i;
3779 uint8_t max_wait;
3780 uint32_t fw_ctrl = 0;
3781 uint32_t fw_state;
3782 uint32_t cur_state;
3783 uint32_t cur_abs_reg_val;
3784 uint32_t prev_abs_reg_val;
3785 uint32_t status;
3786
3787 cur_abs_reg_val =
3788 instance->func_ptr->read_fw_status_reg(instance);
3789 fw_state =
3790 cur_abs_reg_val & MFI_STATE_MASK;
3791 con_log(CL_ANN1, (CE_CONT,
3792 "mfi_state_transition_to_ready:FW state = 0x%x", fw_state));
3793
3794 while (fw_state != MFI_STATE_READY) {
3795 con_log(CL_ANN, (CE_CONT,
3796 "mfi_state_transition_to_ready:FW state%x", fw_state));
3797
3798 switch (fw_state) {
3799 case MFI_STATE_FAULT:
3800 con_log(CL_ANN, (CE_NOTE,
3801 "mr_sas: FW in FAULT state!!"));
3802
3803 return (ENODEV);
3804 case MFI_STATE_WAIT_HANDSHAKE:
3805 /* set the CLR bit in IMR0 */
3806 con_log(CL_ANN1, (CE_NOTE,
3807 "mr_sas: FW waiting for HANDSHAKE"));
3808 /*
3809 * PCI_Hot Plug: MFI F/W requires
3810 * (MFI_INIT_CLEAR_HANDSHAKE|MFI_INIT_HOTPLUG)
3811 * to be set
3812 */
3813 /* WR_IB_MSG_0(MFI_INIT_CLEAR_HANDSHAKE, instance); */
3814 if (!instance->tbolt && !instance->skinny) {
3815 WR_IB_DOORBELL(MFI_INIT_CLEAR_HANDSHAKE |
3816 MFI_INIT_HOTPLUG, instance);
3817 } else {
3818 WR_RESERVED0_REGISTER(MFI_INIT_CLEAR_HANDSHAKE |
3819 MFI_INIT_HOTPLUG, instance);
3820 }
3821 max_wait = (instance->tbolt == 1) ? 180 : 2;
3822 cur_state = MFI_STATE_WAIT_HANDSHAKE;
3823 break;
3824 case MFI_STATE_BOOT_MESSAGE_PENDING:
3825 /* set the CLR bit in IMR0 */
3826 con_log(CL_ANN1, (CE_NOTE,
3827 "mr_sas: FW state boot message pending"));
3828 /*
3829 * PCI_Hot Plug: MFI F/W requires
3830 * (MFI_INIT_CLEAR_HANDSHAKE|MFI_INIT_HOTPLUG)
3831 * to be set
3832 */
3833 if (!instance->tbolt && !instance->skinny) {
3834 WR_IB_DOORBELL(MFI_INIT_HOTPLUG, instance);
3835 } else {
3836 WR_RESERVED0_REGISTER(MFI_INIT_HOTPLUG,
3837 instance);
3838 }
3839 max_wait = (instance->tbolt == 1) ? 180 : 10;
3840 cur_state = MFI_STATE_BOOT_MESSAGE_PENDING;
3841 break;
3842 case MFI_STATE_OPERATIONAL:
3843 /* bring it to READY state; assuming max wait 2 secs */
3844 instance->func_ptr->disable_intr(instance);
3845 con_log(CL_ANN1, (CE_NOTE,
3846 "mr_sas: FW in OPERATIONAL state"));
3847 /*
3848 * PCI_Hot Plug: MFI F/W requires
3849 * (MFI_INIT_READY | MFI_INIT_MFIMODE | MFI_INIT_ABORT)
3850 * to be set
3851 */
3852 /* WR_IB_DOORBELL(MFI_INIT_READY, instance); */
3853 if (!instance->tbolt && !instance->skinny) {
3854 WR_IB_DOORBELL(MFI_RESET_FLAGS, instance);
3855 } else {
3856 WR_RESERVED0_REGISTER(MFI_RESET_FLAGS,
3857 instance);
3858
3859 for (i = 0; i < (10 * 1000); i++) {
3860 status =
3861 RD_RESERVED0_REGISTER(instance);
3862 if (status & 1) {
3863 delay(1 *
3864 drv_usectohz(MILLISEC));
3865 } else {
3866 break;
3867 }
3868 }
3869
3870 }
3871 max_wait = (instance->tbolt == 1) ? 180 : 10;
3872 cur_state = MFI_STATE_OPERATIONAL;
3873 break;
3874 case MFI_STATE_UNDEFINED:
3875 /* this state should not last for more than 2 seconds */
3876 con_log(CL_ANN1, (CE_NOTE, "FW state undefined"));
3877
3878 max_wait = (instance->tbolt == 1) ? 180 : 2;
3879 cur_state = MFI_STATE_UNDEFINED;
3880 break;
3881 case MFI_STATE_BB_INIT:
3882 max_wait = (instance->tbolt == 1) ? 180 : 2;
3883 cur_state = MFI_STATE_BB_INIT;
3884 break;
3885 case MFI_STATE_FW_INIT:
3886 max_wait = (instance->tbolt == 1) ? 180 : 2;
3887 cur_state = MFI_STATE_FW_INIT;
3888 break;
3889 case MFI_STATE_FW_INIT_2:
3890 max_wait = 180;
3891 cur_state = MFI_STATE_FW_INIT_2;
3892 break;
3893 case MFI_STATE_DEVICE_SCAN:
3894 max_wait = 180;
3895 cur_state = MFI_STATE_DEVICE_SCAN;
3896 prev_abs_reg_val = cur_abs_reg_val;
3897 con_log(CL_NONE, (CE_NOTE,
3898 "Device scan in progress ...\n"));
3899 break;
3900 case MFI_STATE_FLUSH_CACHE:
3901 max_wait = 180;
3902 cur_state = MFI_STATE_FLUSH_CACHE;
3903 break;
3904 default:
3905 con_log(CL_ANN1, (CE_NOTE,
3906 "mr_sas: Unknown state 0x%x", fw_state));
3907 return (ENODEV);
3908 }
3909
3910 /* the cur_state should not last for more than max_wait secs */
3911 for (i = 0; i < (max_wait * MILLISEC); i++) {
3912 /* fw_state = RD_OB_MSG_0(instance) & MFI_STATE_MASK; */
3913 cur_abs_reg_val =
3914 instance->func_ptr->read_fw_status_reg(instance);
3915 fw_state = cur_abs_reg_val & MFI_STATE_MASK;
3916
3917 if (fw_state == cur_state) {
3918 delay(1 * drv_usectohz(MILLISEC));
3919 } else {
3920 break;
3921 }
3922 }
3923 if (fw_state == MFI_STATE_DEVICE_SCAN) {
3924 if (prev_abs_reg_val != cur_abs_reg_val) {
3925 continue;
3926 }
3927 }
3928
3929 /* return error if fw_state hasn't changed after max_wait */
3930 if (fw_state == cur_state) {
3931 con_log(CL_ANN1, (CE_WARN,
3932 "FW state hasn't changed in %d secs", max_wait));
3933 return (ENODEV);
3934 }
3935 };
3936
3937 /* This may also need to apply to Skinny, but for now, don't worry. */
3938 if (!instance->tbolt && !instance->skinny) {
3939 fw_ctrl = RD_IB_DOORBELL(instance);
3940 con_log(CL_ANN1, (CE_CONT,
3941 "mfi_state_transition_to_ready:FW ctrl = 0x%x", fw_ctrl));
3942
3943 /*
3944 * Write 0xF to the doorbell register to do the following.
3945 * - Abort all outstanding commands (bit 0).
3946 * - Transition from OPERATIONAL to READY state (bit 1).
3947 * - Discard (possible) low MFA posted in 64-bit mode (bit-2).
3948 * - Set to release FW to continue running (i.e. BIOS handshake
3949 * (bit 3).
3950 */
3951 WR_IB_DOORBELL(0xF, instance);
3952 }
3953
3954 if (mrsas_check_acc_handle(instance->regmap_handle) != DDI_SUCCESS) {
3955 return (EIO);
3956 }
3957
3958 return (DDI_SUCCESS);
3959 }
3960
3961 /*
3962 * get_seq_num
3963 */
3964 static int
3965 get_seq_num(struct mrsas_instance *instance,
3966 struct mrsas_evt_log_info *eli)
3967 {
3968 int ret = DDI_SUCCESS;
3969
3970 dma_obj_t dcmd_dma_obj;
3971 struct mrsas_cmd *cmd;
3972 struct mrsas_dcmd_frame *dcmd;
3973 struct mrsas_evt_log_info *eli_tmp;
3974 if (instance->tbolt) {
3975 cmd = get_raid_msg_mfi_pkt(instance);
3976 } else {
3977 cmd = mrsas_get_mfi_pkt(instance);
3978 }
3979
3980 if (!cmd) {
3981 dev_err(instance->dip, CE_WARN, "failed to get a cmd");
3982 DTRACE_PROBE2(seq_num_mfi_err, uint16_t,
3983 instance->fw_outstanding, uint16_t, instance->max_fw_cmds);
3984 return (ENOMEM);
3985 }
3986
3987 /* Clear the frame buffer and assign back the context id */
3988 (void) memset((char *)&cmd->frame[0], 0, sizeof (union mrsas_frame));
3989 ddi_put32(cmd->frame_dma_obj.acc_handle, &cmd->frame->hdr.context,
3990 cmd->index);
3991
3992 dcmd = &cmd->frame->dcmd;
3993
3994 /* allocate the data transfer buffer */
3995 dcmd_dma_obj.size = sizeof (struct mrsas_evt_log_info);
3996 dcmd_dma_obj.dma_attr = mrsas_generic_dma_attr;
3997 dcmd_dma_obj.dma_attr.dma_attr_addr_hi = 0xFFFFFFFFU;
3998 dcmd_dma_obj.dma_attr.dma_attr_count_max = 0xFFFFFFFFU;
3999 dcmd_dma_obj.dma_attr.dma_attr_sgllen = 1;
4000 dcmd_dma_obj.dma_attr.dma_attr_align = 1;
4001
4002 if (mrsas_alloc_dma_obj(instance, &dcmd_dma_obj,
4003 (uchar_t)DDI_STRUCTURE_LE_ACC) != 1) {
4004 dev_err(instance->dip, CE_WARN,
4005 "get_seq_num: could not allocate data transfer buffer.");
4006 return (DDI_FAILURE);
4007 }
4008
4009 (void) memset(dcmd_dma_obj.buffer, 0,
4010 sizeof (struct mrsas_evt_log_info));
4011
4012 (void) memset(dcmd->mbox.b, 0, DCMD_MBOX_SZ);
4013
4014 ddi_put8(cmd->frame_dma_obj.acc_handle, &dcmd->cmd, MFI_CMD_OP_DCMD);
4015 ddi_put8(cmd->frame_dma_obj.acc_handle, &dcmd->cmd_status, 0);
4016 ddi_put8(cmd->frame_dma_obj.acc_handle, &dcmd->sge_count, 1);
4017 ddi_put16(cmd->frame_dma_obj.acc_handle, &dcmd->flags,
4018 MFI_FRAME_DIR_READ);
4019 ddi_put16(cmd->frame_dma_obj.acc_handle, &dcmd->timeout, 0);
4020 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->data_xfer_len,
4021 sizeof (struct mrsas_evt_log_info));
4022 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->opcode,
4023 MR_DCMD_CTRL_EVENT_GET_INFO);
4024 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->sgl.sge32[0].length,
4025 sizeof (struct mrsas_evt_log_info));
4026 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->sgl.sge32[0].phys_addr,
4027 dcmd_dma_obj.dma_cookie[0].dmac_address);
4028
4029 cmd->sync_cmd = MRSAS_TRUE;
4030 cmd->frame_count = 1;
4031
4032 if (instance->tbolt) {
4033 mr_sas_tbolt_build_mfi_cmd(instance, cmd);
4034 }
4035
4036 if (instance->func_ptr->issue_cmd_in_sync_mode(instance, cmd)) {
4037 dev_err(instance->dip, CE_WARN, "get_seq_num: "
4038 "failed to issue MRSAS_DCMD_CTRL_EVENT_GET_INFO");
4039 ret = DDI_FAILURE;
4040 } else {
4041 eli_tmp = (struct mrsas_evt_log_info *)dcmd_dma_obj.buffer;
4042 eli->newest_seq_num = ddi_get32(cmd->frame_dma_obj.acc_handle,
4043 &eli_tmp->newest_seq_num);
4044 ret = DDI_SUCCESS;
4045 }
4046
4047 if (mrsas_free_dma_obj(instance, dcmd_dma_obj) != DDI_SUCCESS)
4048 ret = DDI_FAILURE;
4049
4050 if (instance->tbolt) {
4051 return_raid_msg_mfi_pkt(instance, cmd);
4052 } else {
4053 mrsas_return_mfi_pkt(instance, cmd);
4054 }
4055
4056 return (ret);
4057 }
4058
4059 /*
4060 * start_mfi_aen
4061 */
4062 static int
4063 start_mfi_aen(struct mrsas_instance *instance)
4064 {
4065 int ret = 0;
4066
4067 struct mrsas_evt_log_info eli;
4068 union mrsas_evt_class_locale class_locale;
4069
4070 /* get the latest sequence number from FW */
4071 (void) memset(&eli, 0, sizeof (struct mrsas_evt_log_info));
4072
4073 if (get_seq_num(instance, &eli)) {
4074 dev_err(instance->dip, CE_WARN,
4075 "start_mfi_aen: failed to get seq num");
4076 return (-1);
4077 }
4078
4079 /* register AEN with FW for latest sequence number plus 1 */
4080 class_locale.members.reserved = 0;
4081 class_locale.members.locale = LE_16(MR_EVT_LOCALE_ALL);
4082 class_locale.members.class = MR_EVT_CLASS_INFO;
4083 class_locale.word = LE_32(class_locale.word);
4084 ret = register_mfi_aen(instance, eli.newest_seq_num + 1,
4085 class_locale.word);
4086
4087 if (ret) {
4088 dev_err(instance->dip, CE_WARN,
4089 "start_mfi_aen: aen registration failed");
4090 return (-1);
4091 }
4092
4093
4094 return (ret);
4095 }
4096
4097 /*
4098 * flush_cache
4099 */
4100 static void
4101 flush_cache(struct mrsas_instance *instance)
4102 {
4103 struct mrsas_cmd *cmd = NULL;
4104 struct mrsas_dcmd_frame *dcmd;
4105 if (instance->tbolt) {
4106 cmd = get_raid_msg_mfi_pkt(instance);
4107 } else {
4108 cmd = mrsas_get_mfi_pkt(instance);
4109 }
4110
4111 if (!cmd) {
4112 con_log(CL_ANN1, (CE_WARN,
4113 "flush_cache():Failed to get a cmd for flush_cache"));
4114 DTRACE_PROBE2(flush_cache_err, uint16_t,
4115 instance->fw_outstanding, uint16_t, instance->max_fw_cmds);
4116 return;
4117 }
4118
4119 /* Clear the frame buffer and assign back the context id */
4120 (void) memset((char *)&cmd->frame[0], 0, sizeof (union mrsas_frame));
4121 ddi_put32(cmd->frame_dma_obj.acc_handle, &cmd->frame->hdr.context,
4122 cmd->index);
4123
4124 dcmd = &cmd->frame->dcmd;
4125
4126 (void) memset(dcmd->mbox.b, 0, DCMD_MBOX_SZ);
4127
4128 ddi_put8(cmd->frame_dma_obj.acc_handle, &dcmd->cmd, MFI_CMD_OP_DCMD);
4129 ddi_put8(cmd->frame_dma_obj.acc_handle, &dcmd->cmd_status, 0x0);
4130 ddi_put8(cmd->frame_dma_obj.acc_handle, &dcmd->sge_count, 0);
4131 ddi_put16(cmd->frame_dma_obj.acc_handle, &dcmd->flags,
4132 MFI_FRAME_DIR_NONE);
4133 ddi_put16(cmd->frame_dma_obj.acc_handle, &dcmd->timeout, 0);
4134 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->data_xfer_len, 0);
4135 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->opcode,
4136 MR_DCMD_CTRL_CACHE_FLUSH);
4137 ddi_put8(cmd->frame_dma_obj.acc_handle, &dcmd->mbox.b[0],
4138 MR_FLUSH_CTRL_CACHE | MR_FLUSH_DISK_CACHE);
4139
4140 cmd->frame_count = 1;
4141
4142 if (instance->tbolt) {
4143 mr_sas_tbolt_build_mfi_cmd(instance, cmd);
4144 }
4145
4146 if (instance->func_ptr->issue_cmd_in_poll_mode(instance, cmd)) {
4147 con_log(CL_ANN1, (CE_WARN,
4148 "flush_cache: failed to issue MFI_DCMD_CTRL_CACHE_FLUSH"));
4149 }
4150 con_log(CL_ANN1, (CE_CONT, "flush_cache done"));
4151 if (instance->tbolt) {
4152 return_raid_msg_mfi_pkt(instance, cmd);
4153 } else {
4154 mrsas_return_mfi_pkt(instance, cmd);
4155 }
4156
4157 }
4158
4159 /*
4160 * service_mfi_aen- Completes an AEN command
4161 * @instance: Adapter soft state
4162 * @cmd: Command to be completed
4163 *
4164 */
4165 void
4166 service_mfi_aen(struct mrsas_instance *instance, struct mrsas_cmd *cmd)
4167 {
4168 uint32_t seq_num;
4169 struct mrsas_evt_detail *evt_detail =
4170 (struct mrsas_evt_detail *)instance->mfi_evt_detail_obj.buffer;
4171 int rval = 0;
4172 int tgt = 0;
4173 uint8_t dtype;
4174 mrsas_pd_address_t *pd_addr;
4175 ddi_acc_handle_t acc_handle;
4176
4177 con_log(CL_ANN, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__));
4178
4179 acc_handle = cmd->frame_dma_obj.acc_handle;
4180 cmd->cmd_status = ddi_get8(acc_handle, &cmd->frame->io.cmd_status);
4181 if (cmd->cmd_status == ENODATA) {
4182 cmd->cmd_status = 0;
4183 }
4184
4185 /*
4186 * log the MFI AEN event to the sysevent queue so that
4187 * application will get noticed
4188 */
4189 if (ddi_log_sysevent(instance->dip, DDI_VENDOR_LSI, "LSIMEGA", "SAS",
4190 NULL, NULL, DDI_NOSLEEP) != DDI_SUCCESS) {
4191 int instance_no = ddi_get_instance(instance->dip);
4192 con_log(CL_ANN, (CE_WARN,
4193 "mr_sas%d: Failed to log AEN event", instance_no));
4194 }
4195 /*
4196 * Check for any ld devices that has changed state. i.e. online
4197 * or offline.
4198 */
4199 con_log(CL_ANN1, (CE_CONT,
4200 "AEN: code = %x class = %x locale = %x args = %x",
4201 ddi_get32(acc_handle, &evt_detail->code),
4202 evt_detail->cl.members.class,
4203 ddi_get16(acc_handle, &evt_detail->cl.members.locale),
4204 ddi_get8(acc_handle, &evt_detail->arg_type)));
4205
4206 switch (ddi_get32(acc_handle, &evt_detail->code)) {
4207 case MR_EVT_CFG_CLEARED: {
4208 for (tgt = 0; tgt < MRDRV_MAX_LD; tgt++) {
4209 if (instance->mr_ld_list[tgt].dip != NULL) {
4210 mutex_enter(&instance->config_dev_mtx);
4211 instance->mr_ld_list[tgt].flag =
4212 (uint8_t)~MRDRV_TGT_VALID;
4213 mutex_exit(&instance->config_dev_mtx);
4214 rval = mrsas_service_evt(instance, tgt, 0,
4215 MRSAS_EVT_UNCONFIG_TGT, NULL);
4216 con_log(CL_ANN1, (CE_WARN,
4217 "mr_sas: CFG CLEARED AEN rval = %d "
4218 "tgt id = %d", rval, tgt));
4219 }
4220 }
4221 break;
4222 }
4223
4224 case MR_EVT_LD_DELETED: {
4225 tgt = ddi_get16(acc_handle, &evt_detail->args.ld.target_id);
4226 mutex_enter(&instance->config_dev_mtx);
4227 instance->mr_ld_list[tgt].flag = (uint8_t)~MRDRV_TGT_VALID;
4228 mutex_exit(&instance->config_dev_mtx);
4229 rval = mrsas_service_evt(instance,
4230 ddi_get16(acc_handle, &evt_detail->args.ld.target_id), 0,
4231 MRSAS_EVT_UNCONFIG_TGT, NULL);
4232 con_log(CL_ANN1, (CE_WARN, "mr_sas: LD DELETED AEN rval = %d "
4233 "tgt id = %d index = %d", rval,
4234 ddi_get16(acc_handle, &evt_detail->args.ld.target_id),
4235 ddi_get8(acc_handle, &evt_detail->args.ld.ld_index)));
4236 break;
4237 } /* End of MR_EVT_LD_DELETED */
4238
4239 case MR_EVT_LD_CREATED: {
4240 rval = mrsas_service_evt(instance,
4241 ddi_get16(acc_handle, &evt_detail->args.ld.target_id), 0,
4242 MRSAS_EVT_CONFIG_TGT, NULL);
4243 con_log(CL_ANN1, (CE_WARN, "mr_sas: LD CREATED AEN rval = %d "
4244 "tgt id = %d index = %d", rval,
4245 ddi_get16(acc_handle, &evt_detail->args.ld.target_id),
4246 ddi_get8(acc_handle, &evt_detail->args.ld.ld_index)));
4247 break;
4248 } /* End of MR_EVT_LD_CREATED */
4249
4250 case MR_EVT_PD_REMOVED_EXT: {
4251 if (instance->tbolt || instance->skinny) {
4252 pd_addr = &evt_detail->args.pd_addr;
4253 dtype = pd_addr->scsi_dev_type;
4254 con_log(CL_DLEVEL1, (CE_NOTE,
4255 " MR_EVT_PD_REMOVED_EXT: dtype = %x,"
4256 " arg_type = %d ", dtype, evt_detail->arg_type));
4257 tgt = ddi_get16(acc_handle,
4258 &evt_detail->args.pd.device_id);
4259 mutex_enter(&instance->config_dev_mtx);
4260 instance->mr_tbolt_pd_list[tgt].flag =
4261 (uint8_t)~MRDRV_TGT_VALID;
4262 mutex_exit(&instance->config_dev_mtx);
4263 rval = mrsas_service_evt(instance, ddi_get16(
4264 acc_handle, &evt_detail->args.pd.device_id),
4265 1, MRSAS_EVT_UNCONFIG_TGT, NULL);
4266 con_log(CL_ANN1, (CE_WARN, "mr_sas: PD_REMOVED:"
4267 "rval = %d tgt id = %d ", rval,
4268 ddi_get16(acc_handle,
4269 &evt_detail->args.pd.device_id)));
4270 }
4271 break;
4272 } /* End of MR_EVT_PD_REMOVED_EXT */
4273
4274 case MR_EVT_PD_INSERTED_EXT: {
4275 if (instance->tbolt || instance->skinny) {
4276 rval = mrsas_service_evt(instance,
4277 ddi_get16(acc_handle,
4278 &evt_detail->args.pd.device_id),
4279 1, MRSAS_EVT_CONFIG_TGT, NULL);
4280 con_log(CL_ANN1, (CE_WARN, "mr_sas: PD_INSERTEDi_EXT:"
4281 "rval = %d tgt id = %d ", rval,
4282 ddi_get16(acc_handle,
4283 &evt_detail->args.pd.device_id)));
4284 }
4285 break;
4286 } /* End of MR_EVT_PD_INSERTED_EXT */
4287
4288 case MR_EVT_PD_STATE_CHANGE: {
4289 if (instance->tbolt || instance->skinny) {
4290 tgt = ddi_get16(acc_handle,
4291 &evt_detail->args.pd.device_id);
4292 if ((evt_detail->args.pd_state.prevState ==
4293 PD_SYSTEM) &&
4294 (evt_detail->args.pd_state.newState != PD_SYSTEM)) {
4295 mutex_enter(&instance->config_dev_mtx);
4296 instance->mr_tbolt_pd_list[tgt].flag =
4297 (uint8_t)~MRDRV_TGT_VALID;
4298 mutex_exit(&instance->config_dev_mtx);
4299 rval = mrsas_service_evt(instance,
4300 ddi_get16(acc_handle,
4301 &evt_detail->args.pd.device_id),
4302 1, MRSAS_EVT_UNCONFIG_TGT, NULL);
4303 con_log(CL_ANN1, (CE_WARN, "mr_sas: PD_REMOVED:"
4304 "rval = %d tgt id = %d ", rval,
4305 ddi_get16(acc_handle,
4306 &evt_detail->args.pd.device_id)));
4307 break;
4308 }
4309 if ((evt_detail->args.pd_state.prevState
4310 == UNCONFIGURED_GOOD) &&
4311 (evt_detail->args.pd_state.newState == PD_SYSTEM)) {
4312 rval = mrsas_service_evt(instance,
4313 ddi_get16(acc_handle,
4314 &evt_detail->args.pd.device_id),
4315 1, MRSAS_EVT_CONFIG_TGT, NULL);
4316 con_log(CL_ANN1, (CE_WARN,
4317 "mr_sas: PD_INSERTED: rval = %d "
4318 " tgt id = %d ", rval,
4319 ddi_get16(acc_handle,
4320 &evt_detail->args.pd.device_id)));
4321 break;
4322 }
4323 }
4324 break;
4325 }
4326
4327 } /* End of Main Switch */
4328
4329 /* get copy of seq_num and class/locale for re-registration */
4330 seq_num = ddi_get32(acc_handle, &evt_detail->seq_num);
4331 seq_num++;
4332 (void) memset(instance->mfi_evt_detail_obj.buffer, 0,
4333 sizeof (struct mrsas_evt_detail));
4334
4335 ddi_put8(acc_handle, &cmd->frame->dcmd.cmd_status, 0x0);
4336 ddi_put32(acc_handle, &cmd->frame->dcmd.mbox.w[0], seq_num);
4337
4338 instance->aen_seq_num = seq_num;
4339
4340 cmd->frame_count = 1;
4341
4342 cmd->retry_count_for_ocr = 0;
4343 cmd->drv_pkt_time = 0;
4344
4345 /* Issue the aen registration frame */
4346 instance->func_ptr->issue_cmd(cmd, instance);
4347 }
4348
4349 /*
4350 * complete_cmd_in_sync_mode - Completes an internal command
4351 * @instance: Adapter soft state
4352 * @cmd: Command to be completed
4353 *
4354 * The issue_cmd_in_sync_mode() function waits for a command to complete
4355 * after it issues a command. This function wakes up that waiting routine by
4356 * calling wake_up() on the wait queue.
4357 */
4358 static void
4359 complete_cmd_in_sync_mode(struct mrsas_instance *instance,
4360 struct mrsas_cmd *cmd)
4361 {
4362 cmd->cmd_status = ddi_get8(cmd->frame_dma_obj.acc_handle,
4363 &cmd->frame->io.cmd_status);
4364
4365 cmd->sync_cmd = MRSAS_FALSE;
4366
4367 con_log(CL_ANN1, (CE_NOTE, "complete_cmd_in_sync_mode called %p \n",
4368 (void *)cmd));
4369
4370 mutex_enter(&instance->int_cmd_mtx);
4371 if (cmd->cmd_status == ENODATA) {
4372 cmd->cmd_status = 0;
4373 }
4374 cv_broadcast(&instance->int_cmd_cv);
4375 mutex_exit(&instance->int_cmd_mtx);
4376
4377 }
4378
4379 /*
4380 * Call this function inside mrsas_softintr.
4381 * mrsas_initiate_ocr_if_fw_is_faulty - Initiates OCR if FW status is faulty
4382 * @instance: Adapter soft state
4383 */
4384
4385 static uint32_t
4386 mrsas_initiate_ocr_if_fw_is_faulty(struct mrsas_instance *instance)
4387 {
4388 uint32_t cur_abs_reg_val;
4389 uint32_t fw_state;
4390
4391 cur_abs_reg_val = instance->func_ptr->read_fw_status_reg(instance);
4392 fw_state = cur_abs_reg_val & MFI_STATE_MASK;
4393 if (fw_state == MFI_STATE_FAULT) {
4394 if (instance->disable_online_ctrl_reset == 1) {
4395 dev_err(instance->dip, CE_WARN,
4396 "mrsas_initiate_ocr_if_fw_is_faulty: "
4397 "FW in Fault state, detected in ISR: "
4398 "FW doesn't support ocr ");
4399
4400 return (ADAPTER_RESET_NOT_REQUIRED);
4401 } else {
4402 con_log(CL_ANN, (CE_NOTE,
4403 "mrsas_initiate_ocr_if_fw_is_faulty: FW in Fault "
4404 "state, detected in ISR: FW supports ocr "));
4405
4406 return (ADAPTER_RESET_REQUIRED);
4407 }
4408 }
4409
4410 return (ADAPTER_RESET_NOT_REQUIRED);
4411 }
4412
4413 /*
4414 * mrsas_softintr - The Software ISR
4415 * @param arg : HBA soft state
4416 *
4417 * called from high-level interrupt if hi-level interrupt are not there,
4418 * otherwise triggered as a soft interrupt
4419 */
4420 static uint_t
4421 mrsas_softintr(struct mrsas_instance *instance)
4422 {
4423 struct scsi_pkt *pkt;
4424 struct scsa_cmd *acmd;
4425 struct mrsas_cmd *cmd;
4426 struct mlist_head *pos, *next;
4427 mlist_t process_list;
4428 struct mrsas_header *hdr;
4429 struct scsi_arq_status *arqstat;
4430
4431 con_log(CL_ANN1, (CE_NOTE, "mrsas_softintr() called."));
4432
4433 ASSERT(instance);
4434
4435 mutex_enter(&instance->completed_pool_mtx);
4436
4437 if (mlist_empty(&instance->completed_pool_list)) {
4438 mutex_exit(&instance->completed_pool_mtx);
4439 return (DDI_INTR_CLAIMED);
4440 }
4441
4442 instance->softint_running = 1;
4443
4444 INIT_LIST_HEAD(&process_list);
4445 mlist_splice(&instance->completed_pool_list, &process_list);
4446 INIT_LIST_HEAD(&instance->completed_pool_list);
4447
4448 mutex_exit(&instance->completed_pool_mtx);
4449
4450 /* perform all callbacks first, before releasing the SCBs */
4451 mlist_for_each_safe(pos, next, &process_list) {
4452 cmd = mlist_entry(pos, struct mrsas_cmd, list);
4453
4454 /* syncronize the Cmd frame for the controller */
4455 (void) ddi_dma_sync(cmd->frame_dma_obj.dma_handle,
4456 0, 0, DDI_DMA_SYNC_FORCPU);
4457
4458 if (mrsas_check_dma_handle(cmd->frame_dma_obj.dma_handle) !=
4459 DDI_SUCCESS) {
4460 mrsas_fm_ereport(instance, DDI_FM_DEVICE_NO_RESPONSE);
4461 ddi_fm_service_impact(instance->dip, DDI_SERVICE_LOST);
4462 con_log(CL_ANN1, (CE_WARN,
4463 "mrsas_softintr: "
4464 "FMA check reports DMA handle failure"));
4465 return (DDI_INTR_CLAIMED);
4466 }
4467
4468 hdr = &cmd->frame->hdr;
4469
4470 /* remove the internal command from the process list */
4471 mlist_del_init(&cmd->list);
4472
4473 switch (ddi_get8(cmd->frame_dma_obj.acc_handle, &hdr->cmd)) {
4474 case MFI_CMD_OP_PD_SCSI:
4475 case MFI_CMD_OP_LD_SCSI:
4476 case MFI_CMD_OP_LD_READ:
4477 case MFI_CMD_OP_LD_WRITE:
4478 /*
4479 * MFI_CMD_OP_PD_SCSI and MFI_CMD_OP_LD_SCSI
4480 * could have been issued either through an
4481 * IO path or an IOCTL path. If it was via IOCTL,
4482 * we will send it to internal completion.
4483 */
4484 if (cmd->sync_cmd == MRSAS_TRUE) {
4485 complete_cmd_in_sync_mode(instance, cmd);
4486 break;
4487 }
4488
4489 /* regular commands */
4490 acmd = cmd->cmd;
4491 pkt = CMD2PKT(acmd);
4492
4493 if (acmd->cmd_flags & CFLAG_DMAVALID) {
4494 if (acmd->cmd_flags & CFLAG_CONSISTENT) {
4495 (void) ddi_dma_sync(acmd->cmd_dmahandle,
4496 acmd->cmd_dma_offset,
4497 acmd->cmd_dma_len,
4498 DDI_DMA_SYNC_FORCPU);
4499 }
4500 }
4501
4502 pkt->pkt_reason = CMD_CMPLT;
4503 pkt->pkt_statistics = 0;
4504 pkt->pkt_state = STATE_GOT_BUS
4505 | STATE_GOT_TARGET | STATE_SENT_CMD
4506 | STATE_XFERRED_DATA | STATE_GOT_STATUS;
4507
4508 con_log(CL_ANN, (CE_CONT,
4509 "CDB[0] = %x completed for %s: size %lx context %x",
4510 pkt->pkt_cdbp[0], ((acmd->islogical) ? "LD" : "PD"),
4511 acmd->cmd_dmacount, hdr->context));
4512 DTRACE_PROBE3(softintr_cdb, uint8_t, pkt->pkt_cdbp[0],
4513 uint_t, acmd->cmd_cdblen, ulong_t,
4514 acmd->cmd_dmacount);
4515
4516 if (pkt->pkt_cdbp[0] == SCMD_INQUIRY) {
4517 struct scsi_inquiry *inq;
4518
4519 if (acmd->cmd_dmacount != 0) {
4520 bp_mapin(acmd->cmd_buf);
4521 inq = (struct scsi_inquiry *)
4522 acmd->cmd_buf->b_un.b_addr;
4523
4524 if (hdr->cmd_status == MFI_STAT_OK) {
4525 display_scsi_inquiry(
4526 (caddr_t)inq);
4527 }
4528 }
4529 }
4530
4531 DTRACE_PROBE2(softintr_done, uint8_t, hdr->cmd,
4532 uint8_t, hdr->cmd_status);
4533
4534 switch (hdr->cmd_status) {
4535 case MFI_STAT_OK:
4536 pkt->pkt_scbp[0] = STATUS_GOOD;
4537 break;
4538 case MFI_STAT_LD_CC_IN_PROGRESS:
4539 case MFI_STAT_LD_RECON_IN_PROGRESS:
4540 pkt->pkt_scbp[0] = STATUS_GOOD;
4541 break;
4542 case MFI_STAT_LD_INIT_IN_PROGRESS:
4543 con_log(CL_ANN,
4544 (CE_WARN, "Initialization in Progress"));
4545 pkt->pkt_reason = CMD_TRAN_ERR;
4546
4547 break;
4548 case MFI_STAT_SCSI_DONE_WITH_ERROR:
4549 con_log(CL_ANN, (CE_CONT, "scsi_done error"));
4550
4551 pkt->pkt_reason = CMD_CMPLT;
4552 ((struct scsi_status *)
4553 pkt->pkt_scbp)->sts_chk = 1;
4554
4555 if (pkt->pkt_cdbp[0] == SCMD_TEST_UNIT_READY) {
4556 con_log(CL_ANN,
4557 (CE_WARN, "TEST_UNIT_READY fail"));
4558 } else {
4559 pkt->pkt_state |= STATE_ARQ_DONE;
4560 arqstat = (void *)(pkt->pkt_scbp);
4561 arqstat->sts_rqpkt_reason = CMD_CMPLT;
4562 arqstat->sts_rqpkt_resid = 0;
4563 arqstat->sts_rqpkt_state |=
4564 STATE_GOT_BUS | STATE_GOT_TARGET
4565 | STATE_SENT_CMD
4566 | STATE_XFERRED_DATA;
4567 *(uint8_t *)&arqstat->sts_rqpkt_status =
4568 STATUS_GOOD;
4569 ddi_rep_get8(
4570 cmd->frame_dma_obj.acc_handle,
4571 (uint8_t *)
4572 &(arqstat->sts_sensedata),
4573 cmd->sense,
4574 sizeof (struct scsi_extended_sense),
4575 DDI_DEV_AUTOINCR);
4576 }
4577 break;
4578 case MFI_STAT_LD_OFFLINE:
4579 case MFI_STAT_DEVICE_NOT_FOUND:
4580 con_log(CL_ANN, (CE_CONT,
4581 "mrsas_softintr:device not found error"));
4582 pkt->pkt_reason = CMD_DEV_GONE;
4583 pkt->pkt_statistics = STAT_DISCON;
4584 break;
4585 case MFI_STAT_LD_LBA_OUT_OF_RANGE:
4586 pkt->pkt_state |= STATE_ARQ_DONE;
4587 pkt->pkt_reason = CMD_CMPLT;
4588 ((struct scsi_status *)
4589 pkt->pkt_scbp)->sts_chk = 1;
4590
4591 arqstat = (void *)(pkt->pkt_scbp);
4592 arqstat->sts_rqpkt_reason = CMD_CMPLT;
4593 arqstat->sts_rqpkt_resid = 0;
4594 arqstat->sts_rqpkt_state |= STATE_GOT_BUS
4595 | STATE_GOT_TARGET | STATE_SENT_CMD
4596 | STATE_XFERRED_DATA;
4597 *(uint8_t *)&arqstat->sts_rqpkt_status =
4598 STATUS_GOOD;
4599
4600 arqstat->sts_sensedata.es_valid = 1;
4601 arqstat->sts_sensedata.es_key =
4602 KEY_ILLEGAL_REQUEST;
4603 arqstat->sts_sensedata.es_class =
4604 CLASS_EXTENDED_SENSE;
4605
4606 /*
4607 * LOGICAL BLOCK ADDRESS OUT OF RANGE:
4608 * ASC: 0x21h; ASCQ: 0x00h;
4609 */
4610 arqstat->sts_sensedata.es_add_code = 0x21;
4611 arqstat->sts_sensedata.es_qual_code = 0x00;
4612
4613 break;
4614
4615 default:
4616 con_log(CL_ANN, (CE_CONT, "Unknown status!"));
4617 pkt->pkt_reason = CMD_TRAN_ERR;
4618
4619 break;
4620 }
4621
4622 atomic_add_16(&instance->fw_outstanding, (-1));
4623
4624 (void) mrsas_common_check(instance, cmd);
4625
4626 if (acmd->cmd_dmahandle) {
4627 if (mrsas_check_dma_handle(
4628 acmd->cmd_dmahandle) != DDI_SUCCESS) {
4629 ddi_fm_service_impact(instance->dip,
4630 DDI_SERVICE_UNAFFECTED);
4631 pkt->pkt_reason = CMD_TRAN_ERR;
4632 pkt->pkt_statistics = 0;
4633 }
4634 }
4635
4636 mrsas_return_mfi_pkt(instance, cmd);
4637
4638 /* Call the callback routine */
4639 if (((pkt->pkt_flags & FLAG_NOINTR) == 0) &&
4640 pkt->pkt_comp) {
4641 (*pkt->pkt_comp)(pkt);
4642 }
4643
4644 break;
4645
4646 case MFI_CMD_OP_SMP:
4647 case MFI_CMD_OP_STP:
4648 complete_cmd_in_sync_mode(instance, cmd);
4649 break;
4650
4651 case MFI_CMD_OP_DCMD:
4652 /* see if got an event notification */
4653 if (ddi_get32(cmd->frame_dma_obj.acc_handle,
4654 &cmd->frame->dcmd.opcode) ==
4655 MR_DCMD_CTRL_EVENT_WAIT) {
4656 if ((instance->aen_cmd == cmd) &&
4657 (instance->aen_cmd->abort_aen)) {
4658 con_log(CL_ANN, (CE_WARN,
4659 "mrsas_softintr: "
4660 "aborted_aen returned"));
4661 } else {
4662 atomic_add_16(&instance->fw_outstanding,
4663 (-1));
4664 service_mfi_aen(instance, cmd);
4665 }
4666 } else {
4667 complete_cmd_in_sync_mode(instance, cmd);
4668 }
4669
4670 break;
4671
4672 case MFI_CMD_OP_ABORT:
4673 con_log(CL_ANN, (CE_NOTE, "MFI_CMD_OP_ABORT complete"));
4674 /*
4675 * MFI_CMD_OP_ABORT successfully completed
4676 * in the synchronous mode
4677 */
4678 complete_cmd_in_sync_mode(instance, cmd);
4679 break;
4680
4681 default:
4682 mrsas_fm_ereport(instance, DDI_FM_DEVICE_NO_RESPONSE);
4683 ddi_fm_service_impact(instance->dip, DDI_SERVICE_LOST);
4684
4685 if (cmd->pkt != NULL) {
4686 pkt = cmd->pkt;
4687 if (((pkt->pkt_flags & FLAG_NOINTR) == 0) &&
4688 pkt->pkt_comp) {
4689
4690 con_log(CL_ANN1, (CE_CONT, "posting to "
4691 "scsa cmd %p index %x pkt %p"
4692 "time %llx, default ", (void *)cmd,
4693 cmd->index, (void *)pkt,
4694 gethrtime()));
4695
4696 (*pkt->pkt_comp)(pkt);
4697
4698 }
4699 }
4700 con_log(CL_ANN, (CE_WARN, "Cmd type unknown !"));
4701 break;
4702 }
4703 }
4704
4705 instance->softint_running = 0;
4706
4707 return (DDI_INTR_CLAIMED);
4708 }
4709
4710 /*
4711 * mrsas_alloc_dma_obj
4712 *
4713 * Allocate the memory and other resources for an dma object.
4714 */
4715 int
4716 mrsas_alloc_dma_obj(struct mrsas_instance *instance, dma_obj_t *obj,
4717 uchar_t endian_flags)
4718 {
4719 int i;
4720 size_t alen = 0;
4721 uint_t cookie_cnt;
4722 struct ddi_device_acc_attr tmp_endian_attr;
4723
4724 tmp_endian_attr = endian_attr;
4725 tmp_endian_attr.devacc_attr_endian_flags = endian_flags;
4726 tmp_endian_attr.devacc_attr_access = DDI_DEFAULT_ACC;
4727
4728 i = ddi_dma_alloc_handle(instance->dip, &obj->dma_attr,
4729 DDI_DMA_SLEEP, NULL, &obj->dma_handle);
4730 if (i != DDI_SUCCESS) {
4731
4732 switch (i) {
4733 case DDI_DMA_BADATTR :
4734 con_log(CL_ANN, (CE_WARN,
4735 "Failed ddi_dma_alloc_handle- Bad attribute"));
4736 break;
4737 case DDI_DMA_NORESOURCES :
4738 con_log(CL_ANN, (CE_WARN,
4739 "Failed ddi_dma_alloc_handle- No Resources"));
4740 break;
4741 default :
4742 con_log(CL_ANN, (CE_WARN,
4743 "Failed ddi_dma_alloc_handle: "
4744 "unknown status %d", i));
4745 break;
4746 }
4747
4748 return (-1);
4749 }
4750
4751 if ((ddi_dma_mem_alloc(obj->dma_handle, obj->size, &tmp_endian_attr,
4752 DDI_DMA_RDWR | DDI_DMA_STREAMING, DDI_DMA_SLEEP, NULL,
4753 &obj->buffer, &alen, &obj->acc_handle) != DDI_SUCCESS) ||
4754 alen < obj->size) {
4755
4756 ddi_dma_free_handle(&obj->dma_handle);
4757
4758 con_log(CL_ANN, (CE_WARN, "Failed : ddi_dma_mem_alloc"));
4759
4760 return (-1);
4761 }
4762
4763 if (ddi_dma_addr_bind_handle(obj->dma_handle, NULL, obj->buffer,
4764 obj->size, DDI_DMA_RDWR | DDI_DMA_STREAMING, DDI_DMA_SLEEP,
4765 NULL, &obj->dma_cookie[0], &cookie_cnt) != DDI_SUCCESS) {
4766
4767 ddi_dma_mem_free(&obj->acc_handle);
4768 ddi_dma_free_handle(&obj->dma_handle);
4769
4770 con_log(CL_ANN, (CE_WARN, "Failed : ddi_dma_addr_bind_handle"));
4771
4772 return (-1);
4773 }
4774
4775 if (mrsas_check_dma_handle(obj->dma_handle) != DDI_SUCCESS) {
4776 ddi_fm_service_impact(instance->dip, DDI_SERVICE_LOST);
4777 return (-1);
4778 }
4779
4780 if (mrsas_check_acc_handle(obj->acc_handle) != DDI_SUCCESS) {
4781 ddi_fm_service_impact(instance->dip, DDI_SERVICE_LOST);
4782 return (-1);
4783 }
4784
4785 return (cookie_cnt);
4786 }
4787
4788 /*
4789 * mrsas_free_dma_obj(struct mrsas_instance *, dma_obj_t)
4790 *
4791 * De-allocate the memory and other resources for an dma object, which must
4792 * have been alloated by a previous call to mrsas_alloc_dma_obj()
4793 */
4794 int
4795 mrsas_free_dma_obj(struct mrsas_instance *instance, dma_obj_t obj)
4796 {
4797
4798 if ((obj.dma_handle == NULL) || (obj.acc_handle == NULL)) {
4799 return (DDI_SUCCESS);
4800 }
4801
4802 /*
4803 * NOTE: These check-handle functions fail if *_handle == NULL, but
4804 * this function succeeds because of the previous check.
4805 */
4806 if (mrsas_check_dma_handle(obj.dma_handle) != DDI_SUCCESS) {
4807 ddi_fm_service_impact(instance->dip, DDI_SERVICE_UNAFFECTED);
4808 return (DDI_FAILURE);
4809 }
4810
4811 if (mrsas_check_acc_handle(obj.acc_handle) != DDI_SUCCESS) {
4812 ddi_fm_service_impact(instance->dip, DDI_SERVICE_UNAFFECTED);
4813 return (DDI_FAILURE);
4814 }
4815
4816 (void) ddi_dma_unbind_handle(obj.dma_handle);
4817 ddi_dma_mem_free(&obj.acc_handle);
4818 ddi_dma_free_handle(&obj.dma_handle);
4819 obj.acc_handle = NULL;
4820 return (DDI_SUCCESS);
4821 }
4822
4823 /*
4824 * mrsas_dma_alloc(instance_t *, struct scsi_pkt *, struct buf *,
4825 * int, int (*)())
4826 *
4827 * Allocate dma resources for a new scsi command
4828 */
4829 int
4830 mrsas_dma_alloc(struct mrsas_instance *instance, struct scsi_pkt *pkt,
4831 struct buf *bp, int flags, int (*callback)())
4832 {
4833 int dma_flags;
4834 int (*cb)(caddr_t);
4835 int i;
4836
4837 ddi_dma_attr_t tmp_dma_attr = mrsas_generic_dma_attr;
4838 struct scsa_cmd *acmd = PKT2CMD(pkt);
4839
4840 acmd->cmd_buf = bp;
4841
4842 if (bp->b_flags & B_READ) {
4843 acmd->cmd_flags &= ~CFLAG_DMASEND;
4844 dma_flags = DDI_DMA_READ;
4845 } else {
4846 acmd->cmd_flags |= CFLAG_DMASEND;
4847 dma_flags = DDI_DMA_WRITE;
4848 }
4849
4850 if (flags & PKT_CONSISTENT) {
4851 acmd->cmd_flags |= CFLAG_CONSISTENT;
4852 dma_flags |= DDI_DMA_CONSISTENT;
4853 }
4854
4855 if (flags & PKT_DMA_PARTIAL) {
4856 dma_flags |= DDI_DMA_PARTIAL;
4857 }
4858
4859 dma_flags |= DDI_DMA_REDZONE;
4860
4861 cb = (callback == NULL_FUNC) ? DDI_DMA_DONTWAIT : DDI_DMA_SLEEP;
4862
4863 tmp_dma_attr.dma_attr_sgllen = instance->max_num_sge;
4864 tmp_dma_attr.dma_attr_addr_hi = 0xffffffffffffffffull;
4865 if (instance->tbolt) {
4866 /* OCR-RESET FIX */
4867 tmp_dma_attr.dma_attr_count_max =
4868 (U64)mrsas_tbolt_max_cap_maxxfer; /* limit to 256K */
4869 tmp_dma_attr.dma_attr_maxxfer =
4870 (U64)mrsas_tbolt_max_cap_maxxfer; /* limit to 256K */
4871 }
4872
4873 if ((i = ddi_dma_alloc_handle(instance->dip, &tmp_dma_attr,
4874 cb, 0, &acmd->cmd_dmahandle)) != DDI_SUCCESS) {
4875 switch (i) {
4876 case DDI_DMA_BADATTR:
4877 bioerror(bp, EFAULT);
4878 return (DDI_FAILURE);
4879
4880 case DDI_DMA_NORESOURCES:
4881 bioerror(bp, 0);
4882 return (DDI_FAILURE);
4883
4884 default:
4885 con_log(CL_ANN, (CE_PANIC, "ddi_dma_alloc_handle: "
4886 "impossible result (0x%x)", i));
4887 bioerror(bp, EFAULT);
4888 return (DDI_FAILURE);
4889 }
4890 }
4891
4892 i = ddi_dma_buf_bind_handle(acmd->cmd_dmahandle, bp, dma_flags,
4893 cb, 0, &acmd->cmd_dmacookies[0], &acmd->cmd_ncookies);
4894
4895 switch (i) {
4896 case DDI_DMA_PARTIAL_MAP:
4897 if ((dma_flags & DDI_DMA_PARTIAL) == 0) {
4898 con_log(CL_ANN, (CE_PANIC, "ddi_dma_buf_bind_handle: "
4899 "DDI_DMA_PARTIAL_MAP impossible"));
4900 goto no_dma_cookies;
4901 }
4902
4903 if (ddi_dma_numwin(acmd->cmd_dmahandle, &acmd->cmd_nwin) ==
4904 DDI_FAILURE) {
4905 con_log(CL_ANN, (CE_PANIC, "ddi_dma_numwin failed"));
4906 goto no_dma_cookies;
4907 }
4908
4909 if (ddi_dma_getwin(acmd->cmd_dmahandle, acmd->cmd_curwin,
4910 &acmd->cmd_dma_offset, &acmd->cmd_dma_len,
4911 &acmd->cmd_dmacookies[0], &acmd->cmd_ncookies) ==
4912 DDI_FAILURE) {
4913
4914 con_log(CL_ANN, (CE_PANIC, "ddi_dma_getwin failed"));
4915 goto no_dma_cookies;
4916 }
4917
4918 goto get_dma_cookies;
4919 case DDI_DMA_MAPPED:
4920 acmd->cmd_nwin = 1;
4921 acmd->cmd_dma_len = 0;
4922 acmd->cmd_dma_offset = 0;
4923
4924 get_dma_cookies:
4925 i = 0;
4926 acmd->cmd_dmacount = 0;
4927 for (;;) {
4928 acmd->cmd_dmacount +=
4929 acmd->cmd_dmacookies[i++].dmac_size;
4930
4931 if (i == instance->max_num_sge ||
4932 i == acmd->cmd_ncookies)
4933 break;
4934
4935 ddi_dma_nextcookie(acmd->cmd_dmahandle,
4936 &acmd->cmd_dmacookies[i]);
4937 }
4938
4939 acmd->cmd_cookie = i;
4940 acmd->cmd_cookiecnt = i;
4941
4942 acmd->cmd_flags |= CFLAG_DMAVALID;
4943
4944 if (bp->b_bcount >= acmd->cmd_dmacount) {
4945 pkt->pkt_resid = bp->b_bcount - acmd->cmd_dmacount;
4946 } else {
4947 pkt->pkt_resid = 0;
4948 }
4949
4950 return (DDI_SUCCESS);
4951 case DDI_DMA_NORESOURCES:
4952 bioerror(bp, 0);
4953 break;
4954 case DDI_DMA_NOMAPPING:
4955 bioerror(bp, EFAULT);
4956 break;
4957 case DDI_DMA_TOOBIG:
4958 bioerror(bp, EINVAL);
4959 break;
4960 case DDI_DMA_INUSE:
4961 con_log(CL_ANN, (CE_PANIC, "ddi_dma_buf_bind_handle:"
4962 " DDI_DMA_INUSE impossible"));
4963 break;
4964 default:
4965 con_log(CL_ANN, (CE_PANIC, "ddi_dma_buf_bind_handle: "
4966 "impossible result (0x%x)", i));
4967 break;
4968 }
4969
4970 no_dma_cookies:
4971 ddi_dma_free_handle(&acmd->cmd_dmahandle);
4972 acmd->cmd_dmahandle = NULL;
4973 acmd->cmd_flags &= ~CFLAG_DMAVALID;
4974 return (DDI_FAILURE);
4975 }
4976
4977 /*
4978 * mrsas_dma_move(struct mrsas_instance *, struct scsi_pkt *, struct buf *)
4979 *
4980 * move dma resources to next dma window
4981 *
4982 */
4983 int
4984 mrsas_dma_move(struct mrsas_instance *instance, struct scsi_pkt *pkt,
4985 struct buf *bp)
4986 {
4987 int i = 0;
4988
4989 struct scsa_cmd *acmd = PKT2CMD(pkt);
4990
4991 /*
4992 * If there are no more cookies remaining in this window,
4993 * must move to the next window first.
4994 */
4995 if (acmd->cmd_cookie == acmd->cmd_ncookies) {
4996 if (acmd->cmd_curwin == acmd->cmd_nwin && acmd->cmd_nwin == 1) {
4997 return (DDI_SUCCESS);
4998 }
4999
5000 /* at last window, cannot move */
5001 if (++acmd->cmd_curwin >= acmd->cmd_nwin) {
5002 return (DDI_FAILURE);
5003 }
5004
5005 if (ddi_dma_getwin(acmd->cmd_dmahandle, acmd->cmd_curwin,
5006 &acmd->cmd_dma_offset, &acmd->cmd_dma_len,
5007 &acmd->cmd_dmacookies[0], &acmd->cmd_ncookies) ==
5008 DDI_FAILURE) {
5009 return (DDI_FAILURE);
5010 }
5011
5012 acmd->cmd_cookie = 0;
5013 } else {
5014 /* still more cookies in this window - get the next one */
5015 ddi_dma_nextcookie(acmd->cmd_dmahandle,
5016 &acmd->cmd_dmacookies[0]);
5017 }
5018
5019 /* get remaining cookies in this window, up to our maximum */
5020 for (;;) {
5021 acmd->cmd_dmacount += acmd->cmd_dmacookies[i++].dmac_size;
5022 acmd->cmd_cookie++;
5023
5024 if (i == instance->max_num_sge ||
5025 acmd->cmd_cookie == acmd->cmd_ncookies) {
5026 break;
5027 }
5028
5029 ddi_dma_nextcookie(acmd->cmd_dmahandle,
5030 &acmd->cmd_dmacookies[i]);
5031 }
5032
5033 acmd->cmd_cookiecnt = i;
5034
5035 if (bp->b_bcount >= acmd->cmd_dmacount) {
5036 pkt->pkt_resid = bp->b_bcount - acmd->cmd_dmacount;
5037 } else {
5038 pkt->pkt_resid = 0;
5039 }
5040
5041 return (DDI_SUCCESS);
5042 }
5043
5044 /*
5045 * build_cmd
5046 */
5047 static struct mrsas_cmd *
5048 build_cmd(struct mrsas_instance *instance, struct scsi_address *ap,
5049 struct scsi_pkt *pkt, uchar_t *cmd_done)
5050 {
5051 uint16_t flags = 0;
5052 uint32_t i;
5053 uint32_t sge_bytes;
5054 uint32_t tmp_data_xfer_len;
5055 ddi_acc_handle_t acc_handle;
5056 struct mrsas_cmd *cmd;
5057 struct mrsas_sge64 *mfi_sgl;
5058 struct mrsas_sge_ieee *mfi_sgl_ieee;
5059 struct scsa_cmd *acmd = PKT2CMD(pkt);
5060 struct mrsas_pthru_frame *pthru;
5061 struct mrsas_io_frame *ldio;
5062
5063 /* find out if this is logical or physical drive command. */
5064 acmd->islogical = MRDRV_IS_LOGICAL(ap);
5065 acmd->device_id = MAP_DEVICE_ID(instance, ap);
5066 *cmd_done = 0;
5067
5068 /* get the command packet */
5069 if (!(cmd = mrsas_get_mfi_pkt(instance))) {
5070 DTRACE_PROBE2(build_cmd_mfi_err, uint16_t,
5071 instance->fw_outstanding, uint16_t, instance->max_fw_cmds);
5072 return (NULL);
5073 }
5074
5075 acc_handle = cmd->frame_dma_obj.acc_handle;
5076
5077 /* Clear the frame buffer and assign back the context id */
5078 (void) memset((char *)&cmd->frame[0], 0, sizeof (union mrsas_frame));
5079 ddi_put32(acc_handle, &cmd->frame->hdr.context, cmd->index);
5080
5081 cmd->pkt = pkt;
5082 cmd->cmd = acmd;
5083 DTRACE_PROBE3(build_cmds, uint8_t, pkt->pkt_cdbp[0],
5084 ulong_t, acmd->cmd_dmacount, ulong_t, acmd->cmd_dma_len);
5085
5086 /* lets get the command directions */
5087 if (acmd->cmd_flags & CFLAG_DMASEND) {
5088 flags = MFI_FRAME_DIR_WRITE;
5089
5090 if (acmd->cmd_flags & CFLAG_CONSISTENT) {
5091 (void) ddi_dma_sync(acmd->cmd_dmahandle,
5092 acmd->cmd_dma_offset, acmd->cmd_dma_len,
5093 DDI_DMA_SYNC_FORDEV);
5094 }
5095 } else if (acmd->cmd_flags & ~CFLAG_DMASEND) {
5096 flags = MFI_FRAME_DIR_READ;
5097
5098 if (acmd->cmd_flags & CFLAG_CONSISTENT) {
5099 (void) ddi_dma_sync(acmd->cmd_dmahandle,
5100 acmd->cmd_dma_offset, acmd->cmd_dma_len,
5101 DDI_DMA_SYNC_FORCPU);
5102 }
5103 } else {
5104 flags = MFI_FRAME_DIR_NONE;
5105 }
5106
5107 if (instance->flag_ieee) {
5108 flags |= MFI_FRAME_IEEE;
5109 }
5110 flags |= MFI_FRAME_SGL64;
5111
5112 switch (pkt->pkt_cdbp[0]) {
5113
5114 /*
5115 * case SCMD_SYNCHRONIZE_CACHE:
5116 * flush_cache(instance);
5117 * mrsas_return_mfi_pkt(instance, cmd);
5118 * *cmd_done = 1;
5119 *
5120 * return (NULL);
5121 */
5122
5123 case SCMD_READ:
5124 case SCMD_WRITE:
5125 case SCMD_READ_G1:
5126 case SCMD_WRITE_G1:
5127 case SCMD_READ_G4:
5128 case SCMD_WRITE_G4:
5129 case SCMD_READ_G5:
5130 case SCMD_WRITE_G5:
5131 if (acmd->islogical) {
5132 ldio = (struct mrsas_io_frame *)cmd->frame;
5133
5134 /*
5135 * preare the Logical IO frame:
5136 * 2nd bit is zero for all read cmds
5137 */
5138 ddi_put8(acc_handle, &ldio->cmd,
5139 (pkt->pkt_cdbp[0] & 0x02) ? MFI_CMD_OP_LD_WRITE
5140 : MFI_CMD_OP_LD_READ);
5141 ddi_put8(acc_handle, &ldio->cmd_status, 0x0);
5142 ddi_put8(acc_handle, &ldio->scsi_status, 0x0);
5143 ddi_put8(acc_handle, &ldio->target_id, acmd->device_id);
5144 ddi_put16(acc_handle, &ldio->timeout, 0);
5145 ddi_put8(acc_handle, &ldio->reserved_0, 0);
5146 ddi_put16(acc_handle, &ldio->pad_0, 0);
5147 ddi_put16(acc_handle, &ldio->flags, flags);
5148
5149 /* Initialize sense Information */
5150 bzero(cmd->sense, SENSE_LENGTH);
5151 ddi_put8(acc_handle, &ldio->sense_len, SENSE_LENGTH);
5152 ddi_put32(acc_handle, &ldio->sense_buf_phys_addr_hi, 0);
5153 ddi_put32(acc_handle, &ldio->sense_buf_phys_addr_lo,
5154 cmd->sense_phys_addr);
5155 ddi_put32(acc_handle, &ldio->start_lba_hi, 0);
5156 ddi_put8(acc_handle, &ldio->access_byte,
5157 (acmd->cmd_cdblen != 6) ? pkt->pkt_cdbp[1] : 0);
5158 ddi_put8(acc_handle, &ldio->sge_count,
5159 acmd->cmd_cookiecnt);
5160 if (instance->flag_ieee) {
5161 mfi_sgl_ieee =
5162 (struct mrsas_sge_ieee *)&ldio->sgl;
5163 } else {
5164 mfi_sgl = (struct mrsas_sge64 *)&ldio->sgl;
5165 }
5166
5167 (void) ddi_get32(acc_handle, &ldio->context);
5168
5169 if (acmd->cmd_cdblen == CDB_GROUP0) {
5170 /* 6-byte cdb */
5171 ddi_put32(acc_handle, &ldio->lba_count, (
5172 (uint16_t)(pkt->pkt_cdbp[4])));
5173
5174 ddi_put32(acc_handle, &ldio->start_lba_lo, (
5175 ((uint32_t)(pkt->pkt_cdbp[3])) |
5176 ((uint32_t)(pkt->pkt_cdbp[2]) << 8) |
5177 ((uint32_t)((pkt->pkt_cdbp[1]) & 0x1F)
5178 << 16)));
5179 } else if (acmd->cmd_cdblen == CDB_GROUP1) {
5180 /* 10-byte cdb */
5181 ddi_put32(acc_handle, &ldio->lba_count, (
5182 ((uint16_t)(pkt->pkt_cdbp[8])) |
5183 ((uint16_t)(pkt->pkt_cdbp[7]) << 8)));
5184
5185 ddi_put32(acc_handle, &ldio->start_lba_lo, (
5186 ((uint32_t)(pkt->pkt_cdbp[5])) |
5187 ((uint32_t)(pkt->pkt_cdbp[4]) << 8) |
5188 ((uint32_t)(pkt->pkt_cdbp[3]) << 16) |
5189 ((uint32_t)(pkt->pkt_cdbp[2]) << 24)));
5190 } else if (acmd->cmd_cdblen == CDB_GROUP5) {
5191 /* 12-byte cdb */
5192 ddi_put32(acc_handle, &ldio->lba_count, (
5193 ((uint32_t)(pkt->pkt_cdbp[9])) |
5194 ((uint32_t)(pkt->pkt_cdbp[8]) << 8) |
5195 ((uint32_t)(pkt->pkt_cdbp[7]) << 16) |
5196 ((uint32_t)(pkt->pkt_cdbp[6]) << 24)));
5197
5198 ddi_put32(acc_handle, &ldio->start_lba_lo, (
5199 ((uint32_t)(pkt->pkt_cdbp[5])) |
5200 ((uint32_t)(pkt->pkt_cdbp[4]) << 8) |
5201 ((uint32_t)(pkt->pkt_cdbp[3]) << 16) |
5202 ((uint32_t)(pkt->pkt_cdbp[2]) << 24)));
5203 } else if (acmd->cmd_cdblen == CDB_GROUP4) {
5204 /* 16-byte cdb */
5205 ddi_put32(acc_handle, &ldio->lba_count, (
5206 ((uint32_t)(pkt->pkt_cdbp[13])) |
5207 ((uint32_t)(pkt->pkt_cdbp[12]) << 8) |
5208 ((uint32_t)(pkt->pkt_cdbp[11]) << 16) |
5209 ((uint32_t)(pkt->pkt_cdbp[10]) << 24)));
5210
5211 ddi_put32(acc_handle, &ldio->start_lba_lo, (
5212 ((uint32_t)(pkt->pkt_cdbp[9])) |
5213 ((uint32_t)(pkt->pkt_cdbp[8]) << 8) |
5214 ((uint32_t)(pkt->pkt_cdbp[7]) << 16) |
5215 ((uint32_t)(pkt->pkt_cdbp[6]) << 24)));
5216
5217 ddi_put32(acc_handle, &ldio->start_lba_hi, (
5218 ((uint32_t)(pkt->pkt_cdbp[5])) |
5219 ((uint32_t)(pkt->pkt_cdbp[4]) << 8) |
5220 ((uint32_t)(pkt->pkt_cdbp[3]) << 16) |
5221 ((uint32_t)(pkt->pkt_cdbp[2]) << 24)));
5222 }
5223
5224 break;
5225 }
5226 /* For all non-rd/wr and physical disk cmds */
5227 /* FALLTHROUGH */
5228 default:
5229
5230 switch (pkt->pkt_cdbp[0]) {
5231 case SCMD_MODE_SENSE:
5232 case SCMD_MODE_SENSE_G1: {
5233 union scsi_cdb *cdbp;
5234 uint16_t page_code;
5235
5236 cdbp = (void *)pkt->pkt_cdbp;
5237 page_code = (uint16_t)cdbp->cdb_un.sg.scsi[0];
5238 switch (page_code) {
5239 case 0x3:
5240 case 0x4:
5241 (void) mrsas_mode_sense_build(pkt);
5242 mrsas_return_mfi_pkt(instance, cmd);
5243 *cmd_done = 1;
5244 return (NULL);
5245 }
5246 break;
5247 }
5248 default:
5249 break;
5250 }
5251
5252 pthru = (struct mrsas_pthru_frame *)cmd->frame;
5253
5254 /* prepare the DCDB frame */
5255 ddi_put8(acc_handle, &pthru->cmd, (acmd->islogical) ?
5256 MFI_CMD_OP_LD_SCSI : MFI_CMD_OP_PD_SCSI);
5257 ddi_put8(acc_handle, &pthru->cmd_status, 0x0);
5258 ddi_put8(acc_handle, &pthru->scsi_status, 0x0);
5259 ddi_put8(acc_handle, &pthru->target_id, acmd->device_id);
5260 ddi_put8(acc_handle, &pthru->lun, 0);
5261 ddi_put8(acc_handle, &pthru->cdb_len, acmd->cmd_cdblen);
5262 ddi_put16(acc_handle, &pthru->timeout, 0);
5263 ddi_put16(acc_handle, &pthru->flags, flags);
5264 tmp_data_xfer_len = 0;
5265 for (i = 0; i < acmd->cmd_cookiecnt; i++) {
5266 tmp_data_xfer_len += acmd->cmd_dmacookies[i].dmac_size;
5267 }
5268 ddi_put32(acc_handle, &pthru->data_xfer_len,
5269 tmp_data_xfer_len);
5270 ddi_put8(acc_handle, &pthru->sge_count, acmd->cmd_cookiecnt);
5271 if (instance->flag_ieee) {
5272 mfi_sgl_ieee = (struct mrsas_sge_ieee *)&pthru->sgl;
5273 } else {
5274 mfi_sgl = (struct mrsas_sge64 *)&pthru->sgl;
5275 }
5276
5277 bzero(cmd->sense, SENSE_LENGTH);
5278 ddi_put8(acc_handle, &pthru->sense_len, SENSE_LENGTH);
5279 ddi_put32(acc_handle, &pthru->sense_buf_phys_addr_hi, 0);
5280 ddi_put32(acc_handle, &pthru->sense_buf_phys_addr_lo,
5281 cmd->sense_phys_addr);
5282
5283 (void) ddi_get32(acc_handle, &pthru->context);
5284 ddi_rep_put8(acc_handle, (uint8_t *)pkt->pkt_cdbp,
5285 (uint8_t *)pthru->cdb, acmd->cmd_cdblen, DDI_DEV_AUTOINCR);
5286
5287 break;
5288 }
5289
5290 /* prepare the scatter-gather list for the firmware */
5291 if (instance->flag_ieee) {
5292 for (i = 0; i < acmd->cmd_cookiecnt; i++, mfi_sgl_ieee++) {
5293 ddi_put64(acc_handle, &mfi_sgl_ieee->phys_addr,
5294 acmd->cmd_dmacookies[i].dmac_laddress);
5295 ddi_put32(acc_handle, &mfi_sgl_ieee->length,
5296 acmd->cmd_dmacookies[i].dmac_size);
5297 }
5298 sge_bytes = sizeof (struct mrsas_sge_ieee)*acmd->cmd_cookiecnt;
5299 } else {
5300 for (i = 0; i < acmd->cmd_cookiecnt; i++, mfi_sgl++) {
5301 ddi_put64(acc_handle, &mfi_sgl->phys_addr,
5302 acmd->cmd_dmacookies[i].dmac_laddress);
5303 ddi_put32(acc_handle, &mfi_sgl->length,
5304 acmd->cmd_dmacookies[i].dmac_size);
5305 }
5306 sge_bytes = sizeof (struct mrsas_sge64)*acmd->cmd_cookiecnt;
5307 }
5308
5309 cmd->frame_count = (sge_bytes / MRMFI_FRAME_SIZE) +
5310 ((sge_bytes % MRMFI_FRAME_SIZE) ? 1 : 0) + 1;
5311
5312 if (cmd->frame_count >= 8) {
5313 cmd->frame_count = 8;
5314 }
5315
5316 return (cmd);
5317 }
5318
5319 /*
5320 * wait_for_outstanding - Wait for all outstanding cmds
5321 * @instance: Adapter soft state
5322 *
5323 * This function waits for upto MRDRV_RESET_WAIT_TIME seconds for FW to
5324 * complete all its outstanding commands. Returns error if one or more IOs
5325 * are pending after this time period.
5326 */
5327 static int
5328 wait_for_outstanding(struct mrsas_instance *instance)
5329 {
5330 int i;
5331 uint32_t wait_time = 90;
5332
5333 for (i = 0; i < wait_time; i++) {
5334 if (!instance->fw_outstanding) {
5335 break;
5336 }
5337
5338 drv_usecwait(MILLISEC); /* wait for 1000 usecs */;
5339 }
5340
5341 if (instance->fw_outstanding) {
5342 return (1);
5343 }
5344
5345 return (0);
5346 }
5347
5348 /*
5349 * issue_mfi_pthru
5350 */
5351 static int
5352 issue_mfi_pthru(struct mrsas_instance *instance, struct mrsas_ioctl *ioctl,
5353 struct mrsas_cmd *cmd, int mode)
5354 {
5355 void *ubuf;
5356 uint32_t kphys_addr = 0;
5357 uint32_t xferlen = 0;
5358 uint32_t new_xfer_length = 0;
5359 uint_t model;
5360 ddi_acc_handle_t acc_handle = cmd->frame_dma_obj.acc_handle;
5361 dma_obj_t pthru_dma_obj;
5362 struct mrsas_pthru_frame *kpthru;
5363 struct mrsas_pthru_frame *pthru;
5364 int i;
5365 pthru = &cmd->frame->pthru;
5366 kpthru = (struct mrsas_pthru_frame *)&ioctl->frame[0];
5367
5368 if (instance->adapterresetinprogress) {
5369 con_log(CL_ANN1, (CE_WARN, "issue_mfi_pthru: Reset flag set, "
5370 "returning mfi_pkt and setting TRAN_BUSY\n"));
5371 return (DDI_FAILURE);
5372 }
5373 model = ddi_model_convert_from(mode & FMODELS);
5374 if (model == DDI_MODEL_ILP32) {
5375 con_log(CL_ANN1, (CE_CONT, "issue_mfi_pthru: DDI_MODEL_LP32"));
5376
5377 xferlen = kpthru->sgl.sge32[0].length;
5378
5379 ubuf = (void *)(ulong_t)kpthru->sgl.sge32[0].phys_addr;
5380 } else {
5381 #ifdef _ILP32
5382 con_log(CL_ANN1, (CE_CONT, "issue_mfi_pthru: DDI_MODEL_LP32"));
5383 xferlen = kpthru->sgl.sge32[0].length;
5384 ubuf = (void *)(ulong_t)kpthru->sgl.sge32[0].phys_addr;
5385 #else
5386 con_log(CL_ANN1, (CE_CONT, "issue_mfi_pthru: DDI_MODEL_LP64"));
5387 xferlen = kpthru->sgl.sge64[0].length;
5388 ubuf = (void *)(ulong_t)kpthru->sgl.sge64[0].phys_addr;
5389 #endif
5390 }
5391
5392 if (xferlen) {
5393 /* means IOCTL requires DMA */
5394 /* allocate the data transfer buffer */
5395 /* pthru_dma_obj.size = xferlen; */
5396 MRSAS_GET_BOUNDARY_ALIGNED_LEN(xferlen, new_xfer_length,
5397 PAGESIZE);
5398 pthru_dma_obj.size = new_xfer_length;
5399 pthru_dma_obj.dma_attr = mrsas_generic_dma_attr;
5400 pthru_dma_obj.dma_attr.dma_attr_addr_hi = 0xFFFFFFFFU;
5401 pthru_dma_obj.dma_attr.dma_attr_count_max = 0xFFFFFFFFU;
5402 pthru_dma_obj.dma_attr.dma_attr_sgllen = 1;
5403 pthru_dma_obj.dma_attr.dma_attr_align = 1;
5404
5405 /* allocate kernel buffer for DMA */
5406 if (mrsas_alloc_dma_obj(instance, &pthru_dma_obj,
5407 (uchar_t)DDI_STRUCTURE_LE_ACC) != 1) {
5408 con_log(CL_ANN, (CE_WARN, "issue_mfi_pthru: "
5409 "could not allocate data transfer buffer."));
5410 return (DDI_FAILURE);
5411 }
5412 (void) memset(pthru_dma_obj.buffer, 0, xferlen);
5413
5414 /* If IOCTL requires DMA WRITE, do ddi_copyin IOCTL data copy */
5415 if (kpthru->flags & MFI_FRAME_DIR_WRITE) {
5416 for (i = 0; i < xferlen; i++) {
5417 if (ddi_copyin((uint8_t *)ubuf+i,
5418 (uint8_t *)pthru_dma_obj.buffer+i,
5419 1, mode)) {
5420 con_log(CL_ANN, (CE_WARN,
5421 "issue_mfi_pthru : "
5422 "copy from user space failed"));
5423 return (DDI_FAILURE);
5424 }
5425 }
5426 }
5427
5428 kphys_addr = pthru_dma_obj.dma_cookie[0].dmac_address;
5429 }
5430
5431 ddi_put8(acc_handle, &pthru->cmd, kpthru->cmd);
5432 ddi_put8(acc_handle, &pthru->sense_len, SENSE_LENGTH);
5433 ddi_put8(acc_handle, &pthru->cmd_status, 0);
5434 ddi_put8(acc_handle, &pthru->scsi_status, 0);
5435 ddi_put8(acc_handle, &pthru->target_id, kpthru->target_id);
5436 ddi_put8(acc_handle, &pthru->lun, kpthru->lun);
5437 ddi_put8(acc_handle, &pthru->cdb_len, kpthru->cdb_len);
5438 ddi_put8(acc_handle, &pthru->sge_count, kpthru->sge_count);
5439 ddi_put16(acc_handle, &pthru->timeout, kpthru->timeout);
5440 ddi_put32(acc_handle, &pthru->data_xfer_len, kpthru->data_xfer_len);
5441
5442 ddi_put32(acc_handle, &pthru->sense_buf_phys_addr_hi, 0);
5443 pthru->sense_buf_phys_addr_lo = cmd->sense_phys_addr;
5444 /* ddi_put32(acc_handle, &pthru->sense_buf_phys_addr_lo, 0); */
5445
5446 ddi_rep_put8(acc_handle, (uint8_t *)kpthru->cdb, (uint8_t *)pthru->cdb,
5447 pthru->cdb_len, DDI_DEV_AUTOINCR);
5448
5449 ddi_put16(acc_handle, &pthru->flags, kpthru->flags & ~MFI_FRAME_SGL64);
5450 ddi_put32(acc_handle, &pthru->sgl.sge32[0].length, xferlen);
5451 ddi_put32(acc_handle, &pthru->sgl.sge32[0].phys_addr, kphys_addr);
5452
5453 cmd->sync_cmd = MRSAS_TRUE;
5454 cmd->frame_count = 1;
5455
5456 if (instance->tbolt) {
5457 mr_sas_tbolt_build_mfi_cmd(instance, cmd);
5458 }
5459
5460 if (instance->func_ptr->issue_cmd_in_sync_mode(instance, cmd)) {
5461 con_log(CL_ANN, (CE_WARN,
5462 "issue_mfi_pthru: fw_ioctl failed"));
5463 } else {
5464 if (xferlen && kpthru->flags & MFI_FRAME_DIR_READ) {
5465 for (i = 0; i < xferlen; i++) {
5466 if (ddi_copyout(
5467 (uint8_t *)pthru_dma_obj.buffer+i,
5468 (uint8_t *)ubuf+i, 1, mode)) {
5469 con_log(CL_ANN, (CE_WARN,
5470 "issue_mfi_pthru : "
5471 "copy to user space failed"));
5472 return (DDI_FAILURE);
5473 }
5474 }
5475 }
5476 }
5477
5478 kpthru->cmd_status = ddi_get8(acc_handle, &pthru->cmd_status);
5479 kpthru->scsi_status = ddi_get8(acc_handle, &pthru->scsi_status);
5480
5481 con_log(CL_ANN, (CE_CONT, "issue_mfi_pthru: cmd_status %x, "
5482 "scsi_status %x", kpthru->cmd_status, kpthru->scsi_status));
5483 DTRACE_PROBE3(issue_pthru, uint8_t, kpthru->cmd, uint8_t,
5484 kpthru->cmd_status, uint8_t, kpthru->scsi_status);
5485
5486 if (kpthru->sense_len) {
5487 uint_t sense_len = SENSE_LENGTH;
5488 void *sense_ubuf =
5489 (void *)(ulong_t)kpthru->sense_buf_phys_addr_lo;
5490 if (kpthru->sense_len <= SENSE_LENGTH) {
5491 sense_len = kpthru->sense_len;
5492 }
5493
5494 for (i = 0; i < sense_len; i++) {
5495 if (ddi_copyout(
5496 (uint8_t *)cmd->sense+i,
5497 (uint8_t *)sense_ubuf+i, 1, mode)) {
5498 con_log(CL_ANN, (CE_WARN,
5499 "issue_mfi_pthru : "
5500 "copy to user space failed"));
5501 }
5502 con_log(CL_DLEVEL1, (CE_WARN,
5503 "Copying Sense info sense_buff[%d] = 0x%X",
5504 i, *((uint8_t *)cmd->sense + i)));
5505 }
5506 }
5507 (void) ddi_dma_sync(cmd->frame_dma_obj.dma_handle, 0, 0,
5508 DDI_DMA_SYNC_FORDEV);
5509
5510 if (xferlen) {
5511 /* free kernel buffer */
5512 if (mrsas_free_dma_obj(instance, pthru_dma_obj) != DDI_SUCCESS)
5513 return (DDI_FAILURE);
5514 }
5515
5516 return (DDI_SUCCESS);
5517 }
5518
5519 /*
5520 * issue_mfi_dcmd
5521 */
5522 static int
5523 issue_mfi_dcmd(struct mrsas_instance *instance, struct mrsas_ioctl *ioctl,
5524 struct mrsas_cmd *cmd, int mode)
5525 {
5526 void *ubuf;
5527 uint32_t kphys_addr = 0;
5528 uint32_t xferlen = 0;
5529 uint32_t new_xfer_length = 0;
5530 uint32_t model;
5531 dma_obj_t dcmd_dma_obj;
5532 struct mrsas_dcmd_frame *kdcmd;
5533 struct mrsas_dcmd_frame *dcmd;
5534 ddi_acc_handle_t acc_handle = cmd->frame_dma_obj.acc_handle;
5535 int i;
5536 dcmd = &cmd->frame->dcmd;
5537 kdcmd = (struct mrsas_dcmd_frame *)&ioctl->frame[0];
5538
5539 if (instance->adapterresetinprogress) {
5540 con_log(CL_ANN1, (CE_NOTE, "Reset flag set, "
5541 "returning mfi_pkt and setting TRAN_BUSY"));
5542 return (DDI_FAILURE);
5543 }
5544 model = ddi_model_convert_from(mode & FMODELS);
5545 if (model == DDI_MODEL_ILP32) {
5546 con_log(CL_ANN1, (CE_CONT, "issue_mfi_dcmd: DDI_MODEL_ILP32"));
5547
5548 xferlen = kdcmd->sgl.sge32[0].length;
5549
5550 ubuf = (void *)(ulong_t)kdcmd->sgl.sge32[0].phys_addr;
5551 } else {
5552 #ifdef _ILP32
5553 con_log(CL_ANN1, (CE_CONT, "issue_mfi_dcmd: DDI_MODEL_ILP32"));
5554 xferlen = kdcmd->sgl.sge32[0].length;
5555 ubuf = (void *)(ulong_t)kdcmd->sgl.sge32[0].phys_addr;
5556 #else
5557 con_log(CL_ANN1, (CE_CONT, "issue_mfi_dcmd: DDI_MODEL_LP64"));
5558 xferlen = kdcmd->sgl.sge64[0].length;
5559 ubuf = (void *)(ulong_t)kdcmd->sgl.sge64[0].phys_addr;
5560 #endif
5561 }
5562 if (xferlen) {
5563 /* means IOCTL requires DMA */
5564 /* allocate the data transfer buffer */
5565 /* dcmd_dma_obj.size = xferlen; */
5566 MRSAS_GET_BOUNDARY_ALIGNED_LEN(xferlen, new_xfer_length,
5567 PAGESIZE);
5568 dcmd_dma_obj.size = new_xfer_length;
5569 dcmd_dma_obj.dma_attr = mrsas_generic_dma_attr;
5570 dcmd_dma_obj.dma_attr.dma_attr_addr_hi = 0xFFFFFFFFU;
5571 dcmd_dma_obj.dma_attr.dma_attr_count_max = 0xFFFFFFFFU;
5572 dcmd_dma_obj.dma_attr.dma_attr_sgllen = 1;
5573 dcmd_dma_obj.dma_attr.dma_attr_align = 1;
5574
5575 /* allocate kernel buffer for DMA */
5576 if (mrsas_alloc_dma_obj(instance, &dcmd_dma_obj,
5577 (uchar_t)DDI_STRUCTURE_LE_ACC) != 1) {
5578 con_log(CL_ANN,
5579 (CE_WARN, "issue_mfi_dcmd: could not "
5580 "allocate data transfer buffer."));
5581 return (DDI_FAILURE);
5582 }
5583 (void) memset(dcmd_dma_obj.buffer, 0, xferlen);
5584
5585 /* If IOCTL requires DMA WRITE, do ddi_copyin IOCTL data copy */
5586 if (kdcmd->flags & MFI_FRAME_DIR_WRITE) {
5587 for (i = 0; i < xferlen; i++) {
5588 if (ddi_copyin((uint8_t *)ubuf + i,
5589 (uint8_t *)dcmd_dma_obj.buffer + i,
5590 1, mode)) {
5591 con_log(CL_ANN, (CE_WARN,
5592 "issue_mfi_dcmd : "
5593 "copy from user space failed"));
5594 return (DDI_FAILURE);
5595 }
5596 }
5597 }
5598
5599 kphys_addr = dcmd_dma_obj.dma_cookie[0].dmac_address;
5600 }
5601
5602 ddi_put8(acc_handle, &dcmd->cmd, kdcmd->cmd);
5603 ddi_put8(acc_handle, &dcmd->cmd_status, 0);
5604 ddi_put8(acc_handle, &dcmd->sge_count, kdcmd->sge_count);
5605 ddi_put16(acc_handle, &dcmd->timeout, kdcmd->timeout);
5606 ddi_put32(acc_handle, &dcmd->data_xfer_len, kdcmd->data_xfer_len);
5607 ddi_put32(acc_handle, &dcmd->opcode, kdcmd->opcode);
5608
5609 ddi_rep_put8(acc_handle, (uint8_t *)kdcmd->mbox.b,
5610 (uint8_t *)dcmd->mbox.b, DCMD_MBOX_SZ, DDI_DEV_AUTOINCR);
5611
5612 ddi_put16(acc_handle, &dcmd->flags, kdcmd->flags & ~MFI_FRAME_SGL64);
5613 ddi_put32(acc_handle, &dcmd->sgl.sge32[0].length, xferlen);
5614 ddi_put32(acc_handle, &dcmd->sgl.sge32[0].phys_addr, kphys_addr);
5615
5616 cmd->sync_cmd = MRSAS_TRUE;
5617 cmd->frame_count = 1;
5618
5619 if (instance->tbolt) {
5620 mr_sas_tbolt_build_mfi_cmd(instance, cmd);
5621 }
5622
5623 if (instance->func_ptr->issue_cmd_in_sync_mode(instance, cmd)) {
5624 con_log(CL_ANN, (CE_WARN, "issue_mfi_dcmd: fw_ioctl failed"));
5625 } else {
5626 if (xferlen && (kdcmd->flags & MFI_FRAME_DIR_READ)) {
5627 for (i = 0; i < xferlen; i++) {
5628 if (ddi_copyout(
5629 (uint8_t *)dcmd_dma_obj.buffer + i,
5630 (uint8_t *)ubuf + i,
5631 1, mode)) {
5632 con_log(CL_ANN, (CE_WARN,
5633 "issue_mfi_dcmd : "
5634 "copy to user space failed"));
5635 return (DDI_FAILURE);
5636 }
5637 }
5638 }
5639 }
5640
5641 kdcmd->cmd_status = ddi_get8(acc_handle, &dcmd->cmd_status);
5642 con_log(CL_ANN,
5643 (CE_CONT, "issue_mfi_dcmd: cmd_status %x", kdcmd->cmd_status));
5644 DTRACE_PROBE3(issue_dcmd, uint32_t, kdcmd->opcode, uint8_t,
5645 kdcmd->cmd, uint8_t, kdcmd->cmd_status);
5646
5647 if (xferlen) {
5648 /* free kernel buffer */
5649 if (mrsas_free_dma_obj(instance, dcmd_dma_obj) != DDI_SUCCESS)
5650 return (DDI_FAILURE);
5651 }
5652
5653 return (DDI_SUCCESS);
5654 }
5655
5656 /*
5657 * issue_mfi_smp
5658 */
5659 static int
5660 issue_mfi_smp(struct mrsas_instance *instance, struct mrsas_ioctl *ioctl,
5661 struct mrsas_cmd *cmd, int mode)
5662 {
5663 void *request_ubuf;
5664 void *response_ubuf;
5665 uint32_t request_xferlen = 0;
5666 uint32_t response_xferlen = 0;
5667 uint32_t new_xfer_length1 = 0;
5668 uint32_t new_xfer_length2 = 0;
5669 uint_t model;
5670 dma_obj_t request_dma_obj;
5671 dma_obj_t response_dma_obj;
5672 ddi_acc_handle_t acc_handle = cmd->frame_dma_obj.acc_handle;
5673 struct mrsas_smp_frame *ksmp;
5674 struct mrsas_smp_frame *smp;
5675 struct mrsas_sge32 *sge32;
5676 #ifndef _ILP32
5677 struct mrsas_sge64 *sge64;
5678 #endif
5679 int i;
5680 uint64_t tmp_sas_addr;
5681
5682 smp = &cmd->frame->smp;
5683 ksmp = (struct mrsas_smp_frame *)&ioctl->frame[0];
5684
5685 if (instance->adapterresetinprogress) {
5686 con_log(CL_ANN1, (CE_WARN, "Reset flag set, "
5687 "returning mfi_pkt and setting TRAN_BUSY\n"));
5688 return (DDI_FAILURE);
5689 }
5690 model = ddi_model_convert_from(mode & FMODELS);
5691 if (model == DDI_MODEL_ILP32) {
5692 con_log(CL_ANN1, (CE_CONT, "issue_mfi_smp: DDI_MODEL_ILP32"));
5693
5694 sge32 = &ksmp->sgl[0].sge32[0];
5695 response_xferlen = sge32[0].length;
5696 request_xferlen = sge32[1].length;
5697 con_log(CL_ANN, (CE_CONT, "issue_mfi_smp: "
5698 "response_xferlen = %x, request_xferlen = %x",
5699 response_xferlen, request_xferlen));
5700
5701 response_ubuf = (void *)(ulong_t)sge32[0].phys_addr;
5702 request_ubuf = (void *)(ulong_t)sge32[1].phys_addr;
5703 con_log(CL_ANN1, (CE_CONT, "issue_mfi_smp: "
5704 "response_ubuf = %p, request_ubuf = %p",
5705 response_ubuf, request_ubuf));
5706 } else {
5707 #ifdef _ILP32
5708 con_log(CL_ANN1, (CE_CONT, "issue_mfi_smp: DDI_MODEL_ILP32"));
5709
5710 sge32 = &ksmp->sgl[0].sge32[0];
5711 response_xferlen = sge32[0].length;
5712 request_xferlen = sge32[1].length;
5713 con_log(CL_ANN, (CE_CONT, "issue_mfi_smp: "
5714 "response_xferlen = %x, request_xferlen = %x",
5715 response_xferlen, request_xferlen));
5716
5717 response_ubuf = (void *)(ulong_t)sge32[0].phys_addr;
5718 request_ubuf = (void *)(ulong_t)sge32[1].phys_addr;
5719 con_log(CL_ANN1, (CE_CONT, "issue_mfi_smp: "
5720 "response_ubuf = %p, request_ubuf = %p",
5721 response_ubuf, request_ubuf));
5722 #else
5723 con_log(CL_ANN1, (CE_CONT, "issue_mfi_smp: DDI_MODEL_LP64"));
5724
5725 sge64 = &ksmp->sgl[0].sge64[0];
5726 response_xferlen = sge64[0].length;
5727 request_xferlen = sge64[1].length;
5728
5729 response_ubuf = (void *)(ulong_t)sge64[0].phys_addr;
5730 request_ubuf = (void *)(ulong_t)sge64[1].phys_addr;
5731 #endif
5732 }
5733 if (request_xferlen) {
5734 /* means IOCTL requires DMA */
5735 /* allocate the data transfer buffer */
5736 /* request_dma_obj.size = request_xferlen; */
5737 MRSAS_GET_BOUNDARY_ALIGNED_LEN(request_xferlen,
5738 new_xfer_length1, PAGESIZE);
5739 request_dma_obj.size = new_xfer_length1;
5740 request_dma_obj.dma_attr = mrsas_generic_dma_attr;
5741 request_dma_obj.dma_attr.dma_attr_addr_hi = 0xFFFFFFFFU;
5742 request_dma_obj.dma_attr.dma_attr_count_max = 0xFFFFFFFFU;
5743 request_dma_obj.dma_attr.dma_attr_sgllen = 1;
5744 request_dma_obj.dma_attr.dma_attr_align = 1;
5745
5746 /* allocate kernel buffer for DMA */
5747 if (mrsas_alloc_dma_obj(instance, &request_dma_obj,
5748 (uchar_t)DDI_STRUCTURE_LE_ACC) != 1) {
5749 con_log(CL_ANN, (CE_WARN, "issue_mfi_smp: "
5750 "could not allocate data transfer buffer."));
5751 return (DDI_FAILURE);
5752 }
5753 (void) memset(request_dma_obj.buffer, 0, request_xferlen);
5754
5755 /* If IOCTL requires DMA WRITE, do ddi_copyin IOCTL data copy */
5756 for (i = 0; i < request_xferlen; i++) {
5757 if (ddi_copyin((uint8_t *)request_ubuf + i,
5758 (uint8_t *)request_dma_obj.buffer + i,
5759 1, mode)) {
5760 con_log(CL_ANN, (CE_WARN, "issue_mfi_smp: "
5761 "copy from user space failed"));
5762 return (DDI_FAILURE);
5763 }
5764 }
5765 }
5766
5767 if (response_xferlen) {
5768 /* means IOCTL requires DMA */
5769 /* allocate the data transfer buffer */
5770 /* response_dma_obj.size = response_xferlen; */
5771 MRSAS_GET_BOUNDARY_ALIGNED_LEN(response_xferlen,
5772 new_xfer_length2, PAGESIZE);
5773 response_dma_obj.size = new_xfer_length2;
5774 response_dma_obj.dma_attr = mrsas_generic_dma_attr;
5775 response_dma_obj.dma_attr.dma_attr_addr_hi = 0xFFFFFFFFU;
5776 response_dma_obj.dma_attr.dma_attr_count_max = 0xFFFFFFFFU;
5777 response_dma_obj.dma_attr.dma_attr_sgllen = 1;
5778 response_dma_obj.dma_attr.dma_attr_align = 1;
5779
5780 /* allocate kernel buffer for DMA */
5781 if (mrsas_alloc_dma_obj(instance, &response_dma_obj,
5782 (uchar_t)DDI_STRUCTURE_LE_ACC) != 1) {
5783 con_log(CL_ANN, (CE_WARN, "issue_mfi_smp: "
5784 "could not allocate data transfer buffer."));
5785 return (DDI_FAILURE);
5786 }
5787 (void) memset(response_dma_obj.buffer, 0, response_xferlen);
5788
5789 /* If IOCTL requires DMA WRITE, do ddi_copyin IOCTL data copy */
5790 for (i = 0; i < response_xferlen; i++) {
5791 if (ddi_copyin((uint8_t *)response_ubuf + i,
5792 (uint8_t *)response_dma_obj.buffer + i,
5793 1, mode)) {
5794 con_log(CL_ANN, (CE_WARN, "issue_mfi_smp: "
5795 "copy from user space failed"));
5796 return (DDI_FAILURE);
5797 }
5798 }
5799 }
5800
5801 ddi_put8(acc_handle, &smp->cmd, ksmp->cmd);
5802 ddi_put8(acc_handle, &smp->cmd_status, 0);
5803 ddi_put8(acc_handle, &smp->connection_status, 0);
5804 ddi_put8(acc_handle, &smp->sge_count, ksmp->sge_count);
5805 /* smp->context = ksmp->context; */
5806 ddi_put16(acc_handle, &smp->timeout, ksmp->timeout);
5807 ddi_put32(acc_handle, &smp->data_xfer_len, ksmp->data_xfer_len);
5808
5809 bcopy((void *)&ksmp->sas_addr, (void *)&tmp_sas_addr,
5810 sizeof (uint64_t));
5811 ddi_put64(acc_handle, &smp->sas_addr, tmp_sas_addr);
5812
5813 ddi_put16(acc_handle, &smp->flags, ksmp->flags & ~MFI_FRAME_SGL64);
5814
5815 model = ddi_model_convert_from(mode & FMODELS);
5816 if (model == DDI_MODEL_ILP32) {
5817 con_log(CL_ANN1, (CE_CONT,
5818 "issue_mfi_smp: DDI_MODEL_ILP32"));
5819
5820 sge32 = &smp->sgl[0].sge32[0];
5821 ddi_put32(acc_handle, &sge32[0].length, response_xferlen);
5822 ddi_put32(acc_handle, &sge32[0].phys_addr,
5823 response_dma_obj.dma_cookie[0].dmac_address);
5824 ddi_put32(acc_handle, &sge32[1].length, request_xferlen);
5825 ddi_put32(acc_handle, &sge32[1].phys_addr,
5826 request_dma_obj.dma_cookie[0].dmac_address);
5827 } else {
5828 #ifdef _ILP32
5829 con_log(CL_ANN1, (CE_CONT,
5830 "issue_mfi_smp: DDI_MODEL_ILP32"));
5831 sge32 = &smp->sgl[0].sge32[0];
5832 ddi_put32(acc_handle, &sge32[0].length, response_xferlen);
5833 ddi_put32(acc_handle, &sge32[0].phys_addr,
5834 response_dma_obj.dma_cookie[0].dmac_address);
5835 ddi_put32(acc_handle, &sge32[1].length, request_xferlen);
5836 ddi_put32(acc_handle, &sge32[1].phys_addr,
5837 request_dma_obj.dma_cookie[0].dmac_address);
5838 #else
5839 con_log(CL_ANN1, (CE_CONT,
5840 "issue_mfi_smp: DDI_MODEL_LP64"));
5841 sge64 = &smp->sgl[0].sge64[0];
5842 ddi_put32(acc_handle, &sge64[0].length, response_xferlen);
5843 ddi_put64(acc_handle, &sge64[0].phys_addr,
5844 response_dma_obj.dma_cookie[0].dmac_address);
5845 ddi_put32(acc_handle, &sge64[1].length, request_xferlen);
5846 ddi_put64(acc_handle, &sge64[1].phys_addr,
5847 request_dma_obj.dma_cookie[0].dmac_address);
5848 #endif
5849 }
5850 con_log(CL_ANN1, (CE_CONT, "issue_mfi_smp : "
5851 "smp->response_xferlen = %d, smp->request_xferlen = %d "
5852 "smp->data_xfer_len = %d", ddi_get32(acc_handle, &sge32[0].length),
5853 ddi_get32(acc_handle, &sge32[1].length),
5854 ddi_get32(acc_handle, &smp->data_xfer_len)));
5855
5856 cmd->sync_cmd = MRSAS_TRUE;
5857 cmd->frame_count = 1;
5858
5859 if (instance->tbolt) {
5860 mr_sas_tbolt_build_mfi_cmd(instance, cmd);
5861 }
5862
5863 if (instance->func_ptr->issue_cmd_in_sync_mode(instance, cmd)) {
5864 con_log(CL_ANN, (CE_WARN,
5865 "issue_mfi_smp: fw_ioctl failed"));
5866 } else {
5867 con_log(CL_ANN1, (CE_CONT,
5868 "issue_mfi_smp: copy to user space"));
5869
5870 if (request_xferlen) {
5871 for (i = 0; i < request_xferlen; i++) {
5872 if (ddi_copyout(
5873 (uint8_t *)request_dma_obj.buffer +
5874 i, (uint8_t *)request_ubuf + i,
5875 1, mode)) {
5876 con_log(CL_ANN, (CE_WARN,
5877 "issue_mfi_smp : copy to user space"
5878 " failed"));
5879 return (DDI_FAILURE);
5880 }
5881 }
5882 }
5883
5884 if (response_xferlen) {
5885 for (i = 0; i < response_xferlen; i++) {
5886 if (ddi_copyout(
5887 (uint8_t *)response_dma_obj.buffer
5888 + i, (uint8_t *)response_ubuf
5889 + i, 1, mode)) {
5890 con_log(CL_ANN, (CE_WARN,
5891 "issue_mfi_smp : copy to "
5892 "user space failed"));
5893 return (DDI_FAILURE);
5894 }
5895 }
5896 }
5897 }
5898
5899 ksmp->cmd_status = ddi_get8(acc_handle, &smp->cmd_status);
5900 con_log(CL_ANN1, (CE_NOTE, "issue_mfi_smp: smp->cmd_status = %d",
5901 ksmp->cmd_status));
5902 DTRACE_PROBE2(issue_smp, uint8_t, ksmp->cmd, uint8_t, ksmp->cmd_status);
5903
5904 if (request_xferlen) {
5905 /* free kernel buffer */
5906 if (mrsas_free_dma_obj(instance, request_dma_obj) !=
5907 DDI_SUCCESS)
5908 return (DDI_FAILURE);
5909 }
5910
5911 if (response_xferlen) {
5912 /* free kernel buffer */
5913 if (mrsas_free_dma_obj(instance, response_dma_obj) !=
5914 DDI_SUCCESS)
5915 return (DDI_FAILURE);
5916 }
5917
5918 return (DDI_SUCCESS);
5919 }
5920
5921 /*
5922 * issue_mfi_stp
5923 */
5924 static int
5925 issue_mfi_stp(struct mrsas_instance *instance, struct mrsas_ioctl *ioctl,
5926 struct mrsas_cmd *cmd, int mode)
5927 {
5928 void *fis_ubuf;
5929 void *data_ubuf;
5930 uint32_t fis_xferlen = 0;
5931 uint32_t new_xfer_length1 = 0;
5932 uint32_t new_xfer_length2 = 0;
5933 uint32_t data_xferlen = 0;
5934 uint_t model;
5935 dma_obj_t fis_dma_obj;
5936 dma_obj_t data_dma_obj;
5937 struct mrsas_stp_frame *kstp;
5938 struct mrsas_stp_frame *stp;
5939 ddi_acc_handle_t acc_handle = cmd->frame_dma_obj.acc_handle;
5940 int i;
5941
5942 stp = &cmd->frame->stp;
5943 kstp = (struct mrsas_stp_frame *)&ioctl->frame[0];
5944
5945 if (instance->adapterresetinprogress) {
5946 con_log(CL_ANN1, (CE_WARN, "Reset flag set, "
5947 "returning mfi_pkt and setting TRAN_BUSY\n"));
5948 return (DDI_FAILURE);
5949 }
5950 model = ddi_model_convert_from(mode & FMODELS);
5951 if (model == DDI_MODEL_ILP32) {
5952 con_log(CL_ANN1, (CE_CONT, "issue_mfi_stp: DDI_MODEL_ILP32"));
5953
5954 fis_xferlen = kstp->sgl.sge32[0].length;
5955 data_xferlen = kstp->sgl.sge32[1].length;
5956
5957 fis_ubuf = (void *)(ulong_t)kstp->sgl.sge32[0].phys_addr;
5958 data_ubuf = (void *)(ulong_t)kstp->sgl.sge32[1].phys_addr;
5959 } else {
5960 #ifdef _ILP32
5961 con_log(CL_ANN1, (CE_CONT, "issue_mfi_stp: DDI_MODEL_ILP32"));
5962
5963 fis_xferlen = kstp->sgl.sge32[0].length;
5964 data_xferlen = kstp->sgl.sge32[1].length;
5965
5966 fis_ubuf = (void *)(ulong_t)kstp->sgl.sge32[0].phys_addr;
5967 data_ubuf = (void *)(ulong_t)kstp->sgl.sge32[1].phys_addr;
5968 #else
5969 con_log(CL_ANN1, (CE_CONT, "issue_mfi_stp: DDI_MODEL_LP64"));
5970
5971 fis_xferlen = kstp->sgl.sge64[0].length;
5972 data_xferlen = kstp->sgl.sge64[1].length;
5973
5974 fis_ubuf = (void *)(ulong_t)kstp->sgl.sge64[0].phys_addr;
5975 data_ubuf = (void *)(ulong_t)kstp->sgl.sge64[1].phys_addr;
5976 #endif
5977 }
5978
5979
5980 if (fis_xferlen) {
5981 con_log(CL_ANN, (CE_CONT, "issue_mfi_stp: "
5982 "fis_ubuf = %p fis_xferlen = %x", fis_ubuf, fis_xferlen));
5983
5984 /* means IOCTL requires DMA */
5985 /* allocate the data transfer buffer */
5986 /* fis_dma_obj.size = fis_xferlen; */
5987 MRSAS_GET_BOUNDARY_ALIGNED_LEN(fis_xferlen,
5988 new_xfer_length1, PAGESIZE);
5989 fis_dma_obj.size = new_xfer_length1;
5990 fis_dma_obj.dma_attr = mrsas_generic_dma_attr;
5991 fis_dma_obj.dma_attr.dma_attr_addr_hi = 0xFFFFFFFFU;
5992 fis_dma_obj.dma_attr.dma_attr_count_max = 0xFFFFFFFFU;
5993 fis_dma_obj.dma_attr.dma_attr_sgllen = 1;
5994 fis_dma_obj.dma_attr.dma_attr_align = 1;
5995
5996 /* allocate kernel buffer for DMA */
5997 if (mrsas_alloc_dma_obj(instance, &fis_dma_obj,
5998 (uchar_t)DDI_STRUCTURE_LE_ACC) != 1) {
5999 con_log(CL_ANN, (CE_WARN, "issue_mfi_stp : "
6000 "could not allocate data transfer buffer."));
6001 return (DDI_FAILURE);
6002 }
6003 (void) memset(fis_dma_obj.buffer, 0, fis_xferlen);
6004
6005 /* If IOCTL requires DMA WRITE, do ddi_copyin IOCTL data copy */
6006 for (i = 0; i < fis_xferlen; i++) {
6007 if (ddi_copyin((uint8_t *)fis_ubuf + i,
6008 (uint8_t *)fis_dma_obj.buffer + i, 1, mode)) {
6009 con_log(CL_ANN, (CE_WARN, "issue_mfi_stp: "
6010 "copy from user space failed"));
6011 return (DDI_FAILURE);
6012 }
6013 }
6014 }
6015
6016 if (data_xferlen) {
6017 con_log(CL_ANN, (CE_CONT, "issue_mfi_stp: data_ubuf = %p "
6018 "data_xferlen = %x", data_ubuf, data_xferlen));
6019
6020 /* means IOCTL requires DMA */
6021 /* allocate the data transfer buffer */
6022 /* data_dma_obj.size = data_xferlen; */
6023 MRSAS_GET_BOUNDARY_ALIGNED_LEN(data_xferlen, new_xfer_length2,
6024 PAGESIZE);
6025 data_dma_obj.size = new_xfer_length2;
6026 data_dma_obj.dma_attr = mrsas_generic_dma_attr;
6027 data_dma_obj.dma_attr.dma_attr_addr_hi = 0xFFFFFFFFU;
6028 data_dma_obj.dma_attr.dma_attr_count_max = 0xFFFFFFFFU;
6029 data_dma_obj.dma_attr.dma_attr_sgllen = 1;
6030 data_dma_obj.dma_attr.dma_attr_align = 1;
6031
6032 /* allocate kernel buffer for DMA */
6033 if (mrsas_alloc_dma_obj(instance, &data_dma_obj,
6034 (uchar_t)DDI_STRUCTURE_LE_ACC) != 1) {
6035 con_log(CL_ANN, (CE_WARN, "issue_mfi_stp: "
6036 "could not allocate data transfer buffer."));
6037 return (DDI_FAILURE);
6038 }
6039 (void) memset(data_dma_obj.buffer, 0, data_xferlen);
6040
6041 /* If IOCTL requires DMA WRITE, do ddi_copyin IOCTL data copy */
6042 for (i = 0; i < data_xferlen; i++) {
6043 if (ddi_copyin((uint8_t *)data_ubuf + i,
6044 (uint8_t *)data_dma_obj.buffer + i, 1, mode)) {
6045 con_log(CL_ANN, (CE_WARN, "issue_mfi_stp: "
6046 "copy from user space failed"));
6047 return (DDI_FAILURE);
6048 }
6049 }
6050 }
6051
6052 ddi_put8(acc_handle, &stp->cmd, kstp->cmd);
6053 ddi_put8(acc_handle, &stp->cmd_status, 0);
6054 ddi_put8(acc_handle, &stp->connection_status, 0);
6055 ddi_put8(acc_handle, &stp->target_id, kstp->target_id);
6056 ddi_put8(acc_handle, &stp->sge_count, kstp->sge_count);
6057
6058 ddi_put16(acc_handle, &stp->timeout, kstp->timeout);
6059 ddi_put32(acc_handle, &stp->data_xfer_len, kstp->data_xfer_len);
6060
6061 ddi_rep_put8(acc_handle, (uint8_t *)kstp->fis, (uint8_t *)stp->fis, 10,
6062 DDI_DEV_AUTOINCR);
6063
6064 ddi_put16(acc_handle, &stp->flags, kstp->flags & ~MFI_FRAME_SGL64);
6065 ddi_put32(acc_handle, &stp->stp_flags, kstp->stp_flags);
6066 ddi_put32(acc_handle, &stp->sgl.sge32[0].length, fis_xferlen);
6067 ddi_put32(acc_handle, &stp->sgl.sge32[0].phys_addr,
6068 fis_dma_obj.dma_cookie[0].dmac_address);
6069 ddi_put32(acc_handle, &stp->sgl.sge32[1].length, data_xferlen);
6070 ddi_put32(acc_handle, &stp->sgl.sge32[1].phys_addr,
6071 data_dma_obj.dma_cookie[0].dmac_address);
6072
6073 cmd->sync_cmd = MRSAS_TRUE;
6074 cmd->frame_count = 1;
6075
6076 if (instance->tbolt) {
6077 mr_sas_tbolt_build_mfi_cmd(instance, cmd);
6078 }
6079
6080 if (instance->func_ptr->issue_cmd_in_sync_mode(instance, cmd)) {
6081 con_log(CL_ANN, (CE_WARN, "issue_mfi_stp: fw_ioctl failed"));
6082 } else {
6083
6084 if (fis_xferlen) {
6085 for (i = 0; i < fis_xferlen; i++) {
6086 if (ddi_copyout(
6087 (uint8_t *)fis_dma_obj.buffer + i,
6088 (uint8_t *)fis_ubuf + i, 1, mode)) {
6089 con_log(CL_ANN, (CE_WARN,
6090 "issue_mfi_stp : copy to "
6091 "user space failed"));
6092 return (DDI_FAILURE);
6093 }
6094 }
6095 }
6096 }
6097 if (data_xferlen) {
6098 for (i = 0; i < data_xferlen; i++) {
6099 if (ddi_copyout(
6100 (uint8_t *)data_dma_obj.buffer + i,
6101 (uint8_t *)data_ubuf + i, 1, mode)) {
6102 con_log(CL_ANN, (CE_WARN,
6103 "issue_mfi_stp : copy to"
6104 " user space failed"));
6105 return (DDI_FAILURE);
6106 }
6107 }
6108 }
6109
6110 kstp->cmd_status = ddi_get8(acc_handle, &stp->cmd_status);
6111 con_log(CL_ANN1, (CE_NOTE, "issue_mfi_stp: stp->cmd_status = %d",
6112 kstp->cmd_status));
6113 DTRACE_PROBE2(issue_stp, uint8_t, kstp->cmd, uint8_t, kstp->cmd_status);
6114
6115 if (fis_xferlen) {
6116 /* free kernel buffer */
6117 if (mrsas_free_dma_obj(instance, fis_dma_obj) != DDI_SUCCESS)
6118 return (DDI_FAILURE);
6119 }
6120
6121 if (data_xferlen) {
6122 /* free kernel buffer */
6123 if (mrsas_free_dma_obj(instance, data_dma_obj) != DDI_SUCCESS)
6124 return (DDI_FAILURE);
6125 }
6126
6127 return (DDI_SUCCESS);
6128 }
6129
6130 /*
6131 * fill_up_drv_ver
6132 */
6133 void
6134 fill_up_drv_ver(struct mrsas_drv_ver *dv)
6135 {
6136 (void) memset(dv, 0, sizeof (struct mrsas_drv_ver));
6137
6138 (void) memcpy(dv->signature, "$LSI LOGIC$", strlen("$LSI LOGIC$"));
6139 (void) memcpy(dv->os_name, "Solaris", strlen("Solaris"));
6140 (void) memcpy(dv->drv_name, "mr_sas", strlen("mr_sas"));
6141 (void) memcpy(dv->drv_ver, MRSAS_VERSION, strlen(MRSAS_VERSION));
6142 (void) memcpy(dv->drv_rel_date, MRSAS_RELDATE,
6143 strlen(MRSAS_RELDATE));
6144
6145 }
6146
6147 /*
6148 * handle_drv_ioctl
6149 */
6150 static int
6151 handle_drv_ioctl(struct mrsas_instance *instance, struct mrsas_ioctl *ioctl,
6152 int mode)
6153 {
6154 int i;
6155 int rval = DDI_SUCCESS;
6156 int *props = NULL;
6157 void *ubuf;
6158
6159 uint8_t *pci_conf_buf;
6160 uint32_t xferlen;
6161 uint32_t num_props;
6162 uint_t model;
6163 struct mrsas_dcmd_frame *kdcmd;
6164 struct mrsas_drv_ver dv;
6165 struct mrsas_pci_information pi;
6166
6167 kdcmd = (struct mrsas_dcmd_frame *)&ioctl->frame[0];
6168
6169 model = ddi_model_convert_from(mode & FMODELS);
6170 if (model == DDI_MODEL_ILP32) {
6171 con_log(CL_ANN1, (CE_CONT,
6172 "handle_drv_ioctl: DDI_MODEL_ILP32"));
6173
6174 xferlen = kdcmd->sgl.sge32[0].length;
6175
6176 ubuf = (void *)(ulong_t)kdcmd->sgl.sge32[0].phys_addr;
6177 } else {
6178 #ifdef _ILP32
6179 con_log(CL_ANN1, (CE_CONT,
6180 "handle_drv_ioctl: DDI_MODEL_ILP32"));
6181 xferlen = kdcmd->sgl.sge32[0].length;
6182 ubuf = (void *)(ulong_t)kdcmd->sgl.sge32[0].phys_addr;
6183 #else
6184 con_log(CL_ANN1, (CE_CONT,
6185 "handle_drv_ioctl: DDI_MODEL_LP64"));
6186 xferlen = kdcmd->sgl.sge64[0].length;
6187 ubuf = (void *)(ulong_t)kdcmd->sgl.sge64[0].phys_addr;
6188 #endif
6189 }
6190 con_log(CL_ANN1, (CE_CONT, "handle_drv_ioctl: "
6191 "dataBuf=%p size=%d bytes", ubuf, xferlen));
6192
6193 switch (kdcmd->opcode) {
6194 case MRSAS_DRIVER_IOCTL_DRIVER_VERSION:
6195 con_log(CL_ANN1, (CE_CONT, "handle_drv_ioctl: "
6196 "MRSAS_DRIVER_IOCTL_DRIVER_VERSION"));
6197
6198 fill_up_drv_ver(&dv);
6199
6200 if (ddi_copyout(&dv, ubuf, xferlen, mode)) {
6201 con_log(CL_ANN, (CE_WARN, "handle_drv_ioctl: "
6202 "MRSAS_DRIVER_IOCTL_DRIVER_VERSION : "
6203 "copy to user space failed"));
6204 kdcmd->cmd_status = 1;
6205 rval = 1;
6206 } else {
6207 kdcmd->cmd_status = 0;
6208 }
6209 break;
6210 case MRSAS_DRIVER_IOCTL_PCI_INFORMATION:
6211 con_log(CL_ANN1, (CE_NOTE, "handle_drv_ioctl: "
6212 "MRSAS_DRIVER_IOCTL_PCI_INFORMAITON"));
6213
6214 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, instance->dip,
6215 0, "reg", &props, &num_props)) {
6216 con_log(CL_ANN, (CE_WARN, "handle_drv_ioctl: "
6217 "MRSAS_DRIVER_IOCTL_PCI_INFORMATION : "
6218 "ddi_prop_look_int_array failed"));
6219 rval = DDI_FAILURE;
6220 } else {
6221
6222 pi.busNumber = (props[0] >> 16) & 0xFF;
6223 pi.deviceNumber = (props[0] >> 11) & 0x1f;
6224 pi.functionNumber = (props[0] >> 8) & 0x7;
6225 ddi_prop_free((void *)props);
6226 }
6227
6228 pci_conf_buf = (uint8_t *)&pi.pciHeaderInfo;
6229
6230 for (i = 0; i < (sizeof (struct mrsas_pci_information) -
6231 offsetof(struct mrsas_pci_information, pciHeaderInfo));
6232 i++) {
6233 pci_conf_buf[i] =
6234 pci_config_get8(instance->pci_handle, i);
6235 }
6236
6237 if (ddi_copyout(&pi, ubuf, xferlen, mode)) {
6238 con_log(CL_ANN, (CE_WARN, "handle_drv_ioctl: "
6239 "MRSAS_DRIVER_IOCTL_PCI_INFORMATION : "
6240 "copy to user space failed"));
6241 kdcmd->cmd_status = 1;
6242 rval = 1;
6243 } else {
6244 kdcmd->cmd_status = 0;
6245 }
6246 break;
6247 default:
6248 con_log(CL_ANN, (CE_WARN, "handle_drv_ioctl: "
6249 "invalid driver specific IOCTL opcode = 0x%x",
6250 kdcmd->opcode));
6251 kdcmd->cmd_status = 1;
6252 rval = DDI_FAILURE;
6253 break;
6254 }
6255
6256 return (rval);
6257 }
6258
6259 /*
6260 * handle_mfi_ioctl
6261 */
6262 static int
6263 handle_mfi_ioctl(struct mrsas_instance *instance, struct mrsas_ioctl *ioctl,
6264 int mode)
6265 {
6266 int rval = DDI_SUCCESS;
6267
6268 struct mrsas_header *hdr;
6269 struct mrsas_cmd *cmd;
6270
6271 if (instance->tbolt) {
6272 cmd = get_raid_msg_mfi_pkt(instance);
6273 } else {
6274 cmd = mrsas_get_mfi_pkt(instance);
6275 }
6276 if (!cmd) {
6277 con_log(CL_ANN, (CE_WARN, "mr_sas: "
6278 "failed to get a cmd packet"));
6279 DTRACE_PROBE2(mfi_ioctl_err, uint16_t,
6280 instance->fw_outstanding, uint16_t, instance->max_fw_cmds);
6281 return (DDI_FAILURE);
6282 }
6283
6284 /* Clear the frame buffer and assign back the context id */
6285 (void) memset((char *)&cmd->frame[0], 0, sizeof (union mrsas_frame));
6286 ddi_put32(cmd->frame_dma_obj.acc_handle, &cmd->frame->hdr.context,
6287 cmd->index);
6288
6289 hdr = (struct mrsas_header *)&ioctl->frame[0];
6290
6291 switch (ddi_get8(cmd->frame_dma_obj.acc_handle, &hdr->cmd)) {
6292 case MFI_CMD_OP_DCMD:
6293 rval = issue_mfi_dcmd(instance, ioctl, cmd, mode);
6294 break;
6295 case MFI_CMD_OP_SMP:
6296 rval = issue_mfi_smp(instance, ioctl, cmd, mode);
6297 break;
6298 case MFI_CMD_OP_STP:
6299 rval = issue_mfi_stp(instance, ioctl, cmd, mode);
6300 break;
6301 case MFI_CMD_OP_LD_SCSI:
6302 case MFI_CMD_OP_PD_SCSI:
6303 rval = issue_mfi_pthru(instance, ioctl, cmd, mode);
6304 break;
6305 default:
6306 con_log(CL_ANN, (CE_WARN, "handle_mfi_ioctl: "
6307 "invalid mfi ioctl hdr->cmd = %d", hdr->cmd));
6308 rval = DDI_FAILURE;
6309 break;
6310 }
6311
6312 if (mrsas_common_check(instance, cmd) != DDI_SUCCESS)
6313 rval = DDI_FAILURE;
6314
6315 if (instance->tbolt) {
6316 return_raid_msg_mfi_pkt(instance, cmd);
6317 } else {
6318 mrsas_return_mfi_pkt(instance, cmd);
6319 }
6320
6321 return (rval);
6322 }
6323
6324 /*
6325 * AEN
6326 */
6327 static int
6328 handle_mfi_aen(struct mrsas_instance *instance, struct mrsas_aen *aen)
6329 {
6330 int rval = 0;
6331
6332 rval = register_mfi_aen(instance, instance->aen_seq_num,
6333 aen->class_locale_word);
6334
6335 aen->cmd_status = (uint8_t)rval;
6336
6337 return (rval);
6338 }
6339
6340 static int
6341 register_mfi_aen(struct mrsas_instance *instance, uint32_t seq_num,
6342 uint32_t class_locale_word)
6343 {
6344 int ret_val;
6345
6346 struct mrsas_cmd *cmd, *aen_cmd;
6347 struct mrsas_dcmd_frame *dcmd;
6348 union mrsas_evt_class_locale curr_aen;
6349 union mrsas_evt_class_locale prev_aen;
6350
6351 con_log(CL_ANN, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__));
6352 /*
6353 * If there an AEN pending already (aen_cmd), check if the
6354 * class_locale of that pending AEN is inclusive of the new
6355 * AEN request we currently have. If it is, then we don't have
6356 * to do anything. In other words, whichever events the current
6357 * AEN request is subscribing to, have already been subscribed
6358 * to.
6359 *
6360 * If the old_cmd is _not_ inclusive, then we have to abort
6361 * that command, form a class_locale that is superset of both
6362 * old and current and re-issue to the FW
6363 */
6364
6365 curr_aen.word = LE_32(class_locale_word);
6366 curr_aen.members.locale = LE_16(curr_aen.members.locale);
6367 aen_cmd = instance->aen_cmd;
6368 if (aen_cmd) {
6369 prev_aen.word = ddi_get32(aen_cmd->frame_dma_obj.acc_handle,
6370 &aen_cmd->frame->dcmd.mbox.w[1]);
6371 prev_aen.word = LE_32(prev_aen.word);
6372 prev_aen.members.locale = LE_16(prev_aen.members.locale);
6373 /*
6374 * A class whose enum value is smaller is inclusive of all
6375 * higher values. If a PROGRESS (= -1) was previously
6376 * registered, then a new registration requests for higher
6377 * classes need not be sent to FW. They are automatically
6378 * included.
6379 *
6380 * Locale numbers don't have such hierarchy. They are bitmap
6381 * values
6382 */
6383 if ((prev_aen.members.class <= curr_aen.members.class) &&
6384 !((prev_aen.members.locale & curr_aen.members.locale) ^
6385 curr_aen.members.locale)) {
6386 /*
6387 * Previously issued event registration includes
6388 * current request. Nothing to do.
6389 */
6390
6391 return (0);
6392 } else {
6393 curr_aen.members.locale |= prev_aen.members.locale;
6394
6395 if (prev_aen.members.class < curr_aen.members.class)
6396 curr_aen.members.class = prev_aen.members.class;
6397
6398 ret_val = abort_aen_cmd(instance, aen_cmd);
6399
6400 if (ret_val) {
6401 con_log(CL_ANN, (CE_WARN, "register_mfi_aen: "
6402 "failed to abort prevous AEN command"));
6403
6404 return (ret_val);
6405 }
6406 }
6407 } else {
6408 curr_aen.word = LE_32(class_locale_word);
6409 curr_aen.members.locale = LE_16(curr_aen.members.locale);
6410 }
6411
6412 if (instance->tbolt) {
6413 cmd = get_raid_msg_mfi_pkt(instance);
6414 } else {
6415 cmd = mrsas_get_mfi_pkt(instance);
6416 }
6417
6418 if (!cmd) {
6419 DTRACE_PROBE2(mfi_aen_err, uint16_t, instance->fw_outstanding,
6420 uint16_t, instance->max_fw_cmds);
6421 return (ENOMEM);
6422 }
6423
6424 /* Clear the frame buffer and assign back the context id */
6425 (void) memset((char *)&cmd->frame[0], 0, sizeof (union mrsas_frame));
6426 ddi_put32(cmd->frame_dma_obj.acc_handle, &cmd->frame->hdr.context,
6427 cmd->index);
6428
6429 dcmd = &cmd->frame->dcmd;
6430
6431 /* for(i = 0; i < DCMD_MBOX_SZ; i++) dcmd->mbox.b[i] = 0; */
6432 (void) memset(dcmd->mbox.b, 0, DCMD_MBOX_SZ);
6433
6434 (void) memset(instance->mfi_evt_detail_obj.buffer, 0,
6435 sizeof (struct mrsas_evt_detail));
6436
6437 /* Prepare DCMD for aen registration */
6438 ddi_put8(cmd->frame_dma_obj.acc_handle, &dcmd->cmd, MFI_CMD_OP_DCMD);
6439 ddi_put8(cmd->frame_dma_obj.acc_handle, &dcmd->cmd_status, 0x0);
6440 ddi_put8(cmd->frame_dma_obj.acc_handle, &dcmd->sge_count, 1);
6441 ddi_put16(cmd->frame_dma_obj.acc_handle, &dcmd->flags,
6442 MFI_FRAME_DIR_READ);
6443 ddi_put16(cmd->frame_dma_obj.acc_handle, &dcmd->timeout, 0);
6444 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->data_xfer_len,
6445 sizeof (struct mrsas_evt_detail));
6446 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->opcode,
6447 MR_DCMD_CTRL_EVENT_WAIT);
6448 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->mbox.w[0], seq_num);
6449 curr_aen.members.locale = LE_16(curr_aen.members.locale);
6450 curr_aen.word = LE_32(curr_aen.word);
6451 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->mbox.w[1],
6452 curr_aen.word);
6453 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->sgl.sge32[0].phys_addr,
6454 instance->mfi_evt_detail_obj.dma_cookie[0].dmac_address);
6455 ddi_put32(cmd->frame_dma_obj.acc_handle, &dcmd->sgl.sge32[0].length,
6456 sizeof (struct mrsas_evt_detail));
6457
6458 instance->aen_seq_num = seq_num;
6459
6460
6461 /*
6462 * Store reference to the cmd used to register for AEN. When an
6463 * application wants us to register for AEN, we have to abort this
6464 * cmd and re-register with a new EVENT LOCALE supplied by that app
6465 */
6466 instance->aen_cmd = cmd;
6467
6468 cmd->frame_count = 1;
6469
6470 /* Issue the aen registration frame */
6471 /* atomic_add_16 (&instance->fw_outstanding, 1); */
6472 if (instance->tbolt) {
6473 mr_sas_tbolt_build_mfi_cmd(instance, cmd);
6474 }
6475 instance->func_ptr->issue_cmd(cmd, instance);
6476
6477 return (0);
6478 }
6479
6480 void
6481 display_scsi_inquiry(caddr_t scsi_inq)
6482 {
6483 #define MAX_SCSI_DEVICE_CODE 14
6484 int i;
6485 char inquiry_buf[256] = {0};
6486 int len;
6487 const char *const scsi_device_types[] = {
6488 "Direct-Access ",
6489 "Sequential-Access",
6490 "Printer ",
6491 "Processor ",
6492 "WORM ",
6493 "CD-ROM ",
6494 "Scanner ",
6495 "Optical Device ",
6496 "Medium Changer ",
6497 "Communications ",
6498 "Unknown ",
6499 "Unknown ",
6500 "Unknown ",
6501 "Enclosure ",
6502 };
6503
6504 len = 0;
6505
6506 len += snprintf(inquiry_buf + len, 265 - len, " Vendor: ");
6507 for (i = 8; i < 16; i++) {
6508 len += snprintf(inquiry_buf + len, 265 - len, "%c",
6509 scsi_inq[i]);
6510 }
6511
6512 len += snprintf(inquiry_buf + len, 265 - len, " Model: ");
6513
6514 for (i = 16; i < 32; i++) {
6515 len += snprintf(inquiry_buf + len, 265 - len, "%c",
6516 scsi_inq[i]);
6517 }
6518
6519 len += snprintf(inquiry_buf + len, 265 - len, " Rev: ");
6520
6521 for (i = 32; i < 36; i++) {
6522 len += snprintf(inquiry_buf + len, 265 - len, "%c",
6523 scsi_inq[i]);
6524 }
6525
6526 len += snprintf(inquiry_buf + len, 265 - len, "\n");
6527
6528
6529 i = scsi_inq[0] & 0x1f;
6530
6531
6532 len += snprintf(inquiry_buf + len, 265 - len, " Type: %s ",
6533 i < MAX_SCSI_DEVICE_CODE ? scsi_device_types[i] :
6534 "Unknown ");
6535
6536
6537 len += snprintf(inquiry_buf + len, 265 - len,
6538 " ANSI SCSI revision: %02x", scsi_inq[2] & 0x07);
6539
6540 if ((scsi_inq[2] & 0x07) == 1 && (scsi_inq[3] & 0x0f) == 1) {
6541 len += snprintf(inquiry_buf + len, 265 - len, " CCS\n");
6542 } else {
6543 len += snprintf(inquiry_buf + len, 265 - len, "\n");
6544 }
6545
6546 con_log(CL_DLEVEL2, (CE_CONT, inquiry_buf));
6547 }
6548
6549 static void
6550 io_timeout_checker(void *arg)
6551 {
6552 struct scsi_pkt *pkt;
6553 struct mrsas_instance *instance = arg;
6554 struct mrsas_cmd *cmd = NULL;
6555 struct mrsas_header *hdr;
6556 int time = 0;
6557 int counter = 0;
6558 struct mlist_head *pos, *next;
6559 mlist_t process_list;
6560
6561 if (instance->adapterresetinprogress == 1) {
6562 con_log(CL_ANN, (CE_NOTE, "io_timeout_checker:"
6563 " reset in progress"));
6564
6565 instance->timeout_id = timeout(io_timeout_checker,
6566 (void *) instance, drv_usectohz(MRSAS_1_SECOND));
6567 return;
6568 }
6569
6570 /* See if this check needs to be in the beginning or last in ISR */
6571 if (mrsas_initiate_ocr_if_fw_is_faulty(instance) == 1) {
6572 dev_err(instance->dip, CE_WARN, "io_timeout_checker: "
6573 "FW Fault, calling reset adapter");
6574 dev_err(instance->dip, CE_CONT, "io_timeout_checker: "
6575 "fw_outstanding 0x%X max_fw_cmds 0x%X",
6576 instance->fw_outstanding, instance->max_fw_cmds);
6577 if (instance->adapterresetinprogress == 0) {
6578 instance->adapterresetinprogress = 1;
6579 if (instance->tbolt)
6580 (void) mrsas_tbolt_reset_ppc(instance);
6581 else
6582 (void) mrsas_reset_ppc(instance);
6583 instance->adapterresetinprogress = 0;
6584 }
6585 instance->timeout_id = timeout(io_timeout_checker,
6586 (void *) instance, drv_usectohz(MRSAS_1_SECOND));
6587 return;
6588 }
6589
6590 INIT_LIST_HEAD(&process_list);
6591
6592 mutex_enter(&instance->cmd_pend_mtx);
6593 mlist_for_each_safe(pos, next, &instance->cmd_pend_list) {
6594 cmd = mlist_entry(pos, struct mrsas_cmd, list);
6595
6596 if (cmd == NULL) {
6597 continue;
6598 }
6599
6600 if (cmd->sync_cmd == MRSAS_TRUE) {
6601 hdr = (struct mrsas_header *)&cmd->frame->hdr;
6602 if (hdr == NULL) {
6603 continue;
6604 }
6605 time = --cmd->drv_pkt_time;
6606 } else {
6607 pkt = cmd->pkt;
6608 if (pkt == NULL) {
6609 continue;
6610 }
6611 time = --cmd->drv_pkt_time;
6612 }
6613 if (time <= 0) {
6614 dev_err(instance->dip, CE_WARN, "%llx: "
6615 "io_timeout_checker: TIMING OUT: pkt: %p, "
6616 "cmd %p fw_outstanding 0x%X max_fw_cmds 0x%X",
6617 gethrtime(), (void *)pkt, (void *)cmd,
6618 instance->fw_outstanding, instance->max_fw_cmds);
6619
6620 counter++;
6621 break;
6622 }
6623 }
6624 mutex_exit(&instance->cmd_pend_mtx);
6625
6626 if (counter) {
6627 if (instance->disable_online_ctrl_reset == 1) {
6628 dev_err(instance->dip, CE_WARN, "%s(): OCR is NOT "
6629 "supported by Firmware, KILL adapter!!!",
6630 __func__);
6631
6632 if (instance->tbolt)
6633 mrsas_tbolt_kill_adapter(instance);
6634 else
6635 (void) mrsas_kill_adapter(instance);
6636
6637 return;
6638 } else {
6639 if (cmd->retry_count_for_ocr <= IO_RETRY_COUNT) {
6640 if (instance->adapterresetinprogress == 0) {
6641 if (instance->tbolt) {
6642 (void) mrsas_tbolt_reset_ppc(
6643 instance);
6644 } else {
6645 (void) mrsas_reset_ppc(
6646 instance);
6647 }
6648 }
6649 } else {
6650 dev_err(instance->dip, CE_WARN,
6651 "io_timeout_checker: "
6652 "cmd %p cmd->index %d "
6653 "timed out even after 3 resets: "
6654 "so KILL adapter", (void *)cmd, cmd->index);
6655
6656 mrsas_print_cmd_details(instance, cmd, 0xDD);
6657
6658 if (instance->tbolt)
6659 mrsas_tbolt_kill_adapter(instance);
6660 else
6661 (void) mrsas_kill_adapter(instance);
6662 return;
6663 }
6664 }
6665 }
6666 con_log(CL_ANN, (CE_NOTE, "mrsas: "
6667 "schedule next timeout check: "
6668 "do timeout \n"));
6669 instance->timeout_id =
6670 timeout(io_timeout_checker, (void *)instance,
6671 drv_usectohz(MRSAS_1_SECOND));
6672 }
6673
6674 static uint32_t
6675 read_fw_status_reg_ppc(struct mrsas_instance *instance)
6676 {
6677 return ((uint32_t)RD_OB_SCRATCH_PAD_0(instance));
6678 }
6679
6680 static void
6681 issue_cmd_ppc(struct mrsas_cmd *cmd, struct mrsas_instance *instance)
6682 {
6683 struct scsi_pkt *pkt;
6684 atomic_inc_16(&instance->fw_outstanding);
6685
6686 pkt = cmd->pkt;
6687 if (pkt) {
6688 con_log(CL_DLEVEL1, (CE_NOTE, "%llx : issue_cmd_ppc:"
6689 "ISSUED CMD TO FW : called : cmd:"
6690 ": %p instance : %p pkt : %p pkt_time : %x\n",
6691 gethrtime(), (void *)cmd, (void *)instance,
6692 (void *)pkt, cmd->drv_pkt_time));
6693 if (instance->adapterresetinprogress) {
6694 cmd->drv_pkt_time = (uint16_t)debug_timeout_g;
6695 con_log(CL_ANN1, (CE_NOTE, "Reset the scsi_pkt timer"));
6696 } else {
6697 push_pending_mfi_pkt(instance, cmd);
6698 }
6699
6700 } else {
6701 con_log(CL_DLEVEL1, (CE_NOTE, "%llx : issue_cmd_ppc:"
6702 "ISSUED CMD TO FW : called : cmd : %p, instance: %p"
6703 "(NO PKT)\n", gethrtime(), (void *)cmd, (void *)instance));
6704 }
6705
6706 mutex_enter(&instance->reg_write_mtx);
6707 /* Issue the command to the FW */
6708 WR_IB_PICK_QPORT((cmd->frame_phys_addr) |
6709 (((cmd->frame_count - 1) << 1) | 1), instance);
6710 mutex_exit(&instance->reg_write_mtx);
6711
6712 }
6713
6714 /*
6715 * issue_cmd_in_sync_mode
6716 */
6717 static int
6718 issue_cmd_in_sync_mode_ppc(struct mrsas_instance *instance,
6719 struct mrsas_cmd *cmd)
6720 {
6721 int i;
6722 uint32_t msecs = MFI_POLL_TIMEOUT_SECS * MILLISEC;
6723 struct mrsas_header *hdr = &cmd->frame->hdr;
6724
6725 con_log(CL_ANN1, (CE_NOTE, "issue_cmd_in_sync_mode_ppc: called"));
6726
6727 if (instance->adapterresetinprogress) {
6728 cmd->drv_pkt_time = ddi_get16(
6729 cmd->frame_dma_obj.acc_handle, &hdr->timeout);
6730 if (cmd->drv_pkt_time < debug_timeout_g)
6731 cmd->drv_pkt_time = (uint16_t)debug_timeout_g;
6732
6733 con_log(CL_ANN1, (CE_NOTE, "sync_mode_ppc: "
6734 "issue and return in reset case\n"));
6735 WR_IB_PICK_QPORT((cmd->frame_phys_addr) |
6736 (((cmd->frame_count - 1) << 1) | 1), instance);
6737
6738 return (DDI_SUCCESS);
6739 } else {
6740 con_log(CL_ANN1, (CE_NOTE, "sync_mode_ppc: pushing the pkt\n"));
6741 push_pending_mfi_pkt(instance, cmd);
6742 }
6743
6744 cmd->cmd_status = ENODATA;
6745
6746 mutex_enter(&instance->reg_write_mtx);
6747 /* Issue the command to the FW */
6748 WR_IB_PICK_QPORT((cmd->frame_phys_addr) |
6749 (((cmd->frame_count - 1) << 1) | 1), instance);
6750 mutex_exit(&instance->reg_write_mtx);
6751
6752 mutex_enter(&instance->int_cmd_mtx);
6753 for (i = 0; i < msecs && (cmd->cmd_status == ENODATA); i++) {
6754 cv_wait(&instance->int_cmd_cv, &instance->int_cmd_mtx);
6755 }
6756 mutex_exit(&instance->int_cmd_mtx);
6757
6758 con_log(CL_ANN1, (CE_NOTE, "issue_cmd_in_sync_mode_ppc: done"));
6759
6760 if (i < (msecs -1)) {
6761 return (DDI_SUCCESS);
6762 } else {
6763 return (DDI_FAILURE);
6764 }
6765 }
6766
6767 /*
6768 * issue_cmd_in_poll_mode
6769 */
6770 static int
6771 issue_cmd_in_poll_mode_ppc(struct mrsas_instance *instance,
6772 struct mrsas_cmd *cmd)
6773 {
6774 int i;
6775 uint16_t flags;
6776 uint32_t msecs = MFI_POLL_TIMEOUT_SECS * MILLISEC;
6777 struct mrsas_header *frame_hdr;
6778
6779 con_log(CL_ANN1, (CE_NOTE, "issue_cmd_in_poll_mode_ppc: called"));
6780
6781 frame_hdr = (struct mrsas_header *)cmd->frame;
6782 ddi_put8(cmd->frame_dma_obj.acc_handle, &frame_hdr->cmd_status,
6783 MFI_CMD_STATUS_POLL_MODE);
6784 flags = ddi_get16(cmd->frame_dma_obj.acc_handle, &frame_hdr->flags);
6785 flags |= MFI_FRAME_DONT_POST_IN_REPLY_QUEUE;
6786
6787 ddi_put16(cmd->frame_dma_obj.acc_handle, &frame_hdr->flags, flags);
6788
6789 /* issue the frame using inbound queue port */
6790 WR_IB_PICK_QPORT((cmd->frame_phys_addr) |
6791 (((cmd->frame_count - 1) << 1) | 1), instance);
6792
6793 /* wait for cmd_status to change from 0xFF */
6794 for (i = 0; i < msecs && (
6795 ddi_get8(cmd->frame_dma_obj.acc_handle, &frame_hdr->cmd_status)
6796 == MFI_CMD_STATUS_POLL_MODE); i++) {
6797 drv_usecwait(MILLISEC); /* wait for 1000 usecs */
6798 }
6799
6800 if (ddi_get8(cmd->frame_dma_obj.acc_handle, &frame_hdr->cmd_status)
6801 == MFI_CMD_STATUS_POLL_MODE) {
6802 con_log(CL_ANN, (CE_NOTE, "issue_cmd_in_poll_mode: "
6803 "cmd polling timed out"));
6804 return (DDI_FAILURE);
6805 }
6806
6807 return (DDI_SUCCESS);
6808 }
6809
6810 static void
6811 enable_intr_ppc(struct mrsas_instance *instance)
6812 {
6813 uint32_t mask;
6814
6815 con_log(CL_ANN1, (CE_NOTE, "enable_intr_ppc: called"));
6816
6817 if (instance->skinny) {
6818 /* For SKINNY, write ~0x1, from BSD's mfi driver. */
6819 WR_OB_INTR_MASK(0xfffffffe, instance);
6820 } else {
6821 /* WR_OB_DOORBELL_CLEAR(0xFFFFFFFF, instance); */
6822 WR_OB_DOORBELL_CLEAR(OB_DOORBELL_CLEAR_MASK, instance);
6823
6824 /* WR_OB_INTR_MASK(~0x80000000, instance); */
6825 WR_OB_INTR_MASK(~(MFI_REPLY_2108_MESSAGE_INTR_MASK), instance);
6826 }
6827
6828 /* dummy read to force PCI flush */
6829 mask = RD_OB_INTR_MASK(instance);
6830
6831 con_log(CL_ANN1, (CE_NOTE, "enable_intr_ppc: "
6832 "outbound_intr_mask = 0x%x", mask));
6833 }
6834
6835 static void
6836 disable_intr_ppc(struct mrsas_instance *instance)
6837 {
6838 con_log(CL_ANN1, (CE_NOTE, "disable_intr_ppc: called"));
6839
6840 con_log(CL_ANN1, (CE_NOTE, "disable_intr_ppc: before : "
6841 "outbound_intr_mask = 0x%x", RD_OB_INTR_MASK(instance)));
6842
6843 /* For now, assume there are no extras needed for Skinny support. */
6844
6845 WR_OB_INTR_MASK(OB_INTR_MASK, instance);
6846
6847 con_log(CL_ANN1, (CE_NOTE, "disable_intr_ppc: after : "
6848 "outbound_intr_mask = 0x%x", RD_OB_INTR_MASK(instance)));
6849
6850 /* dummy read to force PCI flush */
6851 (void) RD_OB_INTR_MASK(instance);
6852 }
6853
6854 static int
6855 intr_ack_ppc(struct mrsas_instance *instance)
6856 {
6857 uint32_t status;
6858 int ret = DDI_INTR_CLAIMED;
6859
6860 con_log(CL_ANN1, (CE_NOTE, "intr_ack_ppc: called"));
6861
6862 /* check if it is our interrupt */
6863 status = RD_OB_INTR_STATUS(instance);
6864
6865 con_log(CL_ANN1, (CE_NOTE, "intr_ack_ppc: status = 0x%x", status));
6866
6867 /*
6868 * NOTE: Some drivers call out SKINNY here, but the return is the same
6869 * for SKINNY and 2108.
6870 */
6871 if (!(status & MFI_REPLY_2108_MESSAGE_INTR)) {
6872 ret = DDI_INTR_UNCLAIMED;
6873 }
6874
6875 if (mrsas_check_acc_handle(instance->regmap_handle) != DDI_SUCCESS) {
6876 ddi_fm_service_impact(instance->dip, DDI_SERVICE_LOST);
6877 ret = DDI_INTR_UNCLAIMED;
6878 }
6879
6880 if (ret == DDI_INTR_UNCLAIMED) {
6881 return (ret);
6882 }
6883
6884 /*
6885 * Clear the interrupt by writing back the same value.
6886 * Another case where SKINNY is slightly different.
6887 */
6888 if (instance->skinny) {
6889 WR_OB_INTR_STATUS(status, instance);
6890 } else {
6891 WR_OB_DOORBELL_CLEAR(status, instance);
6892 }
6893
6894 /* dummy READ */
6895 status = RD_OB_INTR_STATUS(instance);
6896
6897 con_log(CL_ANN1, (CE_NOTE, "intr_ack_ppc: interrupt cleared"));
6898
6899 return (ret);
6900 }
6901
6902 /*
6903 * Marks HBA as bad. This will be called either when an
6904 * IO packet times out even after 3 FW resets
6905 * or FW is found to be fault even after 3 continuous resets.
6906 */
6907
6908 static int
6909 mrsas_kill_adapter(struct mrsas_instance *instance)
6910 {
6911 if (instance->deadadapter == 1)
6912 return (DDI_FAILURE);
6913
6914 con_log(CL_ANN1, (CE_NOTE, "mrsas_kill_adapter: "
6915 "Writing to doorbell with MFI_STOP_ADP "));
6916 mutex_enter(&instance->ocr_flags_mtx);
6917 instance->deadadapter = 1;
6918 mutex_exit(&instance->ocr_flags_mtx);
6919 instance->func_ptr->disable_intr(instance);
6920 WR_IB_DOORBELL(MFI_STOP_ADP, instance);
6921 (void) mrsas_complete_pending_cmds(instance);
6922 return (DDI_SUCCESS);
6923 }
6924
6925
6926 static int
6927 mrsas_reset_ppc(struct mrsas_instance *instance)
6928 {
6929 uint32_t status;
6930 uint32_t retry = 0;
6931 uint32_t cur_abs_reg_val;
6932 uint32_t fw_state;
6933
6934 con_log(CL_ANN, (CE_NOTE, "chkpnt:%s:%d", __func__, __LINE__));
6935
6936 if (instance->deadadapter == 1) {
6937 dev_err(instance->dip, CE_WARN, "mrsas_reset_ppc: "
6938 "no more resets as HBA has been marked dead ");
6939 return (DDI_FAILURE);
6940 }
6941 mutex_enter(&instance->ocr_flags_mtx);
6942 instance->adapterresetinprogress = 1;
6943 mutex_exit(&instance->ocr_flags_mtx);
6944 con_log(CL_ANN1, (CE_NOTE, "mrsas_reset_ppc: adpterresetinprogress "
6945 "flag set, time %llx", gethrtime()));
6946
6947 instance->func_ptr->disable_intr(instance);
6948 retry_reset:
6949 WR_IB_WRITE_SEQ(0, instance);
6950 WR_IB_WRITE_SEQ(4, instance);
6951 WR_IB_WRITE_SEQ(0xb, instance);
6952 WR_IB_WRITE_SEQ(2, instance);
6953 WR_IB_WRITE_SEQ(7, instance);
6954 WR_IB_WRITE_SEQ(0xd, instance);
6955 con_log(CL_ANN1, (CE_NOTE, "mrsas_reset_ppc: magic number written "
6956 "to write sequence register\n"));
6957 delay(100 * drv_usectohz(MILLISEC));
6958 status = RD_OB_DRWE(instance);
6959
6960 while (!(status & DIAG_WRITE_ENABLE)) {
6961 delay(100 * drv_usectohz(MILLISEC));
6962 status = RD_OB_DRWE(instance);
6963 if (retry++ == 100) {
6964 dev_err(instance->dip, CE_WARN,
6965 "mrsas_reset_ppc: DRWE bit "
6966 "check retry count %d", retry);
6967 return (DDI_FAILURE);
6968 }
6969 }
6970 WR_IB_DRWE(status | DIAG_RESET_ADAPTER, instance);
6971 delay(100 * drv_usectohz(MILLISEC));
6972 status = RD_OB_DRWE(instance);
6973 while (status & DIAG_RESET_ADAPTER) {
6974 delay(100 * drv_usectohz(MILLISEC));
6975 status = RD_OB_DRWE(instance);
6976 if (retry++ == 100) {
6977 dev_err(instance->dip, CE_WARN, "mrsas_reset_ppc: "
6978 "RESET FAILED. KILL adapter called.");
6979
6980 (void) mrsas_kill_adapter(instance);
6981 return (DDI_FAILURE);
6982 }
6983 }
6984 con_log(CL_ANN, (CE_NOTE, "mrsas_reset_ppc: Adapter reset complete"));
6985 con_log(CL_ANN1, (CE_NOTE, "mrsas_reset_ppc: "
6986 "Calling mfi_state_transition_to_ready"));
6987
6988 /* Mark HBA as bad, if FW is fault after 3 continuous resets */
6989 if (mfi_state_transition_to_ready(instance) ||
6990 debug_fw_faults_after_ocr_g == 1) {
6991 cur_abs_reg_val =
6992 instance->func_ptr->read_fw_status_reg(instance);
6993 fw_state = cur_abs_reg_val & MFI_STATE_MASK;
6994
6995 #ifdef OCRDEBUG
6996 con_log(CL_ANN1, (CE_NOTE,
6997 "mrsas_reset_ppc :before fake: FW is not ready "
6998 "FW state = 0x%x", fw_state));
6999 if (debug_fw_faults_after_ocr_g == 1)
7000 fw_state = MFI_STATE_FAULT;
7001 #endif
7002
7003 con_log(CL_ANN1, (CE_NOTE, "mrsas_reset_ppc : FW is not ready "
7004 "FW state = 0x%x", fw_state));
7005
7006 if (fw_state == MFI_STATE_FAULT) {
7007 /* increment the count */
7008 instance->fw_fault_count_after_ocr++;
7009 if (instance->fw_fault_count_after_ocr
7010 < MAX_FW_RESET_COUNT) {
7011 dev_err(instance->dip, CE_WARN,
7012 "mrsas_reset_ppc: "
7013 "FW is in fault after OCR count %d "
7014 "Retry Reset",
7015 instance->fw_fault_count_after_ocr);
7016 goto retry_reset;
7017
7018 } else {
7019 dev_err(instance->dip, CE_WARN,
7020 "mrsas_reset_ppc: "
7021 "Max Reset Count exceeded >%d"
7022 "Mark HBA as bad, KILL adapter",
7023 MAX_FW_RESET_COUNT);
7024
7025 (void) mrsas_kill_adapter(instance);
7026 return (DDI_FAILURE);
7027 }
7028 }
7029 }
7030 /* reset the counter as FW is up after OCR */
7031 instance->fw_fault_count_after_ocr = 0;
7032
7033
7034 ddi_put32(instance->mfi_internal_dma_obj.acc_handle,
7035 instance->producer, 0);
7036
7037 ddi_put32(instance->mfi_internal_dma_obj.acc_handle,
7038 instance->consumer, 0);
7039
7040 con_log(CL_ANN1, (CE_NOTE, "mrsas_reset_ppc: "
7041 " after resetting produconsumer chck indexs:"
7042 "producer %x consumer %x", *instance->producer,
7043 *instance->consumer));
7044
7045 con_log(CL_ANN1, (CE_NOTE, "mrsas_reset_ppc: "
7046 "Calling mrsas_issue_init_mfi"));
7047 (void) mrsas_issue_init_mfi(instance);
7048 con_log(CL_ANN1, (CE_NOTE, "mrsas_reset_ppc: "
7049 "mrsas_issue_init_mfi Done"));
7050
7051 con_log(CL_ANN1, (CE_NOTE, "mrsas_reset_ppc: "
7052 "Calling mrsas_print_pending_cmd\n"));
7053 (void) mrsas_print_pending_cmds(instance);
7054 con_log(CL_ANN1, (CE_NOTE, "mrsas_reset_ppc: "
7055 "mrsas_print_pending_cmd done\n"));
7056
7057 instance->func_ptr->enable_intr(instance);
7058 instance->fw_outstanding = 0;
7059
7060 con_log(CL_ANN1, (CE_NOTE, "mrsas_reset_ppc: "
7061 "Calling mrsas_issue_pending_cmds"));
7062 (void) mrsas_issue_pending_cmds(instance);
7063 con_log(CL_ANN1, (CE_NOTE, "mrsas_reset_ppc: "
7064 "issue_pending_cmds done.\n"));
7065
7066 con_log(CL_ANN1, (CE_NOTE, "mrsas_reset_ppc: "
7067 "Calling aen registration"));
7068
7069
7070 instance->aen_cmd->retry_count_for_ocr = 0;
7071 instance->aen_cmd->drv_pkt_time = 0;
7072
7073 instance->func_ptr->issue_cmd(instance->aen_cmd, instance);
7074 con_log(CL_ANN1, (CE_NOTE, "Unsetting adpresetinprogress flag.\n"));
7075
7076 mutex_enter(&instance->ocr_flags_mtx);
7077 instance->adapterresetinprogress = 0;
7078 mutex_exit(&instance->ocr_flags_mtx);
7079 con_log(CL_ANN1, (CE_NOTE, "mrsas_reset_ppc: "
7080 "adpterresetinprogress flag unset"));
7081
7082 con_log(CL_ANN1, (CE_NOTE, "mrsas_reset_ppc done\n"));
7083 return (DDI_SUCCESS);
7084 }
7085
7086 /*
7087 * FMA functions.
7088 */
7089 int
7090 mrsas_common_check(struct mrsas_instance *instance, struct mrsas_cmd *cmd)
7091 {
7092 int ret = DDI_SUCCESS;
7093
7094 if (cmd != NULL &&
7095 mrsas_check_dma_handle(cmd->frame_dma_obj.dma_handle) !=
7096 DDI_SUCCESS) {
7097 ddi_fm_service_impact(instance->dip, DDI_SERVICE_UNAFFECTED);
7098 if (cmd->pkt != NULL) {
7099 cmd->pkt->pkt_reason = CMD_TRAN_ERR;
7100 cmd->pkt->pkt_statistics = 0;
7101 }
7102 ret = DDI_FAILURE;
7103 }
7104 if (mrsas_check_dma_handle(instance->mfi_internal_dma_obj.dma_handle)
7105 != DDI_SUCCESS) {
7106 ddi_fm_service_impact(instance->dip, DDI_SERVICE_UNAFFECTED);
7107 if (cmd != NULL && cmd->pkt != NULL) {
7108 cmd->pkt->pkt_reason = CMD_TRAN_ERR;
7109 cmd->pkt->pkt_statistics = 0;
7110 }
7111 ret = DDI_FAILURE;
7112 }
7113 if (mrsas_check_dma_handle(instance->mfi_evt_detail_obj.dma_handle) !=
7114 DDI_SUCCESS) {
7115 ddi_fm_service_impact(instance->dip, DDI_SERVICE_UNAFFECTED);
7116 if (cmd != NULL && cmd->pkt != NULL) {
7117 cmd->pkt->pkt_reason = CMD_TRAN_ERR;
7118 cmd->pkt->pkt_statistics = 0;
7119 }
7120 ret = DDI_FAILURE;
7121 }
7122 if (mrsas_check_acc_handle(instance->regmap_handle) != DDI_SUCCESS) {
7123 ddi_fm_service_impact(instance->dip, DDI_SERVICE_UNAFFECTED);
7124
7125 ddi_fm_acc_err_clear(instance->regmap_handle, DDI_FME_VER0);
7126
7127 if (cmd != NULL && cmd->pkt != NULL) {
7128 cmd->pkt->pkt_reason = CMD_TRAN_ERR;
7129 cmd->pkt->pkt_statistics = 0;
7130 }
7131 ret = DDI_FAILURE;
7132 }
7133
7134 return (ret);
7135 }
7136
7137 /*ARGSUSED*/
7138 static int
7139 mrsas_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, const void *impl_data)
7140 {
7141 /*
7142 * as the driver can always deal with an error in any dma or
7143 * access handle, we can just return the fme_status value.
7144 */
7145 pci_ereport_post(dip, err, NULL);
7146 return (err->fme_status);
7147 }
7148
7149 static void
7150 mrsas_fm_init(struct mrsas_instance *instance)
7151 {
7152 /* Need to change iblock to priority for new MSI intr */
7153 ddi_iblock_cookie_t fm_ibc;
7154
7155 /* Only register with IO Fault Services if we have some capability */
7156 if (instance->fm_capabilities) {
7157 /* Adjust access and dma attributes for FMA */
7158 endian_attr.devacc_attr_access = DDI_FLAGERR_ACC;
7159 mrsas_generic_dma_attr.dma_attr_flags = DDI_DMA_FLAGERR;
7160
7161 /*
7162 * Register capabilities with IO Fault Services.
7163 * fm_capabilities will be updated to indicate
7164 * capabilities actually supported (not requested.)
7165 */
7166
7167 ddi_fm_init(instance->dip, &instance->fm_capabilities, &fm_ibc);
7168
7169 /*
7170 * Initialize pci ereport capabilities if ereport
7171 * capable (should always be.)
7172 */
7173
7174 if (DDI_FM_EREPORT_CAP(instance->fm_capabilities) ||
7175 DDI_FM_ERRCB_CAP(instance->fm_capabilities)) {
7176 pci_ereport_setup(instance->dip);
7177 }
7178
7179 /*
7180 * Register error callback if error callback capable.
7181 */
7182 if (DDI_FM_ERRCB_CAP(instance->fm_capabilities)) {
7183 ddi_fm_handler_register(instance->dip,
7184 mrsas_fm_error_cb, (void*) instance);
7185 }
7186 } else {
7187 endian_attr.devacc_attr_access = DDI_DEFAULT_ACC;
7188 mrsas_generic_dma_attr.dma_attr_flags = 0;
7189 }
7190 }
7191
7192 static void
7193 mrsas_fm_fini(struct mrsas_instance *instance)
7194 {
7195 /* Only unregister FMA capabilities if registered */
7196 if (instance->fm_capabilities) {
7197 /*
7198 * Un-register error callback if error callback capable.
7199 */
7200 if (DDI_FM_ERRCB_CAP(instance->fm_capabilities)) {
7201 ddi_fm_handler_unregister(instance->dip);
7202 }
7203
7204 /*
7205 * Release any resources allocated by pci_ereport_setup()
7206 */
7207 if (DDI_FM_EREPORT_CAP(instance->fm_capabilities) ||
7208 DDI_FM_ERRCB_CAP(instance->fm_capabilities)) {
7209 pci_ereport_teardown(instance->dip);
7210 }
7211
7212 /* Unregister from IO Fault Services */
7213 ddi_fm_fini(instance->dip);
7214
7215 /* Adjust access and dma attributes for FMA */
7216 endian_attr.devacc_attr_access = DDI_DEFAULT_ACC;
7217 mrsas_generic_dma_attr.dma_attr_flags = 0;
7218 }
7219 }
7220
7221 int
7222 mrsas_check_acc_handle(ddi_acc_handle_t handle)
7223 {
7224 ddi_fm_error_t de;
7225
7226 if (handle == NULL) {
7227 return (DDI_FAILURE);
7228 }
7229
7230 ddi_fm_acc_err_get(handle, &de, DDI_FME_VERSION);
7231
7232 return (de.fme_status);
7233 }
7234
7235 int
7236 mrsas_check_dma_handle(ddi_dma_handle_t handle)
7237 {
7238 ddi_fm_error_t de;
7239
7240 if (handle == NULL) {
7241 return (DDI_FAILURE);
7242 }
7243
7244 ddi_fm_dma_err_get(handle, &de, DDI_FME_VERSION);
7245
7246 return (de.fme_status);
7247 }
7248
7249 void
7250 mrsas_fm_ereport(struct mrsas_instance *instance, char *detail)
7251 {
7252 uint64_t ena;
7253 char buf[FM_MAX_CLASS];
7254
7255 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", DDI_FM_DEVICE, detail);
7256 ena = fm_ena_generate(0, FM_ENA_FMT1);
7257 if (DDI_FM_EREPORT_CAP(instance->fm_capabilities)) {
7258 ddi_fm_ereport_post(instance->dip, buf, ena, DDI_NOSLEEP,
7259 FM_VERSION, DATA_TYPE_UINT8, FM_EREPORT_VERSION, NULL);
7260 }
7261 }
7262
7263 static int
7264 mrsas_add_intrs(struct mrsas_instance *instance, int intr_type)
7265 {
7266
7267 dev_info_t *dip = instance->dip;
7268 int avail, actual, count;
7269 int i, flag, ret;
7270
7271 con_log(CL_DLEVEL1, (CE_NOTE, "mrsas_add_intrs: intr_type = %x",
7272 intr_type));
7273
7274 /* Get number of interrupts */
7275 ret = ddi_intr_get_nintrs(dip, intr_type, &count);
7276 if ((ret != DDI_SUCCESS) || (count == 0)) {
7277 con_log(CL_ANN, (CE_WARN, "ddi_intr_get_nintrs() failed:"
7278 "ret %d count %d", ret, count));
7279
7280 return (DDI_FAILURE);
7281 }
7282
7283 con_log(CL_DLEVEL1, (CE_NOTE, "mrsas_add_intrs: count = %d ", count));
7284
7285 /* Get number of available interrupts */
7286 ret = ddi_intr_get_navail(dip, intr_type, &avail);
7287 if ((ret != DDI_SUCCESS) || (avail == 0)) {
7288 con_log(CL_ANN, (CE_WARN, "ddi_intr_get_navail() failed:"
7289 "ret %d avail %d", ret, avail));
7290
7291 return (DDI_FAILURE);
7292 }
7293 con_log(CL_DLEVEL1, (CE_NOTE, "mrsas_add_intrs: avail = %d ", avail));
7294
7295 /* Only one interrupt routine. So limit the count to 1 */
7296 if (count > 1) {
7297 count = 1;
7298 }
7299
7300 /*
7301 * Allocate an array of interrupt handlers. Currently we support
7302 * only one interrupt. The framework can be extended later.
7303 */
7304 instance->intr_htable_size = count * sizeof (ddi_intr_handle_t);
7305 instance->intr_htable = kmem_zalloc(instance->intr_htable_size,
7306 KM_SLEEP);
7307 ASSERT(instance->intr_htable);
7308
7309 flag = ((intr_type == DDI_INTR_TYPE_MSI) ||
7310 (intr_type == DDI_INTR_TYPE_MSIX)) ?
7311 DDI_INTR_ALLOC_STRICT : DDI_INTR_ALLOC_NORMAL;
7312
7313 /* Allocate interrupt */
7314 ret = ddi_intr_alloc(dip, instance->intr_htable, intr_type, 0,
7315 count, &actual, flag);
7316
7317 if ((ret != DDI_SUCCESS) || (actual == 0)) {
7318 con_log(CL_ANN, (CE_WARN, "mrsas_add_intrs: "
7319 "avail = %d", avail));
7320 goto mrsas_free_htable;
7321 }
7322
7323 if (actual < count) {
7324 con_log(CL_ANN, (CE_WARN, "mrsas_add_intrs: "
7325 "Requested = %d Received = %d", count, actual));
7326 }
7327 instance->intr_cnt = actual;
7328
7329 /*
7330 * Get the priority of the interrupt allocated.
7331 */
7332 if ((ret = ddi_intr_get_pri(instance->intr_htable[0],
7333 &instance->intr_pri)) != DDI_SUCCESS) {
7334 con_log(CL_ANN, (CE_WARN, "mrsas_add_intrs: "
7335 "get priority call failed"));
7336 goto mrsas_free_handles;
7337 }
7338
7339 /*
7340 * Test for high level mutex. we don't support them.
7341 */
7342 if (instance->intr_pri >= ddi_intr_get_hilevel_pri()) {
7343 con_log(CL_ANN, (CE_WARN, "mrsas_add_intrs: "
7344 "High level interrupts not supported."));
7345 goto mrsas_free_handles;
7346 }
7347
7348 con_log(CL_DLEVEL1, (CE_NOTE, "mrsas_add_intrs: intr_pri = 0x%x ",
7349 instance->intr_pri));
7350
7351 /* Call ddi_intr_add_handler() */
7352 for (i = 0; i < actual; i++) {
7353 ret = ddi_intr_add_handler(instance->intr_htable[i],
7354 (ddi_intr_handler_t *)mrsas_isr, (caddr_t)instance,
7355 (caddr_t)(uintptr_t)i);
7356
7357 if (ret != DDI_SUCCESS) {
7358 con_log(CL_ANN, (CE_WARN, "mrsas_add_intrs:"
7359 "failed %d", ret));
7360 goto mrsas_free_handles;
7361 }
7362
7363 }
7364
7365 con_log(CL_DLEVEL1, (CE_NOTE, " ddi_intr_add_handler done"));
7366
7367 if ((ret = ddi_intr_get_cap(instance->intr_htable[0],
7368 &instance->intr_cap)) != DDI_SUCCESS) {
7369 con_log(CL_ANN, (CE_WARN, "ddi_intr_get_cap() failed %d",
7370 ret));
7371 goto mrsas_free_handlers;
7372 }
7373
7374 if (instance->intr_cap & DDI_INTR_FLAG_BLOCK) {
7375 con_log(CL_ANN, (CE_WARN, "Calling ddi_intr_block _enable"));
7376
7377 (void) ddi_intr_block_enable(instance->intr_htable,
7378 instance->intr_cnt);
7379 } else {
7380 con_log(CL_ANN, (CE_NOTE, " calling ddi_intr_enable"));
7381
7382 for (i = 0; i < instance->intr_cnt; i++) {
7383 (void) ddi_intr_enable(instance->intr_htable[i]);
7384 con_log(CL_ANN, (CE_NOTE, "ddi intr enable returns "
7385 "%d", i));
7386 }
7387 }
7388
7389 return (DDI_SUCCESS);
7390
7391 mrsas_free_handlers:
7392 for (i = 0; i < actual; i++)
7393 (void) ddi_intr_remove_handler(instance->intr_htable[i]);
7394
7395 mrsas_free_handles:
7396 for (i = 0; i < actual; i++)
7397 (void) ddi_intr_free(instance->intr_htable[i]);
7398
7399 mrsas_free_htable:
7400 if (instance->intr_htable != NULL)
7401 kmem_free(instance->intr_htable, instance->intr_htable_size);
7402
7403 instance->intr_htable = NULL;
7404 instance->intr_htable_size = 0;
7405
7406 return (DDI_FAILURE);
7407
7408 }
7409
7410
7411 static void
7412 mrsas_rem_intrs(struct mrsas_instance *instance)
7413 {
7414 int i;
7415
7416 con_log(CL_ANN, (CE_NOTE, "mrsas_rem_intrs called"));
7417
7418 /* Disable all interrupts first */
7419 if (instance->intr_cap & DDI_INTR_FLAG_BLOCK) {
7420 (void) ddi_intr_block_disable(instance->intr_htable,
7421 instance->intr_cnt);
7422 } else {
7423 for (i = 0; i < instance->intr_cnt; i++) {
7424 (void) ddi_intr_disable(instance->intr_htable[i]);
7425 }
7426 }
7427
7428 /* Remove all the handlers */
7429
7430 for (i = 0; i < instance->intr_cnt; i++) {
7431 (void) ddi_intr_remove_handler(instance->intr_htable[i]);
7432 (void) ddi_intr_free(instance->intr_htable[i]);
7433 }
7434
7435 if (instance->intr_htable != NULL)
7436 kmem_free(instance->intr_htable, instance->intr_htable_size);
7437
7438 instance->intr_htable = NULL;
7439 instance->intr_htable_size = 0;
7440
7441 }
7442
7443 static int
7444 mrsas_tran_bus_config(dev_info_t *parent, uint_t flags,
7445 ddi_bus_config_op_t op, void *arg, dev_info_t **childp)
7446 {
7447 struct mrsas_instance *instance;
7448 int config;
7449 int rval = NDI_SUCCESS;
7450
7451 char *ptr = NULL;
7452 int tgt, lun;
7453
7454 con_log(CL_ANN1, (CE_NOTE, "Bus config called for op = %x", op));
7455
7456 if ((instance = ddi_get_soft_state(mrsas_state,
7457 ddi_get_instance(parent))) == NULL) {
7458 return (NDI_FAILURE);
7459 }
7460
7461 /* Hold nexus during bus_config */
7462 ndi_devi_enter(parent, &config);
7463 switch (op) {
7464 case BUS_CONFIG_ONE: {
7465
7466 /* parse wwid/target name out of name given */
7467 if ((ptr = strchr((char *)arg, '@')) == NULL) {
7468 rval = NDI_FAILURE;
7469 break;
7470 }
7471 ptr++;
7472
7473 if (mrsas_parse_devname(arg, &tgt, &lun) != 0) {
7474 rval = NDI_FAILURE;
7475 break;
7476 }
7477
7478 if (lun == 0) {
7479 rval = mrsas_config_ld(instance, tgt, lun, childp);
7480 } else if ((instance->tbolt || instance->skinny) && lun != 0) {
7481 rval = mrsas_tbolt_config_pd(instance,
7482 tgt, lun, childp);
7483 } else {
7484 rval = NDI_FAILURE;
7485 }
7486
7487 break;
7488 }
7489 case BUS_CONFIG_DRIVER:
7490 case BUS_CONFIG_ALL: {
7491
7492 rval = mrsas_config_all_devices(instance);
7493
7494 rval = NDI_SUCCESS;
7495 break;
7496 }
7497 }
7498
7499 if (rval == NDI_SUCCESS) {
7500 rval = ndi_busop_bus_config(parent, flags, op, arg, childp, 0);
7501
7502 }
7503 ndi_devi_exit(parent, config);
7504
7505 con_log(CL_ANN1, (CE_NOTE, "mrsas_tran_bus_config: rval = %x",
7506 rval));
7507 return (rval);
7508 }
7509
7510 static int
7511 mrsas_config_all_devices(struct mrsas_instance *instance)
7512 {
7513 int rval, tgt;
7514
7515 for (tgt = 0; tgt < MRDRV_MAX_LD; tgt++) {
7516 (void) mrsas_config_ld(instance, tgt, 0, NULL);
7517
7518 }
7519
7520 /* Config PD devices connected to the card */
7521 if (instance->tbolt || instance->skinny) {
7522 for (tgt = 0; tgt < instance->mr_tbolt_pd_max; tgt++) {
7523 (void) mrsas_tbolt_config_pd(instance, tgt, 1, NULL);
7524 }
7525 }
7526
7527 rval = NDI_SUCCESS;
7528 return (rval);
7529 }
7530
7531 static int
7532 mrsas_parse_devname(char *devnm, int *tgt, int *lun)
7533 {
7534 char devbuf[SCSI_MAXNAMELEN];
7535 char *addr;
7536 char *p, *tp, *lp;
7537 long num;
7538
7539 /* Parse dev name and address */
7540 (void) strcpy(devbuf, devnm);
7541 addr = "";
7542 for (p = devbuf; *p != '\0'; p++) {
7543 if (*p == '@') {
7544 addr = p + 1;
7545 *p = '\0';
7546 } else if (*p == ':') {
7547 *p = '\0';
7548 break;
7549 }
7550 }
7551
7552 /* Parse target and lun */
7553 for (p = tp = addr, lp = NULL; *p != '\0'; p++) {
7554 if (*p == ',') {
7555 lp = p + 1;
7556 *p = '\0';
7557 break;
7558 }
7559 }
7560 if (tgt && tp) {
7561 if (ddi_strtol(tp, NULL, 0x10, &num)) {
7562 return (DDI_FAILURE); /* Can declare this as constant */
7563 }
7564 *tgt = (int)num;
7565 }
7566 if (lun && lp) {
7567 if (ddi_strtol(lp, NULL, 0x10, &num)) {
7568 return (DDI_FAILURE);
7569 }
7570 *lun = (int)num;
7571 }
7572 return (DDI_SUCCESS); /* Success case */
7573 }
7574
7575 static int
7576 mrsas_config_ld(struct mrsas_instance *instance, uint16_t tgt,
7577 uint8_t lun, dev_info_t **ldip)
7578 {
7579 struct scsi_device *sd;
7580 dev_info_t *child;
7581 int rval;
7582
7583 con_log(CL_DLEVEL1, (CE_NOTE, "mrsas_config_ld: t = %d l = %d",
7584 tgt, lun));
7585
7586 if ((child = mrsas_find_child(instance, tgt, lun)) != NULL) {
7587 if (ldip) {
7588 *ldip = child;
7589 }
7590 if (instance->mr_ld_list[tgt].flag != MRDRV_TGT_VALID) {
7591 rval = mrsas_service_evt(instance, tgt, 0,
7592 MRSAS_EVT_UNCONFIG_TGT, NULL);
7593 con_log(CL_ANN1, (CE_WARN,
7594 "mr_sas: DELETING STALE ENTRY rval = %d "
7595 "tgt id = %d ", rval, tgt));
7596 return (NDI_FAILURE);
7597 }
7598 return (NDI_SUCCESS);
7599 }
7600
7601 sd = kmem_zalloc(sizeof (struct scsi_device), KM_SLEEP);
7602 sd->sd_address.a_hba_tran = instance->tran;
7603 sd->sd_address.a_target = (uint16_t)tgt;
7604 sd->sd_address.a_lun = (uint8_t)lun;
7605
7606 if (scsi_hba_probe(sd, NULL) == SCSIPROBE_EXISTS)
7607 rval = mrsas_config_scsi_device(instance, sd, ldip);
7608 else
7609 rval = NDI_FAILURE;
7610
7611 /* sd_unprobe is blank now. Free buffer manually */
7612 if (sd->sd_inq) {
7613 kmem_free(sd->sd_inq, SUN_INQSIZE);
7614 sd->sd_inq = (struct scsi_inquiry *)NULL;
7615 }
7616
7617 kmem_free(sd, sizeof (struct scsi_device));
7618 con_log(CL_DLEVEL1, (CE_NOTE, "mrsas_config_ld: return rval = %d",
7619 rval));
7620 return (rval);
7621 }
7622
7623 int
7624 mrsas_config_scsi_device(struct mrsas_instance *instance,
7625 struct scsi_device *sd, dev_info_t **dipp)
7626 {
7627 char *nodename = NULL;
7628 char **compatible = NULL;
7629 int ncompatible = 0;
7630 char *childname;
7631 dev_info_t *ldip = NULL;
7632 int tgt = sd->sd_address.a_target;
7633 int lun = sd->sd_address.a_lun;
7634 int dtype = sd->sd_inq->inq_dtype & DTYPE_MASK;
7635 int rval;
7636
7637 con_log(CL_DLEVEL1, (CE_NOTE, "mr_sas: scsi_device t%dL%d", tgt, lun));
7638 scsi_hba_nodename_compatible_get(sd->sd_inq, NULL, dtype,
7639 NULL, &nodename, &compatible, &ncompatible);
7640
7641 if (nodename == NULL) {
7642 con_log(CL_ANN1, (CE_WARN, "mr_sas: Found no compatible driver "
7643 "for t%dL%d", tgt, lun));
7644 rval = NDI_FAILURE;
7645 goto finish;
7646 }
7647
7648 childname = (dtype == DTYPE_DIRECT) ? "sd" : nodename;
7649 con_log(CL_DLEVEL1, (CE_NOTE,
7650 "mr_sas: Childname = %2s nodename = %s", childname, nodename));
7651
7652 /* Create a dev node */
7653 rval = ndi_devi_alloc(instance->dip, childname, DEVI_SID_NODEID, &ldip);
7654 con_log(CL_DLEVEL1, (CE_NOTE,
7655 "mr_sas_config_scsi_device: ndi_devi_alloc rval = %x", rval));
7656 if (rval == NDI_SUCCESS) {
7657 if (ndi_prop_update_int(DDI_DEV_T_NONE, ldip, "target", tgt) !=
7658 DDI_PROP_SUCCESS) {
7659 con_log(CL_ANN1, (CE_WARN, "mr_sas: unable to create "
7660 "property for t%dl%d target", tgt, lun));
7661 rval = NDI_FAILURE;
7662 goto finish;
7663 }
7664 if (ndi_prop_update_int(DDI_DEV_T_NONE, ldip, "lun", lun) !=
7665 DDI_PROP_SUCCESS) {
7666 con_log(CL_ANN1, (CE_WARN, "mr_sas: unable to create "
7667 "property for t%dl%d lun", tgt, lun));
7668 rval = NDI_FAILURE;
7669 goto finish;
7670 }
7671
7672 if (ndi_prop_update_string_array(DDI_DEV_T_NONE, ldip,
7673 "compatible", compatible, ncompatible) !=
7674 DDI_PROP_SUCCESS) {
7675 con_log(CL_ANN1, (CE_WARN, "mr_sas: unable to create "
7676 "property for t%dl%d compatible", tgt, lun));
7677 rval = NDI_FAILURE;
7678 goto finish;
7679 }
7680
7681 rval = ndi_devi_online(ldip, NDI_ONLINE_ATTACH);
7682 if (rval != NDI_SUCCESS) {
7683 con_log(CL_ANN1, (CE_WARN, "mr_sas: unable to online "
7684 "t%dl%d", tgt, lun));
7685 ndi_prop_remove_all(ldip);
7686 (void) ndi_devi_free(ldip);
7687 } else {
7688 con_log(CL_ANN1, (CE_CONT, "mr_sas: online Done :"
7689 "0 t%dl%d", tgt, lun));
7690 }
7691
7692 }
7693 finish:
7694 if (dipp) {
7695 *dipp = ldip;
7696 }
7697
7698 con_log(CL_DLEVEL1, (CE_NOTE,
7699 "mr_sas: config_scsi_device rval = %d t%dL%d",
7700 rval, tgt, lun));
7701 scsi_hba_nodename_compatible_free(nodename, compatible);
7702 return (rval);
7703 }
7704
7705 /*ARGSUSED*/
7706 int
7707 mrsas_service_evt(struct mrsas_instance *instance, int tgt, int lun, int event,
7708 uint64_t wwn)
7709 {
7710 struct mrsas_eventinfo *mrevt = NULL;
7711
7712 con_log(CL_ANN1, (CE_NOTE,
7713 "mrsas_service_evt called for t%dl%d event = %d",
7714 tgt, lun, event));
7715
7716 if ((instance->taskq == NULL) || (mrevt =
7717 kmem_zalloc(sizeof (struct mrsas_eventinfo), KM_NOSLEEP)) == NULL) {
7718 return (ENOMEM);
7719 }
7720
7721 mrevt->instance = instance;
7722 mrevt->tgt = tgt;
7723 mrevt->lun = lun;
7724 mrevt->event = event;
7725 mrevt->wwn = wwn;
7726
7727 if ((ddi_taskq_dispatch(instance->taskq,
7728 (void (*)(void *))mrsas_issue_evt_taskq, mrevt, DDI_NOSLEEP)) !=
7729 DDI_SUCCESS) {
7730 con_log(CL_ANN1, (CE_NOTE,
7731 "mr_sas: Event task failed for t%dl%d event = %d",
7732 tgt, lun, event));
7733 kmem_free(mrevt, sizeof (struct mrsas_eventinfo));
7734 return (DDI_FAILURE);
7735 }
7736 DTRACE_PROBE3(service_evt, int, tgt, int, lun, int, event);
7737 return (DDI_SUCCESS);
7738 }
7739
7740 static void
7741 mrsas_issue_evt_taskq(struct mrsas_eventinfo *mrevt)
7742 {
7743 struct mrsas_instance *instance = mrevt->instance;
7744 dev_info_t *dip;
7745 int circ1 = 0;
7746
7747 con_log(CL_ANN1, (CE_NOTE, "mrsas_issue_evt_taskq: called for"
7748 " tgt %d lun %d event %d",
7749 mrevt->tgt, mrevt->lun, mrevt->event));
7750
7751 if (mrevt->tgt < MRDRV_MAX_LD && mrevt->lun == 0) {
7752 mutex_enter(&instance->config_dev_mtx);
7753 dip = instance->mr_ld_list[mrevt->tgt].dip;
7754 mutex_exit(&instance->config_dev_mtx);
7755 } else {
7756 mutex_enter(&instance->config_dev_mtx);
7757 dip = instance->mr_tbolt_pd_list[mrevt->tgt].dip;
7758 mutex_exit(&instance->config_dev_mtx);
7759 }
7760
7761
7762 ndi_devi_enter(instance->dip, &circ1);
7763 switch (mrevt->event) {
7764 case MRSAS_EVT_CONFIG_TGT:
7765 if (dip == NULL) {
7766 if (mrevt->lun == 0) {
7767 (void) mrsas_config_ld(instance, mrevt->tgt,
7768 0, NULL);
7769 } else if (instance->tbolt || instance->skinny) {
7770 (void) mrsas_tbolt_config_pd(instance,
7771 mrevt->tgt,
7772 1, NULL);
7773 }
7774 con_log(CL_ANN1, (CE_NOTE,
7775 "mr_sas: EVT_CONFIG_TGT called:"
7776 " for tgt %d lun %d event %d",
7777 mrevt->tgt, mrevt->lun, mrevt->event));
7778 } else {
7779 con_log(CL_ANN1, (CE_NOTE,
7780 "mr_sas: EVT_CONFIG_TGT dip != NULL:"
7781 " for tgt %d lun %d event %d",
7782 mrevt->tgt, mrevt->lun, mrevt->event));
7783 }
7784 break;
7785 case MRSAS_EVT_UNCONFIG_TGT:
7786 if (dip) {
7787 (void) ndi_devi_offline(dip,
7788 NDI_DEVFS_CLEAN | NDI_DEVI_REMOVE);
7789 con_log(CL_ANN1, (CE_NOTE,
7790 "mr_sas: EVT_UNCONFIG_TGT called:"
7791 " for tgt %d lun %d event %d",
7792 mrevt->tgt, mrevt->lun, mrevt->event));
7793 } else {
7794 con_log(CL_ANN1, (CE_NOTE,
7795 "mr_sas: EVT_UNCONFIG_TGT dip == NULL:"
7796 " for tgt %d lun %d event %d",
7797 mrevt->tgt, mrevt->lun, mrevt->event));
7798 }
7799 break;
7800 }
7801 kmem_free(mrevt, sizeof (struct mrsas_eventinfo));
7802 ndi_devi_exit(instance->dip, circ1);
7803 }
7804
7805
7806 int
7807 mrsas_mode_sense_build(struct scsi_pkt *pkt)
7808 {
7809 union scsi_cdb *cdbp;
7810 uint16_t page_code;
7811 struct scsa_cmd *acmd;
7812 struct buf *bp;
7813 struct mode_header *modehdrp;
7814
7815 cdbp = (void *)pkt->pkt_cdbp;
7816 page_code = cdbp->cdb_un.sg.scsi[0];
7817 acmd = PKT2CMD(pkt);
7818 bp = acmd->cmd_buf;
7819 if ((!bp) && bp->b_un.b_addr && bp->b_bcount && acmd->cmd_dmacount) {
7820 con_log(CL_ANN1, (CE_WARN, "Failing MODESENSE Command"));
7821 /* ADD pkt statistics as Command failed. */
7822 return (NULL);
7823 }
7824
7825 bp_mapin(bp);
7826 bzero(bp->b_un.b_addr, bp->b_bcount);
7827
7828 switch (page_code) {
7829 case 0x3: {
7830 struct mode_format *page3p = NULL;
7831 modehdrp = (struct mode_header *)(bp->b_un.b_addr);
7832 modehdrp->bdesc_length = MODE_BLK_DESC_LENGTH;
7833
7834 page3p = (void *)((caddr_t)modehdrp +
7835 MODE_HEADER_LENGTH + MODE_BLK_DESC_LENGTH);
7836 page3p->mode_page.code = 0x3;
7837 page3p->mode_page.length =
7838 (uchar_t)(sizeof (struct mode_format));
7839 page3p->data_bytes_sect = 512;
7840 page3p->sect_track = 63;
7841 break;
7842 }
7843 case 0x4: {
7844 struct mode_geometry *page4p = NULL;
7845 modehdrp = (struct mode_header *)(bp->b_un.b_addr);
7846 modehdrp->bdesc_length = MODE_BLK_DESC_LENGTH;
7847
7848 page4p = (void *)((caddr_t)modehdrp +
7849 MODE_HEADER_LENGTH + MODE_BLK_DESC_LENGTH);
7850 page4p->mode_page.code = 0x4;
7851 page4p->mode_page.length =
7852 (uchar_t)(sizeof (struct mode_geometry));
7853 page4p->heads = 255;
7854 page4p->rpm = 10000;
7855 break;
7856 }
7857 default:
7858 break;
7859 }
7860 return (NULL);
7861 }