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9695 Slow crash dumps, significantly slower than live core
Reviewed by: Dan Fields <dan.fields@nexenta.com>
Reviewed by: Yuri Pankov <yuri.pankov@nexenta.com>
Reviewed by: Rick McNeal <rick.mcneal@nexenta.com>
Reviewed by: Sanjay Nadkarni <sanjay.nadkarni@nexenta.com>
Reviewed by: Toomas Soome <tsoome@me.com>
Reviewed by: Robert Mustacchi <rm@joyent.com>
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--- old/usr/src/uts/common/io/sata/adapters/ahci/ahci.c
+++ new/usr/src/uts/common/io/sata/adapters/ahci/ahci.c
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
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13 lines elided |
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14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21
22 22 /*
23 23 * Copyright (c) 2006, 2010, Oracle and/or its affiliates. All rights reserved.
24 - * Copyright 2013 Nexenta Systems, Inc. All rights reserved.
24 + * Copyright 2018 Nexenta Systems, Inc. All rights reserved.
25 25 */
26 26
27 27 /*
28 28 * AHCI (Advanced Host Controller Interface) SATA HBA Driver
29 29 *
30 30 * Power Management Support
31 31 * ------------------------
32 32 *
33 33 * At the moment, the ahci driver only implements suspend/resume to
34 34 * support Suspend to RAM on X86 feature. Device power management isn't
35 35 * implemented, link power management is disabled, and hot plug isn't
36 36 * allowed during the period from suspend to resume.
37 37 *
38 38 * For s/r support, the ahci driver only need to implement DDI_SUSPEND
39 39 * and DDI_RESUME entries, and don't need to take care of new requests
40 40 * sent down after suspend because the target driver (sd) has already
41 41 * handled these conditions, and blocked these requests. For the detailed
42 42 * information, please check with sdopen, sdclose and sdioctl routines.
43 43 *
44 44 */
45 45
46 46 #include <sys/note.h>
47 47 #include <sys/scsi/scsi.h>
48 48 #include <sys/pci.h>
49 49 #include <sys/disp.h>
50 50 #include <sys/sata/sata_hba.h>
51 51 #include <sys/sata/adapters/ahci/ahcireg.h>
52 52 #include <sys/sata/adapters/ahci/ahcivar.h>
53 53
54 54 /*
55 55 * FMA header files
56 56 */
57 57 #include <sys/ddifm.h>
58 58 #include <sys/fm/protocol.h>
59 59 #include <sys/fm/util.h>
60 60 #include <sys/fm/io/ddi.h>
61 61
62 62 /*
63 63 * This is the string displayed by modinfo, etc.
64 64 */
65 65 static char ahci_ident[] = "ahci driver";
66 66
67 67 /*
68 68 * Function prototypes for driver entry points
69 69 */
70 70 static int ahci_attach(dev_info_t *, ddi_attach_cmd_t);
71 71 static int ahci_detach(dev_info_t *, ddi_detach_cmd_t);
72 72 static int ahci_getinfo(dev_info_t *, ddi_info_cmd_t, void *, void **);
73 73 static int ahci_quiesce(dev_info_t *);
74 74
75 75 /*
76 76 * Function prototypes for SATA Framework interfaces
77 77 */
78 78 static int ahci_register_sata_hba_tran(ahci_ctl_t *, uint32_t);
79 79 static int ahci_unregister_sata_hba_tran(ahci_ctl_t *);
80 80
81 81 static int ahci_tran_probe_port(dev_info_t *, sata_device_t *);
82 82 static int ahci_tran_start(dev_info_t *, sata_pkt_t *spkt);
83 83 static int ahci_tran_abort(dev_info_t *, sata_pkt_t *, int);
84 84 static int ahci_tran_reset_dport(dev_info_t *, sata_device_t *);
85 85 static int ahci_tran_hotplug_port_activate(dev_info_t *, sata_device_t *);
86 86 static int ahci_tran_hotplug_port_deactivate(dev_info_t *, sata_device_t *);
87 87 #if defined(__lock_lint)
88 88 static int ahci_selftest(dev_info_t *, sata_device_t *);
89 89 #endif
90 90
91 91 /*
92 92 * FMA Prototypes
93 93 */
94 94 static void ahci_fm_init(ahci_ctl_t *);
95 95 static void ahci_fm_fini(ahci_ctl_t *);
96 96 static int ahci_fm_error_cb(dev_info_t *, ddi_fm_error_t *, const void*);
97 97 int ahci_check_acc_handle(ddi_acc_handle_t);
98 98 int ahci_check_dma_handle(ddi_dma_handle_t);
99 99 void ahci_fm_ereport(ahci_ctl_t *, char *);
100 100 static int ahci_check_all_handle(ahci_ctl_t *);
101 101 static int ahci_check_ctl_handle(ahci_ctl_t *);
102 102 static int ahci_check_port_handle(ahci_ctl_t *, int);
103 103 static int ahci_check_slot_handle(ahci_port_t *, int);
104 104
105 105 /*
106 106 * Local function prototypes
107 107 */
108 108 static int ahci_setup_port_base_addresses(ahci_ctl_t *, ahci_port_t *);
109 109 static int ahci_alloc_ports_state(ahci_ctl_t *);
110 110 static void ahci_dealloc_ports_state(ahci_ctl_t *);
111 111 static int ahci_alloc_port_state(ahci_ctl_t *, uint8_t);
112 112 static void ahci_dealloc_port_state(ahci_ctl_t *, uint8_t);
113 113 static int ahci_alloc_rcvd_fis(ahci_ctl_t *, ahci_port_t *);
114 114 static void ahci_dealloc_rcvd_fis(ahci_port_t *);
115 115 static int ahci_alloc_cmd_list(ahci_ctl_t *, ahci_port_t *);
116 116 static void ahci_dealloc_cmd_list(ahci_ctl_t *, ahci_port_t *);
117 117 static int ahci_alloc_cmd_tables(ahci_ctl_t *, ahci_port_t *);
118 118 static void ahci_dealloc_cmd_tables(ahci_ctl_t *, ahci_port_t *);
119 119 static void ahci_alloc_pmult(ahci_ctl_t *, ahci_port_t *);
120 120 static void ahci_dealloc_pmult(ahci_ctl_t *, ahci_port_t *);
121 121
122 122 static int ahci_initialize_controller(ahci_ctl_t *);
123 123 static void ahci_uninitialize_controller(ahci_ctl_t *);
124 124 static int ahci_initialize_port(ahci_ctl_t *, ahci_port_t *, ahci_addr_t *);
125 125 static int ahci_config_space_init(ahci_ctl_t *);
126 126 static void ahci_staggered_spin_up(ahci_ctl_t *, uint8_t);
127 127
128 128 static void ahci_drain_ports_taskq(ahci_ctl_t *);
129 129 static int ahci_rdwr_pmult(ahci_ctl_t *, ahci_addr_t *, uint8_t, uint32_t *,
130 130 uint8_t);
131 131 static int ahci_read_pmult(ahci_ctl_t *, ahci_addr_t *, uint8_t, uint32_t *);
132 132 static int ahci_write_pmult(ahci_ctl_t *, ahci_addr_t *, uint8_t, uint32_t);
133 133 static int ahci_update_pmult_pscr(ahci_ctl_t *, ahci_addr_t *,
134 134 sata_device_t *);
135 135 static int ahci_update_pmult_gscr(ahci_ctl_t *, ahci_addr_t *,
136 136 sata_pmult_gscr_t *);
137 137 static int ahci_initialize_pmult(ahci_ctl_t *, ahci_port_t *, ahci_addr_t *,
138 138 sata_device_t *);
139 139 static int ahci_initialize_pmport(ahci_ctl_t *, ahci_port_t *, ahci_addr_t *);
140 140 static int ahci_probe_pmult(ahci_ctl_t *, ahci_port_t *, ahci_addr_t *);
141 141 static int ahci_probe_pmport(ahci_ctl_t *, ahci_port_t *, ahci_addr_t *,
142 142 sata_device_t *);
143 143
144 144 static void ahci_disable_interface_pm(ahci_ctl_t *, uint8_t);
145 145 static int ahci_start_port(ahci_ctl_t *, ahci_port_t *, uint8_t);
146 146 static void ahci_find_dev_signature(ahci_ctl_t *, ahci_port_t *,
147 147 ahci_addr_t *);
148 148 static void ahci_update_sata_registers(ahci_ctl_t *, uint8_t, sata_device_t *);
149 149 static int ahci_deliver_satapkt(ahci_ctl_t *, ahci_port_t *,
150 150 ahci_addr_t *, sata_pkt_t *);
151 151 static int ahci_do_sync_start(ahci_ctl_t *, ahci_port_t *,
152 152 ahci_addr_t *, sata_pkt_t *);
153 153 static int ahci_claim_free_slot(ahci_ctl_t *, ahci_port_t *,
154 154 ahci_addr_t *, int);
155 155 static void ahci_copy_err_cnxt(sata_cmd_t *, ahci_fis_d2h_register_t *);
156 156 static void ahci_copy_ncq_err_page(sata_cmd_t *,
157 157 struct sata_ncq_error_recovery_page *);
158 158 static void ahci_copy_out_regs(sata_cmd_t *, ahci_fis_d2h_register_t *);
159 159 static void ahci_add_doneq(ahci_port_t *, sata_pkt_t *, int);
160 160 static void ahci_flush_doneq(ahci_port_t *);
161 161
162 162 static int ahci_software_reset(ahci_ctl_t *, ahci_port_t *, ahci_addr_t *);
163 163 static int ahci_hba_reset(ahci_ctl_t *);
164 164 static int ahci_port_reset(ahci_ctl_t *, ahci_port_t *, ahci_addr_t *);
165 165 static int ahci_pmport_reset(ahci_ctl_t *, ahci_port_t *, ahci_addr_t *);
166 166 static void ahci_reject_all_abort_pkts(ahci_ctl_t *, ahci_port_t *, uint8_t);
167 167 static int ahci_reset_device_reject_pkts(ahci_ctl_t *, ahci_port_t *,
168 168 ahci_addr_t *);
169 169 static int ahci_reset_pmdevice_reject_pkts(ahci_ctl_t *, ahci_port_t *,
170 170 ahci_addr_t *);
171 171 static int ahci_reset_port_reject_pkts(ahci_ctl_t *, ahci_port_t *,
172 172 ahci_addr_t *);
173 173 static int ahci_reset_hba_reject_pkts(ahci_ctl_t *);
174 174 static int ahci_put_port_into_notrunning_state(ahci_ctl_t *, ahci_port_t *,
175 175 uint8_t);
176 176 static int ahci_restart_port_wait_till_ready(ahci_ctl_t *, ahci_port_t *,
177 177 uint8_t, int, int *);
178 178 static void ahci_mop_commands(ahci_ctl_t *, ahci_port_t *, uint32_t,
179 179 uint32_t, uint32_t, uint32_t, uint32_t);
180 180 static uint32_t ahci_get_rdlogext_data(ahci_ctl_t *, ahci_port_t *, uint8_t);
181 181 static void ahci_get_rqsense_data(ahci_ctl_t *, ahci_port_t *,
182 182 uint8_t, sata_pkt_t *);
183 183 static void ahci_fatal_error_recovery_handler(ahci_ctl_t *, ahci_port_t *,
184 184 ahci_addr_t *, uint32_t);
185 185 static void ahci_pmult_error_recovery_handler(ahci_ctl_t *, ahci_port_t *,
186 186 uint8_t, uint32_t);
187 187 static void ahci_timeout_pkts(ahci_ctl_t *, ahci_port_t *,
188 188 uint8_t, uint32_t);
189 189 static void ahci_events_handler(void *);
190 190 static void ahci_watchdog_handler(ahci_ctl_t *);
191 191
192 192 static uint_t ahci_intr(caddr_t, caddr_t);
193 193 static void ahci_port_intr(ahci_ctl_t *, ahci_port_t *, uint8_t);
194 194 static int ahci_add_intrs(ahci_ctl_t *, int);
195 195 static void ahci_rem_intrs(ahci_ctl_t *);
196 196 static void ahci_enable_all_intrs(ahci_ctl_t *);
197 197 static void ahci_disable_all_intrs(ahci_ctl_t *);
198 198 static void ahci_enable_port_intrs(ahci_ctl_t *, uint8_t);
199 199 static void ahci_disable_port_intrs(ahci_ctl_t *, uint8_t);
200 200
201 201 static int ahci_intr_cmd_cmplt(ahci_ctl_t *, ahci_port_t *, uint8_t);
202 202 static int ahci_intr_set_device_bits(ahci_ctl_t *, ahci_port_t *, uint8_t);
203 203 static int ahci_intr_ncq_events(ahci_ctl_t *, ahci_port_t *, ahci_addr_t *);
204 204 static int ahci_intr_pmult_sntf_events(ahci_ctl_t *, ahci_port_t *, uint8_t);
205 205 static int ahci_intr_port_connect_change(ahci_ctl_t *, ahci_port_t *, uint8_t);
206 206 static int ahci_intr_device_mechanical_presence_status(ahci_ctl_t *,
207 207 ahci_port_t *, uint8_t);
208 208 static int ahci_intr_phyrdy_change(ahci_ctl_t *, ahci_port_t *, uint8_t);
209 209 static int ahci_intr_non_fatal_error(ahci_ctl_t *, ahci_port_t *,
210 210 uint8_t, uint32_t);
211 211 static int ahci_intr_fatal_error(ahci_ctl_t *, ahci_port_t *,
212 212 uint8_t, uint32_t);
213 213 static int ahci_intr_cold_port_detect(ahci_ctl_t *, ahci_port_t *, uint8_t);
214 214
215 215 static void ahci_get_ahci_addr(ahci_ctl_t *, sata_device_t *, ahci_addr_t *);
216 216 static int ahci_get_num_implemented_ports(uint32_t);
217 217 static void ahci_log_fatal_error_message(ahci_ctl_t *, uint8_t, uint32_t);
218 218 static void ahci_dump_commands(ahci_ctl_t *, uint8_t, uint32_t);
219 219 static void ahci_log_serror_message(ahci_ctl_t *, uint8_t, uint32_t, int);
220 220 #if AHCI_DEBUG
221 221 static void ahci_log(ahci_ctl_t *, uint_t, char *, ...);
222 222 #endif
223 223
224 224
225 225 /*
226 226 * DMA attributes for the data buffer
227 227 *
228 228 * dma_attr_addr_hi will be changed to 0xffffffffull if the HBA
229 229 * does not support 64-bit addressing
230 230 */
231 231 static ddi_dma_attr_t buffer_dma_attr = {
232 232 DMA_ATTR_V0, /* dma_attr_version */
233 233 0x0ull, /* dma_attr_addr_lo: lowest bus address */
234 234 0xffffffffffffffffull, /* dma_attr_addr_hi: highest bus address */
235 235 0x3fffffull, /* dma_attr_count_max i.e. for one cookie */
236 236 0x2ull, /* dma_attr_align: word aligned */
237 237 1, /* dma_attr_burstsizes */
238 238 1, /* dma_attr_minxfer */
239 239 0xffffffffull, /* dma_attr_maxxfer i.e. includes all cookies */
240 240 0xffffffffull, /* dma_attr_seg */
241 241 AHCI_PRDT_NUMBER, /* dma_attr_sgllen */
242 242 512, /* dma_attr_granular */
243 243 0, /* dma_attr_flags */
244 244 };
245 245
246 246 /*
247 247 * DMA attributes for the rcvd FIS
248 248 *
249 249 * dma_attr_addr_hi will be changed to 0xffffffffull if the HBA
250 250 * does not support 64-bit addressing
251 251 */
252 252 static ddi_dma_attr_t rcvd_fis_dma_attr = {
253 253 DMA_ATTR_V0, /* dma_attr_version */
254 254 0x0ull, /* dma_attr_addr_lo: lowest bus address */
255 255 0xffffffffffffffffull, /* dma_attr_addr_hi: highest bus address */
256 256 0xffffffffull, /* dma_attr_count_max i.e. for one cookie */
257 257 0x100ull, /* dma_attr_align: 256-byte aligned */
258 258 1, /* dma_attr_burstsizes */
259 259 1, /* dma_attr_minxfer */
260 260 0xffffffffull, /* dma_attr_maxxfer i.e. includes all cookies */
261 261 0xffffffffull, /* dma_attr_seg */
262 262 1, /* dma_attr_sgllen */
263 263 1, /* dma_attr_granular */
264 264 0, /* dma_attr_flags */
265 265 };
266 266
267 267 /*
268 268 * DMA attributes for the command list
269 269 *
270 270 * dma_attr_addr_hi will be changed to 0xffffffffull if the HBA
271 271 * does not support 64-bit addressing
272 272 */
273 273 static ddi_dma_attr_t cmd_list_dma_attr = {
274 274 DMA_ATTR_V0, /* dma_attr_version */
275 275 0x0ull, /* dma_attr_addr_lo: lowest bus address */
276 276 0xffffffffffffffffull, /* dma_attr_addr_hi: highest bus address */
277 277 0xffffffffull, /* dma_attr_count_max i.e. for one cookie */
278 278 0x400ull, /* dma_attr_align: 1K-byte aligned */
279 279 1, /* dma_attr_burstsizes */
280 280 1, /* dma_attr_minxfer */
281 281 0xffffffffull, /* dma_attr_maxxfer i.e. includes all cookies */
282 282 0xffffffffull, /* dma_attr_seg */
283 283 1, /* dma_attr_sgllen */
284 284 1, /* dma_attr_granular */
285 285 0, /* dma_attr_flags */
286 286 };
287 287
288 288 /*
289 289 * DMA attributes for cmd tables
290 290 *
291 291 * dma_attr_addr_hi will be changed to 0xffffffffull if the HBA
292 292 * does not support 64-bit addressing
293 293 */
294 294 static ddi_dma_attr_t cmd_table_dma_attr = {
295 295 DMA_ATTR_V0, /* dma_attr_version */
296 296 0x0ull, /* dma_attr_addr_lo: lowest bus address */
297 297 0xffffffffffffffffull, /* dma_attr_addr_hi: highest bus address */
298 298 0xffffffffull, /* dma_attr_count_max i.e. for one cookie */
299 299 0x80ull, /* dma_attr_align: 128-byte aligned */
300 300 1, /* dma_attr_burstsizes */
301 301 1, /* dma_attr_minxfer */
302 302 0xffffffffull, /* dma_attr_maxxfer i.e. includes all cookies */
303 303 0xffffffffull, /* dma_attr_seg */
304 304 1, /* dma_attr_sgllen */
305 305 1, /* dma_attr_granular */
306 306 0, /* dma_attr_flags */
307 307 };
308 308
309 309
310 310 /* Device access attributes */
311 311 static ddi_device_acc_attr_t accattr = {
312 312 DDI_DEVICE_ATTR_V1,
313 313 DDI_STRUCTURE_LE_ACC,
314 314 DDI_STRICTORDER_ACC,
315 315 DDI_DEFAULT_ACC
316 316 };
317 317
318 318
319 319 static struct dev_ops ahcictl_dev_ops = {
320 320 DEVO_REV, /* devo_rev */
321 321 0, /* refcnt */
322 322 ahci_getinfo, /* info */
323 323 nulldev, /* identify */
324 324 nulldev, /* probe */
325 325 ahci_attach, /* attach */
326 326 ahci_detach, /* detach */
327 327 nodev, /* no reset */
328 328 (struct cb_ops *)0, /* driver operations */
329 329 NULL, /* bus operations */
330 330 NULL, /* power */
331 331 ahci_quiesce, /* quiesce */
332 332 };
333 333
334 334 static sata_tran_hotplug_ops_t ahci_tran_hotplug_ops = {
335 335 SATA_TRAN_HOTPLUG_OPS_REV_1,
336 336 ahci_tran_hotplug_port_activate,
337 337 ahci_tran_hotplug_port_deactivate
338 338 };
339 339
340 340 extern struct mod_ops mod_driverops;
341 341
342 342 static struct modldrv modldrv = {
343 343 &mod_driverops, /* driverops */
344 344 ahci_ident, /* short description */
345 345 &ahcictl_dev_ops, /* driver ops */
346 346 };
347 347
348 348 static struct modlinkage modlinkage = {
349 349 MODREV_1,
350 350 &modldrv,
351 351 NULL
352 352 };
353 353
354 354 /* The following variables are watchdog handler related */
355 355 static clock_t ahci_watchdog_timeout = 5; /* 5 seconds */
356 356 static clock_t ahci_watchdog_tick;
357 357
358 358 /*
359 359 * This static variable indicates the size of command table,
360 360 * and it's changeable with prdt number, which ahci_dma_prdt_number
361 361 * indicates.
362 362 */
363 363 static size_t ahci_cmd_table_size;
364 364
365 365 /*
366 366 * The below global variables are tunable via /etc/system
367 367 *
368 368 * ahci_dma_prdt_number
369 369 * ahci_msi_enabled
370 370 * ahci_buf_64bit_dma
371 371 * ahci_commu_64bit_dma
372 372 */
373 373
374 374 /* The number of Physical Region Descriptor Table(PRDT) in Command Table */
375 375 int ahci_dma_prdt_number = AHCI_PRDT_NUMBER;
376 376
377 377 /* AHCI MSI is tunable */
378 378 boolean_t ahci_msi_enabled = B_TRUE;
379 379
380 380 /*
381 381 * 64-bit dma addressing for data buffer is tunable
382 382 *
383 383 * The variable controls only the below value:
384 384 * DBAU (upper 32-bits physical address of data block)
385 385 */
386 386 boolean_t ahci_buf_64bit_dma = B_TRUE;
387 387
388 388 /*
389 389 * 64-bit dma addressing for communication system descriptors is tunable
390 390 *
391 391 * The variable controls the below three values:
392 392 *
393 393 * PxCLBU (upper 32-bits for the command list base physical address)
394 394 * PxFBU (upper 32-bits for the received FIS base physical address)
395 395 * CTBAU (upper 32-bits of command table base)
396 396 */
397 397 boolean_t ahci_commu_64bit_dma = B_TRUE;
398 398
399 399 /*
400 400 * By default, 64-bit dma for data buffer will be disabled for AMD/ATI SB600
401 401 * chipset. If the users want to have a try with 64-bit dma, please change
402 402 * the below variable value to enable it.
403 403 */
404 404 boolean_t sb600_buf_64bit_dma_disable = B_TRUE;
405 405
406 406 /*
407 407 * By default, 64-bit dma for command buffer will be disabled for AMD/ATI
408 408 * SB600/700/710/750/800. If the users want to have a try with 64-bit dma,
409 409 * please change the below value to enable it.
410 410 */
411 411 boolean_t sbxxx_commu_64bit_dma_disable = B_TRUE;
412 412
413 413
414 414 /*
415 415 * End of global tunable variable definition
416 416 */
417 417
418 418 #if AHCI_DEBUG
419 419 uint32_t ahci_debug_flags = 0;
420 420 #else
421 421 uint32_t ahci_debug_flags = (AHCIDBG_ERRS|AHCIDBG_TIMEOUT);
422 422 #endif
423 423
424 424
425 425 #if AHCI_DEBUG
426 426 /* The following is needed for ahci_log() */
427 427 static kmutex_t ahci_log_mutex;
428 428 static char ahci_log_buf[512];
429 429 #endif
430 430
431 431 /* Opaque state pointer initialized by ddi_soft_state_init() */
432 432 static void *ahci_statep = NULL;
433 433
434 434 /*
435 435 * ahci module initialization.
436 436 */
437 437 int
438 438 _init(void)
439 439 {
440 440 int ret;
441 441
442 442 ret = ddi_soft_state_init(&ahci_statep, sizeof (ahci_ctl_t), 0);
443 443 if (ret != 0) {
444 444 goto err_out;
445 445 }
446 446
447 447 #if AHCI_DEBUG
448 448 mutex_init(&ahci_log_mutex, NULL, MUTEX_DRIVER, NULL);
449 449 #endif
450 450
451 451 if ((ret = sata_hba_init(&modlinkage)) != 0) {
452 452 #if AHCI_DEBUG
453 453 mutex_destroy(&ahci_log_mutex);
454 454 #endif
455 455 ddi_soft_state_fini(&ahci_statep);
456 456 goto err_out;
457 457 }
458 458
459 459 /* watchdog tick */
460 460 ahci_watchdog_tick = drv_usectohz(
461 461 (clock_t)ahci_watchdog_timeout * 1000000);
462 462
463 463 ret = mod_install(&modlinkage);
464 464 if (ret != 0) {
465 465 sata_hba_fini(&modlinkage);
466 466 #if AHCI_DEBUG
467 467 mutex_destroy(&ahci_log_mutex);
468 468 #endif
469 469 ddi_soft_state_fini(&ahci_statep);
470 470 goto err_out;
471 471 }
472 472
473 473 return (ret);
474 474
475 475 err_out:
476 476 cmn_err(CE_WARN, "!ahci: Module init failed");
477 477 return (ret);
478 478 }
479 479
480 480 /*
481 481 * ahci module uninitialize.
482 482 */
483 483 int
484 484 _fini(void)
485 485 {
486 486 int ret;
487 487
488 488 ret = mod_remove(&modlinkage);
489 489 if (ret != 0) {
490 490 return (ret);
491 491 }
492 492
493 493 /* Remove the resources allocated in _init(). */
494 494 sata_hba_fini(&modlinkage);
495 495 #if AHCI_DEBUG
496 496 mutex_destroy(&ahci_log_mutex);
497 497 #endif
498 498 ddi_soft_state_fini(&ahci_statep);
499 499
500 500 return (ret);
501 501 }
502 502
503 503 /*
504 504 * _info entry point
505 505 */
506 506 int
507 507 _info(struct modinfo *modinfop)
508 508 {
509 509 return (mod_info(&modlinkage, modinfop));
510 510 }
511 511
512 512 /*
513 513 * The attach entry point for dev_ops.
514 514 */
515 515 static int
516 516 ahci_attach(dev_info_t *dip, ddi_attach_cmd_t cmd)
517 517 {
518 518 ahci_ctl_t *ahci_ctlp = NULL;
519 519 int instance = ddi_get_instance(dip);
520 520 int status;
521 521 int attach_state;
522 522 uint32_t cap_status, ahci_version;
523 523 uint32_t ghc_control;
524 524 int intr_types;
525 525 int i;
526 526 pci_regspec_t *regs;
527 527 int regs_length;
528 528 int rnumber;
529 529 #if AHCI_DEBUG
530 530 int speed;
531 531 #endif
532 532
533 533 AHCIDBG(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, "ahci_attach enter",
534 534 NULL);
535 535
536 536 switch (cmd) {
537 537 case DDI_ATTACH:
538 538 break;
539 539
540 540 case DDI_RESUME:
541 541
542 542 /*
543 543 * During DDI_RESUME, the hardware state of the device
544 544 * (power may have been removed from the device) must be
545 545 * restored, allow pending requests to continue, and
546 546 * service new requests.
547 547 */
548 548 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance);
549 549 mutex_enter(&ahci_ctlp->ahcictl_mutex);
550 550
551 551 /*
552 552 * GHC.AE must be set to 1 before any other AHCI register
553 553 * is accessed
554 554 */
555 555 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
556 556 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp));
557 557 ghc_control |= AHCI_HBA_GHC_AE;
558 558 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
559 559 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp), ghc_control);
560 560
561 561 /* Restart watch thread */
562 562 if (ahci_ctlp->ahcictl_timeout_id == 0)
563 563 ahci_ctlp->ahcictl_timeout_id = timeout(
564 564 (void (*)(void *))ahci_watchdog_handler,
565 565 (caddr_t)ahci_ctlp, ahci_watchdog_tick);
566 566
567 567 mutex_exit(&ahci_ctlp->ahcictl_mutex);
568 568
569 569 /*
570 570 * Re-initialize the controller and enable the interrupts and
571 571 * restart all the ports.
572 572 *
573 573 * Note that so far we don't support hot-plug during
574 574 * suspend/resume.
575 575 */
576 576 if (ahci_initialize_controller(ahci_ctlp) != AHCI_SUCCESS) {
577 577 AHCIDBG(AHCIDBG_ERRS|AHCIDBG_PM, ahci_ctlp,
578 578 "Failed to initialize the controller "
579 579 "during DDI_RESUME", NULL);
580 580 return (DDI_FAILURE);
581 581 }
582 582
583 583 mutex_enter(&ahci_ctlp->ahcictl_mutex);
584 584 ahci_ctlp->ahcictl_flags &= ~AHCI_SUSPEND;
585 585 mutex_exit(&ahci_ctlp->ahcictl_mutex);
586 586
587 587 return (DDI_SUCCESS);
588 588
589 589 default:
590 590 return (DDI_FAILURE);
591 591 }
592 592
593 593 attach_state = AHCI_ATTACH_STATE_NONE;
594 594
595 595 /* Allocate soft state */
596 596 status = ddi_soft_state_zalloc(ahci_statep, instance);
597 597 if (status != DDI_SUCCESS) {
598 598 cmn_err(CE_WARN, "!ahci%d: Cannot allocate soft state",
599 599 instance);
600 600 goto err_out;
601 601 }
602 602
603 603 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance);
604 604 ahci_ctlp->ahcictl_flags |= AHCI_ATTACH;
605 605 ahci_ctlp->ahcictl_dip = dip;
606 606
607 607 /* Initialize the cport/port mapping */
608 608 for (i = 0; i < AHCI_MAX_PORTS; i++) {
609 609 ahci_ctlp->ahcictl_port_to_cport[i] = 0xff;
610 610 ahci_ctlp->ahcictl_cport_to_port[i] = 0xff;
611 611 }
612 612
613 613 attach_state |= AHCI_ATTACH_STATE_STATEP_ALLOC;
614 614
615 615 /* Initialize FMA properties */
616 616 ahci_fm_init(ahci_ctlp);
617 617
618 618 attach_state |= AHCI_ATTACH_STATE_FMA;
619 619
620 620 /*
621 621 * Now map the AHCI base address; which includes global
622 622 * registers and port control registers
623 623 *
624 624 * According to the spec, the AHCI Base Address is BAR5,
625 625 * but BAR0-BAR4 are optional, so we need to check which
626 626 * rnumber is used for BAR5.
627 627 */
628 628
629 629 /*
630 630 * search through DDI "reg" property for the AHCI register set
631 631 */
632 632 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip,
633 633 DDI_PROP_DONTPASS, "reg", (int **)®s,
634 634 (uint_t *)®s_length) != DDI_PROP_SUCCESS) {
635 635 cmn_err(CE_WARN, "!ahci%d: Cannot lookup reg property",
636 636 instance);
637 637 goto err_out;
638 638 }
639 639
640 640 /* AHCI Base Address is located at 0x24 offset */
641 641 for (rnumber = 0; rnumber < regs_length; ++rnumber) {
642 642 if ((regs[rnumber].pci_phys_hi & PCI_REG_REG_M)
643 643 == AHCI_PCI_RNUM)
644 644 break;
645 645 }
646 646
647 647 ddi_prop_free(regs);
648 648
649 649 if (rnumber == regs_length) {
650 650 cmn_err(CE_WARN, "!ahci%d: Cannot find AHCI register set",
651 651 instance);
652 652 goto err_out;
653 653 }
654 654
655 655 AHCIDBG(AHCIDBG_INIT, ahci_ctlp, "rnumber = %d", rnumber);
656 656
657 657 status = ddi_regs_map_setup(dip,
658 658 rnumber,
659 659 (caddr_t *)&ahci_ctlp->ahcictl_ahci_addr,
660 660 0,
661 661 0,
662 662 &accattr,
663 663 &ahci_ctlp->ahcictl_ahci_acc_handle);
664 664 if (status != DDI_SUCCESS) {
665 665 cmn_err(CE_WARN, "!ahci%d: Cannot map register space",
666 666 instance);
667 667 goto err_out;
668 668 }
669 669
670 670 attach_state |= AHCI_ATTACH_STATE_REG_MAP;
671 671
672 672 /*
673 673 * GHC.AE must be set to 1 before any other AHCI register
674 674 * is accessed
675 675 */
676 676 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
677 677 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp));
678 678 ghc_control |= AHCI_HBA_GHC_AE;
679 679 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
680 680 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp), ghc_control);
681 681
682 682 /* Get the AHCI version information */
683 683 ahci_version = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
684 684 (uint32_t *)AHCI_GLOBAL_VS(ahci_ctlp));
685 685
686 686 cmn_err(CE_NOTE, "!ahci%d: hba AHCI version = %x.%x", instance,
687 687 (ahci_version & 0xffff0000) >> 16,
688 688 ((ahci_version & 0x0000ff00) >> 4 |
689 689 (ahci_version & 0x000000ff)));
690 690
691 691 /* We don't support controllers whose versions are lower than 1.0 */
692 692 if (!(ahci_version & 0xffff0000)) {
693 693 cmn_err(CE_WARN, "ahci%d: Don't support AHCI HBA with lower "
694 694 "than version 1.0", instance);
695 695 goto err_out;
696 696 }
697 697
698 698 /* Get the HBA capabilities information */
699 699 cap_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
700 700 (uint32_t *)AHCI_GLOBAL_CAP(ahci_ctlp));
701 701
702 702 AHCIDBG(AHCIDBG_INIT, ahci_ctlp, "hba capabilities = 0x%x",
703 703 cap_status);
704 704
705 705 /* CAP2 (HBA Capabilities Extended) is available since AHCI spec 1.2 */
706 706 if (ahci_version >= 0x00010200) {
707 707 uint32_t cap2_status;
708 708
709 709 /* Get the HBA capabilities extended information */
710 710 cap2_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
711 711 (uint32_t *)AHCI_GLOBAL_CAP2(ahci_ctlp));
712 712
713 713 AHCIDBG(AHCIDBG_INIT, ahci_ctlp,
714 714 "hba capabilities extended = 0x%x", cap2_status);
715 715 }
716 716
717 717 #if AHCI_DEBUG
718 718 /* Get the interface speed supported by the HBA */
719 719 speed = (cap_status & AHCI_HBA_CAP_ISS) >> AHCI_HBA_CAP_ISS_SHIFT;
720 720 if (speed == 0x01) {
721 721 AHCIDBG(AHCIDBG_INIT, ahci_ctlp,
722 722 "hba interface speed support: Gen 1 (1.5Gbps)", NULL);
723 723 } else if (speed == 0x10) {
724 724 AHCIDBG(AHCIDBG_INIT, ahci_ctlp,
725 725 "hba interface speed support: Gen 2 (3 Gbps)", NULL);
726 726 } else if (speed == 0x11) {
727 727 AHCIDBG(AHCIDBG_INIT, ahci_ctlp,
728 728 "hba interface speed support: Gen 3 (6 Gbps)", NULL);
729 729 }
730 730 #endif
731 731
732 732 /* Get the number of command slots supported by the HBA */
733 733 ahci_ctlp->ahcictl_num_cmd_slots =
734 734 ((cap_status & AHCI_HBA_CAP_NCS) >>
735 735 AHCI_HBA_CAP_NCS_SHIFT) + 1;
736 736
737 737 AHCIDBG(AHCIDBG_INIT, ahci_ctlp, "hba number of cmd slots: %d",
738 738 ahci_ctlp->ahcictl_num_cmd_slots);
739 739
740 740 /* Get the bit map which indicates ports implemented by the HBA */
741 741 ahci_ctlp->ahcictl_ports_implemented =
742 742 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
743 743 (uint32_t *)AHCI_GLOBAL_PI(ahci_ctlp));
744 744
745 745 AHCIDBG(AHCIDBG_INIT, ahci_ctlp, "hba implementation of ports: 0x%x",
746 746 ahci_ctlp->ahcictl_ports_implemented);
747 747
748 748 /* Max port number implemented */
749 749 ahci_ctlp->ahcictl_num_ports =
750 750 ddi_fls(ahci_ctlp->ahcictl_ports_implemented);
751 751
752 752 AHCIDBG(AHCIDBG_INIT, ahci_ctlp, "hba number of ports: %d",
753 753 (cap_status & AHCI_HBA_CAP_NP) + 1);
754 754
755 755 /* Get the number of implemented ports by the HBA */
756 756 ahci_ctlp->ahcictl_num_implemented_ports =
757 757 ahci_get_num_implemented_ports(
758 758 ahci_ctlp->ahcictl_ports_implemented);
759 759
760 760 AHCIDBG(AHCIDBG_INIT, ahci_ctlp,
761 761 "hba number of implemented ports: %d",
762 762 ahci_ctlp->ahcictl_num_implemented_ports);
763 763
764 764 /* Check whether HBA supports 64bit DMA addressing */
765 765 if (!(cap_status & AHCI_HBA_CAP_S64A)) {
766 766 ahci_ctlp->ahcictl_cap |= AHCI_CAP_BUF_32BIT_DMA;
767 767 ahci_ctlp->ahcictl_cap |= AHCI_CAP_COMMU_32BIT_DMA;
768 768 AHCIDBG(AHCIDBG_INIT, ahci_ctlp,
769 769 "hba does not support 64-bit addressing", NULL);
770 770 }
771 771
772 772 /* Checking for the support of Port Multiplier */
773 773 if (cap_status & AHCI_HBA_CAP_SPM) {
774 774 ahci_ctlp->ahcictl_cap |= AHCI_CAP_PMULT_CBSS;
775 775 AHCIDBG(AHCIDBG_INIT|AHCIDBG_PMULT, ahci_ctlp,
776 776 "hba supports port multiplier (CBSS)", NULL);
777 777
778 778 /* Support FIS-based switching ? */
779 779 if (cap_status & AHCI_HBA_CAP_FBSS) {
780 780 ahci_ctlp->ahcictl_cap |= AHCI_CAP_PMULT_FBSS;
781 781 AHCIDBG(AHCIDBG_INIT|AHCIDBG_PMULT, ahci_ctlp,
782 782 "hba supports FIS-based switching (FBSS)", NULL);
783 783 }
784 784 }
785 785
786 786 /* Checking for Support Command List Override */
787 787 if (cap_status & AHCI_HBA_CAP_SCLO) {
788 788 ahci_ctlp->ahcictl_cap |= AHCI_CAP_SCLO;
789 789 AHCIDBG(AHCIDBG_INIT|AHCIDBG_PMULT, ahci_ctlp,
790 790 "hba supports command list override.", NULL);
791 791 }
792 792
793 793 /* Checking for Asynchronous Notification */
794 794 if (cap_status & AHCI_HBA_CAP_SSNTF) {
795 795 ahci_ctlp->ahcictl_cap |= AHCI_CAP_SNTF;
796 796 AHCIDBG(AHCIDBG_INIT|AHCIDBG_PMULT, ahci_ctlp,
797 797 "hba supports asynchronous notification.", NULL);
798 798 }
799 799
800 800 if (pci_config_setup(dip, &ahci_ctlp->ahcictl_pci_conf_handle)
801 801 != DDI_SUCCESS) {
802 802 cmn_err(CE_WARN, "!ahci%d: Cannot set up pci configure space",
803 803 instance);
804 804 goto err_out;
805 805 }
806 806
807 807 attach_state |= AHCI_ATTACH_STATE_PCICFG_SETUP;
808 808
809 809 /*
810 810 * Check the pci configuration space, and set caps. We also
811 811 * handle the hardware defect in this function.
812 812 *
813 813 * For example, force ATI SB600 to use 32-bit dma addressing
814 814 * since it doesn't support 64-bit dma though its CAP register
815 815 * declares it support.
816 816 */
817 817 if (ahci_config_space_init(ahci_ctlp) == AHCI_FAILURE) {
818 818 cmn_err(CE_WARN, "!ahci%d: ahci_config_space_init failed",
819 819 instance);
820 820 goto err_out;
821 821 }
822 822
823 823 /*
824 824 * Disable the whole controller interrupts before adding
825 825 * interrupt handlers(s).
826 826 */
827 827 ahci_disable_all_intrs(ahci_ctlp);
828 828
829 829 /* Get supported interrupt types */
830 830 if (ddi_intr_get_supported_types(dip, &intr_types) != DDI_SUCCESS) {
831 831 cmn_err(CE_WARN, "!ahci%d: ddi_intr_get_supported_types failed",
832 832 instance);
833 833 goto err_out;
834 834 }
835 835
836 836 AHCIDBG(AHCIDBG_INIT|AHCIDBG_INTR, ahci_ctlp,
837 837 "ddi_intr_get_supported_types() returned: 0x%x",
838 838 intr_types);
839 839
840 840 if (ahci_msi_enabled && (intr_types & DDI_INTR_TYPE_MSI)) {
841 841 /*
842 842 * Try MSI first, but fall back to FIXED if failed
843 843 */
844 844 if (ahci_add_intrs(ahci_ctlp, DDI_INTR_TYPE_MSI) ==
845 845 DDI_SUCCESS) {
846 846 ahci_ctlp->ahcictl_intr_type = DDI_INTR_TYPE_MSI;
847 847 AHCIDBG(AHCIDBG_INIT|AHCIDBG_INTR, ahci_ctlp,
848 848 "Using MSI interrupt type", NULL);
849 849 goto intr_done;
850 850 }
851 851
852 852 AHCIDBG(AHCIDBG_INIT|AHCIDBG_INTR, ahci_ctlp,
853 853 "MSI registration failed, "
854 854 "trying FIXED interrupts", NULL);
855 855 }
856 856
857 857 if (intr_types & DDI_INTR_TYPE_FIXED) {
858 858 if (ahci_add_intrs(ahci_ctlp, DDI_INTR_TYPE_FIXED) ==
859 859 DDI_SUCCESS) {
860 860 ahci_ctlp->ahcictl_intr_type = DDI_INTR_TYPE_FIXED;
861 861 AHCIDBG(AHCIDBG_INIT|AHCIDBG_INTR, ahci_ctlp,
862 862 "Using FIXED interrupt type", NULL);
863 863 goto intr_done;
864 864 }
865 865
866 866 AHCIDBG(AHCIDBG_INIT|AHCIDBG_INTR, ahci_ctlp,
867 867 "FIXED interrupt registration failed", NULL);
868 868 }
869 869
870 870 cmn_err(CE_WARN, "!ahci%d: Interrupt registration failed", instance);
871 871
872 872 goto err_out;
873 873
874 874 intr_done:
875 875
876 876 attach_state |= AHCI_ATTACH_STATE_INTR_ADDED;
877 877
878 878 /* Initialize the controller mutex */
879 879 mutex_init(&ahci_ctlp->ahcictl_mutex, NULL, MUTEX_DRIVER,
880 880 (void *)(uintptr_t)ahci_ctlp->ahcictl_intr_pri);
881 881
882 882 attach_state |= AHCI_ATTACH_STATE_MUTEX_INIT;
883 883
884 884 if (ahci_dma_prdt_number < AHCI_MIN_PRDT_NUMBER) {
885 885 ahci_dma_prdt_number = AHCI_MIN_PRDT_NUMBER;
886 886 } else if (ahci_dma_prdt_number > AHCI_MAX_PRDT_NUMBER) {
887 887 ahci_dma_prdt_number = AHCI_MAX_PRDT_NUMBER;
888 888 }
889 889
890 890 ahci_cmd_table_size = (sizeof (ahci_cmd_table_t) +
891 891 (ahci_dma_prdt_number - AHCI_PRDT_NUMBER) *
892 892 sizeof (ahci_prdt_item_t));
893 893
894 894 AHCIDBG(AHCIDBG_INIT, ahci_ctlp,
895 895 "ahci_attach: ahci_dma_prdt_number set by user is 0x%x,"
896 896 " ahci_cmd_table_size is 0x%x",
897 897 ahci_dma_prdt_number, ahci_cmd_table_size);
898 898
899 899 if (ahci_dma_prdt_number != AHCI_PRDT_NUMBER)
900 900 ahci_ctlp->ahcictl_buffer_dma_attr.dma_attr_sgllen =
901 901 ahci_dma_prdt_number;
902 902
903 903 ahci_ctlp->ahcictl_buffer_dma_attr = buffer_dma_attr;
904 904 ahci_ctlp->ahcictl_rcvd_fis_dma_attr = rcvd_fis_dma_attr;
905 905 ahci_ctlp->ahcictl_cmd_list_dma_attr = cmd_list_dma_attr;
906 906 ahci_ctlp->ahcictl_cmd_table_dma_attr = cmd_table_dma_attr;
907 907
908 908 /*
909 909 * enable 64bit dma for data buffer for SB600 if
910 910 * sb600_buf_64bit_dma_disable is B_FALSE
911 911 */
912 912 if ((ahci_buf_64bit_dma == B_FALSE) ||
913 913 ((ahci_ctlp->ahcictl_cap & AHCI_CAP_BUF_32BIT_DMA) &&
914 914 !(sb600_buf_64bit_dma_disable == B_FALSE &&
915 915 ahci_ctlp->ahcictl_venid == 0x1002 &&
916 916 ahci_ctlp->ahcictl_devid == 0x4380))) {
917 917 ahci_ctlp->ahcictl_buffer_dma_attr.dma_attr_addr_hi =
918 918 0xffffffffull;
919 919 }
920 920
921 921 /*
922 922 * enable 64bit dma for command buffer for SB600/700/710/800
923 923 * if sbxxx_commu_64bit_dma_disable is B_FALSE
924 924 */
925 925 if ((ahci_commu_64bit_dma == B_FALSE) ||
926 926 ((ahci_ctlp->ahcictl_cap & AHCI_CAP_COMMU_32BIT_DMA) &&
927 927 !(sbxxx_commu_64bit_dma_disable == B_FALSE &&
928 928 ahci_ctlp->ahcictl_venid == 0x1002 &&
929 929 (ahci_ctlp->ahcictl_devid == 0x4380 ||
930 930 ahci_ctlp->ahcictl_devid == 0x4391)))) {
931 931 ahci_ctlp->ahcictl_rcvd_fis_dma_attr.dma_attr_addr_hi =
932 932 0xffffffffull;
933 933 ahci_ctlp->ahcictl_cmd_list_dma_attr.dma_attr_addr_hi =
934 934 0xffffffffull;
935 935 ahci_ctlp->ahcictl_cmd_table_dma_attr.dma_attr_addr_hi =
936 936 0xffffffffull;
937 937 }
938 938
939 939 /* Allocate the ports structure */
940 940 status = ahci_alloc_ports_state(ahci_ctlp);
941 941 if (status != AHCI_SUCCESS) {
942 942 cmn_err(CE_WARN, "!ahci%d: Cannot allocate ports structure",
943 943 instance);
944 944 goto err_out;
945 945 }
946 946
947 947 attach_state |= AHCI_ATTACH_STATE_PORT_ALLOC;
948 948
949 949 /*
950 950 * Initialize the controller and ports.
951 951 */
952 952 status = ahci_initialize_controller(ahci_ctlp);
953 953 if (status != AHCI_SUCCESS) {
954 954 cmn_err(CE_WARN, "!ahci%d: HBA initialization failed",
955 955 instance);
956 956 goto err_out;
957 957 }
958 958
959 959 attach_state |= AHCI_ATTACH_STATE_HW_INIT;
960 960
961 961 /* Start one thread to check packet timeouts */
962 962 ahci_ctlp->ahcictl_timeout_id = timeout(
963 963 (void (*)(void *))ahci_watchdog_handler,
964 964 (caddr_t)ahci_ctlp, ahci_watchdog_tick);
965 965
966 966 attach_state |= AHCI_ATTACH_STATE_TIMEOUT_ENABLED;
967 967
968 968 if (ahci_register_sata_hba_tran(ahci_ctlp, cap_status)) {
969 969 cmn_err(CE_WARN, "!ahci%d: sata hba tran registration failed",
970 970 instance);
971 971 goto err_out;
972 972 }
973 973
974 974 /* Check all handles at the end of the attach operation. */
975 975 if (ahci_check_all_handle(ahci_ctlp) != DDI_SUCCESS) {
976 976 cmn_err(CE_WARN, "!ahci%d: invalid dma/acc handles",
977 977 instance);
978 978 goto err_out;
979 979 }
980 980
981 981 ahci_ctlp->ahcictl_flags &= ~AHCI_ATTACH;
982 982
983 983 AHCIDBG(AHCIDBG_INIT, ahci_ctlp, "ahci_attach success!", NULL);
984 984
985 985 return (DDI_SUCCESS);
986 986
987 987 err_out:
988 988 /* FMA message */
989 989 ahci_fm_ereport(ahci_ctlp, DDI_FM_DEVICE_NO_RESPONSE);
990 990 ddi_fm_service_impact(ahci_ctlp->ahcictl_dip, DDI_SERVICE_LOST);
991 991
992 992 if (attach_state & AHCI_ATTACH_STATE_TIMEOUT_ENABLED) {
993 993 mutex_enter(&ahci_ctlp->ahcictl_mutex);
994 994 (void) untimeout(ahci_ctlp->ahcictl_timeout_id);
995 995 ahci_ctlp->ahcictl_timeout_id = 0;
996 996 mutex_exit(&ahci_ctlp->ahcictl_mutex);
997 997 }
998 998
999 999 if (attach_state & AHCI_ATTACH_STATE_HW_INIT) {
1000 1000 ahci_uninitialize_controller(ahci_ctlp);
1001 1001 }
1002 1002
1003 1003 if (attach_state & AHCI_ATTACH_STATE_PORT_ALLOC) {
1004 1004 ahci_dealloc_ports_state(ahci_ctlp);
1005 1005 }
1006 1006
1007 1007 if (attach_state & AHCI_ATTACH_STATE_MUTEX_INIT) {
1008 1008 mutex_destroy(&ahci_ctlp->ahcictl_mutex);
1009 1009 }
1010 1010
1011 1011 if (attach_state & AHCI_ATTACH_STATE_INTR_ADDED) {
1012 1012 ahci_rem_intrs(ahci_ctlp);
1013 1013 }
1014 1014
1015 1015 if (attach_state & AHCI_ATTACH_STATE_PCICFG_SETUP) {
1016 1016 pci_config_teardown(&ahci_ctlp->ahcictl_pci_conf_handle);
1017 1017 }
1018 1018
1019 1019 if (attach_state & AHCI_ATTACH_STATE_REG_MAP) {
1020 1020 ddi_regs_map_free(&ahci_ctlp->ahcictl_ahci_acc_handle);
1021 1021 }
1022 1022
1023 1023 if (attach_state & AHCI_ATTACH_STATE_FMA) {
1024 1024 ahci_fm_fini(ahci_ctlp);
1025 1025 }
1026 1026
1027 1027 if (attach_state & AHCI_ATTACH_STATE_STATEP_ALLOC) {
1028 1028 ddi_soft_state_free(ahci_statep, instance);
1029 1029 }
1030 1030
1031 1031 return (DDI_FAILURE);
1032 1032 }
1033 1033
1034 1034 /*
1035 1035 * The detach entry point for dev_ops.
1036 1036 */
1037 1037 static int
1038 1038 ahci_detach(dev_info_t *dip, ddi_detach_cmd_t cmd)
1039 1039 {
1040 1040 ahci_ctl_t *ahci_ctlp;
1041 1041 int instance;
1042 1042 int ret;
1043 1043
1044 1044 instance = ddi_get_instance(dip);
1045 1045 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance);
1046 1046
1047 1047 AHCIDBG(AHCIDBG_ENTRY, ahci_ctlp, "ahci_detach enter", NULL);
1048 1048
1049 1049 switch (cmd) {
1050 1050 case DDI_DETACH:
1051 1051
1052 1052 /* disable the interrupts for an uninterrupted detach */
1053 1053 mutex_enter(&ahci_ctlp->ahcictl_mutex);
1054 1054 ahci_disable_all_intrs(ahci_ctlp);
1055 1055 mutex_exit(&ahci_ctlp->ahcictl_mutex);
1056 1056
1057 1057 /* unregister from the sata framework. */
1058 1058 ret = ahci_unregister_sata_hba_tran(ahci_ctlp);
1059 1059 if (ret != AHCI_SUCCESS) {
1060 1060 mutex_enter(&ahci_ctlp->ahcictl_mutex);
1061 1061 ahci_enable_all_intrs(ahci_ctlp);
1062 1062 mutex_exit(&ahci_ctlp->ahcictl_mutex);
1063 1063 return (DDI_FAILURE);
1064 1064 }
1065 1065
1066 1066 mutex_enter(&ahci_ctlp->ahcictl_mutex);
1067 1067
1068 1068 /* stop the watchdog handler */
1069 1069 (void) untimeout(ahci_ctlp->ahcictl_timeout_id);
1070 1070 ahci_ctlp->ahcictl_timeout_id = 0;
1071 1071
1072 1072 mutex_exit(&ahci_ctlp->ahcictl_mutex);
1073 1073
1074 1074 /* uninitialize the controller */
1075 1075 ahci_uninitialize_controller(ahci_ctlp);
1076 1076
1077 1077 /* remove the interrupts */
1078 1078 ahci_rem_intrs(ahci_ctlp);
1079 1079
1080 1080 /* deallocate the ports structures */
1081 1081 ahci_dealloc_ports_state(ahci_ctlp);
1082 1082
1083 1083 /* destroy mutex */
1084 1084 mutex_destroy(&ahci_ctlp->ahcictl_mutex);
1085 1085
1086 1086 /* teardown the pci config */
1087 1087 pci_config_teardown(&ahci_ctlp->ahcictl_pci_conf_handle);
1088 1088
1089 1089 /* remove the reg maps. */
1090 1090 ddi_regs_map_free(&ahci_ctlp->ahcictl_ahci_acc_handle);
1091 1091
1092 1092 /* release fma resource */
1093 1093 ahci_fm_fini(ahci_ctlp);
1094 1094
1095 1095 /* free the soft state. */
1096 1096 ddi_soft_state_free(ahci_statep, instance);
1097 1097
1098 1098 return (DDI_SUCCESS);
1099 1099
1100 1100 case DDI_SUSPEND:
1101 1101
1102 1102 /*
1103 1103 * The steps associated with suspension must include putting
1104 1104 * the underlying device into a quiescent state so that it
1105 1105 * will not generate interrupts or modify or access memory.
1106 1106 */
1107 1107 mutex_enter(&ahci_ctlp->ahcictl_mutex);
1108 1108 if (ahci_ctlp->ahcictl_flags & AHCI_SUSPEND) {
1109 1109 mutex_exit(&ahci_ctlp->ahcictl_mutex);
1110 1110 return (DDI_SUCCESS);
1111 1111 }
1112 1112
1113 1113 ahci_ctlp->ahcictl_flags |= AHCI_SUSPEND;
1114 1114
1115 1115 /* stop the watchdog handler */
1116 1116 if (ahci_ctlp->ahcictl_timeout_id) {
1117 1117 (void) untimeout(ahci_ctlp->ahcictl_timeout_id);
1118 1118 ahci_ctlp->ahcictl_timeout_id = 0;
1119 1119 }
1120 1120
1121 1121 mutex_exit(&ahci_ctlp->ahcictl_mutex);
1122 1122
1123 1123 /*
1124 1124 * drain the taskq
1125 1125 */
1126 1126 ahci_drain_ports_taskq(ahci_ctlp);
1127 1127
1128 1128 /*
1129 1129 * Disable the interrupts and stop all the ports.
1130 1130 */
1131 1131 ahci_uninitialize_controller(ahci_ctlp);
1132 1132
1133 1133 return (DDI_SUCCESS);
1134 1134
1135 1135 default:
↓ open down ↓ |
1101 lines elided |
↑ open up ↑ |
1136 1136 return (DDI_FAILURE);
1137 1137 }
1138 1138 }
1139 1139
1140 1140 /*
1141 1141 * The info entry point for dev_ops.
1142 1142 *
1143 1143 */
1144 1144 static int
1145 1145 ahci_getinfo(dev_info_t *dip, ddi_info_cmd_t infocmd,
1146 - void *arg, void **result)
1146 + void *arg, void **result)
1147 1147 {
1148 1148 #ifndef __lock_lint
1149 1149 _NOTE(ARGUNUSED(dip))
1150 1150 #endif /* __lock_lint */
1151 1151
1152 1152 ahci_ctl_t *ahci_ctlp;
1153 1153 int instance;
1154 1154 dev_t dev;
1155 1155
1156 1156 dev = (dev_t)arg;
1157 1157 instance = getminor(dev);
1158 1158
1159 1159 switch (infocmd) {
1160 1160 case DDI_INFO_DEVT2DEVINFO:
1161 1161 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance);
1162 1162 if (ahci_ctlp != NULL) {
1163 1163 *result = ahci_ctlp->ahcictl_dip;
1164 1164 return (DDI_SUCCESS);
1165 1165 } else {
1166 1166 *result = NULL;
1167 1167 return (DDI_FAILURE);
1168 1168 }
1169 1169 case DDI_INFO_DEVT2INSTANCE:
1170 1170 *(int *)result = instance;
1171 1171 break;
1172 1172 default:
1173 1173 break;
1174 1174 }
1175 1175
1176 1176 return (DDI_SUCCESS);
1177 1177 }
1178 1178
1179 1179 /*
1180 1180 * Registers the ahci with sata framework.
1181 1181 */
1182 1182 static int
1183 1183 ahci_register_sata_hba_tran(ahci_ctl_t *ahci_ctlp, uint32_t cap_status)
1184 1184 {
1185 1185 struct sata_hba_tran *sata_hba_tran;
1186 1186
1187 1187 AHCIDBG(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp,
1188 1188 "ahci_register_sata_hba_tran enter", NULL);
1189 1189
1190 1190 mutex_enter(&ahci_ctlp->ahcictl_mutex);
1191 1191
1192 1192 /* Allocate memory for the sata_hba_tran */
1193 1193 sata_hba_tran = kmem_zalloc(sizeof (sata_hba_tran_t), KM_SLEEP);
1194 1194
1195 1195 sata_hba_tran->sata_tran_hba_rev = SATA_TRAN_HBA_REV;
1196 1196 sata_hba_tran->sata_tran_hba_dip = ahci_ctlp->ahcictl_dip;
1197 1197 sata_hba_tran->sata_tran_hba_dma_attr =
1198 1198 &ahci_ctlp->ahcictl_buffer_dma_attr;
1199 1199
1200 1200 /* Report the number of implemented ports */
1201 1201 sata_hba_tran->sata_tran_hba_num_cports =
1202 1202 ahci_ctlp->ahcictl_num_implemented_ports;
1203 1203
1204 1204 /* Support ATAPI device */
1205 1205 sata_hba_tran->sata_tran_hba_features_support = SATA_CTLF_ATAPI;
1206 1206
1207 1207 /* Get the data transfer capability for PIO command by the HBA */
1208 1208 if (cap_status & AHCI_HBA_CAP_PMD) {
1209 1209 ahci_ctlp->ahcictl_cap |= AHCI_CAP_PIO_MDRQ;
1210 1210 AHCIDBG(AHCIDBG_INFO, ahci_ctlp, "HBA supports multiple "
1211 1211 "DRQ block data transfer for PIO command protocol", NULL);
1212 1212 }
1213 1213
1214 1214 /*
1215 1215 * According to the AHCI spec, the ATA/ATAPI-7 queued feature set
1216 1216 * is not supported by AHCI (including the READ QUEUED (EXT), WRITE
1217 1217 * QUEUED (EXT), and SERVICE commands). Queued operations are
1218 1218 * supported in AHCI using the READ FPDMA QUEUED and WRITE FPDMA
1219 1219 * QUEUED commands when the HBA and device support native command
1220 1220 * queuing(NCQ).
1221 1221 *
1222 1222 * SATA_CTLF_NCQ will be set to sata_tran_hba_features_support if the
1223 1223 * CAP register of the HBA indicates NCQ is supported.
1224 1224 *
1225 1225 * SATA_CTLF_NCQ cannot be set if AHCI_CAP_NO_MCMDLIST_NONQUEUE is
1226 1226 * set because the previous register content of PxCI can be re-written
1227 1227 * in the register write.
1228 1228 */
1229 1229 if ((cap_status & AHCI_HBA_CAP_SNCQ) &&
1230 1230 !(ahci_ctlp->ahcictl_cap & AHCI_CAP_NO_MCMDLIST_NONQUEUE)) {
1231 1231 sata_hba_tran->sata_tran_hba_features_support |= SATA_CTLF_NCQ;
1232 1232 ahci_ctlp->ahcictl_cap |= AHCI_CAP_NCQ;
1233 1233 AHCIDBG(AHCIDBG_INFO, ahci_ctlp, "HBA supports Native "
1234 1234 "Command Queuing", NULL);
1235 1235 }
1236 1236
1237 1237 /* Support port multiplier? */
1238 1238 if (cap_status & AHCI_HBA_CAP_SPM) {
1239 1239 sata_hba_tran->sata_tran_hba_features_support |=
1240 1240 SATA_CTLF_PORT_MULTIPLIER;
1241 1241
1242 1242 /* Support FIS-based switching for port multiplier? */
1243 1243 if (cap_status & AHCI_HBA_CAP_FBSS) {
1244 1244 sata_hba_tran->sata_tran_hba_features_support |=
1245 1245 SATA_CTLF_PMULT_FBS;
1246 1246 }
1247 1247 }
1248 1248
1249 1249 /* Report the number of command slots */
1250 1250 sata_hba_tran->sata_tran_hba_qdepth = ahci_ctlp->ahcictl_num_cmd_slots;
1251 1251
1252 1252 sata_hba_tran->sata_tran_probe_port = ahci_tran_probe_port;
1253 1253 sata_hba_tran->sata_tran_start = ahci_tran_start;
1254 1254 sata_hba_tran->sata_tran_abort = ahci_tran_abort;
1255 1255 sata_hba_tran->sata_tran_reset_dport = ahci_tran_reset_dport;
1256 1256 sata_hba_tran->sata_tran_hotplug_ops = &ahci_tran_hotplug_ops;
1257 1257 #ifdef __lock_lint
1258 1258 sata_hba_tran->sata_tran_selftest = ahci_selftest;
1259 1259 #endif
1260 1260 /*
1261 1261 * When SATA framework adds support for pwrmgt the
1262 1262 * pwrmgt_ops needs to be updated
1263 1263 */
1264 1264 sata_hba_tran->sata_tran_pwrmgt_ops = NULL;
1265 1265 sata_hba_tran->sata_tran_ioctl = NULL;
1266 1266
1267 1267 ahci_ctlp->ahcictl_sata_hba_tran = sata_hba_tran;
1268 1268
1269 1269 mutex_exit(&ahci_ctlp->ahcictl_mutex);
1270 1270
1271 1271 /* Attach it to SATA framework */
1272 1272 if (sata_hba_attach(ahci_ctlp->ahcictl_dip, sata_hba_tran, DDI_ATTACH)
1273 1273 != DDI_SUCCESS) {
1274 1274 kmem_free((void *)sata_hba_tran, sizeof (sata_hba_tran_t));
1275 1275 mutex_enter(&ahci_ctlp->ahcictl_mutex);
1276 1276 ahci_ctlp->ahcictl_sata_hba_tran = NULL;
1277 1277 mutex_exit(&ahci_ctlp->ahcictl_mutex);
1278 1278 return (AHCI_FAILURE);
1279 1279 }
1280 1280
1281 1281 return (AHCI_SUCCESS);
1282 1282 }
1283 1283
1284 1284 /*
1285 1285 * Unregisters the ahci with sata framework.
1286 1286 */
1287 1287 static int
1288 1288 ahci_unregister_sata_hba_tran(ahci_ctl_t *ahci_ctlp)
1289 1289 {
1290 1290 AHCIDBG(AHCIDBG_ENTRY, ahci_ctlp,
1291 1291 "ahci_unregister_sata_hba_tran enter", NULL);
1292 1292
1293 1293 /* Detach from the SATA framework. */
1294 1294 if (sata_hba_detach(ahci_ctlp->ahcictl_dip, DDI_DETACH) !=
1295 1295 DDI_SUCCESS) {
1296 1296 return (AHCI_FAILURE);
1297 1297 }
1298 1298
1299 1299 /* Deallocate sata_hba_tran. */
1300 1300 kmem_free((void *)ahci_ctlp->ahcictl_sata_hba_tran,
1301 1301 sizeof (sata_hba_tran_t));
1302 1302
1303 1303 mutex_enter(&ahci_ctlp->ahcictl_mutex);
1304 1304 ahci_ctlp->ahcictl_sata_hba_tran = NULL;
1305 1305 mutex_exit(&ahci_ctlp->ahcictl_mutex);
1306 1306
1307 1307 return (AHCI_SUCCESS);
1308 1308 }
1309 1309
1310 1310 #define SET_PORTSTR(str, addrp) \
1311 1311 if (AHCI_ADDR_IS_PORT(addrp)) \
1312 1312 (void) sprintf((str), "%d", (addrp)->aa_port); \
1313 1313 else if (AHCI_ADDR_IS_PMULT(addrp)) \
1314 1314 (void) sprintf((str), "%d (pmult)", (addrp)->aa_port); \
1315 1315 else \
1316 1316 (void) sprintf((str), "%d:%d", (addrp)->aa_port, \
1317 1317 (addrp)->aa_pmport);
1318 1318
1319 1319 /*
1320 1320 * ahci_tran_probe_port is called by SATA framework. It returns port state,
1321 1321 * port status registers and an attached device type via sata_device
1322 1322 * structure.
1323 1323 *
1324 1324 * We return the cached information from a previous hardware probe. The
1325 1325 * actual hardware probing itself was done either from within
1326 1326 * ahci_initialize_controller() during the driver attach or from a phy
1327 1327 * ready change interrupt handler.
1328 1328 */
1329 1329 static int
1330 1330 ahci_tran_probe_port(dev_info_t *dip, sata_device_t *sd)
1331 1331 {
1332 1332 ahci_ctl_t *ahci_ctlp;
1333 1333 ahci_port_t *ahci_portp;
1334 1334 ahci_addr_t addr, pmult_addr;
1335 1335 uint8_t cport = sd->satadev_addr.cport;
1336 1336 char portstr[10];
1337 1337 uint8_t device_type;
1338 1338 uint32_t port_state;
1339 1339 uint8_t port;
1340 1340 int rval = SATA_SUCCESS, rval_init;
1341 1341
1342 1342 ahci_ctlp = ddi_get_soft_state(ahci_statep, ddi_get_instance(dip));
1343 1343 port = ahci_ctlp->ahcictl_cport_to_port[cport];
1344 1344
1345 1345 ahci_portp = ahci_ctlp->ahcictl_ports[port];
1346 1346
1347 1347 mutex_enter(&ahci_portp->ahciport_mutex);
1348 1348
1349 1349 ahci_get_ahci_addr(ahci_ctlp, sd, &addr);
1350 1350 ASSERT(AHCI_ADDR_IS_VALID(&addr));
1351 1351 SET_PORTSTR(portstr, &addr);
1352 1352
1353 1353 AHCIDBG(AHCIDBG_ENTRY, ahci_ctlp,
1354 1354 "ahci_tran_probe_port enter: port %s", portstr);
1355 1355
1356 1356 if ((AHCI_ADDR_IS_PMULT(&addr) || AHCI_ADDR_IS_PMPORT(&addr)) &&
1357 1357 (ahci_portp->ahciport_device_type != SATA_DTYPE_PMULT ||
1358 1358 ahci_portp->ahciport_pmult_info == NULL)) {
1359 1359 /* port mutliplier is removed. */
1360 1360 AHCIDBG(AHCIDBG_PMULT, ahci_ctlp,
1361 1361 "ahci_tran_probe_port: "
1362 1362 "pmult is removed from port %s", portstr);
1363 1363 mutex_exit(&ahci_portp->ahciport_mutex);
1364 1364 return (SATA_FAILURE);
1365 1365 }
1366 1366
1367 1367 /*
1368 1368 * The sata_device may refer to
1369 1369 * 1. A controller port.
1370 1370 * A controller port should be ready here.
1371 1371 * 2. A port multiplier.
1372 1372 * SATA_ADDR_PMULT_SPEC - if it is not initialized yet, initialize
1373 1373 * it and register the port multiplier to the framework.
1374 1374 * SATA_ADDR_PMULT - check the status of all its device ports.
1375 1375 * 3. A port multiplier port.
1376 1376 * If it has not been initialized, initialized it.
1377 1377 *
1378 1378 * A port multiplier or a port multiplier port may require some
1379 1379 * initialization because we cannot do these time-consuming jobs in an
1380 1380 * interrupt context.
1381 1381 */
1382 1382 if (sd->satadev_addr.qual & SATA_ADDR_PMULT_SPEC) {
1383 1383 AHCI_ADDR_SET_PMULT(&pmult_addr, port);
1384 1384 /* Initialize registers on a port multiplier */
1385 1385 rval_init = ahci_initialize_pmult(ahci_ctlp,
1386 1386 ahci_portp, &pmult_addr, sd);
1387 1387 if (rval_init != AHCI_SUCCESS) {
1388 1388 AHCIDBG(AHCIDBG_PMULT, ahci_ctlp,
1389 1389 "ahci_tran_probe_port: "
1390 1390 "pmult initialization failed.", NULL);
1391 1391 mutex_exit(&ahci_portp->ahciport_mutex);
1392 1392 return (SATA_FAILURE);
1393 1393 }
1394 1394 } else if (sd->satadev_addr.qual & SATA_ADDR_PMULT) {
1395 1395 /* Check pmports hotplug events */
1396 1396 (void) ahci_probe_pmult(ahci_ctlp, ahci_portp, &addr);
1397 1397 } else if (sd->satadev_addr.qual & (SATA_ADDR_PMPORT |
1398 1398 SATA_ADDR_DPMPORT)) {
1399 1399 if (ahci_probe_pmport(ahci_ctlp, ahci_portp,
1400 1400 &addr, sd) != AHCI_SUCCESS) {
1401 1401 rval = SATA_FAILURE;
1402 1402 goto out;
1403 1403 }
1404 1404 }
1405 1405
1406 1406 /* Update port state and device type */
1407 1407 port_state = AHCIPORT_GET_STATE(ahci_portp, &addr);
1408 1408
1409 1409 switch (port_state) {
1410 1410
1411 1411 case SATA_PSTATE_FAILED:
1412 1412 sd->satadev_state = SATA_PSTATE_FAILED;
1413 1413 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
1414 1414 "ahci_tran_probe_port: port %s PORT FAILED", portstr);
1415 1415 goto out;
1416 1416
1417 1417 case SATA_PSTATE_SHUTDOWN:
1418 1418 sd->satadev_state = SATA_PSTATE_SHUTDOWN;
1419 1419 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
1420 1420 "ahci_tran_probe_port: port %s PORT SHUTDOWN", portstr);
1421 1421 goto out;
1422 1422
1423 1423 case SATA_PSTATE_PWROFF:
1424 1424 sd->satadev_state = SATA_PSTATE_PWROFF;
1425 1425 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
1426 1426 "ahci_tran_probe_port: port %s PORT PWROFF", portstr);
1427 1427 goto out;
1428 1428
1429 1429 case SATA_PSTATE_PWRON:
1430 1430 sd->satadev_state = SATA_PSTATE_PWRON;
1431 1431 AHCIDBG(AHCIDBG_INFO, ahci_ctlp,
1432 1432 "ahci_tran_probe_port: port %s PORT PWRON", portstr);
1433 1433 break;
1434 1434
1435 1435 default:
1436 1436 sd->satadev_state = port_state;
1437 1437 AHCIDBG(AHCIDBG_INFO, ahci_ctlp,
1438 1438 "ahci_tran_probe_port: port %s PORT NORMAL %x",
1439 1439 portstr, port_state);
1440 1440 break;
1441 1441 }
1442 1442
1443 1443 device_type = AHCIPORT_GET_DEV_TYPE(ahci_portp, &addr);
1444 1444
1445 1445 switch (device_type) {
1446 1446
1447 1447 case SATA_DTYPE_ATADISK:
1448 1448 sd->satadev_type = SATA_DTYPE_ATADISK;
1449 1449 AHCIDBG(AHCIDBG_INFO, ahci_ctlp,
1450 1450 "ahci_tran_probe_port: port %s DISK found", portstr);
1451 1451 break;
1452 1452
1453 1453 case SATA_DTYPE_ATAPI:
1454 1454 /*
1455 1455 * HBA driver only knows it's an ATAPI device, and don't know
1456 1456 * it's CD/DVD, tape or ATAPI disk because the ATAPI device
1457 1457 * type need to be determined by checking IDENTIFY PACKET
1458 1458 * DEVICE data
1459 1459 */
1460 1460 sd->satadev_type = SATA_DTYPE_ATAPI;
1461 1461 AHCIDBG(AHCIDBG_INFO, ahci_ctlp,
1462 1462 "ahci_tran_probe_port: port %s ATAPI found", portstr);
1463 1463 break;
1464 1464
1465 1465 case SATA_DTYPE_PMULT:
1466 1466 ASSERT(AHCI_ADDR_IS_PORT(&addr) || AHCI_ADDR_IS_PMULT(&addr));
1467 1467 sd->satadev_type = SATA_DTYPE_PMULT;
1468 1468
1469 1469 /* Update the number of pmports. */
1470 1470 ASSERT(ahci_portp->ahciport_pmult_info != NULL);
1471 1471 sd->satadev_add_info = ahci_portp->
1472 1472 ahciport_pmult_info->ahcipmi_num_dev_ports;
1473 1473
1474 1474 AHCIDBG(AHCIDBG_INFO, ahci_ctlp,
1475 1475 "ahci_tran_probe_port: port %s Port Multiplier found",
1476 1476 portstr);
1477 1477 break;
1478 1478
1479 1479 case SATA_DTYPE_UNKNOWN:
1480 1480 sd->satadev_type = SATA_DTYPE_UNKNOWN;
1481 1481 AHCIDBG(AHCIDBG_INFO, ahci_ctlp,
1482 1482 "ahci_tran_probe_port: port %s Unknown device found",
1483 1483 portstr);
1484 1484 break;
1485 1485
1486 1486 default:
1487 1487 /* we don't support any other device types */
1488 1488 sd->satadev_type = SATA_DTYPE_NONE;
1489 1489 AHCIDBG(AHCIDBG_INFO, ahci_ctlp,
1490 1490 "ahci_tran_probe_port: port %s No device found", portstr);
1491 1491 break;
1492 1492 }
1493 1493
1494 1494 out:
1495 1495 /* Register update only fails while probing a pmult/pmport */
1496 1496 if (AHCI_ADDR_IS_PORT(&addr) || AHCI_ADDR_IS_PMULT(&addr)) {
1497 1497 ahci_update_sata_registers(ahci_ctlp, port, sd);
1498 1498 } else if (AHCI_ADDR_IS_PMPORT(&addr)) {
1499 1499 if (port_state & SATA_STATE_READY)
1500 1500 if (ahci_update_pmult_pscr(ahci_ctlp,
1501 1501 &addr, sd) != AHCI_SUCCESS)
1502 1502 rval = SATA_FAILURE;
1503 1503 }
1504 1504
1505 1505 /* Check handles for the sata registers access */
1506 1506 if ((ahci_check_ctl_handle(ahci_ctlp) != DDI_SUCCESS) ||
1507 1507 (ahci_check_port_handle(ahci_ctlp, port) != DDI_SUCCESS)) {
1508 1508 ddi_fm_service_impact(ahci_ctlp->ahcictl_dip,
1509 1509 DDI_SERVICE_UNAFFECTED);
1510 1510 rval = SATA_FAILURE;
1511 1511 }
1512 1512
1513 1513 mutex_exit(&ahci_portp->ahciport_mutex);
1514 1514 return (rval);
1515 1515 }
1516 1516
1517 1517 /*
1518 1518 * There are four operation modes in sata framework:
1519 1519 * SATA_OPMODE_INTERRUPTS
1520 1520 * SATA_OPMODE_POLLING
1521 1521 * SATA_OPMODE_ASYNCH
1522 1522 * SATA_OPMODE_SYNCH
1523 1523 *
1524 1524 * Their combined meanings as following:
1525 1525 *
1526 1526 * SATA_OPMODE_SYNCH
1527 1527 * The command has to be completed before sata_tran_start functions returns.
1528 1528 * Either interrupts or polling could be used - it's up to the driver.
1529 1529 * Mode used currently for internal, sata-module initiated operations.
1530 1530 *
1531 1531 * SATA_OPMODE_SYNCH | SATA_OPMODE_INTERRUPTS
1532 1532 * It is the same as the one above.
1533 1533 *
1534 1534 * SATA_OPMODE_SYNCH | SATA_OPMODE_POLLING
1535 1535 * The command has to be completed before sata_tran_start function returns.
1536 1536 * No interrupt used, polling only. This should be the mode used for scsi
1537 1537 * packets with FLAG_NOINTR.
1538 1538 *
1539 1539 * SATA_OPMODE_ASYNCH | SATA_OPMODE_INTERRUPTS
1540 1540 * The command may be queued (callback function specified). Interrupts could
1541 1541 * be used. It's normal operation mode.
1542 1542 */
1543 1543 /*
1544 1544 * Called by sata framework to transport a sata packet down stream.
1545 1545 */
1546 1546 static int
1547 1547 ahci_tran_start(dev_info_t *dip, sata_pkt_t *spkt)
1548 1548 {
1549 1549 ahci_ctl_t *ahci_ctlp;
1550 1550 ahci_port_t *ahci_portp;
1551 1551 ahci_addr_t addr;
1552 1552 uint8_t cport = spkt->satapkt_device.satadev_addr.cport;
1553 1553 uint8_t port;
1554 1554 char portstr[10];
1555 1555
1556 1556 ahci_ctlp = ddi_get_soft_state(ahci_statep, ddi_get_instance(dip));
1557 1557 port = ahci_ctlp->ahcictl_cport_to_port[cport];
1558 1558
1559 1559 AHCIDBG(AHCIDBG_ENTRY, ahci_ctlp,
1560 1560 "ahci_tran_start enter: cport %d satapkt 0x%p",
1561 1561 cport, (void *)spkt);
1562 1562
1563 1563 ahci_portp = ahci_ctlp->ahcictl_ports[port];
1564 1564
1565 1565 mutex_enter(&ahci_portp->ahciport_mutex);
1566 1566 ahci_get_ahci_addr(ahci_ctlp, &spkt->satapkt_device, &addr);
1567 1567 SET_PORTSTR(portstr, &addr);
1568 1568
1569 1569 /* Sanity check */
1570 1570 if (AHCI_ADDR_IS_PMPORT(&addr)) {
1571 1571 if (ahci_portp->ahciport_device_type != SATA_DTYPE_PMULT ||
1572 1572 ahci_portp->ahciport_pmult_info == NULL) {
1573 1573
1574 1574 spkt->satapkt_reason = SATA_PKT_PORT_ERROR;
1575 1575 spkt->satapkt_device.satadev_type = SATA_DTYPE_NONE;
1576 1576 spkt->satapkt_device.satadev_state = SATA_STATE_UNKNOWN;
1577 1577 ahci_update_sata_registers(ahci_ctlp, port,
1578 1578 &spkt->satapkt_device);
1579 1579 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
1580 1580 "ahci_tran_start returning PORT_ERROR while "
1581 1581 "pmult removed: port: %s", portstr);
1582 1582 mutex_exit(&ahci_portp->ahciport_mutex);
1583 1583 return (SATA_TRAN_PORT_ERROR);
1584 1584 }
1585 1585
1586 1586 if (!(AHCIPORT_GET_STATE(ahci_portp, &addr) &
1587 1587 SATA_STATE_READY)) {
1588 1588 if (!ddi_in_panic() ||
1589 1589 ahci_initialize_pmport(ahci_ctlp,
1590 1590 ahci_portp, &addr) != AHCI_SUCCESS) {
1591 1591 spkt->satapkt_reason = SATA_PKT_PORT_ERROR;
1592 1592 spkt->satapkt_device.satadev_type =
1593 1593 AHCIPORT_GET_DEV_TYPE(ahci_portp, &addr);
1594 1594 spkt->satapkt_device.satadev_state =
1595 1595 AHCIPORT_GET_STATE(ahci_portp, &addr);
1596 1596 ahci_update_sata_registers(ahci_ctlp, port,
1597 1597 &spkt->satapkt_device);
1598 1598 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
1599 1599 "ahci_tran_start returning PORT_ERROR "
1600 1600 "while sub-link is not initialized "
1601 1601 "at port: %s", portstr);
1602 1602 mutex_exit(&ahci_portp->ahciport_mutex);
1603 1603 return (SATA_TRAN_PORT_ERROR);
1604 1604 }
1605 1605 }
1606 1606 }
1607 1607
1608 1608 if (AHCIPORT_GET_STATE(ahci_portp, &addr) & SATA_PSTATE_FAILED ||
1609 1609 AHCIPORT_GET_STATE(ahci_portp, &addr) & SATA_PSTATE_SHUTDOWN||
1610 1610 AHCIPORT_GET_STATE(ahci_portp, &addr) & SATA_PSTATE_PWROFF) {
1611 1611 /*
1612 1612 * In case the target driver would send the packet before
1613 1613 * sata framework can have the opportunity to process those
1614 1614 * event reports.
1615 1615 */
1616 1616 spkt->satapkt_reason = SATA_PKT_PORT_ERROR;
1617 1617 spkt->satapkt_device.satadev_state =
1618 1618 ahci_portp->ahciport_port_state;
1619 1619 ahci_update_sata_registers(ahci_ctlp, port,
1620 1620 &spkt->satapkt_device);
1621 1621 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
1622 1622 "ahci_tran_start returning PORT_ERROR while "
1623 1623 "port in FAILED/SHUTDOWN/PWROFF state: "
1624 1624 "port: %s", portstr);
1625 1625 mutex_exit(&ahci_portp->ahciport_mutex);
1626 1626 return (SATA_TRAN_PORT_ERROR);
1627 1627 }
1628 1628
1629 1629 if (AHCIPORT_GET_DEV_TYPE(ahci_portp, &addr) == SATA_DTYPE_NONE) {
1630 1630 /*
1631 1631 * ahci_intr_phyrdy_change() may have rendered it to
1632 1632 * SATA_DTYPE_NONE.
1633 1633 */
1634 1634 spkt->satapkt_reason = SATA_PKT_PORT_ERROR;
1635 1635 spkt->satapkt_device.satadev_type = SATA_DTYPE_NONE;
1636 1636 spkt->satapkt_device.satadev_state =
1637 1637 ahci_portp->ahciport_port_state;
1638 1638 ahci_update_sata_registers(ahci_ctlp, port,
1639 1639 &spkt->satapkt_device);
1640 1640 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
1641 1641 "ahci_tran_start returning PORT_ERROR while "
1642 1642 "no device attached: port: %s", portstr);
1643 1643 mutex_exit(&ahci_portp->ahciport_mutex);
1644 1644 return (SATA_TRAN_PORT_ERROR);
1645 1645 }
1646 1646
1647 1647 /* R/W PMULT command will occupy the whole HBA port */
1648 1648 if (RDWR_PMULT_CMD_IN_PROGRESS(ahci_portp)) {
1649 1649 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
1650 1650 "ahci_tran_start returning BUSY while "
1651 1651 "executing READ/WRITE PORT-MULT command: "
1652 1652 "port: %s", portstr);
1653 1653 spkt->satapkt_reason = SATA_PKT_BUSY;
1654 1654 mutex_exit(&ahci_portp->ahciport_mutex);
1655 1655 return (SATA_TRAN_BUSY);
1656 1656 }
1657 1657
1658 1658 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_HOTPLUG) {
1659 1659 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
1660 1660 "ahci_tran_start returning BUSY while "
1661 1661 "hot-plug in progress: port: %s", portstr);
1662 1662 spkt->satapkt_reason = SATA_PKT_BUSY;
1663 1663 mutex_exit(&ahci_portp->ahciport_mutex);
1664 1664 return (SATA_TRAN_BUSY);
1665 1665 }
1666 1666
1667 1667 /*
1668 1668 * SATA HBA driver should remember that a device was reset and it
1669 1669 * is supposed to reject any packets which do not specify either
1670 1670 * SATA_IGNORE_DEV_RESET_STATE or SATA_CLEAR_DEV_RESET_STATE.
1671 1671 *
1672 1672 * This is to prevent a race condition when a device was arbitrarily
1673 1673 * reset by the HBA driver (and lost it's setting) and a target
1674 1674 * driver sending some commands to a device before the sata framework
1675 1675 * has a chance to restore the device setting (such as cache enable/
1676 1676 * disable or other resettable stuff).
1677 1677 */
1678 1678 /*
1679 1679 * It is unnecessary to use specific flags to indicate
1680 1680 * reset_in_progress for a pmport. While mopping, all command will be
1681 1681 * mopped so that the entire HBA port is being dealt as a single
1682 1682 * object.
1683 1683 */
1684 1684 if (spkt->satapkt_cmd.satacmd_flags.sata_clear_dev_reset) {
1685 1685 ahci_portp->ahciport_reset_in_progress = 0;
1686 1686 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
1687 1687 "ahci_tran_start [CLEAR] the "
1688 1688 "reset_in_progress for port: %d", port);
1689 1689 }
1690 1690
1691 1691 if (ahci_portp->ahciport_reset_in_progress &&
1692 1692 ! spkt->satapkt_cmd.satacmd_flags.sata_ignore_dev_reset &&
1693 1693 ! ddi_in_panic()) {
1694 1694 spkt->satapkt_reason = SATA_PKT_BUSY;
1695 1695 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
1696 1696 "ahci_tran_start returning BUSY while "
1697 1697 "reset in progress: port: %d", port);
1698 1698 mutex_exit(&ahci_portp->ahciport_mutex);
1699 1699 return (SATA_TRAN_BUSY);
1700 1700 }
1701 1701
1702 1702 #ifdef AHCI_DEBUG
1703 1703 if (spkt->satapkt_cmd.satacmd_flags.sata_ignore_dev_reset) {
1704 1704 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
1705 1705 "ahci_tran_start: packet 0x%p [PASSTHRU] at port %d",
1706 1706 spkt, port);
1707 1707 }
1708 1708 #endif
1709 1709
1710 1710 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) {
1711 1711 spkt->satapkt_reason = SATA_PKT_BUSY;
1712 1712 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
1713 1713 "ahci_tran_start returning BUSY while "
1714 1714 "mopping in progress: port: %d", port);
1715 1715 mutex_exit(&ahci_portp->ahciport_mutex);
1716 1716 return (SATA_TRAN_BUSY);
1717 1717 }
1718 1718
1719 1719 if (ahci_check_ctl_handle(ahci_ctlp) != DDI_SUCCESS) {
1720 1720 ddi_fm_service_impact(ahci_ctlp->ahcictl_dip,
1721 1721 DDI_SERVICE_UNAFFECTED);
1722 1722 mutex_exit(&ahci_portp->ahciport_mutex);
1723 1723 return (SATA_TRAN_BUSY);
1724 1724 }
1725 1725
1726 1726 if (spkt->satapkt_op_mode &
1727 1727 (SATA_OPMODE_SYNCH | SATA_OPMODE_POLLING)) {
1728 1728 /*
1729 1729 * If a SYNC command to be executed in interrupt context,
1730 1730 * bounce it back to sata module.
1731 1731 */
1732 1732 if (!(spkt->satapkt_op_mode & SATA_OPMODE_POLLING) &&
1733 1733 servicing_interrupt()) {
1734 1734 spkt->satapkt_reason = SATA_PKT_BUSY;
1735 1735 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
1736 1736 "ahci_tran_start returning BUSY while "
1737 1737 "sending SYNC mode under interrupt context: "
1738 1738 "port : %d", port);
1739 1739 mutex_exit(&ahci_portp->ahciport_mutex);
1740 1740 return (SATA_TRAN_BUSY);
1741 1741 }
1742 1742
1743 1743 /* We need to do the sync start now */
1744 1744 if (ahci_do_sync_start(ahci_ctlp, ahci_portp, &addr,
1745 1745 spkt) == AHCI_FAILURE) {
1746 1746 goto fail_out;
1747 1747 }
1748 1748 } else {
1749 1749 /* Async start, using interrupt */
1750 1750 if (ahci_deliver_satapkt(ahci_ctlp, ahci_portp, &addr, spkt)
1751 1751 == AHCI_FAILURE) {
1752 1752 spkt->satapkt_reason = SATA_PKT_QUEUE_FULL;
1753 1753 goto fail_out;
1754 1754 }
1755 1755 }
1756 1756
1757 1757 AHCIDBG(AHCIDBG_INFO, ahci_ctlp, "ahci_tran_start "
1758 1758 "sata tran accepted: port %s", portstr);
1759 1759
1760 1760 mutex_exit(&ahci_portp->ahciport_mutex);
1761 1761 return (SATA_TRAN_ACCEPTED);
1762 1762
1763 1763 fail_out:
1764 1764 /*
1765 1765 * Failed to deliver packet to the controller.
1766 1766 * Check if it's caused by invalid handles.
1767 1767 */
1768 1768 if (ahci_check_ctl_handle(ahci_ctlp) != DDI_SUCCESS ||
1769 1769 ahci_check_port_handle(ahci_ctlp, port) != DDI_SUCCESS) {
1770 1770 spkt->satapkt_device.satadev_type =
1771 1771 AHCIPORT_GET_DEV_TYPE(ahci_portp, &addr);
1772 1772 spkt->satapkt_device.satadev_state =
1773 1773 AHCIPORT_GET_STATE(ahci_portp, &addr);
1774 1774 spkt->satapkt_reason = SATA_PKT_DEV_ERROR;
1775 1775 mutex_exit(&ahci_portp->ahciport_mutex);
1776 1776 return (SATA_TRAN_PORT_ERROR);
1777 1777 }
1778 1778
1779 1779 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp, "ahci_tran_start "
1780 1780 "return QUEUE_FULL: port %d", port);
1781 1781 mutex_exit(&ahci_portp->ahciport_mutex);
1782 1782 return (SATA_TRAN_QUEUE_FULL);
1783 1783 }
1784 1784
1785 1785 /*
1786 1786 * SATA_OPMODE_SYNCH flag is set
1787 1787 *
1788 1788 * If SATA_OPMODE_POLLING flag is set, then we must poll the command
1789 1789 * without interrupt, otherwise we can still use the interrupt.
1790 1790 */
1791 1791 static int
1792 1792 ahci_do_sync_start(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp,
1793 1793 ahci_addr_t *addrp, sata_pkt_t *spkt)
1794 1794 {
1795 1795 int pkt_timeout_ticks;
1796 1796 uint32_t timeout_tags;
1797 1797 int rval;
1798 1798 int instance = ddi_get_instance(ahci_ctlp->ahcictl_dip);
1799 1799 uint8_t port = addrp->aa_port;
1800 1800
1801 1801 ASSERT(MUTEX_HELD(&ahci_portp->ahciport_mutex));
1802 1802
1803 1803 AHCIDBG(AHCIDBG_ENTRY, ahci_ctlp, "ahci_do_sync_start enter: "
1804 1804 "port %d:%d spkt 0x%p", port, addrp->aa_pmport, spkt);
1805 1805
1806 1806 if (spkt->satapkt_op_mode & SATA_OPMODE_POLLING) {
1807 1807 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_POLLING;
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1808 1808 if ((rval = ahci_deliver_satapkt(ahci_ctlp, ahci_portp,
1809 1809 addrp, spkt)) == AHCI_FAILURE) {
1810 1810 ahci_portp->ahciport_flags &= ~AHCI_PORT_FLAG_POLLING;
1811 1811 return (rval);
1812 1812 }
1813 1813
1814 1814 pkt_timeout_ticks =
1815 1815 drv_usectohz((clock_t)spkt->satapkt_time * 1000000);
1816 1816
1817 1817 while (spkt->satapkt_reason == SATA_PKT_BUSY) {
1818 - mutex_exit(&ahci_portp->ahciport_mutex);
1819 -
1820 1818 /* Simulate the interrupt */
1819 + mutex_exit(&ahci_portp->ahciport_mutex);
1821 1820 ahci_port_intr(ahci_ctlp, ahci_portp, port);
1821 + mutex_enter(&ahci_portp->ahciport_mutex);
1822 1822
1823 - drv_usecwait(AHCI_10MS_USECS);
1823 + if (spkt->satapkt_reason != SATA_PKT_BUSY)
1824 + break;
1824 1825
1826 + mutex_exit(&ahci_portp->ahciport_mutex);
1827 + drv_usecwait(AHCI_1MS_USECS);
1825 1828 mutex_enter(&ahci_portp->ahciport_mutex);
1826 - pkt_timeout_ticks -= AHCI_10MS_TICKS;
1829 +
1830 + pkt_timeout_ticks -= AHCI_1MS_TICKS;
1827 1831 if (pkt_timeout_ticks < 0) {
1828 1832 cmn_err(CE_WARN, "!ahci%d: ahci_do_sync_start "
1829 1833 "port %d satapkt 0x%p timed out\n",
1830 1834 instance, port, (void *)spkt);
1831 1835 timeout_tags = (0x1 << rval);
1832 1836 mutex_exit(&ahci_portp->ahciport_mutex);
1833 1837 ahci_timeout_pkts(ahci_ctlp, ahci_portp,
1834 1838 port, timeout_tags);
1835 1839 mutex_enter(&ahci_portp->ahciport_mutex);
1836 1840 }
1837 1841 }
1842 +
1838 1843 ahci_portp->ahciport_flags &= ~AHCI_PORT_FLAG_POLLING;
1839 1844 return (AHCI_SUCCESS);
1840 1845
1841 1846 } else {
1842 1847 if ((rval = ahci_deliver_satapkt(ahci_ctlp, ahci_portp,
1843 1848 addrp, spkt)) == AHCI_FAILURE)
1844 1849 return (rval);
1845 1850
1846 1851 #if AHCI_DEBUG
1847 1852 /*
1848 1853 * Note that the driver always uses the slot 0 to deliver
1849 1854 * REQUEST SENSE or READ LOG EXT command
1850 1855 */
1851 1856 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp))
1852 1857 ASSERT(rval == 0);
1853 1858 #endif
1854 1859
1855 1860 while (spkt->satapkt_reason == SATA_PKT_BUSY)
1856 1861 cv_wait(&ahci_portp->ahciport_cv,
1857 1862 &ahci_portp->ahciport_mutex);
1858 1863
1859 1864 return (AHCI_SUCCESS);
1860 1865 }
1861 1866 }
1862 1867
1863 1868 /*
1864 1869 * Searches for and claims a free command slot.
1865 1870 *
1866 1871 * Returns value:
1867 1872 *
1868 1873 * AHCI_FAILURE returned only if
1869 1874 * 1. No empty slot left
1870 1875 * 2. Non-queued command requested while queued command(s) is outstanding
1871 1876 * 3. Queued command requested while non-queued command(s) is outstanding
1872 1877 * 4. HBA doesn't support multiple-use of command list while already a
1873 1878 * non-queued command is oustanding
1874 1879 * 5. Queued command requested while some queued command(s) has been
1875 1880 * outstanding on a different port multiplier port. (AHCI spec 1.2,
1876 1881 * 9.1.2)
1877 1882 *
1878 1883 * claimed slot number returned if succeeded
1879 1884 *
1880 1885 * NOTE: it will always return slot 0 for following commands to simplify the
1881 1886 * algorithm.
1882 1887 * 1. REQUEST SENSE or READ LOG EXT command during error recovery process
1883 1888 * 2. READ/WRITE PORTMULT command
1884 1889 */
1885 1890 static int
1886 1891 ahci_claim_free_slot(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp,
1887 1892 ahci_addr_t *addrp, int command_type)
1888 1893 {
1889 1894 uint32_t port_cmd_issue;
1890 1895 uint32_t free_slots;
1891 1896 int slot;
1892 1897
1893 1898 ASSERT(MUTEX_HELD(&ahci_portp->ahciport_mutex));
1894 1899
1895 1900 AHCIDBG(AHCIDBG_ENTRY, ahci_ctlp, "ahci_claim_free_slot enter "
1896 1901 "ahciport_pending_tags = 0x%x "
1897 1902 "ahciport_pending_ncq_tags = 0x%x",
1898 1903 ahci_portp->ahciport_pending_tags,
1899 1904 ahci_portp->ahciport_pending_ncq_tags);
1900 1905
1901 1906 /*
1902 1907 * According to the AHCI spec, system software is responsible to
1903 1908 * ensure that queued and non-queued commands are not mixed in
1904 1909 * the command list.
1905 1910 */
1906 1911 if (command_type == AHCI_NON_NCQ_CMD) {
1907 1912 /* Non-NCQ command request */
1908 1913 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) {
1909 1914 AHCIDBG(AHCIDBG_INFO|AHCIDBG_NCQ, ahci_ctlp,
1910 1915 "ahci_claim_free_slot: there is still pending "
1911 1916 "queued command(s) in the command list, "
1912 1917 "so no available slot for the non-queued "
1913 1918 "command", NULL);
1914 1919 return (AHCI_FAILURE);
1915 1920 }
1916 1921 if (RDWR_PMULT_CMD_IN_PROGRESS(ahci_portp)) {
1917 1922 AHCIDBG(AHCIDBG_INFO|AHCIDBG_PMULT, ahci_ctlp,
1918 1923 "ahci_claim_free_slot: there is still pending "
1919 1924 "read/write port-mult command(s) in command list, "
1920 1925 "so no available slot for the non-queued command",
1921 1926 NULL);
1922 1927 return (AHCI_FAILURE);
1923 1928 }
1924 1929 if ((ahci_ctlp->ahcictl_cap & AHCI_CAP_NO_MCMDLIST_NONQUEUE) &&
1925 1930 NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) {
1926 1931 AHCIDBG(AHCIDBG_INFO, ahci_ctlp,
1927 1932 "ahci_claim_free_slot: HBA cannot support multiple-"
1928 1933 "use of the command list for non-queued commands",
1929 1934 NULL);
1930 1935 return (AHCI_FAILURE);
1931 1936 }
1932 1937 free_slots = (~ahci_portp->ahciport_pending_tags) &
1933 1938 AHCI_SLOT_MASK(ahci_ctlp);
1934 1939 } else if (command_type == AHCI_NCQ_CMD) {
1935 1940 /* NCQ command request */
1936 1941 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) {
1937 1942 AHCIDBG(AHCIDBG_INFO|AHCIDBG_NCQ, ahci_ctlp,
1938 1943 "ahci_claim_free_slot: there is still pending "
1939 1944 "non-queued command(s) in the command list, "
1940 1945 "so no available slot for the queued command",
1941 1946 NULL);
1942 1947 return (AHCI_FAILURE);
1943 1948 }
1944 1949
1945 1950 /*
1946 1951 * NCQ commands cannot be sent to different port multiplier
1947 1952 * ports in Command-Based Switching mode
1948 1953 */
1949 1954 /*
1950 1955 * NOTE: In Command-Based Switching mode, AHCI controller
1951 1956 * usually reports a 'Handshake Error' when multiple NCQ
1952 1957 * commands are outstanding simultaneously.
1953 1958 */
1954 1959 if (AHCIPORT_DEV_TYPE(ahci_portp, addrp) == SATA_DTYPE_PMULT) {
1955 1960 ASSERT(ahci_portp->ahciport_pmult_info != NULL);
1956 1961 if (!(ahci_ctlp->ahcictl_cap & AHCI_CAP_PMULT_FBSS) &&
1957 1962 NCQ_CMD_IN_PROGRESS(ahci_portp) &&
1958 1963 AHCIPORT_NCQ_PMPORT(ahci_portp) !=
1959 1964 addrp->aa_pmport) {
1960 1965 AHCIDBG(AHCIDBG_INFO, ahci_ctlp,
1961 1966 "ahci_claim_free_slot: there is still "
1962 1967 "pending queued command(s) in the "
1963 1968 "command list for another Port Multiplier "
1964 1969 "port, so no available slot.", NULL);
1965 1970 return (AHCI_FAILURE);
1966 1971 }
1967 1972 }
1968 1973
1969 1974 free_slots = (~ahci_portp->ahciport_pending_ncq_tags) &
1970 1975 AHCI_NCQ_SLOT_MASK(ahci_portp);
1971 1976 } else if (command_type == AHCI_ERR_RETRI_CMD) {
1972 1977 /* Error retrieval command request */
1973 1978 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
1974 1979 "ahci_claim_free_slot: slot 0 is allocated for REQUEST "
1975 1980 "SENSE or READ LOG EXT command", NULL);
1976 1981 slot = 0;
1977 1982 goto out;
1978 1983 } else if (command_type == AHCI_RDWR_PMULT_CMD) {
1979 1984 /*
1980 1985 * An extra check on PxCI. Sometimes PxCI bits may not be
1981 1986 * cleared during hot-plug or error recovery process.
1982 1987 */
1983 1988 port_cmd_issue = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
1984 1989 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, addrp->aa_port));
1985 1990
1986 1991 if (port_cmd_issue != 0) {
1987 1992 AHCIDBG(AHCIDBG_INFO|AHCIDBG_PMULT, ahci_ctlp,
1988 1993 "ahci_claim_free_slot: there is still pending "
1989 1994 "command(s) in command list (0x%x/0x%x, PxCI %x),"
1990 1995 "so no available slot for R/W PMULT command.",
1991 1996 NON_NCQ_CMD_IN_PROGRESS(ahci_portp),
1992 1997 NCQ_CMD_IN_PROGRESS(ahci_portp),
1993 1998 port_cmd_issue);
1994 1999 return (AHCI_FAILURE);
1995 2000 }
1996 2001
1997 2002 AHCIDBG(AHCIDBG_INFO, ahci_ctlp,
1998 2003 "ahci_claim_free_slot: slot 0 is allocated for "
1999 2004 "READ/WRITE PORTMULT command", NULL);
2000 2005 slot = 0;
2001 2006 goto out;
2002 2007 }
2003 2008
2004 2009 slot = ddi_ffs(free_slots) - 1;
2005 2010 if (slot == -1) {
2006 2011 AHCIDBG(AHCIDBG_VERBOSE, ahci_ctlp,
2007 2012 "ahci_claim_free_slot: no empty slots", NULL);
2008 2013 return (AHCI_FAILURE);
2009 2014 }
2010 2015
2011 2016 /*
2012 2017 * According to the AHCI spec, to allow a simple mechanism for the
2013 2018 * HBA to map command list slots to queue entries, software must
2014 2019 * match the tag number it uses to the slot it is placing the command
2015 2020 * in. For example, if a queued command is placed in slot 5, the tag
2016 2021 * for that command must be 5.
2017 2022 */
2018 2023 if (command_type == AHCI_NCQ_CMD) {
2019 2024 ahci_portp->ahciport_pending_ncq_tags |= (0x1 << slot);
2020 2025 if (AHCI_ADDR_IS_PMPORT(addrp)) {
2021 2026 ASSERT(ahci_portp->ahciport_pmult_info != NULL);
2022 2027 AHCIPORT_NCQ_PMPORT(ahci_portp) = addrp->aa_pmport;
2023 2028 }
2024 2029 }
2025 2030
2026 2031 ahci_portp->ahciport_pending_tags |= (0x1 << slot);
2027 2032
2028 2033 out:
2029 2034 AHCIDBG(AHCIDBG_VERBOSE, ahci_ctlp,
2030 2035 "ahci_claim_free_slot: found slot: 0x%x", slot);
2031 2036
2032 2037 return (slot);
2033 2038 }
2034 2039
2035 2040 /*
2036 2041 * Builds the Command Table for the sata packet and delivers it to controller.
2037 2042 *
2038 2043 * Returns:
2039 2044 * slot number if we can obtain a slot successfully
2040 2045 * otherwise, return AHCI_FAILURE
2041 2046 */
2042 2047 static int
2043 2048 ahci_deliver_satapkt(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp,
2044 2049 ahci_addr_t *addrp, sata_pkt_t *spkt)
2045 2050 {
2046 2051 int cmd_slot;
2047 2052 sata_cmd_t *scmd;
2048 2053 ahci_fis_h2d_register_t *h2d_register_fisp;
2049 2054 ahci_cmd_table_t *cmd_table;
2050 2055 ahci_cmd_header_t *cmd_header;
2051 2056 int ncookies;
2052 2057 int i;
2053 2058 int command_type = AHCI_NON_NCQ_CMD;
2054 2059 int ncq_qdepth;
2055 2060 int instance = ddi_get_instance(ahci_ctlp->ahcictl_dip);
2056 2061 uint8_t port, pmport;
2057 2062 #if AHCI_DEBUG
2058 2063 uint32_t *ptr;
2059 2064 uint8_t *ptr2;
2060 2065 #endif
2061 2066
2062 2067 ASSERT(MUTEX_HELD(&ahci_portp->ahciport_mutex));
2063 2068
2064 2069 port = addrp->aa_port;
2065 2070 pmport = addrp->aa_pmport;
2066 2071
2067 2072 spkt->satapkt_reason = SATA_PKT_BUSY;
2068 2073
2069 2074 scmd = &spkt->satapkt_cmd;
2070 2075
2071 2076 /* Check if the command is a NCQ command */
2072 2077 if (scmd->satacmd_cmd_reg == SATAC_READ_FPDMA_QUEUED ||
2073 2078 scmd->satacmd_cmd_reg == SATAC_WRITE_FPDMA_QUEUED) {
2074 2079 command_type = AHCI_NCQ_CMD;
2075 2080
2076 2081 /*
2077 2082 * When NCQ is support, system software must determine the
2078 2083 * maximum tag allowed by the device and the HBA, and it
2079 2084 * must use a value not beyond of the lower bound of the two.
2080 2085 *
2081 2086 * Sata module is going to calculate the qdepth and send
2082 2087 * down to HBA driver via sata_cmd.
2083 2088 */
2084 2089 ncq_qdepth = scmd->satacmd_flags.sata_max_queue_depth + 1;
2085 2090
2086 2091 /*
2087 2092 * At the moment, the driver doesn't support the dynamic
2088 2093 * setting of the maximum ncq depth, and the value can be
2089 2094 * set either during the attach or after hot-plug insertion.
2090 2095 */
2091 2096 if (ahci_portp->ahciport_max_ncq_tags == 0) {
2092 2097 ahci_portp->ahciport_max_ncq_tags = ncq_qdepth;
2093 2098 AHCIDBG(AHCIDBG_NCQ, ahci_ctlp,
2094 2099 "ahci_deliver_satapkt: port %d the max tags for "
2095 2100 "NCQ command is %d", port, ncq_qdepth);
2096 2101 } else {
2097 2102 if (ncq_qdepth != ahci_portp->ahciport_max_ncq_tags) {
2098 2103 cmn_err(CE_WARN, "!ahci%d: ahci_deliver_satapkt"
2099 2104 " port %d the max tag for NCQ command is "
2100 2105 "requested to change from %d to %d, at the"
2101 2106 " moment the driver doesn't support the "
2102 2107 "dynamic change so it's going to "
2103 2108 "still use the previous tag value",
2104 2109 instance, port,
2105 2110 ahci_portp->ahciport_max_ncq_tags,
2106 2111 ncq_qdepth);
2107 2112 }
2108 2113 }
2109 2114 }
2110 2115
2111 2116 /* Check if the command is an error retrieval command */
2112 2117 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp))
2113 2118 command_type = AHCI_ERR_RETRI_CMD;
2114 2119
2115 2120 /* Check if the command is an read/write pmult command */
2116 2121 if (RDWR_PMULT_CMD_IN_PROGRESS(ahci_portp))
2117 2122 command_type = AHCI_RDWR_PMULT_CMD;
2118 2123
2119 2124 /* Check if there is an empty command slot */
2120 2125 cmd_slot = ahci_claim_free_slot(ahci_ctlp, ahci_portp,
2121 2126 addrp, command_type);
2122 2127 if (cmd_slot == AHCI_FAILURE) {
2123 2128 AHCIDBG(AHCIDBG_INFO, ahci_ctlp, "no free command slot", NULL);
2124 2129 return (AHCI_FAILURE);
2125 2130 }
2126 2131
2127 2132 AHCIDBG(AHCIDBG_ENTRY|AHCIDBG_INFO, ahci_ctlp,
2128 2133 "ahci_deliver_satapkt enter: cmd_reg: 0x%x, cmd_slot: 0x%x, "
2129 2134 "port: %d, satapkt: 0x%p", scmd->satacmd_cmd_reg,
2130 2135 cmd_slot, port, (void *)spkt);
2131 2136
2132 2137 cmd_table = ahci_portp->ahciport_cmd_tables[cmd_slot];
2133 2138 bzero((void *)cmd_table, ahci_cmd_table_size);
2134 2139
2135 2140 /* For data transfer operations, it is the H2D Register FIS */
2136 2141 h2d_register_fisp =
2137 2142 &(cmd_table->ahcict_command_fis.ahcifc_fis.ahcifc_h2d_register);
2138 2143
2139 2144 SET_FIS_TYPE(h2d_register_fisp, AHCI_H2D_REGISTER_FIS_TYPE);
2140 2145
2141 2146 /*
2142 2147 * PMP field only make sense when target is a port multiplier or a
2143 2148 * device behind a port multiplier. Otherwise should set it to 0.
2144 2149 */
2145 2150 if (AHCI_ADDR_IS_PMULT(addrp) || AHCI_ADDR_IS_PMPORT(addrp))
2146 2151 SET_FIS_PMP(h2d_register_fisp, pmport);
2147 2152
2148 2153 SET_FIS_CDMDEVCTL(h2d_register_fisp, 1);
2149 2154 SET_FIS_COMMAND(h2d_register_fisp, scmd->satacmd_cmd_reg);
2150 2155 SET_FIS_FEATURES(h2d_register_fisp, scmd->satacmd_features_reg);
2151 2156 SET_FIS_SECTOR_COUNT(h2d_register_fisp, scmd->satacmd_sec_count_lsb);
2152 2157
2153 2158 switch (scmd->satacmd_addr_type) {
2154 2159
2155 2160 case 0:
2156 2161 /*
2157 2162 * satacmd_addr_type will be 0 for the commands below:
2158 2163 * ATAPI command
2159 2164 * SATAC_IDLE_IM
2160 2165 * SATAC_STANDBY_IM
2161 2166 * SATAC_DOWNLOAD_MICROCODE
2162 2167 * SATAC_FLUSH_CACHE
2163 2168 * SATAC_SET_FEATURES
2164 2169 * SATAC_SMART
2165 2170 * SATAC_ID_PACKET_DEVICE
2166 2171 * SATAC_ID_DEVICE
2167 2172 * SATAC_READ_PORTMULT
2168 2173 * SATAC_WRITE_PORTMULT
2169 2174 */
2170 2175 /* FALLTHRU */
2171 2176
2172 2177 case ATA_ADDR_LBA:
2173 2178 /* FALLTHRU */
2174 2179
2175 2180 case ATA_ADDR_LBA28:
2176 2181 /* LBA[7:0] */
2177 2182 SET_FIS_SECTOR(h2d_register_fisp, scmd->satacmd_lba_low_lsb);
2178 2183
2179 2184 /* LBA[15:8] */
2180 2185 SET_FIS_CYL_LOW(h2d_register_fisp, scmd->satacmd_lba_mid_lsb);
2181 2186
2182 2187 /* LBA[23:16] */
2183 2188 SET_FIS_CYL_HI(h2d_register_fisp, scmd->satacmd_lba_high_lsb);
2184 2189
2185 2190 /* LBA [27:24] (also called dev_head) */
2186 2191 SET_FIS_DEV_HEAD(h2d_register_fisp, scmd->satacmd_device_reg);
2187 2192
2188 2193 break;
2189 2194
2190 2195 case ATA_ADDR_LBA48:
2191 2196 /* LBA[7:0] */
2192 2197 SET_FIS_SECTOR(h2d_register_fisp, scmd->satacmd_lba_low_lsb);
2193 2198
2194 2199 /* LBA[15:8] */
2195 2200 SET_FIS_CYL_LOW(h2d_register_fisp, scmd->satacmd_lba_mid_lsb);
2196 2201
2197 2202 /* LBA[23:16] */
2198 2203 SET_FIS_CYL_HI(h2d_register_fisp, scmd->satacmd_lba_high_lsb);
2199 2204
2200 2205 /* LBA [31:24] */
2201 2206 SET_FIS_SECTOR_EXP(h2d_register_fisp,
2202 2207 scmd->satacmd_lba_low_msb);
2203 2208
2204 2209 /* LBA [39:32] */
2205 2210 SET_FIS_CYL_LOW_EXP(h2d_register_fisp,
2206 2211 scmd->satacmd_lba_mid_msb);
2207 2212
2208 2213 /* LBA [47:40] */
2209 2214 SET_FIS_CYL_HI_EXP(h2d_register_fisp,
2210 2215 scmd->satacmd_lba_high_msb);
2211 2216
2212 2217 /* Set dev_head */
2213 2218 SET_FIS_DEV_HEAD(h2d_register_fisp,
2214 2219 scmd->satacmd_device_reg);
2215 2220
2216 2221 /* Set the extended sector count and features */
2217 2222 SET_FIS_SECTOR_COUNT_EXP(h2d_register_fisp,
2218 2223 scmd->satacmd_sec_count_msb);
2219 2224 SET_FIS_FEATURES_EXP(h2d_register_fisp,
2220 2225 scmd->satacmd_features_reg_ext);
2221 2226 break;
2222 2227 }
2223 2228
2224 2229 /*
2225 2230 * For NCQ command (READ/WRITE FPDMA QUEUED), sector count 7:0 is
2226 2231 * filled into features field, and sector count 8:15 is filled into
2227 2232 * features (exp) field. The hba driver doesn't need to anything
2228 2233 * special with regard to this, since sata framework has already
2229 2234 * done so.
2230 2235 *
2231 2236 * However the driver needs to make sure TAG is filled into sector
2232 2237 * field.
2233 2238 */
2234 2239 if (command_type == AHCI_NCQ_CMD) {
2235 2240 SET_FIS_SECTOR_COUNT(h2d_register_fisp,
2236 2241 (cmd_slot << SATA_TAG_QUEUING_SHIFT));
2237 2242 }
2238 2243
2239 2244 ncookies = scmd->satacmd_num_dma_cookies;
2240 2245 AHCIDBG(AHCIDBG_PRDT, ahci_ctlp,
2241 2246 "ncookies = 0x%x, ahci_dma_prdt_number = 0x%x",
2242 2247 ncookies, ahci_dma_prdt_number);
2243 2248
2244 2249 ASSERT(ncookies <= ahci_dma_prdt_number);
2245 2250 ahci_portp->ahciport_prd_bytecounts[cmd_slot] = 0;
2246 2251
2247 2252 /* *** now fill the scatter gather list ******* */
2248 2253 for (i = 0; i < ncookies; i++) {
2249 2254 cmd_table->ahcict_prdt[i].ahcipi_data_base_addr =
2250 2255 scmd->satacmd_dma_cookie_list[i]._dmu._dmac_la[0];
2251 2256 cmd_table->ahcict_prdt[i].ahcipi_data_base_addr_upper =
2252 2257 scmd->satacmd_dma_cookie_list[i]._dmu._dmac_la[1];
2253 2258 cmd_table->ahcict_prdt[i].ahcipi_descr_info =
2254 2259 scmd->satacmd_dma_cookie_list[i].dmac_size - 1;
2255 2260 ahci_portp->ahciport_prd_bytecounts[cmd_slot] +=
2256 2261 scmd->satacmd_dma_cookie_list[i].dmac_size;
2257 2262 }
2258 2263
2259 2264 AHCIDBG(AHCIDBG_PRDT, ahci_ctlp,
2260 2265 "ahciport_prd_bytecounts 0x%x for cmd_slot 0x%x",
2261 2266 ahci_portp->ahciport_prd_bytecounts[cmd_slot], cmd_slot);
2262 2267
2263 2268 /* The ACMD field is filled in for ATAPI command */
2264 2269 if (scmd->satacmd_cmd_reg == SATAC_PACKET) {
2265 2270 bcopy(scmd->satacmd_acdb, cmd_table->ahcict_atapi_cmd,
2266 2271 SATA_ATAPI_MAX_CDB_LEN);
2267 2272 }
2268 2273
2269 2274 /* Set Command Header in Command List */
2270 2275 cmd_header = &ahci_portp->ahciport_cmd_list[cmd_slot];
2271 2276 BZERO_DESCR_INFO(cmd_header);
2272 2277 BZERO_PRD_BYTE_COUNT(cmd_header);
2273 2278
2274 2279 /* Set the number of entries in the PRD table */
2275 2280 SET_PRD_TABLE_LENGTH(cmd_header, ncookies);
2276 2281
2277 2282 /* Set the length of the command in the CFIS area */
2278 2283 SET_COMMAND_FIS_LENGTH(cmd_header, AHCI_H2D_REGISTER_FIS_LENGTH);
2279 2284
2280 2285 /*
2281 2286 * PMP field only make sense when target is a port multiplier or a
2282 2287 * device behind a port multiplier. Otherwise should set it to 0.
2283 2288 */
2284 2289 if (AHCI_ADDR_IS_PMULT(addrp) || AHCI_ADDR_IS_PMPORT(addrp))
2285 2290 SET_PORT_MULTI_PORT(cmd_header, pmport);
2286 2291
2287 2292 AHCIDBG(AHCIDBG_INFO, ahci_ctlp, "command data direction is "
2288 2293 "sata_data_direction = 0x%x",
2289 2294 scmd->satacmd_flags.sata_data_direction);
2290 2295
2291 2296 /* Set A bit if it is an ATAPI command */
2292 2297 if (scmd->satacmd_cmd_reg == SATAC_PACKET)
2293 2298 SET_ATAPI(cmd_header, AHCI_CMDHEAD_ATAPI);
2294 2299
2295 2300 /* Set W bit if data is going to the device */
2296 2301 if (scmd->satacmd_flags.sata_data_direction == SATA_DIR_WRITE)
2297 2302 SET_WRITE(cmd_header, AHCI_CMDHEAD_DATA_WRITE);
2298 2303
2299 2304 /*
2300 2305 * Set the prefetchable bit - this bit is only valid if the PRDTL
2301 2306 * field is non-zero or the ATAPI 'A' bit is set in the command
2302 2307 * header. This bit cannot be set when using native command
2303 2308 * queuing commands or when using FIS-based switching with a Port
2304 2309 * multiplier.
2305 2310 */
2306 2311 if (command_type != AHCI_NCQ_CMD)
2307 2312 SET_PREFETCHABLE(cmd_header, AHCI_CMDHEAD_PREFETCHABLE);
2308 2313
2309 2314 /*
2310 2315 * Now remember the sata packet in ahciport_slot_pkts[].
2311 2316 * Error retrieval command and r/w port multiplier command will
2312 2317 * be stored specifically for each port.
2313 2318 */
2314 2319 if (!ERR_RETRI_CMD_IN_PROGRESS(ahci_portp) &&
2315 2320 !RDWR_PMULT_CMD_IN_PROGRESS(ahci_portp))
2316 2321 ahci_portp->ahciport_slot_pkts[cmd_slot] = spkt;
2317 2322
2318 2323 /*
2319 2324 * Keep the timeout value
2320 2325 */
2321 2326 ahci_portp->ahciport_slot_timeout[cmd_slot] = spkt->satapkt_time;
2322 2327
2323 2328 /*
2324 2329 * If the intial timout is less than 1 tick, then make it longer by
2325 2330 * 1 tick to avoid immediate timeout
2326 2331 */
2327 2332 if (ahci_portp->ahciport_slot_timeout[cmd_slot] <=
2328 2333 ahci_watchdog_timeout)
2329 2334 ahci_portp->ahciport_slot_timeout[cmd_slot] +=
2330 2335 ahci_watchdog_timeout;
2331 2336
2332 2337 #if AHCI_DEBUG
2333 2338 if (ahci_debug_flags & AHCIDBG_ATACMD &&
2334 2339 scmd->satacmd_cmd_reg != SATAC_PACKET ||
2335 2340 ahci_debug_flags & AHCIDBG_ATAPICMD &&
2336 2341 scmd->satacmd_cmd_reg == SATAC_PACKET) {
2337 2342
2338 2343 /* Dump the command header and table */
2339 2344 ahci_log(ahci_ctlp, CE_WARN, "\n");
2340 2345 ahci_log(ahci_ctlp, CE_WARN, "Command header&table for spkt "
2341 2346 "0x%p cmd_reg 0x%x port %d", spkt,
2342 2347 scmd->satacmd_cmd_reg, port);
2343 2348 ptr = (uint32_t *)cmd_header;
2344 2349 ahci_log(ahci_ctlp, CE_WARN,
2345 2350 " Command Header:%8x %8x %8x %8x",
2346 2351 ptr[0], ptr[1], ptr[2], ptr[3]);
2347 2352
2348 2353 /* Dump the H2D register FIS */
2349 2354 ptr = (uint32_t *)h2d_register_fisp;
2350 2355 ahci_log(ahci_ctlp, CE_WARN,
2351 2356 " Command FIS: %8x %8x %8x %8x",
2352 2357 ptr[0], ptr[1], ptr[2], ptr[3]);
2353 2358
2354 2359 /* Dump the ACMD register FIS */
2355 2360 ptr2 = (uint8_t *)&(cmd_table->ahcict_atapi_cmd);
2356 2361 for (i = 0; i < SATA_ATAPI_MAX_CDB_LEN/8; i++)
2357 2362 if (ahci_debug_flags & AHCIDBG_ATAPICMD)
2358 2363 ahci_log(ahci_ctlp, CE_WARN,
2359 2364 " ATAPI command: %2x %2x %2x %2x "
2360 2365 "%2x %2x %2x %2x",
2361 2366 ptr2[8 * i], ptr2[8 * i + 1],
2362 2367 ptr2[8 * i + 2], ptr2[8 * i + 3],
2363 2368 ptr2[8 * i + 4], ptr2[8 * i + 5],
2364 2369 ptr2[8 * i + 6], ptr2[8 * i + 7]);
2365 2370
2366 2371 /* Dump the PRDT */
2367 2372 for (i = 0; i < ncookies; i++) {
2368 2373 ptr = (uint32_t *)&(cmd_table->ahcict_prdt[i]);
2369 2374 ahci_log(ahci_ctlp, CE_WARN,
2370 2375 " Cookie %d: %8x %8x %8x %8x",
2371 2376 i, ptr[0], ptr[1], ptr[2], ptr[3]);
2372 2377 }
2373 2378 }
2374 2379 #endif
2375 2380
2376 2381 (void) ddi_dma_sync(
2377 2382 ahci_portp->ahciport_cmd_tables_dma_handle[cmd_slot],
2378 2383 0,
2379 2384 ahci_cmd_table_size,
2380 2385 DDI_DMA_SYNC_FORDEV);
2381 2386
2382 2387 (void) ddi_dma_sync(ahci_portp->ahciport_cmd_list_dma_handle,
2383 2388 cmd_slot * sizeof (ahci_cmd_header_t),
2384 2389 sizeof (ahci_cmd_header_t),
2385 2390 DDI_DMA_SYNC_FORDEV);
2386 2391
2387 2392 if ((ahci_check_dma_handle(ahci_portp->
2388 2393 ahciport_cmd_tables_dma_handle[cmd_slot]) != DDI_FM_OK) ||
2389 2394 ahci_check_dma_handle(ahci_portp->
2390 2395 ahciport_cmd_list_dma_handle) != DDI_FM_OK) {
2391 2396 ddi_fm_service_impact(ahci_ctlp->ahcictl_dip,
2392 2397 DDI_SERVICE_UNAFFECTED);
2393 2398 return (AHCI_FAILURE);
2394 2399 }
2395 2400
2396 2401 /* Set the corresponding bit in the PxSACT.DS for queued command */
2397 2402 if (command_type == AHCI_NCQ_CMD) {
2398 2403 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
2399 2404 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port),
2400 2405 (0x1 << cmd_slot));
2401 2406 }
2402 2407
2403 2408 /* Indicate to the HBA that a command is active. */
2404 2409 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
2405 2410 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port),
2406 2411 (0x1 << cmd_slot));
2407 2412
2408 2413 AHCIDBG(AHCIDBG_INFO, ahci_ctlp, "ahci_deliver_satapkt "
2409 2414 "exit: port %d", port);
2410 2415
2411 2416 /* Make sure the command is started by the PxSACT/PxCI */
2412 2417 if (ahci_check_acc_handle(ahci_ctlp->
2413 2418 ahcictl_ahci_acc_handle) != DDI_FM_OK) {
2414 2419 ddi_fm_service_impact(ahci_ctlp->ahcictl_dip,
2415 2420 DDI_SERVICE_UNAFFECTED);
2416 2421 return (AHCI_FAILURE);
2417 2422 }
2418 2423
2419 2424 return (cmd_slot);
2420 2425 }
2421 2426
2422 2427 /*
2423 2428 * Called by the sata framework to abort the previously sent packet(s).
2424 2429 *
2425 2430 * Reset device to abort commands.
2426 2431 */
2427 2432 static int
2428 2433 ahci_tran_abort(dev_info_t *dip, sata_pkt_t *spkt, int flag)
2429 2434 {
2430 2435 ahci_ctl_t *ahci_ctlp;
2431 2436 ahci_port_t *ahci_portp;
2432 2437 uint32_t slot_status = 0;
2433 2438 uint32_t aborted_tags = 0;
2434 2439 uint32_t finished_tags = 0;
2435 2440 uint8_t cport = spkt->satapkt_device.satadev_addr.cport;
2436 2441 uint8_t port;
2437 2442 int tmp_slot;
2438 2443 int instance = ddi_get_instance(dip);
2439 2444
2440 2445 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance);
2441 2446 port = ahci_ctlp->ahcictl_cport_to_port[cport];
2442 2447
2443 2448 AHCIDBG(AHCIDBG_ENTRY, ahci_ctlp,
2444 2449 "ahci_tran_abort enter: port %d", port);
2445 2450
2446 2451 ahci_portp = ahci_ctlp->ahcictl_ports[port];
2447 2452 mutex_enter(&ahci_portp->ahciport_mutex);
2448 2453
2449 2454 /*
2450 2455 * If AHCI_PORT_FLAG_MOPPING flag is set, it means all the pending
2451 2456 * commands are being mopped, therefore there is nothing else to do
2452 2457 */
2453 2458 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) {
2454 2459 AHCIDBG(AHCIDBG_INFO, ahci_ctlp,
2455 2460 "ahci_tran_abort: port %d is in "
2456 2461 "mopping process, so just return directly ", port);
2457 2462 mutex_exit(&ahci_portp->ahciport_mutex);
2458 2463 return (SATA_SUCCESS);
2459 2464 }
2460 2465
2461 2466 /*
2462 2467 * If AHCI_PORT_FLAG_RDWR_PMULT flag is set, it means a R/W PMULT
2463 2468 * command is being executed so no other commands is outstanding,
2464 2469 * nothing to do.
2465 2470 */
2466 2471 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_RDWR_PMULT) {
2467 2472 AHCIDBG(AHCIDBG_INFO, ahci_ctlp,
2468 2473 "ahci_tran_abort: port %d is reading/writing "
2469 2474 "port multiplier, so just return directly ", port);
2470 2475 mutex_exit(&ahci_portp->ahciport_mutex);
2471 2476 return (SATA_SUCCESS);
2472 2477 }
2473 2478
2474 2479 if (ahci_portp->ahciport_port_state & SATA_PSTATE_FAILED |
2475 2480 ahci_portp->ahciport_port_state & SATA_PSTATE_SHUTDOWN |
2476 2481 ahci_portp->ahciport_port_state & SATA_PSTATE_PWROFF) {
2477 2482 /*
2478 2483 * In case the targer driver would send the request before
2479 2484 * sata framework can have the opportunity to process those
2480 2485 * event reports.
2481 2486 */
2482 2487 spkt->satapkt_reason = SATA_PKT_PORT_ERROR;
2483 2488 spkt->satapkt_device.satadev_state =
2484 2489 ahci_portp->ahciport_port_state;
2485 2490 ahci_update_sata_registers(ahci_ctlp, port,
2486 2491 &spkt->satapkt_device);
2487 2492 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
2488 2493 "ahci_tran_abort returning SATA_FAILURE while "
2489 2494 "port in FAILED/SHUTDOWN/PWROFF state: "
2490 2495 "port: %d", port);
2491 2496 mutex_exit(&ahci_portp->ahciport_mutex);
2492 2497 return (SATA_FAILURE);
2493 2498 }
2494 2499
2495 2500 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) {
2496 2501 /*
2497 2502 * ahci_intr_phyrdy_change() may have rendered it to
2498 2503 * AHCI_PORT_TYPE_NODEV.
2499 2504 */
2500 2505 spkt->satapkt_reason = SATA_PKT_PORT_ERROR;
2501 2506 spkt->satapkt_device.satadev_type = SATA_DTYPE_NONE;
2502 2507 spkt->satapkt_device.satadev_state =
2503 2508 ahci_portp->ahciport_port_state;
2504 2509 ahci_update_sata_registers(ahci_ctlp, port,
2505 2510 &spkt->satapkt_device);
2506 2511 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
2507 2512 "ahci_tran_abort returning SATA_FAILURE while "
2508 2513 "no device attached: port: %d", port);
2509 2514 mutex_exit(&ahci_portp->ahciport_mutex);
2510 2515 return (SATA_FAILURE);
2511 2516 }
2512 2517
2513 2518 if (flag == SATA_ABORT_ALL_PACKETS) {
2514 2519 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp))
2515 2520 aborted_tags = ahci_portp->ahciport_pending_tags;
2516 2521 else if (NCQ_CMD_IN_PROGRESS(ahci_portp))
2517 2522 aborted_tags = ahci_portp->ahciport_pending_ncq_tags;
2518 2523
2519 2524 cmn_err(CE_NOTE, "!ahci%d: ahci port %d abort all packets",
2520 2525 instance, port);
2521 2526 } else {
2522 2527 aborted_tags = 0xffffffff;
2523 2528 /*
2524 2529 * Aborting one specific packet, first search the
2525 2530 * ahciport_slot_pkts[] list for matching spkt.
2526 2531 */
2527 2532 for (tmp_slot = 0;
2528 2533 tmp_slot < ahci_ctlp->ahcictl_num_cmd_slots; tmp_slot++) {
2529 2534 if (ahci_portp->ahciport_slot_pkts[tmp_slot] == spkt) {
2530 2535 aborted_tags = (0x1 << tmp_slot);
2531 2536 break;
2532 2537 }
2533 2538 }
2534 2539
2535 2540 if (aborted_tags == 0xffffffff) {
2536 2541 /* request packet is not on the pending list */
2537 2542 AHCIDBG(AHCIDBG_INFO, ahci_ctlp,
2538 2543 "Cannot find the aborting pkt 0x%p on the "
2539 2544 "pending list", (void *)spkt);
2540 2545 ahci_update_sata_registers(ahci_ctlp, port,
2541 2546 &spkt->satapkt_device);
2542 2547 mutex_exit(&ahci_portp->ahciport_mutex);
2543 2548 return (SATA_FAILURE);
2544 2549 }
2545 2550 cmn_err(CE_NOTE, "!ahci%d: ahci port %d abort satapkt 0x%p",
2546 2551 instance, port, (void *)spkt);
2547 2552 }
2548 2553
2549 2554 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp))
2550 2555 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
2551 2556 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port));
2552 2557 else if (NCQ_CMD_IN_PROGRESS(ahci_portp))
2553 2558 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
2554 2559 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port));
2555 2560
2556 2561 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING;
2557 2562 ahci_portp->ahciport_mop_in_progress++;
2558 2563
2559 2564 /*
2560 2565 * To abort the packet(s), first we are trying to clear PxCMD.ST
2561 2566 * to stop the port, and if the port can be stopped
2562 2567 * successfully with PxTFD.STS.BSY and PxTFD.STS.DRQ cleared to '0',
2563 2568 * then we just send back the aborted packet(s) with ABORTED flag
2564 2569 * and then restart the port by setting PxCMD.ST and PxCMD.FRE.
2565 2570 * If PxTFD.STS.BSY or PxTFD.STS.DRQ is set to '1', then we
2566 2571 * perform a COMRESET.
2567 2572 */
2568 2573 (void) ahci_restart_port_wait_till_ready(ahci_ctlp,
2569 2574 ahci_portp, port, NULL, NULL);
2570 2575
2571 2576 /*
2572 2577 * Compute which have finished and which need to be retried.
2573 2578 *
2574 2579 * The finished tags are ahciport_pending_tags/ahciport_pending_ncq_tags
2575 2580 * minus the slot_status. The aborted_tags has to be deducted by
2576 2581 * finished_tags since we can't possibly abort a tag which had finished
2577 2582 * already.
2578 2583 */
2579 2584 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp))
2580 2585 finished_tags = ahci_portp->ahciport_pending_tags &
2581 2586 ~slot_status & AHCI_SLOT_MASK(ahci_ctlp);
2582 2587 else if (NCQ_CMD_IN_PROGRESS(ahci_portp))
2583 2588 finished_tags = ahci_portp->ahciport_pending_ncq_tags &
2584 2589 ~slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp);
2585 2590
2586 2591 aborted_tags &= ~finished_tags;
2587 2592
2588 2593 ahci_mop_commands(ahci_ctlp,
2589 2594 ahci_portp,
2590 2595 slot_status,
2591 2596 0, /* failed tags */
2592 2597 0, /* timeout tags */
2593 2598 aborted_tags,
2594 2599 0); /* reset tags */
2595 2600
2596 2601 ahci_update_sata_registers(ahci_ctlp, port, &spkt->satapkt_device);
2597 2602 mutex_exit(&ahci_portp->ahciport_mutex);
2598 2603
2599 2604 return (SATA_SUCCESS);
2600 2605 }
2601 2606
2602 2607 /*
2603 2608 * Used to do device reset and reject all the pending packets on a device
2604 2609 * during the reset operation.
2605 2610 *
2606 2611 * NOTE: ONLY called by ahci_tran_reset_dport
2607 2612 */
2608 2613 static int
2609 2614 ahci_reset_device_reject_pkts(ahci_ctl_t *ahci_ctlp,
2610 2615 ahci_port_t *ahci_portp, ahci_addr_t *addrp)
2611 2616 {
2612 2617 uint32_t slot_status = 0;
2613 2618 uint32_t reset_tags = 0;
2614 2619 uint32_t finished_tags = 0;
2615 2620 uint8_t port = addrp->aa_port;
2616 2621 sata_device_t sdevice;
2617 2622 int ret;
2618 2623
2619 2624 ASSERT(MUTEX_HELD(&ahci_portp->ahciport_mutex));
2620 2625
2621 2626 AHCIDBG(AHCIDBG_ENTRY, ahci_ctlp,
2622 2627 "ahci_reset_device_reject_pkts on port: %d", port);
2623 2628
2624 2629 /*
2625 2630 * If AHCI_PORT_FLAG_MOPPING flag is set, it means all the pending
2626 2631 * commands are being mopped, therefore there is nothing else to do
2627 2632 */
2628 2633 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) {
2629 2634 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
2630 2635 "ahci_reset_device_reject_pkts: port %d is in "
2631 2636 "mopping process, so return directly ", port);
2632 2637 return (SATA_SUCCESS);
2633 2638 }
2634 2639
2635 2640 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) {
2636 2641 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
2637 2642 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port));
2638 2643 reset_tags = slot_status & AHCI_SLOT_MASK(ahci_ctlp);
2639 2644 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) {
2640 2645 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
2641 2646 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port));
2642 2647 reset_tags = slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp);
2643 2648 }
2644 2649
2645 2650 if (ahci_software_reset(ahci_ctlp, ahci_portp, addrp)
2646 2651 != AHCI_SUCCESS) {
2647 2652 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
2648 2653 "Try to do a port reset after software "
2649 2654 "reset failed", port);
2650 2655 ret = ahci_port_reset(ahci_ctlp, ahci_portp, addrp);
2651 2656 if (ret != AHCI_SUCCESS) {
2652 2657 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
2653 2658 "ahci_reset_device_reject_pkts: port %d "
2654 2659 "failed", port);
2655 2660 return (SATA_FAILURE);
2656 2661 }
2657 2662 }
2658 2663 /* Set the reset in progress flag */
2659 2664 ahci_portp->ahciport_reset_in_progress = 1;
2660 2665
2661 2666 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING;
2662 2667 ahci_portp->ahciport_mop_in_progress++;
2663 2668
2664 2669 /* Indicate to the framework that a reset has happened */
2665 2670 bzero((void *)&sdevice, sizeof (sata_device_t));
2666 2671 sdevice.satadev_addr.cport = ahci_ctlp->ahcictl_port_to_cport[port];
2667 2672 sdevice.satadev_addr.pmport = 0;
2668 2673 sdevice.satadev_addr.qual = SATA_ADDR_DCPORT;
2669 2674 sdevice.satadev_state = SATA_DSTATE_RESET |
2670 2675 SATA_DSTATE_PWR_ACTIVE;
2671 2676 mutex_exit(&ahci_portp->ahciport_mutex);
2672 2677 sata_hba_event_notify(
2673 2678 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip,
2674 2679 &sdevice,
2675 2680 SATA_EVNT_DEVICE_RESET);
2676 2681 mutex_enter(&ahci_portp->ahciport_mutex);
2677 2682
2678 2683 AHCIDBG(AHCIDBG_EVENT, ahci_ctlp,
2679 2684 "port %d sending event up: SATA_EVNT_DEVICE_RESET", port);
2680 2685
2681 2686 /* Next try to mop the pending commands */
2682 2687 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp))
2683 2688 finished_tags = ahci_portp->ahciport_pending_tags &
2684 2689 ~slot_status & AHCI_SLOT_MASK(ahci_ctlp);
2685 2690 else if (NCQ_CMD_IN_PROGRESS(ahci_portp))
2686 2691 finished_tags = ahci_portp->ahciport_pending_ncq_tags &
2687 2692 ~slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp);
2688 2693
2689 2694 reset_tags &= ~finished_tags;
2690 2695
2691 2696 ahci_mop_commands(ahci_ctlp,
2692 2697 ahci_portp,
2693 2698 slot_status,
2694 2699 0, /* failed tags */
2695 2700 0, /* timeout tags */
2696 2701 0, /* aborted tags */
2697 2702 reset_tags); /* reset tags */
2698 2703
2699 2704 return (SATA_SUCCESS);
2700 2705 }
2701 2706
2702 2707 /*
2703 2708 * Used to do device reset and reject all the pending packets on a device
2704 2709 * during the reset operation.
2705 2710 *
2706 2711 * NOTE: ONLY called by ahci_tran_reset_dport
2707 2712 */
2708 2713 static int
2709 2714 ahci_reset_pmdevice_reject_pkts(ahci_ctl_t *ahci_ctlp,
2710 2715 ahci_port_t *ahci_portp, ahci_addr_t *addrp)
2711 2716 {
2712 2717 uint32_t finished_tags = 0, reset_tags = 0, slot_status = 0;
2713 2718 uint8_t port = addrp->aa_port;
2714 2719 uint8_t pmport = addrp->aa_pmport;
2715 2720 sata_device_t sdevice;
2716 2721
2717 2722 ASSERT(MUTEX_HELD(&ahci_portp->ahciport_mutex));
2718 2723
2719 2724 AHCIDBG(AHCIDBG_ENTRY|AHCIDBG_PMULT, ahci_ctlp,
2720 2725 "ahci_reset_pmdevice_reject_pkts at port %d:%d", port, pmport);
2721 2726
2722 2727 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) {
2723 2728 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
2724 2729 "ahci_reset_pmdevice_reject_pkts: port %d is in "
2725 2730 "mopping process, so return directly ", port);
2726 2731 return (SATA_SUCCESS);
2727 2732 }
2728 2733
2729 2734 /* Checking for outstanding commands */
2730 2735 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) {
2731 2736 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
2732 2737 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port));
2733 2738 reset_tags = slot_status & AHCI_SLOT_MASK(ahci_ctlp);
2734 2739 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) {
2735 2740 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
2736 2741 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port));
2737 2742 reset_tags = slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp);
2738 2743 }
2739 2744
2740 2745 /* Issue SOFTWARE reset command. */
2741 2746 if (ahci_software_reset(ahci_ctlp, ahci_portp, addrp)
2742 2747 != AHCI_SUCCESS) {
2743 2748 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
2744 2749 "Try to do a port reset after software "
2745 2750 "reset failed", port);
2746 2751 return (SATA_FAILURE);
2747 2752 }
2748 2753
2749 2754 /* Set the reset in progress flag */
2750 2755 ahci_portp->ahciport_reset_in_progress = 1;
2751 2756
2752 2757 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING;
2753 2758 ahci_portp->ahciport_mop_in_progress++;
2754 2759
2755 2760 /* Indicate to the framework that a reset has happened */
2756 2761 bzero((void *)&sdevice, sizeof (sata_device_t));
2757 2762 sdevice.satadev_addr.cport = ahci_ctlp->ahcictl_port_to_cport[port];
2758 2763 sdevice.satadev_addr.pmport = pmport;
2759 2764 if (AHCI_ADDR_IS_PMULT(addrp))
2760 2765 sdevice.satadev_addr.qual = SATA_ADDR_PMULT;
2761 2766 else
2762 2767 sdevice.satadev_addr.qual = SATA_ADDR_DPMPORT;
2763 2768 sdevice.satadev_state = SATA_DSTATE_RESET |
2764 2769 SATA_DSTATE_PWR_ACTIVE;
2765 2770 mutex_exit(&ahci_portp->ahciport_mutex);
2766 2771 sata_hba_event_notify(
2767 2772 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip,
2768 2773 &sdevice,
2769 2774 SATA_EVNT_DEVICE_RESET);
2770 2775 mutex_enter(&ahci_portp->ahciport_mutex);
2771 2776
2772 2777 AHCIDBG(AHCIDBG_EVENT, ahci_ctlp,
2773 2778 "port %d:%d sending event up: SATA_EVNT_DEVICE_RESET",
2774 2779 port, pmport);
2775 2780
2776 2781 /* Next try to mop the pending commands */
2777 2782 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp))
2778 2783 finished_tags = ahci_portp->ahciport_pending_tags &
2779 2784 ~slot_status & AHCI_SLOT_MASK(ahci_ctlp);
2780 2785 else if (NCQ_CMD_IN_PROGRESS(ahci_portp))
2781 2786 finished_tags = ahci_portp->ahciport_pending_ncq_tags &
2782 2787 ~slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp);
2783 2788 reset_tags &= ~finished_tags;
2784 2789
2785 2790 AHCIDBG(AHCIDBG_EVENT|AHCIDBG_PMULT, ahci_ctlp,
2786 2791 "reset_tags = %x, finished_tags = %x, slot_status = %x",
2787 2792 reset_tags, finished_tags, slot_status);
2788 2793
2789 2794 /*
2790 2795 * NOTE: Because PxCI be only erased by unset PxCMD.ST bit, so even we
2791 2796 * try to reset a single device behind a port multiplier will
2792 2797 * terminate all the commands on that HBA port. We need mop these
2793 2798 * commands as well.
2794 2799 */
2795 2800 ahci_mop_commands(ahci_ctlp,
2796 2801 ahci_portp,
2797 2802 slot_status,
2798 2803 0, /* failed tags */
2799 2804 0, /* timeout tags */
2800 2805 0, /* aborted tags */
2801 2806 reset_tags); /* reset tags */
2802 2807
2803 2808 return (SATA_SUCCESS);
2804 2809 }
2805 2810
2806 2811 /*
2807 2812 * Used to do port reset and reject all the pending packets on a port during
2808 2813 * the reset operation.
2809 2814 */
2810 2815 static int
2811 2816 ahci_reset_port_reject_pkts(ahci_ctl_t *ahci_ctlp,
2812 2817 ahci_port_t *ahci_portp, ahci_addr_t *addrp)
2813 2818 {
2814 2819 uint32_t slot_status = 0;
2815 2820 uint32_t reset_tags = 0;
2816 2821 uint32_t finished_tags = 0;
2817 2822 uint8_t port = addrp->aa_port;
2818 2823
2819 2824 ASSERT(MUTEX_HELD(&ahci_portp->ahciport_mutex));
2820 2825
2821 2826 AHCIDBG(AHCIDBG_ENTRY, ahci_ctlp,
2822 2827 "ahci_reset_port_reject_pkts at port: %d", port);
2823 2828
2824 2829 /*
2825 2830 * If AHCI_PORT_FLAG_MOPPING flag is set, it means all the pending
2826 2831 * commands are being mopped, therefore there is nothing else to do
2827 2832 */
2828 2833 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) {
2829 2834 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
2830 2835 "ahci_reset_port_reject_pkts: port %d is in "
2831 2836 "mopping process, so return directly ", port);
2832 2837 return (SATA_SUCCESS);
2833 2838 }
2834 2839
2835 2840 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING;
2836 2841 ahci_portp->ahciport_mop_in_progress++;
2837 2842
2838 2843 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) {
2839 2844 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
2840 2845 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port));
2841 2846 reset_tags = slot_status & AHCI_SLOT_MASK(ahci_ctlp);
2842 2847 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) {
2843 2848 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
2844 2849 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port));
2845 2850 reset_tags = slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp);
2846 2851 }
2847 2852
2848 2853 if (ahci_restart_port_wait_till_ready(ahci_ctlp,
2849 2854 ahci_portp, port, AHCI_PORT_RESET|AHCI_RESET_NO_EVENTS_UP,
2850 2855 NULL) != AHCI_SUCCESS) {
2851 2856
2852 2857 /* Clear mop flag */
2853 2858 ahci_portp->ahciport_mop_in_progress--;
2854 2859 if (ahci_portp->ahciport_mop_in_progress == 0)
2855 2860 ahci_portp->ahciport_flags &=
2856 2861 ~AHCI_PORT_FLAG_MOPPING;
2857 2862 return (SATA_FAILURE);
2858 2863 }
2859 2864
2860 2865 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp))
2861 2866 finished_tags = ahci_portp->ahciport_pending_tags &
2862 2867 ~slot_status & AHCI_SLOT_MASK(ahci_ctlp);
2863 2868 else if (NCQ_CMD_IN_PROGRESS(ahci_portp))
2864 2869 finished_tags = ahci_portp->ahciport_pending_ncq_tags &
2865 2870 ~slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp);
2866 2871
2867 2872 reset_tags &= ~finished_tags;
2868 2873
2869 2874 ahci_mop_commands(ahci_ctlp,
2870 2875 ahci_portp,
2871 2876 slot_status,
2872 2877 0, /* failed tags */
2873 2878 0, /* timeout tags */
2874 2879 0, /* aborted tags */
2875 2880 reset_tags); /* reset tags */
2876 2881
2877 2882 return (SATA_SUCCESS);
2878 2883 }
2879 2884
2880 2885 /*
2881 2886 * Used to do hba reset and reject all the pending packets on all ports
2882 2887 * during the reset operation.
2883 2888 */
2884 2889 static int
2885 2890 ahci_reset_hba_reject_pkts(ahci_ctl_t *ahci_ctlp)
2886 2891 {
2887 2892 ahci_port_t *ahci_portp;
2888 2893 uint32_t slot_status[AHCI_MAX_PORTS];
2889 2894 uint32_t reset_tags[AHCI_MAX_PORTS];
2890 2895 uint32_t finished_tags[AHCI_MAX_PORTS];
2891 2896 int port;
2892 2897 int ret = SATA_SUCCESS;
2893 2898
2894 2899 AHCIDBG(AHCIDBG_ENTRY, ahci_ctlp,
2895 2900 "ahci_reset_hba_reject_pkts enter", NULL);
2896 2901
2897 2902 bzero(slot_status, sizeof (slot_status));
2898 2903 bzero(reset_tags, sizeof (reset_tags));
2899 2904 bzero(finished_tags, sizeof (finished_tags));
2900 2905
2901 2906 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) {
2902 2907 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) {
2903 2908 continue;
2904 2909 }
2905 2910
2906 2911 ahci_portp = ahci_ctlp->ahcictl_ports[port];
2907 2912
2908 2913 mutex_enter(&ahci_portp->ahciport_mutex);
2909 2914 ahci_portp->ahciport_reset_in_progress = 1;
2910 2915 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) {
2911 2916 slot_status[port] = ddi_get32(
2912 2917 ahci_ctlp->ahcictl_ahci_acc_handle,
2913 2918 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port));
2914 2919 reset_tags[port] = slot_status[port] &
2915 2920 AHCI_SLOT_MASK(ahci_ctlp);
2916 2921 AHCIDBG(AHCIDBG_INIT, ahci_ctlp,
2917 2922 "port %d: reset_tags = 0x%x pending_tags = 0x%x",
2918 2923 port, reset_tags[port],
2919 2924 ahci_portp->ahciport_pending_tags);
2920 2925 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) {
2921 2926 slot_status[port] = ddi_get32(
2922 2927 ahci_ctlp->ahcictl_ahci_acc_handle,
2923 2928 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port));
2924 2929 reset_tags[port] = slot_status[port] &
2925 2930 AHCI_NCQ_SLOT_MASK(ahci_portp);
2926 2931 AHCIDBG(AHCIDBG_INIT, ahci_ctlp,
2927 2932 "port %d: reset_tags = 0x%x pending_tags = 0x%x",
2928 2933 port, reset_tags[port],
2929 2934 ahci_portp->ahciport_pending_tags);
2930 2935 }
2931 2936 mutex_exit(&ahci_portp->ahciport_mutex);
2932 2937 }
2933 2938
2934 2939 if (ahci_hba_reset(ahci_ctlp) != AHCI_SUCCESS) {
2935 2940 ret = SATA_FAILURE;
2936 2941 }
2937 2942
2938 2943 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) {
2939 2944 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) {
2940 2945 continue;
2941 2946 }
2942 2947
2943 2948 ahci_portp = ahci_ctlp->ahcictl_ports[port];
2944 2949
2945 2950 mutex_enter(&ahci_portp->ahciport_mutex);
2946 2951 /*
2947 2952 * To prevent recursive enter to ahci_mop_commands, we need
2948 2953 * check AHCI_PORT_FLAG_MOPPING flag.
2949 2954 */
2950 2955 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) {
2951 2956 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
2952 2957 "ahci_reset_hba_reject_pkts: port %d is in "
2953 2958 "mopping process, so return directly ", port);
2954 2959 mutex_exit(&ahci_portp->ahciport_mutex);
2955 2960 continue;
2956 2961 }
2957 2962
2958 2963 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING;
2959 2964 ahci_portp->ahciport_mop_in_progress++;
2960 2965
2961 2966 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp))
2962 2967 finished_tags[port] =
2963 2968 ahci_portp->ahciport_pending_tags &
2964 2969 ~slot_status[port] & AHCI_SLOT_MASK(ahci_ctlp);
2965 2970 else if (NCQ_CMD_IN_PROGRESS(ahci_portp))
2966 2971 finished_tags[port] =
2967 2972 ahci_portp->ahciport_pending_ncq_tags &
2968 2973 ~slot_status[port] & AHCI_NCQ_SLOT_MASK(ahci_portp);
2969 2974
2970 2975 reset_tags[port] &= ~finished_tags[port];
2971 2976
2972 2977 ahci_mop_commands(ahci_ctlp,
2973 2978 ahci_portp,
2974 2979 slot_status[port],
2975 2980 0, /* failed tags */
2976 2981 0, /* timeout tags */
2977 2982 0, /* aborted tags */
2978 2983 reset_tags[port]); /* reset tags */
2979 2984 mutex_exit(&ahci_portp->ahciport_mutex);
2980 2985 }
2981 2986 out:
2982 2987 return (ret);
2983 2988 }
2984 2989
2985 2990 /*
2986 2991 * Called by sata framework to reset a port(s) or device.
2987 2992 */
2988 2993 static int
2989 2994 ahci_tran_reset_dport(dev_info_t *dip, sata_device_t *sd)
2990 2995 {
2991 2996 ahci_ctl_t *ahci_ctlp;
2992 2997 ahci_port_t *ahci_portp;
2993 2998 ahci_addr_t addr;
2994 2999 uint8_t cport = sd->satadev_addr.cport;
2995 3000 uint8_t pmport = sd->satadev_addr.pmport;
2996 3001 uint8_t port;
2997 3002 int ret = SATA_SUCCESS;
2998 3003 int instance = ddi_get_instance(dip);
2999 3004
3000 3005 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance);
3001 3006 port = ahci_ctlp->ahcictl_cport_to_port[cport];
3002 3007 ahci_portp = ahci_ctlp->ahcictl_ports[port];
3003 3008
3004 3009 ahci_get_ahci_addr(ahci_ctlp, sd, &addr);
3005 3010
3006 3011 AHCIDBG(AHCIDBG_ENTRY, ahci_ctlp,
3007 3012 "ahci_tran_reset_dport enter: cport %d", cport);
3008 3013
3009 3014 switch (sd->satadev_addr.qual) {
3010 3015 case SATA_ADDR_PMPORT:
3011 3016 /*
3012 3017 * If we want to issue a COMRESET on a pmport, we need to
3013 3018 * reject the outstanding commands on that pmport. According
3014 3019 * to AHCI spec, PxCI register could only be cleared by
3015 3020 * clearing PxCMD.ST, which will halt the controller port - as
3016 3021 * well as other pmports.
3017 3022 *
3018 3023 * Therefore we directly reset the controller port for
3019 3024 * simplicity. ahci_tran_probe_port() will handle reset stuff
3020 3025 * like initializing the given pmport.
3021 3026 */
3022 3027 /* FALLTHRU */
3023 3028 case SATA_ADDR_CPORT:
3024 3029 /* Port reset */
3025 3030 ahci_portp = ahci_ctlp->ahcictl_ports[port];
3026 3031 cmn_err(CE_NOTE, "!ahci%d: ahci_tran_reset_dport "
3027 3032 "port %d reset port", instance, port);
3028 3033
3029 3034 mutex_enter(&ahci_portp->ahciport_mutex);
3030 3035 ret = ahci_reset_port_reject_pkts(ahci_ctlp, ahci_portp, &addr);
3031 3036 mutex_exit(&ahci_portp->ahciport_mutex);
3032 3037
3033 3038 break;
3034 3039
3035 3040 case SATA_ADDR_DPMPORT:
3036 3041 cmn_err(CE_NOTE, "!ahci%d: ahci_tran_reset_dport "
3037 3042 "port %d:%d reset device", instance, port, pmport);
3038 3043 /* FALLTHRU */
3039 3044 case SATA_ADDR_DCPORT:
3040 3045 /* Device reset */
3041 3046 if (sd->satadev_addr.qual == SATA_ADDR_DCPORT)
3042 3047 cmn_err(CE_NOTE, "!ahci%d: ahci_tran_reset_dport "
3043 3048 "port %d reset device", instance, port);
3044 3049
3045 3050 mutex_enter(&ahci_portp->ahciport_mutex);
3046 3051 /*
3047 3052 * software reset request must be sent to SATA_PMULT_HOSTPORT
3048 3053 * if target is a port multiplier:
3049 3054 */
3050 3055 if (sd->satadev_addr.qual == SATA_ADDR_DCPORT &&
3051 3056 ahci_portp->ahciport_device_type == SATA_DTYPE_PMULT)
3052 3057 AHCI_ADDR_SET_PMULT(&addr, port);
3053 3058
3054 3059 if (ahci_portp->ahciport_port_state & SATA_PSTATE_FAILED |
3055 3060 ahci_portp->ahciport_port_state & SATA_PSTATE_SHUTDOWN |
3056 3061 ahci_portp->ahciport_port_state & SATA_PSTATE_PWROFF) {
3057 3062 /*
3058 3063 * In case the targer driver would send the request
3059 3064 * before sata framework can have the opportunity to
3060 3065 * process those event reports.
3061 3066 */
3062 3067 sd->satadev_state = ahci_portp->ahciport_port_state;
3063 3068 ahci_update_sata_registers(ahci_ctlp, port, sd);
3064 3069 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
3065 3070 "ahci_tran_reset_dport returning SATA_FAILURE "
3066 3071 "while port in FAILED/SHUTDOWN/PWROFF state: "
3067 3072 "port: %d", port);
3068 3073 mutex_exit(&ahci_portp->ahciport_mutex);
3069 3074 ret = SATA_FAILURE;
3070 3075 break;
3071 3076 }
3072 3077
3073 3078 if (AHCIPORT_GET_DEV_TYPE(ahci_portp, &addr) ==
3074 3079 SATA_DTYPE_NONE) {
3075 3080 /*
3076 3081 * ahci_intr_phyrdy_change() may have rendered it to
3077 3082 * AHCI_PORT_TYPE_NODEV.
3078 3083 */
3079 3084 sd->satadev_type = SATA_DTYPE_NONE;
3080 3085 sd->satadev_state = AHCIPORT_GET_STATE(ahci_portp,
3081 3086 &addr);
3082 3087 ahci_update_sata_registers(ahci_ctlp, port, sd);
3083 3088 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
3084 3089 "ahci_tran_reset_dport returning SATA_FAILURE "
3085 3090 "while no device attached: port: %d", port);
3086 3091 mutex_exit(&ahci_portp->ahciport_mutex);
3087 3092 ret = SATA_FAILURE;
3088 3093 break;
3089 3094 }
3090 3095
3091 3096 if (AHCI_ADDR_IS_PORT(&addr)) {
3092 3097 ret = ahci_reset_device_reject_pkts(ahci_ctlp,
3093 3098 ahci_portp, &addr);
3094 3099 } else {
3095 3100 ret = ahci_reset_pmdevice_reject_pkts(ahci_ctlp,
3096 3101 ahci_portp, &addr);
3097 3102 }
3098 3103
3099 3104 mutex_exit(&ahci_portp->ahciport_mutex);
3100 3105 break;
3101 3106
3102 3107 case SATA_ADDR_CNTRL:
3103 3108 /* Reset the whole controller */
3104 3109 cmn_err(CE_NOTE, "!ahci%d: ahci_tran_reset_dport "
3105 3110 "reset the whole hba", instance);
3106 3111 ret = ahci_reset_hba_reject_pkts(ahci_ctlp);
3107 3112 break;
3108 3113
3109 3114 default:
3110 3115 ret = SATA_FAILURE;
3111 3116 }
3112 3117
3113 3118 return (ret);
3114 3119 }
3115 3120
3116 3121 /*
3117 3122 * Called by sata framework to activate a port as part of hotplug.
3118 3123 * (cfgadm -c connect satax/y)
3119 3124 * Support port multiplier.
3120 3125 */
3121 3126 static int
3122 3127 ahci_tran_hotplug_port_activate(dev_info_t *dip, sata_device_t *satadev)
3123 3128 {
3124 3129 ahci_ctl_t *ahci_ctlp;
3125 3130 ahci_port_t *ahci_portp;
3126 3131 ahci_addr_t addr;
3127 3132 uint8_t cport = satadev->satadev_addr.cport;
3128 3133 uint8_t pmport = satadev->satadev_addr.pmport;
3129 3134 uint8_t port;
3130 3135 int instance = ddi_get_instance(dip);
3131 3136
3132 3137 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance);
3133 3138 port = ahci_ctlp->ahcictl_cport_to_port[cport];
3134 3139
3135 3140 AHCIDBG(AHCIDBG_ENTRY, ahci_ctlp,
3136 3141 "ahci_tran_hotplug_port_activate enter: cport %d", cport);
3137 3142
3138 3143 ahci_portp = ahci_ctlp->ahcictl_ports[port];
3139 3144
3140 3145 mutex_enter(&ahci_portp->ahciport_mutex);
3141 3146 ahci_get_ahci_addr(ahci_ctlp, satadev, &addr);
3142 3147 ASSERT(AHCI_ADDR_IS_PORT(&addr) || AHCI_ADDR_IS_PMPORT(&addr));
3143 3148
3144 3149 if (AHCI_ADDR_IS_PORT(&addr)) {
3145 3150 cmn_err(CE_NOTE, "!ahci%d: ahci port %d is activated",
3146 3151 instance, port);
3147 3152
3148 3153 /* Enable the interrupts on the port */
3149 3154 ahci_enable_port_intrs(ahci_ctlp, port);
3150 3155
3151 3156 /*
3152 3157 * Reset the port so that the PHY communication would be
3153 3158 * re-established. But this reset is an internal operation
3154 3159 * and the sata module doesn't need to know about it.
3155 3160 * Moreover, the port with a device attached will be started
3156 3161 * too.
3157 3162 */
3158 3163 (void) ahci_restart_port_wait_till_ready(ahci_ctlp,
3159 3164 ahci_portp, port,
3160 3165 AHCI_PORT_RESET|AHCI_RESET_NO_EVENTS_UP,
3161 3166 NULL);
3162 3167
3163 3168 /*
3164 3169 * Need to check the link status and device status of the port
3165 3170 * and consider raising power if the port was in D3 state
3166 3171 */
3167 3172 ahci_portp->ahciport_port_state |= SATA_PSTATE_PWRON;
3168 3173 ahci_portp->ahciport_port_state &= ~SATA_PSTATE_PWROFF;
3169 3174 ahci_portp->ahciport_port_state &= ~SATA_PSTATE_SHUTDOWN;
3170 3175 } else if (AHCI_ADDR_IS_PMPORT(&addr)) {
3171 3176 cmn_err(CE_NOTE, "!ahci%d: ahci port %d:%d is activated",
3172 3177 instance, port, pmport);
3173 3178 /* AHCI_ADDR_PMPORT */
3174 3179 AHCIPORT_PMSTATE(ahci_portp, &addr) |= SATA_PSTATE_PWRON;
3175 3180 AHCIPORT_PMSTATE(ahci_portp, &addr) &=
3176 3181 ~(SATA_PSTATE_PWROFF|SATA_PSTATE_SHUTDOWN);
3177 3182 }
3178 3183
3179 3184 satadev->satadev_state = ahci_portp->ahciport_port_state;
3180 3185
3181 3186 ahci_update_sata_registers(ahci_ctlp, port, satadev);
3182 3187
3183 3188 mutex_exit(&ahci_portp->ahciport_mutex);
3184 3189 return (SATA_SUCCESS);
3185 3190 }
3186 3191
3187 3192 /*
3188 3193 * Called by sata framework to deactivate a port as part of hotplug.
3189 3194 * (cfgadm -c disconnect satax/y)
3190 3195 * Support port multiplier.
3191 3196 */
3192 3197 static int
3193 3198 ahci_tran_hotplug_port_deactivate(dev_info_t *dip, sata_device_t *satadev)
3194 3199 {
3195 3200 ahci_ctl_t *ahci_ctlp;
3196 3201 ahci_port_t *ahci_portp;
3197 3202 ahci_addr_t addr;
3198 3203 uint8_t cport = satadev->satadev_addr.cport;
3199 3204 uint8_t pmport = satadev->satadev_addr.pmport;
3200 3205 uint8_t port;
3201 3206 uint32_t port_scontrol;
3202 3207 int instance = ddi_get_instance(dip);
3203 3208
3204 3209 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance);
3205 3210 port = ahci_ctlp->ahcictl_cport_to_port[cport];
3206 3211
3207 3212 AHCIDBG(AHCIDBG_ENTRY, ahci_ctlp,
3208 3213 "ahci_tran_hotplug_port_deactivate enter: cport %d", cport);
3209 3214
3210 3215 ahci_portp = ahci_ctlp->ahcictl_ports[port];
3211 3216 mutex_enter(&ahci_portp->ahciport_mutex);
3212 3217 ahci_get_ahci_addr(ahci_ctlp, satadev, &addr);
3213 3218 ASSERT(AHCI_ADDR_IS_PORT(&addr) || AHCI_ADDR_IS_PMPORT(&addr));
3214 3219
3215 3220 if (AHCI_ADDR_IS_PORT(&addr)) {
3216 3221 cmn_err(CE_NOTE, "!ahci%d: ahci port %d is deactivated",
3217 3222 instance, port);
3218 3223
3219 3224 /* Disable the interrupts on the port */
3220 3225 ahci_disable_port_intrs(ahci_ctlp, port);
3221 3226
3222 3227 if (ahci_portp->ahciport_device_type != SATA_DTYPE_NONE) {
3223 3228
3224 3229 /* First to abort all the pending commands */
3225 3230 ahci_reject_all_abort_pkts(ahci_ctlp, ahci_portp, port);
3226 3231
3227 3232 /* Then stop the port */
3228 3233 (void) ahci_put_port_into_notrunning_state(ahci_ctlp,
3229 3234 ahci_portp, port);
3230 3235 }
3231 3236
3232 3237 /* Next put the PHY offline */
3233 3238 port_scontrol = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
3234 3239 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port));
3235 3240 SCONTROL_SET_DET(port_scontrol, SCONTROL_DET_DISABLE);
3236 3241 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, (uint32_t *)
3237 3242 AHCI_PORT_PxSCTL(ahci_ctlp, port), port_scontrol);
3238 3243 } else if (AHCI_ADDR_IS_PMPORT(&addr)) {
3239 3244 cmn_err(CE_NOTE, "!ahci%d: ahci port %d:%d is deactivated",
3240 3245 instance, port, pmport);
3241 3246
3242 3247 ahci_disable_port_intrs(ahci_ctlp, port);
3243 3248 if (AHCIPORT_GET_DEV_TYPE(ahci_portp, &addr)
3244 3249 != SATA_DTYPE_NONE)
3245 3250 ahci_reject_all_abort_pkts(ahci_ctlp, ahci_portp, port);
3246 3251
3247 3252 /* Re-enable the interrupts for the other pmports */
3248 3253 ahci_enable_port_intrs(ahci_ctlp, port);
3249 3254 }
3250 3255
3251 3256 /* Update port state */
3252 3257 AHCIPORT_SET_STATE(ahci_portp, &addr, SATA_PSTATE_SHUTDOWN);
3253 3258 satadev->satadev_state = SATA_PSTATE_SHUTDOWN;
3254 3259
3255 3260 ahci_update_sata_registers(ahci_ctlp, port, satadev);
3256 3261
3257 3262 mutex_exit(&ahci_portp->ahciport_mutex);
3258 3263 return (SATA_SUCCESS);
3259 3264 }
3260 3265
3261 3266 /*
3262 3267 * To be used to mark all the outstanding pkts with SATA_PKT_ABORTED
3263 3268 * when a device is unplugged or a port is deactivated.
3264 3269 */
3265 3270 static void
3266 3271 ahci_reject_all_abort_pkts(ahci_ctl_t *ahci_ctlp,
3267 3272 ahci_port_t *ahci_portp, uint8_t port)
3268 3273 {
3269 3274 uint32_t slot_status = 0;
3270 3275 uint32_t abort_tags = 0;
3271 3276
3272 3277 ASSERT(MUTEX_HELD(&ahci_portp->ahciport_mutex));
3273 3278
3274 3279 AHCIDBG(AHCIDBG_ENTRY|AHCIDBG_INTR, ahci_ctlp,
3275 3280 "ahci_reject_all_abort_pkts at port: %d", port);
3276 3281
3277 3282 /* Read/write port multiplier command takes highest priority */
3278 3283 if (RDWR_PMULT_CMD_IN_PROGRESS(ahci_portp)) {
3279 3284 slot_status = 0x1;
3280 3285 abort_tags = 0x1;
3281 3286 goto out;
3282 3287 }
3283 3288
3284 3289 /*
3285 3290 * When AHCI_PORT_FLAG_MOPPING is set, we need to check whether a
3286 3291 * REQUEST SENSE command or READ LOG EXT command is delivered to HBA
3287 3292 * to get the error data, if yes when the device is removed, the
3288 3293 * command needs to be aborted too.
3289 3294 */
3290 3295 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) {
3291 3296 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) {
3292 3297 slot_status = 0x1;
3293 3298 abort_tags = 0x1;
3294 3299 goto out;
3295 3300 } else {
3296 3301 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
3297 3302 "ahci_reject_all_abort_pkts return directly "
3298 3303 "port %d no needs to reject any outstanding "
3299 3304 "commands", port);
3300 3305 return;
3301 3306 }
3302 3307 }
3303 3308
3304 3309 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) {
3305 3310 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
3306 3311 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port));
3307 3312 abort_tags = slot_status & AHCI_SLOT_MASK(ahci_ctlp);
3308 3313 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) {
3309 3314 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
3310 3315 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port));
3311 3316 abort_tags = slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp);
3312 3317 }
3313 3318
3314 3319 out:
3315 3320 /* No need to do mop when there is no outstanding commands */
3316 3321 if (slot_status != 0) {
3317 3322 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING;
3318 3323 ahci_portp->ahciport_mop_in_progress++;
3319 3324
3320 3325 ahci_mop_commands(ahci_ctlp,
3321 3326 ahci_portp,
3322 3327 slot_status,
3323 3328 0, /* failed tags */
3324 3329 0, /* timeout tags */
3325 3330 abort_tags, /* aborting tags */
3326 3331 0); /* reset tags */
3327 3332 }
3328 3333 }
3329 3334
3330 3335 #if defined(__lock_lint)
3331 3336 static int
3332 3337 ahci_selftest(dev_info_t *dip, sata_device_t *device)
3333 3338 {
3334 3339 return (SATA_SUCCESS);
3335 3340 }
3336 3341 #endif
3337 3342
3338 3343 /*
3339 3344 * Initialize fma capabilities and register with IO fault services.
3340 3345 */
3341 3346 static void
3342 3347 ahci_fm_init(ahci_ctl_t *ahci_ctlp)
3343 3348 {
3344 3349 /*
3345 3350 * Need to change iblock to priority for new MSI intr
3346 3351 */
3347 3352 ddi_iblock_cookie_t fm_ibc;
3348 3353
3349 3354 ahci_ctlp->ahcictl_fm_cap = ddi_getprop(DDI_DEV_T_ANY,
3350 3355 ahci_ctlp->ahcictl_dip,
3351 3356 DDI_PROP_CANSLEEP | DDI_PROP_DONTPASS, "fm-capable",
3352 3357 DDI_FM_EREPORT_CAPABLE | DDI_FM_ACCCHK_CAPABLE |
3353 3358 DDI_FM_DMACHK_CAPABLE | DDI_FM_ERRCB_CAPABLE);
3354 3359
3355 3360 /* Only register with IO Fault Services if we have some capability */
3356 3361 if (ahci_ctlp->ahcictl_fm_cap) {
3357 3362 /* Adjust access and dma attributes for FMA */
3358 3363 accattr.devacc_attr_access = DDI_FLAGERR_ACC;
3359 3364 buffer_dma_attr.dma_attr_flags |= DDI_DMA_FLAGERR;
3360 3365 rcvd_fis_dma_attr.dma_attr_flags |= DDI_DMA_FLAGERR;
3361 3366 cmd_list_dma_attr.dma_attr_flags |= DDI_DMA_FLAGERR;
3362 3367 cmd_table_dma_attr.dma_attr_flags |= DDI_DMA_FLAGERR;
3363 3368
3364 3369 /*
3365 3370 * Register capabilities with IO Fault Services.
3366 3371 * ahcictl_fm_cap will be updated to indicate
3367 3372 * capabilities actually supported (not requested.)
3368 3373 */
3369 3374 ddi_fm_init(ahci_ctlp->ahcictl_dip,
3370 3375 &ahci_ctlp->ahcictl_fm_cap, &fm_ibc);
3371 3376
3372 3377 if (ahci_ctlp->ahcictl_fm_cap == DDI_FM_NOT_CAPABLE) {
3373 3378 cmn_err(CE_WARN, "!ahci%d: fma init failed.",
3374 3379 ddi_get_instance(ahci_ctlp->ahcictl_dip));
3375 3380 return;
3376 3381 }
3377 3382 /*
3378 3383 * Initialize pci ereport capabilities if ereport
3379 3384 * capable (should always be.)
3380 3385 */
3381 3386 if (DDI_FM_EREPORT_CAP(ahci_ctlp->ahcictl_fm_cap) ||
3382 3387 DDI_FM_ERRCB_CAP(ahci_ctlp->ahcictl_fm_cap)) {
3383 3388 pci_ereport_setup(ahci_ctlp->ahcictl_dip);
3384 3389 }
3385 3390
3386 3391 /*
3387 3392 * Register error callback if error callback capable.
3388 3393 */
3389 3394 if (DDI_FM_ERRCB_CAP(ahci_ctlp->ahcictl_fm_cap)) {
3390 3395 ddi_fm_handler_register(ahci_ctlp->ahcictl_dip,
3391 3396 ahci_fm_error_cb, (void *) ahci_ctlp);
3392 3397 }
3393 3398
3394 3399 AHCIDBG(AHCIDBG_INIT, ahci_ctlp,
3395 3400 "ahci_fm_fini: fma enabled.", NULL);
3396 3401 }
3397 3402 }
3398 3403
3399 3404 /*
3400 3405 * Releases fma capabilities and un-registers with IO fault services.
3401 3406 */
3402 3407 static void
3403 3408 ahci_fm_fini(ahci_ctl_t *ahci_ctlp)
3404 3409 {
3405 3410 /* Only unregister FMA capabilities if registered */
3406 3411 if (ahci_ctlp->ahcictl_fm_cap) {
3407 3412 /*
3408 3413 * Un-register error callback if error callback capable.
3409 3414 */
3410 3415 if (DDI_FM_ERRCB_CAP(ahci_ctlp->ahcictl_fm_cap)) {
3411 3416 ddi_fm_handler_unregister(ahci_ctlp->ahcictl_dip);
3412 3417 }
3413 3418
3414 3419 /*
3415 3420 * Release any resources allocated by pci_ereport_setup()
3416 3421 */
3417 3422 if (DDI_FM_EREPORT_CAP(ahci_ctlp->ahcictl_fm_cap) ||
3418 3423 DDI_FM_ERRCB_CAP(ahci_ctlp->ahcictl_fm_cap)) {
3419 3424 pci_ereport_teardown(ahci_ctlp->ahcictl_dip);
3420 3425 }
3421 3426
3422 3427 /* Unregister from IO Fault Services */
3423 3428 ddi_fm_fini(ahci_ctlp->ahcictl_dip);
3424 3429
3425 3430 /* Adjust access and dma attributes for FMA */
3426 3431 accattr.devacc_attr_access = DDI_DEFAULT_ACC;
3427 3432 buffer_dma_attr.dma_attr_flags &= ~DDI_DMA_FLAGERR;
3428 3433 rcvd_fis_dma_attr.dma_attr_flags &= ~DDI_DMA_FLAGERR;
3429 3434 cmd_list_dma_attr.dma_attr_flags &= ~DDI_DMA_FLAGERR;
3430 3435 cmd_table_dma_attr.dma_attr_flags &= ~DDI_DMA_FLAGERR;
3431 3436
3432 3437 AHCIDBG(AHCIDBG_INIT, ahci_ctlp,
3433 3438 "ahci_fm_fini: fma disabled.", NULL);
3434 3439 }
3435 3440 }
3436 3441
3437 3442 /*ARGSUSED*/
3438 3443 static int
3439 3444 ahci_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, const void *impl_data)
3440 3445 {
3441 3446 /*
3442 3447 * as the driver can always deal with an error in any dma or
3443 3448 * access handle, we can just return the fme_status value.
3444 3449 */
3445 3450 pci_ereport_post(dip, err, NULL);
3446 3451 return (err->fme_status);
3447 3452 }
3448 3453
3449 3454 int
3450 3455 ahci_check_acc_handle(ddi_acc_handle_t handle)
3451 3456 {
3452 3457 ddi_fm_error_t de;
3453 3458
3454 3459 ddi_fm_acc_err_get(handle, &de, DDI_FME_VERSION);
3455 3460 return (de.fme_status);
3456 3461 }
3457 3462
3458 3463 int
3459 3464 ahci_check_dma_handle(ddi_dma_handle_t handle)
3460 3465 {
3461 3466 ddi_fm_error_t de;
3462 3467
3463 3468 ddi_fm_dma_err_get(handle, &de, DDI_FME_VERSION);
3464 3469 return (de.fme_status);
3465 3470 }
3466 3471
3467 3472 /*
3468 3473 * Generate an ereport
3469 3474 */
3470 3475 void
3471 3476 ahci_fm_ereport(ahci_ctl_t *ahci_ctlp, char *detail)
3472 3477 {
3473 3478 uint64_t ena;
3474 3479 char buf[FM_MAX_CLASS];
3475 3480
3476 3481 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", DDI_FM_DEVICE, detail);
3477 3482 ena = fm_ena_generate(0, FM_ENA_FMT1);
3478 3483 if (DDI_FM_EREPORT_CAP(ahci_ctlp->ahcictl_fm_cap)) {
3479 3484 ddi_fm_ereport_post(ahci_ctlp->ahcictl_dip, buf, ena,
3480 3485 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8,
3481 3486 FM_EREPORT_VERSION, NULL);
3482 3487 }
3483 3488 }
3484 3489
3485 3490 /*
3486 3491 * Check if all handles are correctly allocated.
3487 3492 */
3488 3493 static int
3489 3494 ahci_check_all_handle(ahci_ctl_t *ahci_ctlp)
3490 3495 {
3491 3496 int port;
3492 3497
3493 3498 if (ahci_check_ctl_handle(ahci_ctlp) != DDI_SUCCESS) {
3494 3499 return (DDI_FAILURE);
3495 3500 }
3496 3501
3497 3502 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) {
3498 3503 ahci_port_t *ahci_portp;
3499 3504
3500 3505 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port))
3501 3506 continue;
3502 3507
3503 3508 ahci_portp = ahci_ctlp->ahcictl_ports[port];
3504 3509
3505 3510 mutex_enter(&ahci_portp->ahciport_mutex);
3506 3511 if (ahci_check_port_handle(ahci_ctlp, port) != DDI_SUCCESS) {
3507 3512 mutex_exit(&ahci_portp->ahciport_mutex);
3508 3513 return (DDI_FAILURE);
3509 3514 }
3510 3515 mutex_exit(&ahci_portp->ahciport_mutex);
3511 3516 }
3512 3517
3513 3518 return (DDI_SUCCESS);
3514 3519 }
3515 3520
3516 3521 /*
3517 3522 * Check the access handles for the controller. Note that
3518 3523 * ahcictl_pci_conf_handle is only used in attach process.
3519 3524 */
3520 3525 static int
3521 3526 ahci_check_ctl_handle(ahci_ctl_t *ahci_ctlp)
3522 3527 {
3523 3528 if ((ahci_check_acc_handle(ahci_ctlp->
3524 3529 ahcictl_pci_conf_handle) != DDI_FM_OK) ||
3525 3530 (ahci_check_acc_handle(ahci_ctlp->
3526 3531 ahcictl_ahci_acc_handle) != DDI_FM_OK)) {
3527 3532 return (DDI_FAILURE);
3528 3533 }
3529 3534 return (DDI_SUCCESS);
3530 3535 }
3531 3536
3532 3537 /*
3533 3538 * Check the DMA handles and the access handles of a controller port.
3534 3539 */
3535 3540 static int
3536 3541 ahci_check_port_handle(ahci_ctl_t *ahci_ctlp, int port)
3537 3542 {
3538 3543 ahci_port_t *ahci_portp = ahci_ctlp->ahcictl_ports[port];
3539 3544 int slot;
3540 3545
3541 3546 ASSERT(MUTEX_HELD(&ahci_portp->ahciport_mutex));
3542 3547
3543 3548 if ((ahci_check_dma_handle(ahci_portp->
3544 3549 ahciport_rcvd_fis_dma_handle) != DDI_FM_OK) ||
3545 3550 (ahci_check_dma_handle(ahci_portp->
3546 3551 ahciport_cmd_list_dma_handle) != DDI_FM_OK) ||
3547 3552 (ahci_check_acc_handle(ahci_portp->
3548 3553 ahciport_rcvd_fis_acc_handle) != DDI_FM_OK) ||
3549 3554 (ahci_check_acc_handle(ahci_portp->
3550 3555 ahciport_cmd_list_acc_handle) != DDI_FM_OK)) {
3551 3556 return (DDI_FAILURE);
3552 3557 }
3553 3558 for (slot = 0; slot < ahci_ctlp->ahcictl_num_cmd_slots; slot++) {
3554 3559 if (ahci_check_slot_handle(ahci_portp, slot)
3555 3560 != DDI_SUCCESS) {
3556 3561 return (DDI_FAILURE);
3557 3562 }
3558 3563 }
3559 3564 return (DDI_SUCCESS);
3560 3565 }
3561 3566
3562 3567 /*
3563 3568 * Check the DMA handles and the access handles of a cmd table slot.
3564 3569 */
3565 3570 static int
3566 3571 ahci_check_slot_handle(ahci_port_t *ahci_portp, int slot)
3567 3572 {
3568 3573 ASSERT(MUTEX_HELD(&ahci_portp->ahciport_mutex));
3569 3574
3570 3575 if ((ahci_check_acc_handle(ahci_portp->
3571 3576 ahciport_cmd_tables_acc_handle[slot]) != DDI_FM_OK) ||
3572 3577 (ahci_check_dma_handle(ahci_portp->
3573 3578 ahciport_cmd_tables_dma_handle[slot]) != DDI_FM_OK)) {
3574 3579 return (DDI_FAILURE);
3575 3580 }
3576 3581 return (DDI_SUCCESS);
3577 3582 }
3578 3583
3579 3584 /*
3580 3585 * Allocate the ports structure, only called by ahci_attach
3581 3586 */
3582 3587 static int
3583 3588 ahci_alloc_ports_state(ahci_ctl_t *ahci_ctlp)
3584 3589 {
3585 3590 int port, cport = 0;
3586 3591
3587 3592 AHCIDBG(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp,
3588 3593 "ahci_alloc_ports_state enter", NULL);
3589 3594
3590 3595 mutex_enter(&ahci_ctlp->ahcictl_mutex);
3591 3596
3592 3597 /* Allocate structures only for the implemented ports */
3593 3598 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) {
3594 3599 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) {
3595 3600 AHCIDBG(AHCIDBG_INIT, ahci_ctlp,
3596 3601 "hba port %d not implemented", port);
3597 3602 continue;
3598 3603 }
3599 3604
3600 3605 ahci_ctlp->ahcictl_cport_to_port[cport] = (uint8_t)port;
3601 3606 ahci_ctlp->ahcictl_port_to_cport[port] =
3602 3607 (uint8_t)cport++;
3603 3608
3604 3609 if (ahci_alloc_port_state(ahci_ctlp, port) != AHCI_SUCCESS) {
3605 3610 goto err_out;
3606 3611 }
3607 3612 }
3608 3613
3609 3614 mutex_exit(&ahci_ctlp->ahcictl_mutex);
3610 3615 return (AHCI_SUCCESS);
3611 3616
3612 3617 err_out:
3613 3618 for (port--; port >= 0; port--) {
3614 3619 if (AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) {
3615 3620 ahci_dealloc_port_state(ahci_ctlp, port);
3616 3621 }
3617 3622 }
3618 3623
3619 3624 mutex_exit(&ahci_ctlp->ahcictl_mutex);
3620 3625 return (AHCI_FAILURE);
3621 3626 }
3622 3627
3623 3628 /*
3624 3629 * Reverse of ahci_alloc_ports_state(), only called by ahci_detach
3625 3630 */
3626 3631 static void
3627 3632 ahci_dealloc_ports_state(ahci_ctl_t *ahci_ctlp)
3628 3633 {
3629 3634 int port;
3630 3635
3631 3636 mutex_enter(&ahci_ctlp->ahcictl_mutex);
3632 3637 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) {
3633 3638 /* if this port is implemented by the HBA */
3634 3639 if (AHCI_PORT_IMPLEMENTED(ahci_ctlp, port))
3635 3640 ahci_dealloc_port_state(ahci_ctlp, port);
3636 3641 }
3637 3642 mutex_exit(&ahci_ctlp->ahcictl_mutex);
3638 3643 }
3639 3644
3640 3645 /*
3641 3646 * Drain the taskq.
3642 3647 */
3643 3648 static void
3644 3649 ahci_drain_ports_taskq(ahci_ctl_t *ahci_ctlp)
3645 3650 {
3646 3651 ahci_port_t *ahci_portp;
3647 3652 int port;
3648 3653
3649 3654 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) {
3650 3655 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) {
3651 3656 continue;
3652 3657 }
3653 3658
3654 3659 ahci_portp = ahci_ctlp->ahcictl_ports[port];
3655 3660
3656 3661 mutex_enter(&ahci_portp->ahciport_mutex);
3657 3662 ddi_taskq_wait(ahci_portp->ahciport_event_taskq);
3658 3663 mutex_exit(&ahci_portp->ahciport_mutex);
3659 3664 }
3660 3665 }
3661 3666
3662 3667 /*
3663 3668 * Initialize the controller and all ports. And then try to start the ports
3664 3669 * if there are devices attached.
3665 3670 *
3666 3671 * This routine can be called from three seperate cases: DDI_ATTACH,
3667 3672 * PM_LEVEL_D0 and DDI_RESUME. The DDI_ATTACH case is different from
3668 3673 * other two cases; device signature probing are attempted only during
3669 3674 * DDI_ATTACH case.
3670 3675 */
3671 3676 static int
3672 3677 ahci_initialize_controller(ahci_ctl_t *ahci_ctlp)
3673 3678 {
3674 3679 ahci_port_t *ahci_portp;
3675 3680 ahci_addr_t addr;
3676 3681 int port;
3677 3682
3678 3683 AHCIDBG(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp,
3679 3684 "ahci_initialize_controller enter", NULL);
3680 3685
3681 3686 /* Disable the whole controller interrupts */
3682 3687 mutex_enter(&ahci_ctlp->ahcictl_mutex);
3683 3688 ahci_disable_all_intrs(ahci_ctlp);
3684 3689 mutex_exit(&ahci_ctlp->ahcictl_mutex);
3685 3690
3686 3691 /* Initialize the implemented ports and structures */
3687 3692 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) {
3688 3693 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) {
3689 3694 continue;
3690 3695 }
3691 3696
3692 3697 ahci_portp = ahci_ctlp->ahcictl_ports[port];
3693 3698 mutex_enter(&ahci_portp->ahciport_mutex);
3694 3699
3695 3700 /*
3696 3701 * Ensure that the controller is not in the running state
3697 3702 * by checking every implemented port's PxCMD register
3698 3703 */
3699 3704 AHCI_ADDR_SET_PORT(&addr, (uint8_t)port);
3700 3705
3701 3706 if (ahci_initialize_port(ahci_ctlp, ahci_portp, &addr)
3702 3707 != AHCI_SUCCESS) {
3703 3708 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
3704 3709 "ahci_initialize_controller: failed to "
3705 3710 "initialize port %d", port);
3706 3711 /*
3707 3712 * Set the port state to SATA_PSTATE_FAILED if
3708 3713 * failed to initialize it.
3709 3714 */
3710 3715 ahci_portp->ahciport_port_state = SATA_PSTATE_FAILED;
3711 3716 }
3712 3717
3713 3718 mutex_exit(&ahci_portp->ahciport_mutex);
3714 3719 }
3715 3720
3716 3721 /* Enable the whole controller interrupts */
3717 3722 mutex_enter(&ahci_ctlp->ahcictl_mutex);
3718 3723 ahci_enable_all_intrs(ahci_ctlp);
3719 3724 mutex_exit(&ahci_ctlp->ahcictl_mutex);
3720 3725
3721 3726 return (AHCI_SUCCESS);
3722 3727 }
3723 3728
3724 3729 /*
3725 3730 * Reverse of ahci_initialize_controller()
3726 3731 *
3727 3732 * We only need to stop the ports and disable the interrupt.
3728 3733 */
3729 3734 static void
3730 3735 ahci_uninitialize_controller(ahci_ctl_t *ahci_ctlp)
3731 3736 {
3732 3737 ahci_port_t *ahci_portp;
3733 3738 int port;
3734 3739
3735 3740 AHCIDBG(AHCIDBG_INIT, ahci_ctlp,
3736 3741 "ahci_uninitialize_controller enter", NULL);
3737 3742
3738 3743 /* disable all the interrupts. */
3739 3744 mutex_enter(&ahci_ctlp->ahcictl_mutex);
3740 3745 ahci_disable_all_intrs(ahci_ctlp);
3741 3746 mutex_exit(&ahci_ctlp->ahcictl_mutex);
3742 3747
3743 3748 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) {
3744 3749 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) {
3745 3750 continue;
3746 3751 }
3747 3752
3748 3753 ahci_portp = ahci_ctlp->ahcictl_ports[port];
3749 3754
3750 3755 /* Stop the port by clearing PxCMD.ST */
3751 3756 mutex_enter(&ahci_portp->ahciport_mutex);
3752 3757
3753 3758 /*
3754 3759 * Here we must disable the port interrupt because
3755 3760 * ahci_disable_all_intrs only clear GHC.IE, and IS
3756 3761 * register will be still set if PxIE is enabled.
3757 3762 * When ahci shares one IRQ with other drivers, the
3758 3763 * intr handler may claim the intr mistakenly.
3759 3764 */
3760 3765 ahci_disable_port_intrs(ahci_ctlp, port);
3761 3766 (void) ahci_put_port_into_notrunning_state(ahci_ctlp,
3762 3767 ahci_portp, port);
3763 3768 mutex_exit(&ahci_portp->ahciport_mutex);
3764 3769 }
3765 3770 }
3766 3771
3767 3772 /*
3768 3773 * ahci_alloc_pmult()
3769 3774 * 1. Setting HBA port registers which are necessary for a port multiplier.
3770 3775 * (Set PxCMD.PMA while PxCMD.ST is '0')
3771 3776 * 2. Allocate ahci_pmult_info structure.
3772 3777 *
3773 3778 * NOTE: Must stop port before the function is called.
3774 3779 */
3775 3780 static void
3776 3781 ahci_alloc_pmult(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp)
3777 3782 {
3778 3783 uint32_t port_cmd_status;
3779 3784 uint8_t port = ahci_portp->ahciport_port_num;
3780 3785
3781 3786 ASSERT(MUTEX_HELD(&ahci_portp->ahciport_mutex));
3782 3787
3783 3788 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
3784 3789 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port));
3785 3790
3786 3791 /* The port must have been stopped before. */
3787 3792 ASSERT(!(port_cmd_status & AHCI_CMD_STATUS_ST));
3788 3793
3789 3794 if (!(port_cmd_status & AHCI_CMD_STATUS_PMA)) {
3790 3795 /* set PMA bit */
3791 3796 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
3792 3797 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port),
3793 3798 port_cmd_status|AHCI_CMD_STATUS_PMA);
3794 3799
3795 3800 AHCIDBG(AHCIDBG_INIT|AHCIDBG_PMULT, ahci_ctlp,
3796 3801 "ahci_alloc_pmult: "
3797 3802 "PxCMD.PMA bit set at port %d.", port);
3798 3803 }
3799 3804
3800 3805 /* Allocate port multiplier information structure */
3801 3806 if (ahci_portp->ahciport_pmult_info == NULL) {
3802 3807 ahci_portp->ahciport_pmult_info = (ahci_pmult_info_t *)
3803 3808 kmem_zalloc(sizeof (ahci_pmult_info_t), KM_SLEEP);
3804 3809 }
3805 3810
3806 3811 ASSERT(ahci_portp->ahciport_pmult_info != NULL);
3807 3812 }
3808 3813
3809 3814 /*
3810 3815 * ahci_dealloc_pmult()
3811 3816 * 1. Clearing related registers when a port multiplier is detached.
3812 3817 * (Clear PxCMD.PMA while PxCMD.ST is '0')
3813 3818 * 2. Deallocate ahci_pmult_info structure.
3814 3819 *
3815 3820 * NOTE: Must stop port before the function is called.
3816 3821 */
3817 3822 static void
3818 3823 ahci_dealloc_pmult(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp)
3819 3824 {
3820 3825 uint32_t port_cmd_status;
3821 3826 uint8_t port = ahci_portp->ahciport_port_num;
3822 3827
3823 3828 ASSERT(MUTEX_HELD(&ahci_portp->ahciport_mutex));
3824 3829
3825 3830 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
3826 3831 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port));
3827 3832
3828 3833 if (port_cmd_status & AHCI_CMD_STATUS_PMA) {
3829 3834 /* Clear PMA bit */
3830 3835 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
3831 3836 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port),
3832 3837 (port_cmd_status & (~AHCI_CMD_STATUS_PMA)));
3833 3838
3834 3839 AHCIDBG(AHCIDBG_INIT|AHCIDBG_PMULT, ahci_ctlp,
3835 3840 "ahci_dealloc_pmult: "
3836 3841 "PxCMD.PMA bit cleared at port %d.", port);
3837 3842 }
3838 3843
3839 3844 /* Release port multiplier information structure */
3840 3845 if (ahci_portp->ahciport_pmult_info != NULL) {
3841 3846 kmem_free(ahci_portp->ahciport_pmult_info,
3842 3847 sizeof (ahci_pmult_info_t));
3843 3848 ahci_portp->ahciport_pmult_info = NULL;
3844 3849 }
3845 3850 }
3846 3851
3847 3852 /*
3848 3853 * Staggered Spin-up.
3849 3854 */
3850 3855 static void
3851 3856 ahci_staggered_spin_up(ahci_ctl_t *ahci_ctlp, uint8_t port)
3852 3857 {
3853 3858 uint32_t cap_status;
3854 3859 uint32_t port_cmd_status;
3855 3860
3856 3861 ASSERT(MUTEX_HELD(&ahci_ctlp->ahcictl_ports[port]->ahciport_mutex));
3857 3862
3858 3863 cap_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
3859 3864 (uint32_t *)AHCI_GLOBAL_CAP(ahci_ctlp));
3860 3865
3861 3866 /* Check for staggered spin-up support */
3862 3867 if (!(cap_status & AHCI_HBA_CAP_SSS))
3863 3868 return;
3864 3869
3865 3870 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
3866 3871 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port));
3867 3872
3868 3873 /* If PxCMD.SUD == 1, no staggered spin-up is needed */
3869 3874 if (port_cmd_status & AHCI_CMD_STATUS_SUD)
3870 3875 return;
3871 3876
3872 3877 AHCIDBG(AHCIDBG_INIT, ahci_ctlp, "Spin-up at port %d", port);
3873 3878
3874 3879 /* Set PxCMD.SUD */
3875 3880 port_cmd_status |= AHCI_CMD_STATUS_SUD;
3876 3881 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
3877 3882 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port),
3878 3883 port_cmd_status);
3879 3884 }
3880 3885
3881 3886 /*
3882 3887 * The routine is to initialize a port. First put the port in NotRunning
3883 3888 * state, then enable port interrupt and clear Serror register. And under
3884 3889 * AHCI_ATTACH case, find device signature and then try to start the port.
3885 3890 *
3886 3891 * Called by
3887 3892 * 1. ahci_initialize_controller
3888 3893 * 2. ahci_intr_phyrdy_change (hotplug)
3889 3894 */
3890 3895 static int
3891 3896 ahci_initialize_port(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp,
3892 3897 ahci_addr_t *addrp)
3893 3898 {
3894 3899 uint32_t port_sstatus, port_task_file, port_cmd_status;
3895 3900 uint8_t port = addrp->aa_port;
3896 3901 boolean_t resuming = B_TRUE; /* processing DDI_RESUME */
3897 3902 int ret;
3898 3903
3899 3904 ASSERT(MUTEX_HELD(&ahci_portp->ahciport_mutex));
3900 3905
3901 3906 /* AHCI_ADDR_PORT: We've no idea of the attached device here. */
3902 3907 ASSERT(AHCI_ADDR_IS_PORT(addrp));
3903 3908
3904 3909 /*
3905 3910 * At the time being, only probe ports/devices and get the types of
3906 3911 * attached devices during DDI_ATTACH. In fact, the device can be
3907 3912 * changed during power state changes, but at the time being, we
3908 3913 * don't support the situation.
3909 3914 */
3910 3915 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_HOTPLUG) {
3911 3916 resuming = B_FALSE;
3912 3917 } else {
3913 3918 /* check for DDI_RESUME case */
3914 3919 mutex_exit(&ahci_portp->ahciport_mutex);
3915 3920 mutex_enter(&ahci_ctlp->ahcictl_mutex);
3916 3921 if (ahci_ctlp->ahcictl_flags & AHCI_ATTACH)
3917 3922 resuming = B_FALSE;
3918 3923 mutex_exit(&ahci_ctlp->ahcictl_mutex);
3919 3924 mutex_enter(&ahci_portp->ahciport_mutex);
3920 3925 }
3921 3926
3922 3927 if (resuming) {
3923 3928 /*
3924 3929 * During the resume, we need to set the PxCLB, PxCLBU, PxFB
3925 3930 * and PxFBU registers in case these registers were cleared
3926 3931 * during the suspend.
3927 3932 */
3928 3933 AHCIDBG(AHCIDBG_PM, ahci_ctlp,
3929 3934 "ahci_initialize_port: port %d "
3930 3935 "set PxCLB, PxCLBU, PxFB and PxFBU "
3931 3936 "during resume", port);
3932 3937
3933 3938 if (ahci_setup_port_base_addresses(ahci_ctlp, ahci_portp) !=
3934 3939 AHCI_SUCCESS)
3935 3940 return (AHCI_FAILURE);
3936 3941 }
3937 3942
3938 3943 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
3939 3944 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port));
3940 3945
3941 3946 AHCIDBG(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp,
3942 3947 "ahci_initialize_port: port %d ", port);
3943 3948
3944 3949 /*
3945 3950 * Check whether the port is in NotRunning state, if not,
3946 3951 * put the port in NotRunning state
3947 3952 */
3948 3953 if (port_cmd_status &
3949 3954 (AHCI_CMD_STATUS_ST |
3950 3955 AHCI_CMD_STATUS_CR |
3951 3956 AHCI_CMD_STATUS_FRE |
3952 3957 AHCI_CMD_STATUS_FR)) {
3953 3958 (void) ahci_put_port_into_notrunning_state(ahci_ctlp,
3954 3959 ahci_portp, port);
3955 3960 }
3956 3961
3957 3962 /* Make sure the drive is spun-up */
3958 3963 ahci_staggered_spin_up(ahci_ctlp, port);
3959 3964
3960 3965 /* Disable interrupt */
3961 3966 ahci_disable_port_intrs(ahci_ctlp, port);
3962 3967
3963 3968 /* Device is unknown at first */
3964 3969 AHCIPORT_SET_DEV_TYPE(ahci_portp, addrp, SATA_DTYPE_UNKNOWN);
3965 3970
3966 3971 /* Disable the interface power management */
3967 3972 ahci_disable_interface_pm(ahci_ctlp, port);
3968 3973
3969 3974 port_sstatus = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
3970 3975 (uint32_t *)AHCI_PORT_PxSSTS(ahci_ctlp, port));
3971 3976 port_task_file = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
3972 3977 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port));
3973 3978
3974 3979 /* Check physcial link status */
3975 3980 if (SSTATUS_GET_IPM(port_sstatus) == SSTATUS_IPM_NODEV_NOPHYCOM ||
3976 3981 SSTATUS_GET_DET(port_sstatus) == SSTATUS_DET_DEVPRE_NOPHYCOM ||
3977 3982
3978 3983 /* Check interface status */
3979 3984 port_task_file & AHCI_TFD_STS_BSY ||
3980 3985 port_task_file & AHCI_TFD_STS_DRQ ||
3981 3986
3982 3987 /* Check whether port reset must be executed */
3983 3988 ahci_ctlp->ahcictl_cap & AHCI_CAP_INIT_PORT_RESET ||
3984 3989
3985 3990 /* Always reset port on RESUME */
3986 3991 resuming != B_FALSE) {
3987 3992
3988 3993 /* Something went wrong, we need do some reset things */
3989 3994 ret = ahci_port_reset(ahci_ctlp, ahci_portp, addrp);
3990 3995
3991 3996 /* Does port reset succeed on HBA port? */
3992 3997 if (ret != AHCI_SUCCESS) {
3993 3998 AHCIDBG(AHCIDBG_INIT|AHCIDBG_ERRS, ahci_ctlp,
3994 3999 "ahci_initialize_port:"
3995 4000 "port reset failed at port %d", port);
3996 4001 return (AHCI_FAILURE);
3997 4002 }
3998 4003
3999 4004 /* Is port failed? */
4000 4005 if (AHCIPORT_GET_STATE(ahci_portp, addrp) &
4001 4006 SATA_PSTATE_FAILED) {
4002 4007 AHCIDBG(AHCIDBG_INIT|AHCIDBG_ERRS, ahci_ctlp,
4003 4008 "ahci_initialize_port: port %d state 0x%x",
4004 4009 port, ahci_portp->ahciport_port_state);
4005 4010 return (AHCI_FAILURE);
4006 4011 }
4007 4012 }
4008 4013
4009 4014 AHCIPORT_SET_STATE(ahci_portp, addrp, SATA_STATE_READY);
4010 4015 AHCIDBG(AHCIDBG_INIT, ahci_ctlp, "port %d is ready now.", port);
4011 4016
4012 4017 /*
4013 4018 * Try to get the device signature if the port is not empty.
4014 4019 */
4015 4020 if (!resuming && AHCIPORT_DEV_TYPE(ahci_portp, addrp) !=
4016 4021 SATA_DTYPE_NONE)
4017 4022 ahci_find_dev_signature(ahci_ctlp, ahci_portp, addrp);
4018 4023
4019 4024 /* Return directly if no device connected */
4020 4025 if (AHCIPORT_DEV_TYPE(ahci_portp, addrp) == SATA_DTYPE_NONE) {
4021 4026 AHCIDBG(AHCIDBG_INIT, ahci_ctlp,
4022 4027 "No device connected to port %d", port);
4023 4028 goto out;
4024 4029 }
4025 4030
4026 4031 /* If this is a port multiplier, we need do some initialization */
4027 4032 if (AHCIPORT_DEV_TYPE(ahci_portp, addrp) == SATA_DTYPE_PMULT) {
4028 4033 AHCIDBG(AHCIDBG_INFO|AHCIDBG_PMULT, ahci_ctlp,
4029 4034 "Port multiplier found at port %d", port);
4030 4035 ahci_alloc_pmult(ahci_ctlp, ahci_portp);
4031 4036 }
4032 4037
4033 4038 /* Try to start the port */
4034 4039 if (ahci_start_port(ahci_ctlp, ahci_portp, port)
4035 4040 != AHCI_SUCCESS) {
4036 4041 AHCIDBG(AHCIDBG_INIT, ahci_ctlp,
4037 4042 "failed to start port %d", port);
4038 4043 return (AHCI_FAILURE);
4039 4044 }
4040 4045 out:
4041 4046 /* Enable port interrupts */
4042 4047 ahci_enable_port_intrs(ahci_ctlp, port);
4043 4048
4044 4049 return (AHCI_SUCCESS);
4045 4050 }
4046 4051
4047 4052 /*
4048 4053 * Handle hardware defect, and check the capabilities. For example,
4049 4054 * power management capabilty and MSI capability.
4050 4055 */
4051 4056 static int
4052 4057 ahci_config_space_init(ahci_ctl_t *ahci_ctlp)
4053 4058 {
4054 4059 ushort_t caps_ptr, cap_count, cap;
4055 4060 #if AHCI_DEBUG
4056 4061 ushort_t pmcap, pmcsr;
4057 4062 ushort_t msimc;
4058 4063 #endif
4059 4064 uint8_t revision;
4060 4065
4061 4066 ahci_ctlp->ahcictl_venid =
4062 4067 pci_config_get16(ahci_ctlp->ahcictl_pci_conf_handle,
4063 4068 PCI_CONF_VENID);
4064 4069
4065 4070 ahci_ctlp->ahcictl_devid =
4066 4071 pci_config_get16(ahci_ctlp->ahcictl_pci_conf_handle,
4067 4072 PCI_CONF_DEVID);
4068 4073
4069 4074 /*
4070 4075 * Modify dma_attr_align of ahcictl_buffer_dma_attr. For VT8251, those
4071 4076 * controllers with 0x00 revision id work on 4-byte aligned buffer,
4072 4077 * which is a bug and was fixed after 0x00 revision id controllers.
4073 4078 *
4074 4079 * Moreover, VT8251 cannot use multiple command slots in the command
4075 4080 * list for non-queued commands because the previous register content
4076 4081 * of PxCI can be re-written in the register write, so a flag will be
4077 4082 * set to record this defect - AHCI_CAP_NO_MCMDLIST_NONQUEUE.
4078 4083 *
4079 4084 * For VT8251, software reset also has the same defect as the below
4080 4085 * AMD/ATI chipset. That is, software reset will get failed if 0xf
4081 4086 * is filled in pmport field. Therefore, another software reset need
4082 4087 * to be done with 0 filled in pmport field.
4083 4088 */
4084 4089 if (ahci_ctlp->ahcictl_venid == VIA_VENID) {
4085 4090 revision = pci_config_get8(ahci_ctlp->ahcictl_pci_conf_handle,
4086 4091 PCI_CONF_REVID);
4087 4092 AHCIDBG(AHCIDBG_INIT, ahci_ctlp,
4088 4093 "revision id = 0x%x", revision);
4089 4094 if (revision == 0x00) {
4090 4095 ahci_ctlp->ahcictl_buffer_dma_attr.dma_attr_align = 0x4;
4091 4096 AHCIDBG(AHCIDBG_INIT, ahci_ctlp,
4092 4097 "change ddi_attr_align to 0x4", NULL);
4093 4098 }
4094 4099
4095 4100 ahci_ctlp->ahcictl_cap |= AHCI_CAP_NO_MCMDLIST_NONQUEUE;
4096 4101 AHCIDBG(AHCIDBG_INIT, ahci_ctlp,
4097 4102 "VT8251 cannot use multiple command lists for "
4098 4103 "non-queued commands", NULL);
4099 4104
4100 4105 ahci_ctlp->ahcictl_cap |= AHCI_CAP_SRST_NO_HOSTPORT;
4101 4106 }
4102 4107
4103 4108 /*
4104 4109 * AMD/ATI SB600 (0x1002,0x4380) AHCI chipset doesn't support 64-bit
4105 4110 * DMA addressing for communication memory descriptors though S64A bit
4106 4111 * of CAP register declares it supports. Even though 64-bit DMA for
4107 4112 * data buffer works on ASUS M2A-VM with newer BIOS, three other
4108 4113 * motherboards are known not, so both AHCI_CAP_BUF_32BIT_DMA and
4109 4114 * AHCI_CAP_COMMU_32BIT_DMA are set for this controller.
4110 4115 *
4111 4116 * Due to certain hardware issue, the chipset must do port reset during
4112 4117 * initialization, otherwise, when retrieving device signature,
4113 4118 * software reset will get time out. So AHCI_CAP_INIT_PORT_RESET flag
4114 4119 * need to set.
4115 4120 *
4116 4121 * For this chipset software reset will get failure if the pmport of
4117 4122 * Register FIS was set with SATA_PMULT_HOSTPORT (0xf) and no port
4118 4123 * multiplier is connected to the port. In order to fix the issue,
4119 4124 * AHCI_CAP_SRST_NO_HOSTPORT flag need to be set, and once software
4120 4125 * reset got failure, the driver will try to do another software reset
4121 4126 * with pmport 0.
4122 4127 */
4123 4128 if (ahci_ctlp->ahcictl_venid == 0x1002 &&
4124 4129 ahci_ctlp->ahcictl_devid == 0x4380) {
4125 4130 ahci_ctlp->ahcictl_cap |= AHCI_CAP_BUF_32BIT_DMA;
4126 4131 ahci_ctlp->ahcictl_cap |= AHCI_CAP_COMMU_32BIT_DMA;
4127 4132 ahci_ctlp->ahcictl_cap |= AHCI_CAP_INIT_PORT_RESET;
4128 4133 ahci_ctlp->ahcictl_cap |= AHCI_CAP_SRST_NO_HOSTPORT;
4129 4134
4130 4135 AHCIDBG(AHCIDBG_INIT, ahci_ctlp,
4131 4136 "ATI SB600 cannot do 64-bit DMA for both data buffer and "
4132 4137 "communication memory descriptors though CAP indicates "
4133 4138 "support, so force it to use 32-bit DMA", NULL);
4134 4139 AHCIDBG(AHCIDBG_INIT, ahci_ctlp,
4135 4140 "ATI SB600 need to do a port reset during initialization",
4136 4141 NULL);
4137 4142 AHCIDBG(AHCIDBG_INIT, ahci_ctlp,
4138 4143 "ATI SB600 will get software reset failure if pmport "
4139 4144 "is set 0xf and no port multiplier is attached", NULL);
4140 4145 }
4141 4146
4142 4147 /*
4143 4148 * AMD/ATI SB700/710/750/800 and SP5100 AHCI chipset share the same
4144 4149 * vendor ID and device ID (0x1002,0x4391).
4145 4150 *
4146 4151 * SB700/750 AHCI chipset on some boards doesn't support 64-bit
4147 4152 * DMA addressing for communication memory descriptors though S64A bit
4148 4153 * of CAP register declares the support. However, it does support
4149 4154 * 64-bit DMA for data buffer. So only AHCI_CAP_COMMU_32BIT_DMA is
4150 4155 * set for this controller.
4151 4156 *
4152 4157 * SB710 has the same initialization issue as SB600, so it also need
4153 4158 * a port reset. That is AHCI_CAP_INIT_PORT_RESET need to set for it.
4154 4159 *
4155 4160 * SB700 also has the same issue about software reset, and thus
4156 4161 * AHCI_CAP_SRST_NO_HOSTPORT flag also is needed.
4157 4162 */
4158 4163 if (ahci_ctlp->ahcictl_venid == 0x1002 &&
4159 4164 ahci_ctlp->ahcictl_devid == 0x4391) {
4160 4165 ahci_ctlp->ahcictl_cap |= AHCI_CAP_COMMU_32BIT_DMA;
4161 4166 ahci_ctlp->ahcictl_cap |= AHCI_CAP_INIT_PORT_RESET;
4162 4167 ahci_ctlp->ahcictl_cap |= AHCI_CAP_SRST_NO_HOSTPORT;
4163 4168
4164 4169 AHCIDBG(AHCIDBG_INIT, ahci_ctlp,
4165 4170 "ATI SB700/750 cannot do 64-bit DMA for communication "
4166 4171 "memory descriptors though CAP indicates support, "
4167 4172 "so force it to use 32-bit DMA", NULL);
4168 4173 AHCIDBG(AHCIDBG_INIT, ahci_ctlp,
4169 4174 "ATI SB710 need to do a port reset during initialization",
4170 4175 NULL);
4171 4176 AHCIDBG(AHCIDBG_INIT, ahci_ctlp,
4172 4177 "ATI SB700 will get software reset failure if pmport "
4173 4178 "is set 0xf and no port multiplier is attached", NULL);
4174 4179 }
4175 4180
4176 4181 /*
4177 4182 * Check if capabilities list is supported and if so,
4178 4183 * get initial capabilities pointer and clear bits 0,1.
4179 4184 */
4180 4185 if (pci_config_get16(ahci_ctlp->ahcictl_pci_conf_handle,
4181 4186 PCI_CONF_STAT) & PCI_STAT_CAP) {
4182 4187 caps_ptr = P2ALIGN(pci_config_get8(
4183 4188 ahci_ctlp->ahcictl_pci_conf_handle,
4184 4189 PCI_CONF_CAP_PTR), 4);
4185 4190 } else {
4186 4191 caps_ptr = PCI_CAP_NEXT_PTR_NULL;
4187 4192 }
4188 4193
4189 4194 /*
4190 4195 * Walk capabilities if supported.
4191 4196 */
4192 4197 for (cap_count = 0; caps_ptr != PCI_CAP_NEXT_PTR_NULL; ) {
4193 4198
4194 4199 /*
4195 4200 * Check that we haven't exceeded the maximum number of
4196 4201 * capabilities and that the pointer is in a valid range.
4197 4202 */
4198 4203 if (++cap_count > PCI_CAP_MAX_PTR) {
4199 4204 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
4200 4205 "too many device capabilities", NULL);
4201 4206 return (AHCI_FAILURE);
4202 4207 }
4203 4208 if (caps_ptr < PCI_CAP_PTR_OFF) {
4204 4209 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
4205 4210 "capabilities pointer 0x%x out of range",
4206 4211 caps_ptr);
4207 4212 return (AHCI_FAILURE);
4208 4213 }
4209 4214
4210 4215 /*
4211 4216 * Get next capability and check that it is valid.
4212 4217 * For now, we only support power management.
4213 4218 */
4214 4219 cap = pci_config_get8(ahci_ctlp->ahcictl_pci_conf_handle,
4215 4220 caps_ptr);
4216 4221 switch (cap) {
4217 4222 case PCI_CAP_ID_PM:
4218 4223
4219 4224 /* power management supported */
4220 4225 ahci_ctlp->ahcictl_cap |= AHCI_CAP_PM;
4221 4226
4222 4227 /* Save PMCSR offset */
4223 4228 ahci_ctlp->ahcictl_pmcsr_offset = caps_ptr + PCI_PMCSR;
4224 4229
4225 4230 #if AHCI_DEBUG
4226 4231 pmcap = pci_config_get16(
4227 4232 ahci_ctlp->ahcictl_pci_conf_handle,
4228 4233 caps_ptr + PCI_PMCAP);
4229 4234 pmcsr = pci_config_get16(
4230 4235 ahci_ctlp->ahcictl_pci_conf_handle,
4231 4236 ahci_ctlp->ahcictl_pmcsr_offset);
4232 4237 AHCIDBG(AHCIDBG_PM, ahci_ctlp,
4233 4238 "Power Management capability found PCI_PMCAP "
4234 4239 "= 0x%x PCI_PMCSR = 0x%x", pmcap, pmcsr);
4235 4240 if ((pmcap & 0x3) == 0x3)
4236 4241 AHCIDBG(AHCIDBG_PM, ahci_ctlp,
4237 4242 "PCI Power Management Interface "
4238 4243 "spec 1.2 compliant", NULL);
4239 4244 #endif
4240 4245 break;
4241 4246
4242 4247 case PCI_CAP_ID_MSI:
4243 4248 #if AHCI_DEBUG
4244 4249 msimc = pci_config_get16(
4245 4250 ahci_ctlp->ahcictl_pci_conf_handle,
4246 4251 caps_ptr + PCI_MSI_CTRL);
4247 4252 AHCIDBG(AHCIDBG_MSI, ahci_ctlp,
4248 4253 "Message Signaled Interrupt capability found "
4249 4254 "MSICAP_MC.MMC = 0x%x", (msimc & 0xe) >> 1);
4250 4255 #endif
4251 4256 AHCIDBG(AHCIDBG_MSI, ahci_ctlp,
4252 4257 "MSI capability found", NULL);
4253 4258 break;
4254 4259
4255 4260 case PCI_CAP_ID_PCIX:
4256 4261 AHCIDBG(AHCIDBG_PM, ahci_ctlp,
4257 4262 "PCI-X capability found", NULL);
4258 4263 break;
4259 4264
4260 4265 case PCI_CAP_ID_PCI_E:
4261 4266 AHCIDBG(AHCIDBG_PM, ahci_ctlp,
4262 4267 "PCI Express capability found", NULL);
4263 4268 break;
4264 4269
4265 4270 case PCI_CAP_ID_MSI_X:
4266 4271 AHCIDBG(AHCIDBG_PM, ahci_ctlp,
4267 4272 "MSI-X capability found", NULL);
4268 4273 break;
4269 4274
4270 4275 case PCI_CAP_ID_SATA:
4271 4276 AHCIDBG(AHCIDBG_PM, ahci_ctlp,
4272 4277 "SATA capability found", NULL);
4273 4278 break;
4274 4279
4275 4280 case PCI_CAP_ID_VS:
4276 4281 AHCIDBG(AHCIDBG_PM, ahci_ctlp,
4277 4282 "Vendor Specific capability found", NULL);
4278 4283 break;
4279 4284
4280 4285 default:
4281 4286 AHCIDBG(AHCIDBG_PM, ahci_ctlp,
4282 4287 "unrecognized capability 0x%x", cap);
4283 4288 break;
4284 4289 }
4285 4290
4286 4291 /*
4287 4292 * Get next capabilities pointer and clear bits 0,1.
4288 4293 */
4289 4294 caps_ptr = P2ALIGN(pci_config_get8(
4290 4295 ahci_ctlp->ahcictl_pci_conf_handle,
4291 4296 (caps_ptr + PCI_CAP_NEXT_PTR)), 4);
4292 4297 }
4293 4298
4294 4299 return (AHCI_SUCCESS);
4295 4300 }
4296 4301
4297 4302 /*
4298 4303 * Read/Write a register at port multiplier by SATA READ PORTMULT / SATA WRITE
4299 4304 * PORTMULT command. SYNC & POLLING mode is used.
4300 4305 */
4301 4306 static int
4302 4307 ahci_rdwr_pmult(ahci_ctl_t *ahci_ctlp, ahci_addr_t *addrp,
4303 4308 uint8_t regn, uint32_t *pregv, uint8_t type)
4304 4309 {
4305 4310 ahci_port_t *ahci_portp;
4306 4311 ahci_addr_t pmult_addr;
4307 4312 sata_pkt_t *spkt;
4308 4313 sata_cmd_t *scmd;
4309 4314 sata_device_t sata_device;
4310 4315 uint8_t port = addrp->aa_port;
4311 4316 uint8_t pmport = addrp->aa_pmport;
4312 4317 uint8_t cport;
4313 4318 uint32_t intr_mask;
4314 4319 int rval;
4315 4320 char portstr[10];
4316 4321
4317 4322 SET_PORTSTR(portstr, addrp);
4318 4323 cport = ahci_ctlp->ahcictl_port_to_cport[port];
4319 4324 ahci_portp = ahci_ctlp->ahcictl_ports[port];
4320 4325
4321 4326 ASSERT(AHCI_ADDR_IS_PMPORT(addrp) || AHCI_ADDR_IS_PMULT(addrp));
4322 4327 ASSERT(MUTEX_HELD(&ahci_portp->ahciport_mutex));
4323 4328
4324 4329 /* Check the existence of the port multiplier */
4325 4330 if (ahci_portp->ahciport_device_type != SATA_DTYPE_PMULT)
4326 4331 return (AHCI_FAILURE);
4327 4332
4328 4333 /* Request a READ/WRITE PORTMULT sata packet. */
4329 4334 bzero(&sata_device, sizeof (sata_device_t));
4330 4335 sata_device.satadev_addr.cport = cport;
4331 4336 sata_device.satadev_addr.pmport = pmport;
4332 4337 sata_device.satadev_addr.qual = SATA_ADDR_PMULT;
4333 4338 sata_device.satadev_rev = SATA_DEVICE_REV;
4334 4339
4335 4340 /*
4336 4341 * Make sure no command is outstanding here. All R/W PMULT requests
4337 4342 * come from
4338 4343 *
4339 4344 * 1. ahci_attach()
4340 4345 * The port should be empty.
4341 4346 *
4342 4347 * 2. ahci_tran_probe_port()
4343 4348 * Any request from SATA framework (via ahci_tran_start) should be
4344 4349 * rejected if R/W PMULT command is outstanding.
4345 4350 *
4346 4351 * If we are doing mopping, do not check those flags because no
4347 4352 * command will be actually outstanding.
4348 4353 *
4349 4354 * If the port has been occupied by any other commands, the probe
4350 4355 * function will return a SATA_RETRY. SATA framework will retry
4351 4356 * later.
4352 4357 */
4353 4358 if (RDWR_PMULT_CMD_IN_PROGRESS(ahci_portp)) {
4354 4359 AHCIDBG(AHCIDBG_ERRS|AHCIDBG_PMULT, ahci_ctlp,
4355 4360 "R/W PMULT failed: R/W PMULT in progress at port %d.",
4356 4361 port, ahci_portp->ahciport_flags);
4357 4362 return (AHCI_FAILURE);
4358 4363 }
4359 4364
4360 4365 if (!(ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) && (
4361 4366 ERR_RETRI_CMD_IN_PROGRESS(ahci_portp) ||
4362 4367 NCQ_CMD_IN_PROGRESS(ahci_portp) ||
4363 4368 NON_NCQ_CMD_IN_PROGRESS(ahci_portp))) {
4364 4369 AHCIDBG(AHCIDBG_ERRS|AHCIDBG_PMULT, ahci_ctlp,
4365 4370 "R/W PMULT failed: port %d is occupied (flags 0x%x).",
4366 4371 port, ahci_portp->ahciport_flags);
4367 4372 return (AHCI_FAILURE);
4368 4373 }
4369 4374
4370 4375 /*
4371 4376 * The port multiplier is gone. This may happen when
4372 4377 * 1. Cutting off the power of an enclosure. The device lose the power
4373 4378 * before port multiplier.
4374 4379 * 2. Disconnecting the port multiplier during hot-plugging a sub-drive.
4375 4380 *
4376 4381 * The issued command should be aborted and the following command
4377 4382 * should not be continued.
4378 4383 */
4379 4384 if (!(ahci_portp->ahciport_port_state & SATA_STATE_READY)) {
4380 4385 AHCIDBG(AHCIDBG_ERRS|AHCIDBG_PMULT, ahci_ctlp,
4381 4386 "READ/WRITE PMULT failed: "
4382 4387 "port-mult is removed from port %d", port);
4383 4388 return (AHCI_FAILURE);
4384 4389 }
4385 4390
4386 4391 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_RDWR_PMULT;
4387 4392
4388 4393 spkt = sata_get_rdwr_pmult_pkt(ahci_ctlp->ahcictl_dip,
4389 4394 &sata_device, regn, *pregv, type);
4390 4395
4391 4396 /*
4392 4397 * READ/WRITE PORTMULT command is intended to sent to the control port
4393 4398 * of the port multiplier.
4394 4399 */
4395 4400 AHCI_ADDR_SET_PMULT(&pmult_addr, addrp->aa_port);
4396 4401
4397 4402 ahci_portp->ahciport_rdwr_pmult_pkt = spkt;
4398 4403
4399 4404 /* No interrupt here. Store the interrupt enable mask. */
4400 4405 intr_mask = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
4401 4406 (uint32_t *)AHCI_PORT_PxIE(ahci_ctlp, port));
4402 4407 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
4403 4408 (uint32_t *)AHCI_PORT_PxIE(ahci_ctlp, port), 0);
4404 4409
4405 4410 rval = ahci_do_sync_start(ahci_ctlp, ahci_portp, &pmult_addr, spkt);
4406 4411
4407 4412 if (rval == AHCI_SUCCESS &&
4408 4413 spkt->satapkt_reason == SATA_PKT_COMPLETED) {
4409 4414 if (type == SATA_RDWR_PMULT_PKT_TYPE_READ) {
4410 4415 scmd = &spkt->satapkt_cmd;
4411 4416 *pregv = scmd->satacmd_lba_high_lsb << 24 |
4412 4417 scmd->satacmd_lba_mid_lsb << 16 |
4413 4418 scmd->satacmd_lba_low_lsb << 8 |
4414 4419 scmd->satacmd_sec_count_lsb;
4415 4420 }
4416 4421 } else {
4417 4422 /* Failed or not completed. */
4418 4423 AHCIDBG(AHCIDBG_ERRS|AHCIDBG_PMULT, ahci_ctlp,
4419 4424 "ahci_rdwr_pmult: cannot [%s] %s[%d] at port %s",
4420 4425 type == SATA_RDWR_PMULT_PKT_TYPE_READ?"Read":"Write",
4421 4426 AHCI_ADDR_IS_PMULT(addrp)?"gscr":"pscr", regn, portstr);
4422 4427 rval = AHCI_FAILURE;
4423 4428 }
4424 4429 out:
4425 4430 /* Restore the interrupt mask */
4426 4431 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
4427 4432 (uint32_t *)AHCI_PORT_PxIE(ahci_ctlp, port), intr_mask);
4428 4433
4429 4434 ahci_portp->ahciport_flags &= ~AHCI_PORT_FLAG_RDWR_PMULT;
4430 4435 ahci_portp->ahciport_rdwr_pmult_pkt = NULL;
4431 4436 sata_free_rdwr_pmult_pkt(spkt);
4432 4437 return (rval);
4433 4438 }
4434 4439
4435 4440 static int
4436 4441 ahci_read_pmult(ahci_ctl_t *ahci_ctlp, ahci_addr_t *addrp,
4437 4442 uint8_t regn, uint32_t *pregv)
4438 4443 {
4439 4444 return ahci_rdwr_pmult(ahci_ctlp, addrp, regn, pregv,
4440 4445 SATA_RDWR_PMULT_PKT_TYPE_READ);
4441 4446 }
4442 4447
4443 4448 static int
4444 4449 ahci_write_pmult(ahci_ctl_t *ahci_ctlp, ahci_addr_t *addrp,
4445 4450 uint8_t regn, uint32_t regv)
4446 4451 {
4447 4452 return ahci_rdwr_pmult(ahci_ctlp, addrp, regn, ®v,
4448 4453 SATA_RDWR_PMULT_PKT_TYPE_WRITE);
4449 4454 }
4450 4455
4451 4456 #define READ_PMULT(addrp, r, pv, out) \
4452 4457 if (ahci_read_pmult(ahci_ctlp, addrp, r, pv) != AHCI_SUCCESS) \
4453 4458 goto out;
4454 4459
4455 4460 #define WRITE_PMULT(addrp, r, v, out) \
4456 4461 if (ahci_write_pmult(ahci_ctlp, addrp, r, v) != AHCI_SUCCESS) \
4457 4462 goto out;
4458 4463
4459 4464 /*
4460 4465 * Update sata registers on port multiplier, including GSCR/PSCR registers.
4461 4466 * ahci_update_pmult_gscr()
4462 4467 * ahci_update_pmult_pscr()
4463 4468 */
4464 4469 static int
4465 4470 ahci_update_pmult_gscr(ahci_ctl_t *ahci_ctlp, ahci_addr_t *addrp,
4466 4471 sata_pmult_gscr_t *sg)
4467 4472 {
4468 4473 ASSERT(MUTEX_HELD(
4469 4474 &ahci_ctlp->ahcictl_ports[addrp->aa_port]->ahciport_mutex));
4470 4475
4471 4476 READ_PMULT(addrp, SATA_PMULT_GSCR0, &sg->gscr0, err);
4472 4477 READ_PMULT(addrp, SATA_PMULT_GSCR1, &sg->gscr1, err);
4473 4478 READ_PMULT(addrp, SATA_PMULT_GSCR2, &sg->gscr2, err);
4474 4479 READ_PMULT(addrp, SATA_PMULT_GSCR64, &sg->gscr64, err);
4475 4480
4476 4481 return (AHCI_SUCCESS);
4477 4482
4478 4483 err: /* R/W PMULT error */
4479 4484 return (AHCI_FAILURE);
4480 4485 }
4481 4486
4482 4487 static int
4483 4488 ahci_update_pmult_pscr(ahci_ctl_t *ahci_ctlp, ahci_addr_t *addrp,
4484 4489 sata_device_t *sd)
4485 4490 {
4486 4491 ASSERT(AHCI_ADDR_IS_PMPORT(addrp));
4487 4492 ASSERT(MUTEX_HELD(
4488 4493 &ahci_ctlp->ahcictl_ports[addrp->aa_port]->ahciport_mutex));
4489 4494
4490 4495 READ_PMULT(addrp, SATA_PMULT_REG_SSTS, &sd->satadev_scr.sstatus, err);
4491 4496 READ_PMULT(addrp, SATA_PMULT_REG_SERR, &sd->satadev_scr.serror, err);
4492 4497 READ_PMULT(addrp, SATA_PMULT_REG_SCTL, &sd->satadev_scr.scontrol, err);
4493 4498 READ_PMULT(addrp, SATA_PMULT_REG_SACT, &sd->satadev_scr.sactive, err);
4494 4499
4495 4500 return (AHCI_SUCCESS);
4496 4501
4497 4502 err: /* R/W PMULT error */
4498 4503 return (AHCI_FAILURE);
4499 4504 }
4500 4505
4501 4506 /*
4502 4507 * ahci_initialize_pmult()
4503 4508 *
4504 4509 * Initialize a port multiplier, including
4505 4510 * 1. Enable FEATURES register at port multiplier. (SATA Chp.16)
4506 4511 * 2. Redefine MASK register. (SATA Chap 16.?)
4507 4512 */
4508 4513 static int
4509 4514 ahci_initialize_pmult(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp,
4510 4515 ahci_addr_t *addrp, sata_device_t *sd)
4511 4516 {
4512 4517 sata_pmult_gscr_t sg;
4513 4518 uint32_t gscr64;
4514 4519 uint8_t port = addrp->aa_port;
4515 4520
4516 4521 ASSERT(MUTEX_HELD(&ahci_portp->ahciport_mutex));
4517 4522
4518 4523 AHCIDBG(AHCIDBG_INFO|AHCIDBG_PMULT, ahci_ctlp,
4519 4524 "[Initialize] Port-multiplier at port %d.", port);
4520 4525
4521 4526 /*
4522 4527 * Enable features of port multiplier. Currently only
4523 4528 * Asynchronous Notification is enabled.
4524 4529 */
4525 4530 /* Check gscr64 for supported features. */
4526 4531 READ_PMULT(addrp, SATA_PMULT_GSCR64, &gscr64, err);
4527 4532
4528 4533 if (gscr64 & SATA_PMULT_CAP_SNOTIF) {
4529 4534 AHCIDBG(AHCIDBG_INFO|AHCIDBG_PMULT, ahci_ctlp,
4530 4535 "port %d: Port Multiplier supports "
4531 4536 "Asynchronous Notification.", port);
4532 4537
4533 4538 /* Write to gscr96 to enabled features */
4534 4539 WRITE_PMULT(addrp, SATA_PMULT_GSCR96,
4535 4540 SATA_PMULT_CAP_SNOTIF, err);
4536 4541
4537 4542 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
4538 4543 (uint32_t *)AHCI_PORT_PxSNTF(ahci_ctlp, port),
4539 4544 AHCI_SNOTIF_CLEAR_ALL);
4540 4545 AHCIDBG(AHCIDBG_INFO|AHCIDBG_PMULT, ahci_ctlp,
4541 4546 "port %d: PMult PxSNTF cleared.", port);
4542 4547
4543 4548 }
4544 4549
4545 4550 /*
4546 4551 * Now we need to update gscr33 register to enable hot-plug interrupt
4547 4552 * for sub devices behind port multiplier.
4548 4553 */
4549 4554 WRITE_PMULT(addrp, SATA_PMULT_GSCR33, (0x1ffff), err);
4550 4555 AHCIDBG(AHCIDBG_INFO|AHCIDBG_PMULT, ahci_ctlp,
4551 4556 "port %d: gscr33 mask set to %x.", port, (0x1ffff));
4552 4557
4553 4558 /*
4554 4559 * Fetch the number of device ports of the port multiplier
4555 4560 */
4556 4561 if (ahci_update_pmult_gscr(ahci_ctlp, addrp, &sg) != AHCI_SUCCESS)
4557 4562 return (AHCI_FAILURE);
4558 4563
4559 4564 /* Register the port multiplier to SATA Framework. */
4560 4565 mutex_exit(&ahci_portp->ahciport_mutex);
4561 4566 sata_register_pmult(ahci_ctlp->ahcictl_dip, sd, &sg);
4562 4567 mutex_enter(&ahci_portp->ahciport_mutex);
4563 4568
4564 4569 ahci_portp->ahciport_pmult_info->ahcipmi_num_dev_ports =
4565 4570 sd->satadev_add_info & SATA_PMULT_PORTNUM_MASK;
4566 4571
4567 4572 AHCIDBG(AHCIDBG_INFO|AHCIDBG_PMULT, ahci_ctlp,
4568 4573 "port %d: pmult sub-port number updated to %x.", port,
4569 4574 ahci_portp->ahciport_pmult_info->ahcipmi_num_dev_ports);
4570 4575
4571 4576 /* Till now port-mult is successfully initialized */
4572 4577 ahci_portp->ahciport_port_state |= SATA_DSTATE_PMULT_INIT;
4573 4578 return (AHCI_SUCCESS);
4574 4579
4575 4580 err: /* R/W PMULT error */
4576 4581 return (AHCI_FAILURE);
4577 4582 }
4578 4583
4579 4584 /*
4580 4585 * Initialize a port multiplier port. According to spec, firstly we need
4581 4586 * issue a COMRESET, then a software reset to get its signature.
4582 4587 *
4583 4588 * NOTE: This function should only be called in ahci_probe_pmport()
4584 4589 */
4585 4590 static int
4586 4591 ahci_initialize_pmport(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp,
4587 4592 ahci_addr_t *addrp)
4588 4593 {
4589 4594 uint32_t finished_tags = 0, reset_tags = 0, slot_status = 0;
4590 4595 uint8_t port = addrp->aa_port;
4591 4596 uint8_t pmport = addrp->aa_pmport;
4592 4597 int ret = AHCI_FAILURE;
4593 4598
4594 4599 ASSERT(MUTEX_HELD(&ahci_portp->ahciport_mutex));
4595 4600 ASSERT(AHCI_ADDR_IS_PMPORT(addrp));
4596 4601
4597 4602 AHCIDBG(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp,
4598 4603 "ahci_initialize_pmport: port %d:%d", port, pmport);
4599 4604
4600 4605 /* Check HBA port state */
4601 4606 if (ahci_portp->ahciport_port_state & SATA_PSTATE_FAILED) {
4602 4607 AHCIDBG(AHCIDBG_INIT|AHCIDBG_ERRS, ahci_ctlp,
4603 4608 "ahci_initialize_pmport:"
4604 4609 "port %d:%d Port Multiplier is failed.",
4605 4610 port, pmport);
4606 4611 return (AHCI_FAILURE);
4607 4612 }
4608 4613
4609 4614 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_HOTPLUG) {
4610 4615 return (AHCI_FAILURE);
4611 4616 }
4612 4617 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_HOTPLUG;
4613 4618
4614 4619 /* Checking for outstanding commands */
4615 4620 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) {
4616 4621 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
4617 4622 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port));
4618 4623 reset_tags = slot_status & AHCI_SLOT_MASK(ahci_ctlp);
4619 4624 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) {
4620 4625 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
4621 4626 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port));
4622 4627 reset_tags = slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp);
4623 4628 }
4624 4629
4625 4630 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING;
4626 4631 ahci_portp->ahciport_mop_in_progress++;
4627 4632
4628 4633 /* Clear status */
4629 4634 AHCIPORT_SET_STATE(ahci_portp, addrp, SATA_STATE_UNKNOWN);
4630 4635
4631 4636 /* Firstly assume an unknown device */
4632 4637 AHCIPORT_SET_DEV_TYPE(ahci_portp, addrp, SATA_DTYPE_UNKNOWN);
4633 4638
4634 4639 ahci_disable_port_intrs(ahci_ctlp, port);
4635 4640
4636 4641 /* port reset is necessary for port multiplier port */
4637 4642 if (ahci_pmport_reset(ahci_ctlp, ahci_portp, addrp) != AHCI_SUCCESS) {
4638 4643 AHCIDBG(AHCIDBG_INIT|AHCIDBG_ERRS, ahci_ctlp,
4639 4644 "ahci_initialize_pmport:"
4640 4645 "port reset failed at port %d:%d",
4641 4646 port, pmport);
4642 4647 goto out;
4643 4648 }
4644 4649
4645 4650 /* Is port failed? */
4646 4651 if (AHCIPORT_GET_STATE(ahci_portp, addrp) &
4647 4652 SATA_PSTATE_FAILED) {
4648 4653 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
4649 4654 "ahci_initialize_pmport: port %d:%d failed. "
4650 4655 "state = 0x%x", port, pmport,
4651 4656 ahci_portp->ahciport_port_state);
4652 4657 goto out;
4653 4658 }
4654 4659
4655 4660 /* Is there any device attached? */
4656 4661 if (AHCIPORT_GET_DEV_TYPE(ahci_portp, addrp)
4657 4662 == SATA_DTYPE_NONE) {
4658 4663 /* Do not waste time on an empty port */
4659 4664 AHCIDBG(AHCIDBG_INFO, ahci_ctlp,
4660 4665 "ahci_initialize_pmport: No device is found "
4661 4666 "at port %d:%d", port, pmport);
4662 4667 ret = AHCI_SUCCESS;
4663 4668 goto out;
4664 4669 }
4665 4670
4666 4671 AHCIPORT_SET_STATE(ahci_portp, addrp, SATA_STATE_READY);
4667 4672 AHCIDBG(AHCIDBG_INIT, ahci_ctlp,
4668 4673 "port %d:%d is ready now.", port, pmport);
4669 4674
4670 4675 /*
4671 4676 * Till now we can assure a device attached to that HBA port and work
4672 4677 * correctly. Now try to get the device signature. This is an optional
4673 4678 * step. If failed, unknown device is assumed, then SATA module will
4674 4679 * continue to use IDENTIFY DEVICE to get the information of the
4675 4680 * device.
4676 4681 */
4677 4682 ahci_find_dev_signature(ahci_ctlp, ahci_portp, addrp);
4678 4683
4679 4684 ret = AHCI_SUCCESS;
4680 4685
4681 4686 out:
4682 4687 /* Next try to mop the pending commands */
4683 4688 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp))
4684 4689 finished_tags = ahci_portp->ahciport_pending_tags &
4685 4690 ~slot_status & AHCI_SLOT_MASK(ahci_ctlp);
4686 4691 else if (NCQ_CMD_IN_PROGRESS(ahci_portp))
4687 4692 finished_tags = ahci_portp->ahciport_pending_ncq_tags &
4688 4693 ~slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp);
4689 4694 reset_tags &= ~finished_tags;
4690 4695
4691 4696 ahci_mop_commands(ahci_ctlp,
4692 4697 ahci_portp,
4693 4698 slot_status,
4694 4699 0, /* failed tags */
4695 4700 0, /* timeout tags */
4696 4701 0, /* aborted tags */
4697 4702 reset_tags); /* reset tags */
4698 4703
4699 4704 /* Clear PxSNTF register if supported. */
4700 4705 if (ahci_ctlp->ahcictl_cap & AHCI_CAP_SNTF) {
4701 4706 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
4702 4707 (uint32_t *)AHCI_PORT_PxSNTF(ahci_ctlp, port),
4703 4708 AHCI_SNOTIF_CLEAR_ALL);
4704 4709 }
4705 4710
4706 4711 ahci_portp->ahciport_flags &= ~AHCI_PORT_FLAG_HOTPLUG;
4707 4712 ahci_enable_port_intrs(ahci_ctlp, port);
4708 4713 return (ret);
4709 4714 }
4710 4715
4711 4716 /*
4712 4717 * ahci_probe_pmult()
4713 4718 *
4714 4719 * This function will be called to probe a port multiplier, which will
4715 4720 * handle hotplug events on port multiplier ports.
4716 4721 *
4717 4722 * NOTE: Only called from ahci_tran_probe_port()
4718 4723 */
4719 4724 static int
4720 4725 ahci_probe_pmult(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp,
4721 4726 ahci_addr_t *addrp)
4722 4727 {
4723 4728 sata_device_t sdevice;
4724 4729 ahci_addr_t pmport_addr;
4725 4730 uint32_t gscr32, port_hotplug_tags;
4726 4731 uint32_t pmport_sstatus;
4727 4732 int dev_exists_now = 0, dev_existed_previously = 0;
4728 4733 uint8_t port = addrp->aa_port;
4729 4734 int npmport;
4730 4735
4731 4736 ASSERT(MUTEX_HELD(&ahci_portp->ahciport_mutex));
4732 4737
4733 4738 /* The bits in GSCR32 refers to the pmport that has a hot-plug event. */
4734 4739 READ_PMULT(addrp, SATA_PMULT_GSCR32, &gscr32, err);
4735 4740 port_hotplug_tags = gscr32 & AHCI_PMPORT_MASK(ahci_portp);
4736 4741
4737 4742 do {
4738 4743 npmport = ddi_ffs(port_hotplug_tags) - 1;
4739 4744 if (npmport == -1)
4740 4745 /* no pending hot plug events. */
4741 4746 return (AHCI_SUCCESS);
4742 4747
4743 4748 AHCIDBG(AHCIDBG_EVENT|AHCIDBG_PMULT, ahci_ctlp,
4744 4749 "hot-plug event at port %d:%d", port, npmport);
4745 4750
4746 4751 AHCI_ADDR_SET_PMPORT(&pmport_addr, port, (uint8_t)npmport);
4747 4752
4748 4753 /* Check previous device at that port */
4749 4754 if (AHCIPORT_GET_DEV_TYPE(ahci_portp, &pmport_addr)
4750 4755 != SATA_DTYPE_NONE)
4751 4756 dev_existed_previously = 1;
4752 4757
4753 4758 /* PxSStatus tells the presence of device. */
4754 4759 READ_PMULT(&pmport_addr, SATA_PMULT_REG_SSTS,
4755 4760 &pmport_sstatus, err);
4756 4761
4757 4762 if (SSTATUS_GET_DET(pmport_sstatus) ==
4758 4763 SSTATUS_DET_DEVPRE_PHYCOM)
4759 4764 dev_exists_now = 1;
4760 4765
4761 4766 /*
4762 4767 * Clear PxSERR is critical. The transition from 0 to 1 will
4763 4768 * emit a FIS which generates an asynchronous notification
4764 4769 * event at controller. If we fail to clear the PxSERR, the
4765 4770 * Async Notif events will no longer be activated on this
4766 4771 * pmport.
4767 4772 */
4768 4773 WRITE_PMULT(&pmport_addr, SATA_PMULT_REG_SERR,
4769 4774 AHCI_SERROR_CLEAR_ALL, err);
4770 4775
4771 4776 bzero((void *)&sdevice, sizeof (sata_device_t));
4772 4777 sdevice.satadev_addr.cport = ahci_ctlp->
4773 4778 ahcictl_port_to_cport[port];
4774 4779 sdevice.satadev_addr.qual = SATA_ADDR_PMPORT;
4775 4780 sdevice.satadev_addr.pmport = (uint8_t)npmport;
4776 4781 sdevice.satadev_state = SATA_PSTATE_PWRON;
4777 4782
4778 4783 AHCIDBG(AHCIDBG_EVENT|AHCIDBG_PMULT, ahci_ctlp,
4779 4784 "[Existence] %d -> %d", dev_existed_previously,
4780 4785 dev_exists_now);
4781 4786
4782 4787 if (dev_exists_now) {
4783 4788 if (dev_existed_previously) {
4784 4789 /* Link (may) not change: Exist -> Exist * */
4785 4790 AHCIDBG(AHCIDBG_EVENT, ahci_ctlp,
4786 4791 "ahci_probe_pmult: port %d:%d "
4787 4792 "device link lost/established",
4788 4793 port, npmport);
4789 4794
4790 4795 mutex_exit(&ahci_portp->ahciport_mutex);
4791 4796 sata_hba_event_notify(
4792 4797 ahci_ctlp->ahcictl_sata_hba_tran->
4793 4798 sata_tran_hba_dip,
4794 4799 &sdevice,
4795 4800 SATA_EVNT_LINK_LOST|
4796 4801 SATA_EVNT_LINK_ESTABLISHED);
4797 4802 mutex_enter(&ahci_portp->ahciport_mutex);
4798 4803 } else {
4799 4804 /* Link change: None -> Exist */
4800 4805 AHCIDBG(AHCIDBG_EVENT|AHCIDBG_PMULT, ahci_ctlp,
4801 4806 "ahci_probe_pmult: port %d:%d "
4802 4807 "device link established", port, npmport);
4803 4808
4804 4809 /* Clear port state */
4805 4810 AHCIPORT_SET_STATE(ahci_portp, &pmport_addr,
4806 4811 SATA_STATE_UNKNOWN);
4807 4812 AHCIDBG(AHCIDBG_EVENT|AHCIDBG_PMULT, ahci_ctlp,
4808 4813 "ahci_probe_pmult: port %d "
4809 4814 "ahciport_port_state [Cleared].", port);
4810 4815
4811 4816 mutex_exit(&ahci_portp->ahciport_mutex);
4812 4817 sata_hba_event_notify(
4813 4818 ahci_ctlp->ahcictl_sata_hba_tran->
4814 4819 sata_tran_hba_dip,
4815 4820 &sdevice,
4816 4821 SATA_EVNT_LINK_ESTABLISHED);
4817 4822 mutex_enter(&ahci_portp->ahciport_mutex);
4818 4823 }
4819 4824 } else { /* No device exists now */
4820 4825 if (dev_existed_previously) {
4821 4826
4822 4827 /* Link change: Exist -> None */
4823 4828 AHCIDBG(AHCIDBG_EVENT|AHCIDBG_PMULT, ahci_ctlp,
4824 4829 "ahci_probe_pmult: port %d:%d "
4825 4830 "device link lost", port, npmport);
4826 4831
4827 4832 /* An existing device is lost. */
4828 4833 AHCIPORT_SET_STATE(ahci_portp, &pmport_addr,
4829 4834 SATA_STATE_UNKNOWN);
4830 4835 AHCIPORT_SET_DEV_TYPE(ahci_portp, &pmport_addr,
4831 4836 SATA_DTYPE_NONE);
4832 4837
4833 4838 mutex_exit(&ahci_portp->ahciport_mutex);
4834 4839 sata_hba_event_notify(
4835 4840 ahci_ctlp->ahcictl_sata_hba_tran->
4836 4841 sata_tran_hba_dip,
4837 4842 &sdevice,
4838 4843 SATA_EVNT_LINK_LOST);
4839 4844 mutex_enter(&ahci_portp->ahciport_mutex);
4840 4845 }
4841 4846 }
4842 4847
4843 4848 CLEAR_BIT(port_hotplug_tags, npmport);
4844 4849 } while (port_hotplug_tags != 0);
4845 4850
4846 4851 return (AHCI_SUCCESS);
4847 4852
4848 4853 err: /* R/W PMULT error */
4849 4854 return (AHCI_FAILURE);
4850 4855 }
4851 4856
4852 4857 /*
4853 4858 * Probe and initialize a port multiplier port.
4854 4859 * A port multiplier port could only be initilaizer here.
4855 4860 */
4856 4861 static int
4857 4862 ahci_probe_pmport(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp,
4858 4863 ahci_addr_t *addrp, sata_device_t *sd)
4859 4864 {
4860 4865 uint32_t port_state;
4861 4866 uint8_t port = addrp->aa_port;
4862 4867 ahci_addr_t addr_pmult;
4863 4868
4864 4869 ASSERT(MUTEX_HELD(&ahci_portp->ahciport_mutex));
4865 4870
4866 4871 /*
4867 4872 * Check the parent - port multiplier first.
4868 4873 */
4869 4874
4870 4875 /*
4871 4876 * Parent port multiplier might have been removed. This event will be
4872 4877 * ignored and failure.
4873 4878 */
4874 4879 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE ||
4875 4880 ahci_portp->ahciport_device_type != SATA_DTYPE_PMULT) {
4876 4881 AHCIDBG(AHCIDBG_ERRS|AHCIDBG_PMULT, ahci_ctlp,
4877 4882 "ahci_tran_probe_port: "
4878 4883 "parent device removed, ignore event.", NULL);
4879 4884
4880 4885 return (AHCI_FAILURE);
4881 4886 }
4882 4887
4883 4888 /* The port is ready? */
4884 4889 port_state = ahci_portp->ahciport_port_state;
4885 4890 if (!(port_state & SATA_STATE_READY)) {
4886 4891 AHCIDBG(AHCIDBG_ERRS|AHCIDBG_PMULT, ahci_ctlp,
4887 4892 "ahci_tran_probe_port: "
4888 4893 "parent port-mult is NOT ready.", NULL);
4889 4894
4890 4895 if (ahci_restart_port_wait_till_ready(ahci_ctlp,
4891 4896 ahci_portp, port, AHCI_PORT_RESET, NULL) !=
4892 4897 AHCI_SUCCESS) {
4893 4898 AHCIDBG(AHCIDBG_ERRS|AHCIDBG_PMULT, ahci_ctlp,
4894 4899 "ahci_tran_probe_port: "
4895 4900 "restart port-mult failed.", NULL);
4896 4901 return (AHCI_FAILURE);
4897 4902 }
4898 4903 }
4899 4904
4900 4905 /*
4901 4906 * If port-mult is restarted due to some reason, we need
4902 4907 * re-initialized the PMult.
4903 4908 */
4904 4909 if (!(port_state & SATA_DSTATE_PMULT_INIT)) {
4905 4910 /* Initialize registers on a port multiplier */
4906 4911 AHCI_ADDR_SET_PMULT(&addr_pmult, addrp->aa_port);
4907 4912 if (ahci_initialize_pmult(ahci_ctlp, ahci_portp,
4908 4913 &addr_pmult, sd) != AHCI_SUCCESS)
4909 4914 return (AHCI_FAILURE);
4910 4915 }
4911 4916
4912 4917 /*
4913 4918 * Then we check the port-mult port
4914 4919 */
4915 4920 /* Is this pmport initialized? */
4916 4921 port_state = AHCIPORT_GET_STATE(ahci_portp, addrp);
4917 4922 if (!(port_state & SATA_STATE_READY)) {
4918 4923
4919 4924 /* ahci_initialize_pmport() will set READY state */
4920 4925 if (ahci_initialize_pmport(ahci_ctlp,
4921 4926 ahci_portp, addrp) != AHCI_SUCCESS)
4922 4927 return (AHCI_FAILURE);
4923 4928 }
4924 4929
4925 4930 return (AHCI_SUCCESS);
4926 4931 }
4927 4932
4928 4933 /*
4929 4934 * AHCI device reset ...; a single device on one of the ports is reset,
4930 4935 * but the HBA and physical communication remain intact. This is the
4931 4936 * least intrusive.
4932 4937 *
4933 4938 * When issuing a software reset sequence, there should not be other
4934 4939 * commands in the command list, so we will first clear and then re-set
4935 4940 * PxCMD.ST to clear PxCI. And before issuing the software reset,
4936 4941 * the port must be idle and PxTFD.STS.BSY and PxTFD.STS.DRQ must be
4937 4942 * cleared unless command list override (PxCMD.CLO) is supported.
4938 4943 */
4939 4944 static int
4940 4945 ahci_software_reset(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp,
4941 4946 ahci_addr_t *addrp)
4942 4947 {
4943 4948 ahci_fis_h2d_register_t *h2d_register_fisp;
4944 4949 ahci_cmd_table_t *cmd_table;
4945 4950 ahci_cmd_header_t *cmd_header;
4946 4951 uint32_t port_cmd_status, port_cmd_issue, port_task_file;
4947 4952 int slot, loop_count;
4948 4953 uint8_t port = addrp->aa_port;
4949 4954 uint8_t pmport = addrp->aa_pmport;
4950 4955 int rval = AHCI_FAILURE;
4951 4956
4952 4957 ASSERT(MUTEX_HELD(&ahci_portp->ahciport_mutex));
4953 4958
4954 4959 AHCIDBG(AHCIDBG_ENTRY, ahci_ctlp,
4955 4960 "port %d:%d device software resetting (FIS)", port, pmport);
4956 4961
4957 4962 /* First clear PxCMD.ST (AHCI v1.2 10.4.1) */
4958 4963 if (ahci_put_port_into_notrunning_state(ahci_ctlp, ahci_portp,
4959 4964 port) != AHCI_SUCCESS) {
4960 4965 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
4961 4966 "ahci_software_reset: cannot stop HBA port %d.", port);
4962 4967 goto out;
4963 4968 }
4964 4969
4965 4970 /* Check PxTFD.STS.BSY and PxTFD.STS.DRQ */
4966 4971 port_task_file = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
4967 4972 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port));
4968 4973
4969 4974 if (port_task_file & AHCI_TFD_STS_BSY ||
4970 4975 port_task_file & AHCI_TFD_STS_DRQ) {
4971 4976 if (!(ahci_ctlp->ahcictl_cap & AHCI_CAP_SCLO)) {
4972 4977 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
4973 4978 "PxTFD.STS.BSY/DRQ is set (PxTFD=0x%x), "
4974 4979 "cannot issue a software reset.", port_task_file);
4975 4980 goto out;
4976 4981 }
4977 4982
4978 4983 /*
4979 4984 * If HBA Support CLO, as Command List Override (CAP.SCLO is
4980 4985 * set), PxCMD.CLO bit should be set before set PxCMD.ST, in
4981 4986 * order to clear PxTFD.STS.BSY and PxTFD.STS.DRQ.
4982 4987 */
4983 4988 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
4984 4989 "PxTFD.STS.BSY/DRQ is set, try SCLO.", NULL)
4985 4990
4986 4991 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
4987 4992 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port));
4988 4993 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
4989 4994 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port),
4990 4995 port_cmd_status|AHCI_CMD_STATUS_CLO);
4991 4996
4992 4997 /* Waiting till PxCMD.SCLO bit is cleared */
4993 4998 loop_count = 0;
4994 4999 do {
4995 5000 /* Wait for 10 millisec */
4996 5001 drv_usecwait(AHCI_10MS_USECS);
4997 5002
4998 5003 /* We are effectively timing out after 1 sec. */
4999 5004 if (loop_count++ > 100) {
5000 5005 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
5001 5006 "SCLO time out. port %d is busy.", port);
5002 5007 goto out;
5003 5008 }
5004 5009
5005 5010 port_cmd_status =
5006 5011 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
5007 5012 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port));
5008 5013 } while (port_cmd_status & AHCI_CMD_STATUS_CLO);
5009 5014
5010 5015 /* Re-check */
5011 5016 port_task_file = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
5012 5017 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port));
5013 5018 if (port_task_file & AHCI_TFD_STS_BSY ||
5014 5019 port_task_file & AHCI_TFD_STS_DRQ) {
5015 5020 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
5016 5021 "SCLO cannot clear PxTFD.STS.BSY/DRQ (PxTFD=0x%x)",
5017 5022 port_task_file);
5018 5023 goto out;
5019 5024 }
5020 5025 }
5021 5026
5022 5027 /* Then start port */
5023 5028 if (ahci_start_port(ahci_ctlp, ahci_portp, port)
5024 5029 != AHCI_SUCCESS) {
5025 5030 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
5026 5031 "ahci_software_reset: cannot start AHCI port %d.", port);
5027 5032 goto out;
5028 5033 }
5029 5034
5030 5035 /*
5031 5036 * When ahci_port.ahciport_mop_in_progress is set, A non-zero
5032 5037 * ahci_port.ahciport_pending_ncq_tags may fail
5033 5038 * ahci_claim_free_slot(). Actually according to spec, by clearing
5034 5039 * PxCMD.ST there is no command outstanding while executing software
5035 5040 * reseting. Hence we directly use slot 0 instead of
5036 5041 * ahci_claim_free_slot().
5037 5042 */
5038 5043 slot = 0;
5039 5044
5040 5045 /* Now send the first H2D Register FIS with SRST set to 1 */
5041 5046 cmd_table = ahci_portp->ahciport_cmd_tables[slot];
5042 5047 bzero((void *)cmd_table, ahci_cmd_table_size);
5043 5048
5044 5049 h2d_register_fisp =
5045 5050 &(cmd_table->ahcict_command_fis.ahcifc_fis.ahcifc_h2d_register);
5046 5051
5047 5052 SET_FIS_TYPE(h2d_register_fisp, AHCI_H2D_REGISTER_FIS_TYPE);
5048 5053 SET_FIS_PMP(h2d_register_fisp, pmport);
5049 5054 SET_FIS_DEVCTL(h2d_register_fisp, SATA_DEVCTL_SRST);
5050 5055
5051 5056 /* Set Command Header in Command List */
5052 5057 cmd_header = &ahci_portp->ahciport_cmd_list[slot];
5053 5058 BZERO_DESCR_INFO(cmd_header);
5054 5059 BZERO_PRD_BYTE_COUNT(cmd_header);
5055 5060 SET_COMMAND_FIS_LENGTH(cmd_header, 5);
5056 5061 SET_PORT_MULTI_PORT(cmd_header, pmport);
5057 5062
5058 5063 SET_CLEAR_BUSY_UPON_R_OK(cmd_header, 1);
5059 5064 SET_RESET(cmd_header, 1);
5060 5065 SET_WRITE(cmd_header, 1);
5061 5066
5062 5067 (void) ddi_dma_sync(ahci_portp->ahciport_cmd_tables_dma_handle[slot],
5063 5068 0,
5064 5069 ahci_cmd_table_size,
5065 5070 DDI_DMA_SYNC_FORDEV);
5066 5071
5067 5072 (void) ddi_dma_sync(ahci_portp->ahciport_cmd_list_dma_handle,
5068 5073 slot * sizeof (ahci_cmd_header_t),
5069 5074 sizeof (ahci_cmd_header_t),
5070 5075 DDI_DMA_SYNC_FORDEV);
5071 5076
5072 5077 /* Indicate to the HBA that a command is active. */
5073 5078 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
5074 5079 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port),
5075 5080 (0x1 << slot));
5076 5081
5077 5082 loop_count = 0;
5078 5083
5079 5084 /* Loop till the first command is finished */
5080 5085 do {
5081 5086 port_cmd_issue = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
5082 5087 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port));
5083 5088
5084 5089 /* We are effectively timing out after 1 sec. */
5085 5090 if (loop_count++ > AHCI_POLLRATE_PORT_SOFTRESET) {
5086 5091 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
5087 5092 "the first SRST FIS is timed out, "
5088 5093 "loop_count = %d", loop_count);
5089 5094 goto out;
5090 5095 }
5091 5096 /* Wait for 10 millisec */
5092 5097 drv_usecwait(AHCI_10MS_USECS);
5093 5098 } while (port_cmd_issue & AHCI_SLOT_MASK(ahci_ctlp) & (0x1 << slot));
5094 5099
5095 5100 AHCIDBG(AHCIDBG_POLL_LOOP, ahci_ctlp,
5096 5101 "ahci_software_reset: 1st loop count: %d, "
5097 5102 "port_cmd_issue = 0x%x, slot = 0x%x",
5098 5103 loop_count, port_cmd_issue, slot);
5099 5104
5100 5105 /* According to ATA spec, we need wait at least 5 microsecs here. */
5101 5106 drv_usecwait(AHCI_1MS_USECS);
5102 5107
5103 5108 /* Now send the second H2D Register FIS with SRST cleard to zero */
5104 5109 cmd_table = ahci_portp->ahciport_cmd_tables[slot];
5105 5110 bzero((void *)cmd_table, ahci_cmd_table_size);
5106 5111
5107 5112 h2d_register_fisp =
5108 5113 &(cmd_table->ahcict_command_fis.ahcifc_fis.ahcifc_h2d_register);
5109 5114
5110 5115 SET_FIS_TYPE(h2d_register_fisp, AHCI_H2D_REGISTER_FIS_TYPE);
5111 5116 SET_FIS_PMP(h2d_register_fisp, pmport);
5112 5117
5113 5118 /* Set Command Header in Command List */
5114 5119 cmd_header = &ahci_portp->ahciport_cmd_list[slot];
5115 5120 BZERO_DESCR_INFO(cmd_header);
5116 5121 BZERO_PRD_BYTE_COUNT(cmd_header);
5117 5122 SET_COMMAND_FIS_LENGTH(cmd_header, 5);
5118 5123 SET_PORT_MULTI_PORT(cmd_header, pmport);
5119 5124
5120 5125 SET_WRITE(cmd_header, 1);
5121 5126
5122 5127 (void) ddi_dma_sync(ahci_portp->ahciport_cmd_tables_dma_handle[slot],
5123 5128 0,
5124 5129 ahci_cmd_table_size,
5125 5130 DDI_DMA_SYNC_FORDEV);
5126 5131
5127 5132 (void) ddi_dma_sync(ahci_portp->ahciport_cmd_list_dma_handle,
5128 5133 slot * sizeof (ahci_cmd_header_t),
5129 5134 sizeof (ahci_cmd_header_t),
5130 5135 DDI_DMA_SYNC_FORDEV);
5131 5136
5132 5137 /* Indicate to the HBA that a command is active. */
5133 5138 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
5134 5139 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port),
5135 5140 (0x1 << slot));
5136 5141
5137 5142 loop_count = 0;
5138 5143
5139 5144 /* Loop till the second command is finished */
5140 5145 do {
5141 5146 port_cmd_issue = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
5142 5147 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port));
5143 5148
5144 5149 /* We are effectively timing out after 1 sec. */
5145 5150 if (loop_count++ > AHCI_POLLRATE_PORT_SOFTRESET) {
5146 5151 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
5147 5152 "the second SRST FIS is timed out, "
5148 5153 "loop_count = %d", loop_count);
5149 5154 goto out;
5150 5155 }
5151 5156
5152 5157 /* Wait for 10 millisec */
5153 5158 drv_usecwait(AHCI_10MS_USECS);
5154 5159 } while (port_cmd_issue & AHCI_SLOT_MASK(ahci_ctlp) & (0x1 << slot));
5155 5160
5156 5161 AHCIDBG(AHCIDBG_POLL_LOOP, ahci_ctlp,
5157 5162 "ahci_software_reset: 2nd loop count: %d, "
5158 5163 "port_cmd_issue = 0x%x, slot = 0x%x",
5159 5164 loop_count, port_cmd_issue, slot);
5160 5165
5161 5166 if ((ahci_check_ctl_handle(ahci_ctlp) != DDI_SUCCESS) ||
5162 5167 (ahci_check_port_handle(ahci_ctlp, port) != DDI_SUCCESS)) {
5163 5168 ddi_fm_service_impact(ahci_ctlp->ahcictl_dip,
5164 5169 DDI_SERVICE_UNAFFECTED);
5165 5170 goto out;
5166 5171 }
5167 5172
5168 5173 rval = AHCI_SUCCESS;
5169 5174 out:
5170 5175 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
5171 5176 "ahci_software_reset: %s at port %d:%d",
5172 5177 rval == AHCI_SUCCESS ? "succeed" : "failed",
5173 5178 port, pmport);
5174 5179
5175 5180 return (rval);
5176 5181 }
5177 5182
5178 5183 /*
5179 5184 * AHCI port reset ...; the physical communication between the HBA and device
5180 5185 * on a port are disabled. This is more intrusive.
5181 5186 *
5182 5187 * When an HBA or port reset occurs, Phy communication is going to
5183 5188 * be re-established with the device through a COMRESET followed by the
5184 5189 * normal out-of-band communication sequence defined in Serial ATA. At
5185 5190 * the end of reset, the device, if working properly, will send a D2H
5186 5191 * Register FIS, which contains the device signature. When the HBA receives
5187 5192 * this FIS, it updates PxTFD.STS and PxTFD.ERR register fields, and updates
5188 5193 * the PxSIG register with the signature.
5189 5194 *
5190 5195 * NOTE: It is expected both PxCMD.ST and PxCMD.CR are cleared before the
5191 5196 * function is called. If not, it is assumed the interface is in hung
5192 5197 * condition.
5193 5198 */
5194 5199 static int
5195 5200 ahci_port_reset(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp,
5196 5201 ahci_addr_t *addrp)
5197 5202 {
5198 5203 ahci_addr_t pmult_addr;
5199 5204 uint32_t port_cmd_status;
5200 5205 uint32_t port_scontrol, port_sstatus;
5201 5206 uint32_t port_task_file;
5202 5207 uint32_t port_state;
5203 5208 uint8_t port = addrp->aa_port;
5204 5209
5205 5210 int loop_count;
5206 5211 int instance = ddi_get_instance(ahci_ctlp->ahcictl_dip);
5207 5212
5208 5213 ASSERT(MUTEX_HELD(&ahci_portp->ahciport_mutex));
5209 5214
5210 5215 /* Target is a port multiplier port? */
5211 5216 if (AHCI_ADDR_IS_PMPORT(addrp))
5212 5217 return (ahci_pmport_reset(ahci_ctlp, ahci_portp, addrp));
5213 5218
5214 5219 /* Otherwise it must be an HBA port. */
5215 5220 ASSERT(AHCI_ADDR_IS_PORT(addrp));
5216 5221
5217 5222 AHCIDBG(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp,
5218 5223 "Port %d port resetting...", port);
5219 5224 ahci_portp->ahciport_port_state = 0;
5220 5225
5221 5226 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
5222 5227 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port));
5223 5228
5224 5229 /*
5225 5230 * According to the spec, SUD bit should be set here,
5226 5231 * but JMicron JMB363 doesn't follow it, so print
5227 5232 * a debug message.
5228 5233 */
5229 5234 if (!(port_cmd_status & AHCI_CMD_STATUS_SUD))
5230 5235 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
5231 5236 "ahci_port_reset: port %d SUD bit not set", port);
5232 5237
5233 5238 port_scontrol = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
5234 5239 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port));
5235 5240 SCONTROL_SET_DET(port_scontrol, SCONTROL_DET_COMRESET);
5236 5241
5237 5242 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
5238 5243 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port),
5239 5244 port_scontrol);
5240 5245
5241 5246 /* Enable PxCMD.FRE to read device */
5242 5247 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
5243 5248 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port),
5244 5249 port_cmd_status|AHCI_CMD_STATUS_FRE);
5245 5250
5246 5251 /*
5247 5252 * The port enters P:StartComm state, and the HBA tells the link layer
5248 5253 * to start communication, which involves sending COMRESET to the
5249 5254 * device. And the HBA resets PxTFD.STS to 7Fh.
5250 5255 *
5251 5256 * Give time for COMRESET to percolate, according to the AHCI
5252 5257 * spec, software shall wait at least 1 millisecond before
5253 5258 * clearing PxSCTL.DET
5254 5259 */
5255 5260 drv_usecwait(AHCI_1MS_USECS * 2);
5256 5261
5257 5262 /* Fetch the SCONTROL again and rewrite the DET part with 0 */
5258 5263 port_scontrol = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
5259 5264 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port));
5260 5265 SCONTROL_SET_DET(port_scontrol, SCONTROL_DET_NOACTION);
5261 5266 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
5262 5267 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port),
5263 5268 port_scontrol);
5264 5269
5265 5270 /*
5266 5271 * When a COMINIT is received from the device, then the port enters
5267 5272 * P:ComInit state. And HBA sets PxTFD.STS to FFh or 80h. HBA sets
5268 5273 * PxSSTS.DET to 1h to indicate a device is detected but communication
5269 5274 * is not yet established. HBA sets PxSERR.DIAG.X to '1' to indicate
5270 5275 * a COMINIT has been received.
5271 5276 */
5272 5277 /*
5273 5278 * The DET field is valid only if IPM field indicates
5274 5279 * that the interface is in active state.
5275 5280 */
5276 5281 loop_count = 0;
5277 5282 for (;;) {
5278 5283 port_sstatus = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
5279 5284 (uint32_t *)AHCI_PORT_PxSSTS(ahci_ctlp, port));
5280 5285
5281 5286 if (SSTATUS_GET_IPM(port_sstatus) != SSTATUS_IPM_ACTIVE) {
5282 5287 /*
5283 5288 * If the interface is not active, the DET field
5284 5289 * is considered not accurate. So we want to
5285 5290 * continue looping.
5286 5291 */
5287 5292 SSTATUS_SET_DET(port_sstatus, SSTATUS_DET_NODEV);
5288 5293 }
5289 5294
5290 5295 if (SSTATUS_GET_DET(port_sstatus) == SSTATUS_DET_DEVPRE_PHYCOM)
5291 5296 break;
5292 5297
5293 5298 if (loop_count++ > AHCI_POLLRATE_PORT_SSTATUS) {
5294 5299 /*
5295 5300 * We are effectively timing out after 0.1 sec.
5296 5301 */
5297 5302 break;
5298 5303 }
5299 5304
5300 5305 /* Wait for 10 millisec */
5301 5306 drv_usecwait(AHCI_10MS_USECS);
5302 5307 }
5303 5308
5304 5309 AHCIDBG(AHCIDBG_INIT|AHCIDBG_POLL_LOOP, ahci_ctlp,
5305 5310 "ahci_port_reset: 1st loop count: %d, "
5306 5311 "port_sstatus = 0x%x port %d",
5307 5312 loop_count, port_sstatus, port);
5308 5313
5309 5314 if (SSTATUS_GET_DET(port_sstatus) != SSTATUS_DET_DEVPRE_PHYCOM) {
5310 5315 /*
5311 5316 * Either the port is not active or there
5312 5317 * is no device present.
5313 5318 */
5314 5319 AHCIPORT_SET_DEV_TYPE(ahci_portp, addrp, SATA_DTYPE_NONE);
5315 5320 return (AHCI_SUCCESS);
5316 5321 }
5317 5322
5318 5323 /* Clear port serror register for the port */
5319 5324 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
5320 5325 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port),
5321 5326 AHCI_SERROR_CLEAR_ALL);
5322 5327
5323 5328 /*
5324 5329 * Devices should return a FIS contains its signature to HBA after
5325 5330 * COMINIT signal. Check whether a D2H Register FIS is received by
5326 5331 * polling PxTFD.STS.
5327 5332 */
5328 5333 loop_count = 0;
5329 5334 for (;;) {
5330 5335 port_task_file =
5331 5336 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
5332 5337 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port));
5333 5338
5334 5339 if ((port_task_file & (AHCI_TFD_STS_BSY | AHCI_TFD_STS_DRQ |
5335 5340 AHCI_TFD_STS_ERR)) == 0)
5336 5341 break;
5337 5342
5338 5343 if (loop_count++ > AHCI_POLLRATE_PORT_TFD_ERROR) {
5339 5344 /*
5340 5345 * We are effectively timing out after 11 sec.
5341 5346 */
5342 5347 cmn_err(CE_WARN, "!ahci%d: ahci_port_reset port %d "
5343 5348 "the device hardware has been initialized and "
5344 5349 "the power-up diagnostics failed",
5345 5350 instance, port);
5346 5351
5347 5352 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp, "ahci_port_reset: "
5348 5353 "port %d: some or all of BSY, DRQ and ERR in "
5349 5354 "PxTFD.STS are not clear. We need another "
5350 5355 "software reset.", port);
5351 5356
5352 5357 /* Clear port serror register for the port */
5353 5358 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
5354 5359 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port),
5355 5360 AHCI_SERROR_CLEAR_ALL);
5356 5361
5357 5362 AHCI_ADDR_SET_PMULT(&pmult_addr, port);
5358 5363
5359 5364 /* Try another software reset. */
5360 5365 if (ahci_software_reset(ahci_ctlp, ahci_portp,
5361 5366 &pmult_addr) != AHCI_SUCCESS) {
5362 5367 AHCIPORT_SET_STATE(ahci_portp, addrp,
5363 5368 SATA_PSTATE_FAILED);
5364 5369 return (AHCI_FAILURE);
5365 5370 }
5366 5371 break;
5367 5372 }
5368 5373
5369 5374 /* Wait for 10 millisec */
5370 5375 drv_usecwait(AHCI_10MS_USECS);
5371 5376 }
5372 5377
5373 5378 AHCIDBG(AHCIDBG_INIT|AHCIDBG_POLL_LOOP, ahci_ctlp,
5374 5379 "ahci_port_reset: 2nd loop count: %d, "
5375 5380 "port_task_file = 0x%x port %d",
5376 5381 loop_count, port_task_file, port);
5377 5382
5378 5383 /* Clear port serror register for the port */
5379 5384 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
5380 5385 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port),
5381 5386 AHCI_SERROR_CLEAR_ALL);
5382 5387
5383 5388 /* Set port as ready */
5384 5389 port_state = AHCIPORT_GET_STATE(ahci_portp, addrp);
5385 5390 AHCIPORT_SET_STATE(ahci_portp, addrp, port_state|SATA_STATE_READY);
5386 5391
5387 5392 AHCIDBG(AHCIDBG_INFO|AHCIDBG_ERRS, ahci_ctlp,
5388 5393 "ahci_port_reset: succeed at port %d.", port);
5389 5394 return (AHCI_SUCCESS);
5390 5395 }
5391 5396
5392 5397 /*
5393 5398 * COMRESET on a port multiplier port.
5394 5399 *
5395 5400 * NOTE: Only called in ahci_port_reset()
5396 5401 */
5397 5402 static int
5398 5403 ahci_pmport_reset(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp,
5399 5404 ahci_addr_t *addrp)
5400 5405 {
5401 5406 uint32_t port_scontrol, port_sstatus, port_serror;
5402 5407 uint32_t port_cmd_status, port_intr_status;
5403 5408 uint32_t port_state;
5404 5409 uint8_t port = addrp->aa_port;
5405 5410 uint8_t pmport = addrp->aa_pmport;
5406 5411 int loop_count;
5407 5412 int instance = ddi_get_instance(ahci_ctlp->ahcictl_dip);
5408 5413
5409 5414 AHCIDBG(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp,
5410 5415 "port %d:%d: pmport resetting", port, pmport);
5411 5416
5412 5417 /* Initialize pmport state */
5413 5418 AHCIPORT_SET_STATE(ahci_portp, addrp, 0);
5414 5419
5415 5420 READ_PMULT(addrp, SATA_PMULT_REG_SCTL, &port_scontrol, err);
5416 5421 SCONTROL_SET_DET(port_scontrol, SCONTROL_DET_COMRESET);
5417 5422 WRITE_PMULT(addrp, SATA_PMULT_REG_SCTL, port_scontrol, err);
5418 5423
5419 5424 /* PxCMD.FRE should be set before. */
5420 5425 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
5421 5426 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port));
5422 5427 ASSERT(port_cmd_status & AHCI_CMD_STATUS_FRE);
5423 5428 if (!(port_cmd_status & AHCI_CMD_STATUS_FRE))
5424 5429 return (AHCI_FAILURE);
5425 5430
5426 5431 /*
5427 5432 * Give time for COMRESET to percolate, according to the AHCI
5428 5433 * spec, software shall wait at least 1 millisecond before
5429 5434 * clearing PxSCTL.DET
5430 5435 */
5431 5436 drv_usecwait(AHCI_1MS_USECS*2);
5432 5437
5433 5438 /*
5434 5439 * Fetch the SCONTROL again and rewrite the DET part with 0
5435 5440 * This will generate an Asychronous Notification events.
5436 5441 */
5437 5442 READ_PMULT(addrp, SATA_PMULT_REG_SCTL, &port_scontrol, err);
5438 5443 SCONTROL_SET_DET(port_scontrol, SCONTROL_DET_NOACTION);
5439 5444 WRITE_PMULT(addrp, SATA_PMULT_REG_SCTL, port_scontrol, err);
5440 5445
5441 5446 /*
5442 5447 * The port enters P:StartComm state, and HBA tells link layer to
5443 5448 * start communication, which involves sending COMRESET to device.
5444 5449 * And the HBA resets PxTFD.STS to 7Fh.
5445 5450 *
5446 5451 * When a COMINIT is received from the device, then the port enters
5447 5452 * P:ComInit state. And HBA sets PxTFD.STS to FFh or 80h. HBA sets
5448 5453 * PxSSTS.DET to 1h to indicate a device is detected but communication
5449 5454 * is not yet established. HBA sets PxSERR.DIAG.X to '1' to indicate
5450 5455 * a COMINIT has been received.
5451 5456 */
5452 5457 /*
5453 5458 * The DET field is valid only if IPM field indicates
5454 5459 * that the interface is in active state.
5455 5460 */
5456 5461 loop_count = 0;
5457 5462 do {
5458 5463 READ_PMULT(addrp, SATA_PMULT_REG_SSTS, &port_sstatus, err);
5459 5464
5460 5465 if (SSTATUS_GET_IPM(port_sstatus) != SSTATUS_IPM_ACTIVE) {
5461 5466 /*
5462 5467 * If the interface is not active, the DET field
5463 5468 * is considered not accurate. So we want to
5464 5469 * continue looping.
5465 5470 */
5466 5471 SSTATUS_SET_DET(port_sstatus, SSTATUS_DET_NODEV);
5467 5472 }
5468 5473
5469 5474 if (loop_count++ > AHCI_POLLRATE_PORT_SSTATUS) {
5470 5475 /*
5471 5476 * We are effectively timing out after 0.1 sec.
5472 5477 */
5473 5478 break;
5474 5479 }
5475 5480
5476 5481 /* Wait for 10 millisec */
5477 5482 drv_usecwait(AHCI_10MS_USECS);
5478 5483
5479 5484 } while (SSTATUS_GET_DET(port_sstatus) != SSTATUS_DET_DEVPRE_PHYCOM);
5480 5485
5481 5486 AHCIDBG(AHCIDBG_POLL_LOOP, ahci_ctlp,
5482 5487 "ahci_pmport_reset: 1st loop count: %d, "
5483 5488 "port_sstatus = 0x%x port %d:%d",
5484 5489 loop_count, port_sstatus, port, pmport);
5485 5490
5486 5491 if ((SSTATUS_GET_IPM(port_sstatus) != SSTATUS_IPM_ACTIVE) ||
5487 5492 (SSTATUS_GET_DET(port_sstatus) != SSTATUS_DET_DEVPRE_PHYCOM)) {
5488 5493 /*
5489 5494 * Either the port is not active or there
5490 5495 * is no device present.
5491 5496 */
5492 5497 AHCIDBG(AHCIDBG_INIT|AHCIDBG_INFO, ahci_ctlp,
5493 5498 "ahci_pmport_reset: "
5494 5499 "no device attached to port %d:%d",
5495 5500 port, pmport);
5496 5501 AHCIPORT_SET_DEV_TYPE(ahci_portp, addrp, SATA_DTYPE_NONE);
5497 5502 return (AHCI_SUCCESS);
5498 5503 }
5499 5504
5500 5505 /* Now we can make sure there is a device connected to the port */
5501 5506 /* COMINIT signal is supposed to be received (PxSERR.DIAG.X = '1') */
5502 5507 READ_PMULT(addrp, SATA_PMULT_REG_SERR, &port_serror, err);
5503 5508
5504 5509 if (!(port_serror & (1 << 26))) {
5505 5510 cmn_err(CE_WARN, "!ahci%d: ahci_pmport_reset: "
5506 5511 "COMINIT signal from the device not received port %d:%d",
5507 5512 instance, port, pmport);
5508 5513
5509 5514 AHCIPORT_SET_STATE(ahci_portp, addrp, SATA_PSTATE_FAILED);
5510 5515 return (AHCI_FAILURE);
5511 5516 }
5512 5517
5513 5518 /*
5514 5519 * After clear PxSERR register, we will receive a D2H FIS.
5515 5520 * Normally this FIS will cause a IPMS error according to AHCI spec
5516 5521 * v1.2 because there is no command outstanding for it. So we need
5517 5522 * to ignore this error.
5518 5523 */
5519 5524 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_IGNORE_IPMS;
5520 5525 WRITE_PMULT(addrp, SATA_PMULT_REG_SERR, AHCI_SERROR_CLEAR_ALL, err);
5521 5526
5522 5527 /* Now we need to check the D2H FIS by checking IPMS error. */
5523 5528 loop_count = 0;
5524 5529 do {
5525 5530 port_intr_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
5526 5531 (uint32_t *)AHCI_PORT_PxIS(ahci_ctlp, port));
5527 5532
5528 5533 if (loop_count++ > AHCI_POLLRATE_PORT_TFD_ERROR) {
5529 5534 /*
5530 5535 * No D2H FIS received. This is possible according
5531 5536 * to SATA 2.6 spec.
5532 5537 */
5533 5538 cmn_err(CE_WARN, "ahci_port_reset: port %d:%d "
5534 5539 "PxIS.IPMS is not set, we need another "
5535 5540 "software reset.", port, pmport);
5536 5541
5537 5542 break;
5538 5543 }
5539 5544
5540 5545 /* Wait for 10 millisec */
5541 5546 mutex_exit(&ahci_portp->ahciport_mutex);
5542 5547 delay(AHCI_10MS_TICKS);
5543 5548 mutex_enter(&ahci_portp->ahciport_mutex);
5544 5549
5545 5550 } while (!(port_intr_status & AHCI_INTR_STATUS_IPMS));
5546 5551
5547 5552 AHCIDBG(AHCIDBG_POLL_LOOP, ahci_ctlp,
5548 5553 "ahci_pmport_reset: 2st loop count: %d, "
5549 5554 "port_sstatus = 0x%x port %d:%d",
5550 5555 loop_count, port_sstatus, port, pmport);
5551 5556
5552 5557 /* Clear IPMS */
5553 5558 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
5554 5559 (uint32_t *)AHCI_PORT_PxIS(ahci_ctlp, port),
5555 5560 AHCI_INTR_STATUS_IPMS);
5556 5561 ahci_portp->ahciport_flags &= ~AHCI_PORT_FLAG_IGNORE_IPMS;
5557 5562
5558 5563 /* This pmport is now ready for ahci_tran_start() */
5559 5564 port_state = AHCIPORT_GET_STATE(ahci_portp, addrp);
5560 5565 AHCIPORT_SET_STATE(ahci_portp, addrp, port_state|SATA_STATE_READY);
5561 5566
5562 5567 AHCIDBG(AHCIDBG_INFO|AHCIDBG_ERRS, ahci_ctlp,
5563 5568 "ahci_pmport_reset: succeed at port %d:%d", port, pmport);
5564 5569 return (AHCI_SUCCESS);
5565 5570
5566 5571 err: /* R/W PMULT error */
5567 5572 /* IPMS flags might be set before. */
5568 5573 ahci_portp->ahciport_flags &= ~AHCI_PORT_FLAG_IGNORE_IPMS;
5569 5574 AHCIDBG(AHCIDBG_INFO|AHCIDBG_ERRS, ahci_ctlp,
5570 5575 "ahci_pmport_reset: failed at port %d:%d", port, pmport);
5571 5576
5572 5577 return (AHCI_FAILURE);
5573 5578 }
5574 5579
5575 5580 /*
5576 5581 * AHCI HBA reset ...; the entire HBA is reset, and all ports are disabled.
5577 5582 * This is the most intrusive.
5578 5583 *
5579 5584 * When an HBA reset occurs, Phy communication will be re-established with
5580 5585 * the device through a COMRESET followed by the normal out-of-band
5581 5586 * communication sequence defined in Serial ATA. At the end of reset, the
5582 5587 * device, if working properly, will send a D2H Register FIS, which contains
5583 5588 * the device signature. When the HBA receives this FIS, it updates PxTFD.STS
5584 5589 * and PxTFD.ERR register fields, and updates the PxSIG register with the
5585 5590 * signature.
5586 5591 *
5587 5592 * Remember to set GHC.AE to 1 before calling ahci_hba_reset.
5588 5593 */
5589 5594 static int
5590 5595 ahci_hba_reset(ahci_ctl_t *ahci_ctlp)
5591 5596 {
5592 5597 ahci_port_t *ahci_portp;
5593 5598 uint32_t ghc_control;
5594 5599 uint8_t port;
5595 5600 int loop_count;
5596 5601 int rval = AHCI_SUCCESS;
5597 5602
5598 5603 AHCIDBG(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, "HBA resetting",
5599 5604 NULL);
5600 5605
5601 5606 mutex_enter(&ahci_ctlp->ahcictl_mutex);
5602 5607
5603 5608 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
5604 5609 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp));
5605 5610
5606 5611 /* Setting GHC.HR to 1, remember GHC.AE is already set to 1 before */
5607 5612 ghc_control |= AHCI_HBA_GHC_HR;
5608 5613 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
5609 5614 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp), ghc_control);
5610 5615
5611 5616 /*
5612 5617 * Wait until HBA Reset complete or timeout
5613 5618 */
5614 5619 loop_count = 0;
5615 5620 do {
5616 5621 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
5617 5622 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp));
5618 5623
5619 5624 if (loop_count++ > AHCI_POLLRATE_HBA_RESET) {
5620 5625 AHCIDBG(AHCIDBG_INIT, ahci_ctlp,
5621 5626 "ahci hba reset is timing out, "
5622 5627 "ghc_control = 0x%x", ghc_control);
5623 5628 /* We are effectively timing out after 1 sec. */
5624 5629 break;
5625 5630 }
5626 5631
5627 5632 /* Wait for 10 millisec */
5628 5633 drv_usecwait(AHCI_10MS_USECS);
5629 5634 } while (ghc_control & AHCI_HBA_GHC_HR);
5630 5635
5631 5636 AHCIDBG(AHCIDBG_POLL_LOOP, ahci_ctlp,
5632 5637 "ahci_hba_reset: 1st loop count: %d, "
5633 5638 "ghc_control = 0x%x", loop_count, ghc_control);
5634 5639
5635 5640 if (ghc_control & AHCI_HBA_GHC_HR) {
5636 5641 /* The hba is not reset for some reasons */
5637 5642 AHCIDBG(AHCIDBG_INIT, ahci_ctlp,
5638 5643 "hba reset failed: HBA in a hung or locked state", NULL);
5639 5644 mutex_exit(&ahci_ctlp->ahcictl_mutex);
5640 5645 return (AHCI_FAILURE);
5641 5646 }
5642 5647
5643 5648 /*
5644 5649 * HBA reset will clear (AHCI Spec v1.2 10.4.3) GHC.IE / GHC.AE
5645 5650 */
5646 5651 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
5647 5652 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp));
5648 5653 ghc_control |= (AHCI_HBA_GHC_AE | AHCI_HBA_GHC_IE);
5649 5654 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
5650 5655 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp), ghc_control);
5651 5656
5652 5657 mutex_exit(&ahci_ctlp->ahcictl_mutex);
5653 5658
5654 5659 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) {
5655 5660 /* Only check implemented ports */
5656 5661 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) {
5657 5662 continue;
5658 5663 }
5659 5664
5660 5665 ahci_portp = ahci_ctlp->ahcictl_ports[port];
5661 5666 mutex_enter(&ahci_portp->ahciport_mutex);
5662 5667
5663 5668 /* Make sure the drive is spun-up */
5664 5669 ahci_staggered_spin_up(ahci_ctlp, port);
5665 5670
5666 5671 if (ahci_restart_port_wait_till_ready(ahci_ctlp, ahci_portp,
5667 5672 port, AHCI_PORT_RESET|AHCI_RESET_NO_EVENTS_UP, NULL) !=
5668 5673 AHCI_SUCCESS) {
5669 5674 rval = AHCI_FAILURE;
5670 5675 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
5671 5676 "ahci_hba_reset: port %d failed", port);
5672 5677 /*
5673 5678 * Set the port state to SATA_PSTATE_FAILED if
5674 5679 * failed to initialize it.
5675 5680 */
5676 5681 ahci_portp->ahciport_port_state = SATA_PSTATE_FAILED;
5677 5682 }
5678 5683
5679 5684 mutex_exit(&ahci_portp->ahciport_mutex);
5680 5685 }
5681 5686
5682 5687 return (rval);
5683 5688 }
5684 5689
5685 5690 /*
5686 5691 * This routine is only called from AHCI_ATTACH or phyrdy change
5687 5692 * case. It first calls software reset, then stop the port and try to
5688 5693 * read PxSIG register to find the type of device attached to the port.
5689 5694 *
5690 5695 * The caller should make sure a valid device exists on specified port and
5691 5696 * physical communication has been established so that the signature could
5692 5697 * be retrieved by software reset.
5693 5698 *
5694 5699 * NOTE: The port interrupts should be disabled before the function is called.
5695 5700 */
5696 5701 static void
5697 5702 ahci_find_dev_signature(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp,
5698 5703 ahci_addr_t *addrp)
5699 5704 {
5700 5705 ahci_addr_t dev_addr;
5701 5706 uint32_t signature;
5702 5707 uint8_t port = addrp->aa_port;
5703 5708 uint8_t pmport = addrp->aa_pmport;
5704 5709 int rval;
5705 5710
5706 5711 ASSERT(MUTEX_HELD(&ahci_portp->ahciport_mutex));
5707 5712 ASSERT(AHCI_ADDR_IS_VALID(addrp));
5708 5713
5709 5714 /*
5710 5715 * If the HBA doesn't support port multiplier, then the driver
5711 5716 * doesn't need to bother to check port multiplier device.
5712 5717 *
5713 5718 * The second port of ICH7 on ASUS P5W DH deluxe motherboard is
5714 5719 * connected to Silicon Image 4723, to which the two sata drives
5715 5720 * attached can be set with RAID1, RAID0 or Spanning mode.
5716 5721 *
5717 5722 * We found software reset will get failure if port multiplier address
5718 5723 * 0xf is used by software reset, so just ignore the check since
5719 5724 * ICH7 doesn't support port multiplier device at all.
5720 5725 */
5721 5726 if (AHCI_ADDR_IS_PORT(addrp) &&
5722 5727 (ahci_ctlp->ahcictl_cap & AHCI_CAP_PMULT_CBSS)) {
5723 5728 AHCIDBG(AHCIDBG_ENTRY, ahci_ctlp,
5724 5729 "ahci_find_dev_signature enter: port %d", port);
5725 5730
5726 5731 /*
5727 5732 * NOTE: when the ahci address is a HBA port, we do not know
5728 5733 * it is a device or a port multiplier that attached. we need
5729 5734 * try a software reset at port multiplier address (0xf
5730 5735 * pmport)
5731 5736 */
5732 5737 AHCI_ADDR_SET_PMULT(&dev_addr, addrp->aa_port);
5733 5738 } else {
5734 5739 AHCIDBG(AHCIDBG_ENTRY, ahci_ctlp,
5735 5740 "ahci_find_dev_signature enter: port %d:%d",
5736 5741 port, pmport);
5737 5742 dev_addr = *addrp;
5738 5743 }
5739 5744
5740 5745 /* Assume it is unknown. */
5741 5746 AHCIPORT_SET_DEV_TYPE(ahci_portp, addrp, SATA_DTYPE_UNKNOWN);
5742 5747
5743 5748 /* Issue a software reset to get the signature */
5744 5749 rval = ahci_software_reset(ahci_ctlp, ahci_portp, &dev_addr);
5745 5750 if (rval != AHCI_SUCCESS) {
5746 5751
5747 5752 /*
5748 5753 * Try to do software reset again with pmport set with 0 if
5749 5754 * the controller is set with AHCI_CAP_SRST_NO_HOSTPORT and
5750 5755 * the original pmport is set with SATA_PMULT_HOSTPORT (0xf)
5751 5756 */
5752 5757 if ((ahci_ctlp->ahcictl_cap & AHCI_CAP_SRST_NO_HOSTPORT) &&
5753 5758 (dev_addr.aa_pmport == SATA_PMULT_HOSTPORT)) {
5754 5759 dev_addr.aa_pmport = 0;
5755 5760 rval = ahci_software_reset(ahci_ctlp, ahci_portp,
5756 5761 &dev_addr);
5757 5762 }
5758 5763
5759 5764 if (rval != AHCI_SUCCESS) {
5760 5765 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
5761 5766 "ahci_find_dev_signature: software reset failed "
5762 5767 "at port %d:%d, cannot get signature.",
5763 5768 port, pmport);
5764 5769
5765 5770 AHCIPORT_SET_STATE(ahci_portp, addrp,
5766 5771 SATA_PSTATE_FAILED);
5767 5772 return;
5768 5773 }
5769 5774 }
5770 5775
5771 5776 /*
5772 5777 * ahci_software_reset has started the port, so we need manually stop
5773 5778 * the port again.
5774 5779 */
5775 5780 if (AHCI_ADDR_IS_PORT(addrp)) {
5776 5781 if (ahci_put_port_into_notrunning_state(ahci_ctlp,
5777 5782 ahci_portp, port) != AHCI_SUCCESS) {
5778 5783 AHCIDBG(AHCIDBG_INFO, ahci_ctlp,
5779 5784 "ahci_find_dev_signature: cannot stop port %d.",
5780 5785 port);
5781 5786 ahci_portp->ahciport_port_state = SATA_PSTATE_FAILED;
5782 5787 return;
5783 5788 }
5784 5789 }
5785 5790
5786 5791 /* Now we can make sure that a valid signature is received. */
5787 5792 signature = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
5788 5793 (uint32_t *)AHCI_PORT_PxSIG(ahci_ctlp, port));
5789 5794
5790 5795 if (AHCI_ADDR_IS_PMPORT(addrp)) {
5791 5796 AHCIDBG(AHCIDBG_INIT|AHCIDBG_INFO|AHCIDBG_PMULT, ahci_ctlp,
5792 5797 "ahci_find_dev_signature: signature = 0x%x at port %d:%d",
5793 5798 signature, port, pmport);
5794 5799 } else {
5795 5800 AHCIDBG(AHCIDBG_INIT|AHCIDBG_INFO, ahci_ctlp,
5796 5801 "ahci_find_dev_signature: signature = 0x%x at port %d",
5797 5802 signature, port);
5798 5803 }
5799 5804
5800 5805 /* NOTE: Only support ATAPI device at controller port. */
5801 5806 if (signature == AHCI_SIGNATURE_ATAPI && !AHCI_ADDR_IS_PORT(addrp))
5802 5807 signature = SATA_DTYPE_UNKNOWN;
5803 5808
5804 5809 switch (signature) {
5805 5810
5806 5811 case AHCI_SIGNATURE_DISK:
5807 5812 AHCIPORT_SET_DEV_TYPE(ahci_portp, addrp, SATA_DTYPE_ATADISK);
5808 5813 AHCIDBG(AHCIDBG_INFO, ahci_ctlp,
5809 5814 "Disk is found at port: %d", port);
5810 5815 break;
5811 5816
5812 5817 case AHCI_SIGNATURE_ATAPI:
5813 5818 AHCIPORT_SET_DEV_TYPE(ahci_portp, addrp, SATA_DTYPE_ATAPI);
5814 5819 AHCIDBG(AHCIDBG_INFO, ahci_ctlp,
5815 5820 "ATAPI device is found at port: %d", port);
5816 5821 break;
5817 5822
5818 5823 case AHCI_SIGNATURE_PORT_MULTIPLIER:
5819 5824 /* Port Multiplier cannot recursively attached. */
5820 5825 ASSERT(AHCI_ADDR_IS_PORT(addrp));
5821 5826 AHCIPORT_SET_DEV_TYPE(ahci_portp, addrp, SATA_DTYPE_PMULT);
5822 5827 AHCIDBG(AHCIDBG_INFO, ahci_ctlp,
5823 5828 "Port Multiplier is found at port: %d", port);
5824 5829 break;
5825 5830
5826 5831 default:
5827 5832 AHCIPORT_SET_DEV_TYPE(ahci_portp, addrp, SATA_DTYPE_UNKNOWN);
5828 5833 AHCIDBG(AHCIDBG_INFO, ahci_ctlp,
5829 5834 "Unknown device is found at port: %d", port);
5830 5835 }
5831 5836 }
5832 5837
5833 5838 /*
5834 5839 * According to the spec, to reliably detect hot plug removals, software
5835 5840 * must disable interface power management. Software should perform the
5836 5841 * following initialization on a port after a device is attached:
5837 5842 * Set PxSCTL.IPM to 3h to disable interface state transitions
5838 5843 * Set PxCMD.ALPE to '0' to disable aggressive power management
5839 5844 * Disable device initiated interface power management by SET FEATURE
5840 5845 *
5841 5846 * We can ignore the last item because by default the feature is disabled
5842 5847 */
5843 5848 static void
5844 5849 ahci_disable_interface_pm(ahci_ctl_t *ahci_ctlp, uint8_t port)
5845 5850 {
5846 5851 uint32_t port_scontrol, port_cmd_status;
5847 5852
5848 5853 port_scontrol = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
5849 5854 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port));
5850 5855 SCONTROL_SET_IPM(port_scontrol, SCONTROL_IPM_DISABLE_BOTH);
5851 5856 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
5852 5857 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port), port_scontrol);
5853 5858
5854 5859 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
5855 5860 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port));
5856 5861 port_cmd_status &= ~AHCI_CMD_STATUS_ALPE;
5857 5862 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
5858 5863 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), port_cmd_status);
5859 5864 }
5860 5865
5861 5866 /*
5862 5867 * Start the port - set PxCMD.ST to 1, if PxCMD.FRE is not set
5863 5868 * to 1, then set it firstly.
5864 5869 *
5865 5870 * Each port contains two major DMA engines. One DMA engine walks through
5866 5871 * the command list, and is controlled by PxCMD.ST. The second DMA engine
5867 5872 * copies received FISes into system memory, and is controlled by PxCMD.FRE.
5868 5873 *
5869 5874 * Software shall not set PxCMD.ST to '1' until it verifies that PxCMD.CR
5870 5875 * is '0' and has set PxCMD.FRE is '1'. And software shall not clear
5871 5876 * PxCMD.FRE while PxCMD.ST or PxCMD.CR is set '1'.
5872 5877 *
5873 5878 * Software shall not set PxCMD.ST to '1' unless a functional device is
5874 5879 * present on the port(as determined by PxTFD.STS.BSY = '0',
5875 5880 * PxTFD.STS.DRQ = '0', and PxSSTS.DET = 3h).
5876 5881 */
5877 5882 static int
5878 5883 ahci_start_port(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, uint8_t port)
5879 5884 {
5880 5885 uint32_t port_cmd_status;
5881 5886
5882 5887 ASSERT(MUTEX_HELD(&ahci_portp->ahciport_mutex));
5883 5888
5884 5889 AHCIDBG(AHCIDBG_ENTRY, ahci_ctlp, "ahci_start_port: %d enter", port);
5885 5890
5886 5891 if (ahci_portp->ahciport_port_state & SATA_PSTATE_FAILED) {
5887 5892 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp, "ahci_start_port failed "
5888 5893 "the state for port %d is 0x%x",
5889 5894 port, ahci_portp->ahciport_port_state);
5890 5895 return (AHCI_FAILURE);
5891 5896 }
5892 5897
5893 5898 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) {
5894 5899 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp, "ahci_start_port failed "
5895 5900 "no device is attached at port %d", port);
5896 5901 return (AHCI_FAILURE);
5897 5902 }
5898 5903
5899 5904 /* First to set PxCMD.FRE before setting PxCMD.ST. */
5900 5905 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
5901 5906 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port));
5902 5907
5903 5908 if (!(port_cmd_status & AHCI_CMD_STATUS_FRE)) {
5904 5909 port_cmd_status |= AHCI_CMD_STATUS_FRE;
5905 5910 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
5906 5911 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port),
5907 5912 port_cmd_status);
5908 5913 }
5909 5914
5910 5915 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
5911 5916 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port));
5912 5917
5913 5918 port_cmd_status |= AHCI_CMD_STATUS_ST;
5914 5919
5915 5920 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
5916 5921 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port),
5917 5922 port_cmd_status);
5918 5923
5919 5924 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_STARTED;
5920 5925
5921 5926 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp, "ahci_start_port: "
5922 5927 "PxCMD.ST set to '1' at port %d", port);
5923 5928
5924 5929 return (AHCI_SUCCESS);
5925 5930 }
5926 5931
5927 5932 /*
5928 5933 * Setup PxCLB, PxCLBU, PxFB, and PxFBU for particular port. First, we need
5929 5934 * to make sure PxCMD.ST, PxCMD.CR, PxCMD.FRE, and PxCMD.FR are all cleared.
5930 5935 * Then set PxCLB, PxCLBU, PxFB, and PxFBU.
5931 5936 */
5932 5937 static int
5933 5938 ahci_setup_port_base_addresses(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp)
5934 5939 {
5935 5940 uint8_t port = ahci_portp->ahciport_port_num;
5936 5941 uint32_t port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
5937 5942 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port));
5938 5943
5939 5944 ASSERT(MUTEX_HELD(&ahci_portp->ahciport_mutex));
5940 5945
5941 5946 /* Step 1: Make sure both PxCMD.ST and PxCMD.CR are cleared. */
5942 5947 if (port_cmd_status & (AHCI_CMD_STATUS_ST | AHCI_CMD_STATUS_CR)) {
5943 5948 if (ahci_put_port_into_notrunning_state(ahci_ctlp, ahci_portp,
5944 5949 port) != AHCI_SUCCESS)
5945 5950 return (AHCI_FAILURE);
5946 5951
5947 5952 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
5948 5953 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port));
5949 5954 }
5950 5955
5951 5956 /* Step 2: Make sure both PxCMD.FRE and PxCMD.FR are cleared. */
5952 5957 if (port_cmd_status & (AHCI_CMD_STATUS_FRE | AHCI_CMD_STATUS_FR)) {
5953 5958 int loop_count = 0;
5954 5959
5955 5960 /* Clear PxCMD.FRE */
5956 5961 port_cmd_status &= ~AHCI_CMD_STATUS_FRE;
5957 5962 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
5958 5963 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port),
5959 5964 port_cmd_status);
5960 5965
5961 5966 /* Wait until PxCMD.FR is cleared */
5962 5967 for (;;) {
5963 5968 port_cmd_status =
5964 5969 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
5965 5970 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port));
5966 5971
5967 5972 if (!(port_cmd_status & AHCI_CMD_STATUS_FR))
5968 5973 break;
5969 5974
5970 5975 if (loop_count++ >= AHCI_POLLRATE_PORT_IDLE_FR) {
5971 5976 AHCIDBG(AHCIDBG_INIT | AHCIDBG_ERRS, ahci_ctlp,
5972 5977 "ahci_setup_port_base_addresses: cannot "
5973 5978 "clear PxCMD.FR for port %d.", port);
5974 5979
5975 5980 /*
5976 5981 * We are effectively timing out after 0.5 sec.
5977 5982 * This value is specified in AHCI spec.
5978 5983 */
5979 5984 return (AHCI_FAILURE);
5980 5985 }
5981 5986
5982 5987 /* Wait for 1 millisec */
5983 5988 drv_usecwait(AHCI_1MS_USECS);
5984 5989 }
5985 5990 }
5986 5991
5987 5992 /* Step 3: Config Port Command List Base Address */
5988 5993 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
5989 5994 (uint32_t *)AHCI_PORT_PxCLB(ahci_ctlp, port),
5990 5995 ahci_portp->ahciport_cmd_list_dma_cookie.dmac_address);
5991 5996
5992 5997 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
5993 5998 (uint32_t *)AHCI_PORT_PxCLBU(ahci_ctlp, port),
5994 5999 ahci_portp->ahciport_cmd_list_dma_cookie.dmac_notused);
5995 6000
5996 6001 /* Step 4: Config Port Received FIS Base Address */
5997 6002 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
5998 6003 (uint32_t *)AHCI_PORT_PxFB(ahci_ctlp, port),
5999 6004 ahci_portp->ahciport_rcvd_fis_dma_cookie.dmac_address);
6000 6005
6001 6006 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
6002 6007 (uint32_t *)AHCI_PORT_PxFBU(ahci_ctlp, port),
6003 6008 ahci_portp->ahciport_rcvd_fis_dma_cookie.dmac_notused);
6004 6009
6005 6010 return (AHCI_SUCCESS);
6006 6011 }
6007 6012
6008 6013 /*
6009 6014 * Allocate the ahci_port_t including Received FIS and Command List.
6010 6015 * The argument - port is the physical port number, and not logical
6011 6016 * port number seen by the SATA framework.
6012 6017 */
6013 6018 static int
6014 6019 ahci_alloc_port_state(ahci_ctl_t *ahci_ctlp, uint8_t port)
6015 6020 {
6016 6021 dev_info_t *dip = ahci_ctlp->ahcictl_dip;
6017 6022 ahci_port_t *ahci_portp;
6018 6023 char taskq_name[64] = "event_handle_taskq";
6019 6024
6020 6025 ASSERT(MUTEX_HELD(&ahci_ctlp->ahcictl_mutex));
6021 6026
6022 6027 ahci_portp =
6023 6028 (ahci_port_t *)kmem_zalloc(sizeof (ahci_port_t), KM_SLEEP);
6024 6029
6025 6030 ahci_ctlp->ahcictl_ports[port] = ahci_portp;
6026 6031 ahci_portp->ahciport_port_num = port;
6027 6032
6028 6033 /* Initialize the port condition variable */
6029 6034 cv_init(&ahci_portp->ahciport_cv, NULL, CV_DRIVER, NULL);
6030 6035
6031 6036 /* Initialize the port mutex */
6032 6037 mutex_init(&ahci_portp->ahciport_mutex, NULL, MUTEX_DRIVER,
6033 6038 (void *)(uintptr_t)ahci_ctlp->ahcictl_intr_pri);
6034 6039
6035 6040 mutex_enter(&ahci_portp->ahciport_mutex);
6036 6041
6037 6042 /*
6038 6043 * Allocate memory for received FIS structure and
6039 6044 * command list for this port
6040 6045 */
6041 6046 if (ahci_alloc_rcvd_fis(ahci_ctlp, ahci_portp) != AHCI_SUCCESS) {
6042 6047 goto err_case1;
6043 6048 }
6044 6049
6045 6050 if (ahci_alloc_cmd_list(ahci_ctlp, ahci_portp) != AHCI_SUCCESS) {
6046 6051 goto err_case2;
6047 6052 }
6048 6053
6049 6054 /* Setup PxCMD.CLB, PxCMD.CLBU, PxCMD.FB, and PxCMD.FBU */
6050 6055 if (ahci_setup_port_base_addresses(ahci_ctlp, ahci_portp) !=
6051 6056 AHCI_SUCCESS) {
6052 6057 goto err_case3;
6053 6058 }
6054 6059
6055 6060 (void) snprintf(taskq_name + strlen(taskq_name),
6056 6061 sizeof (taskq_name) - strlen(taskq_name),
6057 6062 "_port%d", port);
6058 6063
6059 6064 /* Create the taskq for the port */
6060 6065 if ((ahci_portp->ahciport_event_taskq = ddi_taskq_create(dip,
6061 6066 taskq_name, 2, TASKQ_DEFAULTPRI, 0)) == NULL) {
6062 6067 cmn_err(CE_WARN, "!ahci%d: ddi_taskq_create failed for event "
6063 6068 "handle", ddi_get_instance(ahci_ctlp->ahcictl_dip));
6064 6069 goto err_case3;
6065 6070 }
6066 6071
6067 6072 /* Allocate the argument for the taskq */
6068 6073 ahci_portp->ahciport_event_args =
6069 6074 kmem_zalloc(sizeof (ahci_event_arg_t), KM_SLEEP);
6070 6075
6071 6076 ahci_portp->ahciport_event_args->ahciea_addrp =
6072 6077 kmem_zalloc(sizeof (ahci_addr_t), KM_SLEEP);
6073 6078
6074 6079 if (ahci_portp->ahciport_event_args == NULL)
6075 6080 goto err_case4;
6076 6081
6077 6082 /* Initialize the done queue */
6078 6083 ahci_portp->ahciport_doneq = NULL;
6079 6084 ahci_portp->ahciport_doneqtail = &ahci_portp->ahciport_doneq;
6080 6085 ahci_portp->ahciport_doneq_len = 0;
6081 6086
6082 6087 mutex_exit(&ahci_portp->ahciport_mutex);
6083 6088
6084 6089 return (AHCI_SUCCESS);
6085 6090
6086 6091 err_case4:
6087 6092 ddi_taskq_destroy(ahci_portp->ahciport_event_taskq);
6088 6093
6089 6094 err_case3:
6090 6095 ahci_dealloc_cmd_list(ahci_ctlp, ahci_portp);
6091 6096
6092 6097 err_case2:
6093 6098 ahci_dealloc_rcvd_fis(ahci_portp);
6094 6099
6095 6100 err_case1:
6096 6101 mutex_exit(&ahci_portp->ahciport_mutex);
6097 6102 mutex_destroy(&ahci_portp->ahciport_mutex);
6098 6103 cv_destroy(&ahci_portp->ahciport_cv);
6099 6104
6100 6105 kmem_free(ahci_portp, sizeof (ahci_port_t));
6101 6106
6102 6107 return (AHCI_FAILURE);
6103 6108 }
6104 6109
6105 6110 /*
6106 6111 * Reverse of ahci_alloc_port_state().
6107 6112 */
6108 6113 static void
6109 6114 ahci_dealloc_port_state(ahci_ctl_t *ahci_ctlp, uint8_t port)
6110 6115 {
6111 6116 ahci_port_t *ahci_portp = ahci_ctlp->ahcictl_ports[port];
6112 6117
6113 6118 ASSERT(MUTEX_HELD(&ahci_ctlp->ahcictl_mutex));
6114 6119 ASSERT(ahci_portp != NULL);
6115 6120
6116 6121 mutex_enter(&ahci_portp->ahciport_mutex);
6117 6122 kmem_free(ahci_portp->ahciport_event_args->ahciea_addrp,
6118 6123 sizeof (ahci_addr_t));
6119 6124 ahci_portp->ahciport_event_args->ahciea_addrp = NULL;
6120 6125 kmem_free(ahci_portp->ahciport_event_args, sizeof (ahci_event_arg_t));
6121 6126 ahci_portp->ahciport_event_args = NULL;
6122 6127 ddi_taskq_destroy(ahci_portp->ahciport_event_taskq);
6123 6128 ahci_dealloc_cmd_list(ahci_ctlp, ahci_portp);
6124 6129 ahci_dealloc_rcvd_fis(ahci_portp);
6125 6130 ahci_dealloc_pmult(ahci_ctlp, ahci_portp);
6126 6131 mutex_exit(&ahci_portp->ahciport_mutex);
6127 6132
6128 6133 mutex_destroy(&ahci_portp->ahciport_mutex);
6129 6134 cv_destroy(&ahci_portp->ahciport_cv);
6130 6135
6131 6136 kmem_free(ahci_portp, sizeof (ahci_port_t));
6132 6137
6133 6138 ahci_ctlp->ahcictl_ports[port] = NULL;
6134 6139 }
6135 6140
6136 6141 /*
6137 6142 * Allocates memory for the Received FIS Structure
6138 6143 */
6139 6144 static int
6140 6145 ahci_alloc_rcvd_fis(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp)
6141 6146 {
6142 6147 size_t rcvd_fis_size;
6143 6148 size_t ret_len;
6144 6149 uint_t cookie_count;
6145 6150
6146 6151 ASSERT(MUTEX_HELD(&ahci_portp->ahciport_mutex));
6147 6152
6148 6153 rcvd_fis_size = sizeof (ahci_rcvd_fis_t);
6149 6154
6150 6155 /* allocate rcvd FIS dma handle. */
6151 6156 if (ddi_dma_alloc_handle(ahci_ctlp->ahcictl_dip,
6152 6157 &ahci_ctlp->ahcictl_rcvd_fis_dma_attr,
6153 6158 DDI_DMA_SLEEP,
6154 6159 NULL,
6155 6160 &ahci_portp->ahciport_rcvd_fis_dma_handle) !=
6156 6161 DDI_SUCCESS) {
6157 6162 AHCIDBG(AHCIDBG_INIT, ahci_ctlp,
6158 6163 "rcvd FIS dma handle alloc failed", NULL);
6159 6164
6160 6165 return (AHCI_FAILURE);
6161 6166 }
6162 6167
6163 6168 if (ddi_dma_mem_alloc(ahci_portp->ahciport_rcvd_fis_dma_handle,
6164 6169 rcvd_fis_size,
6165 6170 &accattr,
6166 6171 DDI_DMA_CONSISTENT,
6167 6172 DDI_DMA_SLEEP,
6168 6173 NULL,
6169 6174 (caddr_t *)&ahci_portp->ahciport_rcvd_fis,
6170 6175 &ret_len,
6171 6176 &ahci_portp->ahciport_rcvd_fis_acc_handle) != NULL) {
6172 6177
6173 6178 AHCIDBG(AHCIDBG_INIT, ahci_ctlp,
6174 6179 "rcvd FIS dma mem alloc fail", NULL);
6175 6180 /* error.. free the dma handle. */
6176 6181 ddi_dma_free_handle(&ahci_portp->ahciport_rcvd_fis_dma_handle);
6177 6182 return (AHCI_FAILURE);
6178 6183 }
6179 6184
6180 6185 if (ddi_dma_addr_bind_handle(ahci_portp->ahciport_rcvd_fis_dma_handle,
6181 6186 NULL,
6182 6187 (caddr_t)ahci_portp->ahciport_rcvd_fis,
6183 6188 rcvd_fis_size,
6184 6189 DDI_DMA_RDWR | DDI_DMA_CONSISTENT,
6185 6190 DDI_DMA_SLEEP,
6186 6191 NULL,
6187 6192 &ahci_portp->ahciport_rcvd_fis_dma_cookie,
6188 6193 &cookie_count) != DDI_DMA_MAPPED) {
6189 6194
6190 6195 AHCIDBG(AHCIDBG_INIT, ahci_ctlp,
6191 6196 "rcvd FIS dma handle bind fail", NULL);
6192 6197 /* error.. free the dma handle & free the memory. */
6193 6198 ddi_dma_mem_free(&ahci_portp->ahciport_rcvd_fis_acc_handle);
6194 6199 ddi_dma_free_handle(&ahci_portp->ahciport_rcvd_fis_dma_handle);
6195 6200 return (AHCI_FAILURE);
6196 6201 }
6197 6202
6198 6203 bzero((void *)ahci_portp->ahciport_rcvd_fis, rcvd_fis_size);
6199 6204
6200 6205 AHCIDBG(AHCIDBG_INIT, ahci_ctlp, "64-bit, dma address: 0x%llx",
6201 6206 ahci_portp->ahciport_rcvd_fis_dma_cookie.dmac_laddress);
6202 6207 AHCIDBG(AHCIDBG_INIT, ahci_ctlp, "32-bit, dma address: 0x%x",
6203 6208 ahci_portp->ahciport_rcvd_fis_dma_cookie.dmac_address);
6204 6209
6205 6210 return (AHCI_SUCCESS);
6206 6211 }
6207 6212
6208 6213 /*
6209 6214 * Deallocates the Received FIS Structure
6210 6215 */
6211 6216 static void
6212 6217 ahci_dealloc_rcvd_fis(ahci_port_t *ahci_portp)
6213 6218 {
6214 6219 ASSERT(MUTEX_HELD(&ahci_portp->ahciport_mutex));
6215 6220
6216 6221 /* Unbind the cmd list dma handle first. */
6217 6222 (void) ddi_dma_unbind_handle(ahci_portp->ahciport_rcvd_fis_dma_handle);
6218 6223
6219 6224 /* Then free the underlying memory. */
6220 6225 ddi_dma_mem_free(&ahci_portp->ahciport_rcvd_fis_acc_handle);
6221 6226
6222 6227 /* Now free the handle itself. */
6223 6228 ddi_dma_free_handle(&ahci_portp->ahciport_rcvd_fis_dma_handle);
6224 6229 }
6225 6230
6226 6231 /*
6227 6232 * Allocates memory for the Command List, which contains up to 32 entries.
6228 6233 * Each entry contains a command header, which is a 32-byte structure that
6229 6234 * includes the pointer to the command table.
6230 6235 */
6231 6236 static int
6232 6237 ahci_alloc_cmd_list(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp)
6233 6238 {
6234 6239 size_t cmd_list_size;
6235 6240 size_t ret_len;
6236 6241 uint_t cookie_count;
6237 6242
6238 6243 ASSERT(MUTEX_HELD(&ahci_portp->ahciport_mutex));
6239 6244
6240 6245 cmd_list_size =
6241 6246 ahci_ctlp->ahcictl_num_cmd_slots * sizeof (ahci_cmd_header_t);
6242 6247
6243 6248 /* allocate cmd list dma handle. */
6244 6249 if (ddi_dma_alloc_handle(ahci_ctlp->ahcictl_dip,
6245 6250 &ahci_ctlp->ahcictl_cmd_list_dma_attr,
6246 6251 DDI_DMA_SLEEP,
6247 6252 NULL,
6248 6253 &ahci_portp->ahciport_cmd_list_dma_handle) != DDI_SUCCESS) {
6249 6254
6250 6255 AHCIDBG(AHCIDBG_INIT, ahci_ctlp,
6251 6256 "cmd list dma handle alloc failed", NULL);
6252 6257 return (AHCI_FAILURE);
6253 6258 }
6254 6259
6255 6260 if (ddi_dma_mem_alloc(ahci_portp->ahciport_cmd_list_dma_handle,
6256 6261 cmd_list_size,
6257 6262 &accattr,
6258 6263 DDI_DMA_CONSISTENT,
6259 6264 DDI_DMA_SLEEP,
6260 6265 NULL,
6261 6266 (caddr_t *)&ahci_portp->ahciport_cmd_list,
6262 6267 &ret_len,
6263 6268 &ahci_portp->ahciport_cmd_list_acc_handle) != NULL) {
6264 6269
6265 6270 AHCIDBG(AHCIDBG_INIT, ahci_ctlp,
6266 6271 "cmd list dma mem alloc fail", NULL);
6267 6272 /* error.. free the dma handle. */
6268 6273 ddi_dma_free_handle(&ahci_portp->ahciport_cmd_list_dma_handle);
6269 6274 return (AHCI_FAILURE);
6270 6275 }
6271 6276
6272 6277 if (ddi_dma_addr_bind_handle(ahci_portp->ahciport_cmd_list_dma_handle,
6273 6278 NULL,
6274 6279 (caddr_t)ahci_portp->ahciport_cmd_list,
6275 6280 cmd_list_size,
6276 6281 DDI_DMA_RDWR | DDI_DMA_CONSISTENT,
6277 6282 DDI_DMA_SLEEP,
6278 6283 NULL,
6279 6284 &ahci_portp->ahciport_cmd_list_dma_cookie,
6280 6285 &cookie_count) != DDI_DMA_MAPPED) {
6281 6286
6282 6287 AHCIDBG(AHCIDBG_INIT, ahci_ctlp,
6283 6288 "cmd list dma handle bind fail", NULL);
6284 6289 /* error.. free the dma handle & free the memory. */
6285 6290 ddi_dma_mem_free(&ahci_portp->ahciport_cmd_list_acc_handle);
6286 6291 ddi_dma_free_handle(&ahci_portp->ahciport_cmd_list_dma_handle);
6287 6292 return (AHCI_FAILURE);
6288 6293 }
6289 6294
6290 6295 bzero((void *)ahci_portp->ahciport_cmd_list, cmd_list_size);
6291 6296
6292 6297 AHCIDBG(AHCIDBG_INIT, ahci_ctlp, "64-bit, dma address: 0x%llx",
6293 6298 ahci_portp->ahciport_cmd_list_dma_cookie.dmac_laddress);
6294 6299
6295 6300 AHCIDBG(AHCIDBG_INIT, ahci_ctlp, "32-bit, dma address: 0x%x",
6296 6301 ahci_portp->ahciport_cmd_list_dma_cookie.dmac_address);
6297 6302
6298 6303 if (ahci_alloc_cmd_tables(ahci_ctlp, ahci_portp) != AHCI_SUCCESS) {
6299 6304 goto err_out;
6300 6305 }
6301 6306
6302 6307 return (AHCI_SUCCESS);
6303 6308
6304 6309 err_out:
6305 6310 /* Unbind the cmd list dma handle first. */
6306 6311 (void) ddi_dma_unbind_handle(ahci_portp->ahciport_cmd_list_dma_handle);
6307 6312
6308 6313 /* Then free the underlying memory. */
6309 6314 ddi_dma_mem_free(&ahci_portp->ahciport_cmd_list_acc_handle);
6310 6315
6311 6316 /* Now free the handle itself. */
6312 6317 ddi_dma_free_handle(&ahci_portp->ahciport_cmd_list_dma_handle);
6313 6318
6314 6319 return (AHCI_FAILURE);
6315 6320 }
6316 6321
6317 6322 /*
6318 6323 * Deallocates the Command List
6319 6324 */
6320 6325 static void
6321 6326 ahci_dealloc_cmd_list(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp)
6322 6327 {
6323 6328 ASSERT(MUTEX_HELD(&ahci_portp->ahciport_mutex));
6324 6329
6325 6330 /* First dealloc command table */
6326 6331 ahci_dealloc_cmd_tables(ahci_ctlp, ahci_portp);
6327 6332
6328 6333 /* Unbind the cmd list dma handle first. */
6329 6334 (void) ddi_dma_unbind_handle(ahci_portp->ahciport_cmd_list_dma_handle);
6330 6335
6331 6336 /* Then free the underlying memory. */
6332 6337 ddi_dma_mem_free(&ahci_portp->ahciport_cmd_list_acc_handle);
6333 6338
6334 6339 /* Now free the handle itself. */
6335 6340 ddi_dma_free_handle(&ahci_portp->ahciport_cmd_list_dma_handle);
6336 6341 }
6337 6342
6338 6343 /*
6339 6344 * Allocates memory for all Command Tables, which contains Command FIS,
6340 6345 * ATAPI Command and Physical Region Descriptor Table.
6341 6346 */
6342 6347 static int
6343 6348 ahci_alloc_cmd_tables(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp)
6344 6349 {
6345 6350 size_t ret_len;
6346 6351 ddi_dma_cookie_t cmd_table_dma_cookie;
6347 6352 uint_t cookie_count;
6348 6353 int slot;
6349 6354
6350 6355 ASSERT(MUTEX_HELD(&ahci_portp->ahciport_mutex));
6351 6356
6352 6357 AHCIDBG(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp,
6353 6358 "ahci_alloc_cmd_tables: port %d enter",
6354 6359 ahci_portp->ahciport_port_num);
6355 6360
6356 6361 for (slot = 0; slot < ahci_ctlp->ahcictl_num_cmd_slots; slot++) {
6357 6362 /* Allocate cmd table dma handle. */
6358 6363 if (ddi_dma_alloc_handle(ahci_ctlp->ahcictl_dip,
6359 6364 &ahci_ctlp->ahcictl_cmd_table_dma_attr,
6360 6365 DDI_DMA_SLEEP,
6361 6366 NULL,
6362 6367 &ahci_portp->ahciport_cmd_tables_dma_handle[slot]) !=
6363 6368 DDI_SUCCESS) {
6364 6369
6365 6370 AHCIDBG(AHCIDBG_INIT, ahci_ctlp,
6366 6371 "cmd table dma handle alloc failed", NULL);
6367 6372
6368 6373 goto err_out;
6369 6374 }
6370 6375
6371 6376 if (ddi_dma_mem_alloc(
6372 6377 ahci_portp->ahciport_cmd_tables_dma_handle[slot],
6373 6378 ahci_cmd_table_size,
6374 6379 &accattr,
6375 6380 DDI_DMA_CONSISTENT,
6376 6381 DDI_DMA_SLEEP,
6377 6382 NULL,
6378 6383 (caddr_t *)&ahci_portp->ahciport_cmd_tables[slot],
6379 6384 &ret_len,
6380 6385 &ahci_portp->ahciport_cmd_tables_acc_handle[slot]) !=
6381 6386 NULL) {
6382 6387
6383 6388 AHCIDBG(AHCIDBG_INIT, ahci_ctlp,
6384 6389 "cmd table dma mem alloc fail", NULL);
6385 6390
6386 6391 /* error.. free the dma handle. */
6387 6392 ddi_dma_free_handle(
6388 6393 &ahci_portp->ahciport_cmd_tables_dma_handle[slot]);
6389 6394 goto err_out;
6390 6395 }
6391 6396
6392 6397 if (ddi_dma_addr_bind_handle(
6393 6398 ahci_portp->ahciport_cmd_tables_dma_handle[slot],
6394 6399 NULL,
6395 6400 (caddr_t)ahci_portp->ahciport_cmd_tables[slot],
6396 6401 ahci_cmd_table_size,
6397 6402 DDI_DMA_RDWR | DDI_DMA_CONSISTENT,
6398 6403 DDI_DMA_SLEEP,
6399 6404 NULL,
6400 6405 &cmd_table_dma_cookie,
6401 6406 &cookie_count) != DDI_DMA_MAPPED) {
6402 6407
6403 6408 AHCIDBG(AHCIDBG_INIT, ahci_ctlp,
6404 6409 "cmd table dma handle bind fail", NULL);
6405 6410 /* error.. free the dma handle & free the memory. */
6406 6411 ddi_dma_mem_free(
6407 6412 &ahci_portp->ahciport_cmd_tables_acc_handle[slot]);
6408 6413 ddi_dma_free_handle(
6409 6414 &ahci_portp->ahciport_cmd_tables_dma_handle[slot]);
6410 6415 goto err_out;
6411 6416 }
6412 6417
6413 6418 bzero((void *)ahci_portp->ahciport_cmd_tables[slot],
6414 6419 ahci_cmd_table_size);
6415 6420
6416 6421 /* Config Port Command Table Base Address */
6417 6422 SET_COMMAND_TABLE_BASE_ADDR(
6418 6423 (&ahci_portp->ahciport_cmd_list[slot]),
6419 6424 cmd_table_dma_cookie.dmac_laddress & 0xffffffffull);
6420 6425
6421 6426 #ifndef __lock_lint
6422 6427 SET_COMMAND_TABLE_BASE_ADDR_UPPER(
6423 6428 (&ahci_portp->ahciport_cmd_list[slot]),
6424 6429 cmd_table_dma_cookie.dmac_laddress >> 32);
6425 6430 #endif
6426 6431 }
6427 6432
6428 6433 return (AHCI_SUCCESS);
6429 6434 err_out:
6430 6435
6431 6436 for (slot--; slot >= 0; slot--) {
6432 6437 /* Unbind the cmd table dma handle first */
6433 6438 (void) ddi_dma_unbind_handle(
6434 6439 ahci_portp->ahciport_cmd_tables_dma_handle[slot]);
6435 6440
6436 6441 /* Then free the underlying memory */
6437 6442 ddi_dma_mem_free(
6438 6443 &ahci_portp->ahciport_cmd_tables_acc_handle[slot]);
6439 6444
6440 6445 /* Now free the handle itself */
6441 6446 ddi_dma_free_handle(
6442 6447 &ahci_portp->ahciport_cmd_tables_dma_handle[slot]);
6443 6448 }
6444 6449
6445 6450 return (AHCI_FAILURE);
6446 6451 }
6447 6452
6448 6453 /*
6449 6454 * Deallocates memory for all Command Tables.
6450 6455 */
6451 6456 static void
6452 6457 ahci_dealloc_cmd_tables(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp)
6453 6458 {
6454 6459 int slot;
6455 6460
6456 6461 ASSERT(MUTEX_HELD(&ahci_portp->ahciport_mutex));
6457 6462
6458 6463 AHCIDBG(AHCIDBG_ENTRY, ahci_ctlp,
6459 6464 "ahci_dealloc_cmd_tables: %d enter",
6460 6465 ahci_portp->ahciport_port_num);
6461 6466
6462 6467 for (slot = 0; slot < ahci_ctlp->ahcictl_num_cmd_slots; slot++) {
6463 6468 /* Unbind the cmd table dma handle first. */
6464 6469 (void) ddi_dma_unbind_handle(
6465 6470 ahci_portp->ahciport_cmd_tables_dma_handle[slot]);
6466 6471
6467 6472 /* Then free the underlying memory. */
6468 6473 ddi_dma_mem_free(
6469 6474 &ahci_portp->ahciport_cmd_tables_acc_handle[slot]);
6470 6475
6471 6476 /* Now free the handle itself. */
6472 6477 ddi_dma_free_handle(
6473 6478 &ahci_portp->ahciport_cmd_tables_dma_handle[slot]);
6474 6479 }
6475 6480 }
6476 6481
6477 6482 /*
6478 6483 * Update SATA registers at controller ports
6479 6484 */
6480 6485 static void
6481 6486 ahci_update_sata_registers(ahci_ctl_t *ahci_ctlp, uint8_t port,
6482 6487 sata_device_t *sd)
6483 6488 {
6484 6489 ASSERT(MUTEX_HELD(&ahci_ctlp->ahcictl_ports[port]->ahciport_mutex));
6485 6490
6486 6491 sd->satadev_scr.sstatus =
6487 6492 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
6488 6493 (uint32_t *)(AHCI_PORT_PxSSTS(ahci_ctlp, port)));
6489 6494 sd->satadev_scr.serror =
6490 6495 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
6491 6496 (uint32_t *)(AHCI_PORT_PxSERR(ahci_ctlp, port)));
6492 6497 sd->satadev_scr.scontrol =
6493 6498 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
6494 6499 (uint32_t *)(AHCI_PORT_PxSCTL(ahci_ctlp, port)));
6495 6500 sd->satadev_scr.sactive =
6496 6501 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
6497 6502 (uint32_t *)(AHCI_PORT_PxSACT(ahci_ctlp, port)));
6498 6503 }
6499 6504
6500 6505 /*
6501 6506 * For poll mode, ahci_port_intr will be called to emulate the interrupt
6502 6507 */
6503 6508 static void
6504 6509 ahci_port_intr(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, uint8_t port)
6505 6510 {
6506 6511 uint32_t port_intr_status;
6507 6512 uint32_t port_intr_enable;
6508 6513
6509 6514 AHCIDBG(AHCIDBG_INTR|AHCIDBG_ENTRY, ahci_ctlp,
6510 6515 "ahci_port_intr enter: port %d", port);
6511 6516
6512 6517 mutex_enter(&ahci_portp->ahciport_mutex);
6513 6518 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_POLLING) {
6514 6519 /* For SATA_OPMODE_POLLING commands */
6515 6520 port_intr_enable =
6516 6521 (AHCI_INTR_STATUS_DHRS |
6517 6522 AHCI_INTR_STATUS_PSS |
6518 6523 AHCI_INTR_STATUS_SDBS |
6519 6524 AHCI_INTR_STATUS_UFS |
6520 6525 AHCI_INTR_STATUS_PCS |
6521 6526 AHCI_INTR_STATUS_PRCS |
6522 6527 AHCI_INTR_STATUS_OFS |
6523 6528 AHCI_INTR_STATUS_INFS |
6524 6529 AHCI_INTR_STATUS_IFS |
6525 6530 AHCI_INTR_STATUS_HBDS |
6526 6531 AHCI_INTR_STATUS_HBFS |
6527 6532 AHCI_INTR_STATUS_TFES);
6528 6533 } else {
6529 6534 /*
6530 6535 * port_intr_enable indicates that the corresponding interrrupt
6531 6536 * reporting is enabled.
6532 6537 */
6533 6538 port_intr_enable = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
6534 6539 (uint32_t *)AHCI_PORT_PxIE(ahci_ctlp, port));
6535 6540 }
6536 6541
6537 6542 /* IPMS error in port reset should be ignored according AHCI spec. */
6538 6543 if (!(ahci_portp->ahciport_flags & AHCI_PORT_FLAG_IGNORE_IPMS))
6539 6544 port_intr_enable |= AHCI_INTR_STATUS_IPMS;
6540 6545 mutex_exit(&ahci_portp->ahciport_mutex);
6541 6546
6542 6547 /*
6543 6548 * port_intr_stats indicates that the corresponding interrupt
6544 6549 * condition is active.
6545 6550 */
6546 6551 port_intr_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
6547 6552 (uint32_t *)AHCI_PORT_PxIS(ahci_ctlp, port));
6548 6553
6549 6554 AHCIDBG(AHCIDBG_INTR, ahci_ctlp,
6550 6555 "ahci_port_intr: port %d, port_intr_status = 0x%x, "
6551 6556 "port_intr_enable = 0x%x",
6552 6557 port, port_intr_status, port_intr_enable);
6553 6558
6554 6559 port_intr_status &= port_intr_enable;
6555 6560
6556 6561 /*
6557 6562 * Pending interrupt events are indicated by the PxIS register.
6558 6563 * Make sure we don't miss any event.
6559 6564 */
6560 6565 if (ahci_check_ctl_handle(ahci_ctlp) != DDI_SUCCESS) {
6561 6566 ddi_fm_service_impact(ahci_ctlp->ahcictl_dip,
6562 6567 DDI_SERVICE_UNAFFECTED);
6563 6568 ddi_fm_acc_err_clear(ahci_ctlp->ahcictl_ahci_acc_handle,
6564 6569 DDI_FME_VERSION);
6565 6570 return;
6566 6571 }
6567 6572
6568 6573 /* First clear the port interrupts status */
6569 6574 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
6570 6575 (uint32_t *)AHCI_PORT_PxIS(ahci_ctlp, port),
6571 6576 port_intr_status);
6572 6577
6573 6578 /* Check the completed non-queued commands */
6574 6579 if (port_intr_status & (AHCI_INTR_STATUS_DHRS |
6575 6580 AHCI_INTR_STATUS_PSS)) {
6576 6581 (void) ahci_intr_cmd_cmplt(ahci_ctlp,
6577 6582 ahci_portp, port);
6578 6583 }
6579 6584
6580 6585 /* Check the completed queued commands */
6581 6586 if (port_intr_status & AHCI_INTR_STATUS_SDBS) {
6582 6587 (void) ahci_intr_set_device_bits(ahci_ctlp,
6583 6588 ahci_portp, port);
6584 6589 }
6585 6590
6586 6591 /* Check the port connect change status interrupt bit */
6587 6592 if (port_intr_status & AHCI_INTR_STATUS_PCS) {
6588 6593 (void) ahci_intr_port_connect_change(ahci_ctlp,
6589 6594 ahci_portp, port);
6590 6595 }
6591 6596
6592 6597 /* Check the device mechanical presence status interrupt bit */
6593 6598 if (port_intr_status & AHCI_INTR_STATUS_DMPS) {
6594 6599 (void) ahci_intr_device_mechanical_presence_status(
6595 6600 ahci_ctlp, ahci_portp, port);
6596 6601 }
6597 6602
6598 6603 /* Check the PhyRdy change status interrupt bit */
6599 6604 if (port_intr_status & AHCI_INTR_STATUS_PRCS) {
6600 6605 (void) ahci_intr_phyrdy_change(ahci_ctlp, ahci_portp,
6601 6606 port);
6602 6607 }
6603 6608
6604 6609 /*
6605 6610 * Check the non-fatal error interrupt bits, there are four
6606 6611 * kinds of non-fatal errors at the time being:
6607 6612 *
6608 6613 * PxIS.UFS - Unknown FIS Error
6609 6614 * PxIS.OFS - Overflow Error
6610 6615 * PxIS.INFS - Interface Non-Fatal Error
6611 6616 * PxIS.IPMS - Incorrect Port Multiplier Status Error
6612 6617 *
6613 6618 * For these non-fatal errors, the HBA can continue to operate,
6614 6619 * so the driver just log the error messages.
6615 6620 */
6616 6621 if (port_intr_status & (AHCI_INTR_STATUS_UFS |
6617 6622 AHCI_INTR_STATUS_OFS |
6618 6623 AHCI_INTR_STATUS_IPMS |
6619 6624 AHCI_INTR_STATUS_INFS)) {
6620 6625 (void) ahci_intr_non_fatal_error(ahci_ctlp, ahci_portp,
6621 6626 port, port_intr_status);
6622 6627 }
6623 6628
6624 6629 /*
6625 6630 * Check the fatal error interrupt bits, there are four kinds
6626 6631 * of fatal errors for AHCI controllers:
6627 6632 *
6628 6633 * PxIS.HBFS - Host Bus Fatal Error
6629 6634 * PxIS.HBDS - Host Bus Data Error
6630 6635 * PxIS.IFS - Interface Fatal Error
6631 6636 * PxIS.TFES - Task File Error
6632 6637 *
6633 6638 * The fatal error means the HBA can not recover from it by
6634 6639 * itself, and it will try to abort the transfer, and the software
6635 6640 * must intervene to restart the port.
6636 6641 */
6637 6642 if (port_intr_status & (AHCI_INTR_STATUS_IFS |
6638 6643 AHCI_INTR_STATUS_HBDS |
6639 6644 AHCI_INTR_STATUS_HBFS |
6640 6645 AHCI_INTR_STATUS_TFES))
6641 6646 (void) ahci_intr_fatal_error(ahci_ctlp, ahci_portp,
6642 6647 port, port_intr_status);
6643 6648
6644 6649 /* Check the cold port detect interrupt bit */
6645 6650 if (port_intr_status & AHCI_INTR_STATUS_CPDS) {
6646 6651 (void) ahci_intr_cold_port_detect(ahci_ctlp, ahci_portp, port);
6647 6652 }
6648 6653
6649 6654 /* Second clear the corresponding bit in IS.IPS */
6650 6655 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
6651 6656 (uint32_t *)AHCI_GLOBAL_IS(ahci_ctlp), (0x1 << port));
6652 6657
6653 6658 /* Try to recover at the end of the interrupt handler. */
6654 6659 if (ahci_check_acc_handle(ahci_ctlp->ahcictl_ahci_acc_handle) !=
6655 6660 DDI_FM_OK) {
6656 6661 ddi_fm_service_impact(ahci_ctlp->ahcictl_dip,
6657 6662 DDI_SERVICE_UNAFFECTED);
6658 6663 ddi_fm_acc_err_clear(ahci_ctlp->ahcictl_ahci_acc_handle,
6659 6664 DDI_FME_VERSION);
6660 6665 }
6661 6666 }
6662 6667
6663 6668 /*
6664 6669 * Interrupt service handler
6665 6670 */
6666 6671 static uint_t
6667 6672 ahci_intr(caddr_t arg1, caddr_t arg2)
6668 6673 {
6669 6674 #ifndef __lock_lint
6670 6675 _NOTE(ARGUNUSED(arg2))
6671 6676 #endif
6672 6677 /* LINTED */
6673 6678 ahci_ctl_t *ahci_ctlp = (ahci_ctl_t *)arg1;
6674 6679 ahci_port_t *ahci_portp;
6675 6680 int32_t global_intr_status;
6676 6681 uint8_t port;
6677 6682
6678 6683 /*
6679 6684 * global_intr_status indicates that the corresponding port has
6680 6685 * an interrupt pending.
6681 6686 */
6682 6687 global_intr_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
6683 6688 (uint32_t *)AHCI_GLOBAL_IS(ahci_ctlp));
6684 6689
6685 6690 if (!(global_intr_status & ahci_ctlp->ahcictl_ports_implemented)) {
6686 6691 /* The interrupt is not ours */
6687 6692 return (DDI_INTR_UNCLAIMED);
6688 6693 }
6689 6694
6690 6695 /*
6691 6696 * Check the handle after reading global_intr_status - we don't want
6692 6697 * to miss any port with pending interrupts.
6693 6698 */
6694 6699 if (ahci_check_acc_handle(ahci_ctlp->ahcictl_ahci_acc_handle) !=
6695 6700 DDI_FM_OK) {
6696 6701 ddi_fm_service_impact(ahci_ctlp->ahcictl_dip,
6697 6702 DDI_SERVICE_UNAFFECTED);
6698 6703 ddi_fm_acc_err_clear(ahci_ctlp->ahcictl_ahci_acc_handle,
6699 6704 DDI_FME_VERSION);
6700 6705 return (DDI_INTR_UNCLAIMED);
6701 6706 }
6702 6707
6703 6708 /* Loop for all the ports */
6704 6709 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) {
6705 6710 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) {
6706 6711 continue;
6707 6712 }
6708 6713 if (!((0x1 << port) & global_intr_status)) {
6709 6714 continue;
6710 6715 }
6711 6716
6712 6717 ahci_portp = ahci_ctlp->ahcictl_ports[port];
6713 6718
6714 6719 /* Call ahci_port_intr */
6715 6720 ahci_port_intr(ahci_ctlp, ahci_portp, port);
6716 6721 }
6717 6722
6718 6723 return (DDI_INTR_CLAIMED);
6719 6724 }
6720 6725
6721 6726 /*
6722 6727 * For non-queued commands, when the corresponding bit in the PxCI register
6723 6728 * is cleared, it means the command is completed successfully. And according
6724 6729 * to the HBA state machine, there are three conditions which possibly will
6725 6730 * try to clear the PxCI register bit.
6726 6731 * 1. Receive one D2H Register FIS which is with 'I' bit set
6727 6732 * 2. Update PIO Setup FIS
6728 6733 * 3. Transmit a command and receive R_OK if CTBA.C is set (software reset)
6729 6734 *
6730 6735 * Process completed non-queued commands when the interrupt status bit -
6731 6736 * AHCI_INTR_STATUS_DHRS or AHCI_INTR_STATUS_PSS is set.
6732 6737 *
6733 6738 * AHCI_INTR_STATUS_DHRS means a D2H Register FIS has been received
6734 6739 * with the 'I' bit set. And the following commands will send thus
6735 6740 * FIS with 'I' bit set upon the successful completion:
6736 6741 * 1. Non-data commands
6737 6742 * 2. DMA data-in command
6738 6743 * 3. DMA data-out command
6739 6744 * 4. PIO data-out command
6740 6745 * 5. PACKET non-data commands
6741 6746 * 6. PACKET PIO data-in command
6742 6747 * 7. PACKET PIO data-out command
6743 6748 * 8. PACKET DMA data-in command
6744 6749 * 9. PACKET DMA data-out command
6745 6750 *
6746 6751 * AHCI_INTR_STATUS_PSS means a PIO Setup FIS has been received
6747 6752 * with the 'I' bit set. And the following commands will send this
6748 6753 * FIS upon the successful completion:
6749 6754 * 1. PIO data-in command
6750 6755 */
6751 6756 static int
6752 6757 ahci_intr_cmd_cmplt(ahci_ctl_t *ahci_ctlp,
6753 6758 ahci_port_t *ahci_portp, uint8_t port)
6754 6759 {
6755 6760 uint32_t port_cmd_issue = 0;
6756 6761 uint32_t finished_tags;
6757 6762 int finished_slot;
6758 6763 sata_pkt_t *satapkt;
6759 6764 ahci_fis_d2h_register_t *rcvd_fisp;
6760 6765 #if AHCI_DEBUG
6761 6766 ahci_cmd_header_t *cmd_header;
6762 6767 uint32_t cmd_dmacount;
6763 6768 #endif
6764 6769
6765 6770 mutex_enter(&ahci_portp->ahciport_mutex);
6766 6771
6767 6772 if (!ERR_RETRI_CMD_IN_PROGRESS(ahci_portp) &&
6768 6773 !RDWR_PMULT_CMD_IN_PROGRESS(ahci_portp) &&
6769 6774 !NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) {
6770 6775 /*
6771 6776 * Spurious interrupt. Nothing to be done.
6772 6777 */
6773 6778 mutex_exit(&ahci_portp->ahciport_mutex);
6774 6779 return (AHCI_SUCCESS);
6775 6780 }
6776 6781
6777 6782 port_cmd_issue = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
6778 6783 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port));
6779 6784
6780 6785 /* If the PxCI corrupts, don't complete the commmands. */
6781 6786 if (ahci_check_acc_handle(ahci_ctlp->ahcictl_ahci_acc_handle)
6782 6787 != DDI_FM_OK) {
6783 6788 mutex_exit(&ahci_portp->ahciport_mutex);
6784 6789 return (AHCI_FAILURE);
6785 6790 }
6786 6791
6787 6792 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) {
6788 6793 /* Slot 0 is always used during error recovery */
6789 6794 finished_tags = 0x1 & ~port_cmd_issue;
6790 6795 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
6791 6796 "ahci_intr_cmd_cmplt: port %d the sata pkt for error "
6792 6797 "retrieval is finished, and finished_tags = 0x%x",
6793 6798 port, finished_tags);
6794 6799 } else if (RDWR_PMULT_CMD_IN_PROGRESS(ahci_portp)) {
6795 6800 finished_tags = 0x1 & ~port_cmd_issue;
6796 6801 AHCIDBG(AHCIDBG_INFO, ahci_ctlp,
6797 6802 "ahci_intr_cmd_cmplt: port %d the sata pkt for r/w "
6798 6803 "port multiplier is finished, and finished_tags = 0x%x",
6799 6804 port, finished_tags);
6800 6805
6801 6806 } else {
6802 6807
6803 6808 finished_tags = ahci_portp->ahciport_pending_tags &
6804 6809 ~port_cmd_issue & AHCI_SLOT_MASK(ahci_ctlp);
6805 6810 }
6806 6811
6807 6812 AHCIDBG(AHCIDBG_INTR, ahci_ctlp,
6808 6813 "ahci_intr_cmd_cmplt: pending_tags = 0x%x, "
6809 6814 "port_cmd_issue = 0x%x finished_tags = 0x%x",
6810 6815 ahci_portp->ahciport_pending_tags, port_cmd_issue,
6811 6816 finished_tags);
6812 6817
6813 6818 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp) &&
6814 6819 (finished_tags == 0x1)) {
6815 6820 satapkt = ahci_portp->ahciport_err_retri_pkt;
6816 6821 ASSERT(satapkt != NULL);
6817 6822
6818 6823 AHCIDBG(AHCIDBG_INTR, ahci_ctlp,
6819 6824 "ahci_intr_cmd_cmplt: sending up pkt 0x%p "
6820 6825 "with SATA_PKT_COMPLETED", (void *)satapkt);
6821 6826
6822 6827 ahci_add_doneq(ahci_portp, satapkt, SATA_PKT_COMPLETED);
6823 6828 goto out;
6824 6829 }
6825 6830
6826 6831 if (RDWR_PMULT_CMD_IN_PROGRESS(ahci_portp) &&
6827 6832 (finished_tags == 0x1)) {
6828 6833 satapkt = ahci_portp->ahciport_rdwr_pmult_pkt;
6829 6834 ASSERT(satapkt != NULL);
6830 6835
6831 6836 AHCIDBG(AHCIDBG_INTR, ahci_ctlp,
6832 6837 "ahci_intr_cmd_cmplt: sending up pkt 0x%p "
6833 6838 "with SATA_PKT_COMPLETED", (void *)satapkt);
6834 6839
6835 6840 /* READ PORTMULT need copy out FIS content. */
6836 6841 if (satapkt->satapkt_cmd.satacmd_flags.sata_special_regs) {
6837 6842 rcvd_fisp = &(ahci_portp->ahciport_rcvd_fis->
6838 6843 ahcirf_d2h_register_fis);
6839 6844 satapkt->satapkt_cmd.satacmd_status_reg =
6840 6845 GET_RFIS_STATUS(rcvd_fisp);
6841 6846 ahci_copy_out_regs(&satapkt->satapkt_cmd, rcvd_fisp);
6842 6847 }
6843 6848
6844 6849 ahci_add_doneq(ahci_portp, satapkt, SATA_PKT_COMPLETED);
6845 6850 goto out;
6846 6851 }
6847 6852
6848 6853 while (finished_tags) {
6849 6854 finished_slot = ddi_ffs(finished_tags) - 1;
6850 6855 if (finished_slot == -1) {
6851 6856 goto out;
6852 6857 }
6853 6858
6854 6859 satapkt = ahci_portp->ahciport_slot_pkts[finished_slot];
6855 6860 ASSERT(satapkt != NULL);
6856 6861 #if AHCI_DEBUG
6857 6862 /*
6858 6863 * For non-native queued commands, the PRD byte count field
6859 6864 * shall contain an accurate count of the number of bytes
6860 6865 * transferred for the command before the PxCI bit is cleared
6861 6866 * to '0' for the command.
6862 6867 *
6863 6868 * The purpose of this field is to let software know how many
6864 6869 * bytes transferred for a given operation in order to
6865 6870 * determine if underflow occurred. When issuing native command
6866 6871 * queuing commands, this field should not be used and is not
6867 6872 * required to be valid since in this case underflow is always
6868 6873 * illegal.
6869 6874 *
6870 6875 * For data reads, the HBA will update its PRD byte count with
6871 6876 * the total number of bytes received from the last FIS, and
6872 6877 * may be able to continue normally. For data writes, the
6873 6878 * device will detect an error, and HBA most likely will get
6874 6879 * a fatal error.
6875 6880 *
6876 6881 * Therefore, here just put code to debug part. And please
6877 6882 * refer to the comment above ahci_intr_fatal_error for the
6878 6883 * definition of underflow error.
6879 6884 */
6880 6885 cmd_dmacount =
6881 6886 ahci_portp->ahciport_prd_bytecounts[finished_slot];
6882 6887 if (cmd_dmacount) {
6883 6888 cmd_header =
6884 6889 &ahci_portp->ahciport_cmd_list[finished_slot];
6885 6890 AHCIDBG(AHCIDBG_INTR|AHCIDBG_PRDT, ahci_ctlp,
6886 6891 "ahci_intr_cmd_cmplt: port %d, "
6887 6892 "PRD Byte Count = 0x%x, "
6888 6893 "ahciport_prd_bytecounts = 0x%x", port,
6889 6894 cmd_header->ahcich_prd_byte_count,
6890 6895 cmd_dmacount);
6891 6896
6892 6897 if (cmd_header->ahcich_prd_byte_count != cmd_dmacount) {
6893 6898 AHCIDBG(AHCIDBG_UNDERFLOW, ahci_ctlp,
6894 6899 "ahci_intr_cmd_cmplt: port %d, "
6895 6900 "an underflow occurred", port);
6896 6901 }
6897 6902 }
6898 6903 #endif
6899 6904
6900 6905 /*
6901 6906 * For SATAC_SMART command with SATA_SMART_RETURN_STATUS
6902 6907 * feature, sata_special_regs flag will be set, and the
6903 6908 * driver should copy the status and the other corresponding
6904 6909 * register values in the D2H Register FIS received (It's
6905 6910 * working on Non-data protocol) from the device back to
6906 6911 * the sata_cmd.
6907 6912 *
6908 6913 * For every AHCI port, there is only one Received FIS
6909 6914 * structure, which contains the FISes received from the
6910 6915 * device, So we're trying to copy the content of D2H
6911 6916 * Register FIS in the Received FIS structure back to
6912 6917 * the sata_cmd.
6913 6918 */
6914 6919 if (satapkt->satapkt_cmd.satacmd_flags.sata_special_regs) {
6915 6920 rcvd_fisp = &(ahci_portp->ahciport_rcvd_fis->
6916 6921 ahcirf_d2h_register_fis);
6917 6922 satapkt->satapkt_cmd.satacmd_status_reg =
6918 6923 GET_RFIS_STATUS(rcvd_fisp);
6919 6924 ahci_copy_out_regs(&satapkt->satapkt_cmd, rcvd_fisp);
6920 6925 }
6921 6926
6922 6927 AHCIDBG(AHCIDBG_INTR, ahci_ctlp,
6923 6928 "ahci_intr_cmd_cmplt: sending up pkt 0x%p "
6924 6929 "with SATA_PKT_COMPLETED", (void *)satapkt);
6925 6930
6926 6931 CLEAR_BIT(ahci_portp->ahciport_pending_tags, finished_slot);
6927 6932 CLEAR_BIT(finished_tags, finished_slot);
6928 6933 ahci_portp->ahciport_slot_pkts[finished_slot] = NULL;
6929 6934
6930 6935 ahci_add_doneq(ahci_portp, satapkt, SATA_PKT_COMPLETED);
6931 6936 }
6932 6937 out:
6933 6938 AHCIDBG(AHCIDBG_PKTCOMP, ahci_ctlp,
6934 6939 "ahci_intr_cmd_cmplt: pending_tags = 0x%x",
6935 6940 ahci_portp->ahciport_pending_tags);
6936 6941
6937 6942 ahci_flush_doneq(ahci_portp);
6938 6943
6939 6944 mutex_exit(&ahci_portp->ahciport_mutex);
6940 6945
6941 6946 return (AHCI_SUCCESS);
6942 6947 }
6943 6948
6944 6949 /*
6945 6950 * AHCI_INTR_STATUS_SDBS means a Set Device Bits FIS has been received
6946 6951 * with the 'I' bit set and has been copied into system memory. It will
6947 6952 * be sent under the following situations:
6948 6953 *
6949 6954 * 1. NCQ command is completed
6950 6955 *
6951 6956 * The completion of NCQ commands (READ/WRITE FPDMA QUEUED) is performed
6952 6957 * via the Set Device Bits FIS. When such event is generated, the software
6953 6958 * needs to read PxSACT register and compares the current value to the
6954 6959 * list of commands previously issue by software. ahciport_pending_ncq_tags
6955 6960 * keeps the tags of previously issued commands.
6956 6961 *
6957 6962 * 2. Asynchronous Notification
6958 6963 *
6959 6964 * Asynchronous Notification is a feature in SATA spec 2.6.
6960 6965 *
6961 6966 * 1) ATAPI device will send a signal to the host when media is inserted or
6962 6967 * removed and avoids polling the device for media changes. The signal
6963 6968 * sent to the host is a Set Device Bits FIS with the 'I' and 'N' bits
6964 6969 * set to '1'. At the moment, it's not supported yet.
6965 6970 *
6966 6971 * 2) Port multiplier will send a signal to the host when a hot plug event
6967 6972 * has occured on a port multiplier port. It is used when command based
6968 6973 * switching is employed. This is handled by ahci_intr_pmult_sntf_events()
6969 6974 */
6970 6975 static int
6971 6976 ahci_intr_set_device_bits(ahci_ctl_t *ahci_ctlp,
6972 6977 ahci_port_t *ahci_portp, uint8_t port)
6973 6978 {
6974 6979 ahci_addr_t addr;
6975 6980
6976 6981 AHCIDBG(AHCIDBG_ENTRY|AHCIDBG_INTR, ahci_ctlp,
6977 6982 "ahci_intr_set_device_bits enter: port %d", port);
6978 6983
6979 6984 /* Initialize HBA port address */
6980 6985 AHCI_ADDR_SET_PORT(&addr, port);
6981 6986
6982 6987 /* NCQ plug handler */
6983 6988 (void) ahci_intr_ncq_events(ahci_ctlp, ahci_portp, &addr);
6984 6989
6985 6990 /* Check port multiplier's asynchronous notification events */
6986 6991 if (ahci_ctlp->ahcictl_cap & AHCI_CAP_SNTF) {
6987 6992 (void) ahci_intr_pmult_sntf_events(ahci_ctlp,
6988 6993 ahci_portp, port);
6989 6994 }
6990 6995
6991 6996 /* ATAPI events is not supported yet */
6992 6997
6993 6998 return (AHCI_SUCCESS);
6994 6999 }
6995 7000 /*
6996 7001 * NCQ interrupt handler. Called upon a NCQ command is completed.
6997 7002 * Only be called from ahci_intr_set_device_bits().
6998 7003 */
6999 7004 static int
7000 7005 ahci_intr_ncq_events(ahci_ctl_t *ahci_ctlp,
7001 7006 ahci_port_t *ahci_portp, ahci_addr_t *addrp)
7002 7007 {
7003 7008 uint32_t port_sactive;
7004 7009 uint32_t port_cmd_issue;
7005 7010 uint32_t issued_tags;
7006 7011 int issued_slot;
7007 7012 uint32_t finished_tags;
7008 7013 int finished_slot;
7009 7014 uint8_t port = addrp->aa_port;
7010 7015 sata_pkt_t *satapkt;
7011 7016
7012 7017 AHCIDBG(AHCIDBG_ENTRY|AHCIDBG_INTR|AHCIDBG_NCQ, ahci_ctlp,
7013 7018 "ahci_intr_set_device_bits enter: port %d", port);
7014 7019
7015 7020 mutex_enter(&ahci_portp->ahciport_mutex);
7016 7021 if (!NCQ_CMD_IN_PROGRESS(ahci_portp)) {
7017 7022 mutex_exit(&ahci_portp->ahciport_mutex);
7018 7023 return (AHCI_SUCCESS);
7019 7024 }
7020 7025
7021 7026 /*
7022 7027 * First the handler got which commands are finished by checking
7023 7028 * PxSACT register
7024 7029 */
7025 7030 port_sactive = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
7026 7031 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port));
7027 7032
7028 7033 finished_tags = ahci_portp->ahciport_pending_ncq_tags &
7029 7034 ~port_sactive & AHCI_NCQ_SLOT_MASK(ahci_portp);
7030 7035
7031 7036 AHCIDBG(AHCIDBG_INTR|AHCIDBG_NCQ, ahci_ctlp,
7032 7037 "ahci_intr_set_device_bits: port %d pending_ncq_tags = 0x%x "
7033 7038 "port_sactive = 0x%x", port,
7034 7039 ahci_portp->ahciport_pending_ncq_tags, port_sactive);
7035 7040
7036 7041 AHCIDBG(AHCIDBG_INTR|AHCIDBG_NCQ, ahci_ctlp,
7037 7042 "ahci_intr_set_device_bits: finished_tags = 0x%x", finished_tags);
7038 7043
7039 7044 /*
7040 7045 * For NCQ commands, the software can determine which command has
7041 7046 * already been transmitted to the device by checking PxCI register.
7042 7047 */
7043 7048 port_cmd_issue = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
7044 7049 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port));
7045 7050
7046 7051 issued_tags = ahci_portp->ahciport_pending_tags &
7047 7052 ~port_cmd_issue & AHCI_SLOT_MASK(ahci_ctlp);
7048 7053
7049 7054 /* If the PxSACT/PxCI corrupts, don't complete the NCQ commmands. */
7050 7055 if (ahci_check_acc_handle(ahci_ctlp->ahcictl_ahci_acc_handle)
7051 7056 != DDI_FM_OK) {
7052 7057 mutex_exit(&ahci_portp->ahciport_mutex);
7053 7058 return (AHCI_FAILURE);
7054 7059 }
7055 7060
7056 7061 AHCIDBG(AHCIDBG_INTR|AHCIDBG_NCQ, ahci_ctlp,
7057 7062 "ahci_intr_set_device_bits: port %d pending_tags = 0x%x "
7058 7063 "port_cmd_issue = 0x%x", port,
7059 7064 ahci_portp->ahciport_pending_tags, port_cmd_issue);
7060 7065
7061 7066 AHCIDBG(AHCIDBG_INTR|AHCIDBG_NCQ, ahci_ctlp,
7062 7067 "ahci_intr_set_device_bits: issued_tags = 0x%x", issued_tags);
7063 7068
7064 7069 /*
7065 7070 * Clear ahciport_pending_tags bit when the corresponding command
7066 7071 * is already sent down to the device.
7067 7072 */
7068 7073 while (issued_tags) {
7069 7074 issued_slot = ddi_ffs(issued_tags) - 1;
7070 7075 if (issued_slot == -1) {
7071 7076 goto next;
7072 7077 }
7073 7078 CLEAR_BIT(ahci_portp->ahciport_pending_tags, issued_slot);
7074 7079 CLEAR_BIT(issued_tags, issued_slot);
7075 7080 }
7076 7081
7077 7082 next:
7078 7083 while (finished_tags) {
7079 7084 finished_slot = ddi_ffs(finished_tags) - 1;
7080 7085 if (finished_slot == -1) {
7081 7086 goto out;
7082 7087 }
7083 7088
7084 7089 /* The command is certainly transmitted to the device */
7085 7090 ASSERT(!(ahci_portp->ahciport_pending_tags &
7086 7091 (0x1 << finished_slot)));
7087 7092
7088 7093 satapkt = ahci_portp->ahciport_slot_pkts[finished_slot];
7089 7094 ASSERT(satapkt != NULL);
7090 7095
7091 7096 AHCIDBG(AHCIDBG_INTR|AHCIDBG_NCQ, ahci_ctlp,
7092 7097 "ahci_intr_set_device_bits: sending up pkt 0x%p "
7093 7098 "with SATA_PKT_COMPLETED", (void *)satapkt);
7094 7099
7095 7100 CLEAR_BIT(ahci_portp->ahciport_pending_ncq_tags, finished_slot);
7096 7101 CLEAR_BIT(finished_tags, finished_slot);
7097 7102 ahci_portp->ahciport_slot_pkts[finished_slot] = NULL;
7098 7103
7099 7104 ahci_add_doneq(ahci_portp, satapkt, SATA_PKT_COMPLETED);
7100 7105 }
7101 7106 out:
7102 7107 AHCIDBG(AHCIDBG_PKTCOMP|AHCIDBG_NCQ, ahci_ctlp,
7103 7108 "ahci_intr_set_device_bits: port %d "
7104 7109 "pending_ncq_tags = 0x%x pending_tags = 0x%x",
7105 7110 port, ahci_portp->ahciport_pending_ncq_tags,
7106 7111 ahci_portp->ahciport_pending_tags);
7107 7112
7108 7113 ahci_flush_doneq(ahci_portp);
7109 7114
7110 7115 mutex_exit(&ahci_portp->ahciport_mutex);
7111 7116
7112 7117 return (AHCI_SUCCESS);
7113 7118 }
7114 7119
7115 7120 /*
7116 7121 * Port multiplier asynchronous notification event handler. Called upon a
7117 7122 * device is hot plugged/pulled.
7118 7123 *
7119 7124 * The async-notification event will only be recorded by ahcipmi_snotif_tags
7120 7125 * here and will be handled by ahci_probe_pmult().
7121 7126 *
7122 7127 * NOTE: called only from ahci_port_intr().
7123 7128 */
7124 7129 static int
7125 7130 ahci_intr_pmult_sntf_events(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp,
7126 7131 uint8_t port)
7127 7132 {
7128 7133 sata_device_t sdevice;
7129 7134
7130 7135 AHCIDBG(AHCIDBG_ENTRY|AHCIDBG_INTR, ahci_ctlp,
7131 7136 "ahci_intr_pmult_sntf_events enter: port %d ", port);
7132 7137
7133 7138 /* no hot-plug while attaching process */
7134 7139 mutex_enter(&ahci_ctlp->ahcictl_mutex);
7135 7140 if (ahci_ctlp->ahcictl_flags & AHCI_ATTACH) {
7136 7141 mutex_exit(&ahci_ctlp->ahcictl_mutex);
7137 7142 return (AHCI_SUCCESS);
7138 7143 }
7139 7144 mutex_exit(&ahci_ctlp->ahcictl_mutex);
7140 7145
7141 7146 mutex_enter(&ahci_portp->ahciport_mutex);
7142 7147 if (ahci_portp->ahciport_device_type != SATA_DTYPE_PMULT) {
7143 7148 mutex_exit(&ahci_portp->ahciport_mutex);
7144 7149 return (AHCI_SUCCESS);
7145 7150 }
7146 7151
7147 7152 ASSERT(ahci_portp->ahciport_pmult_info != NULL);
7148 7153
7149 7154 ahci_portp->ahciport_pmult_info->ahcipmi_snotif_tags =
7150 7155 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
7151 7156 (uint32_t *)AHCI_PORT_PxSNTF(ahci_ctlp, port));
7152 7157 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
7153 7158 (uint32_t *)AHCI_PORT_PxSNTF(ahci_ctlp, port),
7154 7159 AHCI_SNOTIF_CLEAR_ALL);
7155 7160
7156 7161 if (ahci_portp->ahciport_pmult_info->ahcipmi_snotif_tags == 0) {
7157 7162 mutex_exit(&ahci_portp->ahciport_mutex);
7158 7163 return (AHCI_SUCCESS);
7159 7164 }
7160 7165
7161 7166 /* Port Multiplier sub-device hot-plug handler */
7162 7167 if (RDWR_PMULT_CMD_IN_PROGRESS(ahci_portp)) {
7163 7168 mutex_exit(&ahci_portp->ahciport_mutex);
7164 7169 return (AHCI_SUCCESS);
7165 7170 }
7166 7171
7167 7172 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_PMULT_SNTF) {
7168 7173 /* Not allowed to re-enter. */
7169 7174 mutex_exit(&ahci_portp->ahciport_mutex);
7170 7175 return (AHCI_SUCCESS);
7171 7176 }
7172 7177
7173 7178 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_PMULT_SNTF;
7174 7179
7175 7180 /*
7176 7181 * NOTE:
7177 7182 * Even if Asynchronous Notification is supported (and enabled) by
7178 7183 * both controller and the port multiplier, the content of PxSNTF
7179 7184 * register is always set to 0x8000 by async notification event. We
7180 7185 * need to check GSCR[32] on the port multiplier to find out the
7181 7186 * owner of this event.
7182 7187 * This is not accord with SATA spec 2.6 and needs further
7183 7188 * clarification.
7184 7189 */
7185 7190 /* hot-plug will not reported while reseting. */
7186 7191 if (ahci_portp->ahciport_reset_in_progress == 1) {
7187 7192 AHCIDBG(AHCIDBG_INFO|AHCIDBG_PMULT, ahci_ctlp,
7188 7193 "port %d snotif event ignored", port);
7189 7194 ahci_portp->ahciport_flags &= ~AHCI_PORT_FLAG_PMULT_SNTF;
7190 7195 mutex_exit(&ahci_portp->ahciport_mutex);
7191 7196 return (AHCI_SUCCESS);
7192 7197 }
7193 7198
7194 7199 AHCIDBG(AHCIDBG_INFO|AHCIDBG_PMULT, ahci_ctlp,
7195 7200 "PxSNTF is set to 0x%x by port multiplier",
7196 7201 ahci_portp->ahciport_pmult_info->ahcipmi_snotif_tags);
7197 7202
7198 7203 /*
7199 7204 * Now we need do some necessary operation and inform SATA framework
7200 7205 * that link/device events has happened.
7201 7206 */
7202 7207 bzero((void *)&sdevice, sizeof (sata_device_t));
7203 7208 sdevice.satadev_addr.cport = ahci_ctlp->
7204 7209 ahcictl_port_to_cport[port];
7205 7210 sdevice.satadev_addr.pmport = SATA_PMULT_HOSTPORT;
7206 7211 sdevice.satadev_addr.qual = SATA_ADDR_PMULT;
7207 7212 sdevice.satadev_state = SATA_PSTATE_PWRON;
7208 7213
7209 7214 /* Just reject packets, do not stop that port. */
7210 7215 ahci_reject_all_abort_pkts(ahci_ctlp, ahci_portp, port);
7211 7216
7212 7217 mutex_exit(&ahci_portp->ahciport_mutex);
7213 7218 sata_hba_event_notify(
7214 7219 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip,
7215 7220 &sdevice,
7216 7221 SATA_EVNT_PMULT_LINK_CHANGED);
7217 7222 mutex_enter(&ahci_portp->ahciport_mutex);
7218 7223
7219 7224 ahci_portp->ahciport_flags &= ~AHCI_PORT_FLAG_PMULT_SNTF;
7220 7225 mutex_exit(&ahci_portp->ahciport_mutex);
7221 7226
7222 7227 return (AHCI_SUCCESS);
7223 7228 }
7224 7229
7225 7230 /*
7226 7231 * 1=Change in Current Connect Status. 0=No change in Current Connect Status.
7227 7232 * This bit reflects the state of PxSERR.DIAG.X. This bit is only cleared
7228 7233 * when PxSERR.DIAG.X is cleared. When PxSERR.DIAG.X is set to one, it
7229 7234 * indicates a COMINIT signal was received.
7230 7235 *
7231 7236 * Hot plug insertion is detected by reception of a COMINIT signal from the
7232 7237 * device. On reception of unsolicited COMINIT, the HBA shall generate a
7233 7238 * COMRESET. If the COMINIT is in responce to a COMRESET, then the HBA shall
7234 7239 * begin the normal communication negotiation sequence as outlined in the
7235 7240 * Serial ATA 1.0a specification. When a COMRESET is sent to the device the
7236 7241 * PxSSTS.DET field shall be cleared to 0h. When a COMINIT is received, the
7237 7242 * PxSSTS.DET field shall be set to 1h. When the communication negotiation
7238 7243 * sequence is complete and PhyRdy is true the PxSSTS.DET field shall be set
7239 7244 * to 3h. Therefore, at the moment the ahci driver is going to check PhyRdy
7240 7245 * to handle hot plug insertion. In this interrupt handler, just do nothing
7241 7246 * but print some log message and clear the bit.
7242 7247 */
7243 7248 static int
7244 7249 ahci_intr_port_connect_change(ahci_ctl_t *ahci_ctlp,
7245 7250 ahci_port_t *ahci_portp, uint8_t port)
7246 7251 {
7247 7252 #if AHCI_DEBUG
7248 7253 uint32_t port_serror;
7249 7254 #endif
7250 7255
7251 7256 mutex_enter(&ahci_portp->ahciport_mutex);
7252 7257
7253 7258 #if AHCI_DEBUG
7254 7259 port_serror = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
7255 7260 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port));
7256 7261
7257 7262 AHCIDBG(AHCIDBG_INTR|AHCIDBG_ENTRY, ahci_ctlp,
7258 7263 "ahci_intr_port_connect_change: port %d, "
7259 7264 "port_serror = 0x%x", port, port_serror);
7260 7265 #endif
7261 7266
7262 7267 /* Clear PxSERR.DIAG.X to clear the interrupt bit */
7263 7268 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
7264 7269 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port),
7265 7270 SERROR_EXCHANGED_ERR);
7266 7271
7267 7272 mutex_exit(&ahci_portp->ahciport_mutex);
7268 7273
7269 7274 return (AHCI_SUCCESS);
7270 7275 }
7271 7276
7272 7277 /*
7273 7278 * Hot Plug Operation for platforms that support Mechanical Presence
7274 7279 * Switches.
7275 7280 *
7276 7281 * When set, it indicates that a mechanical presence switch attached to this
7277 7282 * port has been opened or closed, which may lead to a change in the connection
7278 7283 * state of the device. This bit is only valid if both CAP.SMPS and PxCMD.MPSP
7279 7284 * are set to '1'.
7280 7285 *
7281 7286 * At the moment, this interrupt is not needed and disabled and we just log
7282 7287 * the debug message.
7283 7288 */
7284 7289 static int
7285 7290 ahci_intr_device_mechanical_presence_status(ahci_ctl_t *ahci_ctlp,
7286 7291 ahci_port_t *ahci_portp, uint8_t port)
7287 7292 {
7288 7293 uint32_t cap_status, port_cmd_status;
7289 7294
7290 7295 AHCIDBG(AHCIDBG_INTR|AHCIDBG_ENTRY, ahci_ctlp,
7291 7296 "ahci_intr_device_mechanical_presence_status enter, "
7292 7297 "port %d", port);
7293 7298
7294 7299 cap_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
7295 7300 (uint32_t *)AHCI_GLOBAL_CAP(ahci_ctlp));
7296 7301
7297 7302 mutex_enter(&ahci_portp->ahciport_mutex);
7298 7303 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
7299 7304 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port));
7300 7305
7301 7306 if (!(cap_status & AHCI_HBA_CAP_SMPS) ||
7302 7307 !(port_cmd_status & AHCI_CMD_STATUS_MPSP)) {
7303 7308 AHCIDBG(AHCIDBG_INTR, ahci_ctlp,
7304 7309 "CAP.SMPS or PxCMD.MPSP is not set, so just ignore "
7305 7310 "the interrupt: cap_status = 0x%x, "
7306 7311 "port_cmd_status = 0x%x", cap_status, port_cmd_status);
7307 7312 mutex_exit(&ahci_portp->ahciport_mutex);
7308 7313
7309 7314 return (AHCI_SUCCESS);
7310 7315 }
7311 7316
7312 7317 #if AHCI_DEBUG
7313 7318 if (port_cmd_status & AHCI_CMD_STATUS_MPSS) {
7314 7319 AHCIDBG(AHCIDBG_INTR, ahci_ctlp,
7315 7320 "The mechanical presence switch is open: "
7316 7321 "port %d, port_cmd_status = 0x%x",
7317 7322 port, port_cmd_status);
7318 7323 } else {
7319 7324 AHCIDBG(AHCIDBG_INTR, ahci_ctlp,
7320 7325 "The mechanical presence switch is close: "
7321 7326 "port %d, port_cmd_status = 0x%x",
7322 7327 port, port_cmd_status);
7323 7328 }
7324 7329 #endif
7325 7330
7326 7331 mutex_exit(&ahci_portp->ahciport_mutex);
7327 7332
7328 7333 return (AHCI_SUCCESS);
7329 7334 }
7330 7335
7331 7336 /*
7332 7337 * Native Hot Plug Support.
7333 7338 *
7334 7339 * When set, it indicates that the internal PHYRDY signal changed state.
7335 7340 * This bit reflects the state of PxSERR.DIAG.N.
7336 7341 *
7337 7342 * There are three kinds of conditions to generate this interrupt event:
7338 7343 * 1. a device is inserted
7339 7344 * 2. a device is disconnected
7340 7345 * 3. when the link enters/exits a Partial or Slumber interface power
7341 7346 * management state
7342 7347 *
7343 7348 * If inteface power management is enabled for a port, the PxSERR.DIAG.N
7344 7349 * bit may be set due to the link entering the Partial or Slumber power
7345 7350 * management state, rather than due to a hot plug insertion or removal
7346 7351 * event. So far, the interface power management is disabled, so the
7347 7352 * driver can reliably get removal detection notification via the
7348 7353 * PxSERR.DIAG.N bit.
7349 7354 */
7350 7355 static int
7351 7356 ahci_intr_phyrdy_change(ahci_ctl_t *ahci_ctlp,
7352 7357 ahci_port_t *ahci_portp, uint8_t port)
7353 7358 {
7354 7359 uint32_t port_sstatus = 0; /* No dev present & PHY not established. */
7355 7360 sata_device_t sdevice;
7356 7361 int dev_exists_now = 0;
7357 7362 int dev_existed_previously = 0;
7358 7363 ahci_addr_t port_addr;
7359 7364
7360 7365 AHCIDBG(AHCIDBG_INTR|AHCIDBG_ENTRY, ahci_ctlp,
7361 7366 "ahci_intr_phyrdy_change enter, port %d", port);
7362 7367
7363 7368 /* Clear PxSERR.DIAG.N to clear the interrupt bit */
7364 7369 mutex_enter(&ahci_portp->ahciport_mutex);
7365 7370 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
7366 7371 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port),
7367 7372 SERROR_PHY_RDY_CHG);
7368 7373 mutex_exit(&ahci_portp->ahciport_mutex);
7369 7374
7370 7375 mutex_enter(&ahci_ctlp->ahcictl_mutex);
7371 7376 if ((ahci_ctlp->ahcictl_sata_hba_tran == NULL) ||
7372 7377 (ahci_portp == NULL)) {
7373 7378 /* The whole controller setup is not yet done. */
7374 7379 mutex_exit(&ahci_ctlp->ahcictl_mutex);
7375 7380 return (AHCI_SUCCESS);
7376 7381 }
7377 7382 mutex_exit(&ahci_ctlp->ahcictl_mutex);
7378 7383
7379 7384 mutex_enter(&ahci_portp->ahciport_mutex);
7380 7385
7381 7386 /* SStatus tells the presence of device. */
7382 7387 port_sstatus = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
7383 7388 (uint32_t *)AHCI_PORT_PxSSTS(ahci_ctlp, port));
7384 7389
7385 7390 if (SSTATUS_GET_DET(port_sstatus) == SSTATUS_DET_DEVPRE_PHYCOM) {
7386 7391 dev_exists_now = 1;
7387 7392 }
7388 7393
7389 7394 if (ahci_portp->ahciport_device_type != SATA_DTYPE_NONE) {
7390 7395 dev_existed_previously = 1;
7391 7396 }
7392 7397
7393 7398 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_NODEV) {
7394 7399 ahci_portp->ahciport_flags &= ~AHCI_PORT_FLAG_NODEV;
7395 7400 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
7396 7401 "ahci_intr_phyrdy_change: port %d "
7397 7402 "AHCI_PORT_FLAG_NODEV is cleared", port);
7398 7403 if (dev_exists_now == 0)
7399 7404 dev_existed_previously = 1;
7400 7405 }
7401 7406
7402 7407 bzero((void *)&sdevice, sizeof (sata_device_t));
7403 7408 sdevice.satadev_addr.cport = ahci_ctlp->ahcictl_port_to_cport[port];
7404 7409 sdevice.satadev_addr.qual = SATA_ADDR_CPORT;
7405 7410 sdevice.satadev_addr.pmport = 0;
7406 7411 sdevice.satadev_state = SATA_PSTATE_PWRON;
7407 7412 ahci_portp->ahciport_port_state = SATA_PSTATE_PWRON;
7408 7413
7409 7414 AHCI_ADDR_SET_PORT(&port_addr, port);
7410 7415
7411 7416 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_HOTPLUG;
7412 7417 if (dev_exists_now) {
7413 7418 if (dev_existed_previously) { /* 1 -> 1 */
7414 7419 /* Things are fine now. The loss was temporary. */
7415 7420 AHCIDBG(AHCIDBG_EVENT, ahci_ctlp,
7416 7421 "ahci_intr_phyrdy_change port %d "
7417 7422 "device link lost/established", port);
7418 7423
7419 7424 mutex_exit(&ahci_portp->ahciport_mutex);
7420 7425 sata_hba_event_notify(
7421 7426 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip,
7422 7427 &sdevice,
7423 7428 SATA_EVNT_LINK_LOST|SATA_EVNT_LINK_ESTABLISHED);
7424 7429 mutex_enter(&ahci_portp->ahciport_mutex);
7425 7430
7426 7431 } else { /* 0 -> 1 */
7427 7432 AHCIDBG(AHCIDBG_EVENT, ahci_ctlp,
7428 7433 "ahci_intr_phyrdy_change: port %d "
7429 7434 "device link established", port);
7430 7435
7431 7436 /*
7432 7437 * A new device has been detected. The new device
7433 7438 * might be a port multiplier instead of a drive, so
7434 7439 * we cannot update the signature directly.
7435 7440 */
7436 7441 (void) ahci_initialize_port(ahci_ctlp,
7437 7442 ahci_portp, &port_addr);
7438 7443
7439 7444 /* Try to start the port */
7440 7445 if (ahci_start_port(ahci_ctlp, ahci_portp, port)
7441 7446 != AHCI_SUCCESS) {
7442 7447 sdevice.satadev_state |= SATA_PSTATE_FAILED;
7443 7448 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
7444 7449 "ahci_intr_phyrdy_change: port %d failed "
7445 7450 "at start port", port);
7446 7451 }
7447 7452
7448 7453 /* Clear the max queue depth for inserted device */
7449 7454 ahci_portp->ahciport_max_ncq_tags = 0;
7450 7455
7451 7456 mutex_exit(&ahci_portp->ahciport_mutex);
7452 7457 sata_hba_event_notify(
7453 7458 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip,
7454 7459 &sdevice,
7455 7460 SATA_EVNT_LINK_ESTABLISHED);
7456 7461 mutex_enter(&ahci_portp->ahciport_mutex);
7457 7462
7458 7463 }
7459 7464 } else { /* No device exists now */
7460 7465
7461 7466 if (dev_existed_previously) { /* 1 -> 0 */
7462 7467 AHCIDBG(AHCIDBG_EVENT, ahci_ctlp,
7463 7468 "ahci_intr_phyrdy_change: port %d "
7464 7469 "device link lost", port);
7465 7470
7466 7471 ahci_reject_all_abort_pkts(ahci_ctlp, ahci_portp, port);
7467 7472 (void) ahci_put_port_into_notrunning_state(ahci_ctlp,
7468 7473 ahci_portp, port);
7469 7474
7470 7475 if (ahci_portp->ahciport_device_type ==
7471 7476 SATA_DTYPE_PMULT) {
7472 7477 ahci_dealloc_pmult(ahci_ctlp, ahci_portp);
7473 7478 }
7474 7479
7475 7480 /* An existing device is lost. */
7476 7481 ahci_portp->ahciport_device_type = SATA_DTYPE_NONE;
7477 7482 ahci_portp->ahciport_port_state = SATA_STATE_UNKNOWN;
7478 7483
7479 7484 mutex_exit(&ahci_portp->ahciport_mutex);
7480 7485 sata_hba_event_notify(
7481 7486 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip,
7482 7487 &sdevice,
7483 7488 SATA_EVNT_LINK_LOST);
7484 7489 mutex_enter(&ahci_portp->ahciport_mutex);
7485 7490 }
7486 7491 }
7487 7492 ahci_portp->ahciport_flags &= ~AHCI_PORT_FLAG_HOTPLUG;
7488 7493
7489 7494 mutex_exit(&ahci_portp->ahciport_mutex);
7490 7495
7491 7496 return (AHCI_SUCCESS);
7492 7497 }
7493 7498
7494 7499 /*
7495 7500 * PxIS.UFS - Unknown FIS Error
7496 7501 *
7497 7502 * This interrupt event means an unknown FIS was received and has been
7498 7503 * copied into system memory. An unknown FIS is not considered an illegal
7499 7504 * FIS, unless the length received is more than 64 bytes. If an unknown
7500 7505 * FIS arrives with length <= 64 bytes, it is posted and the HBA continues
7501 7506 * normal operation. If the unknown FIS is more than 64 bytes, then it
7502 7507 * won't be posted to memory and PxSERR.ERR.P will be set, which is then
7503 7508 * a fatal error.
7504 7509 *
7505 7510 * PxIS.IPMS - Incorrect Port Multiplier Status
7506 7511 *
7507 7512 * IPMS Indicates that the HBA received a FIS from a device that did not
7508 7513 * have a command outstanding. The IPMS bit may be set during enumeration
7509 7514 * of devices on a Port Multiplier due to the normal Port Multiplier
7510 7515 * enumeration process. It is recommended that IPMS only be used after
7511 7516 * enumeration is complete on the Port Multiplier (copied from spec).
7512 7517 *
7513 7518 * PxIS.OFS - Overflow Error
7514 7519 *
7515 7520 * Command list overflow is defined as software building a command table
7516 7521 * that has fewer total bytes than the transaction given to the device.
7517 7522 * On device writes, the HBA will run out of data, and on reads, there
7518 7523 * will be no room to put the data.
7519 7524 *
7520 7525 * For an overflow on data read, either PIO or DMA, the HBA will set
7521 7526 * PxIS.OFS, and the HBA will do a best effort to continue, and it's a
7522 7527 * non-fatal error when the HBA can continues. Sometimes, it will cause
7523 7528 * a fatal error and need the software to do something.
7524 7529 *
7525 7530 * For an overflow on data write, setting PxIS.OFS is optional for both
7526 7531 * DMA and PIO, and it's a fatal error, and a COMRESET is required by
7527 7532 * software to clean up from this serious error.
7528 7533 *
7529 7534 * PxIS.INFS - Interface Non-Fatal Error
7530 7535 *
7531 7536 * This interrupt event indicates that the HBA encountered an error on
7532 7537 * the Serial ATA interface but was able to continue operation. The kind
7533 7538 * of error usually occurred during a non-Data FIS, and under this condition
7534 7539 * the FIS will be re-transmitted by HBA automatically.
7535 7540 *
7536 7541 * When the FMA is implemented, there should be a stat structure to
7537 7542 * record how many every kind of error happens.
7538 7543 */
7539 7544 static int
7540 7545 ahci_intr_non_fatal_error(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp,
7541 7546 uint8_t port, uint32_t intr_status)
7542 7547 {
7543 7548 uint32_t port_serror;
7544 7549 #if AHCI_DEBUG
7545 7550 uint32_t port_cmd_status;
7546 7551 uint32_t port_cmd_issue;
7547 7552 uint32_t port_sactive;
7548 7553 int current_slot;
7549 7554 uint32_t current_tags;
7550 7555 sata_pkt_t *satapkt;
7551 7556 ahci_cmd_header_t *cmd_header;
7552 7557 uint32_t cmd_dmacount;
7553 7558 #endif
7554 7559
7555 7560 mutex_enter(&ahci_portp->ahciport_mutex);
7556 7561
7557 7562 port_serror = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
7558 7563 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port));
7559 7564
7560 7565 AHCIDBG(AHCIDBG_INTR|AHCIDBG_ENTRY|AHCIDBG_ERRS, ahci_ctlp,
7561 7566 "ahci_intr_non_fatal_error: port %d, "
7562 7567 "PxSERR = 0x%x, PxIS = 0x%x ", port, port_serror, intr_status);
7563 7568
7564 7569 ahci_log_serror_message(ahci_ctlp, port, port_serror, 1);
7565 7570
7566 7571 if (intr_status & AHCI_INTR_STATUS_UFS) {
7567 7572 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
7568 7573 "ahci port %d has unknown FIS error", port);
7569 7574
7570 7575 /* Clear the interrupt bit by clearing PxSERR.DIAG.F */
7571 7576 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
7572 7577 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port),
7573 7578 SERROR_FIS_TYPE);
7574 7579 }
7575 7580
7576 7581 #if AHCI_DEBUG
7577 7582 if (intr_status & AHCI_INTR_STATUS_IPMS) {
7578 7583 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp, "ahci port %d "
7579 7584 "has Incorrect Port Multiplier Status error", port);
7580 7585 }
7581 7586
7582 7587 if (intr_status & AHCI_INTR_STATUS_OFS) {
7583 7588 AHCIDBG(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp,
7584 7589 "ahci port %d has overflow error", port);
7585 7590 }
7586 7591
7587 7592 if (intr_status & AHCI_INTR_STATUS_INFS) {
7588 7593 AHCIDBG(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp,
7589 7594 "ahci port %d has interface non fatal error", port);
7590 7595 }
7591 7596
7592 7597 /*
7593 7598 * Record the error occurred command's slot.
7594 7599 */
7595 7600 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp) ||
7596 7601 ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) {
7597 7602 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
7598 7603 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port));
7599 7604
7600 7605 current_slot = (port_cmd_status & AHCI_CMD_STATUS_CCS) >>
7601 7606 AHCI_CMD_STATUS_CCS_SHIFT;
7602 7607
7603 7608 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) {
7604 7609 satapkt = ahci_portp->ahciport_err_retri_pkt;
7605 7610 ASSERT(satapkt != NULL);
7606 7611 ASSERT(current_slot == 0);
7607 7612 } else {
7608 7613 satapkt = ahci_portp->ahciport_slot_pkts[current_slot];
7609 7614 }
7610 7615
7611 7616 if (satapkt != NULL) {
7612 7617 AHCIDBG(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp,
7613 7618 "ahci_intr_non_fatal_error: pending_tags = 0x%x "
7614 7619 "cmd 0x%x", ahci_portp->ahciport_pending_tags,
7615 7620 satapkt->satapkt_cmd.satacmd_cmd_reg);
7616 7621
7617 7622 AHCIDBG(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp,
7618 7623 "ahci_intr_non_fatal_error: port %d, "
7619 7624 "satapkt 0x%p is being processed when error occurs",
7620 7625 port, (void *)satapkt);
7621 7626
7622 7627 /*
7623 7628 * PRD Byte Count field of command header is not
7624 7629 * required to reflect the total number of bytes
7625 7630 * transferred when an overflow occurs, so here
7626 7631 * just log the value.
7627 7632 */
7628 7633 cmd_dmacount =
7629 7634 ahci_portp->ahciport_prd_bytecounts[current_slot];
7630 7635 if (cmd_dmacount) {
7631 7636 cmd_header = &ahci_portp->
7632 7637 ahciport_cmd_list[current_slot];
7633 7638 AHCIDBG(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp,
7634 7639 "ahci_intr_non_fatal_error: port %d, "
7635 7640 "PRD Byte Count = 0x%x, "
7636 7641 "ahciport_prd_bytecounts = 0x%x", port,
7637 7642 cmd_header->ahcich_prd_byte_count,
7638 7643 cmd_dmacount);
7639 7644 }
7640 7645 }
7641 7646 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) {
7642 7647 /*
7643 7648 * For queued command, list those command which have already
7644 7649 * been transmitted to the device and still not completed.
7645 7650 */
7646 7651 port_sactive = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
7647 7652 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port));
7648 7653
7649 7654 port_cmd_issue = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
7650 7655 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port));
7651 7656
7652 7657 AHCIDBG(AHCIDBG_INTR|AHCIDBG_NCQ|AHCIDBG_ERRS, ahci_ctlp,
7653 7658 "ahci_intr_non_fatal_error: pending_ncq_tags = 0x%x "
7654 7659 "port_sactive = 0x%x port_cmd_issue = 0x%x",
7655 7660 ahci_portp->ahciport_pending_ncq_tags,
7656 7661 port_sactive, port_cmd_issue);
7657 7662
7658 7663 current_tags = ahci_portp->ahciport_pending_ncq_tags &
7659 7664 port_sactive & ~port_cmd_issue &
7660 7665 AHCI_NCQ_SLOT_MASK(ahci_portp);
7661 7666
7662 7667 while (current_tags) {
7663 7668 current_slot = ddi_ffs(current_tags) - 1;
7664 7669 if (current_slot == -1) {
7665 7670 goto out;
7666 7671 }
7667 7672
7668 7673 satapkt = ahci_portp->ahciport_slot_pkts[current_slot];
7669 7674 AHCIDBG(AHCIDBG_INTR|AHCIDBG_NCQ|AHCIDBG_ERRS,
7670 7675 ahci_ctlp, "ahci_intr_non_fatal_error: "
7671 7676 "port %d, satapkt 0x%p is outstanding when "
7672 7677 "error occurs", port, (void *)satapkt);
7673 7678
7674 7679 CLEAR_BIT(current_tags, current_slot);
7675 7680 }
7676 7681 }
7677 7682 out:
7678 7683 #endif
7679 7684 mutex_exit(&ahci_portp->ahciport_mutex);
7680 7685
7681 7686 return (AHCI_SUCCESS);
7682 7687 }
7683 7688
7684 7689 /*
7685 7690 * According to the AHCI spec, the error types include system memory
7686 7691 * errors, interface errors, port multiplier errors, device errors,
7687 7692 * command list overflow, command list underflow, native command
7688 7693 * queuing tag errors and pio data transfer errors.
7689 7694 *
7690 7695 * System memory errors such as target abort, master abort, and parity
7691 7696 * may cause the host to stop, and they are serious errors and needed
7692 7697 * to be recovered with software intervention. When system software
7693 7698 * has given a pointer to the HBA that doesn't exist in physical memory,
7694 7699 * a master/target abort error occurs, and PxIS.HBFS will be set. A
7695 7700 * data error such as CRC or parity occurs, the HBA aborts the transfer
7696 7701 * (if necessary) and PxIS.HBDS will be set.
7697 7702 *
7698 7703 * Interface errors are errors that occur due to electrical issues on
7699 7704 * the interface, or protocol miscommunication between the device and
7700 7705 * HBA, and the respective PxSERR register bit will be set. And PxIS.IFS
7701 7706 * (fatal) or PxIS.INFS (non-fatal) will be set. The conditions that
7702 7707 * causes PxIS.IFS/PxIS.INFS to be set are
7703 7708 * 1. in PxSERR.ERR, P bit is set to '1'
7704 7709 * 2. in PxSERR.DIAG, C or H bit is set to '1'
7705 7710 * 3. PhyRdy drop unexpectly, N bit is set to '1'
7706 7711 * If the error occurred during a non-data FIS, the FIS must be
7707 7712 * retransmitted, and the error is non-fatal and PxIS.INFS is set. If
7708 7713 * the error occurred during a data FIS, the transfer will stop, so
7709 7714 * the error is fatal and PxIS.IFS is set.
7710 7715 *
7711 7716 * When a FIS arrives that updates the taskfile, the HBA checks to see
7712 7717 * if PxTFD.STS.ERR is set. If yes, PxIS.TFES will be set and the HBA
7713 7718 * stops processing any more commands.
7714 7719 *
7715 7720 * Command list overflow is defined as software building a command table
7716 7721 * that has fewer total bytes than the transaction given to the device.
7717 7722 * On device writes, the HBA will run out of data, and on reads, there
7718 7723 * will be no room to put the data. For an overflow on data read, either
7719 7724 * PIO or DMA, the HBA will set PxIS.OFS, and it's a non-fatal error.
7720 7725 * For an overflow on data write, setting PxIS.OFS is optional for both
7721 7726 * DMA and PIO, and a COMRESET is required by software to clean up from
7722 7727 * this serious error.
7723 7728 *
7724 7729 * Command list underflow is defined as software building a command
7725 7730 * table that has more total bytes than the transaction given to the
7726 7731 * device. For data writes, both PIO and DMA, the device will detect
7727 7732 * an error and end the transfer. And these errors are most likely going
7728 7733 * to be fatal errors that will cause the port to be restarted. For
7729 7734 * data reads, the HBA updates its PRD byte count, and may be
7730 7735 * able to continue normally, but is not required to. And The HBA is
7731 7736 * not required to detect underflow conditions for native command
7732 7737 * queuing command.
7733 7738 *
7734 7739 * The HBA does not actively check incoming DMA Setup FISes to ensure
7735 7740 * that the PxSACT register bit for that slot is set. Existing error
7736 7741 * mechanisms, such as host bus failure, or bad protocol, are used to
7737 7742 * recover from this case.
7738 7743 *
7739 7744 * In accordance with Serial ATA 1.0a, DATA FISes prior to the final
7740 7745 * DATA FIS must be an integral number of Dwords. If the HBA receives
7741 7746 * a request which is not an integral number of Dwords, the HBA
7742 7747 * set PxSERR.ERR.P to '1', set PxIS.IFS to '1' and stop running until
7743 7748 * software restarts the port. And the HBA ensures that the size
7744 7749 * of the DATA FIS received during a PIO command matches the size in
7745 7750 * the Transfer Cound field of the preceding PIO Setup FIS, if not, the
7746 7751 * HBA sets PxSERR.ERR.P to '1', set PxIS.IFS to '1', and then
7747 7752 * stop running until software restarts the port.
7748 7753 */
7749 7754 /*
7750 7755 * the fatal errors include PxIS.IFS, PxIS.HBDS, PxIS.HBFS and PxIS.TFES.
7751 7756 *
7752 7757 * PxIS.IFS indicates that the hba encountered an error on the serial ata
7753 7758 * interface which caused the transfer to stop.
7754 7759 *
7755 7760 * PxIS.HBDS indicates that the hba encountered a data error
7756 7761 * (uncorrectable ecc/parity) when reading from or writing to system memory.
7757 7762 *
7758 7763 * PxIS.HBFS indicates that the hba encountered a host bus error that it
7759 7764 * cannot recover from, such as a bad software pointer.
7760 7765 *
7761 7766 * PxIS.TFES is set whenever the status register is updated by the device
7762 7767 * and the error bit (bit 0) is set.
7763 7768 */
7764 7769 static int
7765 7770 ahci_intr_fatal_error(ahci_ctl_t *ahci_ctlp,
7766 7771 ahci_port_t *ahci_portp, uint8_t port, uint32_t intr_status)
7767 7772 {
7768 7773 uint32_t port_cmd_status;
7769 7774 uint32_t port_serror;
7770 7775 uint32_t task_file_status;
7771 7776 int failed_slot;
7772 7777 sata_pkt_t *spkt = NULL;
7773 7778 uint8_t err_byte;
7774 7779 ahci_event_arg_t *args;
7775 7780 int instance = ddi_get_instance(ahci_ctlp->ahcictl_dip);
7776 7781 uint32_t failed_tags = 0;
7777 7782 int task_fail_flag = 0, task_abort_flag = 0;
7778 7783 uint32_t slot_status;
7779 7784
7780 7785 mutex_enter(&ahci_portp->ahciport_mutex);
7781 7786
7782 7787 /*
7783 7788 * ahci_intr_phyrdy_change() may have rendered it to
7784 7789 * SATA_DTYPE_NONE.
7785 7790 */
7786 7791 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) {
7787 7792 AHCIDBG(AHCIDBG_ENTRY|AHCIDBG_INTR, ahci_ctlp,
7788 7793 "ahci_intr_fatal_error: port %d no device attached, "
7789 7794 "and just return without doing anything", port);
7790 7795 goto out0;
7791 7796 }
7792 7797
7793 7798 if (intr_status & AHCI_INTR_STATUS_TFES) {
7794 7799 task_file_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
7795 7800 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port));
7796 7801 AHCIDBG(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp,
7797 7802 "ahci_intr_fatal_error: port %d "
7798 7803 "task_file_status = 0x%x", port, task_file_status);
7799 7804 task_fail_flag = 1;
7800 7805
7801 7806 err_byte = (task_file_status & AHCI_TFD_ERR_MASK)
7802 7807 >> AHCI_TFD_ERR_SHIFT;
7803 7808 if (err_byte == SATA_ERROR_ABORT)
7804 7809 task_abort_flag = 1;
7805 7810 }
7806 7811
7807 7812 /*
7808 7813 * Here we just log the fatal error info in interrupt context.
7809 7814 * Misc recovery processing will be handled in task queue.
7810 7815 */
7811 7816 if (task_fail_flag == 1) {
7812 7817 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) {
7813 7818 /*
7814 7819 * Read PxCMD.CCS to determine the slot that the HBA
7815 7820 * was processing when the error occurred.
7816 7821 */
7817 7822 port_cmd_status = ddi_get32(
7818 7823 ahci_ctlp->ahcictl_ahci_acc_handle,
7819 7824 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port));
7820 7825 failed_slot = (port_cmd_status & AHCI_CMD_STATUS_CCS) >>
7821 7826 AHCI_CMD_STATUS_CCS_SHIFT;
7822 7827 failed_tags = 0x1 << failed_slot;
7823 7828
7824 7829 spkt = ahci_portp->ahciport_slot_pkts[failed_slot];
7825 7830 AHCIDBG(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp,
7826 7831 "ahci_intr_fatal_error: spkt 0x%p is being "
7827 7832 "processed when fatal error occurred for port %d",
7828 7833 spkt, port);
7829 7834
7830 7835 /*
7831 7836 * Won't emit the error message if it is an IDENTIFY
7832 7837 * DEVICE command sent to an ATAPI device.
7833 7838 */
7834 7839 if ((spkt != NULL) &&
7835 7840 (spkt->satapkt_cmd.satacmd_cmd_reg ==
7836 7841 SATAC_ID_DEVICE) &&
7837 7842 (task_abort_flag == 1))
7838 7843 goto out1;
7839 7844
7840 7845 /*
7841 7846 * Won't emit the error message if it is an ATAPI PACKET
7842 7847 * command
7843 7848 */
7844 7849 if ((spkt != NULL) &&
7845 7850 (spkt->satapkt_cmd.satacmd_cmd_reg == SATAC_PACKET))
7846 7851 goto out1;
7847 7852
7848 7853 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) {
7849 7854 slot_status = ddi_get32(
7850 7855 ahci_ctlp->ahcictl_ahci_acc_handle,
7851 7856 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port));
7852 7857 failed_tags = slot_status &
7853 7858 AHCI_NCQ_SLOT_MASK(ahci_portp);
7854 7859 }
7855 7860 }
7856 7861
7857 7862 /* print the fatal error type */
7858 7863 ahci_log_fatal_error_message(ahci_ctlp, port, intr_status);
7859 7864 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_ERRPRINT;
7860 7865
7861 7866 port_serror = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
7862 7867 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port));
7863 7868
7864 7869 /* print PxSERR related error message */
7865 7870 ahci_log_serror_message(ahci_ctlp, port, port_serror, 0);
7866 7871
7867 7872 /* print task file register value */
7868 7873 if (task_fail_flag == 1) {
7869 7874 cmn_err(CE_WARN, "!ahci%d: ahci port %d task_file_status "
7870 7875 "= 0x%x", instance, port, task_file_status);
7871 7876 if (task_abort_flag == 1) {
7872 7877 cmn_err(CE_WARN, "!ahci%d: the below command (s) on "
7873 7878 "port %d are aborted", instance, port);
7874 7879 ahci_dump_commands(ahci_ctlp, port, failed_tags);
7875 7880 }
7876 7881 }
7877 7882
7878 7883 out1:
7879 7884 /* Prepare the argument for the taskq */
7880 7885 args = ahci_portp->ahciport_event_args;
7881 7886 args->ahciea_ctlp = (void *)ahci_ctlp;
7882 7887 args->ahciea_portp = (void *)ahci_portp;
7883 7888 args->ahciea_event = intr_status;
7884 7889 AHCI_ADDR_SET_PORT((ahci_addr_t *)args->ahciea_addrp, port);
7885 7890
7886 7891 /* Start the taskq to handle error recovery */
7887 7892 if ((ddi_taskq_dispatch(ahci_portp->ahciport_event_taskq,
7888 7893 ahci_events_handler,
7889 7894 (void *)args, DDI_NOSLEEP)) != DDI_SUCCESS) {
7890 7895 ahci_portp->ahciport_flags &= ~AHCI_PORT_FLAG_ERRPRINT;
7891 7896 cmn_err(CE_WARN, "!ahci%d: start taskq for error recovery "
7892 7897 "port %d failed", instance, port);
7893 7898 }
7894 7899 out0:
7895 7900 mutex_exit(&ahci_portp->ahciport_mutex);
7896 7901
7897 7902 return (AHCI_SUCCESS);
7898 7903 }
7899 7904
7900 7905 /*
7901 7906 * Hot Plug Operation for platforms that support Cold Presence Detect.
7902 7907 *
7903 7908 * When set, a device status has changed as detected by the cold presence
7904 7909 * detect logic. This bit can either be set due to a non-connected port
7905 7910 * receiving a device, or a connected port having its device removed.
7906 7911 * This bit is only valid if the port supports cold presence detect as
7907 7912 * indicated by PxCMD.CPD set to '1'.
7908 7913 *
7909 7914 * At the moment, this interrupt is not needed and disabled and we just
7910 7915 * log the debug message.
7911 7916 */
7912 7917 static int
7913 7918 ahci_intr_cold_port_detect(ahci_ctl_t *ahci_ctlp,
7914 7919 ahci_port_t *ahci_portp, uint8_t port)
7915 7920 {
7916 7921 uint32_t port_cmd_status;
7917 7922 sata_device_t sdevice;
7918 7923
7919 7924 AHCIDBG(AHCIDBG_INTR, ahci_ctlp,
7920 7925 "ahci_intr_cold_port_detect enter, port %d", port);
7921 7926
7922 7927 mutex_enter(&ahci_portp->ahciport_mutex);
7923 7928
7924 7929 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
7925 7930 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port));
7926 7931 if (!(port_cmd_status & AHCI_CMD_STATUS_CPD)) {
7927 7932 AHCIDBG(AHCIDBG_INTR, ahci_ctlp,
7928 7933 "port %d does not support cold presence detect, so "
7929 7934 "we just ignore this interrupt", port);
7930 7935 mutex_exit(&ahci_portp->ahciport_mutex);
7931 7936 return (AHCI_SUCCESS);
7932 7937 }
7933 7938
7934 7939 AHCIDBG(AHCIDBG_INTR, ahci_ctlp,
7935 7940 "port %d device status has changed", port);
7936 7941
7937 7942 bzero((void *)&sdevice, sizeof (sata_device_t));
7938 7943 sdevice.satadev_addr.cport = ahci_ctlp->ahcictl_port_to_cport[port];
7939 7944 sdevice.satadev_addr.qual = SATA_ADDR_CPORT;
7940 7945 sdevice.satadev_addr.pmport = 0;
7941 7946 sdevice.satadev_state = SATA_PSTATE_PWRON;
7942 7947
7943 7948 if (port_cmd_status & AHCI_CMD_STATUS_CPS) {
7944 7949 AHCIDBG(AHCIDBG_INTR, ahci_ctlp,
7945 7950 "port %d: a device is hot plugged", port);
7946 7951 mutex_exit(&ahci_portp->ahciport_mutex);
7947 7952 sata_hba_event_notify(
7948 7953 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip,
7949 7954 &sdevice,
7950 7955 SATA_EVNT_DEVICE_ATTACHED);
7951 7956 mutex_enter(&ahci_portp->ahciport_mutex);
7952 7957
7953 7958 } else {
7954 7959 AHCIDBG(AHCIDBG_INTR, ahci_ctlp,
7955 7960 "port %d: a device is hot unplugged", port);
7956 7961 mutex_exit(&ahci_portp->ahciport_mutex);
7957 7962 sata_hba_event_notify(
7958 7963 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip,
7959 7964 &sdevice,
7960 7965 SATA_EVNT_DEVICE_DETACHED);
7961 7966 mutex_enter(&ahci_portp->ahciport_mutex);
7962 7967 }
7963 7968
7964 7969 mutex_exit(&ahci_portp->ahciport_mutex);
7965 7970
7966 7971 return (AHCI_SUCCESS);
7967 7972 }
7968 7973
7969 7974 /*
7970 7975 * Enable the interrupts for a particular port.
7971 7976 */
7972 7977 static void
7973 7978 ahci_enable_port_intrs(ahci_ctl_t *ahci_ctlp, uint8_t port)
7974 7979 {
7975 7980 ASSERT(MUTEX_HELD(&ahci_ctlp->ahcictl_ports[port]->ahciport_mutex));
7976 7981
7977 7982 AHCIDBG(AHCIDBG_ENTRY, ahci_ctlp,
7978 7983 "ahci_enable_port_intrs enter, port %d", port);
7979 7984
7980 7985 /*
7981 7986 * Clear port interrupt status before enabling interrupt
7982 7987 */
7983 7988 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
7984 7989 (uint32_t *)AHCI_PORT_PxIS(ahci_ctlp, port),
7985 7990 AHCI_PORT_INTR_MASK);
7986 7991
7987 7992 /*
7988 7993 * Clear the pending bit from IS.IPS
7989 7994 */
7990 7995 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
7991 7996 (uint32_t *)AHCI_GLOBAL_IS(ahci_ctlp), (1 << port));
7992 7997
7993 7998 /*
7994 7999 * Enable the following interrupts:
7995 8000 * Device to Host Register FIS Interrupt (DHRS)
7996 8001 * PIO Setup FIS Interrupt (PSS)
7997 8002 * Set Device Bits Interrupt (SDBS)
7998 8003 * Unknown FIS Interrupt (UFS)
7999 8004 * Port Connect Change Status (PCS)
8000 8005 * PhyRdy Change Status (PRCS)
8001 8006 * Overflow Status (OFS)
8002 8007 * Interface Non-fatal Error Status (INFS)
8003 8008 * Interface Fatal Error Status (IFS)
8004 8009 * Host Bus Data Error Status (HBDS)
8005 8010 * Host Bus Fatal Error Status (HBFS)
8006 8011 * Task File Error Status (TFES)
8007 8012 */
8008 8013 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
8009 8014 (uint32_t *)AHCI_PORT_PxIE(ahci_ctlp, port),
8010 8015 (AHCI_INTR_STATUS_DHRS |
8011 8016 AHCI_INTR_STATUS_PSS |
8012 8017 AHCI_INTR_STATUS_SDBS |
8013 8018 AHCI_INTR_STATUS_UFS |
8014 8019 AHCI_INTR_STATUS_DPS |
8015 8020 AHCI_INTR_STATUS_PCS |
8016 8021 AHCI_INTR_STATUS_PRCS |
8017 8022 AHCI_INTR_STATUS_OFS |
8018 8023 AHCI_INTR_STATUS_INFS |
8019 8024 AHCI_INTR_STATUS_IFS |
8020 8025 AHCI_INTR_STATUS_HBDS |
8021 8026 AHCI_INTR_STATUS_HBFS |
8022 8027 AHCI_INTR_STATUS_TFES));
8023 8028 }
8024 8029
8025 8030 /*
8026 8031 * Enable interrupts for all the ports.
8027 8032 */
8028 8033 static void
8029 8034 ahci_enable_all_intrs(ahci_ctl_t *ahci_ctlp)
8030 8035 {
8031 8036 uint32_t ghc_control;
8032 8037
8033 8038 ASSERT(MUTEX_HELD(&ahci_ctlp->ahcictl_mutex));
8034 8039
8035 8040 AHCIDBG(AHCIDBG_ENTRY, ahci_ctlp, "ahci_enable_all_intrs enter", NULL);
8036 8041
8037 8042 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
8038 8043 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp));
8039 8044
8040 8045 ghc_control |= AHCI_HBA_GHC_IE;
8041 8046
8042 8047 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
8043 8048 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp), ghc_control);
8044 8049 }
8045 8050
8046 8051 /*
8047 8052 * Disable interrupts for a particular port.
8048 8053 */
8049 8054 static void
8050 8055 ahci_disable_port_intrs(ahci_ctl_t *ahci_ctlp, uint8_t port)
8051 8056 {
8052 8057 ASSERT(ahci_ctlp->ahcictl_flags & AHCI_QUIESCE ||
8053 8058 MUTEX_HELD(&ahci_ctlp->ahcictl_ports[port]->ahciport_mutex));
8054 8059
8055 8060 AHCIDBG(AHCIDBG_ENTRY, ahci_ctlp,
8056 8061 "ahci_disable_port_intrs enter, port %d", port);
8057 8062
8058 8063 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
8059 8064 (uint32_t *)AHCI_PORT_PxIE(ahci_ctlp, port), 0);
8060 8065 }
8061 8066
8062 8067 /*
8063 8068 * Disable interrupts for the whole HBA.
8064 8069 *
8065 8070 * The global bit is cleared, then all interrupt sources from all
8066 8071 * ports are disabled.
8067 8072 */
8068 8073 static void
8069 8074 ahci_disable_all_intrs(ahci_ctl_t *ahci_ctlp)
8070 8075 {
8071 8076 uint32_t ghc_control;
8072 8077
8073 8078 ASSERT(ahci_ctlp->ahcictl_flags & (AHCI_ATTACH | AHCI_QUIESCE) ||
8074 8079 MUTEX_HELD(&ahci_ctlp->ahcictl_mutex));
8075 8080
8076 8081 AHCIDBG(AHCIDBG_ENTRY, ahci_ctlp, "ahci_disable_all_intrs enter",
8077 8082 NULL);
8078 8083
8079 8084 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
8080 8085 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp));
8081 8086
8082 8087 ghc_control &= ~AHCI_HBA_GHC_IE;
8083 8088
8084 8089 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
8085 8090 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp), ghc_control);
8086 8091 }
8087 8092
8088 8093 /*
8089 8094 * Handle FIXED or MSI interrupts.
8090 8095 */
8091 8096 /*
8092 8097 * According to AHCI spec, the HBA may support several interrupt modes:
8093 8098 * * pin based interrupts (FIXED)
8094 8099 * * single MSI message interrupts
8095 8100 * * multiple MSI based message interrupts
8096 8101 *
8097 8102 * For pin based interrupts, the software interrupt handler need to check IS
8098 8103 * register to find out which port has pending interrupts. And then check
8099 8104 * PxIS register to find out which interrupt events happened on that port.
8100 8105 *
8101 8106 * For single MSI message interrupts, MSICAP.MC.MSIE is set with '1', and
8102 8107 * MSICAP.MC.MME is set with '0'. This mode is similar to pin based interrupts
8103 8108 * in that software interrupt handler need to check IS register to determine
8104 8109 * which port triggered the interrupts since it uses a single message for all
8105 8110 * port interrupts.
8106 8111 *
8107 8112 * HBA may optionally support multiple MSI message for better performance. In
8108 8113 * this mode, each port may have its own interrupt message, and thus generation
8109 8114 * of interrupts is no longer controlled through the IS register. MSICAP.MC.MMC
8110 8115 * represents a power-of-2 wrapper on the number of implemented ports, and
8111 8116 * the mapping of ports to interrupts is done in a 1-1 relationship, up to the
8112 8117 * maximum number of assigned interrupts. When the number of MSI messages
8113 8118 * allocated is less than the number requested, then hardware may have two
8114 8119 * implementation behaviors:
8115 8120 * * assign each ports its own interrupt and then force all additional
8116 8121 * ports to share the last interrupt message, and this condition is
8117 8122 * indicated by clearing GHC.MRSM to '0'
8118 8123 * * revert to single MSI mode, indicated by setting GHC.MRSM to '1'
8119 8124 * When multiple-message MSI is enabled, hardware will still set IS register
8120 8125 * as single message case. And this IS register may be used by software when
8121 8126 * fewer than the requested number of messages is granted in order to determine
8122 8127 * which port had the interrupt.
8123 8128 *
8124 8129 * Note: The current ahci driver only supports the first two interrupt modes:
8125 8130 * pin based interrupts and single MSI message interrupts, and the reason
8126 8131 * is indicated in below code.
8127 8132 */
8128 8133 static int
8129 8134 ahci_add_intrs(ahci_ctl_t *ahci_ctlp, int intr_type)
8130 8135 {
8131 8136 dev_info_t *dip = ahci_ctlp->ahcictl_dip;
8132 8137 int count, avail, actual;
8133 8138 int i, rc;
8134 8139
8135 8140 AHCIDBG(AHCIDBG_ENTRY|AHCIDBG_INIT|AHCIDBG_INTR, ahci_ctlp,
8136 8141 "ahci_add_intrs enter interrupt type 0x%x", intr_type);
8137 8142
8138 8143 /* get number of interrupts. */
8139 8144 rc = ddi_intr_get_nintrs(dip, intr_type, &count);
8140 8145 if ((rc != DDI_SUCCESS) || (count == 0)) {
8141 8146 AHCIDBG(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp,
8142 8147 "ddi_intr_get_nintrs() failed, "
8143 8148 "rc %d count %d\n", rc, count);
8144 8149 return (DDI_FAILURE);
8145 8150 }
8146 8151
8147 8152 /* get number of available interrupts. */
8148 8153 rc = ddi_intr_get_navail(dip, intr_type, &avail);
8149 8154 if ((rc != DDI_SUCCESS) || (avail == 0)) {
8150 8155 AHCIDBG(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp,
8151 8156 "ddi_intr_get_navail() failed, "
8152 8157 "rc %d avail %d\n", rc, avail);
8153 8158 return (DDI_FAILURE);
8154 8159 }
8155 8160
8156 8161 #if AHCI_DEBUG
8157 8162 if (avail < count) {
8158 8163 AHCIDBG(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp,
8159 8164 "ddi_intr_get_nintrs returned %d, navail() returned %d",
8160 8165 count, avail);
8161 8166 }
8162 8167 #endif
8163 8168
8164 8169 /*
8165 8170 * Note: So far Solaris restricts the maximum number of messages for
8166 8171 * x86 to 2, that is avail is 2, so here we set the count with 1 to
8167 8172 * force the driver to use single MSI message interrupt. In future if
8168 8173 * Solaris remove the restriction, then we need to delete the below
8169 8174 * code and try to use multiple interrupt routine to gain better
8170 8175 * performance.
8171 8176 */
8172 8177 if ((intr_type == DDI_INTR_TYPE_MSI) && (count > 1)) {
8173 8178 AHCIDBG(AHCIDBG_INTR, ahci_ctlp,
8174 8179 "force to use one interrupt routine though the "
8175 8180 "HBA supports %d interrupt", count);
8176 8181 count = 1;
8177 8182 }
8178 8183
8179 8184 /* Allocate an array of interrupt handles. */
8180 8185 ahci_ctlp->ahcictl_intr_size = count * sizeof (ddi_intr_handle_t);
8181 8186 ahci_ctlp->ahcictl_intr_htable =
8182 8187 kmem_alloc(ahci_ctlp->ahcictl_intr_size, KM_SLEEP);
8183 8188
8184 8189 /* call ddi_intr_alloc(). */
8185 8190 rc = ddi_intr_alloc(dip, ahci_ctlp->ahcictl_intr_htable,
8186 8191 intr_type, 0, count, &actual, DDI_INTR_ALLOC_NORMAL);
8187 8192
8188 8193 if ((rc != DDI_SUCCESS) || (actual == 0)) {
8189 8194 AHCIDBG(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp,
8190 8195 "ddi_intr_alloc() failed, rc %d count %d actual %d "
8191 8196 "avail %d\n", rc, count, actual, avail);
8192 8197 kmem_free(ahci_ctlp->ahcictl_intr_htable,
8193 8198 ahci_ctlp->ahcictl_intr_size);
8194 8199 return (DDI_FAILURE);
8195 8200 }
8196 8201
8197 8202 /* use interrupt count returned */
8198 8203 #if AHCI_DEBUG
8199 8204 if (actual < count) {
8200 8205 AHCIDBG(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp,
8201 8206 "Requested: %d, Received: %d", count, actual);
8202 8207 }
8203 8208 #endif
8204 8209
8205 8210 ahci_ctlp->ahcictl_intr_cnt = actual;
8206 8211
8207 8212 /*
8208 8213 * Get priority for first, assume remaining are all the same.
8209 8214 */
8210 8215 if (ddi_intr_get_pri(ahci_ctlp->ahcictl_intr_htable[0],
8211 8216 &ahci_ctlp->ahcictl_intr_pri) != DDI_SUCCESS) {
8212 8217 AHCIDBG(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp,
8213 8218 "ddi_intr_get_pri() failed", NULL);
8214 8219
8215 8220 /* Free already allocated intr. */
8216 8221 for (i = 0; i < actual; i++) {
8217 8222 (void) ddi_intr_free(ahci_ctlp->ahcictl_intr_htable[i]);
8218 8223 }
8219 8224
8220 8225 kmem_free(ahci_ctlp->ahcictl_intr_htable,
8221 8226 ahci_ctlp->ahcictl_intr_size);
8222 8227 return (DDI_FAILURE);
8223 8228 }
8224 8229
8225 8230 /* Test for high level interrupt. */
8226 8231 if (ahci_ctlp->ahcictl_intr_pri >= ddi_intr_get_hilevel_pri()) {
8227 8232 AHCIDBG(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp,
8228 8233 "ahci_add_intrs: Hi level intr not supported", NULL);
8229 8234
8230 8235 /* Free already allocated intr. */
8231 8236 for (i = 0; i < actual; i++) {
8232 8237 (void) ddi_intr_free(ahci_ctlp->ahcictl_intr_htable[i]);
8233 8238 }
8234 8239
8235 8240 kmem_free(ahci_ctlp->ahcictl_intr_htable,
8236 8241 sizeof (ddi_intr_handle_t));
8237 8242
8238 8243 return (DDI_FAILURE);
8239 8244 }
8240 8245
8241 8246 /* Call ddi_intr_add_handler(). */
8242 8247 for (i = 0; i < actual; i++) {
8243 8248 if (ddi_intr_add_handler(ahci_ctlp->ahcictl_intr_htable[i],
8244 8249 ahci_intr, (caddr_t)ahci_ctlp, NULL) != DDI_SUCCESS) {
8245 8250 AHCIDBG(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp,
8246 8251 "ddi_intr_add_handler() failed", NULL);
8247 8252
8248 8253 /* Free already allocated intr. */
8249 8254 for (i = 0; i < actual; i++) {
8250 8255 (void) ddi_intr_free(
8251 8256 ahci_ctlp->ahcictl_intr_htable[i]);
8252 8257 }
8253 8258
8254 8259 kmem_free(ahci_ctlp->ahcictl_intr_htable,
8255 8260 ahci_ctlp->ahcictl_intr_size);
8256 8261 return (DDI_FAILURE);
8257 8262 }
8258 8263 }
8259 8264
8260 8265 if (ddi_intr_get_cap(ahci_ctlp->ahcictl_intr_htable[0],
8261 8266 &ahci_ctlp->ahcictl_intr_cap) != DDI_SUCCESS) {
8262 8267 AHCIDBG(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp,
8263 8268 "ddi_intr_get_cap() failed", NULL);
8264 8269
8265 8270 /* Free already allocated intr. */
8266 8271 for (i = 0; i < actual; i++) {
8267 8272 (void) ddi_intr_free(
8268 8273 ahci_ctlp->ahcictl_intr_htable[i]);
8269 8274 }
8270 8275
8271 8276 kmem_free(ahci_ctlp->ahcictl_intr_htable,
8272 8277 ahci_ctlp->ahcictl_intr_size);
8273 8278 return (DDI_FAILURE);
8274 8279 }
8275 8280
8276 8281 if (ahci_ctlp->ahcictl_intr_cap & DDI_INTR_FLAG_BLOCK) {
8277 8282 /* Call ddi_intr_block_enable() for MSI. */
8278 8283 (void) ddi_intr_block_enable(ahci_ctlp->ahcictl_intr_htable,
8279 8284 ahci_ctlp->ahcictl_intr_cnt);
8280 8285 } else {
8281 8286 /* Call ddi_intr_enable() for FIXED or MSI non block enable. */
8282 8287 for (i = 0; i < ahci_ctlp->ahcictl_intr_cnt; i++) {
8283 8288 (void) ddi_intr_enable(
8284 8289 ahci_ctlp->ahcictl_intr_htable[i]);
8285 8290 }
8286 8291 }
8287 8292
8288 8293 return (DDI_SUCCESS);
8289 8294 }
8290 8295
8291 8296 /*
8292 8297 * Removes the registered interrupts irrespective of whether they
8293 8298 * were legacy or MSI.
8294 8299 *
8295 8300 * NOTE: The controller interrupts must be disabled before calling
8296 8301 * this routine.
8297 8302 */
8298 8303 static void
8299 8304 ahci_rem_intrs(ahci_ctl_t *ahci_ctlp)
8300 8305 {
8301 8306 int x;
8302 8307
8303 8308 AHCIDBG(AHCIDBG_ENTRY, ahci_ctlp, "ahci_rem_intrs entered", NULL);
8304 8309
8305 8310 /* Disable all interrupts. */
8306 8311 if ((ahci_ctlp->ahcictl_intr_type == DDI_INTR_TYPE_MSI) &&
8307 8312 (ahci_ctlp->ahcictl_intr_cap & DDI_INTR_FLAG_BLOCK)) {
8308 8313 /* Call ddi_intr_block_disable(). */
8309 8314 (void) ddi_intr_block_disable(ahci_ctlp->ahcictl_intr_htable,
8310 8315 ahci_ctlp->ahcictl_intr_cnt);
8311 8316 } else {
8312 8317 for (x = 0; x < ahci_ctlp->ahcictl_intr_cnt; x++) {
8313 8318 (void) ddi_intr_disable(
8314 8319 ahci_ctlp->ahcictl_intr_htable[x]);
8315 8320 }
8316 8321 }
8317 8322
8318 8323 /* Call ddi_intr_remove_handler(). */
8319 8324 for (x = 0; x < ahci_ctlp->ahcictl_intr_cnt; x++) {
8320 8325 (void) ddi_intr_remove_handler(
8321 8326 ahci_ctlp->ahcictl_intr_htable[x]);
8322 8327 (void) ddi_intr_free(ahci_ctlp->ahcictl_intr_htable[x]);
8323 8328 }
8324 8329
8325 8330 kmem_free(ahci_ctlp->ahcictl_intr_htable, ahci_ctlp->ahcictl_intr_size);
8326 8331 }
8327 8332
8328 8333 /*
8329 8334 * This routine tries to put port into P:NotRunning state by clearing
8330 8335 * PxCMD.ST. HBA will clear PxCI to 0h, PxSACT to 0h, PxCMD.CCS to 0h
8331 8336 * and PxCMD.CR to '0'.
8332 8337 */
8333 8338 static int
8334 8339 ahci_put_port_into_notrunning_state(ahci_ctl_t *ahci_ctlp,
8335 8340 ahci_port_t *ahci_portp, uint8_t port)
8336 8341 {
8337 8342 uint32_t port_cmd_status;
8338 8343 int loop_count;
8339 8344
8340 8345 ASSERT(ahci_ctlp->ahcictl_flags & AHCI_QUIESCE ||
8341 8346 MUTEX_HELD(&ahci_ctlp->ahcictl_ports[port]->ahciport_mutex));
8342 8347
8343 8348 AHCIDBG(AHCIDBG_ENTRY, ahci_ctlp,
8344 8349 "ahci_put_port_into_notrunning_state enter: port %d", port);
8345 8350
8346 8351 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
8347 8352 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port));
8348 8353
8349 8354 port_cmd_status &= ~AHCI_CMD_STATUS_ST;
8350 8355 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
8351 8356 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), port_cmd_status);
8352 8357
8353 8358 /* Wait until PxCMD.CR is cleared */
8354 8359 loop_count = 0;
8355 8360 do {
8356 8361 port_cmd_status =
8357 8362 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
8358 8363 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port));
8359 8364
8360 8365 if (loop_count++ > AHCI_POLLRATE_PORT_IDLE) {
8361 8366 AHCIDBG(AHCIDBG_INIT, ahci_ctlp,
8362 8367 "clearing port %d CMD.CR timeout, "
8363 8368 "port_cmd_status = 0x%x", port,
8364 8369 port_cmd_status);
8365 8370 /*
8366 8371 * We are effectively timing out after 0.5 sec.
8367 8372 * This value is specified in AHCI spec.
8368 8373 */
8369 8374 break;
8370 8375 }
8371 8376
8372 8377 /* Wait for 10 millisec */
8373 8378 drv_usecwait(AHCI_10MS_USECS);
8374 8379 } while (port_cmd_status & AHCI_CMD_STATUS_CR);
8375 8380
8376 8381 ahci_portp->ahciport_flags &= ~AHCI_PORT_FLAG_STARTED;
8377 8382
8378 8383 if (port_cmd_status & AHCI_CMD_STATUS_CR) {
8379 8384 AHCIDBG(AHCIDBG_INIT|AHCIDBG_POLL_LOOP, ahci_ctlp,
8380 8385 "ahci_put_port_into_notrunning_state: failed to clear "
8381 8386 "PxCMD.CR to '0' after loop count: %d, and "
8382 8387 "port_cmd_status = 0x%x", loop_count, port_cmd_status);
8383 8388 return (AHCI_FAILURE);
8384 8389 } else {
8385 8390 AHCIDBG(AHCIDBG_INIT|AHCIDBG_POLL_LOOP, ahci_ctlp,
8386 8391 "ahci_put_port_into_notrunning_state: succeeded to clear "
8387 8392 "PxCMD.CR to '0' after loop count: %d, and "
8388 8393 "port_cmd_status = 0x%x", loop_count, port_cmd_status);
8389 8394 return (AHCI_SUCCESS);
8390 8395 }
8391 8396 }
8392 8397
8393 8398 /*
8394 8399 * First clear PxCMD.ST, and then check PxTFD. If both PxTFD.STS.BSY
8395 8400 * and PxTFD.STS.DRQ cleared to '0', it means the device is in a
8396 8401 * stable state, then set PxCMD.ST to '1' to start the port directly.
8397 8402 * If PxTFD.STS.BSY or PxTFD.STS.DRQ is set to '1', then issue a
8398 8403 * COMRESET to the device to put it in an idle state.
8399 8404 *
8400 8405 * The fifth argument returns whether the port reset is involved during
8401 8406 * the process.
8402 8407 *
8403 8408 * The routine will be called under following scenarios:
8404 8409 * + To reset the HBA
8405 8410 * + To abort the packet(s)
8406 8411 * + To reset the port
8407 8412 * + To activate the port
8408 8413 * + Fatal error recovery
8409 8414 * + To abort the timeout packet(s)
8410 8415 *
8411 8416 * NOTES!!! During this procedure, PxSERR register will be cleared, and
8412 8417 * according to the spec, the clearance of three bits will also clear
8413 8418 * three interrupt status bits.
8414 8419 * 1. PxSERR.DIAG.F will clear PxIS.UFS
8415 8420 * 2. PxSERR.DIAG.X will clear PxIS.PCS
8416 8421 * 3. PxSERR.DIAG.N will clear PxIS.PRCS
8417 8422 *
8418 8423 * Among these three interrupt events, the driver needs to take care of
8419 8424 * PxIS.PRCS, which is the hot plug event. When the driver found out
8420 8425 * a device was unplugged, it will call the interrupt handler.
8421 8426 */
8422 8427 static int
8423 8428 ahci_restart_port_wait_till_ready(ahci_ctl_t *ahci_ctlp,
8424 8429 ahci_port_t *ahci_portp, uint8_t port, int flag, int *reset_flag)
8425 8430 {
8426 8431 uint32_t port_sstatus;
8427 8432 uint32_t task_file_status;
8428 8433 sata_device_t sdevice;
8429 8434 int rval;
8430 8435 ahci_addr_t addr_port;
8431 8436 ahci_pmult_info_t *pminfo = NULL;
8432 8437 int dev_exists_begin = 0;
8433 8438 int dev_exists_end = 0;
8434 8439 uint32_t previous_dev_type = ahci_portp->ahciport_device_type;
8435 8440 int npmport = 0;
8436 8441 uint8_t cport = ahci_ctlp->ahcictl_port_to_cport[port];
8437 8442
8438 8443 ASSERT(MUTEX_HELD(&ahci_portp->ahciport_mutex));
8439 8444
8440 8445 AHCIDBG(AHCIDBG_ENTRY, ahci_ctlp,
8441 8446 "ahci_restart_port_wait_till_ready: port %d enter", port);
8442 8447
8443 8448 AHCI_ADDR_SET_PORT(&addr_port, port);
8444 8449
8445 8450 if (ahci_portp->ahciport_device_type != SATA_DTYPE_NONE)
8446 8451 dev_exists_begin = 1;
8447 8452
8448 8453 /* First clear PxCMD.ST */
8449 8454 rval = ahci_put_port_into_notrunning_state(ahci_ctlp, ahci_portp,
8450 8455 port);
8451 8456 if (rval != AHCI_SUCCESS)
8452 8457 /*
8453 8458 * If PxCMD.CR does not clear within a reasonable time, it
8454 8459 * may assume the interface is in a hung condition and may
8455 8460 * continue with issuing the port reset.
8456 8461 */
8457 8462 goto reset;
8458 8463
8459 8464 /* Then clear PxSERR */
8460 8465 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
8461 8466 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port),
8462 8467 AHCI_SERROR_CLEAR_ALL);
8463 8468
8464 8469 /* Then get PxTFD */
8465 8470 task_file_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
8466 8471 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port));
8467 8472
8468 8473 /*
8469 8474 * Check whether the device is in a stable status, if yes,
8470 8475 * then start the port directly. However for ahci_tran_reset_dport,
8471 8476 * we may have to perform a port reset.
8472 8477 */
8473 8478 if (!(task_file_status & (AHCI_TFD_STS_BSY | AHCI_TFD_STS_DRQ)) &&
8474 8479 !(flag & AHCI_PORT_RESET))
8475 8480 goto out;
8476 8481
8477 8482 reset:
8478 8483 /*
8479 8484 * If PxTFD.STS.BSY or PxTFD.STS.DRQ is set to '1', then issue
8480 8485 * a COMRESET to the device
8481 8486 */
8482 8487 ahci_disable_port_intrs(ahci_ctlp, port);
8483 8488 rval = ahci_port_reset(ahci_ctlp, ahci_portp, &addr_port);
8484 8489 ahci_enable_port_intrs(ahci_ctlp, port);
8485 8490
8486 8491 #ifdef AHCI_DEBUG
8487 8492 if (rval != AHCI_SUCCESS)
8488 8493 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
8489 8494 "ahci_restart_port_wait_till_ready: port %d failed",
8490 8495 port);
8491 8496 #endif
8492 8497
8493 8498 if (reset_flag != NULL)
8494 8499 *reset_flag = 1;
8495 8500
8496 8501 /* Indicate to the framework that a reset has happened. */
8497 8502 if ((ahci_portp->ahciport_device_type != SATA_DTYPE_NONE) &&
8498 8503 (ahci_portp->ahciport_device_type != SATA_DTYPE_PMULT) &&
8499 8504 !(flag & AHCI_RESET_NO_EVENTS_UP)) {
8500 8505 /* Set the reset in progress flag */
8501 8506 ahci_portp->ahciport_reset_in_progress = 1;
8502 8507
8503 8508 bzero((void *)&sdevice, sizeof (sata_device_t));
8504 8509 sdevice.satadev_addr.cport =
8505 8510 ahci_ctlp->ahcictl_port_to_cport[port];
8506 8511 sdevice.satadev_addr.pmport = 0;
8507 8512 sdevice.satadev_addr.qual = SATA_ADDR_DCPORT;
8508 8513
8509 8514 sdevice.satadev_state = SATA_DSTATE_RESET |
8510 8515 SATA_DSTATE_PWR_ACTIVE;
8511 8516 if (ahci_ctlp->ahcictl_sata_hba_tran) {
8512 8517 mutex_exit(&ahci_portp->ahciport_mutex);
8513 8518 sata_hba_event_notify(
8514 8519 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip,
8515 8520 &sdevice,
8516 8521 SATA_EVNT_DEVICE_RESET);
8517 8522 mutex_enter(&ahci_portp->ahciport_mutex);
8518 8523 }
8519 8524
8520 8525 AHCIDBG(AHCIDBG_EVENT, ahci_ctlp,
8521 8526 "port %d sending event up: SATA_EVNT_DEVICE_RESET", port);
8522 8527 } else {
8523 8528 ahci_portp->ahciport_reset_in_progress = 0;
8524 8529 }
8525 8530
8526 8531 out:
8527 8532 (void) ahci_start_port(ahci_ctlp, ahci_portp, port);
8528 8533
8529 8534 /* SStatus tells the presence of device. */
8530 8535 port_sstatus = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
8531 8536 (uint32_t *)AHCI_PORT_PxSSTS(ahci_ctlp, port));
8532 8537
8533 8538 if (SSTATUS_GET_DET(port_sstatus) == SSTATUS_DET_DEVPRE_PHYCOM) {
8534 8539 dev_exists_end = 1;
8535 8540 }
8536 8541
8537 8542 if (dev_exists_begin == 0 && dev_exists_end == 0) /* 0 -> 0 */
8538 8543 return (rval);
8539 8544
8540 8545 /* Check whether a hot plug event happened */
8541 8546 if (dev_exists_begin == 1 && dev_exists_end == 0) { /* 1 -> 0 */
8542 8547 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
8543 8548 "ahci_restart_port_wait_till_ready: port %d "
8544 8549 "device is removed", port);
8545 8550 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_NODEV;
8546 8551 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
8547 8552 "ahci_restart_port_wait_till_ready: port %d "
8548 8553 "AHCI_PORT_FLAG_NODEV flag is set", port);
8549 8554 mutex_exit(&ahci_portp->ahciport_mutex);
8550 8555 (void) ahci_intr_phyrdy_change(ahci_ctlp, ahci_portp, port);
8551 8556 mutex_enter(&ahci_portp->ahciport_mutex);
8552 8557
8553 8558 return (rval);
8554 8559 }
8555 8560
8556 8561
8557 8562 /* 0/1 -> 1 : device may change */
8558 8563 /*
8559 8564 * May be called by ahci_fatal_error_recovery_handler, so
8560 8565 * don't issue software if the previous device is ATAPI.
8561 8566 */
8562 8567 if (ahci_portp->ahciport_device_type == SATA_DTYPE_ATAPI)
8563 8568 return (rval);
8564 8569
8565 8570 /*
8566 8571 * The COMRESET will make port multiplier enter legacy mode.
8567 8572 * Issue a software reset to make it work again.
8568 8573 */
8569 8574 ahci_disable_port_intrs(ahci_ctlp, port);
8570 8575 ahci_find_dev_signature(ahci_ctlp, ahci_portp, &addr_port);
8571 8576 ahci_enable_port_intrs(ahci_ctlp, port);
8572 8577
8573 8578 /*
8574 8579 * Following codes are specific for the port multiplier
8575 8580 */
8576 8581 if (previous_dev_type != SATA_DTYPE_PMULT &&
8577 8582 ahci_portp->ahciport_device_type != SATA_DTYPE_PMULT) {
8578 8583 /* in case previous_dev_type is corrupt */
8579 8584 ahci_dealloc_pmult(ahci_ctlp, ahci_portp);
8580 8585 (void) ahci_start_port(ahci_ctlp, ahci_portp, port);
8581 8586 return (rval);
8582 8587 }
8583 8588
8584 8589 /* Device change: PMult -> Non-PMult */
8585 8590 if (previous_dev_type == SATA_DTYPE_PMULT &&
8586 8591 ahci_portp->ahciport_device_type != SATA_DTYPE_PMULT) {
8587 8592 /*
8588 8593 * This might happen because
8589 8594 * 1. Software reset failed. Port multiplier is not correctly
8590 8595 * enumerated.
8591 8596 * 2. Another non-port-multiplier device is attached. Perhaps
8592 8597 * the port multiplier was replaced by another device by
8593 8598 * whatever reason, but AHCI driver missed hot-plug event.
8594 8599 *
8595 8600 * Now that the port has been initialized, we just need to
8596 8601 * update the port structure according new device, then report
8597 8602 * and wait SATA framework to probe new device.
8598 8603 */
8599 8604
8600 8605 /* Force to release pmult resource */
8601 8606 ahci_dealloc_pmult(ahci_ctlp, ahci_portp);
8602 8607 (void) ahci_start_port(ahci_ctlp, ahci_portp, port);
8603 8608
8604 8609 bzero((void *)&sdevice, sizeof (sata_device_t));
8605 8610 sdevice.satadev_addr.cport =
8606 8611 ahci_ctlp->ahcictl_port_to_cport[port];
8607 8612 sdevice.satadev_addr.pmport = 0;
8608 8613 sdevice.satadev_addr.qual = SATA_ADDR_DCPORT;
8609 8614
8610 8615 sdevice.satadev_state = SATA_DSTATE_RESET |
8611 8616 SATA_DSTATE_PWR_ACTIVE;
8612 8617
8613 8618 mutex_exit(&ahci_portp->ahciport_mutex);
8614 8619 sata_hba_event_notify(
8615 8620 ahci_ctlp->ahcictl_dip,
8616 8621 &sdevice,
8617 8622 SATA_EVNT_DEVICE_RESET);
8618 8623 mutex_enter(&ahci_portp->ahciport_mutex);
8619 8624
8620 8625 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
8621 8626 "Port multiplier is [Gone] at port %d ", port);
8622 8627 AHCIDBG(AHCIDBG_EVENT, ahci_ctlp,
8623 8628 "port %d sending event up: SATA_EVNT_DEVICE_RESET", port);
8624 8629
8625 8630 return (AHCI_SUCCESS);
8626 8631 }
8627 8632
8628 8633 /* Device change: Non-PMult -> PMult */
8629 8634 if (ahci_portp->ahciport_device_type == SATA_DTYPE_PMULT) {
8630 8635
8631 8636 /* NOTE: The PxCMD.PMA may be cleared by HBA reset. */
8632 8637 ahci_alloc_pmult(ahci_ctlp, ahci_portp);
8633 8638
8634 8639 (void) ahci_start_port(ahci_ctlp, ahci_portp, port);
8635 8640 }
8636 8641 pminfo = ahci_portp->ahciport_pmult_info;
8637 8642 ASSERT(pminfo != NULL);
8638 8643
8639 8644 /* Device (may) change: PMult -> PMult */
8640 8645 /*
8641 8646 * First initialize port multiplier. Set state to READY and wait for
8642 8647 * probe entry point to initialize it
8643 8648 */
8644 8649 ahci_portp->ahciport_port_state = SATA_STATE_READY;
8645 8650
8646 8651 /*
8647 8652 * It's a little complicated while target is a port multiplier. we
8648 8653 * need to COMRESET all pmports behind that PMult otherwise those
8649 8654 * sub-links between the PMult and the sub-devices will be in an
8650 8655 * inactive state (indicated by PSCR0/PxSSTS) and the following access
8651 8656 * to those sub-devices will be rejected by Link-Fatal-Error.
8652 8657 */
8653 8658 /*
8654 8659 * The PxSNTF will be set soon after the pmult is plugged. While the
8655 8660 * pmult itself is attaching, sata_hba_event_notfiy will fail. so we
8656 8661 * simply mark every sub-port as 'unknown', then ahci_probe_pmport
8657 8662 * will initialized it.
8658 8663 */
8659 8664 for (npmport = 0; npmport < pminfo->ahcipmi_num_dev_ports; npmport++)
8660 8665 pminfo->ahcipmi_port_state[npmport] = SATA_STATE_UNKNOWN;
8661 8666
8662 8667 /* Report reset event. */
8663 8668 ahci_portp->ahciport_reset_in_progress = 1;
8664 8669
8665 8670 bzero((void *)&sdevice, sizeof (sata_device_t));
8666 8671 sdevice.satadev_addr.cport = cport;
8667 8672 sdevice.satadev_addr.pmport = SATA_PMULT_HOSTPORT;
8668 8673 sdevice.satadev_addr.qual = SATA_ADDR_PMULT;
8669 8674 sdevice.satadev_state = SATA_DSTATE_RESET | SATA_DSTATE_PWR_ACTIVE;
8670 8675 sata_hba_event_notify(ahci_ctlp->ahcictl_dip, &sdevice,
8671 8676 SATA_EVNT_DEVICE_RESET);
8672 8677
8673 8678 return (rval);
8674 8679 }
8675 8680
8676 8681 /*
8677 8682 * This routine may be called under four scenarios:
8678 8683 * a) do the recovery from fatal error
8679 8684 * b) or we need to timeout some commands
8680 8685 * c) or we need to abort some commands
8681 8686 * d) or we need reset device/port/controller
8682 8687 *
8683 8688 * In all these scenarios, we need to send any pending unfinished
8684 8689 * commands up to sata framework.
8685 8690 */
8686 8691 static void
8687 8692 ahci_mop_commands(ahci_ctl_t *ahci_ctlp,
8688 8693 ahci_port_t *ahci_portp,
8689 8694 uint32_t slot_status,
8690 8695 uint32_t failed_tags,
8691 8696 uint32_t timeout_tags,
8692 8697 uint32_t aborted_tags,
8693 8698 uint32_t reset_tags)
8694 8699 {
8695 8700 uint32_t finished_tags = 0;
8696 8701 uint32_t unfinished_tags = 0;
8697 8702 int tmp_slot;
8698 8703 sata_pkt_t *satapkt;
8699 8704 int ncq_cmd_in_progress = 0;
8700 8705 int err_retri_cmd_in_progress = 0;
8701 8706 int rdwr_pmult_cmd_in_progress = 0;
8702 8707
8703 8708 ASSERT(MUTEX_HELD(&ahci_portp->ahciport_mutex));
8704 8709
8705 8710 AHCIDBG(AHCIDBG_ERRS|AHCIDBG_ENTRY, ahci_ctlp,
8706 8711 "ahci_mop_commands entered: port: %d slot_status: 0x%x",
8707 8712 ahci_portp->ahciport_port_num, slot_status);
8708 8713
8709 8714 AHCIDBG(AHCIDBG_ERRS|AHCIDBG_ENTRY, ahci_ctlp,
8710 8715 "ahci_mop_commands: failed_tags: 0x%x, "
8711 8716 "timeout_tags: 0x%x aborted_tags: 0x%x, "
8712 8717 "reset_tags: 0x%x", failed_tags,
8713 8718 timeout_tags, aborted_tags, reset_tags);
8714 8719
8715 8720 #ifdef AHCI_DEBUG
8716 8721 if (ahci_debug_flags & AHCIDBG_ERRS) {
8717 8722 int i;
8718 8723 char msg_buf[200] = {0, };
8719 8724 for (i = 0x1f; i >= 0; i--) {
8720 8725 if (ahci_portp->ahciport_slot_pkts[i] != NULL)
8721 8726 msg_buf[i] = 'X';
8722 8727 else
8723 8728 msg_buf[i] = '.';
8724 8729 }
8725 8730 msg_buf[0x20] = '\0';
8726 8731 cmn_err(CE_NOTE, "port[%d] slots: %s",
8727 8732 ahci_portp->ahciport_port_num, msg_buf);
8728 8733 cmn_err(CE_NOTE, "[ERR-RT] %p [RW-PM] %p ",
8729 8734 (void *)ahci_portp->ahciport_err_retri_pkt,
8730 8735 (void *)ahci_portp->ahciport_rdwr_pmult_pkt);
8731 8736 }
8732 8737 #endif
8733 8738
8734 8739 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) {
8735 8740 finished_tags = ahci_portp->ahciport_pending_tags &
8736 8741 ~slot_status & AHCI_SLOT_MASK(ahci_ctlp);
8737 8742
8738 8743 unfinished_tags = slot_status &
8739 8744 AHCI_SLOT_MASK(ahci_ctlp) &
8740 8745 ~failed_tags &
8741 8746 ~aborted_tags &
8742 8747 ~reset_tags &
8743 8748 ~timeout_tags;
8744 8749 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) {
8745 8750 ncq_cmd_in_progress = 1;
8746 8751 finished_tags = ahci_portp->ahciport_pending_ncq_tags &
8747 8752 ~slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp);
8748 8753
8749 8754 unfinished_tags = slot_status &
8750 8755 AHCI_NCQ_SLOT_MASK(ahci_portp) &
8751 8756 ~failed_tags &
8752 8757 ~aborted_tags &
8753 8758 ~reset_tags &
8754 8759 ~timeout_tags;
8755 8760 } else if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) {
8756 8761
8757 8762 /*
8758 8763 * When AHCI_PORT_FLAG_RQSENSE or AHCI_PORT_FLAG_RDLOGEXT is
8759 8764 * set, it means REQUEST SENSE or READ LOG EXT command doesn't
8760 8765 * complete successfully due to one of the following three
8761 8766 * conditions:
8762 8767 *
8763 8768 * 1. Fatal error - failed_tags includes its slot
8764 8769 * 2. Timed out - timeout_tags includes its slot
8765 8770 * 3. Aborted when hot unplug - aborted_tags includes its
8766 8771 * slot
8767 8772 *
8768 8773 * Please note that the command is always sent down in Slot 0
8769 8774 */
8770 8775 err_retri_cmd_in_progress = 1;
8771 8776 AHCIDBG(AHCIDBG_ERRS|AHCIDBG_NCQ, ahci_ctlp,
8772 8777 "ahci_mop_commands is called for port %d while "
8773 8778 "REQUEST SENSE or READ LOG EXT for error retrieval "
8774 8779 "is being executed slot_status = 0x%x",
8775 8780 ahci_portp->ahciport_port_num, slot_status);
8776 8781 ASSERT(ahci_portp->ahciport_mop_in_progress > 1);
8777 8782 ASSERT(slot_status == 0x1);
8778 8783 } else if (RDWR_PMULT_CMD_IN_PROGRESS(ahci_portp)) {
8779 8784 rdwr_pmult_cmd_in_progress = 1;
8780 8785 AHCIDBG(AHCIDBG_ERRS|AHCIDBG_PMULT, ahci_ctlp,
8781 8786 "ahci_mop_commands is called for port %d while "
8782 8787 "READ/WRITE PORTMULT command is being executed",
8783 8788 ahci_portp->ahciport_port_num);
8784 8789
8785 8790 ASSERT(slot_status == 0x1);
8786 8791 }
8787 8792
8788 8793 #ifdef AHCI_DEBUG
8789 8794 AHCIDBG(AHCIDBG_ERRS|AHCIDBG_ENTRY, ahci_ctlp,
8790 8795 "ahci_mop_commands: finished_tags: 0x%x, "
8791 8796 "unfinished_tags 0x%x", finished_tags, unfinished_tags);
8792 8797 #endif
8793 8798
8794 8799 /* Send up finished packets with SATA_PKT_COMPLETED */
8795 8800 while (finished_tags) {
8796 8801 tmp_slot = ddi_ffs(finished_tags) - 1;
8797 8802 if (tmp_slot == -1) {
8798 8803 break;
8799 8804 }
8800 8805
8801 8806 satapkt = ahci_portp->ahciport_slot_pkts[tmp_slot];
8802 8807 ASSERT(satapkt != NULL);
8803 8808
8804 8809 AHCIDBG(AHCIDBG_INFO, ahci_ctlp, "ahci_mop_commands: "
8805 8810 "sending up pkt 0x%p with SATA_PKT_COMPLETED",
8806 8811 (void *)satapkt);
8807 8812
8808 8813 /*
8809 8814 * Cannot fetch the return register content since the port
8810 8815 * was restarted, so the corresponding tag will be set to
8811 8816 * aborted tags.
8812 8817 */
8813 8818 if (satapkt->satapkt_cmd.satacmd_flags.sata_special_regs) {
8814 8819 CLEAR_BIT(finished_tags, tmp_slot);
8815 8820 aborted_tags |= tmp_slot;
8816 8821 continue;
8817 8822 }
8818 8823
8819 8824 if (ncq_cmd_in_progress)
8820 8825 CLEAR_BIT(ahci_portp->ahciport_pending_ncq_tags,
8821 8826 tmp_slot);
8822 8827 CLEAR_BIT(ahci_portp->ahciport_pending_tags, tmp_slot);
8823 8828 CLEAR_BIT(finished_tags, tmp_slot);
8824 8829 ahci_portp->ahciport_slot_pkts[tmp_slot] = NULL;
8825 8830
8826 8831 ahci_add_doneq(ahci_portp, satapkt, SATA_PKT_COMPLETED);
8827 8832 }
8828 8833
8829 8834 /* Send up failed packets with SATA_PKT_DEV_ERROR. */
8830 8835 while (failed_tags) {
8831 8836 if (err_retri_cmd_in_progress) {
8832 8837 satapkt = ahci_portp->ahciport_err_retri_pkt;
8833 8838 ASSERT(satapkt != NULL);
8834 8839 ASSERT(failed_tags == 0x1);
8835 8840
8836 8841 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: "
8837 8842 "sending up pkt 0x%p with SATA_PKT_DEV_ERROR",
8838 8843 (void *)satapkt);
8839 8844 ahci_add_doneq(ahci_portp, satapkt, SATA_PKT_DEV_ERROR);
8840 8845 break;
8841 8846 }
8842 8847 if (rdwr_pmult_cmd_in_progress) {
8843 8848 satapkt = ahci_portp->ahciport_rdwr_pmult_pkt;
8844 8849 ASSERT(satapkt != NULL);
8845 8850 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
8846 8851 "ahci_mop_commands: sending up "
8847 8852 "rdwr pmult pkt 0x%p with SATA_PKT_DEV_ERROR",
8848 8853 (void *)satapkt);
8849 8854 ahci_add_doneq(ahci_portp, satapkt, SATA_PKT_DEV_ERROR);
8850 8855 break;
8851 8856 }
8852 8857
8853 8858 tmp_slot = ddi_ffs(failed_tags) - 1;
8854 8859 if (tmp_slot == -1) {
8855 8860 break;
8856 8861 }
8857 8862
8858 8863 satapkt = ahci_portp->ahciport_slot_pkts[tmp_slot];
8859 8864 ASSERT(satapkt != NULL);
8860 8865
8861 8866 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: "
8862 8867 "sending up pkt 0x%p with SATA_PKT_DEV_ERROR",
8863 8868 (void *)satapkt);
8864 8869
8865 8870 if (ncq_cmd_in_progress)
8866 8871 CLEAR_BIT(ahci_portp->ahciport_pending_ncq_tags,
8867 8872 tmp_slot);
8868 8873 CLEAR_BIT(ahci_portp->ahciport_pending_tags, tmp_slot);
8869 8874 CLEAR_BIT(failed_tags, tmp_slot);
8870 8875 ahci_portp->ahciport_slot_pkts[tmp_slot] = NULL;
8871 8876
8872 8877 ahci_add_doneq(ahci_portp, satapkt, SATA_PKT_DEV_ERROR);
8873 8878 }
8874 8879
8875 8880 /* Send up timeout packets with SATA_PKT_TIMEOUT. */
8876 8881 while (timeout_tags) {
8877 8882 if (err_retri_cmd_in_progress) {
8878 8883 satapkt = ahci_portp->ahciport_err_retri_pkt;
8879 8884 ASSERT(satapkt != NULL);
8880 8885 ASSERT(timeout_tags == 0x1);
8881 8886
8882 8887 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: "
8883 8888 "sending up pkt 0x%p with SATA_PKT_TIMEOUT",
8884 8889 (void *)satapkt);
8885 8890 ahci_add_doneq(ahci_portp, satapkt, SATA_PKT_TIMEOUT);
8886 8891 break;
8887 8892 }
8888 8893 if (rdwr_pmult_cmd_in_progress) {
8889 8894 satapkt = ahci_portp->ahciport_rdwr_pmult_pkt;
8890 8895 ASSERT(satapkt != NULL);
8891 8896 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
8892 8897 "ahci_mop_commands: sending up "
8893 8898 "rdwr pmult pkt 0x%p with SATA_PKT_TIMEOUT",
8894 8899 (void *)satapkt);
8895 8900 ahci_add_doneq(ahci_portp, satapkt, SATA_PKT_TIMEOUT);
8896 8901 break;
8897 8902 }
8898 8903
8899 8904 tmp_slot = ddi_ffs(timeout_tags) - 1;
8900 8905 if (tmp_slot == -1) {
8901 8906 break;
8902 8907 }
8903 8908
8904 8909 satapkt = ahci_portp->ahciport_slot_pkts[tmp_slot];
8905 8910 ASSERT(satapkt != NULL);
8906 8911
8907 8912 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: "
8908 8913 "sending up pkt 0x%p with SATA_PKT_TIMEOUT",
8909 8914 (void *)satapkt);
8910 8915
8911 8916 if (ncq_cmd_in_progress)
8912 8917 CLEAR_BIT(ahci_portp->ahciport_pending_ncq_tags,
8913 8918 tmp_slot);
8914 8919 CLEAR_BIT(ahci_portp->ahciport_pending_tags, tmp_slot);
8915 8920 CLEAR_BIT(timeout_tags, tmp_slot);
8916 8921 ahci_portp->ahciport_slot_pkts[tmp_slot] = NULL;
8917 8922
8918 8923 ahci_add_doneq(ahci_portp, satapkt, SATA_PKT_TIMEOUT);
8919 8924 }
8920 8925
8921 8926 /* Send up aborted packets with SATA_PKT_ABORTED */
8922 8927 while (aborted_tags) {
8923 8928 if (err_retri_cmd_in_progress) {
8924 8929 satapkt = ahci_portp->ahciport_err_retri_pkt;
8925 8930 ASSERT(satapkt != NULL);
8926 8931 ASSERT(aborted_tags == 0x1);
8927 8932
8928 8933 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: "
8929 8934 "sending up pkt 0x%p with SATA_PKT_ABORTED",
8930 8935 (void *)satapkt);
8931 8936 ahci_add_doneq(ahci_portp, satapkt, SATA_PKT_ABORTED);
8932 8937 break;
8933 8938 }
8934 8939 if (rdwr_pmult_cmd_in_progress) {
8935 8940 satapkt = ahci_portp->ahciport_rdwr_pmult_pkt;
8936 8941 ASSERT(satapkt != NULL);
8937 8942 ASSERT(aborted_tags == 0x1);
8938 8943 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
8939 8944 "ahci_mop_commands: sending up "
8940 8945 "rdwr pmult pkt 0x%p with SATA_PKT_ABORTED",
8941 8946 (void *)satapkt);
8942 8947 ahci_add_doneq(ahci_portp, satapkt, SATA_PKT_ABORTED);
8943 8948 break;
8944 8949 }
8945 8950
8946 8951 tmp_slot = ddi_ffs(aborted_tags) - 1;
8947 8952 if (tmp_slot == -1) {
8948 8953 break;
8949 8954 }
8950 8955
8951 8956 satapkt = ahci_portp->ahciport_slot_pkts[tmp_slot];
8952 8957 ASSERT(satapkt != NULL);
8953 8958
8954 8959 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: "
8955 8960 "sending up pkt 0x%p with SATA_PKT_ABORTED",
8956 8961 (void *)satapkt);
8957 8962
8958 8963 if (ncq_cmd_in_progress)
8959 8964 CLEAR_BIT(ahci_portp->ahciport_pending_ncq_tags,
8960 8965 tmp_slot);
8961 8966 CLEAR_BIT(ahci_portp->ahciport_pending_tags, tmp_slot);
8962 8967 CLEAR_BIT(aborted_tags, tmp_slot);
8963 8968 ahci_portp->ahciport_slot_pkts[tmp_slot] = NULL;
8964 8969
8965 8970 ahci_add_doneq(ahci_portp, satapkt, SATA_PKT_ABORTED);
8966 8971 }
8967 8972
8968 8973 /* Send up reset packets with SATA_PKT_RESET. */
8969 8974 while (reset_tags) {
8970 8975 if (rdwr_pmult_cmd_in_progress) {
8971 8976 satapkt = ahci_portp->ahciport_rdwr_pmult_pkt;
8972 8977 ASSERT(satapkt != NULL);
8973 8978 ASSERT(aborted_tags == 0x1);
8974 8979 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
8975 8980 "ahci_mop_commands: sending up "
8976 8981 "rdwr pmult pkt 0x%p with SATA_PKT_RESET",
8977 8982 (void *)satapkt);
8978 8983 ahci_add_doneq(ahci_portp, satapkt, SATA_PKT_RESET);
8979 8984 break;
8980 8985 }
8981 8986
8982 8987 tmp_slot = ddi_ffs(reset_tags) - 1;
8983 8988 if (tmp_slot == -1) {
8984 8989 break;
8985 8990 }
8986 8991
8987 8992 satapkt = ahci_portp->ahciport_slot_pkts[tmp_slot];
8988 8993 ASSERT(satapkt != NULL);
8989 8994
8990 8995 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: "
8991 8996 "sending up pkt 0x%p with SATA_PKT_RESET",
8992 8997 (void *)satapkt);
8993 8998
8994 8999 if (ncq_cmd_in_progress)
8995 9000 CLEAR_BIT(ahci_portp->ahciport_pending_ncq_tags,
8996 9001 tmp_slot);
8997 9002 CLEAR_BIT(ahci_portp->ahciport_pending_tags, tmp_slot);
8998 9003 CLEAR_BIT(reset_tags, tmp_slot);
8999 9004 ahci_portp->ahciport_slot_pkts[tmp_slot] = NULL;
9000 9005
9001 9006 ahci_add_doneq(ahci_portp, satapkt, SATA_PKT_RESET);
9002 9007 }
9003 9008
9004 9009 /* Send up unfinished packets with SATA_PKT_RESET */
9005 9010 while (unfinished_tags) {
9006 9011 tmp_slot = ddi_ffs(unfinished_tags) - 1;
9007 9012 if (tmp_slot == -1) {
9008 9013 break;
9009 9014 }
9010 9015
9011 9016 satapkt = ahci_portp->ahciport_slot_pkts[tmp_slot];
9012 9017 ASSERT(satapkt != NULL);
9013 9018
9014 9019 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: "
9015 9020 "sending up pkt 0x%p with SATA_PKT_RESET",
9016 9021 (void *)satapkt);
9017 9022
9018 9023 if (ncq_cmd_in_progress)
9019 9024 CLEAR_BIT(ahci_portp->ahciport_pending_ncq_tags,
9020 9025 tmp_slot);
9021 9026 CLEAR_BIT(ahci_portp->ahciport_pending_tags, tmp_slot);
9022 9027 CLEAR_BIT(unfinished_tags, tmp_slot);
9023 9028 ahci_portp->ahciport_slot_pkts[tmp_slot] = NULL;
9024 9029
9025 9030 ahci_add_doneq(ahci_portp, satapkt, SATA_PKT_RESET);
9026 9031 }
9027 9032
9028 9033 ahci_portp->ahciport_mop_in_progress--;
9029 9034 ASSERT(ahci_portp->ahciport_mop_in_progress >= 0);
9030 9035
9031 9036 if (ahci_portp->ahciport_mop_in_progress == 0)
9032 9037 ahci_portp->ahciport_flags &= ~AHCI_PORT_FLAG_MOPPING;
9033 9038
9034 9039 ahci_flush_doneq(ahci_portp);
9035 9040 }
9036 9041
9037 9042 /*
9038 9043 * This routine is going to first request a READ LOG EXT sata pkt from sata
9039 9044 * module, and then deliver it to the HBA to get the ncq failure context.
9040 9045 * The return value is the exactly failed tags.
9041 9046 */
9042 9047 static uint32_t
9043 9048 ahci_get_rdlogext_data(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp,
9044 9049 uint8_t port)
9045 9050 {
9046 9051 sata_device_t sdevice;
9047 9052 sata_pkt_t *rdlog_spkt, *spkt;
9048 9053 ddi_dma_handle_t buf_dma_handle;
9049 9054 ahci_addr_t addr;
9050 9055 int loop_count;
9051 9056 int rval;
9052 9057 int failed_slot;
9053 9058 uint32_t failed_tags = 0;
9054 9059 struct sata_ncq_error_recovery_page *ncq_err_page;
9055 9060
9056 9061 AHCIDBG(AHCIDBG_ENTRY|AHCIDBG_NCQ, ahci_ctlp,
9057 9062 "ahci_get_rdlogext_data enter: port %d", port);
9058 9063
9059 9064 /* Prepare the sdevice data */
9060 9065 bzero((void *)&sdevice, sizeof (sata_device_t));
9061 9066 sdevice.satadev_addr.cport = ahci_ctlp->ahcictl_port_to_cport[port];
9062 9067
9063 9068 sdevice.satadev_addr.qual = SATA_ADDR_DCPORT;
9064 9069 sdevice.satadev_addr.pmport = 0;
9065 9070
9066 9071 /* Translate sata_device.satadev_addr -> ahci_addr */
9067 9072 ahci_get_ahci_addr(ahci_ctlp, &sdevice, &addr);
9068 9073
9069 9074 /*
9070 9075 * Call the sata hba interface to get a rdlog spkt
9071 9076 */
9072 9077 loop_count = 0;
9073 9078 loop:
9074 9079 rdlog_spkt = sata_get_error_retrieval_pkt(ahci_ctlp->ahcictl_dip,
9075 9080 &sdevice, SATA_ERR_RETR_PKT_TYPE_NCQ);
9076 9081 if (rdlog_spkt == NULL) {
9077 9082 if (loop_count++ < AHCI_POLLRATE_GET_SPKT) {
9078 9083 /* Sleep for a while */
9079 9084 drv_usecwait(AHCI_10MS_USECS);
9080 9085 goto loop;
9081 9086 }
9082 9087 /* Timed out after 1s */
9083 9088 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
9084 9089 "failed to get rdlog spkt for port %d", port);
9085 9090 return (failed_tags);
9086 9091 }
9087 9092
9088 9093 ASSERT(rdlog_spkt->satapkt_op_mode & SATA_OPMODE_SYNCH);
9089 9094
9090 9095 /*
9091 9096 * This flag is used to handle the specific error recovery when the
9092 9097 * READ LOG EXT command gets a failure (fatal error or time-out).
9093 9098 */
9094 9099 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_RDLOGEXT;
9095 9100
9096 9101 /*
9097 9102 * This start is not supposed to fail because after port is restarted,
9098 9103 * the whole command list is empty.
9099 9104 */
9100 9105 ahci_portp->ahciport_err_retri_pkt = rdlog_spkt;
9101 9106 (void) ahci_do_sync_start(ahci_ctlp, ahci_portp, &addr, rdlog_spkt);
9102 9107 ahci_portp->ahciport_err_retri_pkt = NULL;
9103 9108
9104 9109 /* Remove the flag after READ LOG EXT command is completed */
9105 9110 ahci_portp->ahciport_flags &= ~AHCI_PORT_FLAG_RDLOGEXT;
9106 9111
9107 9112 if (rdlog_spkt->satapkt_reason == SATA_PKT_COMPLETED) {
9108 9113 /* Update the request log data */
9109 9114 buf_dma_handle = *(ddi_dma_handle_t *)
9110 9115 (rdlog_spkt->satapkt_cmd.satacmd_err_ret_buf_handle);
9111 9116 rval = ddi_dma_sync(buf_dma_handle, 0, 0,
9112 9117 DDI_DMA_SYNC_FORKERNEL);
9113 9118 if (rval == DDI_SUCCESS) {
9114 9119 ncq_err_page =
9115 9120 (struct sata_ncq_error_recovery_page *)rdlog_spkt->
9116 9121 satapkt_cmd.satacmd_bp->b_un.b_addr;
9117 9122
9118 9123 /* Get the failed tag */
9119 9124 failed_slot = ncq_err_page->ncq_tag;
9120 9125 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
9121 9126 "ahci_get_rdlogext_data: port %d "
9122 9127 "failed slot %d", port, failed_slot);
9123 9128 if (failed_slot & NQ) {
9124 9129 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
9125 9130 "the failed slot is not a valid tag", NULL);
9126 9131 goto out;
9127 9132 }
9128 9133
9129 9134 failed_slot &= NCQ_TAG_MASK;
9130 9135 spkt = ahci_portp->ahciport_slot_pkts[failed_slot];
9131 9136 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
9132 9137 "ahci_get_rdlogext_data: failed spkt 0x%p",
9133 9138 (void *)spkt);
9134 9139 if (spkt == NULL) {
9135 9140 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
9136 9141 "the failed slot spkt is NULL", NULL);
9137 9142 goto out;
9138 9143 }
9139 9144
9140 9145 failed_tags = 0x1 << failed_slot;
9141 9146
9142 9147 /* Fill out the error context */
9143 9148 ahci_copy_ncq_err_page(&spkt->satapkt_cmd,
9144 9149 ncq_err_page);
9145 9150 ahci_update_sata_registers(ahci_ctlp, port,
9146 9151 &spkt->satapkt_device);
9147 9152 }
9148 9153 }
9149 9154 out:
9150 9155 sata_free_error_retrieval_pkt(rdlog_spkt);
9151 9156
9152 9157 return (failed_tags);
9153 9158 }
9154 9159
9155 9160 /*
9156 9161 * This routine is going to first request a REQUEST SENSE sata pkt from sata
9157 9162 * module, and then deliver it to the HBA to get the sense data and copy
9158 9163 * the sense data back to the orignal failed sata pkt, and free the REQUEST
9159 9164 * SENSE sata pkt later.
9160 9165 */
9161 9166 static void
9162 9167 ahci_get_rqsense_data(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp,
9163 9168 uint8_t port, sata_pkt_t *spkt)
9164 9169 {
9165 9170 sata_device_t sdevice;
9166 9171 sata_pkt_t *rs_spkt;
9167 9172 sata_cmd_t *sata_cmd;
9168 9173 ddi_dma_handle_t buf_dma_handle;
9169 9174 ahci_addr_t addr;
9170 9175 int loop_count;
9171 9176 #if AHCI_DEBUG
9172 9177 struct scsi_extended_sense *rqsense;
9173 9178 #endif
9174 9179
9175 9180 AHCIDBG(AHCIDBG_ENTRY, ahci_ctlp,
9176 9181 "ahci_get_rqsense_data enter: port %d", port);
9177 9182
9178 9183 /* Prepare the sdevice data */
9179 9184 bzero((void *)&sdevice, sizeof (sata_device_t));
9180 9185 sdevice.satadev_addr.cport = ahci_ctlp->ahcictl_port_to_cport[port];
9181 9186
9182 9187 sdevice.satadev_addr.qual = SATA_ADDR_DCPORT;
9183 9188 sdevice.satadev_addr.pmport = 0;
9184 9189
9185 9190 /* Translate sata_device.satadev_addr -> ahci_addr */
9186 9191 ahci_get_ahci_addr(ahci_ctlp, &sdevice, &addr);
9187 9192
9188 9193 sata_cmd = &spkt->satapkt_cmd;
9189 9194
9190 9195 /*
9191 9196 * Call the sata hba interface to get a rs spkt
9192 9197 */
9193 9198 loop_count = 0;
9194 9199 loop:
9195 9200 rs_spkt = sata_get_error_retrieval_pkt(ahci_ctlp->ahcictl_dip,
9196 9201 &sdevice, SATA_ERR_RETR_PKT_TYPE_ATAPI);
9197 9202 if (rs_spkt == NULL) {
9198 9203 if (loop_count++ < AHCI_POLLRATE_GET_SPKT) {
9199 9204 /* Sleep for a while */
9200 9205 drv_usecwait(AHCI_10MS_USECS);
9201 9206 goto loop;
9202 9207
9203 9208 }
9204 9209 /* Timed out after 1s */
9205 9210 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
9206 9211 "failed to get rs spkt for port %d", port);
9207 9212 return;
9208 9213 }
9209 9214
9210 9215 ASSERT(rs_spkt->satapkt_op_mode & SATA_OPMODE_SYNCH);
9211 9216
9212 9217 /*
9213 9218 * This flag is used to handle the specific error recovery when the
9214 9219 * REQUEST SENSE command gets a faiure (fatal error or time-out).
9215 9220 */
9216 9221 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_RQSENSE;
9217 9222
9218 9223 /*
9219 9224 * This start is not supposed to fail because after port is restarted,
9220 9225 * the whole command list is empty.
9221 9226 */
9222 9227 ahci_portp->ahciport_err_retri_pkt = rs_spkt;
9223 9228 (void) ahci_do_sync_start(ahci_ctlp, ahci_portp, &addr, rs_spkt);
9224 9229 ahci_portp->ahciport_err_retri_pkt = NULL;
9225 9230
9226 9231 /* Remove the flag after REQUEST SENSE command is completed */
9227 9232 ahci_portp->ahciport_flags &= ~AHCI_PORT_FLAG_RQSENSE;
9228 9233
9229 9234 if (rs_spkt->satapkt_reason == SATA_PKT_COMPLETED) {
9230 9235 /* Update the request sense data */
9231 9236 buf_dma_handle = *(ddi_dma_handle_t *)
9232 9237 (rs_spkt->satapkt_cmd.satacmd_err_ret_buf_handle);
9233 9238 (void) ddi_dma_sync(buf_dma_handle, 0, 0,
9234 9239 DDI_DMA_SYNC_FORKERNEL);
9235 9240 /* Copy the request sense data */
9236 9241 bcopy(rs_spkt->
9237 9242 satapkt_cmd.satacmd_bp->b_un.b_addr,
9238 9243 &sata_cmd->satacmd_rqsense,
9239 9244 SATA_ATAPI_MIN_RQSENSE_LEN);
9240 9245 #if AHCI_DEBUG
9241 9246 rqsense = (struct scsi_extended_sense *)
9242 9247 sata_cmd->satacmd_rqsense;
9243 9248
9244 9249 /* Dump the sense data */
9245 9250 AHCIDBG(AHCIDBG_SENSEDATA, ahci_ctlp, "\n", NULL);
9246 9251 AHCIDBG(AHCIDBG_SENSEDATA, ahci_ctlp,
9247 9252 "Sense data for satapkt %p ATAPI cmd 0x%x",
9248 9253 spkt, sata_cmd->satacmd_acdb[0]);
9249 9254 AHCIDBG(AHCIDBG_SENSEDATA, ahci_ctlp,
9250 9255 " es_code 0x%x es_class 0x%x "
9251 9256 "es_key 0x%x es_add_code 0x%x "
9252 9257 "es_qual_code 0x%x",
9253 9258 rqsense->es_code, rqsense->es_class,
9254 9259 rqsense->es_key, rqsense->es_add_code,
9255 9260 rqsense->es_qual_code);
9256 9261 #endif
9257 9262 }
9258 9263
9259 9264 sata_free_error_retrieval_pkt(rs_spkt);
9260 9265 }
9261 9266
9262 9267 /*
9263 9268 * Fatal errors will cause the HBA to enter the ERR: Fatal state. To recover,
9264 9269 * the port must be restarted. When the HBA detects thus error, it may try
9265 9270 * to abort a transfer. And if the transfer was aborted, the device is
9266 9271 * expected to send a D2H Register FIS with PxTFD.STS.ERR set to '1' and both
9267 9272 * PxTFD.STS.BSY and PxTFD.STS.DRQ cleared to '0'. Then system software knows
9268 9273 * that the device is in a stable status and transfers may be restarted without
9269 9274 * issuing a COMRESET to the device. If PxTFD.STS.BSY or PxTFD.STS.DRQ is set,
9270 9275 * then the software will send the COMRESET to do the port reset.
9271 9276 *
9272 9277 * Software should perform the appropriate error recovery actions based on
9273 9278 * whether non-queued commands were being issued or natived command queuing
9274 9279 * commands were being issued.
9275 9280 *
9276 9281 * And software will complete the command that had the error with error mark
9277 9282 * to higher level software.
9278 9283 *
9279 9284 * Fatal errors include the following:
9280 9285 * PxIS.IFS - Interface Fatal Error Status
9281 9286 * PxIS.HBDS - Host Bus Data Error Status
9282 9287 * PxIS.HBFS - Host Bus Fatal Error Status
9283 9288 * PxIS.TFES - Task File Error Status
9284 9289 */
9285 9290 static void
9286 9291 ahci_fatal_error_recovery_handler(ahci_ctl_t *ahci_ctlp,
9287 9292 ahci_port_t *ahci_portp, ahci_addr_t *addrp, uint32_t intr_status)
9288 9293 {
9289 9294 uint32_t port_cmd_status;
9290 9295 uint32_t slot_status = 0;
9291 9296 uint32_t failed_tags = 0;
9292 9297 int failed_slot;
9293 9298 int reset_flag = 0, flag = 0;
9294 9299 ahci_fis_d2h_register_t *ahci_rcvd_fisp;
9295 9300 sata_cmd_t *sata_cmd = NULL;
9296 9301 sata_pkt_t *spkt = NULL;
9297 9302 #if AHCI_DEBUG
9298 9303 ahci_cmd_header_t *cmd_header;
9299 9304 #endif
9300 9305 uint8_t port = addrp->aa_port;
9301 9306 int instance = ddi_get_instance(ahci_ctlp->ahcictl_dip);
9302 9307 int rval;
9303 9308
9304 9309 ASSERT(MUTEX_HELD(&ahci_portp->ahciport_mutex));
9305 9310
9306 9311 AHCIDBG(AHCIDBG_ENTRY, ahci_ctlp,
9307 9312 "ahci_fatal_error_recovery_handler enter: port %d", port);
9308 9313
9309 9314 /* Port multiplier error */
9310 9315 if (ahci_portp->ahciport_device_type == SATA_DTYPE_PMULT) {
9311 9316 /* FBS code is neither completed nor tested. */
9312 9317 ahci_pmult_error_recovery_handler(ahci_ctlp, ahci_portp,
9313 9318 port, intr_status);
9314 9319
9315 9320 /* Force a port reset */
9316 9321 flag = AHCI_PORT_RESET;
9317 9322 }
9318 9323
9319 9324 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp) ||
9320 9325 ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) {
9321 9326
9322 9327 /* Read PxCI to see which commands are still outstanding */
9323 9328 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
9324 9329 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port));
9325 9330
9326 9331 /*
9327 9332 * Read PxCMD.CCS to determine the slot that the HBA
9328 9333 * was processing when the error occurred.
9329 9334 */
9330 9335 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
9331 9336 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port));
9332 9337 failed_slot = (port_cmd_status & AHCI_CMD_STATUS_CCS) >>
9333 9338 AHCI_CMD_STATUS_CCS_SHIFT;
9334 9339
9335 9340 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) {
9336 9341 spkt = ahci_portp->ahciport_err_retri_pkt;
9337 9342 ASSERT(spkt != NULL);
9338 9343 } else {
9339 9344 spkt = ahci_portp->ahciport_slot_pkts[failed_slot];
9340 9345 if (spkt == NULL) {
9341 9346 /* May happen when interface errors occur? */
9342 9347 goto next;
9343 9348 }
9344 9349 }
9345 9350
9346 9351 #if AHCI_DEBUG
9347 9352 /*
9348 9353 * Debugging purpose...
9349 9354 */
9350 9355 if (ahci_portp->ahciport_prd_bytecounts[failed_slot]) {
9351 9356 cmd_header =
9352 9357 &ahci_portp->ahciport_cmd_list[failed_slot];
9353 9358 AHCIDBG(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp,
9354 9359 "ahci_fatal_error_recovery_handler: port %d, "
9355 9360 "PRD Byte Count = 0x%x, "
9356 9361 "ahciport_prd_bytecounts = 0x%x", port,
9357 9362 cmd_header->ahcich_prd_byte_count,
9358 9363 ahci_portp->ahciport_prd_bytecounts[failed_slot]);
9359 9364 }
9360 9365 #endif
9361 9366
9362 9367 sata_cmd = &spkt->satapkt_cmd;
9363 9368
9364 9369 /* Fill out the status and error registers for PxIS.TFES */
9365 9370 if (intr_status & AHCI_INTR_STATUS_TFES) {
9366 9371 ahci_rcvd_fisp = &(ahci_portp->ahciport_rcvd_fis->
9367 9372 ahcirf_d2h_register_fis);
9368 9373
9369 9374 /* Copy the error context back to the sata_cmd */
9370 9375 ahci_copy_err_cnxt(sata_cmd, ahci_rcvd_fisp);
9371 9376 }
9372 9377
9373 9378 /* The failed command must be one of the outstanding commands */
9374 9379 failed_tags = 0x1 << failed_slot;
9375 9380 ASSERT(failed_tags & slot_status);
9376 9381
9377 9382 /* Update the sata registers, especially PxSERR register */
9378 9383 ahci_update_sata_registers(ahci_ctlp, port,
9379 9384 &spkt->satapkt_device);
9380 9385
9381 9386 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) {
9382 9387 /* Read PxSACT to see which commands are still outstanding */
9383 9388 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
9384 9389 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port));
9385 9390 }
9386 9391 next:
9387 9392
9388 9393 #if AHCI_DEBUG
9389 9394 /*
9390 9395 * When AHCI_PORT_FLAG_RQSENSE or AHCI_PORT_FLAG_RDLOGEXT flag is
9391 9396 * set, it means a fatal error happened after REQUEST SENSE command
9392 9397 * or READ LOG EXT command is delivered to the HBA during the error
9393 9398 * recovery process. At this time, the only outstanding command is
9394 9399 * supposed to be REQUEST SENSE command or READ LOG EXT command.
9395 9400 */
9396 9401 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) {
9397 9402 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
9398 9403 "ahci_fatal_error_recovery_handler: port %d REQUEST SENSE "
9399 9404 "command or READ LOG EXT command for error data retrieval "
9400 9405 "failed", port);
9401 9406 ASSERT(slot_status == 0x1);
9402 9407 ASSERT(failed_slot == 0);
9403 9408 ASSERT(spkt->satapkt_cmd.satacmd_acdb[0] ==
9404 9409 SCMD_REQUEST_SENSE ||
9405 9410 spkt->satapkt_cmd.satacmd_cmd_reg ==
9406 9411 SATAC_READ_LOG_EXT);
9407 9412 }
9408 9413 #endif
9409 9414
9410 9415 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING;
9411 9416 ahci_portp->ahciport_mop_in_progress++;
9412 9417
9413 9418 rval = ahci_restart_port_wait_till_ready(ahci_ctlp, ahci_portp,
9414 9419 port, flag, &reset_flag);
9415 9420
9416 9421 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_ERRPRINT) {
9417 9422 ahci_portp->ahciport_flags &= ~AHCI_PORT_FLAG_ERRPRINT;
9418 9423 if (rval == AHCI_SUCCESS)
9419 9424 cmn_err(CE_WARN, "!ahci%d: error recovery for port %d "
9420 9425 "succeed", instance, port);
9421 9426 else
9422 9427 cmn_err(CE_WARN, "!ahci%d: error recovery for port %d "
9423 9428 "failed", instance, port);
9424 9429 }
9425 9430
9426 9431 /*
9427 9432 * Won't retrieve error information:
9428 9433 * 1. Port reset was involved to recover
9429 9434 * 2. Device is gone
9430 9435 * 3. IDENTIFY DEVICE command sent to ATAPI device
9431 9436 * 4. REQUEST SENSE or READ LOG EXT command during error recovery
9432 9437 */
9433 9438 if (reset_flag ||
9434 9439 ahci_portp->ahciport_device_type == SATA_DTYPE_NONE ||
9435 9440 spkt && spkt->satapkt_cmd.satacmd_cmd_reg == SATAC_ID_DEVICE ||
9436 9441 ERR_RETRI_CMD_IN_PROGRESS(ahci_portp))
9437 9442 goto out;
9438 9443
9439 9444 /*
9440 9445 * Deliver READ LOG EXT to gather information about the error when
9441 9446 * a COMRESET has not been performed as part of the error recovery
9442 9447 * during NCQ command processing.
9443 9448 */
9444 9449 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) {
9445 9450 failed_tags = ahci_get_rdlogext_data(ahci_ctlp,
9446 9451 ahci_portp, port);
9447 9452 goto out;
9448 9453 }
9449 9454
9450 9455 /*
9451 9456 * Deliver REQUEST SENSE for ATAPI command to gather information about
9452 9457 * the error when a COMRESET has not been performed as part of the
9453 9458 * error recovery.
9454 9459 */
9455 9460 if (spkt && ahci_portp->ahciport_device_type == SATA_DTYPE_ATAPI)
9456 9461 ahci_get_rqsense_data(ahci_ctlp, ahci_portp, port, spkt);
9457 9462 out:
9458 9463 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
9459 9464 "ahci_fatal_error_recovery_handler: port %d fatal error "
9460 9465 "occurred slot_status = 0x%x, pending_tags = 0x%x, "
9461 9466 "pending_ncq_tags = 0x%x failed_tags = 0x%x",
9462 9467 port, slot_status, ahci_portp->ahciport_pending_tags,
9463 9468 ahci_portp->ahciport_pending_ncq_tags, failed_tags);
9464 9469
9465 9470 ahci_mop_commands(ahci_ctlp,
9466 9471 ahci_portp,
9467 9472 slot_status,
9468 9473 failed_tags, /* failed tags */
9469 9474 0, /* timeout tags */
9470 9475 0, /* aborted tags */
9471 9476 0); /* reset tags */
9472 9477 }
9473 9478
9474 9479 /*
9475 9480 * Used to recovery a PMULT pmport fatal error under FIS-based switching.
9476 9481 * 1. device specific.PxFBS.SDE=1
9477 9482 * 2. Non-Deivce specific.
9478 9483 * Nothing will be done when Command-based switching is employed.
9479 9484 *
9480 9485 * Currently code is neither completed nor tested.
9481 9486 */
9482 9487 static void
9483 9488 ahci_pmult_error_recovery_handler(ahci_ctl_t *ahci_ctlp,
9484 9489 ahci_port_t *ahci_portp, uint8_t port, uint32_t intr_status)
9485 9490 {
9486 9491 #ifndef __lock_lint
9487 9492 _NOTE(ARGUNUSED(intr_status))
9488 9493 #endif
9489 9494 uint32_t port_fbs_ctrl;
9490 9495 int loop_count = 0;
9491 9496 ahci_addr_t addr;
9492 9497
9493 9498 ASSERT(MUTEX_HELD(&ahci_portp->ahciport_mutex));
9494 9499
9495 9500 /* Nothing will be done under Command-based switching. */
9496 9501 if (!(ahci_ctlp->ahcictl_cap & AHCI_CAP_PMULT_FBSS))
9497 9502 return;
9498 9503
9499 9504 port_fbs_ctrl = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
9500 9505 (uint32_t *)AHCI_PORT_PxFBS(ahci_ctlp, port));
9501 9506
9502 9507 if (!(port_fbs_ctrl & AHCI_FBS_EN))
9503 9508 /* FBS is not enabled. */
9504 9509 return;
9505 9510
9506 9511 /* Problem's getting complicated now. */
9507 9512 /*
9508 9513 * If FIS-based switching is used, we need to check
9509 9514 * the PxFBS to see the error type.
9510 9515 */
9511 9516 port_fbs_ctrl = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
9512 9517 (uint32_t *)AHCI_PORT_PxFBS(ahci_ctlp, port));
9513 9518
9514 9519 /* Refer to spec(v1.2) 9.3.6.1 */
9515 9520 if (port_fbs_ctrl & AHCI_FBS_SDE) {
9516 9521 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp,
9517 9522 "A Device Sepcific Error: port %d", port);
9518 9523 /*
9519 9524 * Controller has paused commands for all other
9520 9525 * sub-devices until PxFBS.DEC is set.
9521 9526 */
9522 9527 ahci_reject_all_abort_pkts(ahci_ctlp,
9523 9528 ahci_portp, 0);
9524 9529
9525 9530 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle,
9526 9531 (uint32_t *)AHCI_PORT_PxFBS(ahci_ctlp, port),
9527 9532 port_fbs_ctrl | AHCI_FBS_DEC);
9528 9533
9529 9534 /*
9530 9535 * Wait controller clear PxFBS.DEC,
9531 9536 * then we can continue.
9532 9537 */
9533 9538 loop_count = 0;
9534 9539 do {
9535 9540 port_fbs_ctrl = ddi_get32(ahci_ctlp->
9536 9541 ahcictl_ahci_acc_handle, (uint32_t *)
9537 9542 AHCI_PORT_PxFBS(ahci_ctlp, port));
9538 9543
9539 9544 if (loop_count++ > 1000)
9540 9545 /*
9541 9546 * Esclate the error. Follow
9542 9547 * non-device specific error
9543 9548 * procedure.
9544 9549 */
9545 9550 return;
9546 9551
9547 9552 drv_usecwait(AHCI_100US_USECS);
9548 9553 } while (port_fbs_ctrl & AHCI_FBS_DEC);
9549 9554
9550 9555 /*
9551 9556 * Issue a software reset to ensure drive is in
9552 9557 * a known state.
9553 9558 */
9554 9559 (void) ahci_software_reset(ahci_ctlp,
9555 9560 ahci_portp, &addr);
9556 9561
9557 9562 } else {
9558 9563
9559 9564 /* Process Non-Device Specific Error. */
9560 9565 /* This will be handled later on. */
9561 9566 cmn_err(CE_NOTE, "!FBS is not supported now.");
9562 9567 }
9563 9568 }
9564 9569 /*
9565 9570 * Handle events - fatal error recovery
9566 9571 */
9567 9572 static void
9568 9573 ahci_events_handler(void *args)
9569 9574 {
9570 9575 ahci_event_arg_t *ahci_event_arg;
9571 9576 ahci_ctl_t *ahci_ctlp;
9572 9577 ahci_port_t *ahci_portp;
9573 9578 ahci_addr_t *addrp;
9574 9579 uint32_t event;
9575 9580 int instance;
9576 9581
9577 9582 ahci_event_arg = (ahci_event_arg_t *)args;
9578 9583
9579 9584 ahci_ctlp = ahci_event_arg->ahciea_ctlp;
9580 9585 ahci_portp = ahci_event_arg->ahciea_portp;
9581 9586 addrp = ahci_event_arg->ahciea_addrp;
9582 9587 event = ahci_event_arg->ahciea_event;
9583 9588 instance = ddi_get_instance(ahci_ctlp->ahcictl_dip);
9584 9589
9585 9590 AHCIDBG(AHCIDBG_ENTRY|AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp,
9586 9591 "ahci_events_handler enter: port %d intr_status = 0x%x",
9587 9592 ahci_portp->ahciport_port_num, event);
9588 9593
9589 9594 mutex_enter(&ahci_portp->ahciport_mutex);
9590 9595
9591 9596 /*
9592 9597 * ahci_intr_phyrdy_change() may have rendered it to
9593 9598 * SATA_DTYPE_NONE.
9594 9599 */
9595 9600 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) {
9596 9601 AHCIDBG(AHCIDBG_ENTRY|AHCIDBG_INTR, ahci_ctlp,
9597 9602 "ahci_events_handler: port %d no device attached, "
9598 9603 "and just return without doing anything",
9599 9604 ahci_portp->ahciport_port_num);
9600 9605
9601 9606 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_ERRPRINT) {
9602 9607 ahci_portp->ahciport_flags &= ~AHCI_PORT_FLAG_ERRPRINT;
9603 9608 cmn_err(CE_WARN, "!ahci%d: error recovery for port %d "
9604 9609 "succeed", instance, ahci_portp->ahciport_port_num);
9605 9610 }
9606 9611
9607 9612 goto out;
9608 9613 }
9609 9614
9610 9615 if (event & (AHCI_INTR_STATUS_IFS |
9611 9616 AHCI_INTR_STATUS_HBDS |
9612 9617 AHCI_INTR_STATUS_HBFS |
9613 9618 AHCI_INTR_STATUS_TFES))
9614 9619 ahci_fatal_error_recovery_handler(ahci_ctlp, ahci_portp,
9615 9620 addrp, event);
9616 9621
9617 9622 out:
9618 9623 mutex_exit(&ahci_portp->ahciport_mutex);
9619 9624 }
9620 9625
9621 9626 /*
9622 9627 * ahci_watchdog_handler() and ahci_do_sync_start will call us if they
9623 9628 * detect there are some commands which are timed out.
9624 9629 */
9625 9630 static void
9626 9631 ahci_timeout_pkts(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp,
9627 9632 uint8_t port, uint32_t tmp_timeout_tags)
9628 9633 {
9629 9634 uint32_t slot_status = 0;
9630 9635 uint32_t finished_tags = 0;
9631 9636 uint32_t timeout_tags = 0;
9632 9637
9633 9638 AHCIDBG(AHCIDBG_TIMEOUT|AHCIDBG_ENTRY, ahci_ctlp,
9634 9639 "ahci_timeout_pkts enter: port %d", port);
9635 9640
9636 9641 mutex_enter(&ahci_portp->ahciport_mutex);
9637 9642
9638 9643 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp) ||
9639 9644 RDWR_PMULT_CMD_IN_PROGRESS(ahci_portp) ||
9640 9645 ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) {
9641 9646 /* Read PxCI to see which commands are still outstanding */
9642 9647 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
9643 9648 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port));
9644 9649 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) {
9645 9650 /* Read PxSACT to see which commands are still outstanding */
9646 9651 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
9647 9652 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port));
9648 9653 }
9649 9654
9650 9655 #if AHCI_DEBUG
9651 9656 /*
9652 9657 * When AHCI_PORT_FLAG_RQSENSE or AHCI_PORT_FLAG_RDLOGEXT flag is
9653 9658 * set, it means a fatal error happened after REQUEST SENSE command
9654 9659 * or READ LOG EXT command is delivered to the HBA during the error
9655 9660 * recovery process. At this time, the only outstanding command is
9656 9661 * supposed to be REQUEST SENSE command or READ LOG EXT command.
9657 9662 */
9658 9663 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) {
9659 9664 AHCIDBG(AHCIDBG_ERRS|AHCIDBG_TIMEOUT, ahci_ctlp,
9660 9665 "ahci_timeout_pkts called while REQUEST SENSE "
9661 9666 "command or READ LOG EXT command for error recovery "
9662 9667 "timed out timeout_tags = 0x%x, slot_status = 0x%x, "
9663 9668 "pending_tags = 0x%x, pending_ncq_tags = 0x%x",
9664 9669 tmp_timeout_tags, slot_status,
9665 9670 ahci_portp->ahciport_pending_tags,
9666 9671 ahci_portp->ahciport_pending_ncq_tags);
9667 9672 ASSERT(slot_status == 0x1);
9668 9673 } else if (RDWR_PMULT_CMD_IN_PROGRESS(ahci_portp)) {
9669 9674 AHCIDBG(AHCIDBG_ERRS|AHCIDBG_TIMEOUT, ahci_ctlp,
9670 9675 "ahci_timeout_pkts called while executing R/W PMULT "
9671 9676 "command timeout_tags = 0x%x, slot_status = 0x%x",
9672 9677 tmp_timeout_tags, slot_status);
9673 9678 ASSERT(slot_status == 0x1);
9674 9679 }
9675 9680 #endif
9676 9681
9677 9682 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING;
9678 9683 ahci_portp->ahciport_mop_in_progress++;
9679 9684
9680 9685 (void) ahci_restart_port_wait_till_ready(ahci_ctlp, ahci_portp,
9681 9686 port, AHCI_PORT_RESET, NULL);
9682 9687
9683 9688 /*
9684 9689 * Re-identify timeout tags because some previously checked commands
9685 9690 * could already complete.
9686 9691 */
9687 9692 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) {
9688 9693 finished_tags = ahci_portp->ahciport_pending_tags &
9689 9694 ~slot_status & AHCI_SLOT_MASK(ahci_ctlp);
9690 9695 timeout_tags = tmp_timeout_tags & ~finished_tags;
9691 9696
9692 9697 AHCIDBG(AHCIDBG_TIMEOUT, ahci_ctlp,
9693 9698 "ahci_timeout_pkts: port %d, finished_tags = 0x%x, "
9694 9699 "timeout_tags = 0x%x, port_cmd_issue = 0x%x, "
9695 9700 "pending_tags = 0x%x ",
9696 9701 port, finished_tags, timeout_tags,
9697 9702 slot_status, ahci_portp->ahciport_pending_tags);
9698 9703 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) {
9699 9704 finished_tags = ahci_portp->ahciport_pending_ncq_tags &
9700 9705 ~slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp);
9701 9706 timeout_tags = tmp_timeout_tags & ~finished_tags;
9702 9707
9703 9708 AHCIDBG(AHCIDBG_TIMEOUT|AHCIDBG_NCQ, ahci_ctlp,
9704 9709 "ahci_timeout_pkts: port %d, finished_tags = 0x%x, "
9705 9710 "timeout_tags = 0x%x, port_sactive = 0x%x, "
9706 9711 "pending_ncq_tags = 0x%x ",
9707 9712 port, finished_tags, timeout_tags,
9708 9713 slot_status, ahci_portp->ahciport_pending_ncq_tags);
9709 9714 } else if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp) ||
9710 9715 RDWR_PMULT_CMD_IN_PROGRESS(ahci_portp)) {
9711 9716 timeout_tags = tmp_timeout_tags;
9712 9717 }
9713 9718
9714 9719 ahci_mop_commands(ahci_ctlp,
9715 9720 ahci_portp,
9716 9721 slot_status,
9717 9722 0, /* failed tags */
9718 9723 timeout_tags, /* timeout tags */
9719 9724 0, /* aborted tags */
9720 9725 0); /* reset tags */
9721 9726
9722 9727 mutex_exit(&ahci_portp->ahciport_mutex);
9723 9728 }
9724 9729
9725 9730 /*
9726 9731 * Watchdog handler kicks in every 5 seconds to timeout any commands pending
9727 9732 * for long time.
9728 9733 */
9729 9734 static void
9730 9735 ahci_watchdog_handler(ahci_ctl_t *ahci_ctlp)
9731 9736 {
9732 9737 ahci_port_t *ahci_portp;
9733 9738 sata_pkt_t *spkt;
9734 9739 uint32_t pending_tags;
9735 9740 uint32_t timeout_tags;
9736 9741 uint32_t port_cmd_status;
9737 9742 uint32_t port_sactive;
9738 9743 uint8_t port;
9739 9744 int tmp_slot;
9740 9745 int current_slot;
9741 9746 uint32_t current_tags;
9742 9747 int instance = ddi_get_instance(ahci_ctlp->ahcictl_dip);
9743 9748
9744 9749 mutex_enter(&ahci_ctlp->ahcictl_mutex);
9745 9750
9746 9751 AHCIDBG(AHCIDBG_ENTRY, ahci_ctlp,
9747 9752 "ahci_watchdog_handler entered", NULL);
9748 9753
9749 9754 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) {
9750 9755 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) {
9751 9756 continue;
9752 9757 }
9753 9758
9754 9759 ahci_portp = ahci_ctlp->ahcictl_ports[port];
9755 9760
9756 9761 mutex_enter(&ahci_portp->ahciport_mutex);
9757 9762 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) {
9758 9763 mutex_exit(&ahci_portp->ahciport_mutex);
9759 9764 continue;
9760 9765 }
9761 9766
9762 9767 /* Skip the check for those ports in error recovery */
9763 9768 if ((ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) &&
9764 9769 !(ERR_RETRI_CMD_IN_PROGRESS(ahci_portp))) {
9765 9770 mutex_exit(&ahci_portp->ahciport_mutex);
9766 9771 continue;
9767 9772 }
9768 9773
9769 9774 pending_tags = 0;
9770 9775 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle,
9771 9776 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port));
9772 9777
9773 9778 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp) ||
9774 9779 RDWR_PMULT_CMD_IN_PROGRESS(ahci_portp)) {
9775 9780 current_slot = 0;
9776 9781 pending_tags = 0x1;
9777 9782 } else if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) {
9778 9783 current_slot =
9779 9784 (port_cmd_status & AHCI_CMD_STATUS_CCS) >>
9780 9785 AHCI_CMD_STATUS_CCS_SHIFT;
9781 9786 pending_tags = ahci_portp->ahciport_pending_tags;
9782 9787 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) {
9783 9788 port_sactive = ddi_get32(
9784 9789 ahci_ctlp->ahcictl_ahci_acc_handle,
9785 9790 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port));
9786 9791 current_tags = port_sactive &
9787 9792 ~port_cmd_status &
9788 9793 AHCI_NCQ_SLOT_MASK(ahci_portp);
9789 9794 pending_tags = ahci_portp->ahciport_pending_ncq_tags;
9790 9795 }
9791 9796
9792 9797 timeout_tags = 0;
9793 9798 while (pending_tags) {
9794 9799 tmp_slot = ddi_ffs(pending_tags) - 1;
9795 9800 if (tmp_slot == -1) {
9796 9801 break;
9797 9802 }
9798 9803
9799 9804 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp))
9800 9805 spkt = ahci_portp->ahciport_err_retri_pkt;
9801 9806 else if (RDWR_PMULT_CMD_IN_PROGRESS(ahci_portp))
9802 9807 spkt = ahci_portp->ahciport_rdwr_pmult_pkt;
9803 9808 else
9804 9809 spkt = ahci_portp->ahciport_slot_pkts[tmp_slot];
9805 9810
9806 9811 if ((spkt != NULL) && spkt->satapkt_time &&
9807 9812 !(spkt->satapkt_op_mode & SATA_OPMODE_POLLING)) {
9808 9813 /*
9809 9814 * If a packet has survived for more than it's
9810 9815 * max life cycles, it is a candidate for time
9811 9816 * out.
9812 9817 */
9813 9818 ahci_portp->ahciport_slot_timeout[tmp_slot] -=
9814 9819 ahci_watchdog_timeout;
9815 9820
9816 9821 if (ahci_portp->ahciport_slot_timeout[tmp_slot]
9817 9822 > 0)
9818 9823 goto next;
9819 9824
9820 9825 #if AHCI_DEBUG
9821 9826 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) {
9822 9827 AHCIDBG(AHCIDBG_ERRS|AHCIDBG_TIMEOUT,
9823 9828 ahci_ctlp, "watchdog: the current "
9824 9829 "tags is 0x%x", current_tags);
9825 9830 } else {
9826 9831 AHCIDBG(AHCIDBG_ERRS|AHCIDBG_TIMEOUT,
9827 9832 ahci_ctlp, "watchdog: the current "
9828 9833 "slot is %d", current_slot);
9829 9834 }
9830 9835 #endif
9831 9836
9832 9837 /*
9833 9838 * We need to check whether the HBA has
9834 9839 * begun to execute the command, if not,
9835 9840 * then re-set the timer of the command.
9836 9841 */
9837 9842 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp) &&
9838 9843 (tmp_slot != current_slot) ||
9839 9844 NCQ_CMD_IN_PROGRESS(ahci_portp) &&
9840 9845 ((0x1 << tmp_slot) & current_tags)) {
9841 9846 ahci_portp->ahciport_slot_timeout \
9842 9847 [tmp_slot] = spkt->satapkt_time;
9843 9848 } else {
9844 9849 timeout_tags |= (0x1 << tmp_slot);
9845 9850 cmn_err(CE_WARN, "!ahci%d: watchdog "
9846 9851 "port %d satapkt 0x%p timed out\n",
9847 9852 instance, port, (void *)spkt);
9848 9853 }
9849 9854 }
9850 9855 next:
9851 9856 CLEAR_BIT(pending_tags, tmp_slot);
9852 9857 }
9853 9858
9854 9859 if (timeout_tags) {
9855 9860 mutex_exit(&ahci_portp->ahciport_mutex);
9856 9861 mutex_exit(&ahci_ctlp->ahcictl_mutex);
9857 9862 ahci_timeout_pkts(ahci_ctlp, ahci_portp,
9858 9863 port, timeout_tags);
9859 9864 mutex_enter(&ahci_ctlp->ahcictl_mutex);
9860 9865 mutex_enter(&ahci_portp->ahciport_mutex);
9861 9866 }
9862 9867
9863 9868 mutex_exit(&ahci_portp->ahciport_mutex);
9864 9869 }
9865 9870
9866 9871 /* Re-install the watchdog timeout handler */
9867 9872 if (ahci_ctlp->ahcictl_timeout_id != 0) {
9868 9873 ahci_ctlp->ahcictl_timeout_id =
9869 9874 timeout((void (*)(void *))ahci_watchdog_handler,
9870 9875 (caddr_t)ahci_ctlp, ahci_watchdog_tick);
9871 9876 }
9872 9877
9873 9878 mutex_exit(&ahci_ctlp->ahcictl_mutex);
9874 9879 }
9875 9880
9876 9881 /*
9877 9882 * Fill the error context into sata_cmd for non-queued command error.
9878 9883 */
9879 9884 static void
9880 9885 ahci_copy_err_cnxt(sata_cmd_t *scmd, ahci_fis_d2h_register_t *rfisp)
9881 9886 {
9882 9887 scmd->satacmd_status_reg = GET_RFIS_STATUS(rfisp);
9883 9888 scmd->satacmd_error_reg = GET_RFIS_ERROR(rfisp);
9884 9889 scmd->satacmd_sec_count_lsb = GET_RFIS_SECTOR_COUNT(rfisp);
9885 9890 scmd->satacmd_lba_low_lsb = GET_RFIS_CYL_LOW(rfisp);
9886 9891 scmd->satacmd_lba_mid_lsb = GET_RFIS_CYL_MID(rfisp);
9887 9892 scmd->satacmd_lba_high_lsb = GET_RFIS_CYL_HI(rfisp);
9888 9893 scmd->satacmd_device_reg = GET_RFIS_DEV_HEAD(rfisp);
9889 9894
9890 9895 if (scmd->satacmd_addr_type == ATA_ADDR_LBA48) {
9891 9896 scmd->satacmd_sec_count_msb = GET_RFIS_SECTOR_COUNT_EXP(rfisp);
9892 9897 scmd->satacmd_lba_low_msb = GET_RFIS_CYL_LOW_EXP(rfisp);
9893 9898 scmd->satacmd_lba_mid_msb = GET_RFIS_CYL_MID_EXP(rfisp);
9894 9899 scmd->satacmd_lba_high_msb = GET_RFIS_CYL_HI_EXP(rfisp);
9895 9900 }
9896 9901 }
9897 9902
9898 9903 /*
9899 9904 * Fill the ncq error page into sata_cmd for queued command error.
9900 9905 */
9901 9906 static void
9902 9907 ahci_copy_ncq_err_page(sata_cmd_t *scmd,
9903 9908 struct sata_ncq_error_recovery_page *ncq_err_page)
9904 9909 {
9905 9910 scmd->satacmd_sec_count_msb = ncq_err_page->ncq_sector_count_ext;
9906 9911 scmd->satacmd_sec_count_lsb = ncq_err_page->ncq_sector_count;
9907 9912 scmd->satacmd_lba_low_msb = ncq_err_page->ncq_sector_number_ext;
9908 9913 scmd->satacmd_lba_low_lsb = ncq_err_page->ncq_sector_number;
9909 9914 scmd->satacmd_lba_mid_msb = ncq_err_page->ncq_cyl_low_ext;
9910 9915 scmd->satacmd_lba_mid_lsb = ncq_err_page->ncq_cyl_low;
9911 9916 scmd->satacmd_lba_high_msb = ncq_err_page->ncq_cyl_high_ext;
9912 9917 scmd->satacmd_lba_high_lsb = ncq_err_page->ncq_cyl_high;
9913 9918 scmd->satacmd_device_reg = ncq_err_page->ncq_dev_head;
9914 9919 scmd->satacmd_status_reg = ncq_err_page->ncq_status;
9915 9920 scmd->satacmd_error_reg = ncq_err_page->ncq_error;
9916 9921 }
9917 9922
9918 9923 /*
9919 9924 * Put the respective register value to sata_cmd_t for satacmd_flags.
9920 9925 */
9921 9926 static void
9922 9927 ahci_copy_out_regs(sata_cmd_t *scmd, ahci_fis_d2h_register_t *rfisp)
9923 9928 {
9924 9929 if (scmd->satacmd_flags.sata_copy_out_sec_count_msb)
9925 9930 scmd->satacmd_sec_count_msb = GET_RFIS_SECTOR_COUNT_EXP(rfisp);
9926 9931 if (scmd->satacmd_flags.sata_copy_out_lba_low_msb)
9927 9932 scmd->satacmd_lba_low_msb = GET_RFIS_CYL_LOW_EXP(rfisp);
9928 9933 if (scmd->satacmd_flags.sata_copy_out_lba_mid_msb)
9929 9934 scmd->satacmd_lba_mid_msb = GET_RFIS_CYL_MID_EXP(rfisp);
9930 9935 if (scmd->satacmd_flags.sata_copy_out_lba_high_msb)
9931 9936 scmd->satacmd_lba_high_msb = GET_RFIS_CYL_HI_EXP(rfisp);
9932 9937 if (scmd->satacmd_flags.sata_copy_out_sec_count_lsb)
9933 9938 scmd->satacmd_sec_count_lsb = GET_RFIS_SECTOR_COUNT(rfisp);
9934 9939 if (scmd->satacmd_flags.sata_copy_out_lba_low_lsb)
9935 9940 scmd->satacmd_lba_low_lsb = GET_RFIS_CYL_LOW(rfisp);
9936 9941 if (scmd->satacmd_flags.sata_copy_out_lba_mid_lsb)
9937 9942 scmd->satacmd_lba_mid_lsb = GET_RFIS_CYL_MID(rfisp);
9938 9943 if (scmd->satacmd_flags.sata_copy_out_lba_high_lsb)
9939 9944 scmd->satacmd_lba_high_lsb = GET_RFIS_CYL_HI(rfisp);
9940 9945 if (scmd->satacmd_flags.sata_copy_out_device_reg)
9941 9946 scmd->satacmd_device_reg = GET_RFIS_DEV_HEAD(rfisp);
9942 9947 if (scmd->satacmd_flags.sata_copy_out_error_reg)
9943 9948 scmd->satacmd_error_reg = GET_RFIS_ERROR(rfisp);
9944 9949 }
9945 9950
9946 9951 static void
9947 9952 ahci_log_fatal_error_message(ahci_ctl_t *ahci_ctlp, uint8_t port,
9948 9953 uint32_t intr_status)
9949 9954 {
9950 9955 int instance = ddi_get_instance(ahci_ctlp->ahcictl_dip);
9951 9956
9952 9957 if (intr_status & AHCI_INTR_STATUS_IFS)
9953 9958 cmn_err(CE_WARN, "!ahci%d: ahci port %d has interface fatal "
9954 9959 "error", instance, port);
9955 9960
9956 9961 if (intr_status & AHCI_INTR_STATUS_HBDS)
9957 9962 cmn_err(CE_WARN, "!ahci%d: ahci port %d has bus data error",
9958 9963 instance, port);
9959 9964
9960 9965 if (intr_status & AHCI_INTR_STATUS_HBFS)
9961 9966 cmn_err(CE_WARN, "!ahci%d: ahci port %d has bus fatal error",
9962 9967 instance, port);
9963 9968
9964 9969 if (intr_status & AHCI_INTR_STATUS_TFES)
9965 9970 cmn_err(CE_WARN, "!ahci%d: ahci port %d has task file error",
9966 9971 instance, port);
9967 9972
9968 9973 cmn_err(CE_WARN, "!ahci%d: ahci port %d is trying to do error "
9969 9974 "recovery", instance, port);
9970 9975 }
9971 9976
9972 9977 static void
9973 9978 ahci_dump_commands(ahci_ctl_t *ahci_ctlp, uint8_t port,
9974 9979 uint32_t slot_tags)
9975 9980 {
9976 9981 ahci_port_t *ahci_portp;
9977 9982 int tmp_slot;
9978 9983 sata_pkt_t *spkt;
9979 9984 sata_cmd_t cmd;
9980 9985
9981 9986 ahci_portp = ahci_ctlp->ahcictl_ports[port];
9982 9987 ASSERT(ahci_portp != NULL);
9983 9988
9984 9989 while (slot_tags) {
9985 9990 tmp_slot = ddi_ffs(slot_tags) - 1;
9986 9991 if (tmp_slot == -1) {
9987 9992 break;
9988 9993 }
9989 9994
9990 9995 spkt = ahci_portp->ahciport_slot_pkts[tmp_slot];
9991 9996 ASSERT(spkt != NULL);
9992 9997 cmd = spkt->satapkt_cmd;
9993 9998
9994 9999 cmn_err(CE_WARN, "!satapkt 0x%p: cmd_reg = 0x%x "
9995 10000 "features_reg = 0x%x sec_count_msb = 0x%x "
9996 10001 "lba_low_msb = 0x%x lba_mid_msb = 0x%x "
9997 10002 "lba_high_msb = 0x%x sec_count_lsb = 0x%x "
9998 10003 "lba_low_lsb = 0x%x lba_mid_lsb = 0x%x "
9999 10004 "lba_high_lsb = 0x%x device_reg = 0x%x "
10000 10005 "addr_type = 0x%x cmd_flags = 0x%x", (void *)spkt,
10001 10006 cmd.satacmd_cmd_reg, cmd.satacmd_features_reg,
10002 10007 cmd.satacmd_sec_count_msb, cmd.satacmd_lba_low_msb,
10003 10008 cmd.satacmd_lba_mid_msb, cmd.satacmd_lba_high_msb,
10004 10009 cmd.satacmd_sec_count_lsb, cmd.satacmd_lba_low_lsb,
10005 10010 cmd.satacmd_lba_mid_lsb, cmd.satacmd_lba_high_lsb,
10006 10011 cmd.satacmd_device_reg, cmd.satacmd_addr_type,
10007 10012 *((uint32_t *)&(cmd.satacmd_flags)));
10008 10013
10009 10014 CLEAR_BIT(slot_tags, tmp_slot);
10010 10015 }
10011 10016 }
10012 10017
10013 10018 /*
10014 10019 * Dump the serror message to the log.
10015 10020 */
10016 10021 static void
10017 10022 ahci_log_serror_message(ahci_ctl_t *ahci_ctlp, uint8_t port,
10018 10023 uint32_t port_serror, int debug_only)
10019 10024 {
10020 10025 static char err_buf[512];
10021 10026 static char err_msg_header[16];
10022 10027 char *err_msg = err_buf;
10023 10028
10024 10029 *err_buf = '\0';
10025 10030 *err_msg_header = '\0';
10026 10031
10027 10032 if (port_serror & SERROR_DATA_ERR_FIXED) {
10028 10033 err_msg = strcat(err_msg,
10029 10034 "\tRecovered Data Integrity Error (I)\n");
10030 10035 }
10031 10036
10032 10037 if (port_serror & SERROR_COMM_ERR_FIXED) {
10033 10038 err_msg = strcat(err_msg,
10034 10039 "\tRecovered Communication Error (M)\n");
10035 10040 }
10036 10041
10037 10042 if (port_serror & SERROR_DATA_ERR) {
10038 10043 err_msg = strcat(err_msg,
10039 10044 "\tTransient Data Integrity Error (T)\n");
10040 10045 }
10041 10046
10042 10047 if (port_serror & SERROR_PERSISTENT_ERR) {
10043 10048 err_msg = strcat(err_msg,
10044 10049 "\tPersistent Communication or Data Integrity Error (C)\n");
10045 10050 }
10046 10051
10047 10052 if (port_serror & SERROR_PROTOCOL_ERR) {
10048 10053 err_msg = strcat(err_msg, "\tProtocol Error (P)\n");
10049 10054 }
10050 10055
10051 10056 if (port_serror & SERROR_INT_ERR) {
10052 10057 err_msg = strcat(err_msg, "\tInternal Error (E)\n");
10053 10058 }
10054 10059
10055 10060 if (port_serror & SERROR_PHY_RDY_CHG) {
10056 10061 err_msg = strcat(err_msg, "\tPhyRdy Change (N)\n");
10057 10062 }
10058 10063
10059 10064 if (port_serror & SERROR_PHY_INT_ERR) {
10060 10065 err_msg = strcat(err_msg, "\tPhy Internal Error (I)\n");
10061 10066 }
10062 10067
10063 10068 if (port_serror & SERROR_COMM_WAKE) {
10064 10069 err_msg = strcat(err_msg, "\tComm Wake (W)\n");
10065 10070 }
10066 10071
10067 10072 if (port_serror & SERROR_10B_TO_8B_ERR) {
10068 10073 err_msg = strcat(err_msg, "\t10B to 8B Decode Error (B)\n");
10069 10074 }
10070 10075
10071 10076 if (port_serror & SERROR_DISPARITY_ERR) {
10072 10077 err_msg = strcat(err_msg, "\tDisparity Error (D)\n");
10073 10078 }
10074 10079
10075 10080 if (port_serror & SERROR_CRC_ERR) {
10076 10081 err_msg = strcat(err_msg, "\tCRC Error (C)\n");
10077 10082 }
10078 10083
10079 10084 if (port_serror & SERROR_HANDSHAKE_ERR) {
10080 10085 err_msg = strcat(err_msg, "\tHandshake Error (H)\n");
10081 10086 }
10082 10087
10083 10088 if (port_serror & SERROR_LINK_SEQ_ERR) {
10084 10089 err_msg = strcat(err_msg, "\tLink Sequence Error (S)\n");
10085 10090 }
10086 10091
10087 10092 if (port_serror & SERROR_TRANS_ERR) {
10088 10093 err_msg = strcat(err_msg,
10089 10094 "\tTransport state transition error (T)\n");
10090 10095 }
10091 10096
10092 10097 if (port_serror & SERROR_FIS_TYPE) {
10093 10098 err_msg = strcat(err_msg, "\tUnknown FIS Type (F)\n");
10094 10099 }
10095 10100
10096 10101 if (port_serror & SERROR_EXCHANGED_ERR) {
10097 10102 err_msg = strcat(err_msg, "\tExchanged (X)\n");
10098 10103 }
10099 10104
10100 10105 if (*err_msg == '\0')
10101 10106 return;
10102 10107
10103 10108 if (debug_only) {
10104 10109 (void) sprintf(err_msg_header, "port %d", port);
10105 10110 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp, err_msg_header, NULL);
10106 10111 AHCIDBG(AHCIDBG_ERRS, ahci_ctlp, err_msg, NULL);
10107 10112 } else if (ahci_ctlp) {
10108 10113 cmn_err(CE_WARN, "!ahci%d: %s %s",
10109 10114 ddi_get_instance(ahci_ctlp->ahcictl_dip),
10110 10115 err_msg_header, err_msg);
10111 10116
10112 10117 /* sata trace debug */
10113 10118 sata_trace_debug(ahci_ctlp->ahcictl_dip,
10114 10119 "ahci%d: %s %s", ddi_get_instance(ahci_ctlp->ahcictl_dip),
10115 10120 err_msg_header, err_msg);
10116 10121 } else {
10117 10122 cmn_err(CE_WARN, "!ahci: %s %s", err_msg_header, err_msg);
10118 10123
10119 10124 /* sata trace debug */
10120 10125 sata_trace_debug(NULL, "ahci: %s %s", err_msg_header, err_msg);
10121 10126 }
10122 10127 }
10123 10128
10124 10129 /*
10125 10130 * Translate the sata_address_t type into the ahci_addr_t type.
10126 10131 * sata_device.satadev_addr structure is used as source.
10127 10132 */
10128 10133 static void
10129 10134 ahci_get_ahci_addr(ahci_ctl_t *ahci_ctlp, sata_device_t *sd,
10130 10135 ahci_addr_t *ahci_addrp)
10131 10136 {
10132 10137 sata_address_t *sata_addrp = &sd->satadev_addr;
10133 10138 ahci_addrp->aa_port =
10134 10139 ahci_ctlp->ahcictl_cport_to_port[sata_addrp->cport];
10135 10140 ahci_addrp->aa_pmport = sata_addrp->pmport;
10136 10141
10137 10142 switch (sata_addrp->qual) {
10138 10143 case SATA_ADDR_DCPORT:
10139 10144 case SATA_ADDR_CPORT:
10140 10145 ahci_addrp->aa_qual = AHCI_ADDR_PORT;
10141 10146 break;
10142 10147 case SATA_ADDR_PMULT:
10143 10148 case SATA_ADDR_PMULT_SPEC:
10144 10149 ahci_addrp->aa_qual = AHCI_ADDR_PMULT;
10145 10150 break;
10146 10151 case SATA_ADDR_DPMPORT:
10147 10152 case SATA_ADDR_PMPORT:
10148 10153 ahci_addrp->aa_qual = AHCI_ADDR_PMPORT;
10149 10154 break;
10150 10155 case SATA_ADDR_NULL:
10151 10156 default:
10152 10157 /* something went wrong */
10153 10158 ahci_addrp->aa_qual = AHCI_ADDR_NULL;
10154 10159 break;
10155 10160 }
10156 10161 }
10157 10162
10158 10163 /*
10159 10164 * This routine is to calculate the total number of ports implemented
10160 10165 * by the HBA.
10161 10166 */
10162 10167 static int
10163 10168 ahci_get_num_implemented_ports(uint32_t ports_implemented)
10164 10169 {
10165 10170 uint8_t i;
10166 10171 int num = 0;
10167 10172
10168 10173 for (i = 0; i < AHCI_MAX_PORTS; i++) {
10169 10174 if (((uint32_t)0x1 << i) & ports_implemented)
10170 10175 num++;
10171 10176 }
10172 10177
10173 10178 return (num);
10174 10179 }
10175 10180
10176 10181 #if AHCI_DEBUG
10177 10182 static void
10178 10183 ahci_log(ahci_ctl_t *ahci_ctlp, uint_t level, char *fmt, ...)
10179 10184 {
10180 10185 static char name[16];
10181 10186 va_list ap;
10182 10187
10183 10188 mutex_enter(&ahci_log_mutex);
10184 10189
10185 10190 va_start(ap, fmt);
10186 10191 if (ahci_ctlp) {
10187 10192 (void) sprintf(name, "ahci%d: ",
10188 10193 ddi_get_instance(ahci_ctlp->ahcictl_dip));
10189 10194 } else {
10190 10195 (void) sprintf(name, "ahci: ");
10191 10196 }
10192 10197
10193 10198 (void) vsprintf(ahci_log_buf, fmt, ap);
10194 10199 va_end(ap);
10195 10200
10196 10201 cmn_err(level, "%s%s", name, ahci_log_buf);
10197 10202
10198 10203 mutex_exit(&ahci_log_mutex);
10199 10204 }
10200 10205 #endif
10201 10206
10202 10207 /*
10203 10208 * quiesce(9E) entry point.
10204 10209 *
10205 10210 * This function is called when the system is single-threaded at high
10206 10211 * PIL with preemption disabled. Therefore, this function must not be
10207 10212 * blocked.
10208 10213 *
10209 10214 * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure.
10210 10215 * DDI_FAILURE indicates an error condition and should almost never happen.
10211 10216 */
10212 10217 static int
10213 10218 ahci_quiesce(dev_info_t *dip)
10214 10219 {
10215 10220 ahci_ctl_t *ahci_ctlp;
10216 10221 ahci_port_t *ahci_portp;
10217 10222 int instance, port;
10218 10223
10219 10224 instance = ddi_get_instance(dip);
10220 10225 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance);
10221 10226
10222 10227 if (ahci_ctlp == NULL)
10223 10228 return (DDI_FAILURE);
10224 10229
10225 10230 #if AHCI_DEBUG
10226 10231 ahci_debug_flags = 0;
10227 10232 #endif
10228 10233
10229 10234 ahci_ctlp->ahcictl_flags |= AHCI_QUIESCE;
10230 10235
10231 10236 /* disable all the interrupts. */
10232 10237 ahci_disable_all_intrs(ahci_ctlp);
10233 10238
10234 10239 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) {
10235 10240 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) {
10236 10241 continue;
10237 10242 }
10238 10243
10239 10244 ahci_portp = ahci_ctlp->ahcictl_ports[port];
10240 10245
10241 10246 /*
10242 10247 * Stop the port by clearing PxCMD.ST
10243 10248 *
10244 10249 * Here we must disable the port interrupt because
10245 10250 * ahci_disable_all_intrs only clear GHC.IE, and IS
10246 10251 * register will be still set if PxIE is enabled.
10247 10252 * When ahci shares one IRQ with other drivers, the
10248 10253 * intr handler may claim the intr mistakenly.
10249 10254 */
10250 10255 ahci_disable_port_intrs(ahci_ctlp, port);
10251 10256 (void) ahci_put_port_into_notrunning_state(ahci_ctlp,
10252 10257 ahci_portp, port);
10253 10258 }
10254 10259
10255 10260 ahci_ctlp->ahcictl_flags &= ~AHCI_QUIESCE;
10256 10261
10257 10262 return (DDI_SUCCESS);
10258 10263 }
10259 10264
10260 10265 /*
10261 10266 * The function will add a sata packet to the done queue.
10262 10267 */
10263 10268 static void
10264 10269 ahci_add_doneq(ahci_port_t *ahci_portp, sata_pkt_t *satapkt, int reason)
10265 10270 {
10266 10271 ASSERT(satapkt != NULL);
10267 10272 ASSERT(MUTEX_HELD(&ahci_portp->ahciport_mutex));
10268 10273
10269 10274 /* set the reason for all packets */
10270 10275 satapkt->satapkt_reason = reason;
10271 10276 satapkt->satapkt_hba_driver_private = NULL;
10272 10277
10273 10278 if (! (satapkt->satapkt_op_mode & SATA_OPMODE_SYNCH) &&
10274 10279 satapkt->satapkt_comp) {
10275 10280 /*
10276 10281 * only add to queue when mode is not synch and there is
10277 10282 * completion callback
10278 10283 */
10279 10284 *ahci_portp->ahciport_doneqtail = satapkt;
10280 10285 ahci_portp->ahciport_doneqtail =
10281 10286 (sata_pkt_t **)&(satapkt->satapkt_hba_driver_private);
10282 10287 ahci_portp->ahciport_doneq_len++;
10283 10288
10284 10289 } else if ((satapkt->satapkt_op_mode & SATA_OPMODE_SYNCH) &&
10285 10290 ! (satapkt->satapkt_op_mode & SATA_OPMODE_POLLING))
10286 10291 /*
10287 10292 * for sync/non-poll mode, just call cv_broadcast
10288 10293 */
10289 10294 cv_broadcast(&ahci_portp->ahciport_cv);
10290 10295 }
10291 10296
10292 10297 /*
10293 10298 * The function will call completion callback of sata packet on the
10294 10299 * completed queue
10295 10300 */
10296 10301 static void
10297 10302 ahci_flush_doneq(ahci_port_t *ahci_portp)
10298 10303 {
10299 10304 sata_pkt_t *satapkt, *next;
10300 10305
10301 10306 ASSERT(MUTEX_HELD(&ahci_portp->ahciport_mutex));
10302 10307
10303 10308 if (ahci_portp->ahciport_doneq) {
10304 10309 satapkt = ahci_portp->ahciport_doneq;
10305 10310
10306 10311 ahci_portp->ahciport_doneq = NULL;
10307 10312 ahci_portp->ahciport_doneqtail = &ahci_portp->ahciport_doneq;
10308 10313 ahci_portp->ahciport_doneq_len = 0;
10309 10314
10310 10315 mutex_exit(&ahci_portp->ahciport_mutex);
10311 10316
10312 10317 while (satapkt != NULL) {
10313 10318 next = satapkt->satapkt_hba_driver_private;
10314 10319 satapkt->satapkt_hba_driver_private = NULL;
10315 10320
10316 10321 /* Call the callback */
10317 10322 (*satapkt->satapkt_comp)(satapkt);
10318 10323
10319 10324 satapkt = next;
10320 10325 }
10321 10326
10322 10327 mutex_enter(&ahci_portp->ahciport_mutex);
10323 10328 }
10324 10329 }
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