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9578 HVM fails assertion in opteron_get_nnodes() with a Opteron 6262 HE CPU on the host system
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--- old/usr/src/uts/i86pc/os/mp_startup.c
+++ new/usr/src/uts/i86pc/os/mp_startup.c
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
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21 21
22 22 /*
23 23 * Copyright (c) 1992, 2010, Oracle and/or its affiliates. All rights reserved.
24 24 */
25 25 /*
26 26 * Copyright (c) 2010, Intel Corporation.
27 27 * All rights reserved.
28 28 */
29 29 /*
30 30 * Copyright 2018 Joyent, Inc.
31 - * Copyright 2013 Nexenta Systems, Inc. All rights reserved.
31 + * Copyright 2018 Nexenta Systems, Inc.
32 32 * Copyright 2018 OmniOS Community Edition (OmniOSce) Association.
33 33 */
34 34
35 35 #include <sys/types.h>
36 36 #include <sys/thread.h>
37 37 #include <sys/cpuvar.h>
38 38 #include <sys/cpu.h>
39 39 #include <sys/t_lock.h>
40 40 #include <sys/param.h>
41 41 #include <sys/proc.h>
42 42 #include <sys/disp.h>
43 43 #include <sys/class.h>
44 44 #include <sys/cmn_err.h>
45 45 #include <sys/debug.h>
46 46 #include <sys/note.h>
47 47 #include <sys/asm_linkage.h>
48 48 #include <sys/x_call.h>
49 49 #include <sys/systm.h>
50 50 #include <sys/var.h>
51 51 #include <sys/vtrace.h>
52 52 #include <vm/hat.h>
53 53 #include <vm/as.h>
54 54 #include <vm/seg_kmem.h>
55 55 #include <vm/seg_kp.h>
56 56 #include <sys/segments.h>
57 57 #include <sys/kmem.h>
58 58 #include <sys/stack.h>
59 59 #include <sys/smp_impldefs.h>
60 60 #include <sys/x86_archext.h>
61 61 #include <sys/machsystm.h>
62 62 #include <sys/traptrace.h>
63 63 #include <sys/clock.h>
64 64 #include <sys/cpc_impl.h>
65 65 #include <sys/pg.h>
66 66 #include <sys/cmt.h>
67 67 #include <sys/dtrace.h>
68 68 #include <sys/archsystm.h>
69 69 #include <sys/fp.h>
70 70 #include <sys/reboot.h>
71 71 #include <sys/kdi_machimpl.h>
72 72 #include <vm/hat_i86.h>
73 73 #include <vm/vm_dep.h>
74 74 #include <sys/memnode.h>
75 75 #include <sys/pci_cfgspace.h>
76 76 #include <sys/mach_mmu.h>
77 77 #include <sys/sysmacros.h>
78 78 #if defined(__xpv)
79 79 #include <sys/hypervisor.h>
80 80 #endif
81 81 #include <sys/cpu_module.h>
82 82 #include <sys/ontrap.h>
83 83
84 84 struct cpu cpus[1] __aligned(MMU_PAGESIZE);
85 85 struct cpu *cpu[NCPU] = {&cpus[0]};
86 86 struct cpu *cpu_free_list;
87 87 cpu_core_t cpu_core[NCPU];
88 88
89 89 #define cpu_next_free cpu_prev
90 90
91 91 /*
92 92 * Useful for disabling MP bring-up on a MP capable system.
93 93 */
94 94 int use_mp = 1;
95 95
96 96 /*
97 97 * to be set by a PSM to indicate what cpus
98 98 * are sitting around on the system.
99 99 */
100 100 cpuset_t mp_cpus;
101 101
102 102 /*
103 103 * This variable is used by the hat layer to decide whether or not
104 104 * critical sections are needed to prevent race conditions. For sun4m,
105 105 * this variable is set once enough MP initialization has been done in
106 106 * order to allow cross calls.
107 107 */
108 108 int flushes_require_xcalls;
109 109
110 110 cpuset_t cpu_ready_set; /* initialized in startup() */
111 111
112 112 static void mp_startup_boot(void);
113 113 static void mp_startup_hotplug(void);
114 114
115 115 static void cpu_sep_enable(void);
116 116 static void cpu_sep_disable(void);
117 117 static void cpu_asysc_enable(void);
118 118 static void cpu_asysc_disable(void);
119 119
120 120 /*
121 121 * Init CPU info - get CPU type info for processor_info system call.
122 122 */
123 123 void
124 124 init_cpu_info(struct cpu *cp)
125 125 {
126 126 processor_info_t *pi = &cp->cpu_type_info;
127 127
128 128 /*
129 129 * Get clock-frequency property for the CPU.
130 130 */
131 131 pi->pi_clock = cpu_freq;
132 132
133 133 /*
134 134 * Current frequency in Hz.
135 135 */
136 136 cp->cpu_curr_clock = cpu_freq_hz;
137 137
138 138 /*
139 139 * Supported frequencies.
140 140 */
141 141 if (cp->cpu_supp_freqs == NULL) {
142 142 cpu_set_supp_freqs(cp, NULL);
143 143 }
144 144
145 145 (void) strcpy(pi->pi_processor_type, "i386");
146 146 if (fpu_exists)
147 147 (void) strcpy(pi->pi_fputypes, "i387 compatible");
148 148
149 149 cp->cpu_idstr = kmem_zalloc(CPU_IDSTRLEN, KM_SLEEP);
150 150 cp->cpu_brandstr = kmem_zalloc(CPU_IDSTRLEN, KM_SLEEP);
151 151
152 152 /*
153 153 * If called for the BSP, cp is equal to current CPU.
154 154 * For non-BSPs, cpuid info of cp is not ready yet, so use cpuid info
155 155 * of current CPU as default values for cpu_idstr and cpu_brandstr.
156 156 * They will be corrected in mp_startup_common() after cpuid_pass1()
157 157 * has been invoked on target CPU.
158 158 */
159 159 (void) cpuid_getidstr(CPU, cp->cpu_idstr, CPU_IDSTRLEN);
160 160 (void) cpuid_getbrandstr(CPU, cp->cpu_brandstr, CPU_IDSTRLEN);
161 161 }
162 162
163 163 /*
164 164 * Configure syscall support on this CPU.
165 165 */
166 166 /*ARGSUSED*/
167 167 void
168 168 init_cpu_syscall(struct cpu *cp)
169 169 {
170 170 kpreempt_disable();
171 171
172 172 if (is_x86_feature(x86_featureset, X86FSET_MSR) &&
173 173 is_x86_feature(x86_featureset, X86FSET_ASYSC)) {
174 174 uint64_t flags;
175 175
176 176 #if !defined(__xpv)
177 177 /*
178 178 * The syscall instruction imposes a certain ordering on
179 179 * segment selectors, so we double-check that ordering
180 180 * here.
181 181 */
182 182 CTASSERT(KDS_SEL == KCS_SEL + 8);
183 183 CTASSERT(UDS_SEL == U32CS_SEL + 8);
184 184 CTASSERT(UCS_SEL == U32CS_SEL + 16);
185 185 #endif
186 186
187 187 /*
188 188 * Turn syscall/sysret extensions on.
189 189 */
190 190 cpu_asysc_enable();
191 191
192 192 /*
193 193 * Program the magic registers ..
194 194 */
195 195 wrmsr(MSR_AMD_STAR,
196 196 ((uint64_t)(U32CS_SEL << 16 | KCS_SEL)) << 32);
197 197 if (kpti_enable == 1) {
198 198 wrmsr(MSR_AMD_LSTAR,
199 199 (uint64_t)(uintptr_t)tr_sys_syscall);
200 200 wrmsr(MSR_AMD_CSTAR,
201 201 (uint64_t)(uintptr_t)tr_sys_syscall32);
202 202 } else {
203 203 wrmsr(MSR_AMD_LSTAR,
204 204 (uint64_t)(uintptr_t)sys_syscall);
205 205 wrmsr(MSR_AMD_CSTAR,
206 206 (uint64_t)(uintptr_t)sys_syscall32);
207 207 }
208 208
209 209 /*
210 210 * This list of flags is masked off the incoming
211 211 * %rfl when we enter the kernel.
212 212 */
213 213 flags = PS_IE | PS_T;
214 214 if (is_x86_feature(x86_featureset, X86FSET_SMAP) == B_TRUE)
215 215 flags |= PS_ACHK;
216 216 wrmsr(MSR_AMD_SFMASK, flags);
217 217 }
218 218
219 219 /*
220 220 * On 64-bit kernels on Nocona machines, the 32-bit syscall
221 221 * variant isn't available to 32-bit applications, but sysenter is.
222 222 */
223 223 if (is_x86_feature(x86_featureset, X86FSET_MSR) &&
224 224 is_x86_feature(x86_featureset, X86FSET_SEP)) {
225 225
226 226 #if !defined(__xpv)
227 227 /*
228 228 * The sysenter instruction imposes a certain ordering on
229 229 * segment selectors, so we double-check that ordering
230 230 * here. See "sysenter" in Intel document 245471-012, "IA-32
231 231 * Intel Architecture Software Developer's Manual Volume 2:
232 232 * Instruction Set Reference"
233 233 */
234 234 CTASSERT(KDS_SEL == KCS_SEL + 8);
235 235
236 236 CTASSERT(U32CS_SEL == ((KCS_SEL + 16) | 3));
237 237 CTASSERT(UDS_SEL == U32CS_SEL + 8);
238 238 #endif
239 239
240 240 cpu_sep_enable();
241 241
242 242 /*
243 243 * resume() sets this value to the base of the threads stack
244 244 * via a context handler.
245 245 */
246 246 wrmsr(MSR_INTC_SEP_ESP, 0);
247 247
248 248 if (kpti_enable == 1) {
249 249 wrmsr(MSR_INTC_SEP_EIP,
250 250 (uint64_t)(uintptr_t)tr_sys_sysenter);
251 251 } else {
252 252 wrmsr(MSR_INTC_SEP_EIP,
253 253 (uint64_t)(uintptr_t)sys_sysenter);
254 254 }
255 255 }
256 256
257 257 kpreempt_enable();
258 258 }
259 259
260 260 #if !defined(__xpv)
261 261 /*
262 262 * Configure per-cpu ID GDT
263 263 */
264 264 static void
265 265 init_cpu_id_gdt(struct cpu *cp)
266 266 {
267 267 /* Write cpu_id into limit field of GDT for usermode retrieval */
268 268 #if defined(__amd64)
269 269 set_usegd(&cp->cpu_gdt[GDT_CPUID], SDP_SHORT, NULL, cp->cpu_id,
270 270 SDT_MEMRODA, SEL_UPL, SDP_BYTES, SDP_OP32);
271 271 #elif defined(__i386)
272 272 set_usegd(&cp->cpu_gdt[GDT_CPUID], NULL, cp->cpu_id, SDT_MEMRODA,
273 273 SEL_UPL, SDP_BYTES, SDP_OP32);
274 274 #endif
275 275 }
276 276 #endif /* !defined(__xpv) */
277 277
278 278 /*
279 279 * Multiprocessor initialization.
280 280 *
281 281 * Allocate and initialize the cpu structure, TRAPTRACE buffer, and the
282 282 * startup and idle threads for the specified CPU.
283 283 * Parameter boot is true for boot time operations and is false for CPU
284 284 * DR operations.
285 285 */
286 286 static struct cpu *
287 287 mp_cpu_configure_common(int cpun, boolean_t boot)
288 288 {
289 289 struct cpu *cp;
290 290 kthread_id_t tp;
291 291 caddr_t sp;
292 292 proc_t *procp;
293 293 #if !defined(__xpv)
294 294 extern int idle_cpu_prefer_mwait;
295 295 extern void cpu_idle_mwait();
296 296 #endif
297 297 extern void idle();
298 298 extern void cpu_idle();
299 299
300 300 #ifdef TRAPTRACE
301 301 trap_trace_ctl_t *ttc = &trap_trace_ctl[cpun];
302 302 #endif
303 303
304 304 ASSERT(MUTEX_HELD(&cpu_lock));
305 305 ASSERT(cpun < NCPU && cpu[cpun] == NULL);
306 306
307 307 if (cpu_free_list == NULL) {
308 308 cp = kmem_zalloc(sizeof (*cp), KM_SLEEP);
309 309 } else {
310 310 cp = cpu_free_list;
311 311 cpu_free_list = cp->cpu_next_free;
312 312 }
313 313
314 314 cp->cpu_m.mcpu_istamp = cpun << 16;
315 315
316 316 /* Create per CPU specific threads in the process p0. */
317 317 procp = &p0;
318 318
319 319 /*
320 320 * Initialize the dispatcher first.
321 321 */
322 322 disp_cpu_init(cp);
323 323
324 324 cpu_vm_data_init(cp);
325 325
326 326 /*
327 327 * Allocate and initialize the startup thread for this CPU.
328 328 * Interrupt and process switch stacks get allocated later
329 329 * when the CPU starts running.
330 330 */
331 331 tp = thread_create(NULL, 0, NULL, NULL, 0, procp,
332 332 TS_STOPPED, maxclsyspri);
333 333
334 334 /*
335 335 * Set state to TS_ONPROC since this thread will start running
336 336 * as soon as the CPU comes online.
337 337 *
338 338 * All the other fields of the thread structure are setup by
339 339 * thread_create().
340 340 */
341 341 THREAD_ONPROC(tp, cp);
342 342 tp->t_preempt = 1;
343 343 tp->t_bound_cpu = cp;
344 344 tp->t_affinitycnt = 1;
345 345 tp->t_cpu = cp;
346 346 tp->t_disp_queue = cp->cpu_disp;
347 347
348 348 /*
349 349 * Setup thread to start in mp_startup_common.
350 350 */
351 351 sp = tp->t_stk;
352 352 tp->t_sp = (uintptr_t)(sp - MINFRAME);
353 353 #if defined(__amd64)
354 354 tp->t_sp -= STACK_ENTRY_ALIGN; /* fake a call */
355 355 #endif
356 356 /*
357 357 * Setup thread start entry point for boot or hotplug.
358 358 */
359 359 if (boot) {
360 360 tp->t_pc = (uintptr_t)mp_startup_boot;
361 361 } else {
362 362 tp->t_pc = (uintptr_t)mp_startup_hotplug;
363 363 }
364 364
365 365 cp->cpu_id = cpun;
366 366 cp->cpu_self = cp;
367 367 cp->cpu_thread = tp;
368 368 cp->cpu_lwp = NULL;
369 369 cp->cpu_dispthread = tp;
370 370 cp->cpu_dispatch_pri = DISP_PRIO(tp);
371 371
372 372 /*
373 373 * cpu_base_spl must be set explicitly here to prevent any blocking
374 374 * operations in mp_startup_common from causing the spl of the cpu
375 375 * to drop to 0 (allowing device interrupts before we're ready) in
376 376 * resume().
377 377 * cpu_base_spl MUST remain at LOCK_LEVEL until the cpu is CPU_READY.
378 378 * As an extra bit of security on DEBUG kernels, this is enforced with
379 379 * an assertion in mp_startup_common() -- before cpu_base_spl is set
380 380 * to its proper value.
381 381 */
382 382 cp->cpu_base_spl = ipltospl(LOCK_LEVEL);
383 383
384 384 /*
385 385 * Now, initialize per-CPU idle thread for this CPU.
386 386 */
387 387 tp = thread_create(NULL, PAGESIZE, idle, NULL, 0, procp, TS_ONPROC, -1);
388 388
389 389 cp->cpu_idle_thread = tp;
390 390
391 391 tp->t_preempt = 1;
392 392 tp->t_bound_cpu = cp;
393 393 tp->t_affinitycnt = 1;
394 394 tp->t_cpu = cp;
395 395 tp->t_disp_queue = cp->cpu_disp;
396 396
397 397 /*
398 398 * Bootstrap the CPU's PG data
399 399 */
400 400 pg_cpu_bootstrap(cp);
401 401
402 402 /*
403 403 * Perform CPC initialization on the new CPU.
404 404 */
405 405 kcpc_hw_init(cp);
406 406
407 407 /*
408 408 * Allocate virtual addresses for cpu_caddr1 and cpu_caddr2
409 409 * for each CPU.
410 410 */
411 411 setup_vaddr_for_ppcopy(cp);
412 412
413 413 /*
414 414 * Allocate page for new GDT and initialize from current GDT.
415 415 */
416 416 #if !defined(__lint)
417 417 ASSERT((sizeof (*cp->cpu_gdt) * NGDT) <= PAGESIZE);
418 418 #endif
419 419 cp->cpu_gdt = kmem_zalloc(PAGESIZE, KM_SLEEP);
420 420 bcopy(CPU->cpu_gdt, cp->cpu_gdt, (sizeof (*cp->cpu_gdt) * NGDT));
421 421
422 422 #if defined(__i386)
423 423 /*
424 424 * setup kernel %gs.
425 425 */
426 426 set_usegd(&cp->cpu_gdt[GDT_GS], cp, sizeof (struct cpu) -1, SDT_MEMRWA,
427 427 SEL_KPL, 0, 1);
428 428 #endif
429 429
430 430 /*
431 431 * Allocate pages for the CPU LDT.
432 432 */
433 433 cp->cpu_m.mcpu_ldt = kmem_zalloc(LDT_CPU_SIZE, KM_SLEEP);
434 434 cp->cpu_m.mcpu_ldt_len = 0;
435 435
436 436 /*
437 437 * Allocate a per-CPU IDT and initialize the new IDT to the currently
438 438 * runing CPU.
439 439 */
440 440 #if !defined(__lint)
441 441 ASSERT((sizeof (*CPU->cpu_idt) * NIDT) <= PAGESIZE);
442 442 #endif
443 443 cp->cpu_idt = kmem_alloc(PAGESIZE, KM_SLEEP);
444 444 bcopy(CPU->cpu_idt, cp->cpu_idt, PAGESIZE);
445 445
446 446 /*
447 447 * alloc space for cpuid info
448 448 */
449 449 cpuid_alloc_space(cp);
450 450 #if !defined(__xpv)
451 451 if (is_x86_feature(x86_featureset, X86FSET_MWAIT) &&
452 452 idle_cpu_prefer_mwait) {
453 453 cp->cpu_m.mcpu_mwait = cpuid_mwait_alloc(cp);
454 454 cp->cpu_m.mcpu_idle_cpu = cpu_idle_mwait;
455 455 } else
456 456 #endif
457 457 cp->cpu_m.mcpu_idle_cpu = cpu_idle;
458 458
459 459 init_cpu_info(cp);
460 460
461 461 #if !defined(__xpv)
462 462 init_cpu_id_gdt(cp);
463 463 #endif
464 464
465 465 /*
466 466 * alloc space for ucode_info
467 467 */
468 468 ucode_alloc_space(cp);
469 469 xc_init_cpu(cp);
470 470 hat_cpu_online(cp);
471 471
472 472 #ifdef TRAPTRACE
473 473 /*
474 474 * If this is a TRAPTRACE kernel, allocate TRAPTRACE buffers
475 475 */
476 476 ttc->ttc_first = (uintptr_t)kmem_zalloc(trap_trace_bufsize, KM_SLEEP);
477 477 ttc->ttc_next = ttc->ttc_first;
478 478 ttc->ttc_limit = ttc->ttc_first + trap_trace_bufsize;
479 479 #endif
480 480
481 481 /*
482 482 * Record that we have another CPU.
483 483 */
484 484 /*
485 485 * Initialize the interrupt threads for this CPU
486 486 */
487 487 cpu_intr_alloc(cp, NINTR_THREADS);
488 488
489 489 cp->cpu_flags = CPU_OFFLINE | CPU_QUIESCED | CPU_POWEROFF;
490 490 cpu_set_state(cp);
491 491
492 492 /*
493 493 * Add CPU to list of available CPUs. It'll be on the active list
494 494 * after mp_startup_common().
495 495 */
496 496 cpu_add_unit(cp);
497 497
498 498 return (cp);
499 499 }
500 500
501 501 /*
502 502 * Undo what was done in mp_cpu_configure_common
503 503 */
504 504 static void
505 505 mp_cpu_unconfigure_common(struct cpu *cp, int error)
506 506 {
507 507 ASSERT(MUTEX_HELD(&cpu_lock));
508 508
509 509 /*
510 510 * Remove the CPU from the list of available CPUs.
511 511 */
512 512 cpu_del_unit(cp->cpu_id);
513 513
514 514 if (error == ETIMEDOUT) {
515 515 /*
516 516 * The cpu was started, but never *seemed* to run any
517 517 * code in the kernel; it's probably off spinning in its
518 518 * own private world, though with potential references to
519 519 * our kmem-allocated IDTs and GDTs (for example).
520 520 *
521 521 * Worse still, it may actually wake up some time later,
522 522 * so rather than guess what it might or might not do, we
523 523 * leave the fundamental data structures intact.
524 524 */
525 525 cp->cpu_flags = 0;
526 526 return;
527 527 }
528 528
529 529 /*
530 530 * At this point, the only threads bound to this CPU should
531 531 * special per-cpu threads: it's idle thread, it's pause threads,
532 532 * and it's interrupt threads. Clean these up.
533 533 */
534 534 cpu_destroy_bound_threads(cp);
535 535 cp->cpu_idle_thread = NULL;
536 536
537 537 /*
538 538 * Free the interrupt stack.
539 539 */
540 540 segkp_release(segkp,
541 541 cp->cpu_intr_stack - (INTR_STACK_SIZE - SA(MINFRAME)));
542 542 cp->cpu_intr_stack = NULL;
543 543
544 544 #ifdef TRAPTRACE
545 545 /*
546 546 * Discard the trap trace buffer
547 547 */
548 548 {
549 549 trap_trace_ctl_t *ttc = &trap_trace_ctl[cp->cpu_id];
550 550
551 551 kmem_free((void *)ttc->ttc_first, trap_trace_bufsize);
552 552 ttc->ttc_first = NULL;
553 553 }
554 554 #endif
555 555
556 556 hat_cpu_offline(cp);
557 557
558 558 ucode_free_space(cp);
559 559
560 560 /* Free CPU ID string and brand string. */
561 561 if (cp->cpu_idstr) {
562 562 kmem_free(cp->cpu_idstr, CPU_IDSTRLEN);
563 563 cp->cpu_idstr = NULL;
564 564 }
565 565 if (cp->cpu_brandstr) {
566 566 kmem_free(cp->cpu_brandstr, CPU_IDSTRLEN);
567 567 cp->cpu_brandstr = NULL;
568 568 }
569 569
570 570 #if !defined(__xpv)
571 571 if (cp->cpu_m.mcpu_mwait != NULL) {
572 572 cpuid_mwait_free(cp);
573 573 cp->cpu_m.mcpu_mwait = NULL;
574 574 }
575 575 #endif
576 576 cpuid_free_space(cp);
577 577
578 578 if (cp->cpu_idt != CPU->cpu_idt)
579 579 kmem_free(cp->cpu_idt, PAGESIZE);
580 580 cp->cpu_idt = NULL;
581 581
582 582 kmem_free(cp->cpu_m.mcpu_ldt, LDT_CPU_SIZE);
583 583 cp->cpu_m.mcpu_ldt = NULL;
584 584 cp->cpu_m.mcpu_ldt_len = 0;
585 585
586 586 kmem_free(cp->cpu_gdt, PAGESIZE);
587 587 cp->cpu_gdt = NULL;
588 588
589 589 if (cp->cpu_supp_freqs != NULL) {
590 590 size_t len = strlen(cp->cpu_supp_freqs) + 1;
591 591 kmem_free(cp->cpu_supp_freqs, len);
592 592 cp->cpu_supp_freqs = NULL;
593 593 }
594 594
595 595 teardown_vaddr_for_ppcopy(cp);
596 596
597 597 kcpc_hw_fini(cp);
598 598
599 599 cp->cpu_dispthread = NULL;
600 600 cp->cpu_thread = NULL; /* discarded by cpu_destroy_bound_threads() */
601 601
602 602 cpu_vm_data_destroy(cp);
603 603
604 604 xc_fini_cpu(cp);
605 605 disp_cpu_fini(cp);
606 606
607 607 ASSERT(cp != CPU0);
608 608 bzero(cp, sizeof (*cp));
609 609 cp->cpu_next_free = cpu_free_list;
610 610 cpu_free_list = cp;
611 611 }
612 612
613 613 /*
614 614 * Apply workarounds for known errata, and warn about those that are absent.
615 615 *
616 616 * System vendors occasionally create configurations which contain different
617 617 * revisions of the CPUs that are almost but not exactly the same. At the
618 618 * time of writing, this meant that their clock rates were the same, their
619 619 * feature sets were the same, but the required workaround were -not-
620 620 * necessarily the same. So, this routine is invoked on -every- CPU soon
621 621 * after starting to make sure that the resulting system contains the most
622 622 * pessimal set of workarounds needed to cope with *any* of the CPUs in the
623 623 * system.
624 624 *
625 625 * workaround_errata is invoked early in mlsetup() for CPU 0, and in
626 626 * mp_startup_common() for all slave CPUs. Slaves process workaround_errata
627 627 * prior to acknowledging their readiness to the master, so this routine will
628 628 * never be executed by multiple CPUs in parallel, thus making updates to
629 629 * global data safe.
630 630 *
631 631 * These workarounds are based on Rev 3.57 of the Revision Guide for
632 632 * AMD Athlon(tm) 64 and AMD Opteron(tm) Processors, August 2005.
633 633 */
634 634
635 635 #if defined(OPTERON_ERRATUM_88)
636 636 int opteron_erratum_88; /* if non-zero -> at least one cpu has it */
637 637 #endif
638 638
639 639 #if defined(OPTERON_ERRATUM_91)
640 640 int opteron_erratum_91; /* if non-zero -> at least one cpu has it */
641 641 #endif
642 642
643 643 #if defined(OPTERON_ERRATUM_93)
644 644 int opteron_erratum_93; /* if non-zero -> at least one cpu has it */
645 645 #endif
646 646
647 647 #if defined(OPTERON_ERRATUM_95)
648 648 int opteron_erratum_95; /* if non-zero -> at least one cpu has it */
649 649 #endif
650 650
651 651 #if defined(OPTERON_ERRATUM_100)
652 652 int opteron_erratum_100; /* if non-zero -> at least one cpu has it */
653 653 #endif
654 654
655 655 #if defined(OPTERON_ERRATUM_108)
656 656 int opteron_erratum_108; /* if non-zero -> at least one cpu has it */
657 657 #endif
658 658
659 659 #if defined(OPTERON_ERRATUM_109)
660 660 int opteron_erratum_109; /* if non-zero -> at least one cpu has it */
661 661 #endif
662 662
663 663 #if defined(OPTERON_ERRATUM_121)
664 664 int opteron_erratum_121; /* if non-zero -> at least one cpu has it */
665 665 #endif
666 666
667 667 #if defined(OPTERON_ERRATUM_122)
668 668 int opteron_erratum_122; /* if non-zero -> at least one cpu has it */
669 669 #endif
670 670
671 671 #if defined(OPTERON_ERRATUM_123)
672 672 int opteron_erratum_123; /* if non-zero -> at least one cpu has it */
673 673 #endif
674 674
675 675 #if defined(OPTERON_ERRATUM_131)
676 676 int opteron_erratum_131; /* if non-zero -> at least one cpu has it */
677 677 #endif
678 678
679 679 #if defined(OPTERON_WORKAROUND_6336786)
680 680 int opteron_workaround_6336786; /* non-zero -> WA relevant and applied */
681 681 int opteron_workaround_6336786_UP = 0; /* Not needed for UP */
682 682 #endif
683 683
684 684 #if defined(OPTERON_WORKAROUND_6323525)
685 685 int opteron_workaround_6323525; /* if non-zero -> at least one cpu has it */
686 686 #endif
687 687
688 688 #if defined(OPTERON_ERRATUM_298)
689 689 int opteron_erratum_298;
690 690 #endif
691 691
692 692 #if defined(OPTERON_ERRATUM_721)
693 693 int opteron_erratum_721;
694 694 #endif
695 695
696 696 static void
697 697 workaround_warning(cpu_t *cp, uint_t erratum)
698 698 {
699 699 cmn_err(CE_WARN, "cpu%d: no workaround for erratum %u",
700 700 cp->cpu_id, erratum);
701 701 }
702 702
703 703 static void
704 704 workaround_applied(uint_t erratum)
705 705 {
706 706 if (erratum > 1000000)
707 707 cmn_err(CE_CONT, "?workaround applied for cpu issue #%d\n",
708 708 erratum);
709 709 else
710 710 cmn_err(CE_CONT, "?workaround applied for cpu erratum #%d\n",
711 711 erratum);
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712 712 }
713 713
714 714 static void
715 715 msr_warning(cpu_t *cp, const char *rw, uint_t msr, int error)
716 716 {
717 717 cmn_err(CE_WARN, "cpu%d: couldn't %smsr 0x%x, error %d",
718 718 cp->cpu_id, rw, msr, error);
719 719 }
720 720
721 721 /*
722 - * Determine the number of nodes in a Hammer / Greyhound / Griffin family
723 - * system.
722 + * Determine the number of nodes in a system.
723 + *
724 + * This routine uses a PCI config space based mechanism
725 + * for retrieving the number of nodes in the system.
726 + *
727 + * Current processor families that support this mechanism are
728 + * 0xf, 0x10, 0x11, and 0x15.
724 729 */
725 730 static uint_t
726 731 opteron_get_nnodes(void)
727 732 {
728 733 static uint_t nnodes = 0;
729 734
730 - if (nnodes == 0) {
731 -#ifdef DEBUG
732 - uint_t family;
733 -
734 - /*
735 - * This routine uses a PCI config space based mechanism
736 - * for retrieving the number of nodes in the system.
737 - * Device 24, function 0, offset 0x60 as used here is not
738 - * AMD processor architectural, and may not work on processor
739 - * families other than those listed below.
740 - *
741 - * Callers of this routine must ensure that we're running on
742 - * a processor which supports this mechanism.
743 - * The assertion below is meant to catch calls on unsupported
744 - * processors.
745 - */
746 - family = cpuid_getfamily(CPU);
747 - ASSERT(family == 0xf || family == 0x10 || family == 0x11);
748 -#endif /* DEBUG */
749 -
750 - /*
751 - * Obtain the number of nodes in the system from
752 - * bits [6:4] of the Node ID register on node 0.
753 - *
754 - * The actual node count is NodeID[6:4] + 1
755 - *
756 - * The Node ID register is accessed via function 0,
757 - * offset 0x60. Node 0 is device 24.
758 - */
735 + /*
736 + * Obtain the number of nodes in the system from
737 + * bits [6:4] of the Node ID register on node 0.
738 + *
739 + * The actual node count is NodeID[6:4] + 1
740 + *
741 + * The Node ID register is accessed via function 0,
742 + * offset 0x60. Node 0 is device 24.
743 + */
744 + if (nnodes == 0)
759 745 nnodes = ((pci_getl_func(0, 24, 0, 0x60) & 0x70) >> 4) + 1;
760 - }
746 +
761 747 return (nnodes);
762 748 }
763 749
764 750 uint_t
765 751 do_erratum_298(struct cpu *cpu)
766 752 {
767 753 static int osvwrc = -3;
768 754 extern int osvw_opteron_erratum(cpu_t *, uint_t);
769 755
770 756 /*
771 757 * L2 Eviction May Occur During Processor Operation To Set
772 758 * Accessed or Dirty Bit.
773 759 */
774 760 if (osvwrc == -3) {
775 761 osvwrc = osvw_opteron_erratum(cpu, 298);
776 762 } else {
777 763 /* osvw return codes should be consistent for all cpus */
778 764 ASSERT(osvwrc == osvw_opteron_erratum(cpu, 298));
779 765 }
780 766
781 767 switch (osvwrc) {
782 768 case 0: /* erratum is not present: do nothing */
783 769 break;
784 770 case 1: /* erratum is present: BIOS workaround applied */
785 771 /*
786 772 * check if workaround is actually in place and issue warning
787 773 * if not.
788 774 */
789 775 if (((rdmsr(MSR_AMD_HWCR) & AMD_HWCR_TLBCACHEDIS) == 0) ||
790 776 ((rdmsr(MSR_AMD_BU_CFG) & AMD_BU_CFG_E298) == 0)) {
791 777 #if defined(OPTERON_ERRATUM_298)
792 778 opteron_erratum_298++;
793 779 #else
794 780 workaround_warning(cpu, 298);
795 781 return (1);
796 782 #endif
797 783 }
798 784 break;
799 785 case -1: /* cannot determine via osvw: check cpuid */
800 786 if ((cpuid_opteron_erratum(cpu, 298) > 0) &&
801 787 (((rdmsr(MSR_AMD_HWCR) & AMD_HWCR_TLBCACHEDIS) == 0) ||
802 788 ((rdmsr(MSR_AMD_BU_CFG) & AMD_BU_CFG_E298) == 0))) {
803 789 #if defined(OPTERON_ERRATUM_298)
804 790 opteron_erratum_298++;
805 791 #else
806 792 workaround_warning(cpu, 298);
807 793 return (1);
808 794 #endif
809 795 }
810 796 break;
811 797 }
812 798 return (0);
813 799 }
814 800
815 801 uint_t
816 802 workaround_errata(struct cpu *cpu)
817 803 {
818 804 uint_t missing = 0;
819 805
820 806 ASSERT(cpu == CPU);
821 807
822 808 /*LINTED*/
823 809 if (cpuid_opteron_erratum(cpu, 88) > 0) {
824 810 /*
825 811 * SWAPGS May Fail To Read Correct GS Base
826 812 */
827 813 #if defined(OPTERON_ERRATUM_88)
828 814 /*
829 815 * The workaround is an mfence in the relevant assembler code
830 816 */
831 817 opteron_erratum_88++;
832 818 #else
833 819 workaround_warning(cpu, 88);
834 820 missing++;
835 821 #endif
836 822 }
837 823
838 824 if (cpuid_opteron_erratum(cpu, 91) > 0) {
839 825 /*
840 826 * Software Prefetches May Report A Page Fault
841 827 */
842 828 #if defined(OPTERON_ERRATUM_91)
843 829 /*
844 830 * fix is in trap.c
845 831 */
846 832 opteron_erratum_91++;
847 833 #else
848 834 workaround_warning(cpu, 91);
849 835 missing++;
850 836 #endif
851 837 }
852 838
853 839 if (cpuid_opteron_erratum(cpu, 93) > 0) {
854 840 /*
855 841 * RSM Auto-Halt Restart Returns to Incorrect RIP
856 842 */
857 843 #if defined(OPTERON_ERRATUM_93)
858 844 /*
859 845 * fix is in trap.c
860 846 */
861 847 opteron_erratum_93++;
862 848 #else
863 849 workaround_warning(cpu, 93);
864 850 missing++;
865 851 #endif
866 852 }
867 853
868 854 /*LINTED*/
869 855 if (cpuid_opteron_erratum(cpu, 95) > 0) {
870 856 /*
871 857 * RET Instruction May Return to Incorrect EIP
872 858 */
873 859 #if defined(OPTERON_ERRATUM_95)
874 860 #if defined(_LP64)
875 861 /*
876 862 * Workaround this by ensuring that 32-bit user code and
877 863 * 64-bit kernel code never occupy the same address
878 864 * range mod 4G.
879 865 */
880 866 if (_userlimit32 > 0xc0000000ul)
881 867 *(uintptr_t *)&_userlimit32 = 0xc0000000ul;
882 868
883 869 /*LINTED*/
884 870 ASSERT((uint32_t)COREHEAP_BASE == 0xc0000000u);
885 871 opteron_erratum_95++;
886 872 #endif /* _LP64 */
887 873 #else
888 874 workaround_warning(cpu, 95);
889 875 missing++;
890 876 #endif
891 877 }
892 878
893 879 if (cpuid_opteron_erratum(cpu, 100) > 0) {
894 880 /*
895 881 * Compatibility Mode Branches Transfer to Illegal Address
896 882 */
897 883 #if defined(OPTERON_ERRATUM_100)
898 884 /*
899 885 * fix is in trap.c
900 886 */
901 887 opteron_erratum_100++;
902 888 #else
903 889 workaround_warning(cpu, 100);
904 890 missing++;
905 891 #endif
906 892 }
907 893
908 894 /*LINTED*/
909 895 if (cpuid_opteron_erratum(cpu, 108) > 0) {
910 896 /*
911 897 * CPUID Instruction May Return Incorrect Model Number In
912 898 * Some Processors
913 899 */
914 900 #if defined(OPTERON_ERRATUM_108)
915 901 /*
916 902 * (Our cpuid-handling code corrects the model number on
917 903 * those processors)
918 904 */
919 905 #else
920 906 workaround_warning(cpu, 108);
921 907 missing++;
922 908 #endif
923 909 }
924 910
925 911 /*LINTED*/
926 912 if (cpuid_opteron_erratum(cpu, 109) > 0) do {
927 913 /*
928 914 * Certain Reverse REP MOVS May Produce Unpredictable Behavior
929 915 */
930 916 #if defined(OPTERON_ERRATUM_109)
931 917 /*
932 918 * The "workaround" is to print a warning to upgrade the BIOS
933 919 */
934 920 uint64_t value;
935 921 const uint_t msr = MSR_AMD_PATCHLEVEL;
936 922 int err;
937 923
938 924 if ((err = checked_rdmsr(msr, &value)) != 0) {
939 925 msr_warning(cpu, "rd", msr, err);
940 926 workaround_warning(cpu, 109);
941 927 missing++;
942 928 }
943 929 if (value == 0)
944 930 opteron_erratum_109++;
945 931 #else
946 932 workaround_warning(cpu, 109);
947 933 missing++;
948 934 #endif
949 935 /*CONSTANTCONDITION*/
950 936 } while (0);
951 937
952 938 /*LINTED*/
953 939 if (cpuid_opteron_erratum(cpu, 121) > 0) {
954 940 /*
955 941 * Sequential Execution Across Non_Canonical Boundary Caused
956 942 * Processor Hang
957 943 */
958 944 #if defined(OPTERON_ERRATUM_121)
959 945 #if defined(_LP64)
960 946 /*
961 947 * Erratum 121 is only present in long (64 bit) mode.
962 948 * Workaround is to include the page immediately before the
963 949 * va hole to eliminate the possibility of system hangs due to
964 950 * sequential execution across the va hole boundary.
965 951 */
966 952 if (opteron_erratum_121)
967 953 opteron_erratum_121++;
968 954 else {
969 955 if (hole_start) {
970 956 hole_start -= PAGESIZE;
971 957 } else {
972 958 /*
973 959 * hole_start not yet initialized by
974 960 * mmu_init. Initialize hole_start
975 961 * with value to be subtracted.
976 962 */
977 963 hole_start = PAGESIZE;
978 964 }
979 965 opteron_erratum_121++;
980 966 }
981 967 #endif /* _LP64 */
982 968 #else
983 969 workaround_warning(cpu, 121);
984 970 missing++;
985 971 #endif
986 972 }
987 973
988 974 /*LINTED*/
989 975 if (cpuid_opteron_erratum(cpu, 122) > 0) do {
990 976 /*
991 977 * TLB Flush Filter May Cause Coherency Problem in
992 978 * Multiprocessor Systems
993 979 */
994 980 #if defined(OPTERON_ERRATUM_122)
995 981 uint64_t value;
996 982 const uint_t msr = MSR_AMD_HWCR;
997 983 int error;
998 984
999 985 /*
1000 986 * Erratum 122 is only present in MP configurations (multi-core
1001 987 * or multi-processor).
1002 988 */
1003 989 #if defined(__xpv)
1004 990 if (!DOMAIN_IS_INITDOMAIN(xen_info))
1005 991 break;
1006 992 if (!opteron_erratum_122 && xpv_nr_phys_cpus() == 1)
1007 993 break;
1008 994 #else
1009 995 if (!opteron_erratum_122 && opteron_get_nnodes() == 1 &&
1010 996 cpuid_get_ncpu_per_chip(cpu) == 1)
1011 997 break;
1012 998 #endif
1013 999 /* disable TLB Flush Filter */
1014 1000
1015 1001 if ((error = checked_rdmsr(msr, &value)) != 0) {
1016 1002 msr_warning(cpu, "rd", msr, error);
1017 1003 workaround_warning(cpu, 122);
1018 1004 missing++;
1019 1005 } else {
1020 1006 value |= (uint64_t)AMD_HWCR_FFDIS;
1021 1007 if ((error = checked_wrmsr(msr, value)) != 0) {
1022 1008 msr_warning(cpu, "wr", msr, error);
1023 1009 workaround_warning(cpu, 122);
1024 1010 missing++;
1025 1011 }
1026 1012 }
1027 1013 opteron_erratum_122++;
1028 1014 #else
1029 1015 workaround_warning(cpu, 122);
1030 1016 missing++;
1031 1017 #endif
1032 1018 /*CONSTANTCONDITION*/
1033 1019 } while (0);
1034 1020
1035 1021 /*LINTED*/
1036 1022 if (cpuid_opteron_erratum(cpu, 123) > 0) do {
1037 1023 /*
1038 1024 * Bypassed Reads May Cause Data Corruption of System Hang in
1039 1025 * Dual Core Processors
1040 1026 */
1041 1027 #if defined(OPTERON_ERRATUM_123)
1042 1028 uint64_t value;
1043 1029 const uint_t msr = MSR_AMD_PATCHLEVEL;
1044 1030 int err;
1045 1031
1046 1032 /*
1047 1033 * Erratum 123 applies only to multi-core cpus.
1048 1034 */
1049 1035 if (cpuid_get_ncpu_per_chip(cpu) < 2)
1050 1036 break;
1051 1037 #if defined(__xpv)
1052 1038 if (!DOMAIN_IS_INITDOMAIN(xen_info))
1053 1039 break;
1054 1040 #endif
1055 1041 /*
1056 1042 * The "workaround" is to print a warning to upgrade the BIOS
1057 1043 */
1058 1044 if ((err = checked_rdmsr(msr, &value)) != 0) {
1059 1045 msr_warning(cpu, "rd", msr, err);
1060 1046 workaround_warning(cpu, 123);
1061 1047 missing++;
1062 1048 }
1063 1049 if (value == 0)
1064 1050 opteron_erratum_123++;
1065 1051 #else
1066 1052 workaround_warning(cpu, 123);
1067 1053 missing++;
1068 1054
1069 1055 #endif
1070 1056 /*CONSTANTCONDITION*/
1071 1057 } while (0);
1072 1058
1073 1059 /*LINTED*/
1074 1060 if (cpuid_opteron_erratum(cpu, 131) > 0) do {
1075 1061 /*
1076 1062 * Multiprocessor Systems with Four or More Cores May Deadlock
1077 1063 * Waiting for a Probe Response
1078 1064 */
1079 1065 #if defined(OPTERON_ERRATUM_131)
1080 1066 uint64_t nbcfg;
1081 1067 const uint_t msr = MSR_AMD_NB_CFG;
1082 1068 const uint64_t wabits =
1083 1069 AMD_NB_CFG_SRQ_HEARTBEAT | AMD_NB_CFG_SRQ_SPR;
1084 1070 int error;
1085 1071
1086 1072 /*
1087 1073 * Erratum 131 applies to any system with four or more cores.
1088 1074 */
1089 1075 if (opteron_erratum_131)
1090 1076 break;
1091 1077 #if defined(__xpv)
1092 1078 if (!DOMAIN_IS_INITDOMAIN(xen_info))
1093 1079 break;
1094 1080 if (xpv_nr_phys_cpus() < 4)
1095 1081 break;
1096 1082 #else
1097 1083 if (opteron_get_nnodes() * cpuid_get_ncpu_per_chip(cpu) < 4)
1098 1084 break;
1099 1085 #endif
1100 1086 /*
1101 1087 * Print a warning if neither of the workarounds for
1102 1088 * erratum 131 is present.
1103 1089 */
1104 1090 if ((error = checked_rdmsr(msr, &nbcfg)) != 0) {
1105 1091 msr_warning(cpu, "rd", msr, error);
1106 1092 workaround_warning(cpu, 131);
1107 1093 missing++;
1108 1094 } else if ((nbcfg & wabits) == 0) {
1109 1095 opteron_erratum_131++;
1110 1096 } else {
1111 1097 /* cannot have both workarounds set */
1112 1098 ASSERT((nbcfg & wabits) != wabits);
1113 1099 }
1114 1100 #else
1115 1101 workaround_warning(cpu, 131);
1116 1102 missing++;
1117 1103 #endif
1118 1104 /*CONSTANTCONDITION*/
1119 1105 } while (0);
1120 1106
1121 1107 /*
1122 1108 * This isn't really an erratum, but for convenience the
1123 1109 * detection/workaround code lives here and in cpuid_opteron_erratum.
1124 1110 */
1125 1111 if (cpuid_opteron_erratum(cpu, 6336786) > 0) {
1126 1112 #if defined(OPTERON_WORKAROUND_6336786)
1127 1113 /*
1128 1114 * Disable C1-Clock ramping on multi-core/multi-processor
1129 1115 * K8 platforms to guard against TSC drift.
1130 1116 */
1131 1117 if (opteron_workaround_6336786) {
1132 1118 opteron_workaround_6336786++;
1133 1119 #if defined(__xpv)
1134 1120 } else if ((DOMAIN_IS_INITDOMAIN(xen_info) &&
1135 1121 xpv_nr_phys_cpus() > 1) ||
1136 1122 opteron_workaround_6336786_UP) {
1137 1123 /*
1138 1124 * XXPV Hmm. We can't walk the Northbridges on
1139 1125 * the hypervisor; so just complain and drive
1140 1126 * on. This probably needs to be fixed in
1141 1127 * the hypervisor itself.
1142 1128 */
1143 1129 opteron_workaround_6336786++;
1144 1130 workaround_warning(cpu, 6336786);
1145 1131 #else /* __xpv */
1146 1132 } else if ((opteron_get_nnodes() *
1147 1133 cpuid_get_ncpu_per_chip(cpu) > 1) ||
1148 1134 opteron_workaround_6336786_UP) {
1149 1135
1150 1136 uint_t node, nnodes;
1151 1137 uint8_t data;
1152 1138
1153 1139 nnodes = opteron_get_nnodes();
1154 1140 for (node = 0; node < nnodes; node++) {
1155 1141 /*
1156 1142 * Clear PMM7[1:0] (function 3, offset 0x87)
1157 1143 * Northbridge device is the node id + 24.
1158 1144 */
1159 1145 data = pci_getb_func(0, node + 24, 3, 0x87);
1160 1146 data &= 0xFC;
1161 1147 pci_putb_func(0, node + 24, 3, 0x87, data);
1162 1148 }
1163 1149 opteron_workaround_6336786++;
1164 1150 #endif /* __xpv */
1165 1151 }
1166 1152 #else
1167 1153 workaround_warning(cpu, 6336786);
1168 1154 missing++;
1169 1155 #endif
1170 1156 }
1171 1157
1172 1158 /*LINTED*/
1173 1159 /*
1174 1160 * Mutex primitives don't work as expected.
1175 1161 */
1176 1162 if (cpuid_opteron_erratum(cpu, 6323525) > 0) {
1177 1163 #if defined(OPTERON_WORKAROUND_6323525)
1178 1164 /*
1179 1165 * This problem only occurs with 2 or more cores. If bit in
1180 1166 * MSR_AMD_BU_CFG set, then not applicable. The workaround
1181 1167 * is to patch the semaphone routines with the lfence
1182 1168 * instruction to provide necessary load memory barrier with
1183 1169 * possible subsequent read-modify-write ops.
1184 1170 *
1185 1171 * It is too early in boot to call the patch routine so
1186 1172 * set erratum variable to be done in startup_end().
1187 1173 */
1188 1174 if (opteron_workaround_6323525) {
1189 1175 opteron_workaround_6323525++;
1190 1176 #if defined(__xpv)
1191 1177 } else if (is_x86_feature(x86_featureset, X86FSET_SSE2)) {
1192 1178 if (DOMAIN_IS_INITDOMAIN(xen_info)) {
1193 1179 /*
1194 1180 * XXPV Use dom0_msr here when extended
1195 1181 * operations are supported?
1196 1182 */
1197 1183 if (xpv_nr_phys_cpus() > 1)
1198 1184 opteron_workaround_6323525++;
1199 1185 } else {
1200 1186 /*
1201 1187 * We have no way to tell how many physical
1202 1188 * cpus there are, or even if this processor
1203 1189 * has the problem, so enable the workaround
1204 1190 * unconditionally (at some performance cost).
1205 1191 */
1206 1192 opteron_workaround_6323525++;
1207 1193 }
1208 1194 #else /* __xpv */
1209 1195 } else if (is_x86_feature(x86_featureset, X86FSET_SSE2) &&
1210 1196 ((opteron_get_nnodes() *
1211 1197 cpuid_get_ncpu_per_chip(cpu)) > 1)) {
1212 1198 if ((xrdmsr(MSR_AMD_BU_CFG) & (UINT64_C(1) << 33)) == 0)
1213 1199 opteron_workaround_6323525++;
1214 1200 #endif /* __xpv */
1215 1201 }
1216 1202 #else
1217 1203 workaround_warning(cpu, 6323525);
1218 1204 missing++;
1219 1205 #endif
1220 1206 }
1221 1207
1222 1208 missing += do_erratum_298(cpu);
1223 1209
1224 1210 if (cpuid_opteron_erratum(cpu, 721) > 0) {
1225 1211 #if defined(OPTERON_ERRATUM_721)
1226 1212 on_trap_data_t otd;
1227 1213
1228 1214 if (!on_trap(&otd, OT_DATA_ACCESS))
1229 1215 wrmsr(MSR_AMD_DE_CFG,
1230 1216 rdmsr(MSR_AMD_DE_CFG) | AMD_DE_CFG_E721);
1231 1217 no_trap();
1232 1218
1233 1219 opteron_erratum_721++;
1234 1220 #else
1235 1221 workaround_warning(cpu, 721);
1236 1222 missing++;
1237 1223 #endif
1238 1224 }
1239 1225
1240 1226 #ifdef __xpv
1241 1227 return (0);
1242 1228 #else
1243 1229 return (missing);
1244 1230 #endif
1245 1231 }
1246 1232
1247 1233 void
1248 1234 workaround_errata_end()
1249 1235 {
1250 1236 #if defined(OPTERON_ERRATUM_88)
1251 1237 if (opteron_erratum_88)
1252 1238 workaround_applied(88);
1253 1239 #endif
1254 1240 #if defined(OPTERON_ERRATUM_91)
1255 1241 if (opteron_erratum_91)
1256 1242 workaround_applied(91);
1257 1243 #endif
1258 1244 #if defined(OPTERON_ERRATUM_93)
1259 1245 if (opteron_erratum_93)
1260 1246 workaround_applied(93);
1261 1247 #endif
1262 1248 #if defined(OPTERON_ERRATUM_95)
1263 1249 if (opteron_erratum_95)
1264 1250 workaround_applied(95);
1265 1251 #endif
1266 1252 #if defined(OPTERON_ERRATUM_100)
1267 1253 if (opteron_erratum_100)
1268 1254 workaround_applied(100);
1269 1255 #endif
1270 1256 #if defined(OPTERON_ERRATUM_108)
1271 1257 if (opteron_erratum_108)
1272 1258 workaround_applied(108);
1273 1259 #endif
1274 1260 #if defined(OPTERON_ERRATUM_109)
1275 1261 if (opteron_erratum_109) {
1276 1262 cmn_err(CE_WARN,
1277 1263 "BIOS microcode patch for AMD Athlon(tm) 64/Opteron(tm)"
1278 1264 " processor\nerratum 109 was not detected; updating your"
1279 1265 " system's BIOS to a version\ncontaining this"
1280 1266 " microcode patch is HIGHLY recommended or erroneous"
1281 1267 " system\noperation may occur.\n");
1282 1268 }
1283 1269 #endif
1284 1270 #if defined(OPTERON_ERRATUM_121)
1285 1271 if (opteron_erratum_121)
1286 1272 workaround_applied(121);
1287 1273 #endif
1288 1274 #if defined(OPTERON_ERRATUM_122)
1289 1275 if (opteron_erratum_122)
1290 1276 workaround_applied(122);
1291 1277 #endif
1292 1278 #if defined(OPTERON_ERRATUM_123)
1293 1279 if (opteron_erratum_123) {
1294 1280 cmn_err(CE_WARN,
1295 1281 "BIOS microcode patch for AMD Athlon(tm) 64/Opteron(tm)"
1296 1282 " processor\nerratum 123 was not detected; updating your"
1297 1283 " system's BIOS to a version\ncontaining this"
1298 1284 " microcode patch is HIGHLY recommended or erroneous"
1299 1285 " system\noperation may occur.\n");
1300 1286 }
1301 1287 #endif
1302 1288 #if defined(OPTERON_ERRATUM_131)
1303 1289 if (opteron_erratum_131) {
1304 1290 cmn_err(CE_WARN,
1305 1291 "BIOS microcode patch for AMD Athlon(tm) 64/Opteron(tm)"
1306 1292 " processor\nerratum 131 was not detected; updating your"
1307 1293 " system's BIOS to a version\ncontaining this"
1308 1294 " microcode patch is HIGHLY recommended or erroneous"
1309 1295 " system\noperation may occur.\n");
1310 1296 }
1311 1297 #endif
1312 1298 #if defined(OPTERON_WORKAROUND_6336786)
1313 1299 if (opteron_workaround_6336786)
1314 1300 workaround_applied(6336786);
1315 1301 #endif
1316 1302 #if defined(OPTERON_WORKAROUND_6323525)
1317 1303 if (opteron_workaround_6323525)
1318 1304 workaround_applied(6323525);
1319 1305 #endif
1320 1306 #if defined(OPTERON_ERRATUM_298)
1321 1307 if (opteron_erratum_298) {
1322 1308 cmn_err(CE_WARN,
1323 1309 "BIOS microcode patch for AMD 64/Opteron(tm)"
1324 1310 " processor\nerratum 298 was not detected; updating your"
1325 1311 " system's BIOS to a version\ncontaining this"
1326 1312 " microcode patch is HIGHLY recommended or erroneous"
1327 1313 " system\noperation may occur.\n");
1328 1314 }
1329 1315 #endif
1330 1316 #if defined(OPTERON_ERRATUM_721)
1331 1317 if (opteron_erratum_721)
1332 1318 workaround_applied(721);
1333 1319 #endif
1334 1320 }
1335 1321
1336 1322 /*
1337 1323 * The procset_slave and procset_master are used to synchronize
1338 1324 * between the control CPU and the target CPU when starting CPUs.
1339 1325 */
1340 1326 static cpuset_t procset_slave, procset_master;
1341 1327
1342 1328 static void
1343 1329 mp_startup_wait(cpuset_t *sp, processorid_t cpuid)
1344 1330 {
1345 1331 cpuset_t tempset;
1346 1332
1347 1333 for (tempset = *sp; !CPU_IN_SET(tempset, cpuid);
1348 1334 tempset = *(volatile cpuset_t *)sp) {
1349 1335 SMT_PAUSE();
1350 1336 }
1351 1337 CPUSET_ATOMIC_DEL(*(cpuset_t *)sp, cpuid);
1352 1338 }
1353 1339
1354 1340 static void
1355 1341 mp_startup_signal(cpuset_t *sp, processorid_t cpuid)
1356 1342 {
1357 1343 cpuset_t tempset;
1358 1344
1359 1345 CPUSET_ATOMIC_ADD(*(cpuset_t *)sp, cpuid);
1360 1346 for (tempset = *sp; CPU_IN_SET(tempset, cpuid);
1361 1347 tempset = *(volatile cpuset_t *)sp) {
1362 1348 SMT_PAUSE();
1363 1349 }
1364 1350 }
1365 1351
1366 1352 int
1367 1353 mp_start_cpu_common(cpu_t *cp, boolean_t boot)
1368 1354 {
1369 1355 _NOTE(ARGUNUSED(boot));
1370 1356
1371 1357 void *ctx;
1372 1358 int delays;
1373 1359 int error = 0;
1374 1360 cpuset_t tempset;
1375 1361 processorid_t cpuid;
1376 1362 #ifndef __xpv
1377 1363 extern void cpupm_init(cpu_t *);
1378 1364 #endif
1379 1365
1380 1366 ASSERT(cp != NULL);
1381 1367 cpuid = cp->cpu_id;
1382 1368 ctx = mach_cpucontext_alloc(cp);
1383 1369 if (ctx == NULL) {
1384 1370 cmn_err(CE_WARN,
1385 1371 "cpu%d: failed to allocate context", cp->cpu_id);
1386 1372 return (EAGAIN);
1387 1373 }
1388 1374 error = mach_cpu_start(cp, ctx);
1389 1375 if (error != 0) {
1390 1376 cmn_err(CE_WARN,
1391 1377 "cpu%d: failed to start, error %d", cp->cpu_id, error);
1392 1378 mach_cpucontext_free(cp, ctx, error);
1393 1379 return (error);
1394 1380 }
1395 1381
1396 1382 for (delays = 0, tempset = procset_slave; !CPU_IN_SET(tempset, cpuid);
1397 1383 delays++) {
1398 1384 if (delays == 500) {
1399 1385 /*
1400 1386 * After five seconds, things are probably looking
1401 1387 * a bit bleak - explain the hang.
1402 1388 */
1403 1389 cmn_err(CE_NOTE, "cpu%d: started, "
1404 1390 "but not running in the kernel yet", cpuid);
1405 1391 } else if (delays > 2000) {
1406 1392 /*
1407 1393 * We waited at least 20 seconds, bail ..
1408 1394 */
1409 1395 error = ETIMEDOUT;
1410 1396 cmn_err(CE_WARN, "cpu%d: timed out", cpuid);
1411 1397 mach_cpucontext_free(cp, ctx, error);
1412 1398 return (error);
1413 1399 }
1414 1400
1415 1401 /*
1416 1402 * wait at least 10ms, then check again..
1417 1403 */
1418 1404 delay(USEC_TO_TICK_ROUNDUP(10000));
1419 1405 tempset = *((volatile cpuset_t *)&procset_slave);
1420 1406 }
1421 1407 CPUSET_ATOMIC_DEL(procset_slave, cpuid);
1422 1408
1423 1409 mach_cpucontext_free(cp, ctx, 0);
1424 1410
1425 1411 #ifndef __xpv
1426 1412 if (tsc_gethrtime_enable)
1427 1413 tsc_sync_master(cpuid);
1428 1414 #endif
1429 1415
1430 1416 if (dtrace_cpu_init != NULL) {
1431 1417 (*dtrace_cpu_init)(cpuid);
1432 1418 }
1433 1419
1434 1420 /*
1435 1421 * During CPU DR operations, the cpu_lock is held by current
1436 1422 * (the control) thread. We can't release the cpu_lock here
1437 1423 * because that will break the CPU DR logic.
1438 1424 * On the other hand, CPUPM and processor group initialization
1439 1425 * routines need to access the cpu_lock. So we invoke those
1440 1426 * routines here on behalf of mp_startup_common().
1441 1427 *
1442 1428 * CPUPM and processor group initialization routines depend
1443 1429 * on the cpuid probing results. Wait for mp_startup_common()
1444 1430 * to signal that cpuid probing is done.
1445 1431 */
1446 1432 mp_startup_wait(&procset_slave, cpuid);
1447 1433 #ifndef __xpv
1448 1434 cpupm_init(cp);
1449 1435 #endif
1450 1436 (void) pg_cpu_init(cp, B_FALSE);
1451 1437 cpu_set_state(cp);
1452 1438 mp_startup_signal(&procset_master, cpuid);
1453 1439
1454 1440 return (0);
1455 1441 }
1456 1442
1457 1443 /*
1458 1444 * Start a single cpu, assuming that the kernel context is available
1459 1445 * to successfully start another cpu.
1460 1446 *
1461 1447 * (For example, real mode code is mapped into the right place
1462 1448 * in memory and is ready to be run.)
1463 1449 */
1464 1450 int
1465 1451 start_cpu(processorid_t who)
1466 1452 {
1467 1453 cpu_t *cp;
1468 1454 int error = 0;
1469 1455 cpuset_t tempset;
1470 1456
1471 1457 ASSERT(who != 0);
1472 1458
1473 1459 /*
1474 1460 * Check if there's at least a Mbyte of kmem available
1475 1461 * before attempting to start the cpu.
1476 1462 */
1477 1463 if (kmem_avail() < 1024 * 1024) {
1478 1464 /*
1479 1465 * Kick off a reap in case that helps us with
1480 1466 * later attempts ..
1481 1467 */
1482 1468 kmem_reap();
1483 1469 return (ENOMEM);
1484 1470 }
1485 1471
1486 1472 /*
1487 1473 * First configure cpu.
1488 1474 */
1489 1475 cp = mp_cpu_configure_common(who, B_TRUE);
1490 1476 ASSERT(cp != NULL);
1491 1477
1492 1478 /*
1493 1479 * Then start cpu.
1494 1480 */
1495 1481 error = mp_start_cpu_common(cp, B_TRUE);
1496 1482 if (error != 0) {
1497 1483 mp_cpu_unconfigure_common(cp, error);
1498 1484 return (error);
1499 1485 }
1500 1486
1501 1487 mutex_exit(&cpu_lock);
1502 1488 tempset = cpu_ready_set;
1503 1489 while (!CPU_IN_SET(tempset, who)) {
1504 1490 drv_usecwait(1);
1505 1491 tempset = *((volatile cpuset_t *)&cpu_ready_set);
1506 1492 }
1507 1493 mutex_enter(&cpu_lock);
1508 1494
1509 1495 return (0);
1510 1496 }
1511 1497
1512 1498 void
1513 1499 start_other_cpus(int cprboot)
1514 1500 {
1515 1501 _NOTE(ARGUNUSED(cprboot));
1516 1502
1517 1503 uint_t who;
1518 1504 uint_t bootcpuid = 0;
1519 1505
1520 1506 /*
1521 1507 * Initialize our own cpu_info.
1522 1508 */
1523 1509 init_cpu_info(CPU);
1524 1510
1525 1511 #if !defined(__xpv)
1526 1512 init_cpu_id_gdt(CPU);
1527 1513 #endif
1528 1514
1529 1515 cmn_err(CE_CONT, "?cpu%d: %s\n", CPU->cpu_id, CPU->cpu_idstr);
1530 1516 cmn_err(CE_CONT, "?cpu%d: %s\n", CPU->cpu_id, CPU->cpu_brandstr);
1531 1517
1532 1518 /*
1533 1519 * KPTI initialisation happens very early in boot, before logging is
1534 1520 * set up. Output a status message now as the boot CPU comes online.
1535 1521 */
1536 1522 cmn_err(CE_CONT, "?KPTI %s (PCID %s, INVPCID %s)\n",
1537 1523 kpti_enable ? "enabled" : "disabled",
1538 1524 x86_use_pcid == 1 ? "in use" :
1539 1525 (is_x86_feature(x86_featureset, X86FSET_PCID) ? "disabled" :
1540 1526 "not supported"),
1541 1527 x86_use_pcid == 1 && x86_use_invpcid == 1 ? "in use" :
1542 1528 (is_x86_feature(x86_featureset, X86FSET_INVPCID) ? "disabled" :
1543 1529 "not supported"));
1544 1530
1545 1531 /*
1546 1532 * Initialize our syscall handlers
1547 1533 */
1548 1534 init_cpu_syscall(CPU);
1549 1535
1550 1536 /*
1551 1537 * Take the boot cpu out of the mp_cpus set because we know
1552 1538 * it's already running. Add it to the cpu_ready_set for
1553 1539 * precisely the same reason.
1554 1540 */
1555 1541 CPUSET_DEL(mp_cpus, bootcpuid);
1556 1542 CPUSET_ADD(cpu_ready_set, bootcpuid);
1557 1543
1558 1544 /*
1559 1545 * skip the rest of this if
1560 1546 * . only 1 cpu dectected and system isn't hotplug-capable
1561 1547 * . not using MP
1562 1548 */
1563 1549 if ((CPUSET_ISNULL(mp_cpus) && plat_dr_support_cpu() == 0) ||
1564 1550 use_mp == 0) {
1565 1551 if (use_mp == 0)
1566 1552 cmn_err(CE_CONT, "?***** Not in MP mode\n");
1567 1553 goto done;
1568 1554 }
1569 1555
1570 1556 /*
1571 1557 * perform such initialization as is needed
1572 1558 * to be able to take CPUs on- and off-line.
1573 1559 */
1574 1560 cpu_pause_init();
1575 1561
1576 1562 xc_init_cpu(CPU); /* initialize processor crosscalls */
1577 1563
1578 1564 if (mach_cpucontext_init() != 0)
1579 1565 goto done;
1580 1566
1581 1567 flushes_require_xcalls = 1;
1582 1568
1583 1569 /*
1584 1570 * We lock our affinity to the master CPU to ensure that all slave CPUs
1585 1571 * do their TSC syncs with the same CPU.
1586 1572 */
1587 1573 affinity_set(CPU_CURRENT);
1588 1574
1589 1575 for (who = 0; who < NCPU; who++) {
1590 1576 if (!CPU_IN_SET(mp_cpus, who))
1591 1577 continue;
1592 1578 ASSERT(who != bootcpuid);
1593 1579
1594 1580 mutex_enter(&cpu_lock);
1595 1581 if (start_cpu(who) != 0)
1596 1582 CPUSET_DEL(mp_cpus, who);
1597 1583 cpu_state_change_notify(who, CPU_SETUP);
1598 1584 mutex_exit(&cpu_lock);
1599 1585 }
1600 1586
1601 1587 /* Free the space allocated to hold the microcode file */
1602 1588 ucode_cleanup();
1603 1589
1604 1590 affinity_clear();
1605 1591
1606 1592 mach_cpucontext_fini();
1607 1593
1608 1594 done:
1609 1595 if (get_hwenv() == HW_NATIVE)
1610 1596 workaround_errata_end();
1611 1597 cmi_post_mpstartup();
1612 1598
1613 1599 if (use_mp && ncpus != boot_max_ncpus) {
1614 1600 cmn_err(CE_NOTE,
1615 1601 "System detected %d cpus, but "
1616 1602 "only %d cpu(s) were enabled during boot.",
1617 1603 boot_max_ncpus, ncpus);
1618 1604 cmn_err(CE_NOTE,
1619 1605 "Use \"boot-ncpus\" parameter to enable more CPU(s). "
1620 1606 "See eeprom(1M).");
1621 1607 }
1622 1608 }
1623 1609
1624 1610 int
1625 1611 mp_cpu_configure(int cpuid)
1626 1612 {
1627 1613 cpu_t *cp;
1628 1614
1629 1615 if (use_mp == 0 || plat_dr_support_cpu() == 0) {
1630 1616 return (ENOTSUP);
1631 1617 }
1632 1618
1633 1619 cp = cpu_get(cpuid);
1634 1620 if (cp != NULL) {
1635 1621 return (EALREADY);
1636 1622 }
1637 1623
1638 1624 /*
1639 1625 * Check if there's at least a Mbyte of kmem available
1640 1626 * before attempting to start the cpu.
1641 1627 */
1642 1628 if (kmem_avail() < 1024 * 1024) {
1643 1629 /*
1644 1630 * Kick off a reap in case that helps us with
1645 1631 * later attempts ..
1646 1632 */
1647 1633 kmem_reap();
1648 1634 return (ENOMEM);
1649 1635 }
1650 1636
1651 1637 cp = mp_cpu_configure_common(cpuid, B_FALSE);
1652 1638 ASSERT(cp != NULL && cpu_get(cpuid) == cp);
1653 1639
1654 1640 return (cp != NULL ? 0 : EAGAIN);
1655 1641 }
1656 1642
1657 1643 int
1658 1644 mp_cpu_unconfigure(int cpuid)
1659 1645 {
1660 1646 cpu_t *cp;
1661 1647
1662 1648 if (use_mp == 0 || plat_dr_support_cpu() == 0) {
1663 1649 return (ENOTSUP);
1664 1650 } else if (cpuid < 0 || cpuid >= max_ncpus) {
1665 1651 return (EINVAL);
1666 1652 }
1667 1653
1668 1654 cp = cpu_get(cpuid);
1669 1655 if (cp == NULL) {
1670 1656 return (ENODEV);
1671 1657 }
1672 1658 mp_cpu_unconfigure_common(cp, 0);
1673 1659
1674 1660 return (0);
1675 1661 }
1676 1662
1677 1663 /*
1678 1664 * Startup function for 'other' CPUs (besides boot cpu).
1679 1665 * Called from real_mode_start.
1680 1666 *
1681 1667 * WARNING: until CPU_READY is set, mp_startup_common and routines called by
1682 1668 * mp_startup_common should not call routines (e.g. kmem_free) that could call
1683 1669 * hat_unload which requires CPU_READY to be set.
1684 1670 */
1685 1671 static void
1686 1672 mp_startup_common(boolean_t boot)
1687 1673 {
1688 1674 cpu_t *cp = CPU;
1689 1675 uchar_t new_x86_featureset[BT_SIZEOFMAP(NUM_X86_FEATURES)];
1690 1676 extern void cpu_event_init_cpu(cpu_t *);
1691 1677
1692 1678 /*
1693 1679 * We need to get TSC on this proc synced (i.e., any delta
1694 1680 * from cpu0 accounted for) as soon as we can, because many
1695 1681 * many things use gethrtime/pc_gethrestime, including
1696 1682 * interrupts, cmn_err, etc. Before we can do that, we want to
1697 1683 * clear TSC if we're on a buggy Sandy/Ivy Bridge CPU, so do that
1698 1684 * right away.
1699 1685 */
1700 1686 bzero(new_x86_featureset, BT_SIZEOFMAP(NUM_X86_FEATURES));
1701 1687 cpuid_pass1(cp, new_x86_featureset);
1702 1688
1703 1689 if (boot && get_hwenv() == HW_NATIVE &&
1704 1690 cpuid_getvendor(CPU) == X86_VENDOR_Intel &&
1705 1691 cpuid_getfamily(CPU) == 6 &&
1706 1692 (cpuid_getmodel(CPU) == 0x2d || cpuid_getmodel(CPU) == 0x3e) &&
1707 1693 is_x86_feature(new_x86_featureset, X86FSET_TSC)) {
1708 1694 (void) wrmsr(REG_TSC, 0UL);
1709 1695 }
1710 1696
1711 1697 /* Let the control CPU continue into tsc_sync_master() */
1712 1698 mp_startup_signal(&procset_slave, cp->cpu_id);
1713 1699
1714 1700 #ifndef __xpv
1715 1701 if (tsc_gethrtime_enable)
1716 1702 tsc_sync_slave();
1717 1703 #endif
1718 1704
1719 1705 /*
1720 1706 * Once this was done from assembly, but it's safer here; if
1721 1707 * it blocks, we need to be able to swtch() to and from, and
1722 1708 * since we get here by calling t_pc, we need to do that call
1723 1709 * before swtch() overwrites it.
1724 1710 */
1725 1711 (void) (*ap_mlsetup)();
1726 1712
1727 1713 #ifndef __xpv
1728 1714 /*
1729 1715 * Program this cpu's PAT
1730 1716 */
1731 1717 pat_sync();
1732 1718 #endif
1733 1719
1734 1720 /*
1735 1721 * Set up TSC_AUX to contain the cpuid for this processor
1736 1722 * for the rdtscp instruction.
1737 1723 */
1738 1724 if (is_x86_feature(x86_featureset, X86FSET_TSCP))
1739 1725 (void) wrmsr(MSR_AMD_TSCAUX, cp->cpu_id);
1740 1726
1741 1727 /*
1742 1728 * Initialize this CPU's syscall handlers
1743 1729 */
1744 1730 init_cpu_syscall(cp);
1745 1731
1746 1732 /*
1747 1733 * Enable interrupts with spl set to LOCK_LEVEL. LOCK_LEVEL is the
1748 1734 * highest level at which a routine is permitted to block on
1749 1735 * an adaptive mutex (allows for cpu poke interrupt in case
1750 1736 * the cpu is blocked on a mutex and halts). Setting LOCK_LEVEL blocks
1751 1737 * device interrupts that may end up in the hat layer issuing cross
1752 1738 * calls before CPU_READY is set.
1753 1739 */
1754 1740 splx(ipltospl(LOCK_LEVEL));
1755 1741 sti();
1756 1742
1757 1743 /*
1758 1744 * Do a sanity check to make sure this new CPU is a sane thing
1759 1745 * to add to the collection of processors running this system.
1760 1746 *
1761 1747 * XXX Clearly this needs to get more sophisticated, if x86
1762 1748 * systems start to get built out of heterogenous CPUs; as is
1763 1749 * likely to happen once the number of processors in a configuration
1764 1750 * gets large enough.
1765 1751 */
1766 1752 if (compare_x86_featureset(x86_featureset, new_x86_featureset) ==
1767 1753 B_FALSE) {
1768 1754 cmn_err(CE_CONT, "cpu%d: featureset\n", cp->cpu_id);
1769 1755 print_x86_featureset(new_x86_featureset);
1770 1756 cmn_err(CE_WARN, "cpu%d feature mismatch", cp->cpu_id);
1771 1757 }
1772 1758
1773 1759 /*
1774 1760 * There exists a small subset of systems which expose differing
1775 1761 * MWAIT/MONITOR support between CPUs. If MWAIT support is absent from
1776 1762 * the boot CPU, but is found on a later CPU, the system continues to
1777 1763 * operate as if no MWAIT support is available.
1778 1764 *
1779 1765 * The reverse case, where MWAIT is available on the boot CPU but not
1780 1766 * on a subsequently initialized CPU, is not presently allowed and will
1781 1767 * result in a panic.
1782 1768 */
1783 1769 if (is_x86_feature(x86_featureset, X86FSET_MWAIT) !=
1784 1770 is_x86_feature(new_x86_featureset, X86FSET_MWAIT)) {
1785 1771 if (!is_x86_feature(x86_featureset, X86FSET_MWAIT)) {
1786 1772 remove_x86_feature(new_x86_featureset, X86FSET_MWAIT);
1787 1773 } else {
1788 1774 panic("unsupported mixed cpu mwait support detected");
1789 1775 }
1790 1776 }
1791 1777
1792 1778 /*
1793 1779 * We could be more sophisticated here, and just mark the CPU
1794 1780 * as "faulted" but at this point we'll opt for the easier
1795 1781 * answer of dying horribly. Provided the boot cpu is ok,
1796 1782 * the system can be recovered by booting with use_mp set to zero.
1797 1783 */
1798 1784 if (workaround_errata(cp) != 0)
1799 1785 panic("critical workaround(s) missing for cpu%d", cp->cpu_id);
1800 1786
1801 1787 /*
1802 1788 * We can touch cpu_flags here without acquiring the cpu_lock here
1803 1789 * because the cpu_lock is held by the control CPU which is running
1804 1790 * mp_start_cpu_common().
1805 1791 * Need to clear CPU_QUIESCED flag before calling any function which
1806 1792 * may cause thread context switching, such as kmem_alloc() etc.
1807 1793 * The idle thread checks for CPU_QUIESCED flag and loops for ever if
1808 1794 * it's set. So the startup thread may have no chance to switch back
1809 1795 * again if it's switched away with CPU_QUIESCED set.
1810 1796 */
1811 1797 cp->cpu_flags &= ~(CPU_POWEROFF | CPU_QUIESCED);
1812 1798
1813 1799 enable_pcid();
1814 1800
1815 1801 /*
1816 1802 * Setup this processor for XSAVE.
1817 1803 */
1818 1804 if (fp_save_mech == FP_XSAVE) {
1819 1805 xsave_setup_msr(cp);
1820 1806 }
1821 1807
1822 1808 cpuid_pass2(cp);
1823 1809 cpuid_pass3(cp);
1824 1810 cpuid_pass4(cp, NULL);
1825 1811
1826 1812 /*
1827 1813 * Correct cpu_idstr and cpu_brandstr on target CPU after
1828 1814 * cpuid_pass1() is done.
1829 1815 */
1830 1816 (void) cpuid_getidstr(cp, cp->cpu_idstr, CPU_IDSTRLEN);
1831 1817 (void) cpuid_getbrandstr(cp, cp->cpu_brandstr, CPU_IDSTRLEN);
1832 1818
1833 1819 cp->cpu_flags |= CPU_RUNNING | CPU_READY | CPU_EXISTS;
1834 1820
1835 1821 post_startup_cpu_fixups();
1836 1822
1837 1823 cpu_event_init_cpu(cp);
1838 1824
1839 1825 /*
1840 1826 * Enable preemption here so that contention for any locks acquired
1841 1827 * later in mp_startup_common may be preempted if the thread owning
1842 1828 * those locks is continuously executing on other CPUs (for example,
1843 1829 * this CPU must be preemptible to allow other CPUs to pause it during
1844 1830 * their startup phases). It's safe to enable preemption here because
1845 1831 * the CPU state is pretty-much fully constructed.
1846 1832 */
1847 1833 curthread->t_preempt = 0;
1848 1834
1849 1835 /* The base spl should still be at LOCK LEVEL here */
1850 1836 ASSERT(cp->cpu_base_spl == ipltospl(LOCK_LEVEL));
1851 1837 set_base_spl(); /* Restore the spl to its proper value */
1852 1838
1853 1839 pghw_physid_create(cp);
1854 1840 /*
1855 1841 * Delegate initialization tasks, which need to access the cpu_lock,
1856 1842 * to mp_start_cpu_common() because we can't acquire the cpu_lock here
1857 1843 * during CPU DR operations.
1858 1844 */
1859 1845 mp_startup_signal(&procset_slave, cp->cpu_id);
1860 1846 mp_startup_wait(&procset_master, cp->cpu_id);
1861 1847 pg_cmt_cpu_startup(cp);
1862 1848
1863 1849 if (boot) {
1864 1850 mutex_enter(&cpu_lock);
1865 1851 cp->cpu_flags &= ~CPU_OFFLINE;
1866 1852 cpu_enable_intr(cp);
1867 1853 cpu_add_active(cp);
1868 1854 mutex_exit(&cpu_lock);
1869 1855 }
1870 1856
1871 1857 /* Enable interrupts */
1872 1858 (void) spl0();
1873 1859
1874 1860 /*
1875 1861 * Fill out cpu_ucode_info. Update microcode if necessary.
1876 1862 */
1877 1863 ucode_check(cp);
1878 1864
1879 1865 #ifndef __xpv
1880 1866 {
1881 1867 /*
1882 1868 * Set up the CPU module for this CPU. This can't be done
1883 1869 * before this CPU is made CPU_READY, because we may (in
1884 1870 * heterogeneous systems) need to go load another CPU module.
1885 1871 * The act of attempting to load a module may trigger a
1886 1872 * cross-call, which will ASSERT unless this cpu is CPU_READY.
1887 1873 */
1888 1874 cmi_hdl_t hdl;
1889 1875
1890 1876 if ((hdl = cmi_init(CMI_HDL_NATIVE, cmi_ntv_hwchipid(CPU),
1891 1877 cmi_ntv_hwcoreid(CPU), cmi_ntv_hwstrandid(CPU))) != NULL) {
1892 1878 if (is_x86_feature(x86_featureset, X86FSET_MCA))
1893 1879 cmi_mca_init(hdl);
1894 1880 cp->cpu_m.mcpu_cmi_hdl = hdl;
1895 1881 }
1896 1882 }
1897 1883 #endif /* __xpv */
1898 1884
1899 1885 if (boothowto & RB_DEBUG)
1900 1886 kdi_cpu_init();
1901 1887
1902 1888 /*
1903 1889 * Setting the bit in cpu_ready_set must be the last operation in
1904 1890 * processor initialization; the boot CPU will continue to boot once
1905 1891 * it sees this bit set for all active CPUs.
1906 1892 */
1907 1893 CPUSET_ATOMIC_ADD(cpu_ready_set, cp->cpu_id);
1908 1894
1909 1895 (void) mach_cpu_create_device_node(cp, NULL);
1910 1896
1911 1897 cmn_err(CE_CONT, "?cpu%d: %s\n", cp->cpu_id, cp->cpu_idstr);
1912 1898 cmn_err(CE_CONT, "?cpu%d: %s\n", cp->cpu_id, cp->cpu_brandstr);
1913 1899 cmn_err(CE_CONT, "?cpu%d initialization complete - online\n",
1914 1900 cp->cpu_id);
1915 1901
1916 1902 /*
1917 1903 * Now we are done with the startup thread, so free it up.
1918 1904 */
1919 1905 thread_exit();
1920 1906 panic("mp_startup: cannot return");
1921 1907 /*NOTREACHED*/
1922 1908 }
1923 1909
1924 1910 /*
1925 1911 * Startup function for 'other' CPUs at boot time (besides boot cpu).
1926 1912 */
1927 1913 static void
1928 1914 mp_startup_boot(void)
1929 1915 {
1930 1916 mp_startup_common(B_TRUE);
1931 1917 }
1932 1918
1933 1919 /*
1934 1920 * Startup function for hotplug CPUs at runtime.
1935 1921 */
1936 1922 void
1937 1923 mp_startup_hotplug(void)
1938 1924 {
1939 1925 mp_startup_common(B_FALSE);
1940 1926 }
1941 1927
1942 1928 /*
1943 1929 * Start CPU on user request.
1944 1930 */
1945 1931 /* ARGSUSED */
1946 1932 int
1947 1933 mp_cpu_start(struct cpu *cp)
1948 1934 {
1949 1935 ASSERT(MUTEX_HELD(&cpu_lock));
1950 1936 return (0);
1951 1937 }
1952 1938
1953 1939 /*
1954 1940 * Stop CPU on user request.
1955 1941 */
1956 1942 int
1957 1943 mp_cpu_stop(struct cpu *cp)
1958 1944 {
1959 1945 extern int cbe_psm_timer_mode;
1960 1946 ASSERT(MUTEX_HELD(&cpu_lock));
1961 1947
1962 1948 #ifdef __xpv
1963 1949 /*
1964 1950 * We can't offline vcpu0.
1965 1951 */
1966 1952 if (cp->cpu_id == 0)
1967 1953 return (EBUSY);
1968 1954 #endif
1969 1955
1970 1956 /*
1971 1957 * If TIMER_PERIODIC mode is used, CPU0 is the one running it;
1972 1958 * can't stop it. (This is true only for machines with no TSC.)
1973 1959 */
1974 1960
1975 1961 if ((cbe_psm_timer_mode == TIMER_PERIODIC) && (cp->cpu_id == 0))
1976 1962 return (EBUSY);
1977 1963
1978 1964 return (0);
1979 1965 }
1980 1966
1981 1967 /*
1982 1968 * Take the specified CPU out of participation in interrupts.
1983 1969 */
1984 1970 int
1985 1971 cpu_disable_intr(struct cpu *cp)
1986 1972 {
1987 1973 if (psm_disable_intr(cp->cpu_id) != DDI_SUCCESS)
1988 1974 return (EBUSY);
1989 1975
1990 1976 cp->cpu_flags &= ~CPU_ENABLE;
1991 1977 return (0);
1992 1978 }
1993 1979
1994 1980 /*
1995 1981 * Allow the specified CPU to participate in interrupts.
1996 1982 */
1997 1983 void
1998 1984 cpu_enable_intr(struct cpu *cp)
1999 1985 {
2000 1986 ASSERT(MUTEX_HELD(&cpu_lock));
2001 1987 cp->cpu_flags |= CPU_ENABLE;
2002 1988 psm_enable_intr(cp->cpu_id);
2003 1989 }
2004 1990
2005 1991 void
2006 1992 mp_cpu_faulted_enter(struct cpu *cp)
2007 1993 {
2008 1994 #ifdef __xpv
2009 1995 _NOTE(ARGUNUSED(cp));
2010 1996 #else
2011 1997 cmi_hdl_t hdl = cp->cpu_m.mcpu_cmi_hdl;
2012 1998
2013 1999 if (hdl != NULL) {
2014 2000 cmi_hdl_hold(hdl);
2015 2001 } else {
2016 2002 hdl = cmi_hdl_lookup(CMI_HDL_NATIVE, cmi_ntv_hwchipid(cp),
2017 2003 cmi_ntv_hwcoreid(cp), cmi_ntv_hwstrandid(cp));
2018 2004 }
2019 2005 if (hdl != NULL) {
2020 2006 cmi_faulted_enter(hdl);
2021 2007 cmi_hdl_rele(hdl);
2022 2008 }
2023 2009 #endif
2024 2010 }
2025 2011
2026 2012 void
2027 2013 mp_cpu_faulted_exit(struct cpu *cp)
2028 2014 {
2029 2015 #ifdef __xpv
2030 2016 _NOTE(ARGUNUSED(cp));
2031 2017 #else
2032 2018 cmi_hdl_t hdl = cp->cpu_m.mcpu_cmi_hdl;
2033 2019
2034 2020 if (hdl != NULL) {
2035 2021 cmi_hdl_hold(hdl);
2036 2022 } else {
2037 2023 hdl = cmi_hdl_lookup(CMI_HDL_NATIVE, cmi_ntv_hwchipid(cp),
2038 2024 cmi_ntv_hwcoreid(cp), cmi_ntv_hwstrandid(cp));
2039 2025 }
2040 2026 if (hdl != NULL) {
2041 2027 cmi_faulted_exit(hdl);
2042 2028 cmi_hdl_rele(hdl);
2043 2029 }
2044 2030 #endif
2045 2031 }
2046 2032
2047 2033 /*
2048 2034 * The following two routines are used as context operators on threads belonging
2049 2035 * to processes with a private LDT (see sysi86). Due to the rarity of such
2050 2036 * processes, these routines are currently written for best code readability and
2051 2037 * organization rather than speed. We could avoid checking x86_featureset at
2052 2038 * every context switch by installing different context ops, depending on
2053 2039 * x86_featureset, at LDT creation time -- one for each combination of fast
2054 2040 * syscall features.
2055 2041 */
2056 2042
2057 2043 void
2058 2044 cpu_fast_syscall_disable(void)
2059 2045 {
2060 2046 if (is_x86_feature(x86_featureset, X86FSET_MSR) &&
2061 2047 is_x86_feature(x86_featureset, X86FSET_SEP))
2062 2048 cpu_sep_disable();
2063 2049 if (is_x86_feature(x86_featureset, X86FSET_MSR) &&
2064 2050 is_x86_feature(x86_featureset, X86FSET_ASYSC))
2065 2051 cpu_asysc_disable();
2066 2052 }
2067 2053
2068 2054 void
2069 2055 cpu_fast_syscall_enable(void)
2070 2056 {
2071 2057 if (is_x86_feature(x86_featureset, X86FSET_MSR) &&
2072 2058 is_x86_feature(x86_featureset, X86FSET_SEP))
2073 2059 cpu_sep_enable();
2074 2060 if (is_x86_feature(x86_featureset, X86FSET_MSR) &&
2075 2061 is_x86_feature(x86_featureset, X86FSET_ASYSC))
2076 2062 cpu_asysc_enable();
2077 2063 }
2078 2064
2079 2065 static void
2080 2066 cpu_sep_enable(void)
2081 2067 {
2082 2068 ASSERT(is_x86_feature(x86_featureset, X86FSET_SEP));
2083 2069 ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL);
2084 2070
2085 2071 wrmsr(MSR_INTC_SEP_CS, (uint64_t)(uintptr_t)KCS_SEL);
2086 2072 }
2087 2073
2088 2074 static void
2089 2075 cpu_sep_disable(void)
2090 2076 {
2091 2077 ASSERT(is_x86_feature(x86_featureset, X86FSET_SEP));
2092 2078 ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL);
2093 2079
2094 2080 /*
2095 2081 * Setting the SYSENTER_CS_MSR register to 0 causes software executing
2096 2082 * the sysenter or sysexit instruction to trigger a #gp fault.
2097 2083 */
2098 2084 wrmsr(MSR_INTC_SEP_CS, 0);
2099 2085 }
2100 2086
2101 2087 static void
2102 2088 cpu_asysc_enable(void)
2103 2089 {
2104 2090 ASSERT(is_x86_feature(x86_featureset, X86FSET_ASYSC));
2105 2091 ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL);
2106 2092
2107 2093 wrmsr(MSR_AMD_EFER, rdmsr(MSR_AMD_EFER) |
2108 2094 (uint64_t)(uintptr_t)AMD_EFER_SCE);
2109 2095 }
2110 2096
2111 2097 static void
2112 2098 cpu_asysc_disable(void)
2113 2099 {
2114 2100 ASSERT(is_x86_feature(x86_featureset, X86FSET_ASYSC));
2115 2101 ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL);
2116 2102
2117 2103 /*
2118 2104 * Turn off the SCE (syscall enable) bit in the EFER register. Software
2119 2105 * executing syscall or sysret with this bit off will incur a #ud trap.
2120 2106 */
2121 2107 wrmsr(MSR_AMD_EFER, rdmsr(MSR_AMD_EFER) &
2122 2108 ~((uint64_t)(uintptr_t)AMD_EFER_SCE));
2123 2109 }
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