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8368 remove warlock leftovers from usr/src/uts

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          --- old/usr/src/uts/common/io/ib/adapters/tavor/tavor_event.c
          +++ new/usr/src/uts/common/io/ib/adapters/tavor/tavor_event.c
↓ open down ↓ 655 lines elided ↑ open up ↑
 656  656  {
 657  657          uint64_t        *clr_ecr;
 658  658          tavor_hw_eqe_t  *eqe;
 659  659          uint64_t        ecr_mask;
 660  660          uint32_t        cons_indx, wrap_around_mask;
 661  661          int (*eqfunction)(tavor_state_t *state, tavor_eqhdl_t eq,
 662  662              tavor_hw_eqe_t *eqe);
 663  663  
 664  664          TAVOR_TNF_ENTER(tavor_eq_poll);
 665  665  
 666      -        _NOTE(NOW_INVISIBLE_TO_OTHER_THREADS(*eq))
 667      -
 668  666          /* Find the pointer to the clr_ECR register */
 669  667          clr_ecr = state->ts_cmd_regs.clr_ecr;
 670  668  
 671  669          /*
 672  670           * Check for Local Catastrophic Error If we have this kind of error,
 673  671           * then we don't need to do anything else here, as this kind of
 674  672           * catastrophic error is handled separately.  So we call the
 675  673           * catastrophic handler, clear the ECR and then return.
 676  674           */
 677  675          if (eq->eq_evttypemask == TAVOR_EVT_MSK_LOCAL_CAT_ERROR) {
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 695  693          cons_indx = eq->eq_consindx;
 696  694  
 697  695          /*
 698  696           * Calculate the wrap around mask.  Note: This operation only works
 699  697           * because all Tavor event queues have power-of-2 sizes
 700  698           */
 701  699          wrap_around_mask = (eq->eq_bufsz - 1);
 702  700  
 703  701          /* Calculate the pointer to the first EQ entry */
 704  702          eqe = &eq->eq_buf[cons_indx];
 705      -        _NOTE(NOW_INVISIBLE_TO_OTHER_THREADS(*eqe))
 706  703  
 707  704          /*
 708  705           * Sync the current EQE to read
 709  706           *    We need to force a ddi_dma_sync() here (independent of how the
 710  707           *    EQ was mapped) because it is possible for us to receive the
 711  708           *    interrupt, do a read of the ECR, and have each of these
 712  709           *    operations complete successfully even though the hardware's DMA
 713  710           *    to the EQ has not yet completed.
 714  711           */
 715  712          tavor_eqe_sync(eq, eqe, DDI_DMA_SYNC_FORCPU, TAVOR_EQ_SYNC_FORCE);
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1005 1002          }
1006 1003          op.mro_bind_type   = state->ts_cfg_profile->cp_iommu_bypass;
1007 1004          op.mro_bind_dmahdl = eq->eq_eqinfo.qa_dmahdl;
1008 1005          op.mro_bind_override_addr = 0;
1009 1006          status = tavor_mr_register(state, pd, &mr_attr, &mr, &op);
1010 1007          if (status != DDI_SUCCESS) {
1011 1008                  /* Set "status" and "errormsg" and goto failure */
1012 1009                  TAVOR_TNF_FAIL(DDI_FAILURE, "failed register mr");
1013 1010                  goto eqalloc_fail4;
1014 1011          }
1015      -        _NOTE(NOW_INVISIBLE_TO_OTHER_THREADS(*mr))
1016 1012          addr = mr->mr_bindinfo.bi_addr;
1017 1013          lkey = mr->mr_lkey;
1018 1014  
1019 1015          /* Determine if later ddi_dma_sync will be necessary */
1020 1016          eq->eq_sync = TAVOR_EQ_IS_SYNC_REQ(state, eq->eq_eqinfo);
1021 1017  
1022 1018          /* Sync entire EQ for use by the hardware (if necessary) */
1023 1019          if (eq->eq_sync) {
1024 1020                  (void) ddi_dma_sync(mr->mr_bindinfo.bi_dmahdl, 0,
1025 1021                      eq->eq_eqinfo.qa_size, DDI_DMA_SYNC_FORDEV);
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