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8368 remove warlock leftovers from usr/src/uts
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--- old/usr/src/uts/common/io/ecpp.c
+++ new/usr/src/uts/common/io/ecpp.c
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21 /*
22 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
23 23 * Use is subject to license terms.
24 24 */
25 25
26 26
27 27 /*
28 28 *
29 29 * IEEE 1284 Parallel Port Device Driver
30 30 *
31 31 */
32 32
33 33 #include <sys/param.h>
34 34 #include <sys/errno.h>
35 35 #include <sys/file.h>
36 36 #include <sys/cmn_err.h>
37 37 #include <sys/stropts.h>
38 38 #include <sys/debug.h>
39 39 #include <sys/stream.h>
40 40 #include <sys/strsun.h>
41 41 #include <sys/kmem.h>
42 42 #include <sys/ddi.h>
43 43 #include <sys/sunddi.h>
44 44 #include <sys/conf.h> /* req. by dev_ops flags MTSAFE etc. */
45 45 #include <sys/modctl.h> /* for modldrv */
46 46 #include <sys/stat.h> /* ddi_create_minor_node S_IFCHR */
47 47 #include <sys/open.h>
48 48 #include <sys/ddi_impldefs.h>
49 49 #include <sys/kstat.h>
50 50
51 51 #include <sys/prnio.h>
52 52 #include <sys/ecppreg.h> /* hw description */
53 53 #include <sys/ecppio.h> /* ioctl description */
54 54 #include <sys/ecppvar.h> /* driver description */
55 55 #include <sys/dma_engine.h>
56 56 #include <sys/dma_i8237A.h>
57 57
58 58 /*
59 59 * Background
60 60 * ==========
61 61 * IEEE 1284-1994 standard defines "a signalling method for asynchronous,
62 62 * fully interlocked, bidirectional parallel communications between hosts
63 63 * and printers or other peripherals." (1.1) The standard defines 5 modes
64 64 * of operation - Compatibility, Nibble, Byte, ECP and EPP - which differ
65 65 * in direction, bandwidth, pins assignment, DMA capability, etc.
66 66 *
67 67 * Negotiation is a mechanism for moving between modes. Compatibility mode
68 68 * is a default mode, from which negotiations to other modes occur and
69 69 * to which both host and peripheral break in case of interface errors.
70 70 * Compatibility mode provides a unidirectional (forward) channel for
71 71 * communicating with old pre-1284 peripherals.
72 72 *
73 73 * Each mode has a number of phases. [Mode, phase] pair represents the
74 74 * interface state. Host initiates all transfers, though peripheral can
75 75 * request backchannel transfer by asserting nErr pin.
76 76 *
77 77 * Ecpp driver implements an IEEE 1284-compliant host using a combination
78 78 * of hardware and software. Hardware part is represented by a controller,
79 79 * which is a part of the SuperIO chip. Ecpp supports the following SuperIOs:
80 80 * PC82332/PC82336 (U5/U10/U60), PC97317 (U100), M1553 (Grover).
81 81 * Struct ecpp_hw describes each SuperIO and is determined in ecpp_attach().
82 82 *
83 83 * Negotiation is performed in software. Transfer may be performed either
84 84 * in software by driving output pins for each byte (PIO method), or with
85 85 * hardware assistance - SuperIO has a 16-byte FIFO, which is filled by
86 86 * the driver (normally using DMA), while the chip performs the actual xfer.
87 87 * PIO is used for Nibble and Compat, DMA is used for ECP and Compat modes.
88 88 *
89 89 * Driver currently supports the following modes:
90 90 *
91 91 * - Compatibility mode: byte-wide forward channel ~50KB/sec;
92 92 * pp->io_mode defines PIO or DMA method of transfer;
93 93 * - Nibble mode: nibble-wide (4-bit) reverse channel ~30KB/sec;
94 94 * - ECP mode: byte-wide bidirectional channel (~1MB/sec);
95 95 *
96 96 * Theory of operation
97 97 * ===================
98 98 * The manner in which ecpp drives 1284 interface is that of a state machine.
99 99 * State is a combination of 1284 mode {ECPP_*_MODE}, 1284 phase {ECPP_PHASE_*}
100 100 * and transfer method {PIO, DMA}. State is a function of application actions
101 101 * {write(2), ioctl(2)} and peripheral reaction.
102 102 *
103 103 * 1284 interface state is described by the following variables:
104 104 * pp->current_mode -- 1284 mode used for forward transfers;
105 105 * pp->backchannel -- 1284 mode used for backward transfers;
106 106 * pp->curent_phase -- 1284 phase;
107 107 *
108 108 * Bidirectional operation in Compatibility mode is provided by a combination:
109 109 * pp->current_mode == ECPP_COMPAT_MODE && pp->backchannel == ECPP_NIBBLE_MODE
110 110 * ECPP_CENTRONICS means no backchannel
111 111 *
112 112 * Driver internal state is defined by pp->e_busy as follows:
113 113 * ECPP_IDLE -- idle, no active transfers;
114 114 * ECPP_BUSY -- transfer is in progress;
115 115 * ECPP_ERR -- have data to transfer, but peripheral can`t receive data;
116 116 * ECPP_FLUSH -- flushing the queues;
117 117 *
118 118 * When opened, driver is in ECPP_IDLE state, current mode is ECPP_CENTRONICS
119 119 * Default negotiation tries to negotiate to the best mode supported by printer,
120 120 * sets pp->current_mode and pp->backchannel accordingly.
121 121 *
122 122 * When output data arrives in M_DATA mblks ecpp_wput() puts them on the queue
123 123 * to let ecpp_wsrv() concatenate small blocks into one big transfer
124 124 * by copying them into pp->ioblock. If first the mblk data is bigger than
125 125 * pp->ioblock, then it is used instead of i/o block (pointed by pp->msg)
126 126 *
127 127 * Before starting the transfer the driver will check if peripheral is ready
128 128 * by calling ecpp_check_status() and if it is not, driver goes ECPP_ERR state
129 129 * and schedules ecpp_wsrv_timer() which would qenable() the wq, effectively
130 130 * rechecking the peripheral readiness and restarting itself until it is ready.
131 131 * The transfer is then started by calling ecpp_start(), driver goes ECPP_BUSY
132 132 *
133 133 * While transfer is in progress all arriving messages will be queued up.
134 134 * Transfer can end up in either of two ways:
135 135 * - interrupt occurs, ecpp_isr() checks if all the data was transferred, if so
136 136 * cleanup and go ECPP_IDLE, otherwise putback untransferred and qenable();
137 137 * - ecpp_xfer_timeout() cancels the transfer and puts back untransferred data;
138 138 *
139 139 * PIO transfer method is very CPU intensive: for each sent byte the peripheral
140 140 * state is checked, then the byte is transfered and driver waits for an nAck
141 141 * interrupt; ecpp_isr() will then look if there is more data and if so
142 142 * triggers the soft interrupt, which transfers the next byte. PIO method
143 143 * is needed only for legacy printers which are sensitive to strobe problem
144 144 * (Bugid 4192788).
145 145 *
146 146 * ecpp_wsrv() is responsible for both starting transfers (ecpp_start()) and
147 147 * going idle (ecpp_idle_phase()). Many routines qenable() the write queue,
148 148 * meaning "check if there are pending requests, process them and go idle".
149 149 *
150 150 * In it`s idle state the driver will always try to listen to the backchannel
151 151 * (as advised by 1284).
152 152 *
153 153 * The mechanism for handling backchannel requests is as follows:
154 154 * - when the peripheral has data to send it asserts nErr pin
155 155 * (and also nAck in Nibble Mode) which results in an interrupt on the host;
156 156 * - ISR creates M_CTL message containing an ECPP_BACKCHANNEL byte and
157 157 * puts it back on the write queue;
158 158 * - ecpp_wsrv() gets M_CTL and calls ecpp_peripheral2host(), which kicks off
159 159 * the transfer;
160 160 *
161 161 * This way Nibble and ECP mode backchannel are implemented.
162 162 * If the read queue gets full, backchannel request is rejected.
163 163 * As the application reads data and queue size falls below the low watermark,
164 164 * ecpp_rsrv() gets called and enables the backchannel again.
165 165 *
166 166 * Future enhancements
167 167 * ===================
168 168 *
169 169 * Support new modes: Byte and EPP.
170 170 */
171 171
172 172 #ifndef ECPP_DEBUG
173 173 #define ECPP_DEBUG 0
174 174 #endif /* ECPP_DEBUG */
175 175 int ecpp_debug = ECPP_DEBUG;
176 176
177 177 int noecp = 0; /* flag not to use ECP mode */
178 178
179 179 /* driver entry point fn definitions */
180 180 static int ecpp_open(queue_t *, dev_t *, int, int, cred_t *);
181 181 static int ecpp_close(queue_t *, int, cred_t *);
182 182 static uint_t ecpp_isr(caddr_t);
183 183 static uint_t ecpp_softintr(caddr_t);
184 184
185 185 /* configuration entry point fn definitions */
186 186 static int ecpp_getinfo(dev_info_t *, ddi_info_cmd_t, void *, void **);
187 187 static int ecpp_attach(dev_info_t *, ddi_attach_cmd_t);
188 188 static int ecpp_detach(dev_info_t *, ddi_detach_cmd_t);
189 189 static struct ecpp_hw_bind *ecpp_determine_sio_type(struct ecppunit *);
190 190
191 191 /* isr support routines */
192 192 static uint_t ecpp_nErr_ihdlr(struct ecppunit *);
193 193 static uint_t ecpp_pio_ihdlr(struct ecppunit *);
194 194 static uint_t ecpp_dma_ihdlr(struct ecppunit *);
195 195 static uint_t ecpp_M1553_intr(struct ecppunit *);
196 196
197 197 /* configuration support routines */
198 198 static void ecpp_get_props(struct ecppunit *);
199 199
200 200 /* Streams Routines */
201 201 static int ecpp_wput(queue_t *, mblk_t *);
202 202 static int ecpp_wsrv(queue_t *);
203 203 static int ecpp_rsrv(queue_t *);
204 204 static void ecpp_flush(struct ecppunit *, int);
205 205 static void ecpp_start(struct ecppunit *, caddr_t, size_t);
206 206
207 207 /* ioctl handling */
208 208 static void ecpp_putioc(queue_t *, mblk_t *);
209 209 static void ecpp_srvioc(queue_t *, mblk_t *);
210 210 static void ecpp_wput_iocdata_devid(queue_t *, mblk_t *, uintptr_t);
211 211 static void ecpp_putioc_copyout(queue_t *, mblk_t *, void *, int);
212 212 static void ecpp_putioc_stateful_copyin(queue_t *, mblk_t *, size_t);
213 213 static void ecpp_srvioc_devid(queue_t *, mblk_t *,
214 214 struct ecpp_device_id *, int *);
215 215 static void ecpp_srvioc_prnif(queue_t *, mblk_t *);
216 216 static void ecpp_ack_ioctl(queue_t *, mblk_t *);
217 217 static void ecpp_nack_ioctl(queue_t *, mblk_t *, int);
218 218
219 219 /* kstat routines */
220 220 static void ecpp_kstat_init(struct ecppunit *);
221 221 static int ecpp_kstat_update(kstat_t *, int);
222 222 static int ecpp_kstatintr_update(kstat_t *, int);
223 223
224 224 /* dma routines */
225 225 static void ecpp_putback_untransfered(struct ecppunit *, void *, uint_t);
226 226 static uint8_t ecpp_setup_dma_resources(struct ecppunit *, caddr_t, size_t);
227 227 static uint8_t ecpp_init_dma_xfer(struct ecppunit *, caddr_t, size_t);
228 228
229 229 /* pio routines */
230 230 static void ecpp_pio_writeb(struct ecppunit *);
231 231 static void ecpp_xfer_cleanup(struct ecppunit *);
232 232 static uint8_t ecpp_prep_pio_xfer(struct ecppunit *, caddr_t, size_t);
233 233
234 234 /* misc */
235 235 static uchar_t ecpp_reset_port_regs(struct ecppunit *);
236 236 static void ecpp_xfer_timeout(void *);
237 237 static void ecpp_fifo_timer(void *);
238 238 static void ecpp_wsrv_timer(void *);
239 239 static uchar_t dcr_write(struct ecppunit *, uint8_t);
240 240 static uchar_t ecr_write(struct ecppunit *, uint8_t);
241 241 static uchar_t ecpp_check_status(struct ecppunit *);
242 242 static int ecpp_backchan_req(struct ecppunit *);
243 243 static void ecpp_untimeout_unblock(struct ecppunit *, timeout_id_t *);
244 244 static uint_t ecpp_get_prn_ifcap(struct ecppunit *);
245 245
246 246 /* stubs */
247 247 static void empty_config_mode(struct ecppunit *);
248 248 static void empty_mask_intr(struct ecppunit *);
249 249
250 250 /* PC87332 support */
251 251 static int pc87332_map_regs(struct ecppunit *);
252 252 static void pc87332_unmap_regs(struct ecppunit *);
253 253 static int pc87332_config_chip(struct ecppunit *);
254 254 static void pc87332_config_mode(struct ecppunit *);
255 255 static uint8_t pc87332_read_config_reg(struct ecppunit *, uint8_t);
256 256 static void pc87332_write_config_reg(struct ecppunit *, uint8_t, uint8_t);
257 257 static void cheerio_mask_intr(struct ecppunit *);
258 258 static void cheerio_unmask_intr(struct ecppunit *);
259 259 static int cheerio_dma_start(struct ecppunit *);
260 260 static int cheerio_dma_stop(struct ecppunit *, size_t *);
261 261 static size_t cheerio_getcnt(struct ecppunit *);
262 262 static void cheerio_reset_dcsr(struct ecppunit *);
263 263
264 264 /* PC97317 support */
265 265 static int pc97317_map_regs(struct ecppunit *);
266 266 static void pc97317_unmap_regs(struct ecppunit *);
267 267 static int pc97317_config_chip(struct ecppunit *);
268 268 static void pc97317_config_mode(struct ecppunit *);
269 269
270 270 /* M1553 Southbridge support */
271 271 static int m1553_map_regs(struct ecppunit *pp);
272 272 static void m1553_unmap_regs(struct ecppunit *pp);
273 273 static int m1553_config_chip(struct ecppunit *);
274 274 static uint8_t m1553_read_config_reg(struct ecppunit *, uint8_t);
275 275 static void m1553_write_config_reg(struct ecppunit *, uint8_t, uint8_t);
276 276
277 277 /* M1553 Southbridge DMAC 8237 support routines */
278 278 static int dma8237_dma_start(struct ecppunit *);
279 279 static int dma8237_dma_stop(struct ecppunit *, size_t *);
280 280 static size_t dma8237_getcnt(struct ecppunit *);
281 281 static void dma8237_write_addr(struct ecppunit *, uint32_t);
282 282 static void dma8237_write_count(struct ecppunit *, uint32_t);
283 283 static uint32_t dma8237_read_count(struct ecppunit *);
284 284 static void dma8237_write(struct ecppunit *, int, uint8_t);
285 285 static uint8_t dma8237_read(struct ecppunit *, int);
286 286 #ifdef INCLUDE_DMA8237_READ_ADDR
287 287 static uint32_t dma8237_read_addr(struct ecppunit *);
288 288 #endif
289 289
290 290 /* i86 PC support rountines */
291 291
292 292 #if defined(__x86)
293 293 static int x86_dma_start(struct ecppunit *);
294 294 static int x86_dma_stop(struct ecppunit *, size_t *);
295 295 static int x86_map_regs(struct ecppunit *);
296 296 static void x86_unmap_regs(struct ecppunit *);
297 297 static int x86_config_chip(struct ecppunit *);
298 298 static size_t x86_getcnt(struct ecppunit *);
299 299 #endif
300 300
301 301 /* IEEE 1284 phase transitions */
302 302 static void ecpp_1284_init_interface(struct ecppunit *);
303 303 static int ecpp_1284_termination(struct ecppunit *);
304 304 static uchar_t ecpp_idle_phase(struct ecppunit *);
305 305 static int ecp_forward2reverse(struct ecppunit *);
306 306 static int ecp_reverse2forward(struct ecppunit *);
307 307 static int read_nibble_backchan(struct ecppunit *);
308 308
309 309 /* reverse transfers */
310 310 static uint_t ecpp_peripheral2host(struct ecppunit *);
311 311 static uchar_t ecp_peripheral2host(struct ecppunit *);
312 312 static uchar_t nibble_peripheral2host(struct ecppunit *pp, uint8_t *);
313 313 static int ecpp_getdevid(struct ecppunit *, uint8_t *, int *, int);
314 314 static void ecpp_ecp_read_timeout(void *);
315 315 static void ecpp_ecp_read_completion(struct ecppunit *);
316 316
317 317 /* IEEE 1284 mode transitions */
318 318 static void ecpp_default_negotiation(struct ecppunit *);
319 319 static int ecpp_mode_negotiation(struct ecppunit *, uchar_t);
320 320 static int ecpp_1284_negotiation(struct ecppunit *, uint8_t, uint8_t *);
321 321 static int ecp_negotiation(struct ecppunit *);
322 322 static int nibble_negotiation(struct ecppunit *);
323 323 static int devidnib_negotiation(struct ecppunit *);
324 324
325 325 /* IEEE 1284 utility routines */
326 326 static int wait_dsr(struct ecppunit *, uint8_t, uint8_t, int);
327 327
328 328 /* debugging functions */
329 329 static void ecpp_error(dev_info_t *, char *, ...);
330 330 static uchar_t ecpp_get_error_status(uchar_t);
331 331
332 332 /*
333 333 * Chip-dependent structures
334 334 */
335 335 static ddi_dma_attr_t cheerio_dma_attr = {
336 336 DMA_ATTR_VERSION, /* version */
337 337 0x00000000ull, /* dlim_addr_lo */
338 338 0xfffffffeull, /* dlim_addr_hi */
339 339 0xffffff, /* DMA counter register */
340 340 1, /* DMA address alignment */
341 341 0x74, /* burst sizes */
342 342 0x0001, /* min effective DMA size */
343 343 0xffff, /* maximum transfer size */
344 344 0xffff, /* segment boundary */
345 345 1, /* s/g list length */
346 346 1, /* granularity of device */
347 347 0 /* DMA flags */
348 348 };
349 349
350 350 static struct ecpp_hw pc87332 = {
351 351 pc87332_map_regs,
352 352 pc87332_unmap_regs,
353 353 pc87332_config_chip,
354 354 pc87332_config_mode,
355 355 cheerio_mask_intr,
356 356 cheerio_unmask_intr,
357 357 cheerio_dma_start,
358 358 cheerio_dma_stop,
359 359 cheerio_getcnt,
360 360 &cheerio_dma_attr
361 361 };
362 362
363 363 static struct ecpp_hw pc97317 = {
364 364 pc97317_map_regs,
365 365 pc97317_unmap_regs,
366 366 pc97317_config_chip,
367 367 pc97317_config_mode,
368 368 cheerio_mask_intr,
369 369 cheerio_unmask_intr,
370 370 cheerio_dma_start,
371 371 cheerio_dma_stop,
372 372 cheerio_getcnt,
373 373 &cheerio_dma_attr
374 374 };
375 375
376 376 static ddi_dma_attr_t i8237_dma_attr = {
377 377 DMA_ATTR_VERSION, /* version */
378 378 0x00000000ull, /* dlim_addr_lo */
379 379 0xfffffffeull, /* dlim_addr_hi */
380 380 0xffff, /* DMA counter register */
381 381 1, /* DMA address alignment */
382 382 0x01, /* burst sizes */
383 383 0x0001, /* min effective DMA size */
384 384 0xffff, /* maximum transfer size */
385 385 0x7fff, /* segment boundary */
386 386 1, /* s/g list length */
387 387 1, /* granularity of device */
388 388 0 /* DMA flags */
389 389 };
390 390
391 391 static struct ecpp_hw m1553 = {
392 392 m1553_map_regs,
393 393 m1553_unmap_regs,
394 394 m1553_config_chip,
395 395 empty_config_mode, /* no config_mode */
396 396 empty_mask_intr, /* no mask_intr */
397 397 empty_mask_intr, /* no unmask_intr */
398 398 dma8237_dma_start,
399 399 dma8237_dma_stop,
400 400 dma8237_getcnt,
401 401 &i8237_dma_attr
402 402 };
403 403
404 404 #if defined(__x86)
405 405 static ddi_dma_attr_t sb_dma_attr = {
406 406 DMA_ATTR_VERSION, /* version */
407 407 0x00000000ull, /* dlim_addr_lo */
408 408 0xffffff, /* dlim_addr_hi */
409 409 0xffff, /* DMA counter register */
410 410 1, /* DMA address alignment */
411 411 0x01, /* burst sizes */
412 412 0x0001, /* min effective DMA size */
413 413 0xffffffff, /* maximum transfer size */
414 414 0xffff, /* segment boundary */
415 415 1, /* s/g list length */
416 416 1, /* granularity of device */
417 417 0 /* DMA flags */
418 418 };
419 419
420 420 static struct ecpp_hw x86 = {
421 421 x86_map_regs,
422 422 x86_unmap_regs,
423 423 x86_config_chip,
424 424 empty_config_mode, /* no config_mode */
425 425 empty_mask_intr, /* no mask_intr */
426 426 empty_mask_intr, /* no unmask_intr */
427 427 x86_dma_start,
428 428 x86_dma_stop,
429 429 x86_getcnt,
430 430 &sb_dma_attr
431 431 };
432 432 #endif
433 433
434 434 /*
435 435 * list of supported devices
436 436 */
437 437 struct ecpp_hw_bind ecpp_hw_bind[] = {
438 438 { "ns87317-ecpp", &pc97317, "PC97317" },
439 439 { "pnpALI,1533,3", &m1553, "M1553" },
440 440 { "ecpp", &pc87332, "PC87332" },
441 441 #if defined(__x86)
442 442 { "lp", &x86, "i86pc"},
443 443 #endif
444 444 };
445 445
446 446 static ddi_device_acc_attr_t acc_attr = {
447 447 DDI_DEVICE_ATTR_V0,
448 448 DDI_STRUCTURE_LE_ACC,
449 449 DDI_STRICTORDER_ACC
450 450 };
451 451
452 452 static struct ecpp_transfer_parms default_xfer_parms = {
453 453 FWD_TIMEOUT_DEFAULT, /* write timeout in seconds */
454 454 ECPP_CENTRONICS /* supported mode */
455 455 };
456 456
457 457 /* prnio interface info string */
458 458 static const char prn_ifinfo[] = PRN_PARALLEL;
459 459
460 460 /* prnio timeouts */
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461 461 static const struct prn_timeouts prn_timeouts_default = {
462 462 FWD_TIMEOUT_DEFAULT, /* forward timeout */
463 463 REV_TIMEOUT_DEFAULT /* reverse timeout */
464 464 };
465 465
466 466 static int ecpp_isr_max_delay = ECPP_ISR_MAX_DELAY;
467 467 static int ecpp_def_timeout = 90; /* left in for 2.7 compatibility */
468 468
469 469 static void *ecppsoft_statep;
470 470
471 -/*
472 - * STREAMS framework manages locks for these structures
473 - */
474 -_NOTE(SCHEME_PROTECTS_DATA("unique per call", iocblk))
475 -_NOTE(SCHEME_PROTECTS_DATA("unique per call", datab))
476 -_NOTE(SCHEME_PROTECTS_DATA("unique per call", msgb))
477 -_NOTE(SCHEME_PROTECTS_DATA("unique per call", queue))
478 -_NOTE(SCHEME_PROTECTS_DATA("unique per call", copyreq))
479 -_NOTE(SCHEME_PROTECTS_DATA("unique per call", stroptions))
480 -
481 471 struct module_info ecppinfo = {
482 472 /* id, name, min pkt siz, max pkt siz, hi water, low water */
483 473 42, "ecpp", 0, IO_BLOCK_SZ, ECPPHIWAT, ECPPLOWAT
484 474 };
485 475
486 476 static struct qinit ecpp_rinit = {
487 477 putq, ecpp_rsrv, ecpp_open, ecpp_close, NULL, &ecppinfo, NULL
488 478 };
489 479
490 480 static struct qinit ecpp_wint = {
491 481 ecpp_wput, ecpp_wsrv, ecpp_open, ecpp_close, NULL, &ecppinfo, NULL
492 482 };
493 483
494 484 struct streamtab ecpp_str_info = {
495 485 &ecpp_rinit, &ecpp_wint, NULL, NULL
496 486 };
497 487
498 488 static struct cb_ops ecpp_cb_ops = {
499 489 nodev, /* cb_open */
500 490 nodev, /* cb_close */
501 491 nodev, /* cb_strategy */
502 492 nodev, /* cb_print */
503 493 nodev, /* cb_dump */
504 494 nodev, /* cb_read */
505 495 nodev, /* cb_write */
506 496 nodev, /* cb_ioctl */
507 497 nodev, /* cb_devmap */
508 498 nodev, /* cb_mmap */
509 499 nodev, /* cb_segmap */
510 500 nochpoll, /* cb_chpoll */
511 501 ddi_prop_op, /* cb_prop_op */
512 502 &ecpp_str_info, /* cb_stream */
513 503 (D_NEW | D_MP | D_MTPERQ) /* cb_flag */
514 504 };
515 505
516 506 /*
517 507 * Declare ops vectors for auto configuration.
518 508 */
519 509 struct dev_ops ecpp_ops = {
520 510 DEVO_REV, /* devo_rev */
521 511 0, /* devo_refcnt */
522 512 ecpp_getinfo, /* devo_getinfo */
523 513 nulldev, /* devo_identify */
524 514 nulldev, /* devo_probe */
525 515 ecpp_attach, /* devo_attach */
526 516 ecpp_detach, /* devo_detach */
527 517 nodev, /* devo_reset */
528 518 &ecpp_cb_ops, /* devo_cb_ops */
529 519 (struct bus_ops *)NULL, /* devo_bus_ops */
530 520 nulldev, /* devo_power */
531 521 ddi_quiesce_not_needed, /* devo_quiesce */
532 522 };
533 523
534 524 extern struct mod_ops mod_driverops;
535 525
536 526 static struct modldrv ecppmodldrv = {
537 527 &mod_driverops, /* type of module - driver */
538 528 "parallel port driver",
539 529 &ecpp_ops,
540 530 };
541 531
542 532 static struct modlinkage ecppmodlinkage = {
543 533 MODREV_1,
544 534 &ecppmodldrv,
545 535 0
546 536 };
547 537
548 538
549 539 /*
550 540 *
551 541 * DDI/DKI entry points and supplementary routines
552 542 *
553 543 */
554 544
555 545
556 546 int
557 547 _init(void)
558 548 {
559 549 int error;
560 550
561 551 if ((error = mod_install(&ecppmodlinkage)) == 0) {
562 552 (void) ddi_soft_state_init(&ecppsoft_statep,
563 553 sizeof (struct ecppunit), 1);
564 554 }
565 555
566 556 return (error);
567 557 }
568 558
569 559 int
570 560 _fini(void)
571 561 {
572 562 int error;
573 563
574 564 if ((error = mod_remove(&ecppmodlinkage)) == 0) {
575 565 ddi_soft_state_fini(&ecppsoft_statep);
576 566 }
577 567
578 568 return (error);
579 569 }
580 570
581 571 int
582 572 _info(struct modinfo *modinfop)
583 573 {
584 574 return (mod_info(&ecppmodlinkage, modinfop));
585 575 }
586 576
587 577 static int
588 578 ecpp_attach(dev_info_t *dip, ddi_attach_cmd_t cmd)
589 579 {
590 580 int instance;
591 581 char name[16];
592 582 struct ecppunit *pp;
593 583 struct ecpp_hw_bind *hw_bind;
594 584
595 585 instance = ddi_get_instance(dip);
596 586
597 587 switch (cmd) {
598 588 case DDI_ATTACH:
599 589 break;
600 590
601 591 case DDI_RESUME:
602 592 if (!(pp = ddi_get_soft_state(ecppsoft_statep, instance))) {
603 593 return (DDI_FAILURE);
604 594 }
605 595
606 596 mutex_enter(&pp->umutex);
607 597
608 598 pp->suspended = FALSE;
609 599
610 600 /*
611 601 * Initialize the chip and restore current mode if needed
612 602 */
613 603 (void) ECPP_CONFIG_CHIP(pp);
614 604 (void) ecpp_reset_port_regs(pp);
615 605
616 606 if (pp->oflag == TRUE) {
617 607 int current_mode = pp->current_mode;
618 608
619 609 (void) ecpp_1284_termination(pp);
620 610 (void) ecpp_mode_negotiation(pp, current_mode);
621 611 }
622 612
623 613 mutex_exit(&pp->umutex);
624 614
625 615 return (DDI_SUCCESS);
626 616
627 617 default:
628 618 return (DDI_FAILURE);
629 619 }
630 620
631 621 if (ddi_soft_state_zalloc(ecppsoft_statep, instance) != 0) {
632 622 ecpp_error(dip, "ddi_soft_state_zalloc failed\n");
633 623 goto fail;
634 624 }
635 625
636 626 pp = ddi_get_soft_state(ecppsoft_statep, instance);
637 627
638 628 pp->dip = dip;
639 629 pp->suspended = FALSE;
640 630
641 631 /*
642 632 * Determine SuperIO type and set chip-dependent variables
643 633 */
644 634 hw_bind = ecpp_determine_sio_type(pp);
645 635
646 636 if (hw_bind == NULL) {
647 637 cmn_err(CE_NOTE, "parallel port controller not supported");
648 638 goto fail_sio;
649 639 } else {
650 640 pp->hw = hw_bind->hw;
651 641 ecpp_error(pp->dip, "SuperIO type: %s\n", hw_bind->info);
652 642 }
653 643
654 644 /*
655 645 * Map registers
656 646 */
657 647 if (ECPP_MAP_REGS(pp) != SUCCESS) {
658 648 goto fail_map;
659 649 }
660 650
661 651 if (ddi_dma_alloc_handle(dip, pp->hw->attr, DDI_DMA_DONTWAIT,
662 652 NULL, &pp->dma_handle) != DDI_SUCCESS) {
663 653 ecpp_error(dip, "ecpp_attach: failed ddi_dma_alloc_handle\n");
664 654 goto fail_dma;
665 655 }
666 656
667 657 if (ddi_get_iblock_cookie(dip, 0,
668 658 &pp->ecpp_trap_cookie) != DDI_SUCCESS) {
669 659 ecpp_error(dip, "ecpp_attach: failed ddi_get_iblock_cookie\n");
670 660 goto fail_ibc;
671 661 }
672 662
673 663 mutex_init(&pp->umutex, NULL, MUTEX_DRIVER,
674 664 (void *)pp->ecpp_trap_cookie);
675 665
676 666 cv_init(&pp->pport_cv, NULL, CV_DRIVER, NULL);
677 667
678 668 if (ddi_add_intr(dip, 0, &pp->ecpp_trap_cookie, NULL, ecpp_isr,
679 669 (caddr_t)pp) != DDI_SUCCESS) {
680 670 ecpp_error(dip, "ecpp_attach: failed to add hard intr\n");
681 671 goto fail_intr;
682 672 }
683 673
684 674 if (ddi_add_softintr(dip, DDI_SOFTINT_LOW,
685 675 &pp->softintr_id, 0, 0, ecpp_softintr,
686 676 (caddr_t)pp) != DDI_SUCCESS) {
687 677 ecpp_error(dip, "ecpp_attach: failed to add soft intr\n");
688 678 goto fail_softintr;
689 679 }
690 680
691 681 (void) sprintf(name, "ecpp%d", instance);
692 682
693 683 if (ddi_create_minor_node(dip, name, S_IFCHR, instance,
694 684 DDI_NT_PRINTER, NULL) == DDI_FAILURE) {
695 685 ecpp_error(dip, "ecpp_attach: create_minor_node failed\n");
696 686 goto fail_minor;
697 687 }
698 688
699 689 pp->ioblock = (caddr_t)kmem_alloc(IO_BLOCK_SZ, KM_SLEEP);
700 690 if (pp->ioblock == NULL) {
701 691 ecpp_error(dip, "ecpp_attach: kmem_alloc failed\n");
702 692 goto fail_iob;
703 693 } else {
704 694 ecpp_error(pp->dip, "ecpp_attach: ioblock=0x%x\n", pp->ioblock);
705 695 }
706 696
707 697 ecpp_get_props(pp);
708 698 #if defined(__x86)
709 699 if (pp->hw == &x86 && pp->uh.x86.chn != 0xff) {
710 700 if (ddi_dmae_alloc(dip, pp->uh.x86.chn,
711 701 DDI_DMA_DONTWAIT, NULL) == DDI_SUCCESS)
712 702 ecpp_error(pp->dip, "dmae_alloc success!\n");
713 703 }
714 704 #endif
715 705 if (ECPP_CONFIG_CHIP(pp) == FAILURE) {
716 706 ecpp_error(pp->dip, "config_chip failed.\n");
717 707 goto fail_config;
718 708 }
719 709
720 710 ecpp_kstat_init(pp);
721 711
722 712 ddi_report_dev(dip);
723 713
724 714 return (DDI_SUCCESS);
725 715
726 716 fail_config:
727 717 ddi_prop_remove_all(dip);
728 718 kmem_free(pp->ioblock, IO_BLOCK_SZ);
729 719 fail_iob:
730 720 ddi_remove_minor_node(dip, NULL);
731 721 fail_minor:
732 722 ddi_remove_softintr(pp->softintr_id);
733 723 fail_softintr:
734 724 ddi_remove_intr(dip, (uint_t)0, pp->ecpp_trap_cookie);
735 725 fail_intr:
736 726 mutex_destroy(&pp->umutex);
737 727 cv_destroy(&pp->pport_cv);
738 728 fail_ibc:
739 729 ddi_dma_free_handle(&pp->dma_handle);
740 730 fail_dma:
741 731 ECPP_UNMAP_REGS(pp);
742 732 fail_map:
743 733 fail_sio:
744 734 ddi_soft_state_free(ecppsoft_statep, instance);
745 735 fail:
746 736 ecpp_error(dip, "ecpp_attach: failed.\n");
747 737
748 738 return (DDI_FAILURE);
749 739 }
750 740
751 741 static int
752 742 ecpp_detach(dev_info_t *dip, ddi_detach_cmd_t cmd)
753 743 {
754 744 int instance;
755 745 struct ecppunit *pp;
756 746
757 747 instance = ddi_get_instance(dip);
758 748
759 749 switch (cmd) {
760 750 case DDI_DETACH:
761 751 break;
762 752
763 753 case DDI_SUSPEND:
764 754 if (!(pp = ddi_get_soft_state(ecppsoft_statep, instance))) {
765 755 return (DDI_FAILURE);
766 756 }
767 757
768 758 mutex_enter(&pp->umutex);
769 759 ASSERT(pp->suspended == FALSE);
770 760
771 761 pp->suspended = TRUE; /* prevent new transfers */
772 762
773 763 /*
774 764 * Wait if there's any activity on the port
775 765 */
776 766 if ((pp->e_busy == ECPP_BUSY) || (pp->e_busy == ECPP_FLUSH)) {
777 767 (void) cv_reltimedwait(&pp->pport_cv, &pp->umutex,
778 768 SUSPEND_TOUT * drv_usectohz(1000000),
779 769 TR_CLOCK_TICK);
780 770 if ((pp->e_busy == ECPP_BUSY) ||
781 771 (pp->e_busy == ECPP_FLUSH)) {
782 772 pp->suspended = FALSE;
783 773 mutex_exit(&pp->umutex);
784 774 ecpp_error(pp->dip,
785 775 "ecpp_detach: suspend timeout\n");
786 776 return (DDI_FAILURE);
787 777 }
788 778 }
789 779
790 780 mutex_exit(&pp->umutex);
791 781 return (DDI_SUCCESS);
792 782
793 783 default:
794 784 return (DDI_FAILURE);
795 785 }
796 786
797 787 pp = ddi_get_soft_state(ecppsoft_statep, instance);
798 788 #if defined(__x86)
799 789 if (pp->hw == &x86 && pp->uh.x86.chn != 0xff)
800 790 (void) ddi_dmae_release(pp->dip, pp->uh.x86.chn);
801 791 #endif
802 792 if (pp->dma_handle != NULL)
803 793 ddi_dma_free_handle(&pp->dma_handle);
804 794
805 795 ddi_remove_minor_node(dip, NULL);
806 796
807 797 ddi_remove_softintr(pp->softintr_id);
808 798
809 799 ddi_remove_intr(dip, (uint_t)0, pp->ecpp_trap_cookie);
810 800
811 801 if (pp->ksp) {
812 802 kstat_delete(pp->ksp);
813 803 }
814 804 if (pp->intrstats) {
815 805 kstat_delete(pp->intrstats);
816 806 }
817 807
818 808 cv_destroy(&pp->pport_cv);
819 809
820 810 mutex_destroy(&pp->umutex);
821 811
822 812 ECPP_UNMAP_REGS(pp);
823 813
824 814 kmem_free(pp->ioblock, IO_BLOCK_SZ);
825 815
826 816 ddi_prop_remove_all(dip);
827 817
828 818 ddi_soft_state_free(ecppsoft_statep, instance);
829 819
830 820 return (DDI_SUCCESS);
831 821
832 822 }
833 823
834 824 /*
835 825 * ecpp_get_props() reads ecpp.conf for user defineable tuneables.
836 826 * If the file or a particular variable is not there, a default value
837 827 * is assigned.
838 828 */
839 829
840 830 static void
841 831 ecpp_get_props(struct ecppunit *pp)
842 832 {
843 833 char *prop;
844 834 #if defined(__x86)
845 835 int len;
846 836 int value;
847 837 #endif
848 838 /*
849 839 * If fast_centronics is TRUE, non-compliant IEEE 1284
850 840 * peripherals ( Centronics peripherals) will operate in DMA mode.
851 841 * Transfers betwee main memory and the device will be via DMA;
852 842 * peripheral handshaking will be conducted by superio logic.
853 843 * If ecpp can not read the variable correctly fast_centronics will
854 844 * be set to FALSE. In this case, transfers and handshaking
855 845 * will be conducted by PIO for Centronics devices.
856 846 */
857 847 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, pp->dip, 0,
858 848 "fast-centronics", &prop) == DDI_PROP_SUCCESS) {
859 849 pp->fast_centronics =
860 850 (strcmp(prop, "true") == 0) ? TRUE : FALSE;
861 851 ddi_prop_free(prop);
862 852 } else {
863 853 pp->fast_centronics = FALSE;
864 854 }
865 855
866 856 /*
867 857 * If fast-1284-compatible is set to TRUE, when ecpp communicates
868 858 * with IEEE 1284 compliant peripherals, data transfers between
869 859 * main memory and the parallel port will be conducted by DMA.
870 860 * Handshaking between the port and peripheral will be conducted
871 861 * by superio logic. This is the default characteristic. If
872 862 * fast-1284-compatible is set to FALSE, transfers and handshaking
873 863 * will be conducted by PIO.
874 864 */
875 865
876 866 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, pp->dip, 0,
877 867 "fast-1284-compatible", &prop) == DDI_PROP_SUCCESS) {
878 868 pp->fast_compat = (strcmp(prop, "true") == 0) ? TRUE : FALSE;
879 869 ddi_prop_free(prop);
880 870 } else {
881 871 pp->fast_compat = TRUE;
882 872 }
883 873
884 874 /*
885 875 * Some centronics peripherals require the nInit signal to be
886 876 * toggled to reset the device. If centronics_init_seq is set
887 877 * to TRUE, ecpp will toggle the nInit signal upon every ecpp_open().
888 878 * Applications have the opportunity to toggle the nInit signal
889 879 * with ioctl(2) calls as well. The default is to set it to FALSE.
890 880 */
891 881 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, pp->dip, 0,
892 882 "centronics-init-seq", &prop) == DDI_PROP_SUCCESS) {
893 883 pp->init_seq = (strcmp(prop, "true") == 0) ? TRUE : FALSE;
894 884 ddi_prop_free(prop);
895 885 } else {
896 886 pp->init_seq = FALSE;
897 887 }
898 888
899 889 /*
900 890 * If one of the centronics status signals are in an erroneous
901 891 * state, ecpp_wsrv() will be reinvoked centronics-retry ms to
902 892 * check if the status is ok to transfer. If the property is not
903 893 * found, wsrv_retry will be set to CENTRONICS_RETRY ms.
904 894 */
905 895 pp->wsrv_retry = ddi_prop_get_int(DDI_DEV_T_ANY, pp->dip, 0,
906 896 "centronics-retry", CENTRONICS_RETRY);
907 897
908 898 /*
909 899 * In PIO mode, ecpp_isr() will loop for wait for the busy signal
910 900 * to be deasserted before transferring the next byte. wait_for_busy
911 901 * is specificied in microseconds. If the property is not found
912 902 * ecpp_isr() will wait for a maximum of WAIT_FOR_BUSY us.
913 903 */
914 904 pp->wait_for_busy = ddi_prop_get_int(DDI_DEV_T_ANY, pp->dip, 0,
915 905 "centronics-wait-for-busy", WAIT_FOR_BUSY);
916 906
917 907 /*
918 908 * In PIO mode, centronics transfers must hold the data signals
919 909 * for a data_setup_time milliseconds before the strobe is asserted.
920 910 */
921 911 pp->data_setup_time = ddi_prop_get_int(DDI_DEV_T_ANY, pp->dip, 0,
922 912 "centronics-data-setup-time", DATA_SETUP_TIME);
923 913
924 914 /*
925 915 * In PIO mode, centronics transfers asserts the strobe signal
926 916 * for a period of strobe_pulse_width milliseconds.
927 917 */
928 918 pp->strobe_pulse_width = ddi_prop_get_int(DDI_DEV_T_ANY, pp->dip, 0,
929 919 "centronics-strobe-pulse-width", STROBE_PULSE_WIDTH);
930 920
931 921 /*
932 922 * Upon a transfer the peripheral, ecpp waits write_timeout seconds
933 923 * for the transmission to complete.
934 924 */
935 925 default_xfer_parms.write_timeout = ddi_prop_get_int(DDI_DEV_T_ANY,
936 926 pp->dip, 0, "ecpp-transfer-timeout", ecpp_def_timeout);
937 927
938 928 pp->xfer_parms = default_xfer_parms;
939 929
940 930 /*
941 931 * Get dma channel for M1553
942 932 */
943 933 if (pp->hw == &m1553) {
944 934 pp->uh.m1553.chn = ddi_prop_get_int(DDI_DEV_T_ANY,
945 935 pp->dip, 0, "dma-channel", 0x1);
946 936 ecpp_error(pp->dip, "ecpp_get_prop:chn=%x\n", pp->uh.m1553.chn);
947 937 }
948 938 #if defined(__x86)
949 939 len = sizeof (value);
950 940 /* Get dma channel for i86 pc */
951 941 if (pp->hw == &x86) {
952 942 if (ddi_prop_op(DDI_DEV_T_ANY, pp->dip, PROP_LEN_AND_VAL_BUF,
953 943 DDI_PROP_DONTPASS, "dma-channels", (caddr_t)&value, &len)
954 944 != DDI_PROP_SUCCESS) {
955 945 ecpp_error(pp->dip, "No dma channel found\n");
956 946 pp->uh.x86.chn = 0xff;
957 947 pp->fast_compat = FALSE;
958 948 pp->noecpregs = TRUE;
959 949 } else
960 950 pp->uh.x86.chn = (uint8_t)value;
961 951 }
962 952 #endif
963 953 /*
964 954 * these properties are not yet public
965 955 */
966 956 pp->ecp_rev_speed = ddi_prop_get_int(DDI_DEV_T_ANY, pp->dip, 0,
967 957 "ecp-rev-speed", ECP_REV_SPEED);
968 958
969 959 pp->rev_watchdog = ddi_prop_get_int(DDI_DEV_T_ANY, pp->dip, 0,
970 960 "rev-watchdog", REV_WATCHDOG);
971 961
972 962 ecpp_error(pp->dip,
973 963 "ecpp_get_prop: fast_centronics=%x, fast-1284=%x\n"
974 964 "ecpp_get_prop: wsrv_retry=%d, wait_for_busy=%d\n"
975 965 "ecpp_get_prop: data_setup=%d, strobe_pulse=%d\n"
976 966 "ecpp_get_prop: transfer-timeout=%d\n",
977 967 pp->fast_centronics, pp->fast_compat,
978 968 pp->wsrv_retry, pp->wait_for_busy,
979 969 pp->data_setup_time, pp->strobe_pulse_width,
980 970 pp->xfer_parms.write_timeout);
981 971 }
982 972
983 973 /*ARGSUSED*/
984 974 int
985 975 ecpp_getinfo(dev_info_t *dip, ddi_info_cmd_t infocmd, void *arg, void **result)
986 976 {
987 977 dev_t dev = (dev_t)arg;
988 978 struct ecppunit *pp;
989 979 int instance, ret;
990 980
991 981 instance = getminor(dev);
992 982
993 983 switch (infocmd) {
994 984 case DDI_INFO_DEVT2DEVINFO:
995 985 pp = ddi_get_soft_state(ecppsoft_statep, instance);
996 986 if (pp != NULL) {
997 987 *result = pp->dip;
998 988 ret = DDI_SUCCESS;
999 989 } else {
1000 990 ret = DDI_FAILURE;
1001 991 }
1002 992 break;
1003 993
1004 994 case DDI_INFO_DEVT2INSTANCE:
1005 995 *result = (void *)(uintptr_t)instance;
1006 996 ret = DDI_SUCCESS;
1007 997 break;
1008 998
1009 999 default:
1010 1000 ret = DDI_FAILURE;
1011 1001 break;
1012 1002 }
1013 1003
1014 1004 return (ret);
1015 1005 }
1016 1006
1017 1007 /*ARGSUSED2*/
1018 1008 static int
1019 1009 ecpp_open(queue_t *q, dev_t *dev, int flag, int sflag, cred_t *credp)
1020 1010 {
1021 1011 struct ecppunit *pp;
1022 1012 int instance;
1023 1013 struct stroptions *sop;
1024 1014 mblk_t *mop;
1025 1015
1026 1016 instance = getminor(*dev);
1027 1017
1028 1018 if (instance < 0) {
1029 1019 return (ENXIO);
1030 1020 }
1031 1021
1032 1022 pp = (struct ecppunit *)ddi_get_soft_state(ecppsoft_statep, instance);
1033 1023
1034 1024 if (pp == NULL) {
1035 1025 return (ENXIO);
1036 1026 }
1037 1027
1038 1028 mutex_enter(&pp->umutex);
1039 1029
1040 1030 /*
1041 1031 * Parallel port is an exclusive-use device
1042 1032 * thus providing print job integrity
1043 1033 */
1044 1034 if (pp->oflag == TRUE) {
1045 1035 ecpp_error(pp->dip, "ecpp open failed");
1046 1036 mutex_exit(&pp->umutex);
1047 1037 return (EBUSY);
1048 1038 }
1049 1039
1050 1040 pp->oflag = TRUE;
1051 1041
1052 1042 /* initialize state variables */
1053 1043 pp->prn_timeouts = prn_timeouts_default;
1054 1044 pp->xfer_parms = default_xfer_parms;
1055 1045 pp->current_mode = ECPP_CENTRONICS;
1056 1046 pp->backchannel = ECPP_CENTRONICS;
1057 1047 pp->current_phase = ECPP_PHASE_PO;
1058 1048 pp->port = ECPP_PORT_DMA;
1059 1049 pp->instance = instance;
1060 1050 pp->timeout_error = 0;
1061 1051 pp->saved_dsr = DSR_READ(pp);
1062 1052 pp->ecpp_drain_counter = 0;
1063 1053 pp->dma_cancelled = FALSE;
1064 1054 pp->io_mode = ECPP_DMA;
1065 1055 pp->joblen = 0;
1066 1056 pp->tfifo_intr = 0;
1067 1057 pp->softintr_pending = 0;
1068 1058 pp->nread = 0;
1069 1059
1070 1060 /* clear the state flag */
1071 1061 pp->e_busy = ECPP_IDLE;
1072 1062
1073 1063 pp->readq = RD(q);
1074 1064 pp->writeq = WR(q);
1075 1065 pp->msg = NULL;
1076 1066
1077 1067 RD(q)->q_ptr = WR(q)->q_ptr = (caddr_t)pp;
1078 1068
1079 1069 /*
1080 1070 * Get ready: check host/peripheral, negotiate into default mode
1081 1071 */
1082 1072 if (ecpp_reset_port_regs(pp) == FAILURE) {
1083 1073 mutex_exit(&pp->umutex);
1084 1074 return (EIO);
1085 1075 }
1086 1076
1087 1077 mutex_exit(&pp->umutex);
1088 1078
1089 1079 /*
1090 1080 * Configure the Stream head and enable the Stream
1091 1081 */
1092 1082 if (!(mop = allocb(sizeof (struct stroptions), BPRI_MED))) {
1093 1083 return (EAGAIN);
1094 1084 }
1095 1085
1096 1086 mop->b_datap->db_type = M_SETOPTS;
1097 1087 mop->b_wptr += sizeof (struct stroptions);
1098 1088
1099 1089 /*
1100 1090 * if device is open with O_NONBLOCK flag set, let read(2) return 0
1101 1091 * if no data waiting to be read. Writes will block on flow control.
1102 1092 */
1103 1093 sop = (struct stroptions *)mop->b_rptr;
1104 1094 sop->so_flags = SO_HIWAT | SO_LOWAT | SO_NDELON | SO_MREADON;
1105 1095 sop->so_hiwat = ECPPHIWAT;
1106 1096 sop->so_lowat = ECPPLOWAT;
1107 1097
1108 1098 /* enable the stream */
1109 1099 qprocson(q);
1110 1100
1111 1101 putnext(q, mop);
1112 1102
1113 1103 mutex_enter(&pp->umutex);
1114 1104
1115 1105 ecpp_default_negotiation(pp);
1116 1106
1117 1107 /* go revidle */
1118 1108 (void) ecpp_idle_phase(pp);
1119 1109
1120 1110 ecpp_error(pp->dip,
1121 1111 "ecpp_open: mode=%x, phase=%x ecr=%x, dsr=%x, dcr=%x\n",
1122 1112 pp->current_mode, pp->current_phase,
1123 1113 ECR_READ(pp), DSR_READ(pp), DCR_READ(pp));
1124 1114
1125 1115 mutex_exit(&pp->umutex);
1126 1116
1127 1117 return (0);
1128 1118 }
1129 1119
1130 1120 /*ARGSUSED1*/
1131 1121 static int
1132 1122 ecpp_close(queue_t *q, int flag, cred_t *cred_p)
1133 1123 {
1134 1124 struct ecppunit *pp;
1135 1125 timeout_id_t timeout_id, fifo_timer_id, wsrv_timer_id;
1136 1126
1137 1127 pp = (struct ecppunit *)q->q_ptr;
1138 1128
1139 1129 ecpp_error(pp->dip, "ecpp_close: entering ...\n");
1140 1130
1141 1131 mutex_enter(&pp->umutex);
1142 1132
1143 1133 /*
1144 1134 * ecpp_close() will continue to loop until the
1145 1135 * queue has been drained or if the thread
1146 1136 * has received a SIG. Typically, when the queue
1147 1137 * has data, the port will be ECPP_BUSY. However,
1148 1138 * after a dma completes and before the wsrv
1149 1139 * starts the next transfer, the port may be IDLE.
1150 1140 * In this case, ecpp_close() will loop within this
1151 1141 * while(qsize) segment. Since, ecpp_wsrv() runs
1152 1142 * at software interupt level, this shouldn't loop
1153 1143 * very long.
1154 1144 */
1155 1145 while (pp->e_busy != ECPP_IDLE || qsize(WR(q))) {
1156 1146 if (!cv_wait_sig(&pp->pport_cv, &pp->umutex)) {
1157 1147 ecpp_error(pp->dip, "ecpp_close:B: received SIG\n");
1158 1148 /*
1159 1149 * Returning from a signal such as
1160 1150 * SIGTERM or SIGKILL
1161 1151 */
1162 1152 ecpp_flush(pp, FWRITE);
1163 1153 break;
1164 1154 } else {
1165 1155 ecpp_error(pp->dip, "ecpp_close:rcvd cv-sig\n");
1166 1156 }
1167 1157 }
1168 1158
1169 1159 ecpp_error(pp->dip, "ecpp_close: joblen=%d, ctx_cf=%d, "
1170 1160 "qsize(WR(q))=%d, qsize(RD(q))=%d\n",
1171 1161 pp->joblen, pp->ctx_cf, qsize(pp->writeq), qsize(q));
1172 1162
1173 1163 /*
1174 1164 * Cancel all timeouts, disable interrupts
1175 1165 *
1176 1166 * Note that we can`t call untimeout(9F) with mutex held:
1177 1167 * callout may be blocked on the same mutex, and untimeout() will
1178 1168 * cv_wait() while callout is executing, thus creating a deadlock
1179 1169 * So we zero the timeout id's inside mutex and call untimeout later
1180 1170 */
1181 1171 timeout_id = pp->timeout_id;
1182 1172 fifo_timer_id = pp->fifo_timer_id;
1183 1173 wsrv_timer_id = pp->wsrv_timer_id;
1184 1174
1185 1175 pp->timeout_id = pp->fifo_timer_id = pp->wsrv_timer_id = 0;
1186 1176
1187 1177 pp->softintr_pending = 0;
1188 1178 pp->dma_cancelled = TRUE;
1189 1179 ECPP_MASK_INTR(pp);
1190 1180
1191 1181 mutex_exit(&pp->umutex);
1192 1182
1193 1183 qprocsoff(q);
1194 1184
1195 1185 if (timeout_id) {
1196 1186 (void) untimeout(timeout_id);
1197 1187 }
1198 1188 if (fifo_timer_id) {
1199 1189 (void) untimeout(fifo_timer_id);
1200 1190 }
1201 1191 if (wsrv_timer_id) {
1202 1192 (void) untimeout(wsrv_timer_id);
1203 1193 }
1204 1194
1205 1195 mutex_enter(&pp->umutex);
1206 1196
1207 1197 /* set link to Compatible mode */
1208 1198 if ((pp->current_mode == ECPP_ECP_MODE) &&
1209 1199 (pp->current_phase != ECPP_PHASE_ECP_FWD_IDLE)) {
1210 1200 (void) ecp_reverse2forward(pp);
1211 1201 }
1212 1202
1213 1203 (void) ecpp_1284_termination(pp);
1214 1204
1215 1205 pp->oflag = FALSE;
1216 1206 q->q_ptr = WR(q)->q_ptr = NULL;
1217 1207 pp->readq = pp->writeq = NULL;
1218 1208 pp->msg = NULL;
1219 1209
1220 1210 ecpp_error(pp->dip, "ecpp_close: ecr=%x, dsr=%x, dcr=%x\n",
1221 1211 ECR_READ(pp), DSR_READ(pp), DCR_READ(pp));
1222 1212
1223 1213 mutex_exit(&pp->umutex);
1224 1214
1225 1215 return (0);
1226 1216 }
1227 1217
1228 1218 /*
1229 1219 * standard put procedure for ecpp
1230 1220 */
1231 1221 static int
1232 1222 ecpp_wput(queue_t *q, mblk_t *mp)
1233 1223 {
1234 1224 struct msgb *nmp;
1235 1225 struct ecppunit *pp;
1236 1226
1237 1227 pp = (struct ecppunit *)q->q_ptr;
1238 1228
1239 1229 if (!mp) {
1240 1230 return (0);
1241 1231 }
1242 1232
1243 1233 if ((mp->b_wptr - mp->b_rptr) <= 0) {
1244 1234 ecpp_error(pp->dip,
1245 1235 "ecpp_wput:bogus packet recieved mp=%x\n", mp);
1246 1236 freemsg(mp);
1247 1237 return (0);
1248 1238 }
1249 1239
1250 1240 switch (DB_TYPE(mp)) {
1251 1241 case M_DATA:
1252 1242 /*
1253 1243 * This is a quick fix for multiple message block problem,
1254 1244 * it will be changed later with better performance code.
1255 1245 */
1256 1246 if (mp->b_cont) {
1257 1247 /*
1258 1248 * mblk has scattered data ... do msgpullup
1259 1249 * if it fails, continue with the current mblk
1260 1250 */
1261 1251 if ((nmp = msgpullup(mp, -1)) != NULL) {
1262 1252 freemsg(mp);
1263 1253 mp = nmp;
1264 1254 ecpp_error(pp->dip,
1265 1255 "ecpp_wput:msgpullup: mp=%p len=%d\n",
1266 1256 mp, mp->b_wptr - mp->b_rptr);
1267 1257 }
1268 1258 }
1269 1259
1270 1260 /* let ecpp_wsrv() concatenate small blocks */
1271 1261 (void) putq(q, mp);
1272 1262
1273 1263 break;
1274 1264
1275 1265 case M_CTL:
1276 1266 (void) putq(q, mp);
1277 1267
1278 1268 break;
1279 1269
1280 1270 case M_IOCTL: {
1281 1271 struct iocblk *iocbp;
1282 1272
1283 1273 iocbp = (struct iocblk *)mp->b_rptr;
1284 1274
1285 1275 ecpp_error(pp->dip, "ecpp_wput:M_IOCTL %x\n", iocbp->ioc_cmd);
1286 1276
1287 1277 mutex_enter(&pp->umutex);
1288 1278
1289 1279 /* TESTIO and GET_STATUS can be used during transfer */
1290 1280 if ((pp->e_busy == ECPP_BUSY) &&
1291 1281 (iocbp->ioc_cmd != BPPIOC_TESTIO) &&
1292 1282 (iocbp->ioc_cmd != PRNIOC_GET_STATUS)) {
1293 1283 mutex_exit(&pp->umutex);
1294 1284 (void) putq(q, mp);
1295 1285 } else {
1296 1286 mutex_exit(&pp->umutex);
1297 1287 ecpp_putioc(q, mp);
1298 1288 }
1299 1289
1300 1290 break;
1301 1291 }
1302 1292
1303 1293 case M_IOCDATA: {
1304 1294 struct copyresp *csp;
1305 1295
1306 1296 ecpp_error(pp->dip, "ecpp_wput:M_IOCDATA\n");
1307 1297
1308 1298 csp = (struct copyresp *)mp->b_rptr;
1309 1299
1310 1300 /*
1311 1301 * If copy request failed, quit now
1312 1302 */
1313 1303 if (csp->cp_rval != 0) {
1314 1304 freemsg(mp);
1315 1305 return (0);
1316 1306 }
1317 1307
1318 1308 switch (csp->cp_cmd) {
1319 1309 case ECPPIOC_SETPARMS:
1320 1310 case ECPPIOC_SETREGS:
1321 1311 case ECPPIOC_SETPORT:
1322 1312 case ECPPIOC_SETDATA:
1323 1313 case PRNIOC_SET_IFCAP:
1324 1314 case PRNIOC_SET_TIMEOUTS:
1325 1315 /*
1326 1316 * need to retrieve and use the data, but if the
1327 1317 * device is busy, wait.
1328 1318 */
1329 1319 (void) putq(q, mp);
1330 1320 break;
1331 1321
1332 1322 case ECPPIOC_GETPARMS:
1333 1323 case ECPPIOC_GETREGS:
1334 1324 case ECPPIOC_GETPORT:
1335 1325 case ECPPIOC_GETDATA:
1336 1326 case BPPIOC_GETERR:
1337 1327 case BPPIOC_TESTIO:
1338 1328 case PRNIOC_GET_IFCAP:
1339 1329 case PRNIOC_GET_STATUS:
1340 1330 case PRNIOC_GET_1284_STATUS:
1341 1331 case PRNIOC_GET_TIMEOUTS:
1342 1332 /* data transfered to user space okay */
1343 1333 ecpp_ack_ioctl(q, mp);
1344 1334 break;
1345 1335
1346 1336 case ECPPIOC_GETDEVID:
1347 1337 ecpp_wput_iocdata_devid(q, mp,
1348 1338 offsetof(struct ecpp_device_id, rlen));
1349 1339 break;
1350 1340
1351 1341 case PRNIOC_GET_1284_DEVID:
1352 1342 ecpp_wput_iocdata_devid(q, mp,
1353 1343 offsetof(struct prn_1284_device_id, id_rlen));
1354 1344 break;
1355 1345
1356 1346 case PRNIOC_GET_IFINFO:
1357 1347 ecpp_wput_iocdata_devid(q, mp,
1358 1348 offsetof(struct prn_interface_info, if_rlen));
1359 1349 break;
1360 1350
1361 1351 default:
1362 1352 ecpp_nack_ioctl(q, mp, EINVAL);
1363 1353 break;
1364 1354 }
1365 1355
1366 1356 break;
1367 1357 }
1368 1358
1369 1359 case M_FLUSH:
1370 1360 ecpp_error(pp->dip, "ecpp_wput:M_FLUSH\n");
1371 1361
1372 1362 if (*mp->b_rptr & FLUSHW) {
1373 1363 mutex_enter(&pp->umutex);
1374 1364 ecpp_flush(pp, FWRITE);
1375 1365 mutex_exit(&pp->umutex);
1376 1366 }
1377 1367
1378 1368 if (*mp->b_rptr & FLUSHR) {
1379 1369 mutex_enter(&pp->umutex);
1380 1370 ecpp_flush(pp, FREAD);
1381 1371 mutex_exit(&pp->umutex);
1382 1372 qreply(q, mp);
1383 1373 } else {
1384 1374 freemsg(mp);
1385 1375 }
1386 1376
1387 1377 break;
1388 1378
1389 1379 case M_READ:
1390 1380 /*
1391 1381 * When the user calls read(2), M_READ message is sent to us,
1392 1382 * first byte of which is the number of requested bytes
1393 1383 * We add up user requests and use resulting number
1394 1384 * to calculate the reverse transfer block size
1395 1385 */
1396 1386 mutex_enter(&pp->umutex);
1397 1387 if (pp->e_busy == ECPP_IDLE) {
1398 1388 pp->nread += *(size_t *)mp->b_rptr;
1399 1389 ecpp_error(pp->dip, "ecpp_wput: M_READ %d", pp->nread);
1400 1390 freemsg(mp);
1401 1391 } else {
1402 1392 ecpp_error(pp->dip, "ecpp_wput: M_READ queueing");
1403 1393 (void) putq(q, mp);
1404 1394 }
1405 1395 mutex_exit(&pp->umutex);
1406 1396 break;
1407 1397
1408 1398 default:
1409 1399 ecpp_error(pp->dip, "ecpp_wput: bad messagetype 0x%x\n",
1410 1400 DB_TYPE(mp));
1411 1401 freemsg(mp);
1412 1402 break;
1413 1403 }
1414 1404
1415 1405 return (0);
1416 1406 }
1417 1407
1418 1408 /*
1419 1409 * Process ECPPIOC_GETDEVID-like ioctls
1420 1410 */
1421 1411 static void
1422 1412 ecpp_wput_iocdata_devid(queue_t *q, mblk_t *mp, uintptr_t rlen_offset)
1423 1413 {
1424 1414 struct copyresp *csp;
1425 1415 struct ecpp_copystate *stp;
1426 1416 mblk_t *datamp;
1427 1417
1428 1418 csp = (struct copyresp *)mp->b_rptr;
1429 1419 stp = (struct ecpp_copystate *)csp->cp_private->b_rptr;
1430 1420
1431 1421 /* determine the state of copyin/copyout process */
1432 1422 switch (stp->state) {
1433 1423 case ECPP_STRUCTIN:
1434 1424 /* user structure has arrived */
1435 1425 (void) putq(q, mp);
1436 1426 break;
1437 1427
1438 1428 case ECPP_ADDROUT:
1439 1429 /*
1440 1430 * data transfered to user space okay
1441 1431 * now update user structure
1442 1432 */
1443 1433 datamp = allocb(sizeof (int), BPRI_MED);
1444 1434 if (datamp == NULL) {
1445 1435 ecpp_nack_ioctl(q, mp, ENOSR);
1446 1436 break;
1447 1437 }
1448 1438
1449 1439 *(int *)datamp->b_rptr =
1450 1440 *(int *)((char *)&stp->un + rlen_offset);
1451 1441 stp->state = ECPP_STRUCTOUT;
1452 1442
1453 1443 mcopyout(mp, csp->cp_private, sizeof (int),
1454 1444 (char *)stp->uaddr + rlen_offset, datamp);
1455 1445 qreply(q, mp);
1456 1446 break;
1457 1447
1458 1448 case ECPP_STRUCTOUT:
1459 1449 /* user structure was updated okay */
1460 1450 freemsg(csp->cp_private);
1461 1451 ecpp_ack_ioctl(q, mp);
1462 1452 break;
1463 1453
1464 1454 default:
1465 1455 ecpp_nack_ioctl(q, mp, EINVAL);
1466 1456 break;
1467 1457 }
1468 1458 }
1469 1459
1470 1460 static uchar_t
1471 1461 ecpp_get_error_status(uchar_t status)
1472 1462 {
1473 1463 uchar_t pin_status = 0;
1474 1464
1475 1465 if (!(status & ECPP_nERR)) {
1476 1466 pin_status |= BPP_ERR_ERR;
1477 1467 }
1478 1468
1479 1469 if (status & ECPP_PE) {
1480 1470 pin_status |= BPP_PE_ERR;
1481 1471 }
1482 1472
1483 1473 if (!(status & ECPP_SLCT)) {
1484 1474 pin_status |= BPP_SLCT_ERR;
1485 1475 }
1486 1476
1487 1477 if (!(status & ECPP_nBUSY)) {
1488 1478 pin_status |= BPP_SLCT_ERR;
1489 1479 }
1490 1480
1491 1481 return (pin_status);
1492 1482 }
1493 1483
1494 1484 /*
1495 1485 * ioctl handler for output PUT procedure.
1496 1486 */
1497 1487 static void
1498 1488 ecpp_putioc(queue_t *q, mblk_t *mp)
1499 1489 {
1500 1490 struct iocblk *iocbp;
1501 1491 struct ecppunit *pp;
1502 1492
1503 1493 pp = (struct ecppunit *)q->q_ptr;
1504 1494
1505 1495 iocbp = (struct iocblk *)mp->b_rptr;
1506 1496
1507 1497 /* I_STR ioctls are invalid */
1508 1498 if (iocbp->ioc_count != TRANSPARENT) {
1509 1499 ecpp_nack_ioctl(q, mp, EINVAL);
1510 1500 return;
1511 1501 }
1512 1502
1513 1503 switch (iocbp->ioc_cmd) {
1514 1504 case ECPPIOC_SETPARMS: {
1515 1505 mcopyin(mp, NULL, sizeof (struct ecpp_transfer_parms), NULL);
1516 1506 qreply(q, mp);
1517 1507 break;
1518 1508 }
1519 1509
1520 1510 case ECPPIOC_GETPARMS: {
1521 1511 struct ecpp_transfer_parms xfer_parms;
1522 1512
1523 1513 mutex_enter(&pp->umutex);
1524 1514
1525 1515 pp->xfer_parms.mode = pp->current_mode;
1526 1516 xfer_parms = pp->xfer_parms;
1527 1517
1528 1518 mutex_exit(&pp->umutex);
1529 1519
1530 1520 ecpp_putioc_copyout(q, mp, &xfer_parms, sizeof (xfer_parms));
1531 1521 break;
1532 1522 }
1533 1523
1534 1524 case ECPPIOC_SETREGS: {
1535 1525 mutex_enter(&pp->umutex);
1536 1526 if (pp->current_mode != ECPP_DIAG_MODE) {
1537 1527 mutex_exit(&pp->umutex);
1538 1528 ecpp_nack_ioctl(q, mp, EINVAL);
1539 1529 break;
1540 1530 }
1541 1531 mutex_exit(&pp->umutex);
1542 1532
1543 1533 mcopyin(mp, NULL, sizeof (struct ecpp_regs), NULL);
1544 1534 qreply(q, mp);
1545 1535 break;
1546 1536 }
1547 1537
1548 1538 case ECPPIOC_GETREGS: {
1549 1539 struct ecpp_regs rg;
1550 1540
1551 1541 mutex_enter(&pp->umutex);
1552 1542
1553 1543 if (pp->current_mode != ECPP_DIAG_MODE) {
1554 1544 mutex_exit(&pp->umutex);
1555 1545 ecpp_nack_ioctl(q, mp, EINVAL);
1556 1546 break;
1557 1547 }
1558 1548
1559 1549 rg.dsr = DSR_READ(pp);
1560 1550 rg.dcr = DCR_READ(pp);
1561 1551
1562 1552 mutex_exit(&pp->umutex);
1563 1553
1564 1554 ecpp_error(pp->dip, "ECPPIOC_GETREGS: dsr=%x,dcr=%x\n",
1565 1555 rg.dsr, rg.dcr);
1566 1556
1567 1557 /* these bits must be 1 */
1568 1558 rg.dsr |= ECPP_SETREGS_DSR_MASK;
1569 1559 rg.dcr |= ECPP_SETREGS_DCR_MASK;
1570 1560
1571 1561 ecpp_putioc_copyout(q, mp, &rg, sizeof (rg));
1572 1562 break;
1573 1563 }
1574 1564
1575 1565 case ECPPIOC_SETPORT:
1576 1566 case ECPPIOC_SETDATA: {
1577 1567 mutex_enter(&pp->umutex);
1578 1568 if (pp->current_mode != ECPP_DIAG_MODE) {
1579 1569 mutex_exit(&pp->umutex);
1580 1570 ecpp_nack_ioctl(q, mp, EINVAL);
1581 1571 break;
1582 1572 }
1583 1573 mutex_exit(&pp->umutex);
1584 1574
1585 1575 /*
1586 1576 * each of the commands fetches a byte quantity.
1587 1577 */
1588 1578 mcopyin(mp, NULL, sizeof (uchar_t), NULL);
1589 1579 qreply(q, mp);
1590 1580 break;
1591 1581 }
1592 1582
1593 1583 case ECPPIOC_GETDATA:
1594 1584 case ECPPIOC_GETPORT: {
1595 1585 uchar_t byte;
1596 1586
1597 1587 mutex_enter(&pp->umutex);
1598 1588
1599 1589 /* must be in diagnostic mode for these commands to work */
1600 1590 if (pp->current_mode != ECPP_DIAG_MODE) {
1601 1591 mutex_exit(&pp->umutex);
1602 1592 ecpp_nack_ioctl(q, mp, EINVAL);
1603 1593 break;
1604 1594 }
1605 1595
1606 1596 if (iocbp->ioc_cmd == ECPPIOC_GETPORT) {
1607 1597 byte = pp->port;
1608 1598 } else if (iocbp->ioc_cmd == ECPPIOC_GETDATA) {
1609 1599 switch (pp->port) {
1610 1600 case ECPP_PORT_PIO:
1611 1601 byte = DATAR_READ(pp);
1612 1602 break;
1613 1603 case ECPP_PORT_TDMA:
1614 1604 byte = TFIFO_READ(pp);
1615 1605 ecpp_error(pp->dip, "GETDATA=0x%x\n", byte);
1616 1606 break;
1617 1607 default:
1618 1608 ecpp_nack_ioctl(q, mp, EINVAL);
1619 1609 break;
1620 1610 }
1621 1611 } else {
1622 1612 mutex_exit(&pp->umutex);
1623 1613 ecpp_error(pp->dip, "weird command");
1624 1614 ecpp_nack_ioctl(q, mp, EINVAL);
1625 1615 break;
1626 1616 }
1627 1617
1628 1618 mutex_exit(&pp->umutex);
1629 1619
1630 1620 ecpp_putioc_copyout(q, mp, &byte, sizeof (byte));
1631 1621
1632 1622 break;
1633 1623 }
1634 1624
1635 1625 case BPPIOC_GETERR: {
1636 1626 struct bpp_error_status bpp_status;
1637 1627
1638 1628 mutex_enter(&pp->umutex);
1639 1629
1640 1630 bpp_status.timeout_occurred = pp->timeout_error;
1641 1631 bpp_status.bus_error = 0; /* not used */
1642 1632 bpp_status.pin_status = ecpp_get_error_status(pp->saved_dsr);
1643 1633
1644 1634 mutex_exit(&pp->umutex);
1645 1635
1646 1636 ecpp_putioc_copyout(q, mp, &bpp_status, sizeof (bpp_status));
1647 1637
1648 1638 break;
1649 1639 }
1650 1640
1651 1641 case BPPIOC_TESTIO: {
1652 1642 mutex_enter(&pp->umutex);
1653 1643
1654 1644 if (!((pp->current_mode == ECPP_CENTRONICS) ||
1655 1645 (pp->current_mode == ECPP_COMPAT_MODE))) {
1656 1646 ecpp_nack_ioctl(q, mp, EINVAL);
1657 1647 } else {
1658 1648 pp->saved_dsr = DSR_READ(pp);
1659 1649
1660 1650 if ((pp->saved_dsr & ECPP_PE) ||
1661 1651 !(pp->saved_dsr & ECPP_SLCT) ||
1662 1652 !(pp->saved_dsr & ECPP_nERR)) {
1663 1653 ecpp_nack_ioctl(q, mp, EIO);
1664 1654 } else {
1665 1655 ecpp_ack_ioctl(q, mp);
1666 1656 }
1667 1657 }
1668 1658
1669 1659 mutex_exit(&pp->umutex);
1670 1660
1671 1661 break;
1672 1662 }
1673 1663
1674 1664 case PRNIOC_RESET:
1675 1665 /*
1676 1666 * Initialize interface only if no transfer is in progress
1677 1667 */
1678 1668 mutex_enter(&pp->umutex);
1679 1669 if (pp->e_busy == ECPP_BUSY) {
1680 1670 mutex_exit(&pp->umutex);
1681 1671 ecpp_nack_ioctl(q, mp, EIO);
1682 1672 } else {
1683 1673 (void) ecpp_mode_negotiation(pp, ECPP_CENTRONICS);
1684 1674
1685 1675 DCR_WRITE(pp, ECPP_SLCTIN);
1686 1676 drv_usecwait(2);
1687 1677 DCR_WRITE(pp, ECPP_SLCTIN | ECPP_nINIT);
1688 1678
1689 1679 ecpp_default_negotiation(pp);
1690 1680
1691 1681 mutex_exit(&pp->umutex);
1692 1682 ecpp_ack_ioctl(q, mp);
1693 1683 }
1694 1684 break;
1695 1685
1696 1686 case PRNIOC_GET_IFCAP: {
1697 1687 uint_t ifcap;
1698 1688
1699 1689 mutex_enter(&pp->umutex);
1700 1690
1701 1691 ifcap = ecpp_get_prn_ifcap(pp);
1702 1692
1703 1693 mutex_exit(&pp->umutex);
1704 1694
1705 1695 ecpp_putioc_copyout(q, mp, &ifcap, sizeof (ifcap));
1706 1696 break;
1707 1697 }
1708 1698
1709 1699 case PRNIOC_SET_IFCAP: {
1710 1700 mcopyin(mp, NULL, sizeof (uint_t), NULL);
1711 1701 qreply(q, mp);
1712 1702 break;
1713 1703 }
1714 1704
1715 1705 case PRNIOC_GET_TIMEOUTS: {
1716 1706 struct prn_timeouts timeouts;
1717 1707
1718 1708 mutex_enter(&pp->umutex);
1719 1709 timeouts = pp->prn_timeouts;
1720 1710 mutex_exit(&pp->umutex);
1721 1711
1722 1712 ecpp_putioc_copyout(q, mp, &timeouts, sizeof (timeouts));
1723 1713
1724 1714 break;
1725 1715 }
1726 1716
1727 1717 case PRNIOC_SET_TIMEOUTS:
1728 1718 mcopyin(mp, NULL, sizeof (struct prn_timeouts),
1729 1719 *(caddr_t *)(void *)mp->b_cont->b_rptr);
1730 1720 qreply(q, mp);
1731 1721 break;
1732 1722
1733 1723 case PRNIOC_GET_STATUS: {
1734 1724 uint8_t dsr;
1735 1725 uint_t status;
1736 1726
1737 1727 mutex_enter(&pp->umutex);
1738 1728
1739 1729 /* DSR only makes sense in Centronics & Compat mode */
1740 1730 if (pp->current_mode == ECPP_CENTRONICS ||
1741 1731 pp->current_mode == ECPP_COMPAT_MODE) {
1742 1732 dsr = DSR_READ(pp);
1743 1733 if ((dsr & ECPP_PE) ||
1744 1734 !(dsr & ECPP_SLCT) || !(dsr & ECPP_nERR)) {
1745 1735 status = PRN_ONLINE;
1746 1736 } else {
1747 1737 status = PRN_ONLINE | PRN_READY;
1748 1738 }
1749 1739 } else {
1750 1740 status = PRN_ONLINE | PRN_READY;
1751 1741 }
1752 1742
1753 1743 mutex_exit(&pp->umutex);
1754 1744
1755 1745 ecpp_putioc_copyout(q, mp, &status, sizeof (status));
1756 1746 break;
1757 1747 }
1758 1748
1759 1749 case PRNIOC_GET_1284_STATUS: {
1760 1750 uint8_t dsr;
1761 1751 uchar_t status;
1762 1752
1763 1753 mutex_enter(&pp->umutex);
1764 1754
1765 1755 /* status only makes sense in Centronics & Compat mode */
1766 1756 if (pp->current_mode != ECPP_COMPAT_MODE &&
1767 1757 pp->current_mode != ECPP_CENTRONICS) {
1768 1758 mutex_exit(&pp->umutex);
1769 1759 ecpp_nack_ioctl(q, mp, EINVAL);
1770 1760 break;
1771 1761 }
1772 1762
1773 1763 dsr = DSR_READ(pp); /* read status */
1774 1764
1775 1765 mutex_exit(&pp->umutex);
1776 1766
1777 1767 ecpp_error(pp->dip, "PRNIOC_GET_STATUS: %x\n", dsr);
1778 1768
1779 1769 status = (dsr & (ECPP_SLCT | ECPP_PE | ECPP_nERR)) |
1780 1770 (~dsr & ECPP_nBUSY);
1781 1771
1782 1772 ecpp_putioc_copyout(q, mp, &status, sizeof (status));
1783 1773 break;
1784 1774 }
1785 1775
1786 1776 case ECPPIOC_GETDEVID:
1787 1777 ecpp_putioc_stateful_copyin(q, mp,
1788 1778 sizeof (struct ecpp_device_id));
1789 1779 break;
1790 1780
1791 1781 case PRNIOC_GET_1284_DEVID:
1792 1782 ecpp_putioc_stateful_copyin(q, mp,
1793 1783 sizeof (struct prn_1284_device_id));
1794 1784 break;
1795 1785
1796 1786 case PRNIOC_GET_IFINFO:
1797 1787 ecpp_putioc_stateful_copyin(q, mp,
1798 1788 sizeof (struct prn_interface_info));
1799 1789 break;
1800 1790
1801 1791 default:
1802 1792 ecpp_error(pp->dip, "putioc: unknown IOCTL: %x\n",
1803 1793 iocbp->ioc_cmd);
1804 1794 ecpp_nack_ioctl(q, mp, EINVAL);
1805 1795 break;
1806 1796 }
1807 1797 }
1808 1798
1809 1799 /*
1810 1800 * allocate mblk and copyout the requested number of bytes
1811 1801 */
1812 1802 static void
1813 1803 ecpp_putioc_copyout(queue_t *q, mblk_t *mp, void *buf, int len)
1814 1804 {
1815 1805 mblk_t *tmp;
1816 1806
1817 1807 if ((tmp = allocb(len, BPRI_MED)) == NULL) {
1818 1808 ecpp_nack_ioctl(q, mp, ENOSR);
1819 1809 return;
1820 1810 }
1821 1811
1822 1812 bcopy(buf, tmp->b_wptr, len);
1823 1813
1824 1814 mcopyout(mp, NULL, len, NULL, tmp);
1825 1815 qreply(q, mp);
1826 1816 }
1827 1817
1828 1818 /*
1829 1819 * copyin the structure using struct ecpp_copystate
1830 1820 */
1831 1821 static void
1832 1822 ecpp_putioc_stateful_copyin(queue_t *q, mblk_t *mp, size_t size)
1833 1823 {
1834 1824 mblk_t *tmp;
1835 1825 struct ecpp_copystate *stp;
1836 1826
1837 1827 if ((tmp = allocb(sizeof (struct ecpp_copystate), BPRI_MED)) == NULL) {
1838 1828 ecpp_nack_ioctl(q, mp, EAGAIN);
1839 1829 return;
1840 1830 }
1841 1831
1842 1832 stp = (struct ecpp_copystate *)tmp->b_rptr;
1843 1833 stp->state = ECPP_STRUCTIN;
1844 1834 stp->uaddr = *(caddr_t *)mp->b_cont->b_rptr;
1845 1835
1846 1836 tmp->b_wptr += sizeof (struct ecpp_copystate);
1847 1837
1848 1838 mcopyin(mp, tmp, size, stp->uaddr);
1849 1839 qreply(q, mp);
1850 1840 }
1851 1841
1852 1842 /*
1853 1843 * read queue is only used when the peripheral sends data faster,
1854 1844 * then the application consumes it;
1855 1845 * once the low water mark is reached, this routine will be scheduled
1856 1846 */
1857 1847 static int
1858 1848 ecpp_rsrv(queue_t *q)
1859 1849 {
1860 1850 struct msgb *mp;
1861 1851
1862 1852 /*
1863 1853 * send data upstream until next queue is full or the queue is empty
1864 1854 */
1865 1855 while (canputnext(q) && (mp = getq(q))) {
1866 1856 putnext(q, mp);
1867 1857 }
1868 1858
1869 1859 /*
1870 1860 * if there is still space on the queue, enable backchannel
1871 1861 */
1872 1862 if (canputnext(q)) {
1873 1863 struct ecppunit *pp = (struct ecppunit *)q->q_ptr;
1874 1864
1875 1865 mutex_enter(&pp->umutex);
1876 1866
1877 1867 if (pp->e_busy == ECPP_IDLE) {
1878 1868 (void) ecpp_idle_phase(pp);
1879 1869 cv_signal(&pp->pport_cv); /* signal ecpp_close() */
1880 1870 }
1881 1871
1882 1872 mutex_exit(&pp->umutex);
1883 1873 }
1884 1874
1885 1875 return (0);
1886 1876 }
1887 1877
1888 1878 static int
1889 1879 ecpp_wsrv(queue_t *q)
1890 1880 {
1891 1881 struct ecppunit *pp = (struct ecppunit *)q->q_ptr;
1892 1882 struct msgb *mp;
1893 1883 size_t len, total_len;
1894 1884 size_t my_ioblock_sz;
1895 1885 caddr_t my_ioblock;
1896 1886 caddr_t start_addr;
1897 1887
1898 1888 mutex_enter(&pp->umutex);
1899 1889
1900 1890 ecpp_error(pp->dip, "ecpp_wsrv: e_busy=%x\n", pp->e_busy);
1901 1891
1902 1892 /* if channel is actively doing work, wait till completed */
1903 1893 if (pp->e_busy == ECPP_BUSY || pp->e_busy == ECPP_FLUSH) {
1904 1894 mutex_exit(&pp->umutex);
1905 1895 return (0);
1906 1896 } else if (pp->suspended == TRUE) {
1907 1897 /*
1908 1898 * if the system is about to suspend and ecpp_detach()
1909 1899 * is blocked due to active transfers, wake it up and exit
1910 1900 */
1911 1901 cv_signal(&pp->pport_cv);
1912 1902 mutex_exit(&pp->umutex);
1913 1903 return (0);
1914 1904 }
1915 1905
1916 1906 /* peripheral status should be okay before starting transfer */
1917 1907 if (pp->e_busy == ECPP_ERR) {
1918 1908 if (ecpp_check_status(pp) == FAILURE) {
1919 1909 if (pp->wsrv_timer_id == 0) {
1920 1910 ecpp_error(pp->dip, "wsrv: start wrsv_timer\n");
1921 1911 pp->wsrv_timer_id = timeout(ecpp_wsrv_timer,
1922 1912 (caddr_t)pp,
1923 1913 drv_usectohz(pp->wsrv_retry * 1000));
1924 1914 } else {
1925 1915 ecpp_error(pp->dip,
1926 1916 "ecpp_wsrv: wrsv_timer is active\n");
1927 1917 }
1928 1918
1929 1919 mutex_exit(&pp->umutex);
1930 1920 return (0);
1931 1921 } else {
1932 1922 pp->e_busy = ECPP_IDLE;
1933 1923 }
1934 1924 }
1935 1925
1936 1926 my_ioblock = pp->ioblock;
1937 1927 my_ioblock_sz = IO_BLOCK_SZ;
1938 1928
1939 1929 /*
1940 1930 * it`s important to null pp->msg here,
1941 1931 * cleaning up from the previous transfer attempts
1942 1932 */
1943 1933 pp->msg = NULL;
1944 1934
1945 1935 start_addr = NULL;
1946 1936 len = total_len = 0;
1947 1937 /*
1948 1938 * The following loop is implemented to gather the
1949 1939 * many small writes that the lp subsystem makes and
1950 1940 * compile them into one large dma transfer. The len and
1951 1941 * total_len variables are a running count of the number of
1952 1942 * bytes that have been gathered. They are bcopied to the
1953 1943 * ioblock buffer. The pp->e_busy is set to E_BUSY as soon as
1954 1944 * we start gathering packets to indicate the following transfer.
1955 1945 */
1956 1946 while (mp = getq(q)) {
1957 1947 switch (DB_TYPE(mp)) {
1958 1948 case M_DATA:
1959 1949 pp->e_busy = ECPP_BUSY;
1960 1950 len = mp->b_wptr - mp->b_rptr;
1961 1951
1962 1952 if ((total_len == 0) && (len >= my_ioblock_sz)) {
1963 1953 /*
1964 1954 * if the first M_DATA is bigger than ioblock,
1965 1955 * just use this mblk and start the transfer
1966 1956 */
1967 1957 total_len = len;
1968 1958 start_addr = (caddr_t)mp->b_rptr;
1969 1959 pp->msg = mp;
1970 1960 goto breakout;
1971 1961 } else if (total_len + len > my_ioblock_sz) {
1972 1962 /*
1973 1963 * current M_DATA does not fit in ioblock,
1974 1964 * put it back and start the transfer
1975 1965 */
1976 1966 (void) putbq(q, mp);
1977 1967 goto breakout;
1978 1968 } else {
1979 1969 /*
1980 1970 * otherwise add data to ioblock and free mblk
1981 1971 */
1982 1972 bcopy(mp->b_rptr, my_ioblock, len);
1983 1973 my_ioblock += len;
1984 1974 total_len += len;
1985 1975 start_addr = (caddr_t)pp->ioblock;
1986 1976 freemsg(mp);
1987 1977 }
1988 1978 break;
1989 1979
1990 1980 case M_IOCTL:
1991 1981 /*
1992 1982 * Assume a simple loopback test: an application
1993 1983 * writes data into the TFIFO, reads it using
1994 1984 * ECPPIOC_GETDATA and compares. If the transfer
1995 1985 * times out (which is only possible on Grover),
1996 1986 * the ioctl might be processed before the data
1997 1987 * got to the TFIFO, which leads to miscompare.
1998 1988 * So if we met ioctl, postpone it until after xfer.
1999 1989 */
2000 1990 if (total_len > 0) {
2001 1991 (void) putbq(q, mp);
2002 1992 goto breakout;
2003 1993 }
2004 1994
2005 1995 ecpp_error(pp->dip, "M_IOCTL.\n");
2006 1996
2007 1997 mutex_exit(&pp->umutex);
2008 1998
2009 1999 ecpp_putioc(q, mp);
2010 2000
2011 2001 mutex_enter(&pp->umutex);
2012 2002
2013 2003 break;
2014 2004
2015 2005 case M_IOCDATA: {
2016 2006 struct copyresp *csp = (struct copyresp *)mp->b_rptr;
2017 2007
2018 2008 ecpp_error(pp->dip, "M_IOCDATA\n");
2019 2009
2020 2010 /*
2021 2011 * If copy request failed, quit now
2022 2012 */
2023 2013 if (csp->cp_rval != 0) {
2024 2014 freemsg(mp);
2025 2015 break;
2026 2016 }
2027 2017
2028 2018 switch (csp->cp_cmd) {
2029 2019 case ECPPIOC_SETPARMS:
2030 2020 case ECPPIOC_SETREGS:
2031 2021 case ECPPIOC_SETPORT:
2032 2022 case ECPPIOC_SETDATA:
2033 2023 case ECPPIOC_GETDEVID:
2034 2024 case PRNIOC_SET_IFCAP:
2035 2025 case PRNIOC_GET_1284_DEVID:
2036 2026 case PRNIOC_SET_TIMEOUTS:
2037 2027 case PRNIOC_GET_IFINFO:
2038 2028 ecpp_srvioc(q, mp);
2039 2029 break;
2040 2030
2041 2031 default:
2042 2032 ecpp_nack_ioctl(q, mp, EINVAL);
2043 2033 break;
2044 2034 }
2045 2035
2046 2036 break;
2047 2037 }
2048 2038
2049 2039 case M_CTL:
2050 2040 if (pp->e_busy != ECPP_IDLE) {
2051 2041 ecpp_error(pp->dip, "wsrv: M_CTL postponed\n");
2052 2042 (void) putbq(q, mp);
2053 2043 goto breakout;
2054 2044 } else {
2055 2045 ecpp_error(pp->dip, "wsrv: M_CTL\n");
2056 2046 }
2057 2047
2058 2048 /* sanity check */
2059 2049 if ((mp->b_wptr - mp->b_rptr != sizeof (int)) ||
2060 2050 (*(int *)mp->b_rptr != ECPP_BACKCHANNEL)) {
2061 2051 ecpp_error(pp->dip, "wsrv: bogus M_CTL");
2062 2052 freemsg(mp);
2063 2053 break;
2064 2054 } else {
2065 2055 freemsg(mp);
2066 2056 }
2067 2057
2068 2058 /* This was a backchannel request */
2069 2059 (void) ecpp_peripheral2host(pp);
2070 2060
2071 2061 /* exit if transfer have been initiated */
2072 2062 if (pp->e_busy == ECPP_BUSY) {
2073 2063 goto breakout;
2074 2064 }
2075 2065 break;
2076 2066
2077 2067 case M_READ:
2078 2068 pp->nread += *(size_t *)mp->b_rptr;
2079 2069 freemsg(mp);
2080 2070 ecpp_error(pp->dip, "wsrv: M_READ %d", pp->nread);
2081 2071 break;
2082 2072
2083 2073 default:
2084 2074 ecpp_error(pp->dip, "wsrv: should never get here\n");
2085 2075 freemsg(mp);
2086 2076 break;
2087 2077 }
2088 2078 }
2089 2079 breakout:
2090 2080 /*
2091 2081 * If total_len > 0 then start the transfer, otherwise goto idle state
2092 2082 */
2093 2083 if (total_len > 0) {
2094 2084 ecpp_error(pp->dip, "wsrv:starting: total_len=%d\n", total_len);
2095 2085 pp->e_busy = ECPP_BUSY;
2096 2086 ecpp_start(pp, start_addr, total_len);
2097 2087 } else {
2098 2088 ecpp_error(pp->dip, "wsrv:finishing: ebusy=%x\n", pp->e_busy);
2099 2089
2100 2090 /* IDLE if xfer_timeout, or FIFO_EMPTY */
2101 2091 if (pp->e_busy == ECPP_IDLE) {
2102 2092 (void) ecpp_idle_phase(pp);
2103 2093 cv_signal(&pp->pport_cv); /* signal ecpp_close() */
2104 2094 }
2105 2095 }
2106 2096
2107 2097 mutex_exit(&pp->umutex);
2108 2098 return (1);
2109 2099 }
2110 2100
2111 2101 /*
2112 2102 * Ioctl processor for queued ioctl data transfer messages.
2113 2103 */
2114 2104 static void
2115 2105 ecpp_srvioc(queue_t *q, mblk_t *mp)
2116 2106 {
2117 2107 struct iocblk *iocbp;
2118 2108 struct ecppunit *pp;
2119 2109
2120 2110 iocbp = (struct iocblk *)mp->b_rptr;
2121 2111 pp = (struct ecppunit *)q->q_ptr;
2122 2112
2123 2113 switch (iocbp->ioc_cmd) {
2124 2114 case ECPPIOC_SETPARMS: {
2125 2115 struct ecpp_transfer_parms *xferp;
2126 2116
2127 2117 xferp = (struct ecpp_transfer_parms *)mp->b_cont->b_rptr;
2128 2118
2129 2119 if (xferp->write_timeout <= 0 ||
2130 2120 xferp->write_timeout >= ECPP_MAX_TIMEOUT) {
2131 2121 ecpp_nack_ioctl(q, mp, EINVAL);
2132 2122 break;
2133 2123 }
2134 2124
2135 2125 if (!((xferp->mode == ECPP_CENTRONICS) ||
2136 2126 (xferp->mode == ECPP_COMPAT_MODE) ||
2137 2127 (xferp->mode == ECPP_NIBBLE_MODE) ||
2138 2128 (xferp->mode == ECPP_ECP_MODE) ||
2139 2129 (xferp->mode == ECPP_DIAG_MODE))) {
2140 2130 ecpp_nack_ioctl(q, mp, EINVAL);
2141 2131 break;
2142 2132 }
2143 2133
2144 2134 pp->xfer_parms = *xferp;
2145 2135 pp->prn_timeouts.tmo_forward = pp->xfer_parms.write_timeout;
2146 2136
2147 2137 ecpp_error(pp->dip, "srvioc: current_mode =%x new mode=%x\n",
2148 2138 pp->current_mode, pp->xfer_parms.mode);
2149 2139
2150 2140 if (ecpp_mode_negotiation(pp, pp->xfer_parms.mode) == FAILURE) {
2151 2141 ecpp_nack_ioctl(q, mp, EPROTONOSUPPORT);
2152 2142 } else {
2153 2143 /*
2154 2144 * mode nego was a success. If nibble mode check
2155 2145 * back channel and set into REVIDLE.
2156 2146 */
2157 2147 if ((pp->current_mode == ECPP_NIBBLE_MODE) &&
2158 2148 (read_nibble_backchan(pp) == FAILURE)) {
2159 2149 /*
2160 2150 * problems reading the backchannel
2161 2151 * returned to centronics;
2162 2152 * ioctl fails.
2163 2153 */
2164 2154 ecpp_nack_ioctl(q, mp, EPROTONOSUPPORT);
2165 2155 break;
2166 2156 }
2167 2157
2168 2158 ecpp_ack_ioctl(q, mp);
2169 2159 }
2170 2160 if (pp->current_mode != ECPP_DIAG_MODE) {
2171 2161 pp->port = ECPP_PORT_DMA;
2172 2162 } else {
2173 2163 pp->port = ECPP_PORT_PIO;
2174 2164 }
2175 2165
2176 2166 pp->xfer_parms.mode = pp->current_mode;
2177 2167
2178 2168 break;
2179 2169 }
2180 2170
2181 2171 case ECPPIOC_SETREGS: {
2182 2172 struct ecpp_regs *rg;
2183 2173 uint8_t dcr;
2184 2174
2185 2175 rg = (struct ecpp_regs *)mp->b_cont->b_rptr;
2186 2176
2187 2177 /* must be in diagnostic mode for these commands to work */
2188 2178 if (pp->current_mode != ECPP_DIAG_MODE) {
2189 2179 ecpp_nack_ioctl(q, mp, EINVAL);
2190 2180 break;
2191 2181 }
2192 2182
2193 2183 /* bits 4-7 must be 1 or return EINVAL */
2194 2184 if ((rg->dcr & ECPP_SETREGS_DCR_MASK) !=
2195 2185 ECPP_SETREGS_DCR_MASK) {
2196 2186 ecpp_nack_ioctl(q, mp, EINVAL);
2197 2187 break;
2198 2188 }
2199 2189
2200 2190 /* get the old dcr */
2201 2191 dcr = DCR_READ(pp) & ~ECPP_REV_DIR;
2202 2192 /* get the new dcr */
2203 2193 dcr = (dcr & ECPP_SETREGS_DCR_MASK) |
2204 2194 (rg->dcr & ~ECPP_SETREGS_DCR_MASK);
2205 2195 DCR_WRITE(pp, dcr);
2206 2196 ecpp_error(pp->dip, "ECPPIOC_SETREGS:dcr=%x\n", dcr);
2207 2197 ecpp_ack_ioctl(q, mp);
2208 2198 break;
2209 2199 }
2210 2200
2211 2201 case ECPPIOC_SETPORT: {
2212 2202 uchar_t *port;
2213 2203
2214 2204 port = (uchar_t *)mp->b_cont->b_rptr;
2215 2205
2216 2206 /* must be in diagnostic mode for these commands to work */
2217 2207 if (pp->current_mode != ECPP_DIAG_MODE) {
2218 2208 ecpp_nack_ioctl(q, mp, EINVAL);
2219 2209 break;
2220 2210 }
2221 2211
2222 2212 switch (*port) {
2223 2213 case ECPP_PORT_PIO:
2224 2214 /* put superio into PIO mode */
2225 2215 ECR_WRITE(pp,
2226 2216 ECR_mode_001 | ECPP_INTR_MASK | ECPP_INTR_SRV);
2227 2217 pp->port = *port;
2228 2218 ecpp_ack_ioctl(q, mp);
2229 2219 break;
2230 2220
2231 2221 case ECPP_PORT_TDMA:
2232 2222 ecpp_error(pp->dip, "SETPORT: to TDMA\n");
2233 2223 pp->tfifo_intr = 1;
2234 2224 /* change to mode 110 */
2235 2225 ECR_WRITE(pp,
2236 2226 ECR_mode_110 | ECPP_INTR_MASK | ECPP_INTR_SRV);
2237 2227 pp->port = *port;
2238 2228 ecpp_ack_ioctl(q, mp);
2239 2229 break;
2240 2230
2241 2231 default:
2242 2232 ecpp_nack_ioctl(q, mp, EINVAL);
2243 2233 }
2244 2234
2245 2235 break;
2246 2236 }
2247 2237
2248 2238 case ECPPIOC_SETDATA: {
2249 2239 uchar_t *data;
2250 2240
2251 2241 data = (uchar_t *)mp->b_cont->b_rptr;
2252 2242
2253 2243 /* must be in diagnostic mode for these commands to work */
2254 2244 if (pp->current_mode != ECPP_DIAG_MODE) {
2255 2245 ecpp_nack_ioctl(q, mp, EINVAL);
2256 2246 break;
2257 2247 }
2258 2248
2259 2249 switch (pp->port) {
2260 2250 case ECPP_PORT_PIO:
2261 2251 DATAR_WRITE(pp, *data);
2262 2252 ecpp_ack_ioctl(q, mp);
2263 2253 break;
2264 2254
2265 2255 case ECPP_PORT_TDMA:
2266 2256 TFIFO_WRITE(pp, *data);
2267 2257 ecpp_ack_ioctl(q, mp);
2268 2258 break;
2269 2259
2270 2260 default:
2271 2261 ecpp_nack_ioctl(q, mp, EINVAL);
2272 2262 }
2273 2263
2274 2264 break;
2275 2265 }
2276 2266
2277 2267 case ECPPIOC_GETDEVID: {
2278 2268 struct copyresp *csp;
2279 2269 struct ecpp_copystate *stp;
2280 2270 struct ecpp_device_id *dp;
2281 2271 struct ecpp_device_id id;
2282 2272
2283 2273 csp = (struct copyresp *)mp->b_rptr;
2284 2274 stp = (struct ecpp_copystate *)csp->cp_private->b_rptr;
2285 2275 dp = (struct ecpp_device_id *)mp->b_cont->b_rptr;
2286 2276
2287 2277 #ifdef _MULTI_DATAMODEL
2288 2278 if (IOC_CONVERT_FROM(iocbp) == IOC_ILP32) {
2289 2279 struct ecpp_device_id32 *dp32;
2290 2280
2291 2281 dp32 = (struct ecpp_device_id32 *)dp;
2292 2282 id.mode = dp32->mode;
2293 2283 id.len = dp32->len;
2294 2284 id.addr = (char *)(uintptr_t)dp32->addr;
2295 2285 } else {
2296 2286 #endif /* _MULTI_DATAMODEL */
2297 2287 id = *dp;
2298 2288 #ifdef _MULTI_DATAMODEL
2299 2289 }
2300 2290 #endif /* _MULTI_DATAMODEL */
2301 2291
2302 2292 ecpp_srvioc_devid(q, mp, &id, &stp->un.devid.rlen);
2303 2293 break;
2304 2294 }
2305 2295
2306 2296 case PRNIOC_GET_1284_DEVID: {
2307 2297 struct copyresp *csp;
2308 2298 struct ecpp_copystate *stp;
2309 2299 struct prn_1284_device_id *dp;
2310 2300 struct ecpp_device_id id;
2311 2301
2312 2302 csp = (struct copyresp *)mp->b_rptr;
2313 2303 stp = (struct ecpp_copystate *)csp->cp_private->b_rptr;
2314 2304 dp = (struct prn_1284_device_id *)mp->b_cont->b_rptr;
2315 2305
2316 2306 /* imitate struct ecpp_device_id */
2317 2307 id.mode = ECPP_NIBBLE_MODE;
2318 2308
2319 2309 #ifdef _MULTI_DATAMODEL
2320 2310 if (IOC_CONVERT_FROM(iocbp) == IOC_ILP32) {
2321 2311 struct prn_1284_device_id32 *dp32;
2322 2312
2323 2313 dp32 = (struct prn_1284_device_id32 *)dp;
2324 2314 id.len = dp32->id_len;
2325 2315 id.addr = (char *)(uintptr_t)dp32->id_data;
2326 2316 } else {
2327 2317 #endif /* _MULTI_DATAMODEL */
2328 2318 id.len = dp->id_len;
2329 2319 id.addr = (char *)dp->id_data;
2330 2320 #ifdef _MULTI_DATAMODEL
2331 2321 }
2332 2322 #endif /* _MULTI_DATAMODEL */
2333 2323
2334 2324 ecpp_srvioc_devid(q, mp, &id,
2335 2325 (int *)&stp->un.prn_devid.id_rlen);
2336 2326 break;
2337 2327 }
2338 2328
2339 2329 case PRNIOC_SET_IFCAP: {
2340 2330 uint_t ifcap, new_ifcap;
2341 2331
2342 2332 ifcap = ecpp_get_prn_ifcap(pp);
2343 2333 new_ifcap = *(uint_t *)mp->b_cont->b_rptr;
2344 2334
2345 2335 if (ifcap == new_ifcap) {
2346 2336 ecpp_ack_ioctl(q, mp);
2347 2337 break;
2348 2338 }
2349 2339
2350 2340 /* only changing PRN_BIDI is supported */
2351 2341 if ((ifcap ^ new_ifcap) & ~PRN_BIDI) {
2352 2342 ecpp_nack_ioctl(q, mp, EINVAL);
2353 2343 break;
2354 2344 }
2355 2345
2356 2346 if (new_ifcap & PRN_BIDI) { /* go bidirectional */
2357 2347 ecpp_default_negotiation(pp);
2358 2348 } else { /* go unidirectional */
2359 2349 (void) ecpp_mode_negotiation(pp, ECPP_CENTRONICS);
2360 2350 }
2361 2351
2362 2352 ecpp_ack_ioctl(q, mp);
2363 2353 break;
2364 2354 }
2365 2355
2366 2356 case PRNIOC_SET_TIMEOUTS: {
2367 2357 struct prn_timeouts *prn_timeouts;
2368 2358
2369 2359 prn_timeouts = (struct prn_timeouts *)mp->b_cont->b_rptr;
2370 2360
2371 2361 if (prn_timeouts->tmo_forward > ECPP_MAX_TIMEOUT) {
2372 2362 ecpp_nack_ioctl(q, mp, EINVAL);
2373 2363 break;
2374 2364 }
2375 2365
2376 2366 pp->prn_timeouts = *prn_timeouts;
2377 2367 pp->xfer_parms.write_timeout = (int)prn_timeouts->tmo_forward;
2378 2368
2379 2369 ecpp_ack_ioctl(q, mp);
2380 2370 break;
2381 2371 }
2382 2372
2383 2373 case PRNIOC_GET_IFINFO:
2384 2374 ecpp_srvioc_prnif(q, mp);
2385 2375 break;
2386 2376
2387 2377 default: /* unexpected ioctl type */
2388 2378 ecpp_nack_ioctl(q, mp, EINVAL);
2389 2379 break;
2390 2380 }
2391 2381 }
2392 2382
2393 2383 static void
2394 2384 ecpp_srvioc_devid(queue_t *q, mblk_t *mp, struct ecpp_device_id *id, int *rlen)
2395 2385 {
2396 2386 struct ecppunit *pp;
2397 2387 struct copyresp *csp;
2398 2388 struct ecpp_copystate *stp;
2399 2389 int error;
2400 2390 int len;
2401 2391 int mode;
2402 2392 mblk_t *datamp;
2403 2393
2404 2394 pp = (struct ecppunit *)q->q_ptr;
2405 2395 csp = (struct copyresp *)mp->b_rptr;
2406 2396 stp = (struct ecpp_copystate *)csp->cp_private->b_rptr;
2407 2397 mode = id->mode;
2408 2398
2409 2399 /* check arguments */
2410 2400 if ((mode < ECPP_CENTRONICS) || (mode > ECPP_ECP_MODE)) {
2411 2401 ecpp_error(pp->dip, "ecpp_srvioc_devid: mode=%x, len=%x\n",
2412 2402 mode, id->len);
2413 2403 ecpp_nack_ioctl(q, mp, EINVAL);
2414 2404 return;
2415 2405 }
2416 2406
2417 2407 /* Currently only Nibble mode is supported */
2418 2408 if (mode != ECPP_NIBBLE_MODE) {
2419 2409 ecpp_nack_ioctl(q, mp, EPROTONOSUPPORT);
2420 2410 return;
2421 2411 }
2422 2412
2423 2413 if ((id->addr == NULL) && (id->len != 0)) {
2424 2414 ecpp_nack_ioctl(q, mp, EFAULT);
2425 2415 return;
2426 2416 }
2427 2417
2428 2418 /* read device ID length */
2429 2419 if (error = ecpp_getdevid(pp, NULL, &len, mode)) {
2430 2420 ecpp_nack_ioctl(q, mp, error);
2431 2421 goto breakout;
2432 2422 }
2433 2423
2434 2424 /* don't take into account two length bytes */
2435 2425 len -= 2;
2436 2426 *rlen = len;
2437 2427
2438 2428 /* limit transfer to user buffer length */
2439 2429 if (id->len < len) {
2440 2430 len = id->len;
2441 2431 }
2442 2432
2443 2433 if (len == 0) {
2444 2434 /* just return rlen */
2445 2435 stp->state = ECPP_ADDROUT;
2446 2436 ecpp_wput_iocdata_devid(q, mp,
2447 2437 (uintptr_t)rlen - (uintptr_t)&stp->un);
2448 2438 goto breakout;
2449 2439 }
2450 2440
2451 2441 if ((datamp = allocb(len, BPRI_MED)) == NULL) {
2452 2442 ecpp_nack_ioctl(q, mp, ENOSR);
2453 2443 goto breakout;
2454 2444 }
2455 2445
2456 2446 /* read ID string */
2457 2447 error = ecpp_getdevid(pp, datamp->b_rptr, &len, mode);
2458 2448 if (error) {
2459 2449 freemsg(datamp);
2460 2450 ecpp_nack_ioctl(q, mp, error);
2461 2451 goto breakout;
2462 2452 } else {
2463 2453 datamp->b_wptr += len;
2464 2454
2465 2455 stp->state = ECPP_ADDROUT;
2466 2456 mcopyout(mp, csp->cp_private, len, id->addr, datamp);
2467 2457 qreply(q, mp);
2468 2458 }
2469 2459
2470 2460 return;
2471 2461
2472 2462 breakout:
2473 2463 (void) ecpp_1284_termination(pp);
2474 2464 }
2475 2465
2476 2466 /*
2477 2467 * PRNIOC_GET_IFINFO: return prnio interface info string
2478 2468 */
2479 2469 static void
2480 2470 ecpp_srvioc_prnif(queue_t *q, mblk_t *mp)
2481 2471 {
2482 2472 struct copyresp *csp;
2483 2473 struct ecpp_copystate *stp;
2484 2474 uint_t len;
2485 2475 struct prn_interface_info *ip;
2486 2476 struct prn_interface_info info;
2487 2477 mblk_t *datamp;
2488 2478 #ifdef _MULTI_DATAMODEL
2489 2479 struct iocblk *iocbp = (struct iocblk *)mp->b_rptr;
2490 2480 #endif
2491 2481
2492 2482 csp = (struct copyresp *)mp->b_rptr;
2493 2483 stp = (struct ecpp_copystate *)csp->cp_private->b_rptr;
2494 2484 ip = (struct prn_interface_info *)mp->b_cont->b_rptr;
2495 2485
2496 2486 #ifdef _MULTI_DATAMODEL
2497 2487 if (IOC_CONVERT_FROM(iocbp) == IOC_ILP32) {
2498 2488 struct prn_interface_info32 *ip32;
2499 2489
2500 2490 ip32 = (struct prn_interface_info32 *)ip;
2501 2491 info.if_len = ip32->if_len;
2502 2492 info.if_data = (char *)(uintptr_t)ip32->if_data;
2503 2493 } else {
2504 2494 #endif /* _MULTI_DATAMODEL */
2505 2495 info = *ip;
2506 2496 #ifdef _MULTI_DATAMODEL
2507 2497 }
2508 2498 #endif /* _MULTI_DATAMODEL */
2509 2499
2510 2500 len = strlen(prn_ifinfo);
2511 2501 stp->un.prn_if.if_rlen = len;
2512 2502 stp->state = ECPP_ADDROUT;
2513 2503
2514 2504 /* check arguments */
2515 2505 if ((info.if_data == NULL) && (info.if_len != 0)) {
2516 2506 ecpp_nack_ioctl(q, mp, EFAULT);
2517 2507 return;
2518 2508 }
2519 2509
2520 2510 if (info.if_len == 0) {
2521 2511 /* just copyout rlen */
2522 2512 ecpp_wput_iocdata_devid(q, mp,
2523 2513 offsetof(struct prn_interface_info, if_rlen));
2524 2514 return;
2525 2515 }
2526 2516
2527 2517 /* if needed, trim to the buffer size */
2528 2518 if (len > info.if_len) {
2529 2519 len = info.if_len;
2530 2520 }
2531 2521
2532 2522 if ((datamp = allocb(len, BPRI_MED)) == NULL) {
2533 2523 ecpp_nack_ioctl(q, mp, ENOSR);
2534 2524 return;
2535 2525 }
2536 2526
2537 2527 bcopy(&prn_ifinfo[0], datamp->b_wptr, len);
2538 2528 datamp->b_wptr += len;
2539 2529
2540 2530 mcopyout(mp, csp->cp_private, len, info.if_data, datamp);
2541 2531 qreply(q, mp);
2542 2532 }
2543 2533
2544 2534 static void
2545 2535 ecpp_flush(struct ecppunit *pp, int cmd)
2546 2536 {
2547 2537 queue_t *q;
2548 2538 uint8_t ecr, dcr;
2549 2539 timeout_id_t timeout_id, fifo_timer_id, wsrv_timer_id;
2550 2540
2551 2541 ASSERT(mutex_owned(&pp->umutex));
2552 2542
2553 2543 if (!(cmd & FWRITE)) {
2554 2544 return;
2555 2545 }
2556 2546
2557 2547 q = pp->writeq;
2558 2548 timeout_id = fifo_timer_id = wsrv_timer_id = 0;
2559 2549
2560 2550 ecpp_error(pp->dip, "ecpp_flush e_busy=%x\n", pp->e_busy);
2561 2551
2562 2552 /* if there is an ongoing DMA, it needs to be turned off. */
2563 2553 switch (pp->e_busy) {
2564 2554 case ECPP_BUSY:
2565 2555 /*
2566 2556 * Change the port status to ECPP_FLUSH to
2567 2557 * indicate to ecpp_wsrv that the wq is being flushed.
2568 2558 */
2569 2559 pp->e_busy = ECPP_FLUSH;
2570 2560
2571 2561 /*
2572 2562 * dma_cancelled indicates to ecpp_isr() that we have
2573 2563 * turned off the DMA. Since the mutex is held, ecpp_isr()
2574 2564 * may be blocked. Once ecpp_flush() finishes and ecpp_isr()
2575 2565 * gains the mutex, ecpp_isr() will have a _reset_ DMAC. Most
2576 2566 * significantly, the DMAC will be reset after ecpp_isr() was
2577 2567 * invoked. Therefore we need to have a flag "dma_cancelled"
2578 2568 * to signify when the described condition has occured. If
2579 2569 * ecpp_isr() notes a dma_cancelled, it will ignore the DMAC csr
2580 2570 * and simply claim the interupt.
2581 2571 */
2582 2572
2583 2573 pp->dma_cancelled = TRUE;
2584 2574
2585 2575 /* either DMA or PIO transfer */
2586 2576 if (COMPAT_DMA(pp) ||
2587 2577 (pp->current_mode == ECPP_ECP_MODE) ||
2588 2578 (pp->current_mode == ECPP_DIAG_MODE)) {
2589 2579 /*
2590 2580 * if the bcr is zero, then DMA is complete and
2591 2581 * we are waiting for the fifo to drain. Therefore,
2592 2582 * turn off dma.
2593 2583 */
2594 2584 if (ECPP_DMA_STOP(pp, NULL) == FAILURE) {
2595 2585 ecpp_error(pp->dip,
2596 2586 "ecpp_flush: dma_stop failed.\n");
2597 2587 }
2598 2588
2599 2589 /*
2600 2590 * If the status of the port is ECPP_BUSY,
2601 2591 * the DMA is stopped by either explicitly above, or by
2602 2592 * ecpp_isr() but the FIFO hasn't drained yet. In either
2603 2593 * case, we need to unbind the dma mappings.
2604 2594 */
2605 2595 if (ddi_dma_unbind_handle(
2606 2596 pp->dma_handle) != DDI_SUCCESS)
2607 2597 ecpp_error(pp->dip,
2608 2598 "ecpp_flush: unbind failed.\n");
2609 2599
2610 2600 if (pp->msg != NULL) {
2611 2601 freemsg(pp->msg);
2612 2602 pp->msg = NULL;
2613 2603 }
2614 2604 } else {
2615 2605 /*
2616 2606 * PIO transfer: disable nAck interrups
2617 2607 */
2618 2608 dcr = DCR_READ(pp);
2619 2609 dcr &= ~(ECPP_REV_DIR | ECPP_INTR_EN);
2620 2610 DCR_WRITE(pp, dcr);
2621 2611 ECPP_MASK_INTR(pp);
2622 2612 }
2623 2613
2624 2614 /*
2625 2615 * The transfer is cleaned up. There may or may not be data
2626 2616 * in the fifo. We don't care at this point. Ie. SuperIO may
2627 2617 * transfer the remaining bytes in the fifo or not. it doesn't
2628 2618 * matter. All that is important at this stage is that no more
2629 2619 * fifo timers are started.
2630 2620 */
2631 2621
2632 2622 timeout_id = pp->timeout_id;
2633 2623 fifo_timer_id = pp->fifo_timer_id;
2634 2624 pp->timeout_id = pp->fifo_timer_id = 0;
2635 2625 pp->softintr_pending = 0;
2636 2626
2637 2627 break;
2638 2628
2639 2629 case ECPP_ERR:
2640 2630 /*
2641 2631 * Change the port status to ECPP_FLUSH to
2642 2632 * indicate to ecpp_wsrv that the wq is being flushed.
2643 2633 */
2644 2634 pp->e_busy = ECPP_FLUSH;
2645 2635
2646 2636 /*
2647 2637 * Most likely there are mblks in the queue,
2648 2638 * but the driver can not transmit because
2649 2639 * of the bad port status. In this case,
2650 2640 * ecpp_flush() should make sure ecpp_wsrv_timer()
2651 2641 * is turned off.
2652 2642 */
2653 2643 wsrv_timer_id = pp->wsrv_timer_id;
2654 2644 pp->wsrv_timer_id = 0;
2655 2645
2656 2646 break;
2657 2647
2658 2648 case ECPP_IDLE:
2659 2649 /* No work to do. Ready to flush */
2660 2650 break;
2661 2651
2662 2652 default:
2663 2653 ecpp_error(pp->dip,
2664 2654 "ecpp_flush: illegal state %x\n", pp->e_busy);
2665 2655 }
2666 2656
2667 2657 /* in DIAG mode clear TFIFO if needed */
2668 2658 if (pp->current_mode == ECPP_DIAG_MODE) {
2669 2659 ecr = ECR_READ(pp);
2670 2660 if (!(ecr & ECPP_FIFO_EMPTY)) {
2671 2661 ECR_WRITE(pp,
2672 2662 ECPP_INTR_SRV | ECPP_INTR_MASK | ECR_mode_001);
2673 2663 ECR_WRITE(pp, ecr);
2674 2664 }
2675 2665 }
2676 2666
2677 2667 /* Discard all messages on the output queue. */
2678 2668 flushq(q, FLUSHDATA);
2679 2669
2680 2670 /* The port is no longer flushing or dma'ing for that matter. */
2681 2671 pp->e_busy = ECPP_IDLE;
2682 2672
2683 2673 /* Set the right phase */
2684 2674 if (pp->current_mode == ECPP_ECP_MODE) {
2685 2675 if (pp->current_phase == ECPP_PHASE_ECP_REV_XFER) {
2686 2676 pp->current_phase = ECPP_PHASE_ECP_REV_IDLE;
2687 2677 } else {
2688 2678 pp->current_phase = ECPP_PHASE_ECP_FWD_IDLE;
2689 2679 }
2690 2680 }
2691 2681
2692 2682 /* cancel timeouts if any */
2693 2683 mutex_exit(&pp->umutex);
2694 2684
2695 2685 if (timeout_id) {
2696 2686 (void) untimeout(timeout_id);
2697 2687 }
2698 2688 if (fifo_timer_id) {
2699 2689 (void) untimeout(fifo_timer_id);
2700 2690 }
2701 2691 if (wsrv_timer_id) {
2702 2692 (void) untimeout(wsrv_timer_id);
2703 2693 }
2704 2694
2705 2695 mutex_enter(&pp->umutex);
2706 2696
2707 2697 cv_signal(&pp->pport_cv); /* wake up ecpp_close() */
2708 2698 }
2709 2699
2710 2700 static void
2711 2701 ecpp_start(struct ecppunit *pp, caddr_t addr, size_t len)
2712 2702 {
2713 2703 ASSERT(mutex_owned(&pp->umutex));
2714 2704 ASSERT(pp->e_busy == ECPP_BUSY);
2715 2705
2716 2706 ecpp_error(pp->dip,
2717 2707 "ecpp_start:current_mode=%x,current_phase=%x,ecr=%x,len=%d\n",
2718 2708 pp->current_mode, pp->current_phase, ECR_READ(pp), len);
2719 2709
2720 2710 pp->dma_dir = DDI_DMA_WRITE; /* this is a forward transfer */
2721 2711
2722 2712 switch (pp->current_mode) {
2723 2713 case ECPP_NIBBLE_MODE:
2724 2714 (void) ecpp_1284_termination(pp);
2725 2715
2726 2716 /* After termination we are either Compatible or Centronics */
2727 2717
2728 2718 /* FALLTHRU */
2729 2719
2730 2720 case ECPP_CENTRONICS:
2731 2721 case ECPP_COMPAT_MODE:
2732 2722 if (pp->io_mode == ECPP_DMA) {
2733 2723 if (ecpp_init_dma_xfer(pp, addr, len) == FAILURE) {
2734 2724 return;
2735 2725 }
2736 2726 } else {
2737 2727 /* PIO mode */
2738 2728 if (ecpp_prep_pio_xfer(pp, addr, len) == FAILURE) {
2739 2729 return;
2740 2730 }
2741 2731 (void) ecpp_pio_writeb(pp);
2742 2732 }
2743 2733 break;
2744 2734
2745 2735 case ECPP_DIAG_MODE: {
2746 2736 int oldlen;
2747 2737
2748 2738 /* put superio into TFIFO mode, if not already */
2749 2739 ECR_WRITE(pp, ECPP_INTR_SRV | ECPP_INTR_MASK | ECR_mode_110);
2750 2740 /*
2751 2741 * DMA would block if the TFIFO is not empty
2752 2742 * if by this moment nobody read these bytes, they`re gone
2753 2743 */
2754 2744 drv_usecwait(1);
2755 2745 if (!(ECR_READ(pp) & ECPP_FIFO_EMPTY)) {
2756 2746 ecpp_error(pp->dip,
2757 2747 "ecpp_start: TFIFO not empty, clearing\n");
2758 2748 ECR_WRITE(pp,
2759 2749 ECPP_INTR_SRV | ECPP_INTR_MASK | ECR_mode_001);
2760 2750 ECR_WRITE(pp,
2761 2751 ECPP_INTR_SRV | ECPP_INTR_MASK | ECR_mode_110);
2762 2752 }
2763 2753
2764 2754 /* we can DMA at most 16 bytes into TFIFO */
2765 2755 oldlen = len;
2766 2756 if (len > ECPP_FIFO_SZ) {
2767 2757 len = ECPP_FIFO_SZ;
2768 2758 }
2769 2759
2770 2760 if (ecpp_init_dma_xfer(pp, addr, len) == FAILURE) {
2771 2761 return;
2772 2762 }
2773 2763
2774 2764 /* put the rest of data back on the queue */
2775 2765 if (oldlen > len) {
2776 2766 ecpp_putback_untransfered(pp, addr + len, oldlen - len);
2777 2767 }
2778 2768
2779 2769 break;
2780 2770 }
2781 2771
2782 2772 case ECPP_ECP_MODE:
2783 2773 ASSERT(pp->current_phase == ECPP_PHASE_ECP_FWD_IDLE ||
2784 2774 pp->current_phase == ECPP_PHASE_ECP_REV_IDLE);
2785 2775
2786 2776 /* if in Reverse Phase negotiate to Forward */
2787 2777 if (pp->current_phase == ECPP_PHASE_ECP_REV_IDLE) {
2788 2778 if (ecp_reverse2forward(pp) == FAILURE) {
2789 2779 if (pp->msg) {
2790 2780 (void) putbq(pp->writeq, pp->msg);
2791 2781 } else {
2792 2782 ecpp_putback_untransfered(pp,
2793 2783 addr, len);
2794 2784 }
2795 2785 }
2796 2786 }
2797 2787
2798 2788 if (ecpp_init_dma_xfer(pp, addr, len) == FAILURE) {
2799 2789 return;
2800 2790 }
2801 2791
2802 2792 break;
2803 2793 }
2804 2794
2805 2795 /* schedule transfer timeout */
2806 2796 pp->timeout_id = timeout(ecpp_xfer_timeout, (caddr_t)pp,
2807 2797 pp->xfer_parms.write_timeout * drv_usectohz(1000000));
2808 2798 }
2809 2799
2810 2800 /*
2811 2801 * Transfer a PIO "block" a byte at a time.
2812 2802 * The block is starts at addr and ends at pp->last_byte
2813 2803 */
2814 2804 static uint8_t
2815 2805 ecpp_prep_pio_xfer(struct ecppunit *pp, caddr_t addr, size_t len)
2816 2806 {
2817 2807 pp->next_byte = addr;
2818 2808 pp->last_byte = (caddr_t)((ulong_t)addr + len);
2819 2809
2820 2810 if (ecpp_check_status(pp) == FAILURE) {
2821 2811 /*
2822 2812 * if status signals are bad, do not start PIO,
2823 2813 * put everything back on the queue.
2824 2814 */
2825 2815 ecpp_error(pp->dip,
2826 2816 "ecpp_prep_pio_xfer:suspend PIO len=%d\n", len);
2827 2817
2828 2818 if (pp->msg != NULL) {
2829 2819 /*
2830 2820 * this circumstance we want to copy the
2831 2821 * untransfered section of msg to a new mblk,
2832 2822 * then free the orignal one.
2833 2823 */
2834 2824 ecpp_putback_untransfered(pp,
2835 2825 (void *)pp->msg->b_rptr, len);
2836 2826 ecpp_error(pp->dip,
2837 2827 "ecpp_prep_pio_xfer: len1=%d\n", len);
2838 2828
2839 2829 freemsg(pp->msg);
2840 2830 pp->msg = NULL;
2841 2831 } else {
2842 2832 ecpp_putback_untransfered(pp, pp->ioblock, len);
2843 2833 ecpp_error(pp->dip,
2844 2834 "ecpp_prep_pio_xfer: len2=%d\n", len);
2845 2835 }
2846 2836 qenable(pp->writeq);
2847 2837
2848 2838 return (FAILURE);
2849 2839 }
2850 2840
2851 2841 pp->dma_cancelled = FALSE;
2852 2842
2853 2843 /* pport must be in PIO mode */
2854 2844 if (ecr_write(pp, ECR_mode_001 |
2855 2845 ECPP_INTR_MASK | ECPP_INTR_SRV) != SUCCESS) {
2856 2846 ecpp_error(pp->dip, "ecpp_prep_pio_xfer: failed w/ECR.\n");
2857 2847 }
2858 2848
2859 2849 ecpp_error(pp->dip, "ecpp_prep_pio_xfer: dcr=%x ecr=%x\n",
2860 2850 DCR_READ(pp), ECR_READ(pp));
2861 2851
2862 2852 return (SUCCESS);
2863 2853 }
2864 2854
2865 2855 static uint8_t
2866 2856 ecpp_init_dma_xfer(struct ecppunit *pp, caddr_t addr, size_t len)
2867 2857 {
2868 2858 uint8_t ecr_mode[] = {
2869 2859 0,
2870 2860 ECR_mode_010, /* Centronix */
2871 2861 ECR_mode_010, /* Compat */
2872 2862 0, /* Byte */
2873 2863 0, /* Nibble */
2874 2864 ECR_mode_011, /* ECP */
2875 2865 0, /* Failure */
2876 2866 ECR_mode_110, /* Diag */
2877 2867 };
2878 2868 uint8_t ecr;
2879 2869
2880 2870 ASSERT((pp->current_mode <= ECPP_DIAG_MODE) &&
2881 2871 (ecr_mode[pp->current_mode] != 0));
2882 2872
2883 2873 if (ecpp_setup_dma_resources(pp, addr, len) == FAILURE) {
2884 2874 qenable(pp->writeq);
2885 2875 return (FAILURE);
2886 2876 }
2887 2877
2888 2878 if (ecpp_check_status(pp) == FAILURE) {
2889 2879 /*
2890 2880 * if status signals are bad, do not start DMA, but
2891 2881 * rather put everything back on the queue.
2892 2882 */
2893 2883 ecpp_error(pp->dip,
2894 2884 "ecpp_init_dma_xfer: suspending DMA len=%d\n",
2895 2885 pp->dma_cookie.dmac_size);
2896 2886
2897 2887 if (pp->msg != NULL) {
2898 2888 /*
2899 2889 * this circumstance we want to copy the
2900 2890 * untransfered section of msg to a new mblk,
2901 2891 * then free the orignal one.
2902 2892 */
2903 2893 ecpp_putback_untransfered(pp,
2904 2894 (void *)pp->msg->b_rptr, len);
2905 2895 ecpp_error(pp->dip,
2906 2896 "ecpp_init_dma_xfer:a:len=%d\n", len);
2907 2897
2908 2898 freemsg(pp->msg);
2909 2899 pp->msg = NULL;
2910 2900 } else {
2911 2901 ecpp_putback_untransfered(pp, pp->ioblock, len);
2912 2902 ecpp_error(pp->dip,
2913 2903 "ecpp_init_dma_xfer:b:len=%d\n", len);
2914 2904 }
2915 2905
2916 2906 if (ddi_dma_unbind_handle(pp->dma_handle) != DDI_SUCCESS) {
2917 2907 ecpp_error(pp->dip,
2918 2908 "ecpp_init_dma_xfer: unbind FAILURE.\n");
2919 2909 }
2920 2910 qenable(pp->writeq);
2921 2911 return (FAILURE);
2922 2912 }
2923 2913
2924 2914 pp->xfercnt = pp->resid = len;
2925 2915 pp->dma_cancelled = FALSE;
2926 2916 pp->tfifo_intr = 0;
2927 2917
2928 2918 /* set the right ECR mode and disable DMA */
2929 2919 ecr = ecr_mode[pp->current_mode];
2930 2920 (void) ecr_write(pp, ecr | ECPP_INTR_SRV | ECPP_INTR_MASK);
2931 2921
2932 2922 /* prepare DMAC for a transfer */
2933 2923 if (ECPP_DMA_START(pp) == FAILURE) {
2934 2924 ecpp_error(pp->dip, "ecpp_init_dma_xfer: dma_start FAILED.\n");
2935 2925 return (FAILURE);
2936 2926 }
2937 2927
2938 2928 /* GO! */
2939 2929 (void) ecr_write(pp, ecr | ECPP_DMA_ENABLE | ECPP_INTR_MASK);
2940 2930
2941 2931 return (SUCCESS);
2942 2932 }
2943 2933
2944 2934 static uint8_t
2945 2935 ecpp_setup_dma_resources(struct ecppunit *pp, caddr_t addr, size_t len)
2946 2936 {
2947 2937 int err;
2948 2938 off_t woff;
2949 2939 size_t wlen;
2950 2940
2951 2941 ASSERT(pp->dma_dir == DDI_DMA_READ || pp->dma_dir == DDI_DMA_WRITE);
2952 2942
2953 2943 err = ddi_dma_addr_bind_handle(pp->dma_handle, NULL,
2954 2944 addr, len, pp->dma_dir | DDI_DMA_PARTIAL,
2955 2945 DDI_DMA_DONTWAIT, NULL,
2956 2946 &pp->dma_cookie, &pp->dma_cookie_count);
2957 2947
2958 2948 switch (err) {
2959 2949 case DDI_DMA_MAPPED:
2960 2950 ecpp_error(pp->dip, "ecpp_setup_dma: DMA_MAPPED\n");
2961 2951
2962 2952 pp->dma_nwin = 1;
2963 2953 pp->dma_curwin = 1;
2964 2954 break;
2965 2955
2966 2956 case DDI_DMA_PARTIAL_MAP: {
2967 2957 ecpp_error(pp->dip, "ecpp_setup_dma: DMA_PARTIAL_MAP\n");
2968 2958
2969 2959 if (ddi_dma_numwin(pp->dma_handle,
2970 2960 &pp->dma_nwin) != DDI_SUCCESS) {
2971 2961 (void) ddi_dma_unbind_handle(pp->dma_handle);
2972 2962 return (FAILURE);
2973 2963 }
2974 2964 pp->dma_curwin = 1;
2975 2965
2976 2966 /*
2977 2967 * The very first window is returned by bind_handle,
2978 2968 * but we must do this explicitly here, otherwise
2979 2969 * next getwin would return wrong cookie dmac_size
2980 2970 */
2981 2971 if (ddi_dma_getwin(pp->dma_handle, 0, &woff, &wlen,
2982 2972 &pp->dma_cookie, &pp->dma_cookie_count) != DDI_SUCCESS) {
2983 2973 ecpp_error(pp->dip,
2984 2974 "ecpp_setup_dma: ddi_dma_getwin failed!");
2985 2975 (void) ddi_dma_unbind_handle(pp->dma_handle);
2986 2976 return (FAILURE);
2987 2977 }
2988 2978
2989 2979 ecpp_error(pp->dip,
2990 2980 "ecpp_setup_dma: cookies=%d, windows=%d"
2991 2981 " addr=%lx len=%d\n",
2992 2982 pp->dma_cookie_count, pp->dma_nwin,
2993 2983 pp->dma_cookie.dmac_address, pp->dma_cookie.dmac_size);
2994 2984
2995 2985 break;
2996 2986 }
2997 2987
2998 2988 default:
2999 2989 ecpp_error(pp->dip, "ecpp_setup_dma: err=%x\n", err);
3000 2990 return (FAILURE);
3001 2991 }
3002 2992
3003 2993 return (SUCCESS);
3004 2994 }
3005 2995
3006 2996 static void
3007 2997 ecpp_ack_ioctl(queue_t *q, mblk_t *mp)
3008 2998 {
3009 2999 struct iocblk *iocbp;
3010 3000
3011 3001 mp->b_datap->db_type = M_IOCACK;
3012 3002 mp->b_wptr = mp->b_rptr + sizeof (struct iocblk);
3013 3003
3014 3004 if (mp->b_cont) {
3015 3005 freemsg(mp->b_cont);
3016 3006 mp->b_cont = NULL;
3017 3007 }
3018 3008
3019 3009 iocbp = (struct iocblk *)mp->b_rptr;
3020 3010 iocbp->ioc_error = 0;
3021 3011 iocbp->ioc_count = 0;
3022 3012 iocbp->ioc_rval = 0;
3023 3013
3024 3014 qreply(q, mp);
3025 3015 }
3026 3016
3027 3017 static void
3028 3018 ecpp_nack_ioctl(queue_t *q, mblk_t *mp, int err)
3029 3019 {
3030 3020 struct iocblk *iocbp;
3031 3021
3032 3022 mp->b_datap->db_type = M_IOCNAK;
3033 3023 mp->b_wptr = mp->b_rptr + sizeof (struct iocblk);
3034 3024 iocbp = (struct iocblk *)mp->b_rptr;
3035 3025 iocbp->ioc_error = err;
3036 3026
3037 3027 if (mp->b_cont) {
3038 3028 freemsg(mp->b_cont);
3039 3029 mp->b_cont = NULL;
3040 3030 }
3041 3031
3042 3032 qreply(q, mp);
3043 3033 }
3044 3034
3045 3035 uint_t
3046 3036 ecpp_isr(caddr_t arg)
3047 3037 {
3048 3038 struct ecppunit *pp = (struct ecppunit *)(void *)arg;
3049 3039 uint32_t dcsr;
3050 3040 uint8_t dsr;
3051 3041 int cheerio_pend_counter;
3052 3042 int retval = DDI_INTR_UNCLAIMED;
3053 3043 hrtime_t now;
3054 3044
3055 3045 mutex_enter(&pp->umutex);
3056 3046 /*
3057 3047 * interrupt may occur while other thread is holding the lock
3058 3048 * and cancels DMA transfer (e.g. ecpp_flush())
3059 3049 * since it cannot cancel the interrupt thread,
3060 3050 * it just sets dma_cancelled to TRUE,
3061 3051 * telling interrupt handler to exit immediately
3062 3052 */
3063 3053 if (pp->dma_cancelled == TRUE) {
3064 3054 ecpp_error(pp->dip, "dma-cancel isr\n");
3065 3055
3066 3056 pp->intr_hard++;
3067 3057 pp->dma_cancelled = FALSE;
3068 3058
3069 3059 mutex_exit(&pp->umutex);
3070 3060 return (DDI_INTR_CLAIMED);
3071 3061 }
3072 3062
3073 3063 /* Southbridge interrupts are handled separately */
3074 3064 #if defined(__x86)
3075 3065 if (pp->hw == &x86)
3076 3066 #else
3077 3067 if (pp->hw == &m1553)
3078 3068 #endif
3079 3069 {
3080 3070 retval = ecpp_M1553_intr(pp);
3081 3071 if (retval == DDI_INTR_UNCLAIMED) {
3082 3072 goto unexpected;
3083 3073 }
3084 3074 mutex_exit(&pp->umutex);
3085 3075 return (DDI_INTR_CLAIMED);
3086 3076 }
3087 3077
3088 3078 /*
3089 3079 * the intr is through the motherboard. it is faster than PCI route.
3090 3080 * sometimes ecpp_isr() is invoked before cheerio csr is updated.
3091 3081 */
3092 3082 cheerio_pend_counter = ecpp_isr_max_delay;
3093 3083 dcsr = GET_DMAC_CSR(pp);
3094 3084
3095 3085 while (!(dcsr & DCSR_INT_PEND) && cheerio_pend_counter-- > 0) {
3096 3086 drv_usecwait(1);
3097 3087 dcsr = GET_DMAC_CSR(pp);
3098 3088 }
3099 3089
3100 3090 /*
3101 3091 * This is a workaround for what seems to be a timing problem
3102 3092 * with the delivery of interrupts and CSR updating with the
3103 3093 * ebus2 csr, superio and the n_ERR pin from the peripheral.
3104 3094 *
3105 3095 * delay is not needed for PIO mode
3106 3096 */
3107 3097 if (!COMPAT_PIO(pp)) {
3108 3098 drv_usecwait(100);
3109 3099 dcsr = GET_DMAC_CSR(pp);
3110 3100 }
3111 3101
3112 3102 /* on 97317 in Extended mode IRQ_ST of DSR is deasserted when read */
3113 3103 dsr = DSR_READ(pp);
3114 3104
3115 3105 /*
3116 3106 * check if interrupt is for this device:
3117 3107 * it should be reflected either in cheerio DCSR register
3118 3108 * or in IRQ_ST bit of DSR on 97317
3119 3109 */
3120 3110 if ((dcsr & DCSR_INT_PEND) == 0) {
3121 3111 if (pp->hw != &pc97317) {
3122 3112 goto unclaimed;
3123 3113 }
3124 3114 /*
3125 3115 * on Excalibur, reading DSR will deassert SuperIO IRQx line
3126 3116 * RIO's DCSR_INT_PEND seems to follow IRQx transitions,
3127 3117 * so if DSR is read after interrupt occured, but before
3128 3118 * we get here, IRQx and hence INT_PEND will be deasserted
3129 3119 * as a result, we can miss a service interrupt in PIO mode
3130 3120 *
3131 3121 * malicious DSR reader is BPPIOC_TESTIO, which is called
3132 3122 * by LP in between data blocks to check printer status
3133 3123 * this workaround lets us not to miss an interrupt
3134 3124 *
3135 3125 * also, nErr interrupt (ECP mode) not always reflected in DCSR
3136 3126 */
3137 3127 if (((dsr & ECPP_IRQ_ST) == 0) ||
3138 3128 ((COMPAT_PIO(pp)) && (pp->e_busy == ECPP_BUSY)) ||
3139 3129 (((dsr & ECPP_nERR) == 0) &&
3140 3130 (pp->current_mode == ECPP_ECP_MODE))) {
3141 3131 dcsr = 0;
3142 3132 } else {
3143 3133 goto unclaimed;
3144 3134 }
3145 3135 }
3146 3136
3147 3137 pp->intr_hard++;
3148 3138
3149 3139 /* the intr is for us - check all possible interrupt sources */
3150 3140 if (dcsr & DCSR_ERR_PEND) {
3151 3141 size_t bcr;
3152 3142
3153 3143 /* we are expecting a data transfer interrupt */
3154 3144 ASSERT(pp->e_busy == ECPP_BUSY);
3155 3145
3156 3146 /*
3157 3147 * some kind of DMA error
3158 3148 */
3159 3149 if (ECPP_DMA_STOP(pp, &bcr) == FAILURE) {
3160 3150 ecpp_error(pp->dip, "ecpp_isr: dma_stop failed\n");
3161 3151 }
3162 3152
3163 3153 ecpp_error(pp->dip, "ecpp_isr: DMAC ERROR bcr=%d\n", bcr);
3164 3154
3165 3155 ecpp_xfer_cleanup(pp);
3166 3156
3167 3157 if (ddi_dma_unbind_handle(pp->dma_handle) != DDI_SUCCESS) {
3168 3158 ecpp_error(pp->dip, "ecpp_isr(e): unbind failed\n");
3169 3159 }
3170 3160
3171 3161 mutex_exit(&pp->umutex);
3172 3162 return (DDI_INTR_CLAIMED);
3173 3163 }
3174 3164
3175 3165 if (dcsr & DCSR_TC) {
3176 3166 retval = ecpp_dma_ihdlr(pp);
3177 3167 mutex_exit(&pp->umutex);
3178 3168 return (DDI_INTR_CLAIMED);
3179 3169 }
3180 3170
3181 3171 if (COMPAT_PIO(pp)) {
3182 3172 retval = ecpp_pio_ihdlr(pp);
3183 3173 mutex_exit(&pp->umutex);
3184 3174 return (DDI_INTR_CLAIMED);
3185 3175 }
3186 3176
3187 3177 /* does peripheral need attention? */
3188 3178 if ((dsr & ECPP_nERR) == 0) {
3189 3179 retval = ecpp_nErr_ihdlr(pp);
3190 3180 mutex_exit(&pp->umutex);
3191 3181 return (DDI_INTR_CLAIMED);
3192 3182 }
3193 3183
3194 3184 pp->intr_hard--;
3195 3185
3196 3186 unexpected:
3197 3187
3198 3188 pp->intr_spurious++;
3199 3189
3200 3190 /*
3201 3191 * The following procedure tries to prevent soft hangs
3202 3192 * in event of peripheral/superio misbehaviour:
3203 3193 * if number of unexpected interrupts in the last SPUR_PERIOD ns
3204 3194 * exceeded SPUR_CRITICAL, then shut up interrupts
3205 3195 */
3206 3196 now = gethrtime();
3207 3197 if (pp->lastspur == 0 || now - pp->lastspur > SPUR_PERIOD) {
3208 3198 /* last unexpected interrupt was long ago */
3209 3199 pp->lastspur = now;
3210 3200 pp->nspur = 1;
3211 3201 } else {
3212 3202 /* last unexpected interrupt was recently */
3213 3203 pp->nspur++;
3214 3204 }
3215 3205
3216 3206 if (pp->nspur >= SPUR_CRITICAL) {
3217 3207 ECPP_MASK_INTR(pp);
3218 3208 ECR_WRITE(pp, ECR_READ(pp) | ECPP_INTR_MASK | ECPP_INTR_SRV);
3219 3209 pp->nspur = 0;
3220 3210 cmn_err(CE_NOTE, "%s%d: too many interrupt requests",
3221 3211 ddi_get_name(pp->dip), ddi_get_instance(pp->dip));
3222 3212 } else {
3223 3213 ECR_WRITE(pp, ECR_READ(pp) | ECPP_INTR_SRV | ECPP_INTR_MASK);
3224 3214 }
3225 3215
3226 3216 ecpp_error(pp->dip,
3227 3217 "isr:unknown: dcsr=%x ecr=%x dsr=%x dcr=%x\nmode=%x phase=%x\n",
3228 3218 dcsr, ECR_READ(pp), dsr, DCR_READ(pp),
3229 3219 pp->current_mode, pp->current_phase);
3230 3220
3231 3221 mutex_exit(&pp->umutex);
3232 3222 return (DDI_INTR_CLAIMED);
3233 3223
3234 3224 unclaimed:
3235 3225
3236 3226 pp->intr_spurious++;
3237 3227
3238 3228 ecpp_error(pp->dip,
3239 3229 "isr:UNCL: dcsr=%x ecr=%x dsr=%x dcr=%x\nmode=%x phase=%x\n",
3240 3230 dcsr, ECR_READ(pp), DSR_READ(pp), DCR_READ(pp),
3241 3231 pp->current_mode, pp->current_phase);
3242 3232
3243 3233 mutex_exit(&pp->umutex);
3244 3234 return (DDI_INTR_UNCLAIMED);
3245 3235 }
3246 3236
3247 3237 /*
3248 3238 * M1553 intr handler
3249 3239 */
3250 3240 static uint_t
3251 3241 ecpp_M1553_intr(struct ecppunit *pp)
3252 3242 {
3253 3243 int retval = DDI_INTR_UNCLAIMED;
3254 3244
3255 3245 pp->intr_hard++;
3256 3246
3257 3247 if (pp->e_busy == ECPP_BUSY) {
3258 3248 /* Centronics or Compat PIO transfer */
3259 3249 if (COMPAT_PIO(pp)) {
3260 3250 return (ecpp_pio_ihdlr(pp));
3261 3251 }
3262 3252
3263 3253 /* Centronics or Compat DMA transfer */
3264 3254 if (COMPAT_DMA(pp) ||
3265 3255 (pp->current_mode == ECPP_ECP_MODE) ||
3266 3256 (pp->current_mode == ECPP_DIAG_MODE)) {
3267 3257 return (ecpp_dma_ihdlr(pp));
3268 3258 }
3269 3259 }
3270 3260
3271 3261 /* Nibble or ECP backchannel request? */
3272 3262 if ((DSR_READ(pp) & ECPP_nERR) == 0) {
3273 3263 return (ecpp_nErr_ihdlr(pp));
3274 3264 }
3275 3265
3276 3266 return (retval);
3277 3267 }
3278 3268
3279 3269 /*
3280 3270 * DMA completion interrupt handler
3281 3271 */
3282 3272 static uint_t
3283 3273 ecpp_dma_ihdlr(struct ecppunit *pp)
3284 3274 {
3285 3275 clock_t tm;
3286 3276
3287 3277 ecpp_error(pp->dip, "ecpp_dma_ihdlr(%x): ecr=%x, dsr=%x, dcr=%x\n",
3288 3278 pp->current_mode, ECR_READ(pp), DSR_READ(pp), DCR_READ(pp));
3289 3279
3290 3280 /* we are expecting a data transfer interrupt */
3291 3281 ASSERT(pp->e_busy == ECPP_BUSY);
3292 3282
3293 3283 /* Intr generated while invoking TFIFO mode. Exit */
3294 3284 if (pp->tfifo_intr == 1) {
3295 3285 pp->tfifo_intr = 0;
3296 3286 ecpp_error(pp->dip, "ecpp_dma_ihdlr: tfifo_intr is 1\n");
3297 3287 return (DDI_INTR_CLAIMED);
3298 3288 }
3299 3289
3300 3290 if (ECPP_DMA_STOP(pp, NULL) == FAILURE) {
3301 3291 ecpp_error(pp->dip, "ecpp_dma_ihdlr: dma_stop failed\n");
3302 3292 }
3303 3293
3304 3294 if (pp->current_mode == ECPP_ECP_MODE &&
3305 3295 pp->current_phase == ECPP_PHASE_ECP_REV_XFER) {
3306 3296 ecpp_ecp_read_completion(pp);
3307 3297 } else {
3308 3298 /*
3309 3299 * fifo_timer() will do the cleanup when the FIFO drains
3310 3300 */
3311 3301 if ((ECR_READ(pp) & ECPP_FIFO_EMPTY) ||
3312 3302 (pp->current_mode == ECPP_DIAG_MODE)) {
3313 3303 tm = 0; /* no use in waiting if FIFO is already empty */
3314 3304 } else {
3315 3305 tm = drv_usectohz(FIFO_DRAIN_PERIOD);
3316 3306 }
3317 3307 pp->fifo_timer_id = timeout(ecpp_fifo_timer, (caddr_t)pp, tm);
3318 3308 }
3319 3309
3320 3310 /*
3321 3311 * Stop the DMA transfer timeout timer
3322 3312 * this operation will temporarily give up the mutex,
3323 3313 * so we do it in the end of the handler to avoid races
3324 3314 */
3325 3315 ecpp_untimeout_unblock(pp, &pp->timeout_id);
3326 3316
3327 3317 return (DDI_INTR_CLAIMED);
3328 3318 }
3329 3319
3330 3320 /*
3331 3321 * ecpp_pio_ihdlr() is a PIO interrupt processing routine
3332 3322 * It masks interrupts, updates statistics and initiates next byte transfer
3333 3323 */
3334 3324 static uint_t
3335 3325 ecpp_pio_ihdlr(struct ecppunit *pp)
3336 3326 {
3337 3327 ASSERT(mutex_owned(&pp->umutex));
3338 3328 ASSERT(pp->e_busy == ECPP_BUSY);
3339 3329
3340 3330 /* update statistics */
3341 3331 pp->joblen++;
3342 3332 pp->ctxpio_obytes++;
3343 3333
3344 3334 /* disable nAck interrups */
3345 3335 ECPP_MASK_INTR(pp);
3346 3336 DCR_WRITE(pp, DCR_READ(pp) & ~(ECPP_REV_DIR | ECPP_INTR_EN));
3347 3337
3348 3338 /*
3349 3339 * If it was the last byte of the data block cleanup,
3350 3340 * otherwise trigger a soft interrupt to send the next byte
3351 3341 */
3352 3342 if (pp->next_byte >= pp->last_byte) {
3353 3343 ecpp_xfer_cleanup(pp);
3354 3344 ecpp_error(pp->dip,
3355 3345 "ecpp_pio_ihdlr: pp->joblen=%d,pp->ctx_cf=%d,\n",
3356 3346 pp->joblen, pp->ctx_cf);
3357 3347 } else {
3358 3348 if (pp->softintr_pending) {
3359 3349 ecpp_error(pp->dip,
3360 3350 "ecpp_pio_ihdlr:E: next byte in progress\n");
3361 3351 } else {
3362 3352 pp->softintr_flags = ECPP_SOFTINTR_PIONEXT;
3363 3353 pp->softintr_pending = 1;
3364 3354 ddi_trigger_softintr(pp->softintr_id);
3365 3355 }
3366 3356 }
3367 3357
3368 3358 return (DDI_INTR_CLAIMED);
3369 3359 }
3370 3360
3371 3361 /*
3372 3362 * ecpp_pio_writeb() sends a byte using Centronics handshake
3373 3363 */
3374 3364 static void
3375 3365 ecpp_pio_writeb(struct ecppunit *pp)
3376 3366 {
3377 3367 uint8_t dcr;
3378 3368
3379 3369 dcr = DCR_READ(pp) & ~ECPP_REV_DIR;
3380 3370 dcr |= ECPP_INTR_EN;
3381 3371
3382 3372 /* send the next byte */
3383 3373 DATAR_WRITE(pp, *(pp->next_byte++));
3384 3374
3385 3375 drv_usecwait(pp->data_setup_time);
3386 3376
3387 3377 /* Now Assert (neg logic) nStrobe */
3388 3378 if (dcr_write(pp, dcr | ECPP_STB) == FAILURE) {
3389 3379 ecpp_error(pp->dip, "ecpp_pio_writeb:1: failed w/DCR\n");
3390 3380 }
3391 3381
3392 3382 /* Enable nAck interrupts */
3393 3383 (void) DSR_READ(pp); /* ensure IRQ_ST is armed */
3394 3384 ECPP_UNMASK_INTR(pp);
3395 3385
3396 3386 drv_usecwait(pp->strobe_pulse_width);
3397 3387
3398 3388 if (dcr_write(pp, dcr & ~ECPP_STB) == FAILURE) {
3399 3389 ecpp_error(pp->dip, "ecpp_pio_writeb:2: failed w/DCR\n");
3400 3390 }
3401 3391 }
3402 3392
3403 3393 /*
3404 3394 * Backchannel request interrupt handler
3405 3395 */
3406 3396 static uint_t
3407 3397 ecpp_nErr_ihdlr(struct ecppunit *pp)
3408 3398 {
3409 3399 ecpp_error(pp->dip, "ecpp_nErr_ihdlr: mode=%x, phase=%x\n",
3410 3400 pp->current_mode, pp->current_phase);
3411 3401
3412 3402 if (pp->oflag != TRUE) {
3413 3403 ecpp_error(pp->dip, "ecpp_nErr_ihdlr: not open!\n");
3414 3404 return (DDI_INTR_UNCLAIMED);
3415 3405 }
3416 3406
3417 3407 if (pp->e_busy == ECPP_BUSY) {
3418 3408 ecpp_error(pp->dip, "ecpp_nErr_ihdlr: busy\n");
3419 3409 ECR_WRITE(pp, ECR_READ(pp) | ECPP_INTR_MASK);
3420 3410 return (DDI_INTR_CLAIMED);
3421 3411 }
3422 3412
3423 3413 /* mask nErr & nAck interrupts */
3424 3414 ECPP_MASK_INTR(pp);
3425 3415 DCR_WRITE(pp, DCR_READ(pp) & ~(ECPP_INTR_EN | ECPP_REV_DIR));
3426 3416 ECR_WRITE(pp, ECR_READ(pp) | ECPP_INTR_MASK);
3427 3417
3428 3418 /* going reverse */
3429 3419 switch (pp->current_mode) {
3430 3420 case ECPP_ECP_MODE:
3431 3421 /*
3432 3422 * Peripheral asserts nPeriphRequest (nFault)
3433 3423 */
3434 3424 break;
3435 3425 case ECPP_NIBBLE_MODE:
3436 3426 /*
3437 3427 * Event 18: Periph asserts nErr to indicate data avail
3438 3428 * Event 19: After waiting minimum pulse width,
3439 3429 * periph sets nAck high to generate an interrupt
3440 3430 *
3441 3431 * Interface is in Interrupt Phase
3442 3432 */
3443 3433 pp->current_phase = ECPP_PHASE_NIBT_REVINTR;
3444 3434
3445 3435 break;
3446 3436 default:
3447 3437 ecpp_error(pp->dip, "ecpp_nErr_ihdlr: wrong mode!\n");
3448 3438 return (DDI_INTR_UNCLAIMED);
3449 3439 }
3450 3440
3451 3441 (void) ecpp_backchan_req(pp); /* put backchannel request on the wq */
3452 3442
3453 3443 return (DDI_INTR_CLAIMED);
3454 3444 }
3455 3445
3456 3446 /*
3457 3447 * Softintr handler does work according to softintr_flags:
3458 3448 * in case of ECPP_SOFTINTR_PIONEXT it sends next byte of PIO transfer
3459 3449 */
3460 3450 static uint_t
3461 3451 ecpp_softintr(caddr_t arg)
3462 3452 {
3463 3453 struct ecppunit *pp = (struct ecppunit *)arg;
3464 3454 uint32_t unx_len, ecpp_reattempts = 0;
3465 3455
3466 3456 mutex_enter(&pp->umutex);
3467 3457
3468 3458 pp->intr_soft++;
3469 3459
3470 3460 if (!pp->softintr_pending) {
3471 3461 mutex_exit(&pp->umutex);
3472 3462 return (DDI_INTR_CLAIMED);
3473 3463 } else {
3474 3464 pp->softintr_pending = 0;
3475 3465 }
3476 3466
3477 3467 if (pp->softintr_flags & ECPP_SOFTINTR_PIONEXT) {
3478 3468 pp->softintr_flags &= ~ECPP_SOFTINTR_PIONEXT;
3479 3469 /*
3480 3470 * Sent next byte in PIO mode
3481 3471 */
3482 3472 ecpp_reattempts = 0;
3483 3473 do {
3484 3474 if (ecpp_check_status(pp) == SUCCESS) {
3485 3475 pp->e_busy = ECPP_BUSY;
3486 3476 break;
3487 3477 }
3488 3478 drv_usecwait(1);
3489 3479 if (pp->isr_reattempt_high < ecpp_reattempts) {
3490 3480 pp->isr_reattempt_high = ecpp_reattempts;
3491 3481 }
3492 3482 } while (++ecpp_reattempts < pp->wait_for_busy);
3493 3483
3494 3484 /* if the peripheral still not recovered suspend the transfer */
3495 3485 if (pp->e_busy == ECPP_ERR) {
3496 3486 ++pp->ctx_cf; /* check status fail */
3497 3487 ecpp_error(pp->dip, "ecpp_softintr:check_status:F: "
3498 3488 "dsr=%x jl=%d cf_isr=%d\n",
3499 3489 DSR_READ(pp), pp->joblen, pp->ctx_cf);
3500 3490
3501 3491 /*
3502 3492 * if status signals are bad,
3503 3493 * put everything back on the wq.
3504 3494 */
3505 3495 unx_len = pp->last_byte - pp->next_byte;
3506 3496 if (pp->msg != NULL) {
3507 3497 ecpp_putback_untransfered(pp,
3508 3498 (void *)pp->msg->b_rptr, unx_len);
3509 3499 ecpp_error(pp->dip,
3510 3500 "ecpp_softintr:e1:unx_len=%d\n", unx_len);
3511 3501
3512 3502 freemsg(pp->msg);
3513 3503 pp->msg = NULL;
3514 3504 } else {
3515 3505 ecpp_putback_untransfered(pp,
3516 3506 pp->next_byte, unx_len);
3517 3507 ecpp_error(pp->dip,
3518 3508 "ecpp_softintr:e2:unx_len=%d\n", unx_len);
3519 3509 }
3520 3510
3521 3511 ecpp_xfer_cleanup(pp);
3522 3512 pp->e_busy = ECPP_ERR;
3523 3513 qenable(pp->writeq);
3524 3514 } else {
3525 3515 /* send the next one */
3526 3516 pp->e_busy = ECPP_BUSY;
3527 3517 (void) ecpp_pio_writeb(pp);
3528 3518 }
3529 3519 }
3530 3520
3531 3521 mutex_exit(&pp->umutex);
3532 3522 return (DDI_INTR_CLAIMED);
3533 3523 }
3534 3524
3535 3525
3536 3526 /*
3537 3527 * Transfer clean-up:
3538 3528 * shut down the DMAC
3539 3529 * stop the transfer timer
3540 3530 * enable write queue
3541 3531 */
3542 3532 static void
3543 3533 ecpp_xfer_cleanup(struct ecppunit *pp)
3544 3534 {
3545 3535 ASSERT(mutex_owned(&pp->umutex));
3546 3536
3547 3537 /*
3548 3538 * if we did not use the ioblock, the mblk that
3549 3539 * was used should be freed.
3550 3540 */
3551 3541 if (pp->msg != NULL) {
3552 3542 freemsg(pp->msg);
3553 3543 pp->msg = NULL;
3554 3544 }
3555 3545
3556 3546 /* The port is no longer active */
3557 3547 pp->e_busy = ECPP_IDLE;
3558 3548
3559 3549 /* Stop the transfer timeout timer */
3560 3550 ecpp_untimeout_unblock(pp, &pp->timeout_id);
3561 3551
3562 3552 qenable(pp->writeq);
3563 3553 }
3564 3554
3565 3555 /*VARARGS*/
3566 3556 static void
3567 3557 ecpp_error(dev_info_t *dip, char *fmt, ...)
3568 3558 {
3569 3559 static long last;
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3570 3560 static char *lastfmt;
3571 3561 char msg_buffer[255];
3572 3562 va_list ap;
3573 3563 time_t now;
3574 3564
3575 3565 if (!ecpp_debug) {
3576 3566 return;
3577 3567 }
3578 3568
3579 3569 /*
3580 - * This function is supposed to be a quick non-blockable
3581 - * wrapper for cmn_err(9F), which provides a sensible degree
3582 - * of debug message throttling. Not using any type of lock
3583 - * is a requirement, but this also leaves two static variables
3584 - * - last and lastfmt - unprotected. However, this will not do
3585 - * any harm to driver functionality, it can only weaken throttling.
3586 - * The following directive asks warlock to not worry about these
3587 - * variables.
3588 - */
3589 - _NOTE(NOW_INVISIBLE_TO_OTHER_THREADS(last, lastfmt))
3590 -
3591 - /*
3592 3570 * Don't print same error message too often.
3593 3571 */
3594 3572 now = gethrestime_sec();
3595 3573 if ((last == (now & ~1)) && (lastfmt == fmt))
3596 3574 return;
3597 3575
3598 3576 last = now & ~1;
3599 3577 lastfmt = fmt;
3600 3578
3601 3579 va_start(ap, fmt);
3602 3580 (void) vsprintf(msg_buffer, fmt, ap);
3603 3581 cmn_err(CE_CONT, "%s%d: %s", ddi_get_name(dip),
3604 3582 ddi_get_instance(dip), msg_buffer);
3605 3583 va_end(ap);
3606 3584 }
3607 3585
3608 3586 /*
3609 3587 * Forward transfer timeout
3610 3588 */
3611 3589 static void
3612 3590 ecpp_xfer_timeout(void *arg)
3613 3591 {
3614 3592 struct ecppunit *pp = arg;
3615 3593 void *unx_addr;
3616 3594 size_t unx_len, xferd;
3617 3595 uint8_t dcr;
3618 3596 timeout_id_t fifo_timer_id;
3619 3597
3620 3598 mutex_enter(&pp->umutex);
3621 3599
3622 3600 if (pp->timeout_id == 0) {
3623 3601 mutex_exit(&pp->umutex);
3624 3602 return;
3625 3603 } else {
3626 3604 pp->timeout_id = 0;
3627 3605 }
3628 3606
3629 3607 pp->xfer_tout++;
3630 3608
3631 3609 pp->dma_cancelled = TRUE; /* prevent race with isr() */
3632 3610
3633 3611 if (COMPAT_PIO(pp)) {
3634 3612 /*
3635 3613 * PIO mode timeout
3636 3614 */
3637 3615
3638 3616 /* turn off nAck interrupts */
3639 3617 dcr = DCR_READ(pp);
3640 3618 (void) dcr_write(pp, dcr & ~(ECPP_REV_DIR | ECPP_INTR_EN));
3641 3619 ECPP_MASK_INTR(pp);
3642 3620
3643 3621 pp->softintr_pending = 0;
3644 3622 unx_len = pp->last_byte - pp->next_byte;
3645 3623 ecpp_error(pp->dip, "xfer_timeout: unx_len=%d\n", unx_len);
3646 3624
3647 3625 if (unx_len > 0) {
3648 3626 unx_addr = pp->next_byte;
3649 3627 } else {
3650 3628 ecpp_xfer_cleanup(pp);
3651 3629 qenable(pp->writeq);
3652 3630 mutex_exit(&pp->umutex);
3653 3631 return;
3654 3632 }
3655 3633 } else {
3656 3634 /*
3657 3635 * DMA mode timeout
3658 3636 *
3659 3637 * If DMAC fails to shut off, continue anyways and attempt
3660 3638 * to put untransfered data back on queue.
3661 3639 */
3662 3640 if (ECPP_DMA_STOP(pp, &unx_len) == FAILURE) {
3663 3641 ecpp_error(pp->dip,
3664 3642 "ecpp_xfer_timeout: failed dma_stop\n");
3665 3643 }
3666 3644
3667 3645 ecpp_error(pp->dip, "xfer_timeout: unx_len=%d\n", unx_len);
3668 3646
3669 3647 if (ddi_dma_unbind_handle(pp->dma_handle) == DDI_FAILURE) {
3670 3648 ecpp_error(pp->dip,
3671 3649 "ecpp_xfer_timeout: failed unbind\n");
3672 3650 }
3673 3651
3674 3652 /*
3675 3653 * if the bcr is zero, then DMA is complete and
3676 3654 * we are waiting for the fifo to drain. So let
3677 3655 * ecpp_fifo_timer() look after the clean up.
3678 3656 */
3679 3657 if (unx_len == 0) {
3680 3658 qenable(pp->writeq);
3681 3659 mutex_exit(&pp->umutex);
3682 3660 return;
3683 3661 } else {
3684 3662 xferd = pp->dma_cookie.dmac_size - unx_len;
3685 3663 pp->resid -= xferd;
3686 3664 unx_len = pp->resid;
3687 3665
3688 3666 /* update statistics */
3689 3667 pp->obytes[pp->current_mode] += xferd;
3690 3668 pp->joblen += xferd;
3691 3669
3692 3670 if (pp->msg != NULL) {
3693 3671 unx_addr = (caddr_t)pp->msg->b_wptr - unx_len;
3694 3672 } else {
3695 3673 unx_addr = pp->ioblock +
3696 3674 (pp->xfercnt - unx_len);
3697 3675 }
3698 3676 }
3699 3677 }
3700 3678
3701 3679 /* Following code is common for PIO and DMA modes */
3702 3680
3703 3681 ecpp_putback_untransfered(pp, (caddr_t)unx_addr, unx_len);
3704 3682
3705 3683 if (pp->msg != NULL) {
3706 3684 freemsg(pp->msg);
3707 3685 pp->msg = NULL;
3708 3686 }
3709 3687
3710 3688 /* mark the error status structure */
3711 3689 pp->timeout_error = 1;
3712 3690 pp->e_busy = ECPP_ERR;
3713 3691 fifo_timer_id = pp->fifo_timer_id;
3714 3692 pp->fifo_timer_id = 0;
3715 3693
3716 3694 qenable(pp->writeq);
3717 3695
3718 3696 mutex_exit(&pp->umutex);
3719 3697
3720 3698 if (fifo_timer_id) {
3721 3699 (void) untimeout(fifo_timer_id);
3722 3700 }
3723 3701 }
3724 3702
3725 3703 static void
3726 3704 ecpp_putback_untransfered(struct ecppunit *pp, void *startp, uint_t len)
3727 3705 {
3728 3706 mblk_t *new_mp;
3729 3707
3730 3708 ecpp_error(pp->dip, "ecpp_putback_untrans=%d\n", len);
3731 3709
3732 3710 if (len == 0) {
3733 3711 return;
3734 3712 }
3735 3713
3736 3714 new_mp = allocb(len, BPRI_MED);
3737 3715 if (new_mp == NULL) {
3738 3716 ecpp_error(pp->dip,
3739 3717 "ecpp_putback_untransfered: allocb FAILURE.\n");
3740 3718 return;
3741 3719 }
3742 3720
3743 3721 bcopy(startp, new_mp->b_rptr, len);
3744 3722 new_mp->b_wptr = new_mp->b_rptr + len;
3745 3723
3746 3724 if (!putbq(pp->writeq, new_mp)) {
3747 3725 freemsg(new_mp);
3748 3726 }
3749 3727 }
3750 3728
3751 3729 static uchar_t
3752 3730 ecr_write(struct ecppunit *pp, uint8_t ecr_byte)
3753 3731 {
3754 3732 int i, current_ecr;
3755 3733
3756 3734 for (i = ECPP_REG_WRITE_MAX_LOOP; i > 0; i--) {
3757 3735 ECR_WRITE(pp, ecr_byte);
3758 3736
3759 3737 current_ecr = ECR_READ(pp);
3760 3738
3761 3739 /* mask off the lower two read-only bits */
3762 3740 if ((ecr_byte & 0xFC) == (current_ecr & 0xFC))
3763 3741 return (SUCCESS);
3764 3742 }
3765 3743 return (FAILURE);
3766 3744 }
3767 3745
3768 3746 static uchar_t
3769 3747 dcr_write(struct ecppunit *pp, uint8_t dcr_byte)
3770 3748 {
3771 3749 uint8_t current_dcr;
3772 3750 int i;
3773 3751
3774 3752 for (i = ECPP_REG_WRITE_MAX_LOOP; i > 0; i--) {
3775 3753 DCR_WRITE(pp, dcr_byte);
3776 3754
3777 3755 current_dcr = DCR_READ(pp);
3778 3756
3779 3757 /* compare only bits 0-4 (direction bit return 1) */
3780 3758 if ((dcr_byte & 0x1F) == (current_dcr & 0x1F))
3781 3759 return (SUCCESS);
3782 3760 }
3783 3761 ecpp_error(pp->dip,
3784 3762 "(%d)dcr_write: dcr written =%x, dcr readback =%x\n",
3785 3763 i, dcr_byte, current_dcr);
3786 3764
3787 3765 return (FAILURE);
3788 3766 }
3789 3767
3790 3768 static uchar_t
3791 3769 ecpp_reset_port_regs(struct ecppunit *pp)
3792 3770 {
3793 3771 DCR_WRITE(pp, ECPP_SLCTIN | ECPP_nINIT);
3794 3772 ECR_WRITE(pp, ECR_mode_001 | ECPP_INTR_MASK | ECPP_INTR_SRV);
3795 3773 return (SUCCESS);
3796 3774 }
3797 3775
3798 3776 /*
3799 3777 * The data transferred by the DMA engine goes through the FIFO,
3800 3778 * so that when the DMA counter reaches zero (and an interrupt occurs)
3801 3779 * the FIFO can still contain data. If this is the case, the ISR will
3802 3780 * schedule this callback to wait until the FIFO drains or a timeout occurs.
3803 3781 */
3804 3782 static void
3805 3783 ecpp_fifo_timer(void *arg)
3806 3784 {
3807 3785 struct ecppunit *pp = arg;
3808 3786 uint8_t ecr;
3809 3787 timeout_id_t timeout_id;
3810 3788
3811 3789 mutex_enter(&pp->umutex);
3812 3790
3813 3791 /*
3814 3792 * If the FIFO timer has been turned off, exit.
3815 3793 */
3816 3794 if (pp->fifo_timer_id == 0) {
3817 3795 ecpp_error(pp->dip, "ecpp_fifo_timer: untimedout\n");
3818 3796 mutex_exit(&pp->umutex);
3819 3797 return;
3820 3798 } else {
3821 3799 pp->fifo_timer_id = 0;
3822 3800 }
3823 3801
3824 3802 /*
3825 3803 * If the FIFO is not empty restart timer. Wait FIFO_DRAIN_PERIOD
3826 3804 * (250 ms) and check FIFO_EMPTY bit again. Repeat until FIFO is
3827 3805 * empty or until 10 * FIFO_DRAIN_PERIOD expires.
3828 3806 */
3829 3807 ecr = ECR_READ(pp);
3830 3808
3831 3809 if ((pp->current_mode != ECPP_DIAG_MODE) &&
3832 3810 (((ecr & ECPP_FIFO_EMPTY) == 0) &&
3833 3811 (pp->ecpp_drain_counter < 10))) {
3834 3812
3835 3813 ecpp_error(pp->dip,
3836 3814 "ecpp_fifo_timer(%d):FIFO not empty:ecr=%x\n",
3837 3815 pp->ecpp_drain_counter, ecr);
3838 3816
3839 3817 pp->fifo_timer_id = timeout(ecpp_fifo_timer,
3840 3818 (caddr_t)pp, drv_usectohz(FIFO_DRAIN_PERIOD));
3841 3819 ++pp->ecpp_drain_counter;
3842 3820
3843 3821 mutex_exit(&pp->umutex);
3844 3822 return;
3845 3823 }
3846 3824
3847 3825 if (pp->current_mode != ECPP_DIAG_MODE) {
3848 3826 /*
3849 3827 * If the FIFO won't drain after 10 FIFO_DRAIN_PERIODs
3850 3828 * then don't wait any longer. Simply clean up the transfer.
3851 3829 */
3852 3830 if (pp->ecpp_drain_counter >= 10) {
3853 3831 ecpp_error(pp->dip, "ecpp_fifo_timer(%d):"
3854 3832 " clearing FIFO,can't wait:ecr=%x\n",
3855 3833 pp->ecpp_drain_counter, ecr);
3856 3834 } else {
3857 3835 ecpp_error(pp->dip,
3858 3836 "ecpp_fifo_timer(%d):FIFO empty:ecr=%x\n",
3859 3837 pp->ecpp_drain_counter, ecr);
3860 3838 }
3861 3839
3862 3840 pp->ecpp_drain_counter = 0;
3863 3841 }
3864 3842
3865 3843 /*
3866 3844 * Main section of routine:
3867 3845 * - stop the DMA transfer timer
3868 3846 * - program DMA with next cookie/window or unbind the DMA mapping
3869 3847 * - update stats
3870 3848 * - if last mblk in queue, signal to close() & return to idle state
3871 3849 */
3872 3850
3873 3851 /* Stop the DMA transfer timeout timer */
3874 3852 timeout_id = pp->timeout_id;
3875 3853 pp->timeout_id = 0;
3876 3854
3877 3855 /* data has drained from fifo, it is ok to free dma resource */
3878 3856 if (pp->current_mode == ECPP_ECP_MODE ||
3879 3857 pp->current_mode == ECPP_DIAG_MODE ||
3880 3858 COMPAT_DMA(pp)) {
3881 3859 off_t off;
3882 3860 size_t len;
3883 3861
3884 3862 /* update residual */
3885 3863 pp->resid -= pp->dma_cookie.dmac_size;
3886 3864
3887 3865 /* update statistics */
3888 3866 pp->joblen += pp->dma_cookie.dmac_size;
3889 3867 if (pp->dma_dir == DDI_DMA_WRITE) {
3890 3868 pp->obytes[pp->current_mode] +=
3891 3869 pp->dma_cookie.dmac_size;
3892 3870 } else {
3893 3871 pp->ibytes[pp->current_mode] +=
3894 3872 pp->dma_cookie.dmac_size;
3895 3873 }
3896 3874
3897 3875 /*
3898 3876 * Look if any cookies/windows left
3899 3877 */
3900 3878 if (--pp->dma_cookie_count > 0) {
3901 3879 /* process the next cookie */
3902 3880 ddi_dma_nextcookie(pp->dma_handle,
3903 3881 &pp->dma_cookie);
3904 3882 } else if (pp->dma_curwin < pp->dma_nwin) {
3905 3883 /* process the next window */
3906 3884 if (ddi_dma_getwin(pp->dma_handle,
3907 3885 pp->dma_curwin, &off, &len,
3908 3886 &pp->dma_cookie,
3909 3887 &pp->dma_cookie_count) != DDI_SUCCESS) {
3910 3888 ecpp_error(pp->dip,
3911 3889 "ecpp_fifo_timer: ddi_dma_getwin failed\n");
3912 3890 goto dma_done;
3913 3891 }
3914 3892
3915 3893 pp->dma_curwin++;
3916 3894 } else {
3917 3895 goto dma_done;
3918 3896 }
3919 3897
3920 3898 ecpp_error(pp->dip, "ecpp_fifo_timer: next addr=%llx len=%d\n",
3921 3899 pp->dma_cookie.dmac_address,
3922 3900 pp->dma_cookie.dmac_size);
3923 3901
3924 3902 /* kick off new transfer */
3925 3903 if (ECPP_DMA_START(pp) != SUCCESS) {
3926 3904 ecpp_error(pp->dip,
3927 3905 "ecpp_fifo_timer: dma_start failed\n");
3928 3906 goto dma_done;
3929 3907 }
3930 3908
3931 3909 (void) ecr_write(pp, (ecr & 0xe0) |
3932 3910 ECPP_DMA_ENABLE | ECPP_INTR_MASK);
3933 3911
3934 3912 mutex_exit(&pp->umutex);
3935 3913
3936 3914 if (timeout_id) {
3937 3915 (void) untimeout(timeout_id);
3938 3916 }
3939 3917 return;
3940 3918
3941 3919 dma_done:
3942 3920 if (ddi_dma_unbind_handle(pp->dma_handle) != DDI_SUCCESS) {
3943 3921 ecpp_error(pp->dip, "ecpp_fifo_timer: unbind failed\n");
3944 3922 } else {
3945 3923 ecpp_error(pp->dip, "ecpp_fifo_timer: unbind ok\n");
3946 3924 }
3947 3925 }
3948 3926
3949 3927 /*
3950 3928 * if we did not use the dmablock, the mblk that
3951 3929 * was used should be freed.
3952 3930 */
3953 3931 if (pp->msg != NULL) {
3954 3932 freemsg(pp->msg);
3955 3933 pp->msg = NULL;
3956 3934 }
3957 3935
3958 3936 /* The port is no longer active */
3959 3937 pp->e_busy = ECPP_IDLE;
3960 3938
3961 3939 qenable(pp->writeq);
3962 3940
3963 3941 mutex_exit(&pp->umutex);
3964 3942
3965 3943 if (timeout_id) {
3966 3944 (void) untimeout(timeout_id);
3967 3945 }
3968 3946 }
3969 3947
3970 3948 /*
3971 3949 * In Compatibility mode, check if the peripheral is ready to accept data
3972 3950 */
3973 3951 static uint8_t
3974 3952 ecpp_check_status(struct ecppunit *pp)
3975 3953 {
3976 3954 uint8_t dsr;
3977 3955 uint8_t statmask;
3978 3956
3979 3957 if (pp->current_mode == ECPP_ECP_MODE ||
3980 3958 pp->current_mode == ECPP_DIAG_MODE)
3981 3959 return (SUCCESS);
3982 3960
3983 3961 statmask = ECPP_nERR | ECPP_SLCT | ECPP_nBUSY | ECPP_nACK;
3984 3962
3985 3963 dsr = DSR_READ(pp);
3986 3964 if ((dsr & ECPP_PE) || ((dsr & statmask) != statmask)) {
3987 3965 pp->e_busy = ECPP_ERR;
3988 3966 return (FAILURE);
3989 3967 } else {
3990 3968 return (SUCCESS);
3991 3969 }
3992 3970 }
3993 3971
3994 3972 /*
3995 3973 * if the peripheral is not ready to accept data, write service routine
3996 3974 * periodically reschedules itself to recheck peripheral status
3997 3975 * and start data transfer as soon as possible
3998 3976 */
3999 3977 static void
4000 3978 ecpp_wsrv_timer(void *arg)
4001 3979 {
4002 3980 struct ecppunit *pp = arg;
4003 3981
4004 3982 ecpp_error(pp->dip, "ecpp_wsrv_timer: starting\n");
4005 3983
4006 3984 mutex_enter(&pp->umutex);
4007 3985
4008 3986 if (pp->wsrv_timer_id == 0) {
4009 3987 mutex_exit(&pp->umutex);
4010 3988 return;
4011 3989 } else {
4012 3990 pp->wsrv_timer_id = 0;
4013 3991 }
4014 3992
4015 3993 ecpp_error(pp->dip, "ecpp_wsrv_timer: qenabling...\n");
4016 3994
4017 3995 qenable(pp->writeq);
4018 3996
4019 3997 mutex_exit(&pp->umutex);
4020 3998 }
4021 3999
4022 4000 /*
4023 4001 * Allocate a message indicating a backchannel request
4024 4002 * and put it on the write queue
4025 4003 */
4026 4004 static int
4027 4005 ecpp_backchan_req(struct ecppunit *pp)
4028 4006 {
4029 4007 mblk_t *mp;
4030 4008
4031 4009 if ((mp = allocb(sizeof (int), BPRI_MED)) == NULL) {
4032 4010 ecpp_error(pp->dip, "ecpp_backchan_req: allocb failed\n");
4033 4011 return (FAILURE);
4034 4012 } else {
4035 4013 mp->b_datap->db_type = M_CTL;
4036 4014 *(int *)mp->b_rptr = ECPP_BACKCHANNEL;
4037 4015 mp->b_wptr = mp->b_rptr + sizeof (int);
4038 4016 if (!putbq(pp->writeq, mp)) {
4039 4017 ecpp_error(pp->dip, "ecpp_backchan_req:putbq failed\n");
4040 4018 freemsg(mp);
4041 4019 return (FAILURE);
4042 4020 }
4043 4021 return (SUCCESS);
4044 4022 }
4045 4023 }
4046 4024
4047 4025 /*
4048 4026 * Cancel the function scheduled with timeout(9F)
4049 4027 * This function is to be called with the mutex held
4050 4028 */
4051 4029 static void
4052 4030 ecpp_untimeout_unblock(struct ecppunit *pp, timeout_id_t *id)
4053 4031 {
4054 4032 timeout_id_t saved_id;
4055 4033
4056 4034 ASSERT(mutex_owned(&pp->umutex));
4057 4035
4058 4036 if (*id) {
4059 4037 saved_id = *id;
4060 4038 *id = 0;
4061 4039 mutex_exit(&pp->umutex);
4062 4040 (void) untimeout(saved_id);
4063 4041 mutex_enter(&pp->umutex);
4064 4042 }
4065 4043 }
4066 4044
4067 4045 /*
4068 4046 * get prnio interface capabilities
4069 4047 */
4070 4048 static uint_t
4071 4049 ecpp_get_prn_ifcap(struct ecppunit *pp)
4072 4050 {
4073 4051 uint_t ifcap;
4074 4052
4075 4053 ifcap = PRN_1284_DEVID | PRN_TIMEOUTS | PRN_STREAMS;
4076 4054
4077 4055 /* status (DSR) only makes sense in Centronics & Compat modes */
4078 4056 if (pp->current_mode == ECPP_CENTRONICS ||
4079 4057 pp->current_mode == ECPP_COMPAT_MODE) {
4080 4058 ifcap |= PRN_1284_STATUS;
4081 4059 } else if (pp->current_mode == ECPP_NIBBLE_MODE ||
4082 4060 pp->current_mode == ECPP_ECP_MODE) {
4083 4061 ifcap |= PRN_BIDI;
4084 4062 }
4085 4063
4086 4064 return (ifcap);
4087 4065 }
4088 4066
4089 4067 /*
4090 4068 * Determine SuperI/O type
4091 4069 */
4092 4070 static struct ecpp_hw_bind *
4093 4071 ecpp_determine_sio_type(struct ecppunit *pp)
4094 4072 {
4095 4073 struct ecpp_hw_bind *hw_bind;
4096 4074 char *name;
4097 4075 int i;
4098 4076
4099 4077 name = ddi_binding_name(pp->dip);
4100 4078
4101 4079 for (hw_bind = NULL, i = 0; i < NELEM(ecpp_hw_bind); i++) {
4102 4080 if (strcmp(name, ecpp_hw_bind[i].name) == 0) {
4103 4081 hw_bind = &ecpp_hw_bind[i];
4104 4082 break;
4105 4083 }
4106 4084 }
4107 4085
4108 4086 return (hw_bind);
4109 4087 }
4110 4088
4111 4089
4112 4090 /*
4113 4091 *
4114 4092 * IEEE 1284 support routines:
4115 4093 * negotiation and termination;
4116 4094 * phase transitions;
4117 4095 * device ID;
4118 4096 *
4119 4097 */
4120 4098
4121 4099 /*
4122 4100 * Interface initialization, abnormal termination into Compatibility mode
4123 4101 *
4124 4102 * Peripheral may be non-1284, so we set current mode to ECPP_CENTRONICS
4125 4103 */
4126 4104 static void
4127 4105 ecpp_1284_init_interface(struct ecppunit *pp)
4128 4106 {
4129 4107 ECR_WRITE(pp, ECPP_INTR_SRV | ECPP_INTR_MASK | ECR_mode_001);
4130 4108
4131 4109 /*
4132 4110 * Toggle the nInit signal if configured in ecpp.conf
4133 4111 * for most peripherals it is not needed
4134 4112 */
4135 4113 if (pp->init_seq == TRUE) {
4136 4114 DCR_WRITE(pp, ECPP_SLCTIN);
4137 4115 drv_usecwait(50); /* T(ER) = 50us */
4138 4116 }
4139 4117
4140 4118 DCR_WRITE(pp, ECPP_nINIT | ECPP_SLCTIN);
4141 4119
4142 4120 pp->current_mode = pp->backchannel = ECPP_CENTRONICS;
4143 4121 pp->current_phase = ECPP_PHASE_C_IDLE;
4144 4122 ECPP_CONFIG_MODE(pp);
4145 4123 pp->to_mode[pp->current_mode]++;
4146 4124
4147 4125 ecpp_error(pp->dip, "ecpp_1284_init_interface: ok\n");
4148 4126 }
4149 4127
4150 4128 /*
4151 4129 * ECP mode negotiation
4152 4130 */
4153 4131 static int
4154 4132 ecp_negotiation(struct ecppunit *pp)
4155 4133 {
4156 4134 uint8_t dsr;
4157 4135
4158 4136 /* ECP mode negotiation */
4159 4137
4160 4138 if (ecpp_1284_negotiation(pp, ECPP_XREQ_ECP, &dsr) == FAILURE)
4161 4139 return (FAILURE);
4162 4140
4163 4141 /* Event 5: peripheral deasserts PError and Busy, asserts Select */
4164 4142 if ((dsr & (ECPP_PE | ECPP_nBUSY | ECPP_SLCT)) !=
4165 4143 (ECPP_nBUSY | ECPP_SLCT)) {
4166 4144 ecpp_error(pp->dip,
4167 4145 "ecp_negotiation: failed event 5 %x\n", DSR_READ(pp));
4168 4146 (void) ecpp_1284_termination(pp);
4169 4147 return (FAILURE);
4170 4148 }
4171 4149
4172 4150 /* entered Setup Phase */
4173 4151 pp->current_phase = ECPP_PHASE_ECP_SETUP;
4174 4152
4175 4153 /* Event 30: host asserts nAutoFd */
4176 4154 DCR_WRITE(pp, ECPP_nINIT | ECPP_AFX);
4177 4155
4178 4156 /* Event 31: peripheral asserts PError */
4179 4157 if (wait_dsr(pp, ECPP_PE, ECPP_PE, 35000) < 0) {
4180 4158 ecpp_error(pp->dip,
4181 4159 "ecp_negotiation: failed event 31 %x\n", DSR_READ(pp));
4182 4160 (void) ecpp_1284_termination(pp);
4183 4161 return (FAILURE);
4184 4162 }
4185 4163
4186 4164 /* entered Forward Idle Phase */
4187 4165 pp->current_phase = ECPP_PHASE_ECP_FWD_IDLE;
4188 4166
4189 4167 /* successful negotiation into ECP mode */
4190 4168 pp->current_mode = ECPP_ECP_MODE;
4191 4169 pp->backchannel = ECPP_ECP_MODE;
4192 4170
4193 4171 ecpp_error(pp->dip, "ecp_negotiation: ok\n");
4194 4172
4195 4173 return (SUCCESS);
4196 4174 }
4197 4175
4198 4176 /*
4199 4177 * Nibble mode negotiation
4200 4178 */
4201 4179 static int
4202 4180 nibble_negotiation(struct ecppunit *pp)
4203 4181 {
4204 4182 uint8_t dsr;
4205 4183
4206 4184 if (ecpp_1284_negotiation(pp, ECPP_XREQ_NIBBLE, &dsr) == FAILURE) {
4207 4185 return (FAILURE);
4208 4186 }
4209 4187
4210 4188 /*
4211 4189 * If peripheral has data available, PE and nErr will
4212 4190 * be set low at Event 5 & 6.
4213 4191 */
4214 4192 if ((dsr & (ECPP_PE | ECPP_nERR)) == 0) {
4215 4193 pp->current_phase = ECPP_PHASE_NIBT_AVAIL;
4216 4194 } else {
4217 4195 pp->current_phase = ECPP_PHASE_NIBT_NAVAIL;
4218 4196 }
4219 4197
4220 4198 /* successful negotiation into Nibble mode */
4221 4199 pp->current_mode = ECPP_NIBBLE_MODE;
4222 4200 pp->backchannel = ECPP_NIBBLE_MODE;
4223 4201
4224 4202 ecpp_error(pp->dip, "nibble_negotiation: ok (phase=%x)\n",
4225 4203 pp->current_phase);
4226 4204
4227 4205 return (SUCCESS);
4228 4206
4229 4207 }
4230 4208
4231 4209 /*
4232 4210 * Wait ptimeout usec for periph to set 'mask' bits to 'val' state
4233 4211 *
4234 4212 * return value < 0 indicates timeout
4235 4213 */
4236 4214 static int
4237 4215 wait_dsr(struct ecppunit *pp, uint8_t mask, uint8_t val, int ptimeout)
4238 4216 {
4239 4217 while (((DSR_READ(pp) & mask) != val) && ptimeout--) {
4240 4218 drv_usecwait(1);
4241 4219 }
4242 4220
4243 4221 return (ptimeout);
4244 4222 }
4245 4223
4246 4224 /*
4247 4225 * 1284 negotiation Events 0..6
4248 4226 * required mode is indicated by extensibility request value
4249 4227 *
4250 4228 * After successful negotiation SUCCESS is returned and
4251 4229 * current mode is set according to xreq,
4252 4230 * otherwise FAILURE is returned and current mode is set to
4253 4231 * either COMPAT (1284 periph) or CENTRONICS (non-1284 periph)
4254 4232 *
4255 4233 * Current phase must be set by the caller (mode-specific negotiation)
4256 4234 *
4257 4235 * If rdsr is not NULL, DSR value after Event 6 is stored here
4258 4236 */
4259 4237 static int
4260 4238 ecpp_1284_negotiation(struct ecppunit *pp, uint8_t xreq, uint8_t *rdsr)
4261 4239 {
4262 4240 int xflag;
4263 4241
4264 4242 ecpp_error(pp->dip, "nego(%x): entering...\n", xreq);
4265 4243
4266 4244 /* negotiation should start in Compatibility mode */
4267 4245 (void) ecpp_1284_termination(pp);
4268 4246
4269 4247 /* Set host into Compat mode */
4270 4248 ECR_WRITE(pp, ECPP_INTR_SRV | ECPP_INTR_MASK | ECR_mode_001);
4271 4249
4272 4250 pp->current_phase = ECPP_PHASE_NEGO;
4273 4251
4274 4252 /* Event 0: host sets extensibility request on data lines */
4275 4253 DATAR_WRITE(pp, xreq);
4276 4254
4277 4255 /* Event 1: host deassert nSelectin and assert nAutoFd */
4278 4256 DCR_WRITE(pp, ECPP_nINIT | ECPP_AFX);
4279 4257
4280 4258 drv_usecwait(1); /* Tp(ecp) == 0.5us */
4281 4259
4282 4260 /*
4283 4261 * Event 2: peripheral asserts nAck, deasserts nFault,
4284 4262 * asserts Select, asserts PError
4285 4263 */
4286 4264 if (wait_dsr(pp, ECPP_nERR | ECPP_SLCT | ECPP_PE | ECPP_nACK,
4287 4265 ECPP_nERR | ECPP_SLCT | ECPP_PE, 35000) < 0) {
4288 4266 /* peripheral is not 1284-compliant */
4289 4267 ecpp_error(pp->dip,
4290 4268 "nego(%x): failed event 2 %x\n", xreq, DSR_READ(pp));
4291 4269 (void) ecpp_1284_termination(pp);
4292 4270 return (FAILURE);
4293 4271 }
4294 4272
4295 4273 /*
4296 4274 * Event 3: host asserts nStrobe, latching extensibility value into
4297 4275 * peripherals input latch.
4298 4276 */
4299 4277 DCR_WRITE(pp, ECPP_nINIT | ECPP_AFX | ECPP_STB);
4300 4278
4301 4279 drv_usecwait(2); /* Tp(ecp) = 0.5us */
4302 4280
4303 4281 /*
4304 4282 * Event 4: hosts deasserts nStrobe and nAutoFD to acknowledge that
4305 4283 * it has recognized an 1284 compatible peripheral
4306 4284 */
4307 4285 DCR_WRITE(pp, ECPP_nINIT);
4308 4286
4309 4287 /*
4310 4288 * Event 5: Peripheral confirms it supports requested extension
4311 4289 * For Nibble mode Xflag must be low, otherwise it must be high
4312 4290 */
4313 4291 xflag = (xreq == ECPP_XREQ_NIBBLE) ? 0 : ECPP_SLCT;
4314 4292
4315 4293 /*
4316 4294 * Event 6: Peripheral sets nAck high
4317 4295 * indicating that status lines are valid
4318 4296 */
4319 4297 if (wait_dsr(pp, ECPP_nACK, ECPP_nACK, 35000) < 0) {
4320 4298 /* Something wrong with peripheral */
4321 4299 ecpp_error(pp->dip,
4322 4300 "nego(%x): failed event 6 %x\n", xreq, DSR_READ(pp));
4323 4301 (void) ecpp_1284_termination(pp);
4324 4302 return (FAILURE);
4325 4303 }
4326 4304
4327 4305 if ((DSR_READ(pp) & ECPP_SLCT) != xflag) {
4328 4306 /* Extensibility value is not supported */
4329 4307 ecpp_error(pp->dip,
4330 4308 "nego(%x): failed event 5 %x\n", xreq, DSR_READ(pp));
4331 4309 (void) ecpp_1284_termination(pp);
4332 4310 return (FAILURE);
4333 4311 }
4334 4312
4335 4313 if (rdsr) {
4336 4314 *rdsr = DSR_READ(pp);
4337 4315 }
4338 4316
4339 4317 return (SUCCESS);
4340 4318 }
4341 4319
4342 4320 /*
4343 4321 * 1284 Termination: Events 22..28 - set link to Compatibility mode
4344 4322 *
4345 4323 * This routine is not designed for Immediate termination,
4346 4324 * caller must take care of waiting for a valid state,
4347 4325 * (in particular, in ECP mode current phase must be Forward Idle)
4348 4326 * otherwise interface will be reinitialized
4349 4327 *
4350 4328 * In case of Valid state termination SUCCESS is returned and
4351 4329 * current_mode is ECPP_COMPAT_MODE, current phase is ECPP_PHASE_C_IDLE
4352 4330 * Otherwise interface is reinitialized, FAILURE is returned and
4353 4331 * current mode is ECPP_CENTRONICS, current phase is ECPP_PHASE_C_IDLE
4354 4332 */
4355 4333 static int
4356 4334 ecpp_1284_termination(struct ecppunit *pp)
4357 4335 {
4358 4336 int previous_mode = pp->current_mode;
4359 4337
4360 4338 if (((pp->current_mode == ECPP_COMPAT_MODE ||
4361 4339 pp->current_mode == ECPP_CENTRONICS) &&
4362 4340 pp->current_phase == ECPP_PHASE_C_IDLE) ||
4363 4341 pp->current_mode == ECPP_DIAG_MODE) {
4364 4342 ecpp_error(pp->dip, "termination: not needed\n");
4365 4343 return (SUCCESS);
4366 4344 }
4367 4345
4368 4346 /* Set host into Compat mode, interrupts disabled */
4369 4347 ECPP_MASK_INTR(pp);
4370 4348 ECR_WRITE(pp, ECPP_INTR_SRV | ECPP_INTR_MASK | ECR_mode_001);
4371 4349
4372 4350 pp->current_mode = ECPP_COMPAT_MODE; /* needed by next function */
4373 4351
4374 4352 ECPP_CONFIG_MODE(pp);
4375 4353
4376 4354 /*
4377 4355 * EPP mode uses simple nInit pulse for termination
4378 4356 */
4379 4357 if (previous_mode == ECPP_EPP_MODE) {
4380 4358 /* Event 68: host sets nInit low */
4381 4359 DCR_WRITE(pp, 0);
4382 4360
4383 4361 drv_usecwait(55); /* T(ER) = 50us */
4384 4362
4385 4363 /* Event 69: host sets nInit high */
4386 4364 DCR_WRITE(pp, ECPP_nINIT | ECPP_SLCTIN);
4387 4365
4388 4366 goto endterm;
4389 4367 }
4390 4368
4391 4369 /* terminate peripheral to Compat mode */
4392 4370 pp->current_phase = ECPP_PHASE_TERM;
4393 4371
4394 4372 /* Event 22: hosts sets nSelectIn low and nAutoFd high */
4395 4373 DCR_WRITE(pp, ECPP_nINIT | ECPP_SLCTIN);
4396 4374
4397 4375 /* Event 23: peripheral deasserts nFault and nBusy */
4398 4376 /* Event 24: peripheral asserts nAck */
4399 4377 if (wait_dsr(pp, ECPP_nERR | ECPP_nBUSY | ECPP_nACK,
4400 4378 ECPP_nERR, 35000) < 0) {
4401 4379 ecpp_error(pp->dip,
4402 4380 "termination: failed events 23,24 %x\n", DSR_READ(pp));
4403 4381 ecpp_1284_init_interface(pp);
4404 4382 return (FAILURE);
4405 4383 }
4406 4384
4407 4385 drv_usecwait(1); /* Tp = 0.5us */
4408 4386
4409 4387 /* Event 25: hosts sets nAutoFd low */
4410 4388 DCR_WRITE(pp, ECPP_nINIT | ECPP_SLCTIN | ECPP_AFX);
4411 4389
4412 4390 /* Event 26: the peripheral puts itself in Compatible mode */
4413 4391
4414 4392 /* Event 27: peripheral deasserts nAck */
4415 4393 if (wait_dsr(pp, ECPP_nACK, ECPP_nACK, 35000) < 0) {
4416 4394 ecpp_error(pp->dip,
4417 4395 "termination: failed event 27 %x\n", DSR_READ(pp));
4418 4396 ecpp_1284_init_interface(pp);
4419 4397 return (FAILURE);
4420 4398 }
4421 4399
4422 4400 drv_usecwait(1); /* Tp = 0.5us */
4423 4401
4424 4402 /* Event 28: hosts deasserts nAutoFd */
4425 4403 DCR_WRITE(pp, ECPP_nINIT | ECPP_SLCTIN);
4426 4404
4427 4405 drv_usecwait(1); /* Tp = 0.5us */
4428 4406
4429 4407 endterm:
4430 4408 /* Compatible mode Idle Phase */
4431 4409 pp->current_phase = ECPP_PHASE_C_IDLE;
4432 4410
4433 4411 ecpp_error(pp->dip, "termination: completed %x %x\n",
4434 4412 DSR_READ(pp), DCR_READ(pp));
4435 4413
4436 4414 return (SUCCESS);
4437 4415 }
4438 4416
4439 4417 /*
4440 4418 * Initiate ECP backchannel DMA transfer
4441 4419 */
4442 4420 static uchar_t
4443 4421 ecp_peripheral2host(struct ecppunit *pp)
4444 4422 {
4445 4423 mblk_t *mp = NULL;
4446 4424 size_t len;
4447 4425 uint32_t xfer_time;
4448 4426
4449 4427 ASSERT(pp->current_mode == ECPP_ECP_MODE &&
4450 4428 pp->current_phase == ECPP_PHASE_ECP_REV_IDLE);
4451 4429
4452 4430 /*
4453 4431 * hardware generates cycles to receive data from the peripheral
4454 4432 * we only need to read from FIFO
4455 4433 */
4456 4434
4457 4435 /*
4458 4436 * If user issued read(2) of rev_resid bytes, xfer exactly this amount
4459 4437 * unless it exceeds ECP_REV_BLKSZ_MAX; otherwise try to read
4460 4438 * ECP_REV_BLKSZ_MAX or at least ECP_REV_BLKSZ bytes
4461 4439 */
4462 4440 if (pp->nread > 0) {
4463 4441 len = min(pp->nread, ECP_REV_BLKSZ_MAX);
4464 4442 } else {
4465 4443 len = ECP_REV_BLKSZ_MAX;
4466 4444 }
4467 4445
4468 4446 pp->nread = 0; /* clear after use */
4469 4447
4470 4448 /*
4471 4449 * Allocate mblk for data, make max 2 attepmts:
4472 4450 * if len bytes block fails, try our block size
4473 4451 */
4474 4452 while ((mp = allocb(len, BPRI_MED)) == NULL) {
4475 4453 ecpp_error(pp->dip,
4476 4454 "ecp_periph2host: failed allocb(%d)\n", len);
4477 4455 if (len > ECP_REV_BLKSZ) {
4478 4456 len = ECP_REV_BLKSZ;
4479 4457 } else {
4480 4458 break;
4481 4459 }
4482 4460 }
4483 4461
4484 4462 if (mp == NULL) {
4485 4463 goto fail;
4486 4464 }
4487 4465
4488 4466 pp->msg = mp;
4489 4467 pp->e_busy = ECPP_BUSY;
4490 4468 pp->dma_dir = DDI_DMA_READ;
4491 4469 pp->current_phase = ECPP_PHASE_ECP_REV_XFER;
4492 4470
4493 4471 if (ecpp_init_dma_xfer(pp, (caddr_t)mp->b_rptr, len) == FAILURE) {
4494 4472 goto fail;
4495 4473 }
4496 4474
4497 4475 /*
4498 4476 * there are two problems with defining ECP backchannel xfer timeout
4499 4477 *
4500 4478 * a) IEEE 1284 allows infinite time between backchannel bytes,
4501 4479 * but we must stop at some point to send the data upstream,
4502 4480 * look if any forward transfer requests are pending, etc;
4503 4481 * all that done, we can continue with backchannel data;
4504 4482 *
4505 4483 * b) we don`t know how much data peripheral has;
4506 4484 * DMA counter is set to our buffer size, which can be bigger
4507 4485 * than needed - in this case a timeout must detect this;
4508 4486 *
4509 4487 * The timeout we schedule here serves as both the transfer timeout
4510 4488 * and a means of detecting backchannel stalls; in fact, there are
4511 4489 * two timeouts in one:
4512 4490 *
4513 4491 * - transfer timeout is based on the ECP bandwidth of ~1MB/sec and
4514 4492 * equals the time needed to transfer the whole buffer
4515 4493 * (but not less than ECP_REV_MINTOUT ms); if it occurs,
4516 4494 * DMA is stopped and the data is sent upstream;
4517 4495 *
4518 4496 * - backchannel watchdog, which would look at DMA counter
4519 4497 * every rev_watchdog ms and stop the transfer only
4520 4498 * if the counter hasn`t changed since the last time;
4521 4499 * otherwise it would save DMA counter value and restart itself;
4522 4500 *
4523 4501 * transfer timeout is a multiple of rev_watchdog
4524 4502 * and implemented as a downward counter
4525 4503 *
4526 4504 * on Grover, we can`t access DMAC registers while DMA is in flight,
4527 4505 * so we can`t have watchdog on Grover, only timeout
4528 4506 */
4529 4507
4530 4508 /* calculate number of watchdog invocations equal to the xfer timeout */
4531 4509 xfer_time = max((1000 * len) / pp->ecp_rev_speed, ECP_REV_MINTOUT);
4532 4510 #if defined(__x86)
4533 4511 pp->rev_timeout_cnt = (pp->hw == &x86) ? 1 :
4534 4512 max(xfer_time / pp->rev_watchdog, 1);
4535 4513 #else
4536 4514 pp->rev_timeout_cnt = (pp->hw == &m1553) ? 1 :
4537 4515 max(xfer_time / pp->rev_watchdog, 1);
4538 4516 #endif
4539 4517
4540 4518 pp->last_dmacnt = len; /* nothing xferred yet */
4541 4519
4542 4520 pp->timeout_id = timeout(ecpp_ecp_read_timeout, (caddr_t)pp,
4543 4521 drv_usectohz(pp->rev_watchdog * 1000));
4544 4522
4545 4523 ecpp_error(pp->dip, "ecp_periph2host: DMA started len=%d\n"
4546 4524 "xfer_time=%d wdog=%d cnt=%d\n",
4547 4525 len, xfer_time, pp->rev_watchdog, pp->rev_timeout_cnt);
4548 4526
4549 4527 return (SUCCESS);
4550 4528
4551 4529 fail:
4552 4530 if (mp) {
4553 4531 freemsg(mp);
4554 4532 }
4555 4533 pp->e_busy = ECPP_IDLE;
4556 4534 pp->current_phase = ECPP_PHASE_ECP_REV_IDLE;
4557 4535
4558 4536 return (FAILURE);
4559 4537 }
4560 4538
4561 4539 /*
4562 4540 * ECP backchannel read timeout
4563 4541 * implements both backchannel watchdog and transfer timeout in ECP mode
4564 4542 * if the transfer is still in progress, reschedule itself,
4565 4543 * otherwise call completion routine
4566 4544 */
4567 4545 static void
4568 4546 ecpp_ecp_read_timeout(void *arg)
4569 4547 {
4570 4548 struct ecppunit *pp = arg;
4571 4549 size_t dmacnt;
4572 4550
4573 4551 mutex_enter(&pp->umutex);
4574 4552
4575 4553 if (pp->timeout_id == 0) {
4576 4554 mutex_exit(&pp->umutex);
4577 4555 return;
4578 4556 } else {
4579 4557 pp->timeout_id = 0;
4580 4558 }
4581 4559
4582 4560 if (--pp->rev_timeout_cnt == 0) {
4583 4561 /*
4584 4562 * Transfer timed out
4585 4563 */
4586 4564 ecpp_error(pp->dip, "ecp_read_timeout: timeout\n");
4587 4565 pp->xfer_tout++;
4588 4566 ecpp_ecp_read_completion(pp);
4589 4567 } else {
4590 4568 /*
4591 4569 * Backchannel watchdog:
4592 4570 * look if DMA made any progress from the last time
4593 4571 */
4594 4572 dmacnt = ECPP_DMA_GETCNT(pp);
4595 4573 if (dmacnt - pp->last_dmacnt == 0) {
4596 4574 /*
4597 4575 * No progress - stop the transfer and send
4598 4576 * whatever has been read so far up the stream
4599 4577 */
4600 4578 ecpp_error(pp->dip, "ecp_read_timeout: no progress\n");
4601 4579 pp->xfer_tout++;
4602 4580 ecpp_ecp_read_completion(pp);
4603 4581 } else {
4604 4582 /*
4605 4583 * Something was transferred - restart ourselves
4606 4584 */
4607 4585 ecpp_error(pp->dip, "ecp_read_timeout: restarting\n");
4608 4586 pp->last_dmacnt = dmacnt;
4609 4587 pp->timeout_id = timeout(ecpp_ecp_read_timeout,
4610 4588 (caddr_t)pp,
4611 4589 drv_usectohz(pp->rev_watchdog * 1000));
4612 4590 }
4613 4591 }
4614 4592
4615 4593 mutex_exit(&pp->umutex);
4616 4594 }
4617 4595
4618 4596 /*
4619 4597 * ECP backchannel read completion:
4620 4598 * stop the DMA, free DMA resources and send read data upstream
4621 4599 */
4622 4600 static void
4623 4601 ecpp_ecp_read_completion(struct ecppunit *pp)
4624 4602 {
4625 4603 size_t xfer_len, unx_len;
4626 4604 mblk_t *mp;
4627 4605
4628 4606 ASSERT(mutex_owned(&pp->umutex));
4629 4607 ASSERT(pp->current_mode == ECPP_ECP_MODE &&
4630 4608 pp->current_phase == ECPP_PHASE_ECP_REV_XFER);
4631 4609 ASSERT(pp->msg != NULL);
4632 4610
4633 4611 /*
4634 4612 * Stop the transfer and unbind DMA handle
4635 4613 */
4636 4614 if (ECPP_DMA_STOP(pp, &unx_len) == FAILURE) {
4637 4615 unx_len = pp->resid;
4638 4616 ecpp_error(pp->dip, "ecp_read_completion: failed dma_stop\n");
4639 4617 }
4640 4618
4641 4619 mp = pp->msg;
4642 4620 xfer_len = pp->resid - unx_len; /* how much data was transferred */
4643 4621
4644 4622 if (ddi_dma_unbind_handle(pp->dma_handle) != DDI_SUCCESS) {
4645 4623 ecpp_error(pp->dip, "ecp_read_completion: unbind failed.\n");
4646 4624 }
4647 4625
4648 4626 ecpp_error(pp->dip, "ecp_read_completion: xfered %d bytes of %d\n",
4649 4627 xfer_len, pp->resid);
4650 4628
4651 4629 /* clean up and update statistics */
4652 4630 pp->msg = NULL;
4653 4631 pp->resid -= xfer_len;
4654 4632 pp->ibytes[pp->current_mode] += xfer_len;
4655 4633 pp->e_busy = ECPP_IDLE;
4656 4634 pp->current_phase = ECPP_PHASE_ECP_REV_IDLE;
4657 4635
4658 4636 /*
4659 4637 * Send the read data up the stream
4660 4638 */
4661 4639 mp->b_wptr += xfer_len;
4662 4640 if (canputnext(pp->readq)) {
4663 4641 mutex_exit(&pp->umutex);
4664 4642 putnext(pp->readq, mp);
4665 4643 mutex_enter(&pp->umutex);
4666 4644 } else {
4667 4645 ecpp_error(pp->dip, "ecp_read_completion: fail canputnext\n");
4668 4646 if (!putq(pp->readq, mp)) {
4669 4647 freemsg(mp);
4670 4648 }
4671 4649 }
4672 4650
4673 4651 /* if bytes left in the FIFO another transfer is needed */
4674 4652 if (!(ECR_READ(pp) & ECPP_FIFO_EMPTY)) {
4675 4653 (void) ecpp_backchan_req(pp);
4676 4654 }
4677 4655
4678 4656 qenable(pp->writeq);
4679 4657 }
4680 4658
4681 4659 /*
4682 4660 * Read one byte in the Nibble mode
4683 4661 */
4684 4662 static uchar_t
4685 4663 nibble_peripheral2host(struct ecppunit *pp, uint8_t *byte)
4686 4664 {
4687 4665 uint8_t n[2]; /* two nibbles */
4688 4666 int i;
4689 4667
4690 4668 /*
4691 4669 * One byte is made of two nibbles
4692 4670 */
4693 4671 for (i = 0; i < 2; i++) {
4694 4672 /* Event 7, 12: host asserts nAutoFd to move to read a nibble */
4695 4673 DCR_WRITE(pp, ECPP_nINIT | ECPP_AFX);
4696 4674
4697 4675 /* Event 8: peripheral puts data on the status lines */
4698 4676
4699 4677 /* Event 9: peripheral asserts nAck, data available */
4700 4678 if (wait_dsr(pp, ECPP_nACK, 0, 35000) < 0) {
4701 4679 ecpp_error(pp->dip,
4702 4680 "nibble_periph2host(%d): failed event 9 %x\n",
4703 4681 i + 1, DSR_READ(pp));
4704 4682 (void) ecpp_1284_termination(pp);
4705 4683 return (FAILURE);
4706 4684 }
4707 4685
4708 4686 n[i] = DSR_READ(pp); /* get a nibble */
4709 4687
4710 4688 /* Event 10: host deasserts nAutoFd to say it grabbed data */
4711 4689 DCR_WRITE(pp, ECPP_nINIT);
4712 4690
4713 4691 /* (2) Event 13: peripheral asserts PE - end of data phase */
4714 4692
4715 4693 /* Event 11: peripheral deasserts nAck to finish handshake */
4716 4694 if (wait_dsr(pp, ECPP_nACK, ECPP_nACK, 35000) < 0) {
4717 4695 ecpp_error(pp->dip,
4718 4696 "nibble_periph2host(%d): failed event 11 %x\n",
4719 4697 i + 1, DSR_READ(pp));
4720 4698 (void) ecpp_1284_termination(pp);
4721 4699 return (FAILURE);
4722 4700 }
4723 4701 }
4724 4702
4725 4703 /* extract data byte from two nibbles - optimized formula */
4726 4704 *byte = ((((n[1] & ~ECPP_nACK) << 1) | (~n[1] & ECPP_nBUSY)) & 0xf0) |
4727 4705 ((((n[0] & ~ECPP_nACK) >> 3) | ((~n[0] & ECPP_nBUSY) >> 4)) & 0x0f);
4728 4706
4729 4707 pp->ibytes[ECPP_NIBBLE_MODE]++;
4730 4708 return (SUCCESS);
4731 4709 }
4732 4710
4733 4711 /*
4734 4712 * process data transfers requested by the peripheral
4735 4713 */
4736 4714 static uint_t
4737 4715 ecpp_peripheral2host(struct ecppunit *pp)
4738 4716 {
4739 4717 if (!canputnext(pp->readq)) {
4740 4718 ecpp_error(pp->dip, "ecpp_peripheral2host: readq full\n");
4741 4719 return (SUCCESS);
4742 4720 }
4743 4721
4744 4722 switch (pp->backchannel) {
4745 4723 case ECPP_CENTRONICS:
4746 4724 /* no backchannel */
4747 4725 return (SUCCESS);
4748 4726
4749 4727 case ECPP_NIBBLE_MODE:
4750 4728 ASSERT(pp->current_mode == ECPP_NIBBLE_MODE);
4751 4729
4752 4730 /*
4753 4731 * Event 20: Host sets nAutoFd high to ack request
4754 4732 */
4755 4733 DCR_WRITE(pp, ECPP_nINIT);
4756 4734
4757 4735 /* Event 21: Periph sets PError low to ack host */
4758 4736 if (wait_dsr(pp, ECPP_PE, 0, 35000) < 0) {
4759 4737 ecpp_error(pp->dip,
4760 4738 "ecpp_periph2host: failed event 21 %x\n",
4761 4739 DSR_READ(pp));
4762 4740 (void) ecpp_1284_termination(pp);
4763 4741 return (FAILURE);
4764 4742 }
4765 4743
4766 4744 pp->current_phase = ECPP_PHASE_NIBT_AVAIL;
4767 4745
4768 4746 /* this routine will read the data in Nibble mode */
4769 4747 return (ecpp_idle_phase(pp));
4770 4748
4771 4749 case ECPP_ECP_MODE:
4772 4750 if ((pp->current_phase == ECPP_PHASE_ECP_FWD_IDLE) &&
4773 4751 (ecp_forward2reverse(pp) == FAILURE)) {
4774 4752 return (FAILURE);
4775 4753 }
4776 4754
4777 4755 return (ecp_peripheral2host(pp)); /* start the transfer */
4778 4756
4779 4757 case ECPP_DIAG_MODE: {
4780 4758 mblk_t *mp;
4781 4759 int i;
4782 4760
4783 4761 if (ECR_READ(pp) & ECPP_FIFO_EMPTY) {
4784 4762 ecpp_error(pp->dip, "ecpp_periph2host: fifo empty\n");
4785 4763 return (SUCCESS);
4786 4764 }
4787 4765
4788 4766 /* allocate the FIFO size */
4789 4767 if ((mp = allocb(ECPP_FIFO_SZ, BPRI_MED)) == NULL) {
4790 4768 ecpp_error(pp->dip,
4791 4769 "ecpp_periph2host: allocb FAILURE.\n");
4792 4770 return (FAILURE);
4793 4771 }
4794 4772
4795 4773 /*
4796 4774 * For the time being just read it byte by byte
4797 4775 */
4798 4776 i = ECPP_FIFO_SZ;
4799 4777 while (i-- && (!(ECR_READ(pp) & ECPP_FIFO_EMPTY))) {
4800 4778 *mp->b_wptr++ = TFIFO_READ(pp);
4801 4779 drv_usecwait(1); /* ECR is sometimes slow to update */
4802 4780 }
4803 4781
4804 4782 if (canputnext(pp->readq)) {
4805 4783 mutex_exit(&pp->umutex);
4806 4784 mp->b_datap->db_type = M_DATA;
4807 4785 ecpp_error(pp->dip,
4808 4786 "ecpp_periph2host: sending %d bytes\n",
4809 4787 mp->b_wptr - mp->b_rptr);
4810 4788 putnext(pp->readq, mp);
4811 4789 mutex_enter(&pp->umutex);
4812 4790 return (SUCCESS);
4813 4791 } else {
4814 4792 ecpp_error(pp->dip,
4815 4793 "ecpp_periph2host: !canputnext data lost\n");
4816 4794 freemsg(mp);
4817 4795 return (FAILURE);
4818 4796 }
4819 4797 }
4820 4798
4821 4799 default:
4822 4800 ecpp_error(pp->dip, "ecpp_peripheraltohost: illegal back");
4823 4801 return (FAILURE);
4824 4802 }
4825 4803 }
4826 4804
4827 4805 /*
4828 4806 * Negotiate from ECP Forward Idle to Reverse Idle Phase
4829 4807 *
4830 4808 * (manipulations with dcr/ecr are according to ECP Specification)
4831 4809 */
4832 4810 static int
4833 4811 ecp_forward2reverse(struct ecppunit *pp)
4834 4812 {
4835 4813 ASSERT(pp->current_mode == ECPP_ECP_MODE &&
4836 4814 pp->current_phase == ECPP_PHASE_ECP_FWD_IDLE);
4837 4815
4838 4816 /* place port into PS2 mode */
4839 4817 ECR_WRITE(pp, ECR_mode_001 | ECPP_INTR_SRV | ECPP_INTR_MASK);
4840 4818
4841 4819 /* set direction bit (DCR3-0 must be 0100 - National) */
4842 4820 DCR_WRITE(pp, ECPP_REV_DIR | ECPP_nINIT);
4843 4821
4844 4822 /* enable hardware assist */
4845 4823 ECR_WRITE(pp, ECR_mode_011 | ECPP_INTR_SRV | ECPP_INTR_MASK);
4846 4824
4847 4825 drv_usecwait(1); /* Tp(ecp) = 0.5us */
4848 4826
4849 4827 /* Event 39: host sets nInit low */
4850 4828 DCR_WRITE(pp, ECPP_REV_DIR);
4851 4829
4852 4830 /* Event 40: peripheral sets PError low */
4853 4831
4854 4832 pp->current_phase = ECPP_PHASE_ECP_REV_IDLE;
4855 4833
4856 4834 ecpp_error(pp->dip, "ecp_forward2reverse ok\n");
4857 4835
4858 4836 return (SUCCESS);
4859 4837 }
4860 4838
4861 4839 /*
4862 4840 * Negotiate from ECP Reverse Idle to Forward Idle Phase
4863 4841 *
4864 4842 * (manipulations with dcr/ecr are according to ECP Specification)
4865 4843 */
4866 4844 static int
4867 4845 ecp_reverse2forward(struct ecppunit *pp)
4868 4846 {
4869 4847 ASSERT(pp->current_mode == ECPP_ECP_MODE &&
4870 4848 pp->current_phase == ECPP_PHASE_ECP_REV_IDLE);
4871 4849
4872 4850 /* Event 47: host deasserts nInit */
4873 4851 DCR_WRITE(pp, ECPP_REV_DIR | ECPP_nINIT);
4874 4852
4875 4853 /*
4876 4854 * Event 48: peripheral deasserts nAck
4877 4855 * Event 49: peripheral asserts PError
4878 4856 */
4879 4857 if (wait_dsr(pp, ECPP_PE, ECPP_PE, 35000) < 0) {
4880 4858 ecpp_error(pp->dip,
4881 4859 "ecp_reverse2forward: failed event 49 %x\n", DSR_READ(pp));
4882 4860 (void) ecpp_1284_termination(pp);
4883 4861 return (FAILURE);
4884 4862 }
4885 4863
4886 4864 /* place port into PS2 mode */
4887 4865 ECR_WRITE(pp, ECR_mode_001 | ECPP_INTR_SRV | ECPP_INTR_MASK);
4888 4866
4889 4867 /* clear direction bit */
4890 4868 DCR_WRITE(pp, ECPP_nINIT);
4891 4869
4892 4870 /* reenable hardware assist */
4893 4871 ECR_WRITE(pp, ECR_mode_011 | ECPP_INTR_SRV | ECPP_INTR_MASK);
4894 4872
4895 4873 pp->current_phase = ECPP_PHASE_ECP_FWD_IDLE;
4896 4874
4897 4875 ecpp_error(pp->dip, "ecp_reverse2forward ok\n");
4898 4876
4899 4877 return (SUCCESS);
4900 4878 }
4901 4879
4902 4880 /*
4903 4881 * Default negotiation chooses the best mode supported by peripheral
4904 4882 * Note that backchannel mode may be different from forward mode
4905 4883 */
4906 4884 static void
4907 4885 ecpp_default_negotiation(struct ecppunit *pp)
4908 4886 {
4909 4887 if (!noecp && (ecpp_mode_negotiation(pp, ECPP_ECP_MODE) == SUCCESS)) {
4910 4888 /* 1284 compatible device */
4911 4889 pp->io_mode = (pp->fast_compat == TRUE) ? ECPP_DMA : ECPP_PIO;
4912 4890 return;
4913 4891 } else if (ecpp_mode_negotiation(pp, ECPP_NIBBLE_MODE) == SUCCESS) {
4914 4892 /* 1284 compatible device */
4915 4893 pp->io_mode = (pp->fast_compat == TRUE) ? ECPP_DMA : ECPP_PIO;
4916 4894 } else {
4917 4895 /* Centronics device */
4918 4896 pp->io_mode =
4919 4897 (pp->fast_centronics == TRUE) ? ECPP_DMA : ECPP_PIO;
4920 4898 }
4921 4899 ECPP_CONFIG_MODE(pp);
4922 4900 }
4923 4901
4924 4902 /*
4925 4903 * Negotiate to the mode indicated by newmode
4926 4904 */
4927 4905 static int
4928 4906 ecpp_mode_negotiation(struct ecppunit *pp, uchar_t newmode)
4929 4907 {
4930 4908 /* any other mode is impossible */
4931 4909 ASSERT(pp->current_mode == ECPP_CENTRONICS ||
4932 4910 pp->current_mode == ECPP_COMPAT_MODE ||
4933 4911 pp->current_mode == ECPP_NIBBLE_MODE ||
4934 4912 pp->current_mode == ECPP_ECP_MODE ||
4935 4913 pp->current_mode == ECPP_DIAG_MODE);
4936 4914
4937 4915 if (pp->current_mode == newmode) {
4938 4916 return (SUCCESS);
4939 4917 }
4940 4918
4941 4919 /* termination from ECP is only allowed from the Forward Idle Phase */
4942 4920 if ((pp->current_mode == ECPP_ECP_MODE) &&
4943 4921 (pp->current_phase != ECPP_PHASE_ECP_FWD_IDLE)) {
4944 4922 /* this may break into Centronics */
4945 4923 (void) ecp_reverse2forward(pp);
4946 4924 }
4947 4925
4948 4926 switch (newmode) {
4949 4927 case ECPP_CENTRONICS:
4950 4928 (void) ecpp_1284_termination(pp);
4951 4929
4952 4930 /* put superio into PIO mode */
4953 4931 ECR_WRITE(pp, ECR_mode_001 | ECPP_INTR_MASK | ECPP_INTR_SRV);
4954 4932
4955 4933 pp->current_mode = ECPP_CENTRONICS;
4956 4934 pp->backchannel = ECPP_CENTRONICS;
4957 4935 ECPP_CONFIG_MODE(pp);
4958 4936
4959 4937 pp->to_mode[pp->current_mode]++;
4960 4938 return (SUCCESS);
4961 4939
4962 4940 case ECPP_COMPAT_MODE:
4963 4941 /* ECPP_COMPAT_MODE should support Nibble as a backchannel */
4964 4942 if (pp->current_mode == ECPP_NIBBLE_MODE) {
4965 4943 if (ecpp_1284_termination(pp) == SUCCESS) {
4966 4944 pp->current_mode = ECPP_COMPAT_MODE;
4967 4945 pp->backchannel = ECPP_NIBBLE_MODE;
4968 4946 ECPP_CONFIG_MODE(pp);
4969 4947 pp->to_mode[pp->current_mode]++;
4970 4948 return (SUCCESS);
4971 4949 } else {
4972 4950 return (FAILURE);
4973 4951 }
4974 4952 }
4975 4953
4976 4954 if ((nibble_negotiation(pp) == SUCCESS) &&
4977 4955 (ecpp_1284_termination(pp) == SUCCESS)) {
4978 4956 pp->backchannel = ECPP_NIBBLE_MODE;
4979 4957 pp->current_mode = ECPP_COMPAT_MODE;
4980 4958 ECPP_CONFIG_MODE(pp);
4981 4959 pp->to_mode[pp->current_mode]++;
4982 4960 return (SUCCESS);
4983 4961 } else {
4984 4962 return (FAILURE);
4985 4963 }
4986 4964
4987 4965 case ECPP_NIBBLE_MODE:
4988 4966 if (nibble_negotiation(pp) == FAILURE) {
4989 4967 return (FAILURE);
4990 4968 }
4991 4969
4992 4970 pp->backchannel = ECPP_NIBBLE_MODE;
4993 4971 ECPP_CONFIG_MODE(pp);
4994 4972 pp->to_mode[pp->current_mode]++;
4995 4973
4996 4974 return (SUCCESS);
4997 4975
4998 4976 case ECPP_ECP_MODE:
4999 4977 if (pp->noecpregs)
5000 4978 return (FAILURE);
5001 4979 if (ecp_negotiation(pp) == FAILURE) {
5002 4980 return (FAILURE);
5003 4981 }
5004 4982
5005 4983 /*
5006 4984 * National says CTR[3:0] should be 0100b before moving to 011
5007 4985 */
5008 4986 DCR_WRITE(pp, ECPP_nINIT);
5009 4987
5010 4988 if (ecr_write(pp, ECR_mode_011 |
5011 4989 ECPP_INTR_MASK | ECPP_INTR_SRV) == FAILURE) {
5012 4990 ecpp_error(pp->dip, "mode_nego:ECP: failed w/ecr\n");
5013 4991 return (FAILURE);
5014 4992 }
5015 4993
5016 4994 ECPP_CONFIG_MODE(pp);
5017 4995 pp->to_mode[pp->current_mode]++;
5018 4996
5019 4997 return (SUCCESS);
5020 4998
5021 4999 case ECPP_DIAG_MODE:
5022 5000 /*
5023 5001 * In DIAG mode application can do nasty things(e.g drive pins)
5024 5002 * To keep peripheral sane, terminate to Compatibility mode
5025 5003 */
5026 5004 (void) ecpp_1284_termination(pp);
5027 5005
5028 5006 /* put superio into TFIFO mode */
5029 5007 if (ecr_write(pp, ECR_mode_001 |
5030 5008 ECPP_INTR_MASK | ECPP_INTR_SRV) == FAILURE) {
5031 5009 ecpp_error(pp->dip, "put to TFIFO: failed w/ecr\n");
5032 5010 return (FAILURE);
5033 5011 }
5034 5012
5035 5013 pp->current_mode = ECPP_DIAG_MODE;
5036 5014 pp->backchannel = ECPP_DIAG_MODE;
5037 5015 ECPP_CONFIG_MODE(pp);
5038 5016 pp->to_mode[pp->current_mode]++;
5039 5017
5040 5018 return (SUCCESS);
5041 5019
5042 5020 default:
5043 5021 ecpp_error(pp->dip,
5044 5022 "ecpp_mode_negotiation: mode %d not supported\n", newmode);
5045 5023 return (FAILURE);
5046 5024 }
5047 5025 }
5048 5026
5049 5027 /*
5050 5028 * Standard (9.1): Peripheral data is available only when the host places
5051 5029 * the interface in a mode capable of peripheral-to-host data transfer.
5052 5030 * This requires the host periodically to place the interface in such a mode.
5053 5031 * Polling can be eliminated by leaving the interface in an 1284 idle phase.
5054 5032 */
5055 5033 static uchar_t
5056 5034 ecpp_idle_phase(struct ecppunit *pp)
5057 5035 {
5058 5036 uchar_t rval = FAILURE;
5059 5037
5060 5038 /*
5061 5039 * If there is no space on the read queue, do not reverse channel
5062 5040 */
5063 5041 if (!canputnext(pp->readq)) {
5064 5042 ecpp_error(pp->dip, "ecpp_idle_phase: readq full\n");
5065 5043 return (SUCCESS);
5066 5044 }
5067 5045
5068 5046 switch (pp->backchannel) {
5069 5047 case ECPP_CENTRONICS:
5070 5048 case ECPP_COMPAT_MODE:
5071 5049 case ECPP_DIAG_MODE:
5072 5050 /* nothing */
5073 5051 ecpp_error(pp->dip, "ecpp_idle_phase: compat idle\n");
5074 5052 return (SUCCESS);
5075 5053
5076 5054 case ECPP_NIBBLE_MODE:
5077 5055 /*
5078 5056 * read as much data as possible, ending up in either
5079 5057 * Reverse Idle or Host Busy Data Available phase
5080 5058 */
5081 5059 ecpp_error(pp->dip, "ecpp_idle_phase: nibble backchannel\n");
5082 5060 if ((pp->current_mode != ECPP_NIBBLE_MODE) &&
5083 5061 (ecpp_mode_negotiation(pp, ECPP_NIBBLE_MODE) == FAILURE)) {
5084 5062 break;
5085 5063 }
5086 5064
5087 5065 rval = read_nibble_backchan(pp);
5088 5066
5089 5067 /* put interface into Reverse Idle phase */
5090 5068 if (pp->current_phase == ECPP_PHASE_NIBT_NAVAIL &&
5091 5069 canputnext(pp->readq)) {
5092 5070 ecpp_error(pp->dip, "ecpp_idle_phase: going revidle\n");
5093 5071
5094 5072 /*
5095 5073 * Event 7: host asserts nAutoFd
5096 5074 * enable nAck interrupt to get a backchannel request
5097 5075 */
5098 5076 DCR_WRITE(pp, ECPP_nINIT | ECPP_AFX | ECPP_INTR_EN);
5099 5077
5100 5078 ECPP_UNMASK_INTR(pp);
5101 5079 }
5102 5080
5103 5081 break;
5104 5082
5105 5083 case ECPP_ECP_MODE:
5106 5084 /*
5107 5085 * if data is already available, request the backchannel xfer
5108 5086 * otherwise stay in Forward Idle and enable nErr interrupts
5109 5087 */
5110 5088 ecpp_error(pp->dip, "ecpp_idle_phase: ECP forward\n");
5111 5089
5112 5090 ASSERT(pp->current_phase == ECPP_PHASE_ECP_FWD_IDLE ||
5113 5091 pp->current_phase == ECPP_PHASE_ECP_REV_IDLE);
5114 5092
5115 5093 /* put interface into Forward Idle phase */
5116 5094 if ((pp->current_phase == ECPP_PHASE_ECP_REV_IDLE) &&
5117 5095 (ecp_reverse2forward(pp) == FAILURE)) {
5118 5096 return (FAILURE);
5119 5097 }
5120 5098
5121 5099 /*
5122 5100 * if data already available, put backchannel request on the wq
5123 5101 * otherwise enable nErr interrupts
5124 5102 */
5125 5103 if ((DSR_READ(pp) & ECPP_nERR) == 0) {
5126 5104 (void) ecpp_backchan_req(pp);
5127 5105 } else {
5128 5106 ECR_WRITE(pp,
5129 5107 ECR_READ(pp) & ~ECPP_INTR_MASK | ECPP_INTR_SRV);
5130 5108
5131 5109 ECPP_UNMASK_INTR(pp);
5132 5110 }
5133 5111
5134 5112 return (SUCCESS);
5135 5113
5136 5114 default:
5137 5115 ecpp_error(pp->dip, "ecpp_idle_phase: illegal backchannel");
5138 5116 }
5139 5117
5140 5118 return (rval);
5141 5119 }
5142 5120
5143 5121 /*
5144 5122 * This routine will leave the port in ECPP_PHASE_NIBT_REVIDLE
5145 5123 * Due to flow control, though, it may stop at ECPP_PHASE_NIBT_AVAIL,
5146 5124 * and continue later as the user consumes data from the read queue
5147 5125 *
5148 5126 * The current phase should be NIBT_AVAIL or NIBT_NAVAIL
5149 5127 * If some events fail during transfer, termination puts link
5150 5128 * to Compatibility mode and FAILURE is returned
5151 5129 */
5152 5130 static int
5153 5131 read_nibble_backchan(struct ecppunit *pp)
5154 5132 {
5155 5133 mblk_t *mp;
5156 5134 int i;
5157 5135 int rval = SUCCESS;
5158 5136
5159 5137 ASSERT(pp->current_mode == ECPP_NIBBLE_MODE);
5160 5138
5161 5139 pp->current_phase = (DSR_READ(pp) & (ECPP_nERR | ECPP_PE))
5162 5140 ? ECPP_PHASE_NIBT_NAVAIL : ECPP_PHASE_NIBT_AVAIL;
5163 5141
5164 5142 ecpp_error(pp->dip, "read_nibble_backchan: %x\n", DSR_READ(pp));
5165 5143
5166 5144 /*
5167 5145 * While data is available, read it in NIBBLE_REV_BLKSZ byte chunks
5168 5146 * and send up the stream
5169 5147 */
5170 5148 while (pp->current_phase == ECPP_PHASE_NIBT_AVAIL && rval == SUCCESS) {
5171 5149 /* see if there's space on the queue */
5172 5150 if (!canputnext(pp->readq)) {
5173 5151 ecpp_error(pp->dip,
5174 5152 "read_nibble_backchan: canputnext failed\n");
5175 5153 return (SUCCESS);
5176 5154 }
5177 5155
5178 5156 if ((mp = allocb(NIBBLE_REV_BLKSZ, BPRI_MED)) == NULL) {
5179 5157 ecpp_error(pp->dip,
5180 5158 "read_nibble_backchan: allocb failed\n");
5181 5159 return (SUCCESS);
5182 5160 }
5183 5161
5184 5162 /* read a chunk of data from the peripheral byte by byte */
5185 5163 i = NIBBLE_REV_BLKSZ;
5186 5164 while (i-- && !(DSR_READ(pp) & ECPP_nERR)) {
5187 5165 if (nibble_peripheral2host(pp, mp->b_wptr) != SUCCESS) {
5188 5166 rval = FAILURE;
5189 5167 break;
5190 5168 }
5191 5169 mp->b_wptr++;
5192 5170 }
5193 5171
5194 5172 pp->current_phase = (DSR_READ(pp) & (ECPP_nERR | ECPP_PE))
5195 5173 ? ECPP_PHASE_NIBT_NAVAIL
5196 5174 : ECPP_PHASE_NIBT_AVAIL;
5197 5175
5198 5176 if (mp->b_wptr - mp->b_rptr > 0) {
5199 5177 ecpp_error(pp->dip,
5200 5178 "read_nibble_backchan: sending %d bytes\n",
5201 5179 mp->b_wptr - mp->b_rptr);
5202 5180 pp->nread = 0;
5203 5181 mutex_exit(&pp->umutex);
5204 5182 putnext(pp->readq, mp);
5205 5183 mutex_enter(&pp->umutex);
5206 5184 } else {
5207 5185 freemsg(mp);
5208 5186 }
5209 5187 }
5210 5188
5211 5189 return (rval);
5212 5190 }
5213 5191
5214 5192 /*
5215 5193 * 'Request Device ID using nibble mode' negotiation
5216 5194 */
5217 5195 static int
5218 5196 devidnib_negotiation(struct ecppunit *pp)
5219 5197 {
5220 5198 uint8_t dsr;
5221 5199
5222 5200 if (ecpp_1284_negotiation(pp,
5223 5201 ECPP_XREQ_NIBBLE | ECPP_XREQ_ID, &dsr) == FAILURE) {
5224 5202 return (FAILURE);
5225 5203 }
5226 5204
5227 5205 /*
5228 5206 * If peripheral has data available, PE and nErr will
5229 5207 * be set low at Event 5 & 6.
5230 5208 */
5231 5209 if ((dsr & (ECPP_PE | ECPP_nERR)) == 0) {
5232 5210 pp->current_phase = ECPP_PHASE_NIBT_AVAIL;
5233 5211 } else {
5234 5212 pp->current_phase = ECPP_PHASE_NIBT_NAVAIL;
5235 5213 }
5236 5214
5237 5215 ecpp_error(pp->dip, "ecpp_devidnib_nego: current_phase=%x\n",
5238 5216 pp->current_phase);
5239 5217
5240 5218 /* successful negotiation into Nibble mode */
5241 5219 pp->current_mode = ECPP_NIBBLE_MODE;
5242 5220 pp->backchannel = ECPP_NIBBLE_MODE;
5243 5221
5244 5222 ecpp_error(pp->dip, "ecpp_devidnib_nego: ok\n");
5245 5223
5246 5224 return (SUCCESS);
5247 5225 }
5248 5226
5249 5227 /*
5250 5228 * Read 1284 device ID sequence
5251 5229 *
5252 5230 * This function should be called two times:
5253 5231 * 1) ecpp_getdevid(pp, NULL, &len) - to retrieve ID length;
5254 5232 * 2) ecpp_getdevid(pp, buffer, &len) - to read len bytes into buffer
5255 5233 *
5256 5234 * After 2) port is in Compatible mode
5257 5235 * If the caller fails to make second call, it must reset port to Centronics
5258 5236 *
5259 5237 */
5260 5238 static int
5261 5239 ecpp_getdevid(struct ecppunit *pp, uint8_t *id, int *lenp, int mode)
5262 5240 {
5263 5241 uint8_t lenhi, lenlo;
5264 5242 uint8_t dsr;
5265 5243 int i;
5266 5244
5267 5245 switch (mode) {
5268 5246 case ECPP_NIBBLE_MODE:
5269 5247 /* negotiate only if neccessary */
5270 5248 if ((pp->current_mode != mode) || (id == NULL)) {
5271 5249 if (devidnib_negotiation(pp) == FAILURE) {
5272 5250 return (EIO);
5273 5251 }
5274 5252 }
5275 5253
5276 5254 if (pp->current_phase != ECPP_PHASE_NIBT_AVAIL) {
5277 5255 return (EIO);
5278 5256 }
5279 5257
5280 5258 /*
5281 5259 * Event 14: Host tristates data bus, peripheral
5282 5260 * asserts nERR if data available, usually the
5283 5261 * status bits (7-0) and requires two reads since
5284 5262 * only nibbles are transfered.
5285 5263 */
5286 5264 dsr = DSR_READ(pp);
5287 5265
5288 5266 if (id == NULL) {
5289 5267 /*
5290 5268 * first two bytes are the length of the sequence
5291 5269 * (incl. these bytes)
5292 5270 * first byte is MSB
5293 5271 */
5294 5272 if ((dsr & ECPP_nERR) ||
5295 5273 (nibble_peripheral2host(pp, &lenhi) == FAILURE) ||
5296 5274 (dsr & ECPP_nERR) ||
5297 5275 (nibble_peripheral2host(pp, &lenlo) == FAILURE)) {
5298 5276 ecpp_error(pp->dip,
5299 5277 "ecpp_getdevid: id length read error\n");
5300 5278 return (EIO);
5301 5279 }
5302 5280
5303 5281 *lenp = (lenhi << 8) | (lenlo);
5304 5282
5305 5283 ecpp_error(pp->dip,
5306 5284 "ecpp_getdevid: id length = %d\n", *lenp);
5307 5285
5308 5286 if (*lenp < 2) {
5309 5287 return (EIO);
5310 5288 }
5311 5289 } else {
5312 5290 /*
5313 5291 * read the rest of the data
5314 5292 */
5315 5293 i = *lenp;
5316 5294 while (i && ((dsr & ECPP_nERR) == 0)) {
5317 5295 if (nibble_peripheral2host(pp, id++) == FAILURE)
5318 5296 break;
5319 5297
5320 5298 i--;
5321 5299 dsr = DSR_READ(pp);
5322 5300 }
5323 5301 ecpp_error(pp->dip,
5324 5302 "ecpp_getdevid: read %d bytes\n", *lenp - i);
5325 5303
5326 5304 /*
5327 5305 * 1284: After receiving the sequence, the host is
5328 5306 * required to return the link to the Compatibility mode
5329 5307 */
5330 5308 (void) ecpp_1284_termination(pp);
5331 5309 }
5332 5310
5333 5311 break;
5334 5312
5335 5313 /* Other modes are not yet supported */
5336 5314 default:
5337 5315 return (EINVAL);
5338 5316 }
5339 5317
5340 5318 return (0);
5341 5319 }
5342 5320
5343 5321 /*
5344 5322 * Various hardware support
5345 5323 *
5346 5324 * First define some stubs for functions that do nothing
5347 5325 */
5348 5326
5349 5327 /*ARGSUSED*/
5350 5328 static void
5351 5329 empty_config_mode(struct ecppunit *pp)
5352 5330 {
5353 5331 }
5354 5332
5355 5333 /*ARGSUSED*/
5356 5334 static void
5357 5335 empty_mask_intr(struct ecppunit *pp)
5358 5336 {
5359 5337 }
5360 5338
5361 5339 #if defined(__x86)
5362 5340 static size_t
5363 5341 x86_getcnt(struct ecppunit *pp)
5364 5342 {
5365 5343 int count;
5366 5344
5367 5345 (void) ddi_dmae_getcnt(pp->dip, pp->uh.x86.chn, &count);
5368 5346 return (count);
5369 5347 }
5370 5348 #endif
5371 5349
5372 5350 /*
5373 5351 *
5374 5352 * National PC87332 and PC97317 SuperIOs support routines
5375 5353 * These chips are used in PCI-based Darwin, Quark, Quasar, Excalibur
5376 5354 * and use EBus DMA facilities (Cheerio or RIO)
5377 5355 *
5378 5356 */
5379 5357
5380 5358 static int
5381 5359 pc87332_map_regs(struct ecppunit *pp)
5382 5360 {
5383 5361 if (ddi_regs_map_setup(pp->dip, 1, (caddr_t *)&pp->uh.ebus.c_reg, 0,
5384 5362 sizeof (struct config_reg), &acc_attr,
5385 5363 &pp->uh.ebus.c_handle) != DDI_SUCCESS) {
5386 5364 ecpp_error(pp->dip, "pc87332_map_regs: failed c_reg\n");
5387 5365 goto fail;
5388 5366 }
5389 5367
5390 5368 if (ddi_regs_map_setup(pp->dip, 0, (caddr_t *)&pp->i_reg, 0,
5391 5369 sizeof (struct info_reg), &acc_attr, &pp->i_handle)
5392 5370 != DDI_SUCCESS) {
5393 5371 ecpp_error(pp->dip, "pc87332_map_regs: failed i_reg\n");
5394 5372 goto fail;
5395 5373 }
5396 5374
5397 5375 if (ddi_regs_map_setup(pp->dip, 0, (caddr_t *)&pp->f_reg, 0x400,
5398 5376 sizeof (struct fifo_reg), &acc_attr, &pp->f_handle)
5399 5377 != DDI_SUCCESS) {
5400 5378 ecpp_error(pp->dip, "pc87332_map_regs: failed f_reg\n");
5401 5379 goto fail;
5402 5380 }
5403 5381
5404 5382 if (ddi_regs_map_setup(pp->dip, 2, (caddr_t *)&pp->uh.ebus.dmac, 0,
5405 5383 sizeof (struct cheerio_dma_reg), &acc_attr,
5406 5384 &pp->uh.ebus.d_handle) != DDI_SUCCESS) {
5407 5385 ecpp_error(pp->dip, "pc87332_map_regs: failed dmac\n");
5408 5386 goto fail;
5409 5387 }
5410 5388
5411 5389 return (SUCCESS);
5412 5390
5413 5391 fail:
5414 5392 pc87332_unmap_regs(pp);
5415 5393 return (FAILURE);
5416 5394 }
5417 5395
5418 5396 static void
5419 5397 pc87332_unmap_regs(struct ecppunit *pp)
5420 5398 {
5421 5399 if (pp->uh.ebus.c_handle) {
5422 5400 ddi_regs_map_free(&pp->uh.ebus.c_handle);
5423 5401 }
5424 5402 if (pp->uh.ebus.d_handle) {
5425 5403 ddi_regs_map_free(&pp->uh.ebus.d_handle);
5426 5404 }
5427 5405 if (pp->i_handle) {
5428 5406 ddi_regs_map_free(&pp->i_handle);
5429 5407 }
5430 5408 if (pp->f_handle) {
5431 5409 ddi_regs_map_free(&pp->f_handle);
5432 5410 }
5433 5411 }
5434 5412
5435 5413 static uint8_t
5436 5414 pc87332_read_config_reg(struct ecppunit *pp, uint8_t reg_num)
5437 5415 {
5438 5416 uint8_t retval;
5439 5417
5440 5418 PP_PUTB(pp->uh.ebus.c_handle, &pp->uh.ebus.c_reg->index, reg_num);
5441 5419 retval = PP_GETB(pp->uh.ebus.c_handle, &pp->uh.ebus.c_reg->data);
5442 5420
5443 5421 return (retval);
5444 5422 }
5445 5423
5446 5424 static void
5447 5425 pc87332_write_config_reg(struct ecppunit *pp, uint8_t reg_num, uint8_t val)
5448 5426 {
5449 5427 PP_PUTB(pp->uh.ebus.c_handle, &pp->uh.ebus.c_reg->index, reg_num);
5450 5428 PP_PUTB(pp->uh.ebus.c_handle, &pp->uh.ebus.c_reg->data, val);
5451 5429
5452 5430 /*
5453 5431 * second write to this register is needed. the register behaves as
5454 5432 * a fifo. the first value written goes to the data register. the
5455 5433 * second write pushes the initial value to the register indexed.
5456 5434 */
5457 5435
5458 5436 PP_PUTB(pp->uh.ebus.c_handle, &pp->uh.ebus.c_reg->data, val);
5459 5437 }
5460 5438
5461 5439 static int
5462 5440 pc87332_config_chip(struct ecppunit *pp)
5463 5441 {
5464 5442 uint8_t pmc, fcr;
5465 5443
5466 5444 pp->current_phase = ECPP_PHASE_INIT;
5467 5445
5468 5446 /* ECP DMA configuration bit (PMC4) must be set */
5469 5447 pmc = pc87332_read_config_reg(pp, PMC);
5470 5448 if (!(pmc & PC87332_PMC_ECP_DMA_CONFIG)) {
5471 5449 pc87332_write_config_reg(pp, PMC,
5472 5450 pmc | PC87332_PMC_ECP_DMA_CONFIG);
5473 5451 }
5474 5452
5475 5453 /*
5476 5454 * The Parallel Port Multiplexor pins must be driven.
5477 5455 * Check to see if FCR3 is zero, if not clear FCR3.
5478 5456 */
5479 5457 fcr = pc87332_read_config_reg(pp, FCR);
5480 5458 if (fcr & PC87332_FCR_PPM_FLOAT_CTL) {
5481 5459 pc87332_write_config_reg(pp, FCR,
5482 5460 fcr & ~PC87332_FCR_PPM_FLOAT_CTL);
5483 5461 }
5484 5462
5485 5463 /*
5486 5464 * clear bits 3-0 in CTR (aka DCR) prior to enabling ECP mode
5487 5465 * CTR5 can not be cleared in SPP mode, CTR5 will return 1.
5488 5466 * "FAILURE" in this case is ok. Better to use dcr_write()
5489 5467 * to ensure reliable writing to DCR.
5490 5468 */
5491 5469 if (dcr_write(pp, ECPP_DCR_SET | ECPP_nINIT) == FAILURE) {
5492 5470 ecpp_error(pp->dip, "ecpp_config_87332: DCR config\n");
5493 5471 }
5494 5472
5495 5473 /* enable ECP mode, level intr (note that DCR bits 3-0 == 0x0) */
5496 5474 pc87332_write_config_reg(pp, PCR,
5497 5475 PC87332_PCR_INTR_LEVL | PC87332_PCR_ECP_EN);
5498 5476
5499 5477 /* put SuperIO in initial state */
5500 5478 if (ecr_write(pp, ECR_mode_001 |
5501 5479 ECPP_INTR_MASK | ECPP_INTR_SRV) == FAILURE) {
5502 5480 ecpp_error(pp->dip, "ecpp_config_87332: ECR\n");
5503 5481 }
5504 5482
5505 5483 if (dcr_write(pp, ECPP_DCR_SET | ECPP_SLCTIN | ECPP_nINIT) == FAILURE) {
5506 5484 ecpp_error(pp->dip, "ecpp_config_87332: w/DCR failed2.\n");
5507 5485 return (FAILURE);
5508 5486
5509 5487 }
5510 5488 /* we are in centronic mode */
5511 5489 pp->current_mode = ECPP_CENTRONICS;
5512 5490
5513 5491 /* in compatible mode with no data transfer in progress */
5514 5492 pp->current_phase = ECPP_PHASE_C_IDLE;
5515 5493
5516 5494 return (SUCCESS);
5517 5495 }
5518 5496
5519 5497 /*
5520 5498 * A new mode was set, do some mode specific reconfiguration
5521 5499 * in this case - set interrupt characteristic
5522 5500 */
5523 5501 static void
5524 5502 pc87332_config_mode(struct ecppunit *pp)
5525 5503 {
5526 5504 if (COMPAT_PIO(pp)) {
5527 5505 pc87332_write_config_reg(pp, PCR, 0x04);
5528 5506 } else {
5529 5507 pc87332_write_config_reg(pp, PCR, 0x14);
5530 5508 }
5531 5509 }
5532 5510
5533 5511 static int
5534 5512 pc97317_map_regs(struct ecppunit *pp)
5535 5513 {
5536 5514 if (pc87332_map_regs(pp) != SUCCESS) {
5537 5515 return (FAILURE);
5538 5516 }
5539 5517
5540 5518 if (ddi_regs_map_setup(pp->dip, 0, (caddr_t *)&pp->uh.ebus.c2_reg,
5541 5519 0x403, sizeof (struct config2_reg), &acc_attr,
5542 5520 &pp->uh.ebus.c2_handle) != DDI_SUCCESS) {
5543 5521 ecpp_error(pp->dip, "pc97317_map_regs: failed c2_reg\n");
5544 5522 pc87332_unmap_regs(pp);
5545 5523 return (FAILURE);
5546 5524 } else {
5547 5525 return (SUCCESS);
5548 5526 }
5549 5527 }
5550 5528
5551 5529 static void
5552 5530 pc97317_unmap_regs(struct ecppunit *pp)
5553 5531 {
5554 5532 if (pp->uh.ebus.c2_handle) {
5555 5533 ddi_regs_map_free(&pp->uh.ebus.c2_handle);
5556 5534 }
5557 5535
5558 5536 pc87332_unmap_regs(pp);
5559 5537 }
5560 5538
5561 5539 /*
5562 5540 * OBP should configure the PC97317 such that it does not need further
5563 5541 * configuration. Upon sustaining, it may be necessary to examine
5564 5542 * or change the configuration registers. This routine is left in
5565 5543 * the file for that purpose.
5566 5544 */
5567 5545 static int
5568 5546 pc97317_config_chip(struct ecppunit *pp)
5569 5547 {
5570 5548 uint8_t conreg;
5571 5549
5572 5550 /* set the logical device name */
5573 5551 pc87332_write_config_reg(pp, PC97317_CONFIG_DEV_NO, 0x4);
5574 5552
5575 5553 /* SPP Compatibility */
5576 5554 PP_PUTB(pp->uh.ebus.c2_handle,
5577 5555 &pp->uh.ebus.c2_reg->eir, PC97317_CONFIG2_CONTROL2);
5578 5556 PP_PUTB(pp->uh.ebus.c2_handle, &pp->uh.ebus.c2_reg->edr, 0x80);
5579 5557
5580 5558 /* low interrupt polarity */
5581 5559 pc87332_write_config_reg(pp, PC97317_CONFIG_INTR_TYPE, 0x00);
5582 5560
5583 5561 /* ECP mode */
5584 5562 pc87332_write_config_reg(pp, PC97317_CONFIG_PP_CONFIG, 0xf2);
5585 5563
5586 5564 if (dcr_write(pp, ECPP_SLCTIN | ECPP_nINIT) == FAILURE) {
5587 5565 ecpp_error(pp->dip, "pc97317_config_chip: failed w/DCR\n");
5588 5566 }
5589 5567
5590 5568 if (ecr_write(pp, ECR_mode_001 |
5591 5569 ECPP_INTR_MASK | ECPP_INTR_SRV) == FAILURE) {
5592 5570 ecpp_error(pp->dip, "pc97317_config_chip: failed w/ECR\n");
5593 5571 }
5594 5572
5595 5573 #ifdef DEBUG
5596 5574 conreg = pc87332_read_config_reg(pp, PC97317_CONFIG_DEV_NO);
5597 5575 ecpp_error(pp->dip, "97317:conreg7(logical dev)=%x\n", conreg);
5598 5576
5599 5577 conreg = pc87332_read_config_reg(pp, PC97317_CONFIG_BASE_ADDR_MSB);
5600 5578 ecpp_error(pp->dip, "97317:conreg60(addrHi)=%x\n", conreg);
5601 5579
5602 5580 conreg = pc87332_read_config_reg(pp, PC97317_CONFIG_BASE_ADDR_LSB);
5603 5581 ecpp_error(pp->dip, "97317:conreg61(addrLo)=%x\n", conreg);
5604 5582
5605 5583 conreg = pc87332_read_config_reg(pp, PC97317_CONFIG_INTR_SEL);
5606 5584 ecpp_error(pp->dip, "97317:conreg70(IRQL)=%x\n", conreg);
5607 5585
5608 5586 conreg = pc87332_read_config_reg(pp, PC97317_CONFIG_INTR_TYPE);
5609 5587 ecpp_error(pp->dip, "97317:conreg71(intr type)=%x\n", conreg);
5610 5588
5611 5589 conreg = pc87332_read_config_reg(pp, PC97317_CONFIG_ACTIVATE);
5612 5590 ecpp_error(pp->dip, "97317:conreg30(Active)=%x\n", conreg);
5613 5591
5614 5592 conreg = pc87332_read_config_reg(pp, PC97317_CONFIG_IO_RANGE);
5615 5593 ecpp_error(pp->dip, "97317:conreg31(IO Range Check)=%x\n", conreg);
5616 5594
5617 5595 conreg = pc87332_read_config_reg(pp, PC97317_CONFIG_DMA0_CHAN);
5618 5596 ecpp_error(pp->dip, "97317:conreg74(DMA0 Chan)=%x\n", conreg);
5619 5597 conreg = pc87332_read_config_reg(pp, PC97317_CONFIG_DMA1_CHAN);
5620 5598 ecpp_error(pp->dip, "97317:conreg75(DMA1 Chan)=%x\n", conreg);
5621 5599
5622 5600 conreg = pc87332_read_config_reg(pp, PC97317_CONFIG_PP_CONFIG);
5623 5601 ecpp_error(pp->dip, "97317:conregFO(pport conf)=%x\n", conreg);
5624 5602
5625 5603 conreg = pc87332_read_config_reg(pp, PC97317_CONFIG_PP_CONFIG);
5626 5604 ecpp_error(pp->dip, "97317:conregFO(pport conf)=%x\n", conreg);
5627 5605 #endif /* DEBUG */
5628 5606
5629 5607 return (SUCCESS);
5630 5608 }
5631 5609
5632 5610 /*
5633 5611 * A new mode was set, do some mode specific reconfiguration
5634 5612 * in this case - set interrupt polarity
5635 5613 */
5636 5614 static void
5637 5615 pc97317_config_mode(struct ecppunit *pp)
5638 5616 {
5639 5617 /* set the logical device name */
5640 5618 pc87332_write_config_reg(pp, PC97317_CONFIG_DEV_NO, 0x4);
5641 5619
5642 5620 if (COMPAT_PIO(pp) || pp->current_mode == ECPP_NIBBLE_MODE) {
5643 5621 pc87332_write_config_reg(pp, PC97317_CONFIG_INTR_TYPE, 0x02);
5644 5622 } else {
5645 5623 pc87332_write_config_reg(pp, PC97317_CONFIG_INTR_TYPE, 0x00);
5646 5624 }
5647 5625 }
5648 5626
5649 5627 static void
5650 5628 cheerio_mask_intr(struct ecppunit *pp)
5651 5629 {
5652 5630 /* mask Cheerio interrupts */
5653 5631 AND_SET_LONG_R(pp->uh.ebus.d_handle,
5654 5632 &pp->uh.ebus.dmac->csr, ~DCSR_INT_EN);
5655 5633 }
5656 5634
5657 5635 static void
5658 5636 cheerio_unmask_intr(struct ecppunit *pp)
5659 5637 {
5660 5638 /* unmask Cheerio interrupts */
5661 5639 OR_SET_LONG_R(pp->uh.ebus.d_handle,
5662 5640 &pp->uh.ebus.dmac->csr, DCSR_INT_EN | DCSR_TCI_DIS);
5663 5641 }
5664 5642
5665 5643 static int
5666 5644 cheerio_dma_start(struct ecppunit *pp)
5667 5645 {
5668 5646 cheerio_reset_dcsr(pp);
5669 5647 SET_DMAC_BCR(pp, pp->dma_cookie.dmac_size);
5670 5648 SET_DMAC_ACR(pp, pp->dma_cookie.dmac_address);
5671 5649
5672 5650 if (pp->dma_dir == DDI_DMA_READ) {
5673 5651 SET_DMAC_CSR(pp, DCSR_INT_EN | DCSR_EN_CNT | DCSR_EN_DMA |
5674 5652 DCSR_CSR_DRAIN | DCSR_BURST_1 | DCSR_BURST_0 | DCSR_WRITE);
5675 5653 } else {
5676 5654 SET_DMAC_CSR(pp, DCSR_INT_EN | DCSR_EN_CNT | DCSR_EN_DMA |
5677 5655 DCSR_CSR_DRAIN | DCSR_BURST_1 | DCSR_BURST_0);
5678 5656 }
5679 5657
5680 5658 return (SUCCESS);
5681 5659 }
5682 5660
5683 5661 /*
5684 5662 * Note: BCR is reset to 0, so counter should always be read before dma_stop
5685 5663 */
5686 5664 static int
5687 5665 cheerio_dma_stop(struct ecppunit *pp, size_t *countp)
5688 5666 {
5689 5667 uint8_t ecr;
5690 5668
5691 5669 /* disable DMA and byte counter */
5692 5670 AND_SET_LONG_R(pp->uh.ebus.d_handle, &pp->uh.ebus.dmac->csr,
5693 5671 ~(DCSR_EN_DMA | DCSR_EN_CNT| DCSR_INT_EN));
5694 5672
5695 5673 /* ACK and disable the TC interrupt */
5696 5674 OR_SET_LONG_R(pp->uh.ebus.d_handle, &pp->uh.ebus.dmac->csr,
5697 5675 DCSR_TC | DCSR_TCI_DIS);
5698 5676
5699 5677 /* read DMA count if requested */
5700 5678 if (countp) {
5701 5679 *countp = cheerio_getcnt(pp);
5702 5680 }
5703 5681
5704 5682 cheerio_reset_dcsr(pp);
5705 5683 SET_DMAC_BCR(pp, 0);
5706 5684
5707 5685 /* turn off SuperIO's DMA */
5708 5686 ecr = ECR_READ(pp);
5709 5687 if (ecr_write(pp, ecr & ~ECPP_DMA_ENABLE) == FAILURE) {
5710 5688 return (FAILURE);
5711 5689 }
5712 5690
5713 5691 /* Disable SuperIO interrupts and DMA */
5714 5692 ecr = ECR_READ(pp);
5715 5693
5716 5694 return (ecr_write(pp, ecr | ECPP_INTR_SRV));
5717 5695 }
5718 5696
5719 5697 static size_t
5720 5698 cheerio_getcnt(struct ecppunit *pp)
5721 5699 {
5722 5700 return (GET_DMAC_BCR(pp));
5723 5701 }
5724 5702
5725 5703 /*
5726 5704 * Reset the DCSR by first setting the RESET bit to 1. Poll the
5727 5705 * DCSR_CYC_PEND bit to make sure there are no more pending DMA cycles.
5728 5706 * If there are no more pending cycles, clear the RESET bit.
5729 5707 */
5730 5708 static void
5731 5709 cheerio_reset_dcsr(struct ecppunit *pp)
5732 5710 {
5733 5711 int timeout = DMAC_RESET_TIMEOUT;
5734 5712
5735 5713 SET_DMAC_CSR(pp, DCSR_RESET);
5736 5714
5737 5715 while (GET_DMAC_CSR(pp) & DCSR_CYC_PEND) {
5738 5716 if (timeout == 0) {
5739 5717 ecpp_error(pp->dip, "cheerio_reset_dcsr: timeout\n");
5740 5718 break;
5741 5719 } else {
5742 5720 drv_usecwait(1);
5743 5721 timeout--;
5744 5722 }
5745 5723 }
5746 5724
5747 5725 SET_DMAC_CSR(pp, 0);
5748 5726 }
5749 5727
5750 5728 /*
5751 5729 *
5752 5730 * Grover Southbridge (M1553) support routines
5753 5731 * Southbridge contains an Intel 8237 DMAC onboard which is used
5754 5732 * to transport data to/from PCI space to superio parallel port
5755 5733 *
5756 5734 */
5757 5735
5758 5736
5759 5737 static int
5760 5738 m1553_map_regs(struct ecppunit *pp)
5761 5739 {
5762 5740 if (ddi_regs_map_setup(pp->dip, 1, (caddr_t *)&pp->uh.m1553.isa_space,
5763 5741 0, sizeof (struct isaspace), &acc_attr,
5764 5742 &pp->uh.m1553.d_handle) != DDI_SUCCESS) {
5765 5743 ecpp_error(pp->dip, "m1553_map_regs: failed isa space\n");
5766 5744 goto fail;
5767 5745 }
5768 5746
5769 5747 if (ddi_regs_map_setup(pp->dip, 0, (caddr_t *)&pp->i_reg, 0,
5770 5748 sizeof (struct info_reg), &acc_attr, &pp->i_handle)
5771 5749 != DDI_SUCCESS) {
5772 5750 ecpp_error(pp->dip, "m1553_map_regs: failed i_reg\n");
5773 5751 goto fail;
5774 5752 }
5775 5753
5776 5754 if (ddi_regs_map_setup(pp->dip, 0, (caddr_t *)&pp->f_reg, 0x400,
5777 5755 sizeof (struct fifo_reg), &acc_attr, &pp->f_handle)
5778 5756 != DDI_SUCCESS) {
5779 5757 ecpp_error(pp->dip, "m1553_map_regs: failed f_reg\n");
5780 5758 goto fail;
5781 5759 }
5782 5760
5783 5761 return (SUCCESS);
5784 5762
5785 5763 fail:
5786 5764 m1553_unmap_regs(pp);
5787 5765 return (FAILURE);
5788 5766 }
5789 5767
5790 5768 static void
5791 5769 m1553_unmap_regs(struct ecppunit *pp)
5792 5770 {
5793 5771 if (pp->uh.m1553.d_handle) {
5794 5772 ddi_regs_map_free(&pp->uh.m1553.d_handle);
5795 5773 }
5796 5774 if (pp->i_handle) {
5797 5775 ddi_regs_map_free(&pp->i_handle);
5798 5776 }
5799 5777 if (pp->f_handle) {
5800 5778 ddi_regs_map_free(&pp->f_handle);
5801 5779 }
5802 5780 }
5803 5781
5804 5782 #if defined(__x86)
5805 5783 static int
5806 5784 x86_map_regs(struct ecppunit *pp)
5807 5785 {
5808 5786 int nregs = 0;
5809 5787
5810 5788 if (ddi_regs_map_setup(pp->dip, 0, (caddr_t *)&pp->i_reg, 0,
5811 5789 sizeof (struct info_reg), &acc_attr, &pp->i_handle)
5812 5790 != DDI_SUCCESS) {
5813 5791 ecpp_error(pp->dip, "x86_map_regs: failed i_reg\n");
5814 5792 goto fail;
5815 5793 }
5816 5794 if (ddi_dev_nregs(pp->dip, &nregs) == DDI_SUCCESS && nregs == 2) {
5817 5795 if (ddi_regs_map_setup(pp->dip, 1, (caddr_t *)&pp->f_reg, 0,
5818 5796 sizeof (struct fifo_reg), &acc_attr, &pp->f_handle)
5819 5797 != DDI_SUCCESS) {
5820 5798 ecpp_error(pp->dip, "x86_map_regs: failed f_reg\n");
5821 5799 goto fail;
5822 5800 } else
5823 5801 pp->noecpregs = FALSE;
5824 5802 } else {
5825 5803 pp->noecpregs = TRUE;
5826 5804 }
5827 5805 return (SUCCESS);
5828 5806 fail:
5829 5807 x86_unmap_regs(pp);
5830 5808 return (FAILURE);
5831 5809 }
5832 5810
5833 5811 static void
5834 5812 x86_unmap_regs(struct ecppunit *pp)
5835 5813 {
5836 5814 if (pp->i_handle) {
5837 5815 ddi_regs_map_free(&pp->i_handle);
5838 5816 }
5839 5817 if (pp->f_handle) {
5840 5818 ddi_regs_map_free(&pp->f_handle);
5841 5819 }
5842 5820 }
5843 5821 #endif
5844 5822
5845 5823 static uint8_t
5846 5824 m1553_read_config_reg(struct ecppunit *pp, uint8_t reg_num)
5847 5825 {
5848 5826 uint8_t retval;
5849 5827
5850 5828 dma8237_write(pp, 0x3F0, reg_num);
5851 5829 retval = dma8237_read(pp, 0x3F1);
5852 5830
5853 5831 return (retval);
5854 5832 }
5855 5833
5856 5834 static void
5857 5835 m1553_write_config_reg(struct ecppunit *pp, uint8_t reg_num, uint8_t val)
5858 5836 {
5859 5837 dma8237_write(pp, 0x3F0, reg_num);
5860 5838 dma8237_write(pp, 0x3F1, val);
5861 5839 }
5862 5840
5863 5841 static int
5864 5842 m1553_config_chip(struct ecppunit *pp)
5865 5843 {
5866 5844 uint8_t conreg;
5867 5845
5868 5846 /* Unlock configuration regs with "key sequence" */
5869 5847 dma8237_write(pp, 0x3F0, 0x51);
5870 5848 dma8237_write(pp, 0x3F0, 0x23);
5871 5849
5872 5850 m1553_write_config_reg(pp, PnP_CONFIG_DEV_NO, 0x3);
5873 5851 conreg = m1553_read_config_reg(pp, PnP_CONFIG_DEV_NO);
5874 5852 ecpp_error(pp->dip, "M1553:conreg7(logical dev)=%x\n", conreg);
5875 5853
5876 5854 conreg = m1553_read_config_reg(pp, PnP_CONFIG_ACTIVATE);
5877 5855 ecpp_error(pp->dip, "M1553:conreg30(Active)=%x\n", conreg);
5878 5856
5879 5857 conreg = m1553_read_config_reg(pp, PnP_CONFIG_BASE_ADDR_MSB);
5880 5858 ecpp_error(pp->dip, "M1553:conreg60(addrHi)=%x\n", conreg);
5881 5859 conreg = m1553_read_config_reg(pp, PnP_CONFIG_BASE_ADDR_LSB);
5882 5860 ecpp_error(pp->dip, "M1553:conreg61(addrLo)=%x\n", conreg);
5883 5861
5884 5862 conreg = m1553_read_config_reg(pp, PnP_CONFIG_INTR_SEL);
5885 5863 ecpp_error(pp->dip, "M1553:conreg70(IRQL)=%x\n", conreg);
5886 5864
5887 5865 conreg = m1553_read_config_reg(pp, PnP_CONFIG_DMA0_CHAN);
5888 5866 ecpp_error(pp->dip, "M1553:conreg74(DMA0 Chan)=%x\n", conreg);
5889 5867
5890 5868 /* set FIFO threshold 1 and ECP mode, preserve bit 7 (IRQ polarity) */
5891 5869 conreg = m1553_read_config_reg(pp, PnP_CONFIG_PP_CONFIG0);
5892 5870 conreg = (conreg & ~0x7F) | 0x0A;
5893 5871 m1553_write_config_reg(pp, PnP_CONFIG_PP_CONFIG0, conreg);
5894 5872 conreg = m1553_read_config_reg(pp, PnP_CONFIG_PP_CONFIG0);
5895 5873 ecpp_error(pp->dip, "M1553:conregFO(pport conf)=%x\n", conreg);
5896 5874
5897 5875 m1553_write_config_reg(pp, PnP_CONFIG_PP_CONFIG1, 0x04);
5898 5876 conreg = m1553_read_config_reg(pp, PnP_CONFIG_PP_CONFIG1);
5899 5877 ecpp_error(pp->dip, "M1553:conregF1(outconf)=%x\n", conreg);
5900 5878
5901 5879 /* lock configuration regs with key */
5902 5880 dma8237_write(pp, 0x3F0, 0xBB);
5903 5881
5904 5882 /* Set ECR, DCR in known state */
5905 5883 ECR_WRITE(pp, ECR_mode_001 | ECPP_INTR_MASK | ECPP_INTR_SRV);
5906 5884 DCR_WRITE(pp, ECPP_SLCTIN | ECPP_nINIT);
5907 5885
5908 5886 ecpp_error(pp->dip, "m1553_config_chip: ecr=%x, dsr=%x, dcr=%x\n",
5909 5887 ECR_READ(pp), DSR_READ(pp), DCR_READ(pp));
5910 5888
5911 5889 return (SUCCESS);
5912 5890 }
5913 5891
5914 5892 #if defined(__x86)
5915 5893 static int
5916 5894 x86_config_chip(struct ecppunit *pp)
5917 5895 {
5918 5896 if (ecr_write(pp, ECR_mode_001 |
5919 5897 ECPP_INTR_MASK | ECPP_INTR_SRV) == FAILURE) {
5920 5898 ecpp_error(pp->dip, "config chip: failed w/ecr\n");
5921 5899 pp->noecpregs = TRUE;
5922 5900 }
5923 5901 if (pp->noecpregs)
5924 5902 pp->fast_compat = FALSE;
5925 5903 DCR_WRITE(pp, ECPP_SLCTIN | ECPP_nINIT);
5926 5904 ecpp_error(pp->dip, "x86_config_chip: ecr=%x, dsr=%x, dcr=%x\n",
5927 5905 ECR_READ(pp), DSR_READ(pp), DCR_READ(pp));
5928 5906 return (SUCCESS);
5929 5907 }
5930 5908 #endif
5931 5909
5932 5910 /*
5933 5911 * dma8237_dma_start() programs the selected 8 bit channel
5934 5912 * of DMAC1 with the dma cookie. pp->dma_cookie must
5935 5913 * be set before this routine is called.
5936 5914 */
5937 5915 static int
5938 5916 dma8237_dma_start(struct ecppunit *pp)
5939 5917 {
5940 5918 uint8_t chn;
5941 5919
5942 5920 chn = pp->uh.m1553.chn;
5943 5921
5944 5922 ASSERT(chn <= DMAE_CH3 &&
5945 5923 pp->dma_cookie.dmac_size != 0 &&
5946 5924 pp->dma_cookie.dmac_address != NULL);
5947 5925
5948 5926 /* At this point Southbridge has not yet asserted DREQ */
5949 5927
5950 5928 /* set mode to read-from-memory. */
5951 5929 dma8237_write(pp, DMAC2_MODE, DMAMODE_CASC);
5952 5930 if (pp->dma_dir == DDI_DMA_READ) {
5953 5931 dma8237_write(pp, DMAC1_MODE, DMAMODE_SINGLE |
5954 5932 DMAMODE_READ | chn);
5955 5933 } else {
5956 5934 dma8237_write(pp, DMAC1_MODE, DMAMODE_SINGLE |
5957 5935 DMAMODE_WRITE | chn);
5958 5936 }
5959 5937
5960 5938 dma8237_write_addr(pp, pp->dma_cookie.dmac_address);
5961 5939 dma8237_write_count(pp, pp->dma_cookie.dmac_size - 1);
5962 5940
5963 5941 /*
5964 5942 * M1553 chip does not permit to access DMA register banks
5965 5943 * while DMA is in flight. As a result, ecpp and floppy drivers
5966 5944 * can potentially corrupt each other's DMA. The interlocking mechanism
5967 5945 * is provided by a parent nexus driver (isadma), which is enabled
5968 5946 * indirectly through a DMAC1_ALLMASK register access:
5969 5947 *
5970 5948 * writing a non-zero value to this register enters a lock,
5971 5949 * writing zero releases the lock.
5972 5950 *
5973 5951 * DMA transfer must only occur after entering a lock.
5974 5952 * If the lock is already owned by other driver, we will block.
5975 5953 *
5976 5954 * The following operation unmasks our channel and masks all others
5977 5955 */
5978 5956 dma8237_write(pp, DMAC1_ALLMASK, ~(1 << chn));
5979 5957 pp->uh.m1553.isadma_entered = 1;
5980 5958
5981 5959 return (SUCCESS);
5982 5960 }
5983 5961
5984 5962 static int
5985 5963 dma8237_dma_stop(struct ecppunit *pp, size_t *countp)
5986 5964 {
5987 5965 uint8_t ecr;
5988 5966
5989 5967 /* stop DMA */
5990 5968 ecr = (ECR_READ(pp) & 0xe0) | ECPP_INTR_MASK | ECPP_INTR_SRV;
5991 5969 (void) ecr_write(pp, ecr);
5992 5970
5993 5971 if (pp->uh.m1553.isadma_entered) {
5994 5972 /* reset the channel mask so we can issue PIO's to our device */
5995 5973 dma8237_write(pp, DMAC1_ALLMASK, 0);
5996 5974 pp->uh.m1553.isadma_entered = 0;
5997 5975
5998 5976 }
5999 5977
6000 5978 /* read DMA count if requested */
6001 5979 if (countp) {
6002 5980 *countp = dma8237_getcnt(pp);
6003 5981 if (pp->dma_dir == DDI_DMA_READ && *countp > 0) {
6004 5982 (*countp)++; /* need correction for reverse xfers */
6005 5983 }
6006 5984 }
6007 5985 return (SUCCESS);
6008 5986 }
6009 5987 #if defined(__x86)
6010 5988 static int
6011 5989 x86_dma_start(struct ecppunit *pp)
6012 5990 {
6013 5991 uint8_t chn;
6014 5992 struct ddi_dmae_req dmaereq;
6015 5993
6016 5994 chn = pp->uh.x86.chn;
6017 5995 ASSERT(chn <= DMAE_CH3 &&
6018 5996 pp->dma_cookie.dmac_size != 0 &&
6019 5997 pp->dma_cookie.dmac_address != NULL);
6020 5998 bzero(&dmaereq, sizeof (struct ddi_dmae_req));
6021 5999 dmaereq.der_command =
6022 6000 (pp->dma_dir & DDI_DMA_READ) ? DMAE_CMD_READ : DMAE_CMD_WRITE;
6023 6001 if (ddi_dmae_prog(pp->dip, &dmaereq, &pp->dma_cookie, chn)
6024 6002 != DDI_SUCCESS)
6025 6003 ecpp_error(pp->dip, "prog failed !!!\n");
6026 6004 ecpp_error(pp->dip, "dma_started..\n");
6027 6005 return (SUCCESS);
6028 6006 }
6029 6007
6030 6008 static int
6031 6009 x86_dma_stop(struct ecppunit *pp, size_t *countp)
6032 6010 {
6033 6011 uint8_t ecr;
6034 6012
6035 6013 /* stop DMA */
6036 6014 if (pp->uh.x86.chn == 0xff)
6037 6015 return (FAILURE);
6038 6016 ecr = (ECR_READ(pp) & 0xe0) | ECPP_INTR_MASK | ECPP_INTR_SRV;
6039 6017 (void) ecr_write(pp, ecr);
6040 6018 ecpp_error(pp->dip, "dma_stop\n");
6041 6019
6042 6020 /* read DMA count if requested */
6043 6021 if (countp) {
6044 6022 *countp = x86_getcnt(pp);
6045 6023 }
6046 6024 ecpp_error(pp->dip, "dma_stoped..\n");
6047 6025 return (SUCCESS);
6048 6026 }
6049 6027 #endif
6050 6028
6051 6029 /* channel must be masked */
6052 6030 static void
6053 6031 dma8237_write_addr(struct ecppunit *pp, uint32_t addr)
6054 6032 {
6055 6033 uint8_t c_addr, c_lpage;
6056 6034 uint16_t c_hpage, *p;
6057 6035
6058 6036 switch (pp->uh.m1553.chn) {
6059 6037 case DMAE_CH0:
6060 6038 c_addr = DMA_0ADR;
6061 6039 c_lpage = DMA_0PAGE;
6062 6040 c_hpage = DMA_0HPG;
6063 6041 break;
6064 6042
6065 6043 case DMAE_CH1:
6066 6044 c_addr = DMA_1ADR;
6067 6045 c_lpage = DMA_1PAGE;
6068 6046 c_hpage = DMA_1HPG;
6069 6047 break;
6070 6048
6071 6049 case DMAE_CH2:
6072 6050 c_addr = DMA_2ADR;
6073 6051 c_lpage = DMA_2PAGE;
6074 6052 c_hpage = DMA_2HPG;
6075 6053 break;
6076 6054
6077 6055 case DMAE_CH3:
6078 6056 c_addr = DMA_3ADR;
6079 6057 c_lpage = DMA_3PAGE;
6080 6058 c_hpage = DMA_3HPG;
6081 6059 break;
6082 6060
6083 6061 default:
6084 6062 return;
6085 6063 }
6086 6064
6087 6065 p = (uint16_t *)&pp->uh.m1553.isa_space->isa_reg[c_addr];
6088 6066 ddi_put16(pp->uh.m1553.d_handle, p, addr & 0xFFFF);
6089 6067
6090 6068 dma8237_write(pp, c_lpage, (addr & 0xFF0000) >> 16);
6091 6069 dma8237_write(pp, c_hpage, (addr & 0xFF000000) >> 24);
6092 6070
6093 6071 }
6094 6072
6095 6073 /*
6096 6074 * This function may be useful during debugging,
6097 6075 * so we leave it in, but do not include in the binary
6098 6076 */
6099 6077 #ifdef INCLUDE_DMA8237_READ_ADDR
6100 6078 static uint32_t
6101 6079 dma8237_read_addr(struct ecppunit *pp)
6102 6080 {
6103 6081 uint8_t rval3, rval4;
6104 6082 uint16_t rval16;
6105 6083 uint32_t rval;
6106 6084 uint8_t c_addr, c_lpage;
6107 6085 uint16_t c_hpage, *p;
6108 6086
6109 6087 switch (pp->uh.m1553.chn) {
6110 6088 case DMAE_CH0:
6111 6089 c_addr = DMA_0ADR;
6112 6090 c_lpage = DMA_0PAGE;
6113 6091 c_hpage = DMA_0HPG;
6114 6092 break;
6115 6093
6116 6094 case DMAE_CH1:
6117 6095 c_addr = DMA_1ADR;
6118 6096 c_lpage = DMA_1PAGE;
6119 6097 c_hpage = DMA_1HPG;
6120 6098 break;
6121 6099
6122 6100 case DMAE_CH2:
6123 6101 c_addr = DMA_2ADR;
6124 6102 c_lpage = DMA_2PAGE;
6125 6103 c_hpage = DMA_2HPG;
6126 6104 break;
6127 6105
6128 6106 case DMAE_CH3:
6129 6107 c_addr = DMA_3ADR;
6130 6108 c_lpage = DMA_3PAGE;
6131 6109 c_hpage = DMA_3HPG;
6132 6110 break;
6133 6111
6134 6112 default:
6135 6113 return (NULL);
6136 6114 }
6137 6115
6138 6116 p = (uint16_t *)&pp->uh.m1553.isa_space->isa_reg[c_addr];
6139 6117 rval16 = ddi_get16(pp->uh.m1553.d_handle, p);
6140 6118
6141 6119 rval3 = dma8237_read(pp, c_lpage);
6142 6120 rval4 = dma8237_read(pp, c_hpage);
6143 6121
6144 6122 rval = rval16 | (rval3 << 16) | (rval4 <<24);
6145 6123
6146 6124 return (rval);
6147 6125 }
6148 6126 #endif
6149 6127
6150 6128 static void
6151 6129 dma8237_write_count(struct ecppunit *pp, uint32_t count)
6152 6130 {
6153 6131 uint8_t c_wcnt;
6154 6132 uint16_t *p;
6155 6133
6156 6134 switch (pp->uh.m1553.chn) {
6157 6135 case DMAE_CH0:
6158 6136 c_wcnt = DMA_0WCNT;
6159 6137 break;
6160 6138
6161 6139 case DMAE_CH1:
6162 6140 c_wcnt = DMA_1WCNT;
6163 6141 break;
6164 6142
6165 6143 case DMAE_CH2:
6166 6144 c_wcnt = DMA_2WCNT;
6167 6145 break;
6168 6146
6169 6147 case DMAE_CH3:
6170 6148 c_wcnt = DMA_3WCNT;
6171 6149 break;
6172 6150
6173 6151 default:
6174 6152 return;
6175 6153 }
6176 6154
6177 6155 p = (uint16_t *)&pp->uh.m1553.isa_space->isa_reg[c_wcnt];
6178 6156 ddi_put16(pp->uh.m1553.d_handle, p, count & 0xFFFF);
6179 6157
6180 6158 }
6181 6159
6182 6160 static uint32_t
6183 6161 dma8237_read_count(struct ecppunit *pp)
6184 6162 {
6185 6163 uint8_t c_wcnt;
6186 6164 uint16_t *p;
6187 6165
6188 6166 switch (pp->uh.m1553.chn) {
6189 6167 case DMAE_CH0:
6190 6168 c_wcnt = DMA_0WCNT;
6191 6169 break;
6192 6170
6193 6171 case DMAE_CH1:
6194 6172 c_wcnt = DMA_1WCNT;
6195 6173 break;
6196 6174
6197 6175 case DMAE_CH2:
6198 6176 c_wcnt = DMA_2WCNT;
6199 6177 break;
6200 6178
6201 6179 case DMAE_CH3:
6202 6180 c_wcnt = DMA_3WCNT;
6203 6181 break;
6204 6182
6205 6183 default:
6206 6184 return (NULL);
6207 6185 }
6208 6186
6209 6187 p = (uint16_t *)&pp->uh.m1553.isa_space->isa_reg[c_wcnt];
6210 6188 return (ddi_get16(pp->uh.m1553.d_handle, p));
6211 6189
6212 6190 }
6213 6191
6214 6192 static void
6215 6193 dma8237_write(struct ecppunit *pp, int reg_num, uint8_t val)
6216 6194 {
6217 6195 ddi_put8(pp->uh.m1553.d_handle,
6218 6196 &pp->uh.m1553.isa_space->isa_reg[reg_num], val);
6219 6197 }
6220 6198
6221 6199 static uint8_t
6222 6200 dma8237_read(struct ecppunit *pp, int reg_num)
6223 6201 {
6224 6202 return (ddi_get8(pp->uh.m1553.d_handle,
6225 6203 &pp->uh.m1553.isa_space->isa_reg[reg_num]));
6226 6204 }
6227 6205
6228 6206 static size_t
6229 6207 dma8237_getcnt(struct ecppunit *pp)
6230 6208 {
6231 6209 uint32_t cnt;
6232 6210
6233 6211 if ((cnt = dma8237_read_count(pp)) == 0xffff)
6234 6212 cnt = 0;
6235 6213 else
6236 6214 cnt++;
6237 6215 return (cnt);
6238 6216 }
6239 6217
6240 6218
6241 6219 /*
6242 6220 *
6243 6221 * Kstat support routines
6244 6222 *
6245 6223 */
6246 6224 static void
6247 6225 ecpp_kstat_init(struct ecppunit *pp)
6248 6226 {
6249 6227 struct ecppkstat *ekp;
6250 6228 char buf[16];
6251 6229
6252 6230 /*
6253 6231 * Allocate, initialize and install interrupt counter kstat
6254 6232 */
6255 6233 (void) sprintf(buf, "ecppc%d", pp->instance);
6256 6234 pp->intrstats = kstat_create("ecpp", pp->instance, buf, "controller",
6257 6235 KSTAT_TYPE_INTR, 1, KSTAT_FLAG_PERSISTENT);
6258 6236 if (pp->intrstats == NULL) {
6259 6237 ecpp_error(pp->dip, "ecpp_kstat_init:1: kstat_create failed");
6260 6238 } else {
6261 6239 pp->intrstats->ks_update = ecpp_kstatintr_update;
6262 6240 pp->intrstats->ks_private = (void *) pp;
6263 6241 kstat_install(pp->intrstats);
6264 6242 }
6265 6243
6266 6244 /*
6267 6245 * Allocate, initialize and install misc stats kstat
6268 6246 */
6269 6247 pp->ksp = kstat_create("ecpp", pp->instance, NULL, "misc",
6270 6248 KSTAT_TYPE_NAMED,
6271 6249 sizeof (struct ecppkstat) / sizeof (kstat_named_t),
6272 6250 KSTAT_FLAG_PERSISTENT);
6273 6251 if (pp->ksp == NULL) {
6274 6252 ecpp_error(pp->dip, "ecpp_kstat_init:2: kstat_create failed");
6275 6253 return;
6276 6254 }
6277 6255
6278 6256 ekp = (struct ecppkstat *)pp->ksp->ks_data;
6279 6257
6280 6258 #define EK_NAMED_INIT(name) \
6281 6259 kstat_named_init(&ekp->ek_##name, #name, KSTAT_DATA_UINT32)
6282 6260
6283 6261 EK_NAMED_INIT(ctx_obytes);
6284 6262 EK_NAMED_INIT(ctxpio_obytes);
6285 6263 EK_NAMED_INIT(nib_ibytes);
6286 6264 EK_NAMED_INIT(ecp_obytes);
6287 6265 EK_NAMED_INIT(ecp_ibytes);
6288 6266 EK_NAMED_INIT(epp_obytes);
6289 6267 EK_NAMED_INIT(epp_ibytes);
6290 6268 EK_NAMED_INIT(diag_obytes);
6291 6269 EK_NAMED_INIT(to_ctx);
6292 6270 EK_NAMED_INIT(to_nib);
6293 6271 EK_NAMED_INIT(to_ecp);
6294 6272 EK_NAMED_INIT(to_epp);
6295 6273 EK_NAMED_INIT(to_diag);
6296 6274 EK_NAMED_INIT(xfer_tout);
6297 6275 EK_NAMED_INIT(ctx_cf);
6298 6276 EK_NAMED_INIT(joblen);
6299 6277 EK_NAMED_INIT(isr_reattempt_high);
6300 6278 EK_NAMED_INIT(mode);
6301 6279 EK_NAMED_INIT(phase);
6302 6280 EK_NAMED_INIT(backchan);
6303 6281 EK_NAMED_INIT(iomode);
6304 6282 EK_NAMED_INIT(state);
6305 6283
6306 6284 pp->ksp->ks_update = ecpp_kstat_update;
6307 6285 pp->ksp->ks_private = (void *) pp;
6308 6286 kstat_install(pp->ksp);
6309 6287 }
6310 6288
6311 6289 static int
6312 6290 ecpp_kstat_update(kstat_t *ksp, int rw)
6313 6291 {
6314 6292 struct ecppunit *pp;
6315 6293 struct ecppkstat *ekp;
6316 6294
6317 6295 /*
6318 6296 * For the time being there is no point
6319 6297 * in supporting writable kstats
6320 6298 */
6321 6299 if (rw == KSTAT_WRITE) {
6322 6300 return (EACCES);
6323 6301 }
6324 6302
6325 6303 pp = (struct ecppunit *)ksp->ks_private;
6326 6304 ekp = (struct ecppkstat *)ksp->ks_data;
6327 6305
6328 6306 mutex_enter(&pp->umutex);
6329 6307
6330 6308 ekp->ek_ctx_obytes.value.ui32 = pp->obytes[ECPP_CENTRONICS] +
6331 6309 pp->obytes[ECPP_COMPAT_MODE];
6332 6310 ekp->ek_ctxpio_obytes.value.ui32 = pp->ctxpio_obytes;
6333 6311 ekp->ek_nib_ibytes.value.ui32 = pp->ibytes[ECPP_NIBBLE_MODE];
6334 6312 ekp->ek_ecp_obytes.value.ui32 = pp->obytes[ECPP_ECP_MODE];
6335 6313 ekp->ek_ecp_ibytes.value.ui32 = pp->ibytes[ECPP_ECP_MODE];
6336 6314 ekp->ek_epp_obytes.value.ui32 = pp->obytes[ECPP_EPP_MODE];
6337 6315 ekp->ek_epp_ibytes.value.ui32 = pp->ibytes[ECPP_EPP_MODE];
6338 6316 ekp->ek_diag_obytes.value.ui32 = pp->obytes[ECPP_DIAG_MODE];
6339 6317 ekp->ek_to_ctx.value.ui32 = pp->to_mode[ECPP_CENTRONICS] +
6340 6318 pp->to_mode[ECPP_COMPAT_MODE];
6341 6319 ekp->ek_to_nib.value.ui32 = pp->to_mode[ECPP_NIBBLE_MODE];
6342 6320 ekp->ek_to_ecp.value.ui32 = pp->to_mode[ECPP_ECP_MODE];
6343 6321 ekp->ek_to_epp.value.ui32 = pp->to_mode[ECPP_EPP_MODE];
6344 6322 ekp->ek_to_diag.value.ui32 = pp->to_mode[ECPP_DIAG_MODE];
6345 6323 ekp->ek_xfer_tout.value.ui32 = pp->xfer_tout;
6346 6324 ekp->ek_ctx_cf.value.ui32 = pp->ctx_cf;
6347 6325 ekp->ek_joblen.value.ui32 = pp->joblen;
6348 6326 ekp->ek_isr_reattempt_high.value.ui32 = pp->isr_reattempt_high;
6349 6327 ekp->ek_mode.value.ui32 = pp->current_mode;
6350 6328 ekp->ek_phase.value.ui32 = pp->current_phase;
6351 6329 ekp->ek_backchan.value.ui32 = pp->backchannel;
6352 6330 ekp->ek_iomode.value.ui32 = pp->io_mode;
6353 6331 ekp->ek_state.value.ui32 = pp->e_busy;
6354 6332
6355 6333 mutex_exit(&pp->umutex);
6356 6334
6357 6335 return (0);
6358 6336 }
6359 6337
6360 6338 static int
6361 6339 ecpp_kstatintr_update(kstat_t *ksp, int rw)
6362 6340 {
6363 6341 struct ecppunit *pp;
6364 6342
6365 6343 /*
6366 6344 * For the time being there is no point
6367 6345 * in supporting writable kstats
6368 6346 */
6369 6347 if (rw == KSTAT_WRITE) {
6370 6348 return (EACCES);
6371 6349 }
6372 6350
6373 6351 pp = (struct ecppunit *)ksp->ks_private;
6374 6352
6375 6353 mutex_enter(&pp->umutex);
6376 6354
6377 6355 KSTAT_INTR_PTR(ksp)->intrs[KSTAT_INTR_HARD] = pp->intr_hard;
6378 6356 KSTAT_INTR_PTR(ksp)->intrs[KSTAT_INTR_SPURIOUS] = pp->intr_spurious;
6379 6357 KSTAT_INTR_PTR(ksp)->intrs[KSTAT_INTR_SOFT] = pp->intr_soft;
6380 6358
6381 6359 mutex_exit(&pp->umutex);
6382 6360
6383 6361 return (0);
6384 6362 }
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