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8368 remove warlock leftovers from usr/src/uts
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--- old/usr/src/uts/common/io/audio/drv/audiohd/audiohd.h
+++ new/usr/src/uts/common/io/audio/drv/audiohd/audiohd.h
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21 /*
22 22 * Copyright (c) 2006, 2010, Oracle and/or its affiliates. All rights reserved.
23 23 */
24 24 #ifndef _SYS_AUDIOHD_IMPL_H_
25 25 #define _SYS_AUDIOHD_IMPL_H_
26 26
27 27 #ifdef __cplusplus
28 28 extern "C" {
29 29 #endif
30 30
31 31 /*
32 32 * vendor IDs of PCI audio controllers
33 33 */
34 34 #define AUDIOHD_VID_ATI 0x1002
35 35 #define AUDIOHD_VID_CIRRUS 0x1013
36 36 #define AUDIOHD_VID_NVIDIA 0x10de
37 37 #define AUDIOHD_VID_REALTEK 0x10ec
38 38 #define AUDIOHD_VID_CREATIVE 0x1102
39 39 #define AUDIOHD_VID_IDT 0x111d
40 40 #define AUDIOHD_VID_ANALOG 0x11d4
41 41 #define AUDIOHD_VID_CONEXANT 0x14f1
42 42 #define AUDIOHD_VID_SIGMATEL 0x8384
43 43 #define AUDIOHD_VID_INTEL 0x8086
44 44
45 45 /*
46 46 * specific audiohd controller device id
47 47 */
48 48 #define AUDIOHD_CONTROLLER_MCP51 0x10de026c
49 49
50 50 /*
51 51 * codec special initial flags
52 52 */
53 53 #define NO_GPIO 0x00000001
54 54 #define NO_MIXER 0x00000002
55 55 #define NO_SPDIF 0x00000004
56 56 #define EN_PIN_BEEP 0x00000008
57 57
58 58 #define AUDIOHD_DEV_CONFIG "onboard1"
59 59 #define AUDIOHD_DEV_VERSION "a"
60 60
61 61 /*
62 62 * Only for Intel hardware:
63 63 * PCI Express traffic class select register in PCI configure space
64 64 */
65 65 #define AUDIOHD_INTEL_PCI_TCSEL 0x44
66 66 #define AUDIOHD_INTEL_TCS_MASK 0xf8
67 67
68 68 /*
69 69 * Only for ATI SB450:
70 70 * MISC control register 2
71 71 */
72 72 #define AUDIOHD_ATI_PCI_MISC2 0x42
73 73 #define AUDIOHD_ATI_MISC2_MASK 0xf8
74 74 #define AUDIOHD_ATI_MISC2_SNOOP 0x02
75 75
76 76 /* NVIDIA snoop */
77 77 #define AUDIOHD_NVIDIA_SNOOP 0x0f
78 78
79 79 #define AUDIOHDC_NID(x) x
80 80 #define AUDIOHDC_NULL_NODE -1
81 81 #define AUDIOHD_NULL_CONN ((uint_t)(-1))
82 82
83 83 #define AUDIOHD_EXT_AMP_MASK 0x00010000
84 84 #define AUDIOHD_EXT_AMP_ENABLE 0x02
85 85
86 86 /* Power On/Off */
87 87 #define AUDIOHD_PW_D0 0
88 88 #define AUDIOHD_PW_D2 2
89 89
90 90 /* Pin speaker On/Off */
91 91 #define AUDIOHD_SP_ON 1
92 92 #define AUDIOHD_SP_OFF 0
93 93
94 94 #define AUDIOHD_PORT_MAX 15
95 95 #define AUDIOHD_CODEC_MAX 16
96 96 #define AUDIOHD_MEMIO_LEN 0x4000
97 97
98 98 #define AUDIOHD_RETRY_TIMES 60
99 99 #define AUDIOHD_TEST_TIMES 500
100 100 #define AUDIOHD_OUTSTR_NUM_OFF 12
101 101 #define AUDIOHD_INSTR_NUM_OFF 8
102 102
103 103 #define AUDIOHD_CORB_SIZE_OFF 0x4e
104 104
105 105 #define AUDIOHD_URCAP_MASK 0x80
106 106 #define AUDIOHD_DTCCAP_MASK 0x4
107 107 #define AUDIOHD_UR_ENABLE_OFF 8
108 108 #define AUDIOHD_UR_TAG_MASK 0x3f
109 109
110 110 #define AUDIOHD_CIS_MASK 0x40000000
111 111
112 112 #define AUDIOHD_RIRB_UR_MASK 0x10
113 113 #define AUDIOHD_RIRB_CODEC_MASK 0xf
114 114 #define AUDIOHD_RIRB_WID_OFF 27
115 115 #define AUDIOHD_RIRB_INTRCNT 0x0
116 116 #define AUDIOHD_RIRB_WPMASK 0xff
117 117
118 118 #define AUDIOHD_FORM_MASK 0x0080
119 119 #define AUDIOHD_LEN_MASK 0x007f
120 120 #define AUDIOHD_PIN_CAP_MASK 0x00000010
121 121 #define AUDIOHD_PIN_CONF_MASK 0xc0000000
122 122 #define AUDIOHD_PIN_CON_MASK 3
123 123 #define AUDIOHD_PIN_CON_STEP 30
124 124 #define AUDIOHD_PIN_IO_MASK 0X0018
125 125 #define AUDIOHD_PIN_SEQ_MASK 0x0000000f
126 126 #define AUDIOHD_PIN_ASO_MASK 0x000000f0
127 127 #define AUDIOHD_PIN_ASO_OFF 0x4
128 128 #define AUDIOHD_PIN_DEV_MASK 0x00f00000
129 129 #define AUDIOHD_PIN_DEV_OFF 20
130 130 #define AUDIOHD_PIN_NUMS 6
131 131 #define AUDIOHD_PIN_NO_CONN 0x40000000
132 132 #define AUDIOHD_PIN_IN_ENABLE 0x20
133 133 #define AUDIOHD_PIN_OUT_ENABLE 0x40
134 134 #define AUDIOHD_PIN_PRES_MASK 0x80000000
135 135 #define AUDIOHD_PIN_CONTP_OFF 0x1e
136 136 #define AUDIOHD_PIN_CON_JACK 0
137 137 #define AUDIOHD_PIN_CON_FIXED 0x2
138 138 #define AUDIOHD_PIN_CONTP_MASK 0x3
139 139 #define AUDIOHD_PIN_VREF_L1 0x20
140 140 #define AUDIOHD_PIN_VREF_L2 0x10
141 141 #define AUDIOHD_PIN_VREF_L3 0x04
142 142 #define AUDIOHD_PIN_VREF_L4 0x02
143 143 #define AUDIOHD_PIN_VREF_OFF 8
144 144 #define AUDIOHD_PIN_VREF_MASK 0xff
145 145 #define AUDIOHD_PIN_CLR_MASK 0xf
146 146 #define AUDIOHD_PIN_CLR_OFF 12
147 147
148 148 #define AUDIOHD_VERB_ADDR_OFF 28
149 149 #define AUDIOHD_VERB_NID_OFF 20
150 150 #define AUDIOHD_VERB_CMD_OFF 8
151 151 #define AUDIOHD_VERB_CMD16_OFF 16
152 152
153 153 #define AUDIOHD_RING_MAX_SIZE 0x00ff
154 154 #define AUDIOHD_REC_TAG_OFF 4
155 155 #define AUDIOHD_PLAY_TAG_OFF 4
156 156 #define AUDIOHD_PLAY_CTL_OFF 2
157 157 #define AUDIOHD_REC_CTL_OFF 2
158 158
159 159 #define AUDIOHD_SPDIF_ON 1
160 160 #define AUDIOHD_SPDIF_MASK 0x00ff
161 161
162 162 #define AUDIOHD_GAIN_OFF 8
163 163
164 164 #define AUDIOHD_CODEC_STR_OFF 16
165 165 #define AUDIOHD_CODEC_STR_MASK 0x000000ff
166 166 #define AUDIOHD_CODEC_NUM_MASK 0x000000ff
167 167 #define AUDIOHD_CODEC_TYPE_MASK 0x000000ff
168 168
169 169 #define AUDIOHD_ROUNDUP(x, algn) (((x) + ((algn) - 1)) & ~((algn) - 1))
170 170 #define AUDIOHD_BDLE_BUF_ALIGN 128
171 171 #define AUDIOHD_CMDIO_ENT_MASK 0x00ff /* 256 entries for CORB/RIRB */
172 172 #define AUDIOHD_CDBIO_CORB_LEN 1024 /* 256 entries for CORB, 1024B */
173 173 #define AUDIOHD_CDBIO_RIRB_LEN 2048 /* 256 entries for RIRB, 2048B */
174 174 #define AUDIOHD_BDLE_NUMS 4 /* 4 entires for record/play BD list */
175 175
176 176 #define AUDIOHD_PORT_UNMUTE (0xffffffff)
177 177
178 178 /*
179 179 * Audio registers of high definition
180 180 */
181 181 #define AUDIOHD_REG_GCAP 0x00
182 182 #define AUDIOHDR_GCAP_OUTSTREAMS 0xf000
183 183 #define AUDIOHDR_GCAP_INSTREAMS 0x0f00
184 184 #define AUDIOHDR_GCAP_BSTREAMS 0x00f8
185 185 #define AUDIOHDR_GCAP_NSDO 0x0006
186 186 #define AUDIOHDR_GCAP_64OK 0x0001
187 187
188 188 #define AUDIOHD_REG_VMIN 0x02
189 189 #define AUDIOHD_REG_VMAJ 0x03
190 190 #define AUDIOHD_REG_OUTPAY 0x04
191 191 #define AUDIOHD_REG_INPAY 0x06
192 192 #define AUDIOHD_REG_GCTL 0x08
193 193 #define AUDIOHD_REG_WAKEEN 0x0C
194 194 #define AUDIOHD_REG_STATESTS 0x0E
195 195 #define AUDIOHD_STATESTS_BIT_SDINS 0x7F
196 196
197 197 #define AUDIOHD_REG_GSTS 0x10
198 198 #define AUDIOHD_REG_INTCTL 0x20
199 199 #define AUDIOHD_INTCTL_BIT_GIE 0x80000000
200 200 #define AUDIOHD_INTCTL_BIT_CIE 0x40000000
201 201 #define AUDIOHD_INTCTL_BIT_SIE 0x3FFFFFFF
202 202
203 203
204 204 #define AUDIOHD_REG_INTSTS 0x24
205 205 #define AUDIOHD_INTSTS_BIT_GIS 0x80000000
206 206 #define AUDIOHD_INTSTS_BIT_CIS 0x40000000
207 207 #define AUDIOHD_INTSTS_BIT_SINTS (0x3fffffff)
208 208
209 209 #define AUDIOHD_REG_WALCLK 0x30
210 210 #define AUDIOHD_REG_SYNC 0x38
211 211
212 212 #define AUDIOHD_REG_CORBLBASE 0x40
213 213 #define AUDIOHD_REG_CORBUBASE 0x44
214 214 #define AUDIOHD_REG_CORBWP 0x48
215 215 #define AUDIOHD_REG_CORBRP 0x4A
216 216 #define AUDIOHD_REG_CORBCTL 0x4C
217 217 #define AUDIOHD_REG_CORBST 0x4D
218 218 #define AUDIOHD_REG_CORBSIZE 0x4E
219 219
220 220 #define AUDIOHD_REG_RIRBLBASE 0x50
221 221 #define AUDIOHD_REG_RIRBUBASE 0x54
222 222 #define AUDIOHD_REG_RIRBWP 0x58
223 223 #define AUDIOHD_REG_RINTCNT 0x5A
224 224 #define AUDIOHD_REG_RIRBCTL 0x5C
225 225 #define AUDIOHD_REG_RIRBSTS 0x5D
226 226 #define AUDIOHD_REG_RIRBSIZE 0x5E
227 227
228 228 #define AUDIOHD_REG_IC 0x60
229 229 #define AUDIOHD_REG_IR 0x64
230 230 #define AUDIOHD_REG_IRS 0x68
231 231 #define AUDIOHD_REG_DPLBASE 0x70
232 232 #define AUDIOHD_REG_DPUBASE 0x74
233 233
234 234 #define AUDIOHD_REG_SD_BASE 0x80
235 235 #define AUDIOHD_REG_SD_LEN 0x20
236 236
237 237 /*
238 238 * Offset of Stream Descriptor Registers
239 239 */
240 240 #define AUDIOHD_SDREG_OFFSET_CTL 0x00
241 241 #define AUDIOHD_SDREG_OFFSET_STS 0x03
242 242 #define AUDIOHD_SDREG_OFFSET_LPIB 0x04
243 243 #define AUDIOHD_SDREG_OFFSET_CBL 0x08
244 244 #define AUDIOHD_SDREG_OFFSET_LVI 0x0c
245 245 #define AUDIOHD_SDREG_OFFSET_FIFOW 0x0e
246 246 #define AUDIOHD_SDREG_OFFSET_FIFOSIZE 0x10
247 247 #define AUDIOHD_SDREG_OFFSET_FORMAT 0x12
248 248 #define AUDIOHD_SDREG_OFFSET_BDLPL 0x18
249 249 #define AUDIOHD_SDREG_OFFSET_BDLPU 0x1c
250 250
251 251 /* bits for stream descriptor control reg */
252 252 #define AUDIOHDR_SD_CTL_DEIE 0x000010
253 253 #define AUDIOHDR_SD_CTL_FEIE 0x000008
254 254 #define AUDIOHDR_SD_CTL_IOCE 0x000004
255 255 #define AUDIOHDR_SD_CTL_SRUN 0x000002
256 256 #define AUDIOHDR_SD_CTL_SRST 0x000001
257 257
258 258 /* bits for stream descriptor status register */
259 259 #define AUDIOHDR_SD_STS_BCIS 0x0004
260 260 #define AUDIOHDR_SD_STS_FIFOE 0x0008
261 261 #define AUDIOHDR_SD_STS_DESE 0x0010
262 262 #define AUDIOHDR_SD_STS_FIFORY 0x0020
263 263 #define AUDIOHDR_SD_STS_INTRS \
264 264 (AUDIOHDR_SD_STS_BCIS | \
265 265 AUDIOHDR_SD_STS_FIFOE | \
266 266 AUDIOHDR_SD_STS_DESE)
267 267
268 268 /* bits for GCTL register */
269 269 #define AUDIOHDR_GCTL_CRST 0x00000001
270 270 #define AUDIOHDR_GCTL_URESPE 0x00000100
271 271
272 272 /* bits for CORBRP register */
273 273 #define AUDIOHDR_CORBRP_RESET 0x8000
274 274 #define AUDIOHDR_CORBRP_WPTR 0x00ff
275 275
276 276 /* bits for CORBCTL register */
277 277 #define AUDIOHDR_CORBCTL_CMEIE 0x01
278 278 #define AUDIOHDR_CORBCTL_DMARUN 0x02
279 279
280 280 /* bits for CORB SIZE register */
281 281 #define AUDIOHDR_CORBSZ_8 0
282 282 #define AUDIOHDR_CORBSZ_16 1
283 283 #define AUDIOHDR_CORBSZ_256 2
284 284
285 285 /* bits for RIRBCTL register */
286 286 #define AUDIOHDR_RIRBCTL_RINTCTL 0x01
287 287 #define AUDIOHDR_RIRBCTL_DMARUN 0x02
288 288 #define AUDIOHDR_RIRBCTL_RIRBOIC 0x04
289 289 #define AUDIOHDR_RIRBCTL_RSTINT 0xfe
290 290
291 291 /* bits for RIRBWP register */
292 292 #define AUDIOHDR_RIRBWP_RESET 0x8000
293 293 #define AUDIOHDR_RIRBWP_WPTR 0x00ff
294 294
295 295 /* bits for RIRB SIZE register */
296 296 #define AUDIOHDR_RIRBSZ_8 0
297 297 #define AUDIOHDR_RIRBSZ_16 1
298 298 #define AUDIOHDR_RIRBSZ_256 2
299 299
300 300 #define AUDIOHD_BDLE_RIRB_SDI 0x0000000f
301 301 #define AUDIOHD_BDLE_RIRB_UNSOLICIT 0x00000010
302 302
303 303 /* HD spec: ID of Root node is 0 */
304 304 #define AUDIOHDC_NODE_ROOT 0x00
305 305
306 306 /* HD spec: ID of audio function group is "1" */
307 307 #define AUDIOHDC_AUDIO_FUNC_GROUP 1
308 308
309 309 /*
310 310 * HD audio verbs can be either 12-bit or 4-bit in length.
311 311 */
312 312 #define AUDIOHDC_12BIT_VERB_MASK 0xfffff000
313 313 #define AUDIOHDC_4BIT_VERB_MASK 0xfffffff0
314 314
315 315 #define AUDIOHDC_SAMPR48000 48000
316 316 #define AUDIOHDC_MAX_BEEP_GEN 12000
317 317 #define AUDIOHDC_MIX_BEEP_GEN 47
318 318 #define AUDIOHDC_MUTE_BEEP_GEN 0x0
319 319
320 320 /*
321 321 * 12-bit verbs
322 322 */
323 323 #define AUDIOHDC_VERB_GET_PARAM 0xf00
324 324
325 325 #define AUDIOHDC_VERB_GET_CONN_SEL 0xf01
326 326 #define AUDIOHDC_VERB_SET_CONN_SEL 0x701
327 327
328 328 #define AUDIOHDC_VERB_GET_CONN_LIST_ENT 0xf02
329 329 #define AUDIOHDC_VERB_GET_PROCESS_STATE 0xf03
330 330 #define AUDIOHDC_VERB_GET_SDI_SEL 0xf04
331 331
332 332 #define AUDIOHDC_VERB_GET_POWER_STATE 0xf05
333 333 #define AUDIOHDC_VERB_SET_POWER_STATE 0x705
334 334
335 335 #define AUDIOHDC_VERB_GET_STREAM_CHANN 0xf06
336 336 #define AUDIOHDC_VERB_SET_STREAM_CHANN 0x706
337 337
338 338 #define AUDIOHDC_VERB_GET_PIN_CTRL 0xf07
339 339 #define AUDIOHDC_VERB_SET_PIN_CTRL 0x707
340 340
341 341 #define AUDIOHDC_VERB_GET_UNS_ENABLE 0xf08
342 342 #define AUDIOHDC_VERB_SET_UNS_ENABLE 0x708
343 343
344 344 #define AUDIOHDC_VERB_GET_PIN_SENSE 0xf09
345 345 #define AUDIOHDC_VERB_GET_PIN_SENSE 0xf09
346 346 #define AUDIOHDC_VERB_EXEC_PIN_SENSE 0x709
347 347
348 348 #define AUDIOHDC_VERB_GET_BEEP_GEN 0xf0a
349 349 #define AUDIOHDC_VERB_SET_BEEP_GEN 0x70a
350 350
351 351 #define AUDIOHDC_VERB_GET_EAPD 0xf0c
352 352 #define AUDIOHDC_VERB_SET_EAPD 0x70c
353 353
354 354 #define AUDIOHDC_VERB_GET_DEFAULT_CONF 0xf1c
355 355 #define AUDIOHDC_VERB_GET_SPDIF_CTL 0xf0d
356 356 #define AUDIOHDC_VERB_SET_SPDIF_LCL 0x70d
357 357
358 358 #define AUDIOHDC_VERB_GET_GPIO_MASK 0xf16
359 359 #define AUDIOHDC_VERB_SET_GPIO_MASK 0x716
360 360
361 361 #define AUDIOHDC_VERB_GET_UNSOL_ENABLE_MASK 0xf19
362 362 #define AUDIOHDC_VERB_SET_UNSOL_ENABLE_MASK 0x719
363 363
364 364 #define AUDIOHDC_VERB_GET_GPIO_DIREC 0xf17
365 365 #define AUDIOHDC_VERB_SET_GPIO_DIREC 0x717
366 366
367 367 #define AUDIOHDC_VERB_GET_GPIO_DATA 0xf15
368 368 #define AUDIOHDC_VERB_SET_GPIO_DATA 0x715
369 369
370 370 #define AUDIOHDC_VERB_GET_GPIO_STCK 0xf1a
371 371 #define AUDIOHDC_VERB_SET_GPIO_STCK 0x71a
372 372
373 373 #define AUDIOHDC_GPIO_ENABLE 0xff
374 374 #define AUDIOHDC_GPIO_DIRECT 0xf1
375 375
376 376 #define AUDIOHDC_GPIO_DATA_CTRL 0xff
377 377 #define AUDIOHDC_GPIO_STCK_CTRL 0xff
378 378 /*
379 379 * 4-bit verbs
380 380 */
381 381 #define AUDIOHDC_VERB_GET_CONV_FMT 0xa
382 382 #define AUDIOHDC_VERB_SET_CONV_FMT 0x2
383 383
384 384 #define AUDIOHDC_VERB_GET_AMP_MUTE 0xb
385 385 #define AUDIOHDC_VERB_SET_AMP_MUTE 0x3
386 386 #define AUDIOHDC_VERB_SET_BEEP_VOL 0x3A0
387 387
388 388 /*
389 389 * parameters of nodes
390 390 */
391 391 #define AUDIOHDC_PAR_VENDOR_ID 0x00
392 392 #define AUDIOHDC_PAR_SUBSYS_ID 0x01
393 393 #define AUDIOHDC_PAR_REV_ID 0x02
394 394 #define AUDIOHDC_PAR_NODE_COUNT 0x04
395 395 #define AUDIOHDC_PAR_FUNCTION_TYPE 0x05
396 396 #define AUDIOHDC_PAR_AUDIO_FG_CAP 0x08
397 397 #define AUDIOHDC_PAR_AUDIO_WID_CAP 0x09
398 398 #define AUDIOHDC_PAR_PCM 0x0a
399 399 #define AUDIOHDC_PAR_STREAM 0x0b
400 400 #define AUDIOHDC_PAR_PIN_CAP 0x0c
401 401 #define AUDIOHDC_PAR_INAMP_CAP 0x0d
402 402 #define AUDIOHDC_PAR_CONNLIST_LEN 0x0e
403 403 #define AUDIOHDC_PAR_POWER_STATE 0x0f
404 404 #define AUDIOHDC_PAR_PROC_CAP 0x10
405 405 #define AUDIOHDC_PAR_GPIO_CAP 0x11
406 406 #define AUDIOHDC_PAR_OUTAMP_CAP 0x12
407 407
408 408 /*
409 409 * bits for get/set amplifier gain/mute
410 410 */
411 411 #define AUDIOHDC_AMP_SET_OUTPUT 0x8000
412 412 #define AUDIOHDC_AMP_SET_INPUT 0x4000
413 413 #define AUDIOHDC_AMP_SET_LEFT 0x2000
414 414 #define AUDIOHDC_AMP_SET_RIGHT 0x1000
415 415 #define AUDIOHDC_AMP_SET_MUTE 0x0080
416 416 #define AUDIOHDC_AMP_SET_LNR 0x3000
417 417 #define AUDIOHDC_AMP_SET_LR_INPUT 0x7000
418 418 #define AUDIOHDC_AMP_SET_LR_OUTPUT 0xb000
419 419 #define AUDIOHDC_AMP_SET_INDEX_OFFSET 8
420 420 #define AUDIOHDC_AMP_SET_GAIN_MASK 0x007f
421 421 #define AUDIOHDC_GAIN_MAX 0x7f
422 422 #define AUDIOHDC_GAIN_BITS 7
423 423 #define AUDIOHDC_GAIN_DEFAULT 0x0f
424 424
425 425 #define AUDIOHDC_AMP_GET_OUTPUT 0x8000
426 426 #define AUDIOHDC_AMP_GET_INPUT 0x0000
427 427
428 428 /* value used to set max volume for left output */
429 429 #define AUDIOHDC_AMP_LOUT_MAX \
430 430 (AUDIOHDC_AMP_SET_OUTPUT | \
431 431 AUDIOHDC_AMP_SET_LEFT | \
432 432 AUDIOHDC_GAIN_MAX)
433 433
434 434 /* value used to set max volume for right output */
435 435 #define AUDIOHDC_AMP_ROUT_MAX \
436 436 (AUDIOHDC_AMP_SET_OUTPUT | \
437 437 AUDIOHDC_AMP_SET_RIGHT | \
438 438 AUDIOHDC_GAIN_MAX)
439 439
440 440
441 441 /*
442 442 * Bits for pin widget control verb
443 443 */
444 444 #define AUDIOHDC_PIN_CONTROL_HP_ENABLE 0x80
445 445 #define AUDIOHDC_PIN_CONTROL_OUT_ENABLE 0x40
446 446 #define AUDIOHDC_PIN_CONTROL_IN_ENABLE 0x20
447 447
448 448 /*
449 449 * Bits for Amplifier capabilities
450 450 */
451 451 #define AUDIOHDC_AMP_CAP_MUTE_CAP 0x80000000
452 452 #define AUDIOHDC_AMP_CAP_STEP_SIZE 0x007f0000
453 453 #define AUDIOHDC_AMP_CAP_STEP_NUMS 0x00007f00
454 454 #define AUDIOHDC_AMP_CAP_0DB_OFFSET 0x0000007f
455 455
456 456
457 457 /*
458 458 * Bits for Audio Widget Capabilities
459 459 */
460 460 #define AUDIOHD_WIDCAP_STEREO 0x00000001
461 461 #define AUDIOHD_WIDCAP_INAMP 0x00000002
462 462 #define AUDIOHD_WIDCAP_OUTAMP 0x00000004
463 463 #define AUDIOHD_WIDCAP_AMP_OVRIDE 0x00000008
464 464 #define AUDIOHD_WIDCAP_FMT_OVRIDE 0x00000010
465 465 #define AUDIOHD_WIDCAP_STRIP 0x00000020
466 466 #define AUDIOHD_WIDCAP_PROC_WID 0x00000040
467 467 #define AUDIOHD_WIDCAP_UNSOL 0x00000080
468 468 #define AUDIOHD_WIDCAP_CONNLIST 0x00000100
469 469 #define AUDIOHD_WIDCAP_DIGIT 0x00000200
470 470 #define AUDIOHD_WIDCAP_PWRCTRL 0x00000400
471 471 #define AUDIOHD_WIDCAP_LRSWAP 0x00000800
472 472 #define AUDIOHD_WIDCAP_TYPE 0x00f00000
473 473 #define AUDIOHD_WIDCAP_TO_WIDTYPE(wcap) \
474 474 ((wcap & AUDIOHD_WIDCAP_TYPE) >> 20)
475 475
476 476 #define AUDIOHD_CODEC_FAILURE (uint32_t)(-1)
477 477
478 478 /* Higher sample/bits support */
479 479 #define AUDIOHD_BIT_DEPTH16 0x00020000
480 480 #define AUDIOHD_BIT_DEPTH24 0x00080000
481 481 #define AUDIOHD_SAMP_RATE48 0x00000040
482 482 #define AUDIOHD_SAMP_RATE96 0x00000100
483 483 #define AUDIOHD_SAMP_RATE192 0x00000400
484 484
485 485 /*
486 486 * buffer descriptor list entry of stream descriptor
487 487 */
488 488 typedef struct {
489 489 uint64_t sbde_addr;
490 490 uint32_t sbde_len;
491 491 uint32_t
492 492 sbde_ioc: 1,
493 493 reserved: 31;
494 494 }sd_bdle_t;
495 495
496 496
497 497 #define AUDIOHD_PLAY_STARTED 0x00000001
498 498 #define AUDIOHD_PLAY_EMPTY 0x00000002
499 499 #define AUDIOHD_PLAY_PAUSED 0x00000004
500 500 #define AUDIOHD_RECORD_STARTED 0x00000008
501 501
502 502 enum audiohda_widget_type {
503 503 WTYPE_AUDIO_OUT = 0,
504 504 WTYPE_AUDIO_IN,
505 505 WTYPE_AUDIO_MIX,
506 506 WTYPE_AUDIO_SEL,
507 507 WTYPE_PIN,
508 508 WTYPE_POWER,
509 509 WTYPE_VOL_KNOB,
510 510 WTYPE_BEEP,
511 511 WTYPE_VENDOR = 0xf
512 512 };
513 513
514 514 enum audiohda_device_type {
515 515 DTYPE_LINEOUT = 0,
516 516 DTYPE_SPEAKER,
517 517 DTYPE_HP_OUT,
518 518 DTYPE_CD,
519 519 DTYPE_SPDIF_OUT,
520 520 DTYPE_DIGIT_OUT,
521 521 DTYPE_MODEM_SIDE,
522 522 DTYPE_MODEM_HNAD_SIDE,
523 523 DTYPE_LINE_IN,
524 524 DTYPE_AUX,
525 525 DTYPE_MIC_IN,
526 526 DTYPE_TEL,
527 527 DTYPE_SPDIF_IN,
528 528 DTYPE_DIGIT_IN,
529 529 DTYPE_OTHER = 0x0f,
530 530 };
531 531
532 532 enum audiohd_pin_color {
533 533 AUDIOHD_PIN_UNKNOWN = 0,
534 534 AUDIOHD_PIN_BLACK,
535 535 AUDIOHD_PIN_GREY,
536 536 AUDIOHD_PIN_BLUE,
537 537 AUDIOHD_PIN_GREEN,
538 538 AUDIOHD_PIN_RED,
539 539 AUDIOHD_PIN_ORANGE,
540 540 AUDIOHD_PIN_YELLOW,
541 541 AUDIOHD_PIN_PURPLE,
542 542 AUDIOHD_PIN_PINK,
543 543 AUDIOHD_PIN_WHITE = 0xe,
544 544 AUDIOHD_PIN_OTHER = 0xf,
545 545 };
546 546
547 547 /* values for audiohd_widget.path_flags */
548 548 #define AUDIOHD_PATH_DAC (1 << 0)
549 549 #define AUDIOHD_PATH_ADC (1 << 1)
550 550 #define AUDIOHD_PATH_MON (1 << 2)
551 551 #define AUDIOHD_PATH_NOMON (1 << 3)
552 552 #define AUDIOHD_PATH_BEEP (1 << 4)
553 553 #define AUDIOHD_PATH_LOOPBACK (1 << 5)
554 554
555 555 typedef struct audiohd_path audiohd_path_t;
556 556 typedef struct audiohd_widget audiohd_widget_t;
557 557 typedef struct audiohd_state audiohd_state_t;
558 558 typedef struct audiohd_codec_info audiohd_codec_info_t;
559 559 typedef struct audiohd_pin audiohd_pin_t;
560 560 typedef struct hda_codec hda_codec_t;
561 561 typedef uint32_t wid_t; /* id of widget */
562 562 typedef struct audiohd_entry_prop audiohd_entry_prop_t;
563 563 typedef enum audiohda_device_type audiohda_device_type_t;
564 564 typedef enum audiohd_pin_color audiohd_pin_color_t;
565 565
566 566 #define AUDIOHD_MAX_WIDGET 128
567 567 #define AUDIOHD_MAX_CONN 16
568 568 #define AUDIOHD_MAX_PINS 16
569 569 #define AUDIOHD_MAX_DEPTH 8
570 570
571 571 struct audiohd_entry_prop {
572 572 uint32_t conn_len;
573 573 uint32_t mask_range;
574 574 uint32_t mask_wid;
575 575 wid_t input_wid;
576 576 int conns_per_entry;
577 577 int bits_per_conn;
578 578 };
579 579 struct audiohd_widget {
580 580 wid_t wid_wid;
581 581 hda_codec_t *codec;
582 582 enum audiohda_widget_type type;
583 583
584 584 uint32_t widget_cap;
585 585 uint32_t pcm_format;
586 586 uint32_t inamp_cap;
587 587 uint32_t outamp_cap;
588 588
589 589 uint32_t path_flags;
590 590
591 591 int out_weight;
592 592 int in_weight;
593 593 int finish;
594 594
595 595 /*
596 596 * available (input) connections. 0 means this widget
597 597 * has fixed connection
598 598 */
599 599 int nconns;
600 600
601 601 /*
602 602 * wid of possible & selected input & output connections
603 603 */
604 604 wid_t avail_conn[AUDIOHD_MAX_CONN];
605 605 wid_t output_path_next; /* output pin -> DAC */
606 606 wid_t input_path_next; /* ADC -> input pin */
607 607 wid_t monitor_path_next[AUDIOHD_MAX_CONN];
608 608 /* output pin -> input pin */
609 609 wid_t beep_path_next; /* output pin -> beep widget */
610 610 wid_t loopback_path_next; /* ADC -> output pin */
611 611
612 612 uint16_t used;
613 613
614 614 /*
615 615 * pointer to struct depending on widget type:
616 616 * 1. DAC audiohd_path_t
617 617 * 2. ADC audiohd_path_t
618 618 * 3. PIN audiohd_pin_t
619 619 */
620 620 void *priv;
621 621 };
622 622
623 623 #define AUDIOHD_FLAG_LINEOUT (1 << 0)
624 624 #define AUDIOHD_FLAG_SPEAKER (1 << 1)
625 625 #define AUDIOHD_FLAG_HP (1 << 2)
626 626 #define AUDIOHD_FLAG_MONO (1 << 3)
627 627
628 628 #define AUDIOHD_MAX_MIXER 5
629 629 #define AUDIOHD_MAX_PIN 4
630 630
631 631 #define PORT_DAC 0
632 632 #define PORT_ADC 1
633 633 #define PORT_MAX 2
634 634 typedef enum {
635 635 PLAY = 0,
636 636 RECORD = 1,
637 637 BEEP = 2,
638 638 LOOPBACK = 3,
639 639 } path_type_t;
640 640
641 641 struct audiohd_path {
642 642 wid_t adda_wid;
643 643 wid_t beep_wid;
644 644
645 645 wid_t pin_wid[AUDIOHD_MAX_PINS];
646 646 int sum_selconn[AUDIOHD_MAX_PINS];
647 647 int mon_wid[AUDIOHD_MAX_PIN][AUDIOHD_MAX_MIXER];
648 648 int pin_nums;
649 649 int maxmixer[AUDIOHD_MAX_PINS];
650 650
651 651 path_type_t path_type;
652 652
653 653 wid_t mute_wid;
654 654 int mute_dir;
655 655 wid_t gain_wid;
656 656 int gain_dir;
657 657 uint32_t gain_bits;
658 658
659 659 uint32_t pin_outputs;
660 660 uint8_t tag;
661 661
662 662 hda_codec_t *codec;
663 663
664 664 wid_t sum_wid;
665 665
666 666 audiohd_state_t *statep;
667 667 };
668 668
669 669 typedef struct audiohd_port
670 670 {
671 671 uint8_t nchan;
672 672 int index;
673 673 uint16_t regoff;
674 674
675 675 unsigned nframes;
676 676 size_t bufsize;
677 677 size_t fragsize;
678 678 uint64_t count;
679 679 int curpos;
680 680
681 681 uint_t format;
682 682 unsigned sync_dir;
683 683
684 684 ddi_dma_handle_t samp_dmah;
685 685 ddi_acc_handle_t samp_acch;
686 686 caddr_t samp_kaddr;
687 687 uint64_t samp_paddr;
688 688
689 689 ddi_dma_handle_t bdl_dmah;
690 690 ddi_acc_handle_t bdl_acch;
691 691 size_t bdl_size;
692 692 caddr_t bdl_kaddr;
693 693 uint64_t bdl_paddr;
694 694
695 695 audio_engine_t *engine;
696 696 audiohd_state_t *statep;
697 697 }audiohd_port_t;
698 698
699 699 enum {
700 700 CTL_VOLUME = 0,
701 701 CTL_FRONT,
702 702 CTL_SPEAKER,
703 703 CTL_HEADPHONE,
704 704 CTL_REAR,
705 705 CTL_CENTER,
706 706 CTL_SURROUND,
707 707 CTL_LFE,
708 708 CTL_IGAIN,
709 709 CTL_LINEIN,
710 710 CTL_MIC,
711 711 CTL_CD,
712 712 CTL_MONGAIN,
713 713 CTL_MONSRC,
714 714 CTL_RECSRC,
715 715 CTL_BEEP,
716 716 CTL_LOOP,
717 717
718 718 /* this one must be last */
719 719 CTL_MAX
720 720 };
721 721
722 722 typedef struct audiohd_ctrl
723 723 {
724 724 audiohd_state_t *statep;
725 725 audio_ctrl_t *ctrl;
726 726 int num;
727 727 uint64_t val;
728 728 } audiohd_ctrl_t;
729 729
730 730 struct audiohd_pin {
731 731 audiohd_pin_t *next;
732 732 wid_t wid;
733 733 wid_t mute_wid; /* node used to mute this pin */
734 734 int mute_dir; /* 1: input, 2: output */
735 735 wid_t gain_wid; /* node for gain control */
736 736 int gain_dir; /* _OUTPUT/_INPUT */
737 737 uint32_t gain_bits;
738 738
739 739 uint8_t vrefvalue; /* value of VRef */
740 740
741 741 uint32_t cap;
742 742 uint32_t config;
743 743 uint32_t ctrl;
744 744 uint32_t assoc;
745 745 uint32_t seq;
746 746 wid_t adc_wid;
747 747 wid_t dac_wid;
748 748 wid_t beep_wid;
749 749 int no_phys_conn;
750 750 enum audiohda_device_type device;
751 751
752 752 /*
753 753 * mg_dir, mg_gain, mg_wid are used to store the monitor gain control
754 754 * widget wid.
755 755 */
756 756 int mg_dir[AUDIOHD_MAX_CONN];
757 757 int mg_gain[AUDIOHD_MAX_CONN];
758 758 int mg_wid[AUDIOHD_MAX_CONN];
759 759 int num;
760 760 int finish;
761 761
762 762 };
763 763
764 764 typedef struct {
765 765 ddi_dma_handle_t ad_dmahdl;
766 766 ddi_acc_handle_t ad_acchdl;
767 767 caddr_t ad_vaddr; /* virtual addr */
768 768 uint64_t ad_paddr; /* physical addr */
769 769 size_t ad_req_sz; /* required size of memory */
770 770 size_t ad_real_sz; /* real size of memory */
771 771 } audiohd_dma_t;
772 772
773 773 struct hda_codec {
774 774 uint8_t index; /* codec address */
775 775 uint32_t vid; /* vendor id and device id */
776 776 uint32_t revid; /* revision id */
777 777 wid_t wid_afg; /* id of AFG */
778 778 wid_t first_wid; /* wid of 1st subnode of AFG */
779 779 wid_t last_wid; /* wid of the last subnode of AFG */
780 780 int nnodes; /* # of subnodes of AFG */
781 781 uint8_t nistream;
782 782
783 783 uint32_t outamp_cap;
784 784 uint32_t inamp_cap;
785 785 uint32_t stream_format;
786 786 uint32_t pcm_format;
787 787
788 788 audiohd_state_t *statep;
789 789 audiohd_codec_info_t *codec_info;
790 790
791 791 /* use wid as index to the array of widget pointers */
792 792 audiohd_widget_t *widget[AUDIOHD_MAX_WIDGET];
793 793
794 794 audiohd_port_t *port[AUDIOHD_PORT_MAX];
795 795 uint8_t portnum;
796 796 audiohd_pin_t *first_pin;
797 797 };
798 798
799 799 #define AUDIOHD_MAX_ASSOC 15
800 800 struct audiohd_state {
801 801 dev_info_t *hda_dip;
802 802 kstat_t *hda_ksp;
803 803 kmutex_t hda_mutex;
804 804 uint32_t hda_flags;
805 805
806 806 caddr_t hda_reg_base;
807 807 ddi_acc_handle_t hda_pci_handle;
808 808 ddi_acc_handle_t hda_reg_handle;
809 809
810 810 audiohd_dma_t hda_dma_corb;
811 811 audiohd_dma_t hda_dma_rirb;
812 812
813 813 uint8_t hda_rirb_rp; /* read pointer for rirb */
814 814 uint16_t hda_codec_mask;
815 815
816 816 audio_dev_t *adev;
817 817 uint32_t devid;
818 818
819 819 int hda_input_streams; /* # of input stream */
820 820 int hda_output_streams; /* # of output stream */
821 821 int hda_streams_nums; /* # of stream */
822 822
823 823 uint_t hda_play_regbase;
824 824 uint_t hda_record_regbase;
825 825
826 826 uint_t hda_play_stag; /* tag of playback stream */
827 827 uint_t hda_record_stag; /* tag of record stream */
828 828 uint_t hda_play_lgain; /* left gain for playback */
829 829 uint_t hda_play_rgain; /* right gain for playback */
830 830
831 831 /*
832 832 * Now, for the time being, we add some fields
833 833 * for parsing codec topology
834 834 */
835 835 hda_codec_t *codec[AUDIOHD_CODEC_MAX];
836 836
837 837 /*
838 838 * Suspend/Resume used fields
839 839 */
840 840 boolean_t suspended;
841 841
842 842 audiohd_path_t *path[AUDIOHD_PORT_MAX];
843 843 uint8_t pathnum;
844 844 audiohd_port_t *port[PORT_MAX];
845 845 uint8_t pchan;
846 846 uint8_t rchan;
847 847
848 848 uint64_t inmask;
849 849
850 850 uint_t hda_out_ports;
851 851 uint_t in_port;
852 852
853 853 /* Higher sample/rate */
854 854 uint32_t sample_rate;
855 855 uint32_t sample_bit_depth;
856 856 uint8_t sample_packed_bytes;
857 857
858 858 /*
859 859 * Controls
860 860 */
861 861 audiohd_ctrl_t ctrls[CTL_MAX];
862 862 boolean_t monitor_supported;
863 863 boolean_t loopback_supported;
864 864
865 865 /* for multichannel */
866 866 uint8_t chann[AUDIOHD_MAX_ASSOC];
867 867 uint8_t assoc;
868 868
869 869 };
870 870
871 871 struct audiohd_codec_info {
872 872 uint32_t devid;
873 873 const char *buf;
874 874 uint32_t flags;
875 875 };
876 876
877 877 /*
878 878 * Operation for high definition audio control system bus
879 879 * interface registers
880 880 */
881 881 #define AUDIOHD_REG_GET8(reg) \
882 882 ddi_get8(statep->hda_reg_handle, \
883 883 (void *)((char *)statep->hda_reg_base + (reg)))
884 884
885 885 #define AUDIOHD_REG_GET16(reg) \
886 886 ddi_get16(statep->hda_reg_handle, \
887 887 (void *)((char *)statep->hda_reg_base + (reg)))
888 888
889 889 #define AUDIOHD_REG_GET32(reg) \
890 890 ddi_get32(statep->hda_reg_handle, \
891 891 (void *)((char *)statep->hda_reg_base + (reg)))
892 892
893 893 #define AUDIOHD_REG_GET64(reg) \
894 894 ddi_get64(statep->hda_reg_handle, \
895 895 (void *)((char *)statep->hda_reg_base + (reg)))
896 896
897 897 #define AUDIOHD_REG_SET8(reg, val) \
898 898 ddi_put8(statep->hda_reg_handle, \
899 899 (void *)((char *)statep->hda_reg_base + (reg)), (val))
900 900
901 901 #define AUDIOHD_REG_SET16(reg, val) \
902 902 ddi_put16(statep->hda_reg_handle, \
903 903 (void *)((char *)statep->hda_reg_base + (reg)), (val))
904 904
905 905 #define AUDIOHD_REG_SET32(reg, val) \
906 906 ddi_put32(statep->hda_reg_handle, \
907 907 (void *)((char *)statep->hda_reg_base + (reg)), (val))
908 908
909 909 #define AUDIOHD_REG_SET64(reg, val) \
910 910 ddi_put64(statep->hda_reg_handle, \
911 911 (void *)((char *)statep->hda_reg_base + (reg)), (val))
912 912
913 913
914 914 /*
915 915 * enable a pin widget to input
916 916 */
917 917 #define AUDIOHD_ENABLE_PIN_IN(statep, caddr, wid) \
918 918 { \
919 919 (void) audioha_codec_verb_get(statep, caddr, wid, \
920 920 AUDIOHDC_VERB_SET_PIN_CTRL, AUDIOHDC_PIN_CONTROL_IN_ENABLE | 4); \
921 921 }
922 922
923 923 /*
924 924 * disable input pin
925 925 */
926 926 #define AUDIOHD_DISABLE_PIN_IN(statep, caddr, wid) \
927 927 { \
928 928 uint32_t lTmp; \
929 929 \
930 930 lTmp = audioha_codec_verb_get(statep, caddr, wid, \
931 931 AUDIOHDC_VERB_GET_PIN_CTRL, 0); \
932 932 if (lTmp == AUDIOHD_CODEC_FAILURE) \
933 933 return (DDI_FAILURE); \
934 934 lTmp = audioha_codec_verb_get(statep, caddr, wid, \
935 935 AUDIOHDC_VERB_SET_PIN_CTRL, \
936 936 (lTmp & ~AUDIOHDC_PIN_CONTROL_IN_ENABLE)); \
937 937 if (lTmp == AUDIOHD_CODEC_FAILURE) \
938 938 return (DDI_FAILURE); \
939 939 }
940 940
941 941 /*
942 942 * unmute an output pin
943 943 */
944 944 #define AUDIOHD_NODE_UNMUTE_OUT(statep, caddr, wid) \
945 945 { \
946 946 if (audioha_codec_4bit_verb_get(statep, \
947 947 caddr, wid, AUDIOHDC_VERB_SET_AMP_MUTE, \
948 948 AUDIOHDC_AMP_SET_LR_OUTPUT | AUDIOHDC_GAIN_MAX) == \
949 949 AUDIOHD_CODEC_FAILURE) \
950 950 return (DDI_FAILURE); \
951 951 }
952 952
953 953 /*
954 954 * check volume adjust value of 2 channels control
955 955 */
956 956 #define AUDIOHD_CHECK_2CHANNELS_VOLUME(value) \
957 957 { \
958 958 if ((value) & ~0xffff) \
959 959 return (EINVAL); \
960 960 if ((((value) & 0xff00) >> 8) > 100 || \
961 961 ((value) & 0xff) > 100) \
962 962 return (EINVAL); \
963 963 }
964 964
965 965 /*
966 966 * check volume adjust value of mono channel control
967 967 */
968 968 #define AUDIOHD_CHECK_CHANNEL_VOLUME(value) \
969 969 { \
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969 lines elided |
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970 970 if ((value) & ~0xff) \
971 971 return (EINVAL); \
972 972 if (((value) & 0xff) > 100) \
973 973 return (EINVAL); \
974 974 }
975 975
976 976 #ifdef __cplusplus
977 977 }
978 978 #endif
979 979
980 -/* Warlock annotation */
981 -_NOTE(DATA_READABLE_WITHOUT_LOCK(audiohd_ctrl::statep))
982 -_NOTE(DATA_READABLE_WITHOUT_LOCK(audiohd_state::inmask))
983 -_NOTE(DATA_READABLE_WITHOUT_LOCK(audiohd_state::adev))
984 -_NOTE(DATA_READABLE_WITHOUT_LOCK(audiohd_state::sample_bit_depth))
985 -_NOTE(DATA_READABLE_WITHOUT_LOCK(audiohd_state::sample_rate))
986 -_NOTE(READ_ONLY_DATA(audiohd_state::hda_reg_handle))
987 -_NOTE(DATA_READABLE_WITHOUT_LOCK(audiohd_widget::codec))
988 -_NOTE(DATA_READABLE_WITHOUT_LOCK(audiohd_widget::wid_wid))
989 -_NOTE(DATA_READABLE_WITHOUT_LOCK(hda_codec::index))
990 -_NOTE(DATA_READABLE_WITHOUT_LOCK(hda_codec::statep))
991 -_NOTE(DATA_READABLE_WITHOUT_LOCK(hda_codec::vid))
992 -_NOTE(DATA_READABLE_WITHOUT_LOCK(audiohd_port::nchan))
993 -_NOTE(DATA_READABLE_WITHOUT_LOCK(audiohd_port::statep))
994 -_NOTE(DATA_READABLE_WITHOUT_LOCK(audiohd_port::sync_dir))
995 -
996 980 #endif /* _SYS_AUDIOHD_IMPL_H_ */
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