1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright (c) 2010, Oracle and/or its affiliates. All rights reserved.
24 */
25 /*
26 * Copyright (c) 2010, Intel Corporation.
27 * All rights reserved.
28 */
29 /*
30 * Copyright (c) 2017, Joyent, Inc. All rights reserved.
31 */
32
33 /*
34 * To understand how the apix module interacts with the interrupt subsystem read
35 * the theory statement in uts/i86pc/os/intr.c.
36 */
37
38 /*
39 * PSMI 1.1 extensions are supported only in 2.6 and later versions.
40 * PSMI 1.2 extensions are supported only in 2.7 and later versions.
41 * PSMI 1.3 and 1.4 extensions are supported in Solaris 10.
42 * PSMI 1.5 extensions are supported in Solaris Nevada.
43 * PSMI 1.6 extensions are supported in Solaris Nevada.
44 * PSMI 1.7 extensions are supported in Solaris Nevada.
45 */
46 #define PSMI_1_7
47
48 #include <sys/processor.h>
49 #include <sys/time.h>
50 #include <sys/psm.h>
51 #include <sys/smp_impldefs.h>
52 #include <sys/cram.h>
53 #include <sys/acpi/acpi.h>
54 #include <sys/acpica.h>
55 #include <sys/psm_common.h>
56 #include <sys/pit.h>
57 #include <sys/ddi.h>
58 #include <sys/sunddi.h>
59 #include <sys/ddi_impldefs.h>
60 #include <sys/pci.h>
61 #include <sys/promif.h>
62 #include <sys/x86_archext.h>
63 #include <sys/cpc_impl.h>
64 #include <sys/uadmin.h>
65 #include <sys/panic.h>
66 #include <sys/debug.h>
67 #include <sys/archsystm.h>
68 #include <sys/trap.h>
69 #include <sys/machsystm.h>
70 #include <sys/sysmacros.h>
71 #include <sys/cpuvar.h>
72 #include <sys/rm_platter.h>
73 #include <sys/privregs.h>
74 #include <sys/note.h>
75 #include <sys/pci_intr_lib.h>
76 #include <sys/spl.h>
77 #include <sys/clock.h>
78 #include <sys/cyclic.h>
79 #include <sys/dditypes.h>
80 #include <sys/sunddi.h>
81 #include <sys/x_call.h>
82 #include <sys/reboot.h>
83 #include <sys/mach_intr.h>
84 #include <sys/apix.h>
85 #include <sys/apix_irm_impl.h>
86
87 static int apix_probe();
88 static void apix_init();
89 static void apix_picinit(void);
90 static int apix_intr_enter(int, int *);
91 static void apix_intr_exit(int, int);
92 static void apix_setspl(int);
93 static int apix_disable_intr(processorid_t);
94 static void apix_enable_intr(processorid_t);
95 static int apix_get_clkvect(int);
96 static int apix_get_ipivect(int, int);
97 static void apix_post_cyclic_setup(void *);
98 static int apix_post_cpu_start();
99 static int apix_intr_ops(dev_info_t *, ddi_intr_handle_impl_t *,
100 psm_intr_op_t, int *);
101
102 /*
103 * Helper functions for apix_intr_ops()
104 */
105 static void apix_redistribute_compute(void);
106 static int apix_get_pending(apix_vector_t *);
107 static apix_vector_t *apix_get_req_vector(ddi_intr_handle_impl_t *, ushort_t);
108 static int apix_get_intr_info(ddi_intr_handle_impl_t *, apic_get_intr_t *);
109 static char *apix_get_apic_type(void);
110 static int apix_intx_get_pending(int);
111 static void apix_intx_set_mask(int irqno);
112 static void apix_intx_clear_mask(int irqno);
113 static int apix_intx_get_shared(int irqno);
114 static void apix_intx_set_shared(int irqno, int delta);
115 static apix_vector_t *apix_intx_xlate_vector(dev_info_t *, int,
116 struct intrspec *);
117 static int apix_intx_alloc_vector(dev_info_t *, ddi_intr_handle_impl_t *,
118 struct intrspec *);
119
120 extern int apic_clkinit(int);
121
122 /* IRM initialization for APIX PSM module */
123 extern void apix_irm_init(void);
124
125 extern int irm_enable;
126
127 /*
128 * Local static data
129 */
130 static struct psm_ops apix_ops = {
131 apix_probe,
132
133 apix_init,
134 apix_picinit,
135 apix_intr_enter,
136 apix_intr_exit,
137 apix_setspl,
138 apix_addspl,
139 apix_delspl,
140 apix_disable_intr,
141 apix_enable_intr,
142 NULL, /* psm_softlvl_to_irq */
143 NULL, /* psm_set_softintr */
144
145 apic_set_idlecpu,
146 apic_unset_idlecpu,
147
148 apic_clkinit,
149 apix_get_clkvect,
150 NULL, /* psm_hrtimeinit */
151 apic_gethrtime,
152
153 apic_get_next_processorid,
154 apic_cpu_start,
155 apix_post_cpu_start,
156 apic_shutdown,
157 apix_get_ipivect,
158 apic_send_ipi,
159
160 NULL, /* psm_translate_irq */
161 NULL, /* psm_notify_error */
162 NULL, /* psm_notify_func */
163 apic_timer_reprogram,
164 apic_timer_enable,
165 apic_timer_disable,
166 apix_post_cyclic_setup,
167 apic_preshutdown,
168 apix_intr_ops, /* Advanced DDI Interrupt framework */
169 apic_state, /* save, restore apic state for S3 */
170 apic_cpu_ops, /* CPU control interface. */
171 };
172
173 struct psm_ops *psmops = &apix_ops;
174
175 static struct psm_info apix_psm_info = {
176 PSM_INFO_VER01_7, /* version */
177 PSM_OWN_EXCLUSIVE, /* ownership */
178 &apix_ops, /* operation */
179 APIX_NAME, /* machine name */
180 "apix MPv1.4 compatible",
181 };
182
183 static void *apix_hdlp;
184
185 static int apix_is_enabled = 0;
186
187 /*
188 * Flag to indicate if APIX is to be enabled only for platforms
189 * with specific hw feature(s).
190 */
191 int apix_hw_chk_enable = 1;
192
193 /*
194 * Hw features that are checked for enabling APIX support.
195 */
196 #define APIX_SUPPORT_X2APIC 0x00000001
197 uint_t apix_supported_hw = APIX_SUPPORT_X2APIC;
198
199 /*
200 * apix_lock is used for cpu selection and vector re-binding
201 */
202 lock_t apix_lock;
203 apix_impl_t *apixs[NCPU];
204 /*
205 * Mapping between device interrupt and the allocated vector. Indexed
206 * by major number.
207 */
208 apix_dev_vector_t **apix_dev_vector;
209 /*
210 * Mapping between device major number and cpu id. It gets used
211 * when interrupt binding policy round robin with affinity is
212 * applied. With that policy, devices with the same major number
213 * will be bound to the same CPU.
214 */
215 processorid_t *apix_major_to_cpu; /* major to cpu mapping */
216 kmutex_t apix_mutex; /* for apix_dev_vector & apix_major_to_cpu */
217
218 int apix_nipis = 16; /* Maximum number of IPIs */
219 /*
220 * Maximum number of vectors in a CPU that can be used for interrupt
221 * allocation (including IPIs and the reserved vectors).
222 */
223 int apix_cpu_nvectors = APIX_NVECTOR;
224
225 /* number of CPUs in power-on transition state */
226 static int apic_poweron_cnt = 0;
227
228 /* gcpu.h */
229
230 extern void apic_do_interrupt(struct regs *rp, trap_trace_rec_t *ttp);
231 extern void apic_change_eoi();
232
233 /*
234 * This is the loadable module wrapper
235 */
236
237 int
238 _init(void)
239 {
240 if (apic_coarse_hrtime)
241 apix_ops.psm_gethrtime = &apic_gettime;
242 return (psm_mod_init(&apix_hdlp, &apix_psm_info));
243 }
244
245 int
246 _fini(void)
247 {
248 return (psm_mod_fini(&apix_hdlp, &apix_psm_info));
249 }
250
251 int
252 _info(struct modinfo *modinfop)
253 {
254 return (psm_mod_info(&apix_hdlp, &apix_psm_info, modinfop));
255 }
256
257 static int
258 apix_probe()
259 {
260 int rval;
261
262 if (apix_enable == 0)
263 return (PSM_FAILURE);
264
265 /* check for hw features if specified */
266 if (apix_hw_chk_enable) {
267 /* check if x2APIC mode is supported */
268 if ((apix_supported_hw & APIX_SUPPORT_X2APIC) ==
269 APIX_SUPPORT_X2APIC) {
270 if (apic_local_mode() == LOCAL_X2APIC) {
271 /* x2APIC mode activated by BIOS, switch ops */
272 apic_mode = LOCAL_X2APIC;
273 apic_change_ops();
274 } else if (!apic_detect_x2apic()) {
275 /* x2APIC mode is not supported in the hw */
276 apix_enable = 0;
277 }
278 }
279 if (apix_enable == 0)
280 return (PSM_FAILURE);
281 }
282
283 rval = apic_probe_common(apix_psm_info.p_mach_idstring);
284 if (rval == PSM_SUCCESS)
285 apix_is_enabled = 1;
286 else
287 apix_is_enabled = 0;
288 return (rval);
289 }
290
291 /*
292 * Initialize the data structures needed by pcplusmpx module.
293 * Specifically, the data structures used by addspl() and delspl()
294 * routines.
295 */
296 static void
297 apix_softinit()
298 {
299 int i, *iptr;
300 apix_impl_t *hdlp;
301 int nproc;
302
303 nproc = max(apic_nproc, apic_max_nproc);
304
305 hdlp = kmem_zalloc(nproc * sizeof (apix_impl_t), KM_SLEEP);
306 for (i = 0; i < nproc; i++) {
307 apixs[i] = &hdlp[i];
308 apixs[i]->x_cpuid = i;
309 LOCK_INIT_CLEAR(&apixs[i]->x_lock);
310 }
311
312 /* cpu 0 is always up (for now) */
313 apic_cpus[0].aci_status = APIC_CPU_ONLINE | APIC_CPU_INTR_ENABLE;
314
315 iptr = (int *)&apic_irq_table[0];
316 for (i = 0; i <= APIC_MAX_VECTOR; i++) {
317 apic_level_intr[i] = 0;
318 *iptr++ = NULL;
319 }
320 mutex_init(&airq_mutex, NULL, MUTEX_DEFAULT, NULL);
321
322 apix_dev_vector = kmem_zalloc(sizeof (apix_dev_vector_t *) * devcnt,
323 KM_SLEEP);
324
325 if (apic_intr_policy == INTR_ROUND_ROBIN_WITH_AFFINITY) {
326 apix_major_to_cpu = kmem_zalloc(sizeof (int) * devcnt,
327 KM_SLEEP);
328 for (i = 0; i < devcnt; i++)
329 apix_major_to_cpu[i] = IRQ_UNINIT;
330 }
331
332 mutex_init(&apix_mutex, NULL, MUTEX_DEFAULT, NULL);
333 }
334
335 static int
336 apix_get_pending_spl(void)
337 {
338 int cpuid = CPU->cpu_id;
339
340 return (bsrw_insn(apixs[cpuid]->x_intr_pending));
341 }
342
343 static uintptr_t
344 apix_get_intr_handler(int cpu, short vec)
345 {
346 apix_vector_t *apix_vector;
347
348 ASSERT(cpu < apic_nproc && vec < APIX_NVECTOR);
349 if (cpu >= apic_nproc)
350 return (NULL);
351
352 apix_vector = apixs[cpu]->x_vectbl[vec];
353
354 return ((uintptr_t)(apix_vector->v_autovect));
355 }
356
357 static void
358 apix_init()
359 {
360 extern void (*do_interrupt_common)(struct regs *, trap_trace_rec_t *);
361
362 APIC_VERBOSE(INIT, (CE_CONT, "apix: psm_softinit\n"));
363
364 do_interrupt_common = apix_do_interrupt;
365 addintr = apix_add_avintr;
366 remintr = apix_rem_avintr;
367 get_pending_spl = apix_get_pending_spl;
368 get_intr_handler = apix_get_intr_handler;
369 psm_get_localapicid = apic_get_localapicid;
370 psm_get_ioapicid = apic_get_ioapicid;
371
372 apix_softinit();
373
374 #if !defined(__amd64)
375 if (cpuid_have_cr8access(CPU))
376 apic_have_32bit_cr8 = 1;
377 #endif
378
379 /*
380 * Initialize IRM pool parameters
381 */
382 if (irm_enable) {
383 int i;
384 int lowest_irq;
385 int highest_irq;
386
387 /* number of CPUs present */
388 apix_irminfo.apix_ncpus = apic_nproc;
389 /* total number of entries in all of the IOAPICs present */
390 lowest_irq = apic_io_vectbase[0];
391 highest_irq = apic_io_vectend[0];
392 for (i = 1; i < apic_io_max; i++) {
393 if (apic_io_vectbase[i] < lowest_irq)
394 lowest_irq = apic_io_vectbase[i];
395 if (apic_io_vectend[i] > highest_irq)
396 highest_irq = apic_io_vectend[i];
397 }
398 apix_irminfo.apix_ioapic_max_vectors =
399 highest_irq - lowest_irq + 1;
400 /*
401 * Number of available per-CPU vectors excluding
402 * reserved vectors for Dtrace, int80, system-call,
403 * fast-trap, etc.
404 */
405 apix_irminfo.apix_per_cpu_vectors = APIX_NAVINTR -
406 APIX_SW_RESERVED_VECTORS;
407
408 /* Number of vectors (pre) allocated (SCI and HPET) */
409 apix_irminfo.apix_vectors_allocated = 0;
410 if (apic_hpet_vect != -1)
411 apix_irminfo.apix_vectors_allocated++;
412 if (apic_sci_vect != -1)
413 apix_irminfo.apix_vectors_allocated++;
414 }
415 }
416
417 static void
418 apix_init_intr()
419 {
420 processorid_t cpun = psm_get_cpu_id();
421 uint_t nlvt;
422 uint32_t svr = AV_UNIT_ENABLE | APIC_SPUR_INTR;
423 extern void cmi_cmci_trap(void);
424
425 apic_reg_ops->apic_write_task_reg(APIC_MASK_ALL);
426
427 if (apic_mode == LOCAL_APIC) {
428 /*
429 * We are running APIC in MMIO mode.
430 */
431 if (apic_flat_model) {
432 apic_reg_ops->apic_write(APIC_FORMAT_REG,
433 APIC_FLAT_MODEL);
434 } else {
435 apic_reg_ops->apic_write(APIC_FORMAT_REG,
436 APIC_CLUSTER_MODEL);
437 }
438
439 apic_reg_ops->apic_write(APIC_DEST_REG,
440 AV_HIGH_ORDER >> cpun);
441 }
442
443 if (apic_directed_EOI_supported()) {
444 /*
445 * Setting the 12th bit in the Spurious Interrupt Vector
446 * Register suppresses broadcast EOIs generated by the local
447 * APIC. The suppression of broadcast EOIs happens only when
448 * interrupts are level-triggered.
449 */
450 svr |= APIC_SVR_SUPPRESS_BROADCAST_EOI;
451 }
452
453 /* need to enable APIC before unmasking NMI */
454 apic_reg_ops->apic_write(APIC_SPUR_INT_REG, svr);
455
456 /*
457 * Presence of an invalid vector with delivery mode AV_FIXED can
458 * cause an error interrupt, even if the entry is masked...so
459 * write a valid vector to LVT entries along with the mask bit
460 */
461
462 /* All APICs have timer and LINT0/1 */
463 apic_reg_ops->apic_write(APIC_LOCAL_TIMER, AV_MASK|APIC_RESV_IRQ);
464 apic_reg_ops->apic_write(APIC_INT_VECT0, AV_MASK|APIC_RESV_IRQ);
465 apic_reg_ops->apic_write(APIC_INT_VECT1, AV_NMI); /* enable NMI */
466
467 /*
468 * On integrated APICs, the number of LVT entries is
469 * 'Max LVT entry' + 1; on 82489DX's (non-integrated
470 * APICs), nlvt is "3" (LINT0, LINT1, and timer)
471 */
472
473 if (apic_cpus[cpun].aci_local_ver < APIC_INTEGRATED_VERS) {
474 nlvt = 3;
475 } else {
476 nlvt = ((apic_reg_ops->apic_read(APIC_VERS_REG) >> 16) &
477 0xFF) + 1;
478 }
479
480 if (nlvt >= 5) {
481 /* Enable performance counter overflow interrupt */
482
483 if (!is_x86_feature(x86_featureset, X86FSET_MSR))
484 apic_enable_cpcovf_intr = 0;
485 if (apic_enable_cpcovf_intr) {
486 if (apic_cpcovf_vect == 0) {
487 int ipl = APIC_PCINT_IPL;
488
489 apic_cpcovf_vect = apix_get_ipivect(ipl, -1);
490 ASSERT(apic_cpcovf_vect);
491
492 (void) add_avintr(NULL, ipl,
493 (avfunc)kcpc_hw_overflow_intr,
494 "apic pcint", apic_cpcovf_vect,
495 NULL, NULL, NULL, NULL);
496 kcpc_hw_overflow_intr_installed = 1;
497 kcpc_hw_enable_cpc_intr =
498 apic_cpcovf_mask_clear;
499 }
500 apic_reg_ops->apic_write(APIC_PCINT_VECT,
501 apic_cpcovf_vect);
502 }
503 }
504
505 if (nlvt >= 6) {
506 /* Only mask TM intr if the BIOS apparently doesn't use it */
507
508 uint32_t lvtval;
509
510 lvtval = apic_reg_ops->apic_read(APIC_THERM_VECT);
511 if (((lvtval & AV_MASK) == AV_MASK) ||
512 ((lvtval & AV_DELIV_MODE) != AV_SMI)) {
513 apic_reg_ops->apic_write(APIC_THERM_VECT,
514 AV_MASK|APIC_RESV_IRQ);
515 }
516 }
517
518 /* Enable error interrupt */
519
520 if (nlvt >= 4 && apic_enable_error_intr) {
521 if (apic_errvect == 0) {
522 int ipl = 0xf; /* get highest priority intr */
523 apic_errvect = apix_get_ipivect(ipl, -1);
524 ASSERT(apic_errvect);
525 /*
526 * Not PSMI compliant, but we are going to merge
527 * with ON anyway
528 */
529 (void) add_avintr(NULL, ipl,
530 (avfunc)apic_error_intr, "apic error intr",
531 apic_errvect, NULL, NULL, NULL, NULL);
532 }
533 apic_reg_ops->apic_write(APIC_ERR_VECT, apic_errvect);
534 apic_reg_ops->apic_write(APIC_ERROR_STATUS, 0);
535 apic_reg_ops->apic_write(APIC_ERROR_STATUS, 0);
536 }
537
538 /* Enable CMCI interrupt */
539 if (cmi_enable_cmci) {
540 mutex_enter(&cmci_cpu_setup_lock);
541 if (cmci_cpu_setup_registered == 0) {
542 mutex_enter(&cpu_lock);
543 register_cpu_setup_func(cmci_cpu_setup, NULL);
544 mutex_exit(&cpu_lock);
545 cmci_cpu_setup_registered = 1;
546 }
547 mutex_exit(&cmci_cpu_setup_lock);
548
549 if (apic_cmci_vect == 0) {
550 int ipl = 0x2;
551 apic_cmci_vect = apix_get_ipivect(ipl, -1);
552 ASSERT(apic_cmci_vect);
553
554 (void) add_avintr(NULL, ipl,
555 (avfunc)cmi_cmci_trap, "apic cmci intr",
556 apic_cmci_vect, NULL, NULL, NULL, NULL);
557 }
558 apic_reg_ops->apic_write(APIC_CMCI_VECT, apic_cmci_vect);
559 }
560
561 apic_reg_ops->apic_write_task_reg(0);
562 }
563
564 static void
565 apix_picinit(void)
566 {
567 int i, j;
568 uint_t isr;
569
570 APIC_VERBOSE(INIT, (CE_CONT, "apix: psm_picinit\n"));
571
572 /*
573 * initialize interrupt remapping before apic
574 * hardware initialization
575 */
576 apic_intrmap_init(apic_mode);
577 if (apic_vt_ops == psm_vt_ops)
578 apix_mul_ioapic_method = APIC_MUL_IOAPIC_IIR;
579
580 /*
581 * On UniSys Model 6520, the BIOS leaves vector 0x20 isr
582 * bit on without clearing it with EOI. Since softint
583 * uses vector 0x20 to interrupt itself, so softint will
584 * not work on this machine. In order to fix this problem
585 * a check is made to verify all the isr bits are clear.
586 * If not, EOIs are issued to clear the bits.
587 */
588 for (i = 7; i >= 1; i--) {
589 isr = apic_reg_ops->apic_read(APIC_ISR_REG + (i * 4));
590 if (isr != 0)
591 for (j = 0; ((j < 32) && (isr != 0)); j++)
592 if (isr & (1 << j)) {
593 apic_reg_ops->apic_write(
594 APIC_EOI_REG, 0);
595 isr &= ~(1 << j);
596 apic_error |= APIC_ERR_BOOT_EOI;
597 }
598 }
599
600 /* set a flag so we know we have run apic_picinit() */
601 apic_picinit_called = 1;
602 LOCK_INIT_CLEAR(&apic_gethrtime_lock);
603 LOCK_INIT_CLEAR(&apic_ioapic_lock);
604 LOCK_INIT_CLEAR(&apic_error_lock);
605 LOCK_INIT_CLEAR(&apic_mode_switch_lock);
606
607 picsetup(); /* initialise the 8259 */
608
609 /* add nmi handler - least priority nmi handler */
610 LOCK_INIT_CLEAR(&apic_nmi_lock);
611
612 if (!psm_add_nmintr(0, (avfunc) apic_nmi_intr,
613 "apix NMI handler", (caddr_t)NULL))
614 cmn_err(CE_WARN, "apix: Unable to add nmi handler");
615
616 apix_init_intr();
617
618 /* enable apic mode if imcr present */
619 if (apic_imcrp) {
620 outb(APIC_IMCR_P1, (uchar_t)APIC_IMCR_SELECT);
621 outb(APIC_IMCR_P2, (uchar_t)APIC_IMCR_APIC);
622 }
623
624 ioapix_init_intr(IOAPIC_MASK);
625
626 /* setup global IRM pool if applicable */
627 if (irm_enable)
628 apix_irm_init();
629 }
630
631 static __inline__ void
632 apix_send_eoi(void)
633 {
634 if (apic_mode == LOCAL_APIC)
635 LOCAL_APIC_WRITE_REG(APIC_EOI_REG, 0);
636 else
637 X2APIC_WRITE(APIC_EOI_REG, 0);
638 }
639
640 /*
641 * platform_intr_enter
642 *
643 * Called at the beginning of the interrupt service routine, but unlike
644 * pcplusmp, does not mask interrupts. An EOI is given to the interrupt
645 * controller to enable other HW interrupts but interrupts are still
646 * masked by the IF flag.
647 *
648 * Return -1 for spurious interrupts
649 *
650 */
651 static int
652 apix_intr_enter(int ipl, int *vectorp)
653 {
654 struct cpu *cpu = CPU;
655 uint32_t cpuid = CPU->cpu_id;
656 apic_cpus_info_t *cpu_infop;
657 uchar_t vector;
658 apix_vector_t *vecp;
659 int nipl = -1;
660
661 /*
662 * The real vector delivered is (*vectorp + 0x20), but our caller
663 * subtracts 0x20 from the vector before passing it to us.
664 * (That's why APIC_BASE_VECT is 0x20.)
665 */
666 vector = *vectorp = (uchar_t)*vectorp + APIC_BASE_VECT;
667
668 cpu_infop = &apic_cpus[cpuid];
669 if (vector == APIC_SPUR_INTR) {
670 cpu_infop->aci_spur_cnt++;
671 return (APIC_INT_SPURIOUS);
672 }
673
674 vecp = xv_vector(cpuid, vector);
675 if (vecp == NULL) {
676 if (APIX_IS_FAKE_INTR(vector))
677 nipl = apix_rebindinfo.i_pri;
678 apix_send_eoi();
679 return (nipl);
680 }
681 nipl = vecp->v_pri;
682
683 /* if interrupted by the clock, increment apic_nsec_since_boot */
684 if (vector == (apic_clkvect + APIC_BASE_VECT)) {
685 if (!apic_oneshot) {
686 /* NOTE: this is not MT aware */
687 apic_hrtime_stamp++;
688 apic_nsec_since_boot += apic_nsec_per_intr;
689 apic_hrtime_stamp++;
690 last_count_read = apic_hertz_count;
691 apix_redistribute_compute();
692 }
693
694 apix_send_eoi();
695
696 return (nipl);
697 }
698
699 ASSERT(vecp->v_state != APIX_STATE_OBSOLETED);
700
701 /* pre-EOI handling for level-triggered interrupts */
702 if (!APIX_IS_DIRECTED_EOI(apix_mul_ioapic_method) &&
703 (vecp->v_type & APIX_TYPE_FIXED) && apic_level_intr[vecp->v_inum])
704 apix_level_intr_pre_eoi(vecp->v_inum);
705
706 /* send back EOI */
707 apix_send_eoi();
708
709 cpu_infop->aci_current[nipl] = vector;
710 if ((nipl > ipl) && (nipl > cpu->cpu_base_spl)) {
711 cpu_infop->aci_curipl = (uchar_t)nipl;
712 cpu_infop->aci_ISR_in_progress |= 1 << nipl;
713 }
714
715 #ifdef DEBUG
716 if (vector >= APIX_IPI_MIN)
717 return (nipl); /* skip IPI */
718
719 APIC_DEBUG_BUF_PUT(vector);
720 APIC_DEBUG_BUF_PUT(vecp->v_inum);
721 APIC_DEBUG_BUF_PUT(nipl);
722 APIC_DEBUG_BUF_PUT(psm_get_cpu_id());
723 if ((apic_stretch_interrupts) && (apic_stretch_ISR & (1 << nipl)))
724 drv_usecwait(apic_stretch_interrupts);
725 #endif /* DEBUG */
726
727 return (nipl);
728 }
729
730 /*
731 * Any changes made to this function must also change X2APIC
732 * version of intr_exit.
733 */
734 static void
735 apix_intr_exit(int prev_ipl, int arg2)
736 {
737 int cpuid = psm_get_cpu_id();
738 apic_cpus_info_t *cpu_infop = &apic_cpus[cpuid];
739 apix_impl_t *apixp = apixs[cpuid];
740
741 UNREFERENCED_1PARAMETER(arg2);
742
743 cpu_infop->aci_curipl = (uchar_t)prev_ipl;
744 /* ISR above current pri could not be in progress */
745 cpu_infop->aci_ISR_in_progress &= (2 << prev_ipl) - 1;
746
747 if (apixp->x_obsoletes != NULL) {
748 if (APIX_CPU_LOCK_HELD(cpuid))
749 return;
750
751 APIX_ENTER_CPU_LOCK(cpuid);
752 (void) apix_obsolete_vector(apixp->x_obsoletes);
753 APIX_LEAVE_CPU_LOCK(cpuid);
754 }
755 }
756
757 /*
758 * The pcplusmp setspl code uses the TPR to mask all interrupts at or below the
759 * given ipl, but apix never uses the TPR and we never mask a subset of the
760 * interrupts. They are either all blocked by the IF flag or all can come in.
761 *
762 * For setspl, we mask all interrupts for XC_HI_PIL (15), otherwise, interrupts
763 * can come in if currently enabled by the IF flag. This table shows the state
764 * of the IF flag when we leave this function.
765 *
766 * curr IF | ipl == 15 ipl != 15
767 * --------+---------------------------
768 * 0 | 0 0
769 * 1 | 0 1
770 */
771 static void
772 apix_setspl(int ipl)
773 {
774 /*
775 * Interrupts at ipl above this cannot be in progress, so the following
776 * mask is ok.
777 */
778 apic_cpus[psm_get_cpu_id()].aci_ISR_in_progress &= (2 << ipl) - 1;
779
780 if (ipl == XC_HI_PIL)
781 cli();
782 }
783
784 int
785 apix_addspl(int virtvec, int ipl, int min_ipl, int max_ipl)
786 {
787 uint32_t cpuid = APIX_VIRTVEC_CPU(virtvec);
788 uchar_t vector = (uchar_t)APIX_VIRTVEC_VECTOR(virtvec);
789 apix_vector_t *vecp = xv_vector(cpuid, vector);
790
791 UNREFERENCED_3PARAMETER(ipl, min_ipl, max_ipl);
792 ASSERT(vecp != NULL && LOCK_HELD(&apix_lock));
793
794 if (vecp->v_type == APIX_TYPE_FIXED)
795 apix_intx_set_shared(vecp->v_inum, 1);
796
797 /* There are more interrupts, so it's already been enabled */
798 if (vecp->v_share > 1)
799 return (PSM_SUCCESS);
800
801 /* return if it is not hardware interrupt */
802 if (vecp->v_type == APIX_TYPE_IPI)
803 return (PSM_SUCCESS);
804
805 /*
806 * if apix_picinit() has not been called yet, just return.
807 * At the end of apic_picinit(), we will call setup_io_intr().
808 */
809 if (!apic_picinit_called)
810 return (PSM_SUCCESS);
811
812 (void) apix_setup_io_intr(vecp);
813
814 return (PSM_SUCCESS);
815 }
816
817 int
818 apix_delspl(int virtvec, int ipl, int min_ipl, int max_ipl)
819 {
820 uint32_t cpuid = APIX_VIRTVEC_CPU(virtvec);
821 uchar_t vector = (uchar_t)APIX_VIRTVEC_VECTOR(virtvec);
822 apix_vector_t *vecp = xv_vector(cpuid, vector);
823
824 UNREFERENCED_3PARAMETER(ipl, min_ipl, max_ipl);
825 ASSERT(vecp != NULL && LOCK_HELD(&apix_lock));
826
827 if (vecp->v_type == APIX_TYPE_FIXED)
828 apix_intx_set_shared(vecp->v_inum, -1);
829
830 /* There are more interrupts */
831 if (vecp->v_share > 1)
832 return (PSM_SUCCESS);
833
834 /* return if it is not hardware interrupt */
835 if (vecp->v_type == APIX_TYPE_IPI)
836 return (PSM_SUCCESS);
837
838 if (!apic_picinit_called) {
839 cmn_err(CE_WARN, "apix: delete 0x%x before apic init",
840 virtvec);
841 return (PSM_SUCCESS);
842 }
843
844 apix_disable_vector(vecp);
845
846 return (PSM_SUCCESS);
847 }
848
849 /*
850 * Try and disable all interrupts. We just assign interrupts to other
851 * processors based on policy. If any were bound by user request, we
852 * let them continue and return failure. We do not bother to check
853 * for cache affinity while rebinding.
854 */
855 static int
856 apix_disable_intr(processorid_t cpun)
857 {
858 apix_impl_t *apixp = apixs[cpun];
859 apix_vector_t *vecp, *newp;
860 int bindcpu, i, hardbound = 0, errbound = 0, ret, loop, type;
861
862 lock_set(&apix_lock);
863
864 apic_cpus[cpun].aci_status &= ~APIC_CPU_INTR_ENABLE;
865 apic_cpus[cpun].aci_curipl = 0;
866
867 /* if this is for SUSPEND operation, skip rebinding */
868 if (apic_cpus[cpun].aci_status & APIC_CPU_SUSPEND) {
869 for (i = APIX_AVINTR_MIN; i <= APIX_AVINTR_MAX; i++) {
870 vecp = apixp->x_vectbl[i];
871 if (!IS_VECT_ENABLED(vecp))
872 continue;
873
874 apix_disable_vector(vecp);
875 }
876 lock_clear(&apix_lock);
877 return (PSM_SUCCESS);
878 }
879
880 for (i = APIX_AVINTR_MIN; i <= APIX_AVINTR_MAX; i++) {
881 vecp = apixp->x_vectbl[i];
882 if (!IS_VECT_ENABLED(vecp))
883 continue;
884
885 if (vecp->v_flags & APIX_VECT_USER_BOUND) {
886 hardbound++;
887 continue;
888 }
889 type = vecp->v_type;
890
891 /*
892 * If there are bound interrupts on this cpu, then
893 * rebind them to other processors.
894 */
895 loop = 0;
896 do {
897 bindcpu = apic_find_cpu(APIC_CPU_INTR_ENABLE);
898
899 if (type != APIX_TYPE_MSI)
900 newp = apix_set_cpu(vecp, bindcpu, &ret);
901 else
902 newp = apix_grp_set_cpu(vecp, bindcpu, &ret);
903 } while ((newp == NULL) && (loop++ < apic_nproc));
904
905 if (loop >= apic_nproc) {
906 errbound++;
907 cmn_err(CE_WARN, "apix: failed to rebind vector %x/%x",
908 vecp->v_cpuid, vecp->v_vector);
909 }
910 }
911
912 lock_clear(&apix_lock);
913
914 if (hardbound || errbound) {
915 cmn_err(CE_WARN, "Could not disable interrupts on %d"
916 "due to user bound interrupts or failed operation",
917 cpun);
918 return (PSM_FAILURE);
919 }
920
921 return (PSM_SUCCESS);
922 }
923
924 /*
925 * Bind interrupts to specified CPU
926 */
927 static void
928 apix_enable_intr(processorid_t cpun)
929 {
930 apix_vector_t *vecp;
931 int i, ret;
932 processorid_t n;
933
934 lock_set(&apix_lock);
935
936 apic_cpus[cpun].aci_status |= APIC_CPU_INTR_ENABLE;
937
938 /* interrupt enabling for system resume */
939 if (apic_cpus[cpun].aci_status & APIC_CPU_SUSPEND) {
940 for (i = APIX_AVINTR_MIN; i <= APIX_AVINTR_MAX; i++) {
941 vecp = xv_vector(cpun, i);
942 if (!IS_VECT_ENABLED(vecp))
943 continue;
944
945 apix_enable_vector(vecp);
946 }
947 apic_cpus[cpun].aci_status &= ~APIC_CPU_SUSPEND;
948 }
949
950 for (n = 0; n < apic_nproc; n++) {
951 if (!apic_cpu_in_range(n) || n == cpun ||
952 (apic_cpus[n].aci_status & APIC_CPU_INTR_ENABLE) == 0)
953 continue;
954
955 for (i = APIX_AVINTR_MIN; i <= APIX_AVINTR_MAX; i++) {
956 vecp = xv_vector(n, i);
957 if (!IS_VECT_ENABLED(vecp) ||
958 vecp->v_bound_cpuid != cpun)
959 continue;
960
961 if (vecp->v_type != APIX_TYPE_MSI)
962 (void) apix_set_cpu(vecp, cpun, &ret);
963 else
964 (void) apix_grp_set_cpu(vecp, cpun, &ret);
965 }
966 }
967
968 lock_clear(&apix_lock);
969 }
970
971 /*
972 * Allocate vector for IPI
973 * type == -1 indicates it is an internal request. Do not change
974 * resv_vector for these requests.
975 */
976 static int
977 apix_get_ipivect(int ipl, int type)
978 {
979 uchar_t vector;
980
981 if ((vector = apix_alloc_ipi(ipl)) > 0) {
982 if (type != -1)
983 apic_resv_vector[ipl] = vector;
984 return (vector);
985 }
986 apic_error |= APIC_ERR_GET_IPIVECT_FAIL;
987 return (-1); /* shouldn't happen */
988 }
989
990 static int
991 apix_get_clkvect(int ipl)
992 {
993 int vector;
994
995 if ((vector = apix_get_ipivect(ipl, -1)) == -1)
996 return (-1);
997
998 apic_clkvect = vector - APIC_BASE_VECT;
999 APIC_VERBOSE(IPI, (CE_CONT, "apix: clock vector = %x\n",
1000 apic_clkvect));
1001 return (vector);
1002 }
1003
1004 static int
1005 apix_post_cpu_start()
1006 {
1007 int cpun;
1008 static int cpus_started = 1;
1009
1010 /* We know this CPU + BSP started successfully. */
1011 cpus_started++;
1012
1013 /*
1014 * On BSP we would have enabled X2APIC, if supported by processor,
1015 * in acpi_probe(), but on AP we do it here.
1016 *
1017 * We enable X2APIC mode only if BSP is running in X2APIC & the
1018 * local APIC mode of the current CPU is MMIO (xAPIC).
1019 */
1020 if (apic_mode == LOCAL_X2APIC && apic_detect_x2apic() &&
1021 apic_local_mode() == LOCAL_APIC) {
1022 apic_enable_x2apic();
1023 }
1024
1025 /*
1026 * Switch back to x2apic IPI sending method for performance when target
1027 * CPU has entered x2apic mode.
1028 */
1029 if (apic_mode == LOCAL_X2APIC) {
1030 apic_switch_ipi_callback(B_FALSE);
1031 }
1032
1033 splx(ipltospl(LOCK_LEVEL));
1034 apix_init_intr();
1035
1036 /*
1037 * since some systems don't enable the internal cache on the non-boot
1038 * cpus, so we have to enable them here
1039 */
1040 setcr0(getcr0() & ~(CR0_CD | CR0_NW));
1041
1042 #ifdef DEBUG
1043 APIC_AV_PENDING_SET();
1044 #else
1045 if (apic_mode == LOCAL_APIC)
1046 APIC_AV_PENDING_SET();
1047 #endif /* DEBUG */
1048
1049 /*
1050 * We may be booting, or resuming from suspend; aci_status will
1051 * be APIC_CPU_INTR_ENABLE if coming from suspend, so we add the
1052 * APIC_CPU_ONLINE flag here rather than setting aci_status completely.
1053 */
1054 cpun = psm_get_cpu_id();
1055 apic_cpus[cpun].aci_status |= APIC_CPU_ONLINE;
1056
1057 apic_reg_ops->apic_write(APIC_DIVIDE_REG, apic_divide_reg_init);
1058
1059 return (PSM_SUCCESS);
1060 }
1061
1062 /*
1063 * If this module needs a periodic handler for the interrupt distribution, it
1064 * can be added here. The argument to the periodic handler is not currently
1065 * used, but is reserved for future.
1066 */
1067 static void
1068 apix_post_cyclic_setup(void *arg)
1069 {
1070 UNREFERENCED_1PARAMETER(arg);
1071
1072 cyc_handler_t cyh;
1073 cyc_time_t cyt;
1074
1075 /* cpu_lock is held */
1076 /* set up a periodic handler for intr redistribution */
1077
1078 /*
1079 * In peridoc mode intr redistribution processing is done in
1080 * apic_intr_enter during clk intr processing
1081 */
1082 if (!apic_oneshot)
1083 return;
1084
1085 /*
1086 * Register a periodical handler for the redistribution processing.
1087 * Though we would generally prefer to use the DDI interface for
1088 * periodic handler invocation, ddi_periodic_add(9F), we are
1089 * unfortunately already holding cpu_lock, which ddi_periodic_add will
1090 * attempt to take for us. Thus, we add our own cyclic directly:
1091 */
1092 cyh.cyh_func = (void (*)(void *))apix_redistribute_compute;
1093 cyh.cyh_arg = NULL;
1094 cyh.cyh_level = CY_LOW_LEVEL;
1095
1096 cyt.cyt_when = 0;
1097 cyt.cyt_interval = apic_redistribute_sample_interval;
1098
1099 apic_cyclic_id = cyclic_add(&cyh, &cyt);
1100 }
1101
1102 /*
1103 * Called the first time we enable x2apic mode on this cpu.
1104 * Update some of the function pointers to use x2apic routines.
1105 */
1106 void
1107 x2apic_update_psm()
1108 {
1109 struct psm_ops *pops = &apix_ops;
1110
1111 ASSERT(pops != NULL);
1112
1113 /*
1114 * The pcplusmp module's version of x2apic_update_psm makes additional
1115 * changes that we do not have to make here. It needs to make those
1116 * changes because pcplusmp relies on the TPR register and the means of
1117 * addressing that changes when using the local apic versus the x2apic.
1118 * It's also worth noting that the apix driver specific function end up
1119 * being apix_foo as opposed to apic_foo and x2apic_foo.
1120 */
1121 pops->psm_send_ipi = x2apic_send_ipi;
1122
1123 send_dirintf = pops->psm_send_ipi;
1124
1125 apic_mode = LOCAL_X2APIC;
1126 apic_change_ops();
1127 }
1128
1129 /*
1130 * This function provides external interface to the nexus for all
1131 * functionalities related to the new DDI interrupt framework.
1132 *
1133 * Input:
1134 * dip - pointer to the dev_info structure of the requested device
1135 * hdlp - pointer to the internal interrupt handle structure for the
1136 * requested interrupt
1137 * intr_op - opcode for this call
1138 * result - pointer to the integer that will hold the result to be
1139 * passed back if return value is PSM_SUCCESS
1140 *
1141 * Output:
1142 * return value is either PSM_SUCCESS or PSM_FAILURE
1143 */
1144 static int
1145 apix_intr_ops(dev_info_t *dip, ddi_intr_handle_impl_t *hdlp,
1146 psm_intr_op_t intr_op, int *result)
1147 {
1148 int cap;
1149 apix_vector_t *vecp, *newvecp;
1150 struct intrspec *ispec, intr_spec;
1151 processorid_t target;
1152
1153 ispec = &intr_spec;
1154 ispec->intrspec_pri = hdlp->ih_pri;
1155 ispec->intrspec_vec = hdlp->ih_inum;
1156 ispec->intrspec_func = hdlp->ih_cb_func;
1157
1158 switch (intr_op) {
1159 case PSM_INTR_OP_ALLOC_VECTORS:
1160 switch (hdlp->ih_type) {
1161 case DDI_INTR_TYPE_MSI:
1162 /* allocate MSI vectors */
1163 *result = apix_alloc_msi(dip, hdlp->ih_inum,
1164 hdlp->ih_scratch1,
1165 (int)(uintptr_t)hdlp->ih_scratch2);
1166 break;
1167 case DDI_INTR_TYPE_MSIX:
1168 /* allocate MSI-X vectors */
1169 *result = apix_alloc_msix(dip, hdlp->ih_inum,
1170 hdlp->ih_scratch1,
1171 (int)(uintptr_t)hdlp->ih_scratch2);
1172 break;
1173 case DDI_INTR_TYPE_FIXED:
1174 /* allocate or share vector for fixed */
1175 if ((ihdl_plat_t *)hdlp->ih_private == NULL) {
1176 return (PSM_FAILURE);
1177 }
1178 ispec = ((ihdl_plat_t *)hdlp->ih_private)->ip_ispecp;
1179 *result = apix_intx_alloc_vector(dip, hdlp, ispec);
1180 break;
1181 default:
1182 return (PSM_FAILURE);
1183 }
1184 break;
1185 case PSM_INTR_OP_FREE_VECTORS:
1186 apix_free_vectors(dip, hdlp->ih_inum, hdlp->ih_scratch1,
1187 hdlp->ih_type);
1188 break;
1189 case PSM_INTR_OP_XLATE_VECTOR:
1190 /*
1191 * Vectors are allocated by ALLOC and freed by FREE.
1192 * XLATE finds and returns APIX_VIRTVEC_VECTOR(cpu, vector).
1193 */
1194 *result = APIX_INVALID_VECT;
1195 vecp = apix_get_dev_map(dip, hdlp->ih_inum, hdlp->ih_type);
1196 if (vecp != NULL) {
1197 *result = APIX_VIRTVECTOR(vecp->v_cpuid,
1198 vecp->v_vector);
1199 break;
1200 }
1201
1202 /*
1203 * No vector to device mapping exists. If this is FIXED type
1204 * then check if this IRQ is already mapped for another device
1205 * then return the vector number for it (i.e. shared IRQ case).
1206 * Otherwise, return PSM_FAILURE.
1207 */
1208 if (hdlp->ih_type == DDI_INTR_TYPE_FIXED) {
1209 vecp = apix_intx_xlate_vector(dip, hdlp->ih_inum,
1210 ispec);
1211 *result = (vecp == NULL) ? APIX_INVALID_VECT :
1212 APIX_VIRTVECTOR(vecp->v_cpuid, vecp->v_vector);
1213 }
1214 if (*result == APIX_INVALID_VECT)
1215 return (PSM_FAILURE);
1216 break;
1217 case PSM_INTR_OP_GET_PENDING:
1218 vecp = apix_get_dev_map(dip, hdlp->ih_inum, hdlp->ih_type);
1219 if (vecp == NULL)
1220 return (PSM_FAILURE);
1221
1222 *result = apix_get_pending(vecp);
1223 break;
1224 case PSM_INTR_OP_CLEAR_MASK:
1225 if (hdlp->ih_type != DDI_INTR_TYPE_FIXED)
1226 return (PSM_FAILURE);
1227
1228 vecp = apix_get_dev_map(dip, hdlp->ih_inum, hdlp->ih_type);
1229 if (vecp == NULL)
1230 return (PSM_FAILURE);
1231
1232 apix_intx_clear_mask(vecp->v_inum);
1233 break;
1234 case PSM_INTR_OP_SET_MASK:
1235 if (hdlp->ih_type != DDI_INTR_TYPE_FIXED)
1236 return (PSM_FAILURE);
1237
1238 vecp = apix_get_dev_map(dip, hdlp->ih_inum, hdlp->ih_type);
1239 if (vecp == NULL)
1240 return (PSM_FAILURE);
1241
1242 apix_intx_set_mask(vecp->v_inum);
1243 break;
1244 case PSM_INTR_OP_GET_SHARED:
1245 if (hdlp->ih_type != DDI_INTR_TYPE_FIXED)
1246 return (PSM_FAILURE);
1247
1248 vecp = apix_get_dev_map(dip, hdlp->ih_inum, hdlp->ih_type);
1249 if (vecp == NULL)
1250 return (PSM_FAILURE);
1251
1252 *result = apix_intx_get_shared(vecp->v_inum);
1253 break;
1254 case PSM_INTR_OP_SET_PRI:
1255 /*
1256 * Called prior to adding the interrupt handler or when
1257 * an interrupt handler is unassigned.
1258 */
1259 if (hdlp->ih_type == DDI_INTR_TYPE_FIXED)
1260 return (PSM_SUCCESS);
1261
1262 if (apix_get_dev_map(dip, hdlp->ih_inum, hdlp->ih_type) == NULL)
1263 return (PSM_FAILURE);
1264
1265 break;
1266 case PSM_INTR_OP_SET_CPU:
1267 case PSM_INTR_OP_GRP_SET_CPU:
1268 /*
1269 * The interrupt handle given here has been allocated
1270 * specifically for this command, and ih_private carries
1271 * a CPU value.
1272 */
1273 *result = EINVAL;
1274 target = (int)(intptr_t)hdlp->ih_private;
1275 if (!apic_cpu_in_range(target)) {
1276 DDI_INTR_IMPLDBG((CE_WARN,
1277 "[grp_]set_cpu: cpu out of range: %d\n", target));
1278 return (PSM_FAILURE);
1279 }
1280
1281 lock_set(&apix_lock);
1282
1283 vecp = apix_get_req_vector(hdlp, hdlp->ih_flags);
1284 if (!IS_VECT_ENABLED(vecp)) {
1285 DDI_INTR_IMPLDBG((CE_WARN,
1286 "[grp]_set_cpu: invalid vector 0x%x\n",
1287 hdlp->ih_vector));
1288 lock_clear(&apix_lock);
1289 return (PSM_FAILURE);
1290 }
1291
1292 *result = 0;
1293
1294 if (intr_op == PSM_INTR_OP_SET_CPU)
1295 newvecp = apix_set_cpu(vecp, target, result);
1296 else
1297 newvecp = apix_grp_set_cpu(vecp, target, result);
1298
1299 lock_clear(&apix_lock);
1300
1301 if (newvecp == NULL) {
1302 *result = EIO;
1303 return (PSM_FAILURE);
1304 }
1305 newvecp->v_bound_cpuid = target;
1306 hdlp->ih_vector = APIX_VIRTVECTOR(newvecp->v_cpuid,
1307 newvecp->v_vector);
1308 break;
1309
1310 case PSM_INTR_OP_GET_INTR:
1311 /*
1312 * The interrupt handle given here has been allocated
1313 * specifically for this command, and ih_private carries
1314 * a pointer to a apic_get_intr_t.
1315 */
1316 if (apix_get_intr_info(hdlp, hdlp->ih_private) != PSM_SUCCESS)
1317 return (PSM_FAILURE);
1318 break;
1319
1320 case PSM_INTR_OP_CHECK_MSI:
1321 /*
1322 * Check MSI/X is supported or not at APIC level and
1323 * masked off the MSI/X bits in hdlp->ih_type if not
1324 * supported before return. If MSI/X is supported,
1325 * leave the ih_type unchanged and return.
1326 *
1327 * hdlp->ih_type passed in from the nexus has all the
1328 * interrupt types supported by the device.
1329 */
1330 if (apic_support_msi == 0) { /* uninitialized */
1331 /*
1332 * if apic_support_msi is not set, call
1333 * apic_check_msi_support() to check whether msi
1334 * is supported first
1335 */
1336 if (apic_check_msi_support() == PSM_SUCCESS)
1337 apic_support_msi = 1; /* supported */
1338 else
1339 apic_support_msi = -1; /* not-supported */
1340 }
1341 if (apic_support_msi == 1) {
1342 if (apic_msix_enable)
1343 *result = hdlp->ih_type;
1344 else
1345 *result = hdlp->ih_type & ~DDI_INTR_TYPE_MSIX;
1346 } else
1347 *result = hdlp->ih_type & ~(DDI_INTR_TYPE_MSI |
1348 DDI_INTR_TYPE_MSIX);
1349 break;
1350 case PSM_INTR_OP_GET_CAP:
1351 cap = DDI_INTR_FLAG_PENDING;
1352 if (hdlp->ih_type == DDI_INTR_TYPE_FIXED)
1353 cap |= DDI_INTR_FLAG_MASKABLE;
1354 *result = cap;
1355 break;
1356 case PSM_INTR_OP_APIC_TYPE:
1357 ((apic_get_type_t *)(hdlp->ih_private))->avgi_type =
1358 apix_get_apic_type();
1359 ((apic_get_type_t *)(hdlp->ih_private))->avgi_num_intr =
1360 APIX_IPI_MIN;
1361 ((apic_get_type_t *)(hdlp->ih_private))->avgi_num_cpu =
1362 apic_nproc;
1363 hdlp->ih_ver = apic_get_apic_version();
1364 break;
1365 case PSM_INTR_OP_SET_CAP:
1366 default:
1367 return (PSM_FAILURE);
1368 }
1369
1370 return (PSM_SUCCESS);
1371 }
1372
1373 static void
1374 apix_cleanup_busy(void)
1375 {
1376 int i, j;
1377 apix_vector_t *vecp;
1378
1379 for (i = 0; i < apic_nproc; i++) {
1380 if (!apic_cpu_in_range(i))
1381 continue;
1382 apic_cpus[i].aci_busy = 0;
1383 for (j = APIX_AVINTR_MIN; j < APIX_AVINTR_MAX; j++) {
1384 if ((vecp = xv_vector(i, j)) != NULL)
1385 vecp->v_busy = 0;
1386 }
1387 }
1388 }
1389
1390 static void
1391 apix_redistribute_compute(void)
1392 {
1393 int i, j, max_busy;
1394
1395 if (!apic_enable_dynamic_migration)
1396 return;
1397
1398 if (++apic_nticks == apic_sample_factor_redistribution) {
1399 /*
1400 * Time to call apic_intr_redistribute().
1401 * reset apic_nticks. This will cause max_busy
1402 * to be calculated below and if it is more than
1403 * apic_int_busy, we will do the whole thing
1404 */
1405 apic_nticks = 0;
1406 }
1407 max_busy = 0;
1408 for (i = 0; i < apic_nproc; i++) {
1409 if (!apic_cpu_in_range(i))
1410 continue;
1411 /*
1412 * Check if curipl is non zero & if ISR is in
1413 * progress
1414 */
1415 if (((j = apic_cpus[i].aci_curipl) != 0) &&
1416 (apic_cpus[i].aci_ISR_in_progress & (1 << j))) {
1417
1418 int vect;
1419 apic_cpus[i].aci_busy++;
1420 vect = apic_cpus[i].aci_current[j];
1421 apixs[i]->x_vectbl[vect]->v_busy++;
1422 }
1423
1424 if (!apic_nticks &&
1425 (apic_cpus[i].aci_busy > max_busy))
1426 max_busy = apic_cpus[i].aci_busy;
1427 }
1428 if (!apic_nticks) {
1429 if (max_busy > apic_int_busy_mark) {
1430 /*
1431 * We could make the following check be
1432 * skipped > 1 in which case, we get a
1433 * redistribution at half the busy mark (due to
1434 * double interval). Need to be able to collect
1435 * more empirical data to decide if that is a
1436 * good strategy. Punt for now.
1437 */
1438 apix_cleanup_busy();
1439 apic_skipped_redistribute = 0;
1440 } else
1441 apic_skipped_redistribute++;
1442 }
1443 }
1444
1445 /*
1446 * intr_ops() service routines
1447 */
1448
1449 static int
1450 apix_get_pending(apix_vector_t *vecp)
1451 {
1452 int bit, index, irr, pending;
1453
1454 /* need to get on the bound cpu */
1455 mutex_enter(&cpu_lock);
1456 affinity_set(vecp->v_cpuid);
1457
1458 index = vecp->v_vector / 32;
1459 bit = vecp->v_vector % 32;
1460 irr = apic_reg_ops->apic_read(APIC_IRR_REG + index);
1461
1462 affinity_clear();
1463 mutex_exit(&cpu_lock);
1464
1465 pending = (irr & (1 << bit)) ? 1 : 0;
1466 if (!pending && vecp->v_type == APIX_TYPE_FIXED)
1467 pending = apix_intx_get_pending(vecp->v_inum);
1468
1469 return (pending);
1470 }
1471
1472 static apix_vector_t *
1473 apix_get_req_vector(ddi_intr_handle_impl_t *hdlp, ushort_t flags)
1474 {
1475 apix_vector_t *vecp;
1476 processorid_t cpuid;
1477 int32_t virt_vec = 0;
1478
1479 switch (flags & PSMGI_INTRBY_FLAGS) {
1480 case PSMGI_INTRBY_IRQ:
1481 return (apix_intx_get_vector(hdlp->ih_vector));
1482 case PSMGI_INTRBY_VEC:
1483 virt_vec = (virt_vec == 0) ? hdlp->ih_vector : virt_vec;
1484
1485 cpuid = APIX_VIRTVEC_CPU(virt_vec);
1486 if (!apic_cpu_in_range(cpuid))
1487 return (NULL);
1488
1489 vecp = xv_vector(cpuid, APIX_VIRTVEC_VECTOR(virt_vec));
1490 break;
1491 case PSMGI_INTRBY_DEFAULT:
1492 vecp = apix_get_dev_map(hdlp->ih_dip, hdlp->ih_inum,
1493 hdlp->ih_type);
1494 break;
1495 default:
1496 return (NULL);
1497 }
1498
1499 return (vecp);
1500 }
1501
1502 static int
1503 apix_get_intr_info(ddi_intr_handle_impl_t *hdlp,
1504 apic_get_intr_t *intr_params_p)
1505 {
1506 apix_vector_t *vecp;
1507 struct autovec *av_dev;
1508 int i;
1509
1510 vecp = apix_get_req_vector(hdlp, intr_params_p->avgi_req_flags);
1511 if (IS_VECT_FREE(vecp)) {
1512 intr_params_p->avgi_num_devs = 0;
1513 intr_params_p->avgi_cpu_id = 0;
1514 intr_params_p->avgi_req_flags = 0;
1515 return (PSM_SUCCESS);
1516 }
1517
1518 if (intr_params_p->avgi_req_flags & PSMGI_REQ_CPUID) {
1519 intr_params_p->avgi_cpu_id = vecp->v_cpuid;
1520
1521 /* Return user bound info for intrd. */
1522 if (intr_params_p->avgi_cpu_id & IRQ_USER_BOUND) {
1523 intr_params_p->avgi_cpu_id &= ~IRQ_USER_BOUND;
1524 intr_params_p->avgi_cpu_id |= PSMGI_CPU_USER_BOUND;
1525 }
1526 }
1527
1528 if (intr_params_p->avgi_req_flags & PSMGI_REQ_VECTOR)
1529 intr_params_p->avgi_vector = vecp->v_vector;
1530
1531 if (intr_params_p->avgi_req_flags &
1532 (PSMGI_REQ_NUM_DEVS | PSMGI_REQ_GET_DEVS))
1533 /* Get number of devices from apic_irq table shared field. */
1534 intr_params_p->avgi_num_devs = vecp->v_share;
1535
1536 if (intr_params_p->avgi_req_flags & PSMGI_REQ_GET_DEVS) {
1537
1538 intr_params_p->avgi_req_flags |= PSMGI_REQ_NUM_DEVS;
1539
1540 /* Some devices have NULL dip. Don't count these. */
1541 if (intr_params_p->avgi_num_devs > 0) {
1542 for (i = 0, av_dev = vecp->v_autovect; av_dev;
1543 av_dev = av_dev->av_link) {
1544 if (av_dev->av_vector && av_dev->av_dip)
1545 i++;
1546 }
1547 intr_params_p->avgi_num_devs =
1548 (uint8_t)MIN(intr_params_p->avgi_num_devs, i);
1549 }
1550
1551 /* There are no viable dips to return. */
1552 if (intr_params_p->avgi_num_devs == 0) {
1553 intr_params_p->avgi_dip_list = NULL;
1554
1555 } else { /* Return list of dips */
1556
1557 /* Allocate space in array for that number of devs. */
1558 intr_params_p->avgi_dip_list = kmem_zalloc(
1559 intr_params_p->avgi_num_devs *
1560 sizeof (dev_info_t *),
1561 KM_NOSLEEP);
1562 if (intr_params_p->avgi_dip_list == NULL) {
1563 DDI_INTR_IMPLDBG((CE_WARN,
1564 "apix_get_vector_intr_info: no memory"));
1565 return (PSM_FAILURE);
1566 }
1567
1568 /*
1569 * Loop through the device list of the autovec table
1570 * filling in the dip array.
1571 *
1572 * Note that the autovect table may have some special
1573 * entries which contain NULL dips. These will be
1574 * ignored.
1575 */
1576 for (i = 0, av_dev = vecp->v_autovect; av_dev;
1577 av_dev = av_dev->av_link) {
1578 if (av_dev->av_vector && av_dev->av_dip)
1579 intr_params_p->avgi_dip_list[i++] =
1580 av_dev->av_dip;
1581 }
1582 }
1583 }
1584
1585 return (PSM_SUCCESS);
1586 }
1587
1588 static char *
1589 apix_get_apic_type(void)
1590 {
1591 return (apix_psm_info.p_mach_idstring);
1592 }
1593
1594 apix_vector_t *
1595 apix_set_cpu(apix_vector_t *vecp, int new_cpu, int *result)
1596 {
1597 apix_vector_t *newp = NULL;
1598 dev_info_t *dip;
1599 int inum, cap_ptr;
1600 ddi_acc_handle_t handle;
1601 ddi_intr_msix_t *msix_p = NULL;
1602 ushort_t msix_ctrl;
1603 uintptr_t off = 0;
1604 uint32_t mask = 0;
1605
1606 ASSERT(LOCK_HELD(&apix_lock));
1607 *result = ENXIO;
1608
1609 /* Fail if this is an MSI intr and is part of a group. */
1610 if (vecp->v_type == APIX_TYPE_MSI) {
1611 if (i_ddi_intr_get_current_nintrs(APIX_GET_DIP(vecp)) > 1)
1612 return (NULL);
1613 else
1614 return (apix_grp_set_cpu(vecp, new_cpu, result));
1615 }
1616
1617 /*
1618 * Mask MSI-X. It's unmasked when MSI-X gets enabled.
1619 */
1620 if (vecp->v_type == APIX_TYPE_MSIX && IS_VECT_ENABLED(vecp)) {
1621 if ((dip = APIX_GET_DIP(vecp)) == NULL)
1622 return (NULL);
1623 inum = vecp->v_devp->dv_inum;
1624
1625 handle = i_ddi_get_pci_config_handle(dip);
1626 cap_ptr = i_ddi_get_msi_msix_cap_ptr(dip);
1627 msix_ctrl = pci_config_get16(handle, cap_ptr + PCI_MSIX_CTRL);
1628 if ((msix_ctrl & PCI_MSIX_FUNCTION_MASK) == 0) {
1629 /*
1630 * Function is not masked, then mask "inum"th
1631 * entry in the MSI-X table
1632 */
1633 msix_p = i_ddi_get_msix(dip);
1634 off = (uintptr_t)msix_p->msix_tbl_addr + (inum *
1635 PCI_MSIX_VECTOR_SIZE) + PCI_MSIX_VECTOR_CTRL_OFFSET;
1636 mask = ddi_get32(msix_p->msix_tbl_hdl, (uint32_t *)off);
1637 ddi_put32(msix_p->msix_tbl_hdl, (uint32_t *)off,
1638 mask | 1);
1639 }
1640 }
1641
1642 *result = 0;
1643 if ((newp = apix_rebind(vecp, new_cpu, 1)) == NULL)
1644 *result = EIO;
1645
1646 /* Restore mask bit */
1647 if (msix_p != NULL)
1648 ddi_put32(msix_p->msix_tbl_hdl, (uint32_t *)off, mask);
1649
1650 return (newp);
1651 }
1652
1653 /*
1654 * Set cpu for MSIs
1655 */
1656 apix_vector_t *
1657 apix_grp_set_cpu(apix_vector_t *vecp, int new_cpu, int *result)
1658 {
1659 apix_vector_t *newp, *vp;
1660 uint32_t orig_cpu = vecp->v_cpuid;
1661 int orig_vect = vecp->v_vector;
1662 int i, num_vectors, cap_ptr, msi_mask_off = 0;
1663 uint32_t msi_pvm = 0;
1664 ushort_t msi_ctrl;
1665 ddi_acc_handle_t handle;
1666 dev_info_t *dip;
1667
1668 APIC_VERBOSE(INTR, (CE_CONT, "apix_grp_set_cpu: oldcpu: %x, vector: %x,"
1669 " newcpu:%x\n", vecp->v_cpuid, vecp->v_vector, new_cpu));
1670
1671 ASSERT(LOCK_HELD(&apix_lock));
1672
1673 *result = ENXIO;
1674
1675 if (vecp->v_type != APIX_TYPE_MSI) {
1676 DDI_INTR_IMPLDBG((CE_WARN, "set_grp: intr not MSI\n"));
1677 return (NULL);
1678 }
1679
1680 if ((dip = APIX_GET_DIP(vecp)) == NULL)
1681 return (NULL);
1682
1683 num_vectors = i_ddi_intr_get_current_nintrs(dip);
1684 if ((num_vectors < 1) || ((num_vectors - 1) & orig_vect)) {
1685 APIC_VERBOSE(INTR, (CE_WARN,
1686 "set_grp: base vec not part of a grp or not aligned: "
1687 "vec:0x%x, num_vec:0x%x\n", orig_vect, num_vectors));
1688 return (NULL);
1689 }
1690
1691 if (vecp->v_inum != apix_get_min_dev_inum(dip, vecp->v_type))
1692 return (NULL);
1693
1694 *result = EIO;
1695 for (i = 1; i < num_vectors; i++) {
1696 if ((vp = xv_vector(orig_cpu, orig_vect + i)) == NULL)
1697 return (NULL);
1698 #ifdef DEBUG
1699 /*
1700 * Sanity check: CPU and dip is the same for all entries.
1701 * May be called when first msi to be enabled, at this time
1702 * add_avintr() is not called for other msi
1703 */
1704 if ((vp->v_share != 0) &&
1705 ((APIX_GET_DIP(vp) != dip) ||
1706 (vp->v_cpuid != vecp->v_cpuid))) {
1707 APIC_VERBOSE(INTR, (CE_WARN,
1708 "set_grp: cpu or dip for vec 0x%x difft than for "
1709 "vec 0x%x\n", orig_vect, orig_vect + i));
1710 APIC_VERBOSE(INTR, (CE_WARN,
1711 " cpu: %d vs %d, dip: 0x%p vs 0x%p\n", orig_cpu,
1712 vp->v_cpuid, (void *)dip,
1713 (void *)APIX_GET_DIP(vp)));
1714 return (NULL);
1715 }
1716 #endif /* DEBUG */
1717 }
1718
1719 cap_ptr = i_ddi_get_msi_msix_cap_ptr(dip);
1720 handle = i_ddi_get_pci_config_handle(dip);
1721 msi_ctrl = pci_config_get16(handle, cap_ptr + PCI_MSI_CTRL);
1722
1723 /* MSI Per vector masking is supported. */
1724 if (msi_ctrl & PCI_MSI_PVM_MASK) {
1725 if (msi_ctrl & PCI_MSI_64BIT_MASK)
1726 msi_mask_off = cap_ptr + PCI_MSI_64BIT_MASKBITS;
1727 else
1728 msi_mask_off = cap_ptr + PCI_MSI_32BIT_MASK;
1729 msi_pvm = pci_config_get32(handle, msi_mask_off);
1730 pci_config_put32(handle, msi_mask_off, (uint32_t)-1);
1731 APIC_VERBOSE(INTR, (CE_CONT,
1732 "set_grp: pvm supported. Mask set to 0x%x\n",
1733 pci_config_get32(handle, msi_mask_off)));
1734 }
1735
1736 if ((newp = apix_rebind(vecp, new_cpu, num_vectors)) != NULL)
1737 *result = 0;
1738
1739 /* Reenable vectors if per vector masking is supported. */
1740 if (msi_ctrl & PCI_MSI_PVM_MASK) {
1741 pci_config_put32(handle, msi_mask_off, msi_pvm);
1742 APIC_VERBOSE(INTR, (CE_CONT,
1743 "set_grp: pvm supported. Mask restored to 0x%x\n",
1744 pci_config_get32(handle, msi_mask_off)));
1745 }
1746
1747 return (newp);
1748 }
1749
1750 void
1751 apix_intx_set_vector(int irqno, uint32_t cpuid, uchar_t vector)
1752 {
1753 apic_irq_t *irqp;
1754
1755 mutex_enter(&airq_mutex);
1756 irqp = apic_irq_table[irqno];
1757 irqp->airq_cpu = cpuid;
1758 irqp->airq_vector = vector;
1759 apic_record_rdt_entry(irqp, irqno);
1760 mutex_exit(&airq_mutex);
1761 }
1762
1763 apix_vector_t *
1764 apix_intx_get_vector(int irqno)
1765 {
1766 apic_irq_t *irqp;
1767 uint32_t cpuid;
1768 uchar_t vector;
1769
1770 mutex_enter(&airq_mutex);
1771 irqp = apic_irq_table[irqno & 0xff];
1772 if (IS_IRQ_FREE(irqp) || (irqp->airq_cpu == IRQ_UNINIT)) {
1773 mutex_exit(&airq_mutex);
1774 return (NULL);
1775 }
1776 cpuid = irqp->airq_cpu;
1777 vector = irqp->airq_vector;
1778 mutex_exit(&airq_mutex);
1779
1780 return (xv_vector(cpuid, vector));
1781 }
1782
1783 /*
1784 * Must called with interrupts disabled and apic_ioapic_lock held
1785 */
1786 void
1787 apix_intx_enable(int irqno)
1788 {
1789 uchar_t ioapicindex, intin;
1790 apic_irq_t *irqp = apic_irq_table[irqno];
1791 ioapic_rdt_t irdt;
1792 apic_cpus_info_t *cpu_infop;
1793 apix_vector_t *vecp = xv_vector(irqp->airq_cpu, irqp->airq_vector);
1794
1795 ASSERT(LOCK_HELD(&apic_ioapic_lock) && !IS_IRQ_FREE(irqp));
1796
1797 ioapicindex = irqp->airq_ioapicindex;
1798 intin = irqp->airq_intin_no;
1799 cpu_infop = &apic_cpus[irqp->airq_cpu];
1800
1801 irdt.ir_lo = AV_PDEST | AV_FIXED | irqp->airq_rdt_entry;
1802 irdt.ir_hi = cpu_infop->aci_local_id;
1803
1804 apic_vt_ops->apic_intrmap_alloc_entry(&vecp->v_intrmap_private, NULL,
1805 vecp->v_type, 1, ioapicindex);
1806 apic_vt_ops->apic_intrmap_map_entry(vecp->v_intrmap_private,
1807 (void *)&irdt, vecp->v_type, 1);
1808 apic_vt_ops->apic_intrmap_record_rdt(vecp->v_intrmap_private, &irdt);
1809
1810 /* write RDT entry high dword - destination */
1811 WRITE_IOAPIC_RDT_ENTRY_HIGH_DWORD(ioapicindex, intin,
1812 irdt.ir_hi);
1813
1814 /* Write the vector, trigger, and polarity portion of the RDT */
1815 WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapicindex, intin, irdt.ir_lo);
1816
1817 vecp->v_state = APIX_STATE_ENABLED;
1818
1819 APIC_VERBOSE_IOAPIC((CE_CONT, "apix_intx_enable: ioapic 0x%x"
1820 " intin 0x%x rdt_low 0x%x rdt_high 0x%x\n",
1821 ioapicindex, intin, irdt.ir_lo, irdt.ir_hi));
1822 }
1823
1824 /*
1825 * Must called with interrupts disabled and apic_ioapic_lock held
1826 */
1827 void
1828 apix_intx_disable(int irqno)
1829 {
1830 apic_irq_t *irqp = apic_irq_table[irqno];
1831 int ioapicindex, intin;
1832
1833 ASSERT(LOCK_HELD(&apic_ioapic_lock) && !IS_IRQ_FREE(irqp));
1834 /*
1835 * The assumption here is that this is safe, even for
1836 * systems with IOAPICs that suffer from the hardware
1837 * erratum because all devices have been quiesced before
1838 * they unregister their interrupt handlers. If that
1839 * assumption turns out to be false, this mask operation
1840 * can induce the same erratum result we're trying to
1841 * avoid.
1842 */
1843 ioapicindex = irqp->airq_ioapicindex;
1844 intin = irqp->airq_intin_no;
1845 ioapic_write(ioapicindex, APIC_RDT_CMD + 2 * intin, AV_MASK);
1846
1847 APIC_VERBOSE_IOAPIC((CE_CONT, "apix_intx_disable: ioapic 0x%x"
1848 " intin 0x%x\n", ioapicindex, intin));
1849 }
1850
1851 void
1852 apix_intx_free(int irqno)
1853 {
1854 apic_irq_t *irqp;
1855
1856 mutex_enter(&airq_mutex);
1857 irqp = apic_irq_table[irqno];
1858
1859 if (IS_IRQ_FREE(irqp)) {
1860 mutex_exit(&airq_mutex);
1861 return;
1862 }
1863
1864 irqp->airq_mps_intr_index = FREE_INDEX;
1865 irqp->airq_cpu = IRQ_UNINIT;
1866 irqp->airq_vector = APIX_INVALID_VECT;
1867 mutex_exit(&airq_mutex);
1868 }
1869
1870 #ifdef DEBUG
1871 int apix_intr_deliver_timeouts = 0;
1872 int apix_intr_rirr_timeouts = 0;
1873 int apix_intr_rirr_reset_failure = 0;
1874 #endif
1875 int apix_max_reps_irr_pending = 10;
1876
1877 #define GET_RDT_BITS(ioapic, intin, bits) \
1878 (READ_IOAPIC_RDT_ENTRY_LOW_DWORD((ioapic), (intin)) & (bits))
1879 #define APIX_CHECK_IRR_DELAY drv_usectohz(5000)
1880
1881 int
1882 apix_intx_rebind(int irqno, processorid_t cpuid, uchar_t vector)
1883 {
1884 apic_irq_t *irqp = apic_irq_table[irqno];
1885 ulong_t iflag;
1886 int waited, ioapic_ix, intin_no, level, repeats, rdt_entry, masked;
1887
1888 ASSERT(irqp != NULL);
1889
1890 iflag = intr_clear();
1891 lock_set(&apic_ioapic_lock);
1892
1893 ioapic_ix = irqp->airq_ioapicindex;
1894 intin_no = irqp->airq_intin_no;
1895 level = apic_level_intr[irqno];
1896
1897 /*
1898 * Wait for the delivery status bit to be cleared. This should
1899 * be a very small amount of time.
1900 */
1901 repeats = 0;
1902 do {
1903 repeats++;
1904
1905 for (waited = 0; waited < apic_max_reps_clear_pending;
1906 waited++) {
1907 if (GET_RDT_BITS(ioapic_ix, intin_no, AV_PENDING) == 0)
1908 break;
1909 }
1910 if (!level)
1911 break;
1912
1913 /*
1914 * Mask the RDT entry for level-triggered interrupts.
1915 */
1916 irqp->airq_rdt_entry |= AV_MASK;
1917 rdt_entry = READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix,
1918 intin_no);
1919 if ((masked = (rdt_entry & AV_MASK)) == 0) {
1920 /* Mask it */
1921 WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, intin_no,
1922 AV_MASK | rdt_entry);
1923 }
1924
1925 /*
1926 * If there was a race and an interrupt was injected
1927 * just before we masked, check for that case here.
1928 * Then, unmask the RDT entry and try again. If we're
1929 * on our last try, don't unmask (because we want the
1930 * RDT entry to remain masked for the rest of the
1931 * function).
1932 */
1933 rdt_entry = READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix,
1934 intin_no);
1935 if ((masked == 0) && ((rdt_entry & AV_PENDING) != 0) &&
1936 (repeats < apic_max_reps_clear_pending)) {
1937 /* Unmask it */
1938 WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix,
1939 intin_no, rdt_entry & ~AV_MASK);
1940 irqp->airq_rdt_entry &= ~AV_MASK;
1941 }
1942 } while ((rdt_entry & AV_PENDING) &&
1943 (repeats < apic_max_reps_clear_pending));
1944
1945 #ifdef DEBUG
1946 if (GET_RDT_BITS(ioapic_ix, intin_no, AV_PENDING) != 0)
1947 apix_intr_deliver_timeouts++;
1948 #endif
1949
1950 if (!level || !APIX_IS_MASK_RDT(apix_mul_ioapic_method))
1951 goto done;
1952
1953 /*
1954 * wait for remote IRR to be cleared for level-triggered
1955 * interrupts
1956 */
1957 repeats = 0;
1958 do {
1959 repeats++;
1960
1961 for (waited = 0; waited < apic_max_reps_clear_pending;
1962 waited++) {
1963 if (GET_RDT_BITS(ioapic_ix, intin_no, AV_REMOTE_IRR)
1964 == 0)
1965 break;
1966 }
1967
1968 if (GET_RDT_BITS(ioapic_ix, intin_no, AV_REMOTE_IRR) != 0) {
1969 lock_clear(&apic_ioapic_lock);
1970 intr_restore(iflag);
1971
1972 delay(APIX_CHECK_IRR_DELAY);
1973
1974 iflag = intr_clear();
1975 lock_set(&apic_ioapic_lock);
1976 }
1977 } while (repeats < apix_max_reps_irr_pending);
1978
1979 if (repeats >= apix_max_reps_irr_pending) {
1980 #ifdef DEBUG
1981 apix_intr_rirr_timeouts++;
1982 #endif
1983
1984 /*
1985 * If we waited and the Remote IRR bit is still not cleared,
1986 * AND if we've invoked the timeout APIC_REPROGRAM_MAX_TIMEOUTS
1987 * times for this interrupt, try the last-ditch workaround:
1988 */
1989 if (GET_RDT_BITS(ioapic_ix, intin_no, AV_REMOTE_IRR) != 0) {
1990 /*
1991 * Trying to clear the bit through normal
1992 * channels has failed. So as a last-ditch
1993 * effort, try to set the trigger mode to
1994 * edge, then to level. This has been
1995 * observed to work on many systems.
1996 */
1997 WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix,
1998 intin_no,
1999 READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix,
2000 intin_no) & ~AV_LEVEL);
2001 WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix,
2002 intin_no,
2003 READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix,
2004 intin_no) | AV_LEVEL);
2005 }
2006
2007 if (GET_RDT_BITS(ioapic_ix, intin_no, AV_REMOTE_IRR) != 0) {
2008 #ifdef DEBUG
2009 apix_intr_rirr_reset_failure++;
2010 #endif
2011 lock_clear(&apic_ioapic_lock);
2012 intr_restore(iflag);
2013 prom_printf("apix: Remote IRR still "
2014 "not clear for IOAPIC %d intin %d.\n"
2015 "\tInterrupts to this pin may cease "
2016 "functioning.\n", ioapic_ix, intin_no);
2017 return (1); /* return failure */
2018 }
2019 }
2020
2021 done:
2022 /* change apic_irq_table */
2023 lock_clear(&apic_ioapic_lock);
2024 intr_restore(iflag);
2025 apix_intx_set_vector(irqno, cpuid, vector);
2026 iflag = intr_clear();
2027 lock_set(&apic_ioapic_lock);
2028
2029 /* reprogramme IO-APIC RDT entry */
2030 apix_intx_enable(irqno);
2031
2032 lock_clear(&apic_ioapic_lock);
2033 intr_restore(iflag);
2034
2035 return (0);
2036 }
2037
2038 static int
2039 apix_intx_get_pending(int irqno)
2040 {
2041 apic_irq_t *irqp;
2042 int intin, ioapicindex, pending;
2043 ulong_t iflag;
2044
2045 mutex_enter(&airq_mutex);
2046 irqp = apic_irq_table[irqno];
2047 if (IS_IRQ_FREE(irqp)) {
2048 mutex_exit(&airq_mutex);
2049 return (0);
2050 }
2051
2052 /* check IO-APIC delivery status */
2053 intin = irqp->airq_intin_no;
2054 ioapicindex = irqp->airq_ioapicindex;
2055 mutex_exit(&airq_mutex);
2056
2057 iflag = intr_clear();
2058 lock_set(&apic_ioapic_lock);
2059
2060 pending = (READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapicindex, intin) &
2061 AV_PENDING) ? 1 : 0;
2062
2063 lock_clear(&apic_ioapic_lock);
2064 intr_restore(iflag);
2065
2066 return (pending);
2067 }
2068
2069 /*
2070 * This function will mask the interrupt on the I/O APIC
2071 */
2072 static void
2073 apix_intx_set_mask(int irqno)
2074 {
2075 int intin, ioapixindex, rdt_entry;
2076 ulong_t iflag;
2077 apic_irq_t *irqp;
2078
2079 mutex_enter(&airq_mutex);
2080 irqp = apic_irq_table[irqno];
2081
2082 ASSERT(irqp->airq_mps_intr_index != FREE_INDEX);
2083
2084 intin = irqp->airq_intin_no;
2085 ioapixindex = irqp->airq_ioapicindex;
2086 mutex_exit(&airq_mutex);
2087
2088 iflag = intr_clear();
2089 lock_set(&apic_ioapic_lock);
2090
2091 rdt_entry = READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapixindex, intin);
2092
2093 /* clear mask */
2094 WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapixindex, intin,
2095 (AV_MASK | rdt_entry));
2096
2097 lock_clear(&apic_ioapic_lock);
2098 intr_restore(iflag);
2099 }
2100
2101 /*
2102 * This function will clear the mask for the interrupt on the I/O APIC
2103 */
2104 static void
2105 apix_intx_clear_mask(int irqno)
2106 {
2107 int intin, ioapixindex, rdt_entry;
2108 ulong_t iflag;
2109 apic_irq_t *irqp;
2110
2111 mutex_enter(&airq_mutex);
2112 irqp = apic_irq_table[irqno];
2113
2114 ASSERT(irqp->airq_mps_intr_index != FREE_INDEX);
2115
2116 intin = irqp->airq_intin_no;
2117 ioapixindex = irqp->airq_ioapicindex;
2118 mutex_exit(&airq_mutex);
2119
2120 iflag = intr_clear();
2121 lock_set(&apic_ioapic_lock);
2122
2123 rdt_entry = READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapixindex, intin);
2124
2125 /* clear mask */
2126 WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapixindex, intin,
2127 ((~AV_MASK) & rdt_entry));
2128
2129 lock_clear(&apic_ioapic_lock);
2130 intr_restore(iflag);
2131 }
2132
2133 /*
2134 * For level-triggered interrupt, mask the IRQ line. Mask means
2135 * new interrupts will not be delivered. The interrupt already
2136 * accepted by a local APIC is not affected
2137 */
2138 void
2139 apix_level_intr_pre_eoi(int irq)
2140 {
2141 apic_irq_t *irqp = apic_irq_table[irq];
2142 int apic_ix, intin_ix;
2143
2144 if (irqp == NULL)
2145 return;
2146
2147 ASSERT(apic_level_intr[irq] == TRIGGER_MODE_LEVEL);
2148
2149 lock_set(&apic_ioapic_lock);
2150
2151 intin_ix = irqp->airq_intin_no;
2152 apic_ix = irqp->airq_ioapicindex;
2153
2154 if (irqp->airq_cpu != CPU->cpu_id) {
2155 if (!APIX_IS_MASK_RDT(apix_mul_ioapic_method))
2156 ioapic_write_eoi(apic_ix, irqp->airq_vector);
2157 lock_clear(&apic_ioapic_lock);
2158 return;
2159 }
2160
2161 if (apix_mul_ioapic_method == APIC_MUL_IOAPIC_IOXAPIC) {
2162 /*
2163 * This is a IOxAPIC and there is EOI register:
2164 * Change the vector to reserved unused vector, so that
2165 * the EOI from Local APIC won't clear the Remote IRR for
2166 * this level trigger interrupt. Instead, we'll manually
2167 * clear it in apix_post_hardint() after ISR handling.
2168 */
2169 WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(apic_ix, intin_ix,
2170 (irqp->airq_rdt_entry & (~0xff)) | APIX_RESV_VECTOR);
2171 } else {
2172 WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(apic_ix, intin_ix,
2173 AV_MASK | irqp->airq_rdt_entry);
2174 }
2175
2176 lock_clear(&apic_ioapic_lock);
2177 }
2178
2179 /*
2180 * For level-triggered interrupt, unmask the IRQ line
2181 * or restore the original vector number.
2182 */
2183 void
2184 apix_level_intr_post_dispatch(int irq)
2185 {
2186 apic_irq_t *irqp = apic_irq_table[irq];
2187 int apic_ix, intin_ix;
2188
2189 if (irqp == NULL)
2190 return;
2191
2192 lock_set(&apic_ioapic_lock);
2193
2194 intin_ix = irqp->airq_intin_no;
2195 apic_ix = irqp->airq_ioapicindex;
2196
2197 if (APIX_IS_DIRECTED_EOI(apix_mul_ioapic_method)) {
2198 /*
2199 * Already sent EOI back to Local APIC.
2200 * Send EOI to IO-APIC
2201 */
2202 ioapic_write_eoi(apic_ix, irqp->airq_vector);
2203 } else {
2204 /* clear the mask or restore the vector */
2205 WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(apic_ix, intin_ix,
2206 irqp->airq_rdt_entry);
2207
2208 /* send EOI to IOxAPIC */
2209 if (apix_mul_ioapic_method == APIC_MUL_IOAPIC_IOXAPIC)
2210 ioapic_write_eoi(apic_ix, irqp->airq_vector);
2211 }
2212
2213 lock_clear(&apic_ioapic_lock);
2214 }
2215
2216 static int
2217 apix_intx_get_shared(int irqno)
2218 {
2219 apic_irq_t *irqp;
2220 int share;
2221
2222 mutex_enter(&airq_mutex);
2223 irqp = apic_irq_table[irqno];
2224 if (IS_IRQ_FREE(irqp) || (irqp->airq_cpu == IRQ_UNINIT)) {
2225 mutex_exit(&airq_mutex);
2226 return (0);
2227 }
2228 share = irqp->airq_share;
2229 mutex_exit(&airq_mutex);
2230
2231 return (share);
2232 }
2233
2234 static void
2235 apix_intx_set_shared(int irqno, int delta)
2236 {
2237 apic_irq_t *irqp;
2238
2239 mutex_enter(&airq_mutex);
2240 irqp = apic_irq_table[irqno];
2241 if (IS_IRQ_FREE(irqp)) {
2242 mutex_exit(&airq_mutex);
2243 return;
2244 }
2245 irqp->airq_share += delta;
2246 mutex_exit(&airq_mutex);
2247 }
2248
2249 /*
2250 * Setup IRQ table. Return IRQ no or -1 on failure
2251 */
2252 static int
2253 apix_intx_setup(dev_info_t *dip, int inum, int irqno,
2254 struct apic_io_intr *intrp, struct intrspec *ispec, iflag_t *iflagp)
2255 {
2256 int origirq = ispec->intrspec_vec;
2257 int newirq;
2258 short intr_index;
2259 uchar_t ipin, ioapic, ioapicindex;
2260 apic_irq_t *irqp;
2261
2262 UNREFERENCED_1PARAMETER(inum);
2263
2264 if (intrp != NULL) {
2265 intr_index = (short)(intrp - apic_io_intrp);
2266 ioapic = intrp->intr_destid;
2267 ipin = intrp->intr_destintin;
2268
2269 /* Find ioapicindex. If destid was ALL, we will exit with 0. */
2270 for (ioapicindex = apic_io_max - 1; ioapicindex; ioapicindex--)
2271 if (apic_io_id[ioapicindex] == ioapic)
2272 break;
2273 ASSERT((ioapic == apic_io_id[ioapicindex]) ||
2274 (ioapic == INTR_ALL_APIC));
2275
2276 /* check whether this intin# has been used by another irqno */
2277 if ((newirq = apic_find_intin(ioapicindex, ipin)) != -1)
2278 return (newirq);
2279
2280 } else if (iflagp != NULL) { /* ACPI */
2281 intr_index = ACPI_INDEX;
2282 ioapicindex = acpi_find_ioapic(irqno);
2283 ASSERT(ioapicindex != 0xFF);
2284 ioapic = apic_io_id[ioapicindex];
2285 ipin = irqno - apic_io_vectbase[ioapicindex];
2286
2287 if (apic_irq_table[irqno] &&
2288 apic_irq_table[irqno]->airq_mps_intr_index == ACPI_INDEX) {
2289 ASSERT(apic_irq_table[irqno]->airq_intin_no == ipin &&
2290 apic_irq_table[irqno]->airq_ioapicindex ==
2291 ioapicindex);
2292 return (irqno);
2293 }
2294
2295 } else { /* default configuration */
2296 intr_index = DEFAULT_INDEX;
2297 ioapicindex = 0;
2298 ioapic = apic_io_id[ioapicindex];
2299 ipin = (uchar_t)irqno;
2300 }
2301
2302 /* allocate a new IRQ no */
2303 if ((irqp = apic_irq_table[irqno]) == NULL) {
2304 irqp = kmem_zalloc(sizeof (apic_irq_t), KM_SLEEP);
2305 apic_irq_table[irqno] = irqp;
2306 } else {
2307 if (irqp->airq_mps_intr_index != FREE_INDEX) {
2308 newirq = apic_allocate_irq(apic_first_avail_irq);
2309 if (newirq == -1) {
2310 return (-1);
2311 }
2312 irqno = newirq;
2313 irqp = apic_irq_table[irqno];
2314 ASSERT(irqp != NULL);
2315 }
2316 }
2317 apic_max_device_irq = max(irqno, apic_max_device_irq);
2318 apic_min_device_irq = min(irqno, apic_min_device_irq);
2319
2320 irqp->airq_mps_intr_index = intr_index;
2321 irqp->airq_ioapicindex = ioapicindex;
2322 irqp->airq_intin_no = ipin;
2323 irqp->airq_dip = dip;
2324 irqp->airq_origirq = (uchar_t)origirq;
2325 if (iflagp != NULL)
2326 irqp->airq_iflag = *iflagp;
2327 irqp->airq_cpu = IRQ_UNINIT;
2328 irqp->airq_vector = 0;
2329
2330 return (irqno);
2331 }
2332
2333 /*
2334 * Setup IRQ table for non-pci devices. Return IRQ no or -1 on error
2335 */
2336 static int
2337 apix_intx_setup_nonpci(dev_info_t *dip, int inum, int bustype,
2338 struct intrspec *ispec)
2339 {
2340 int irqno = ispec->intrspec_vec;
2341 int newirq, i;
2342 iflag_t intr_flag;
2343 ACPI_SUBTABLE_HEADER *hp;
2344 ACPI_MADT_INTERRUPT_OVERRIDE *isop;
2345 struct apic_io_intr *intrp;
2346
2347 if (!apic_enable_acpi || apic_use_acpi_madt_only) {
2348 int busid;
2349
2350 if (bustype == 0)
2351 bustype = eisa_level_intr_mask ? BUS_EISA : BUS_ISA;
2352
2353 /* loop checking BUS_ISA/BUS_EISA */
2354 for (i = 0; i < 2; i++) {
2355 if (((busid = apic_find_bus_id(bustype)) != -1) &&
2356 ((intrp = apic_find_io_intr_w_busid(irqno, busid))
2357 != NULL)) {
2358 return (apix_intx_setup(dip, inum, irqno,
2359 intrp, ispec, NULL));
2360 }
2361 bustype = (bustype == BUS_EISA) ? BUS_ISA : BUS_EISA;
2362 }
2363
2364 /* fall back to default configuration */
2365 return (-1);
2366 }
2367
2368 /* search iso entries first */
2369 if (acpi_iso_cnt != 0) {
2370 hp = (ACPI_SUBTABLE_HEADER *)acpi_isop;
2371 i = 0;
2372 while (i < acpi_iso_cnt) {
2373 if (hp->Type == ACPI_MADT_TYPE_INTERRUPT_OVERRIDE) {
2374 isop = (ACPI_MADT_INTERRUPT_OVERRIDE *) hp;
2375 if (isop->Bus == 0 &&
2376 isop->SourceIrq == irqno) {
2377 newirq = isop->GlobalIrq;
2378 intr_flag.intr_po = isop->IntiFlags &
2379 ACPI_MADT_POLARITY_MASK;
2380 intr_flag.intr_el = (isop->IntiFlags &
2381 ACPI_MADT_TRIGGER_MASK) >> 2;
2382 intr_flag.bustype = BUS_ISA;
2383
2384 return (apix_intx_setup(dip, inum,
2385 newirq, NULL, ispec, &intr_flag));
2386 }
2387 i++;
2388 }
2389 hp = (ACPI_SUBTABLE_HEADER *)(((char *)hp) +
2390 hp->Length);
2391 }
2392 }
2393 intr_flag.intr_po = INTR_PO_ACTIVE_HIGH;
2394 intr_flag.intr_el = INTR_EL_EDGE;
2395 intr_flag.bustype = BUS_ISA;
2396 return (apix_intx_setup(dip, inum, irqno, NULL, ispec, &intr_flag));
2397 }
2398
2399
2400 /*
2401 * Setup IRQ table for pci devices. Return IRQ no or -1 on error
2402 */
2403 static int
2404 apix_intx_setup_pci(dev_info_t *dip, int inum, int bustype,
2405 struct intrspec *ispec)
2406 {
2407 int busid, devid, pci_irq;
2408 ddi_acc_handle_t cfg_handle;
2409 uchar_t ipin;
2410 iflag_t intr_flag;
2411 struct apic_io_intr *intrp;
2412
2413 if (acpica_get_bdf(dip, &busid, &devid, NULL) != 0)
2414 return (-1);
2415
2416 if (busid == 0 && apic_pci_bus_total == 1)
2417 busid = (int)apic_single_pci_busid;
2418
2419 if (pci_config_setup(dip, &cfg_handle) != DDI_SUCCESS)
2420 return (-1);
2421 ipin = pci_config_get8(cfg_handle, PCI_CONF_IPIN) - PCI_INTA;
2422 pci_config_teardown(&cfg_handle);
2423
2424 if (apic_enable_acpi && !apic_use_acpi_madt_only) { /* ACPI */
2425 if (apic_acpi_translate_pci_irq(dip, busid, devid,
2426 ipin, &pci_irq, &intr_flag) != ACPI_PSM_SUCCESS)
2427 return (-1);
2428
2429 intr_flag.bustype = (uchar_t)bustype;
2430 return (apix_intx_setup(dip, inum, pci_irq, NULL, ispec,
2431 &intr_flag));
2432 }
2433
2434 /* MP configuration table */
2435 pci_irq = ((devid & 0x1f) << 2) | (ipin & 0x3);
2436 if ((intrp = apic_find_io_intr_w_busid(pci_irq, busid)) == NULL) {
2437 pci_irq = apic_handle_pci_pci_bridge(dip, devid, ipin, &intrp);
2438 if (pci_irq == -1)
2439 return (-1);
2440 }
2441
2442 return (apix_intx_setup(dip, inum, pci_irq, intrp, ispec, NULL));
2443 }
2444
2445 /*
2446 * Translate and return IRQ no
2447 */
2448 static int
2449 apix_intx_xlate_irq(dev_info_t *dip, int inum, struct intrspec *ispec)
2450 {
2451 int newirq, irqno = ispec->intrspec_vec;
2452 int parent_is_pci_or_pciex = 0, child_is_pciex = 0;
2453 int bustype = 0, dev_len;
2454 char dev_type[16];
2455
2456 if (apic_defconf) {
2457 mutex_enter(&airq_mutex);
2458 goto defconf;
2459 }
2460
2461 if ((dip == NULL) || (!apic_irq_translate && !apic_enable_acpi)) {
2462 mutex_enter(&airq_mutex);
2463 goto nonpci;
2464 }
2465
2466 /*
2467 * use ddi_getlongprop_buf() instead of ddi_prop_lookup_string()
2468 * to avoid extra buffer allocation.
2469 */
2470 dev_len = sizeof (dev_type);
2471 if (ddi_getlongprop_buf(DDI_DEV_T_ANY, ddi_get_parent(dip),
2472 DDI_PROP_DONTPASS, "device_type", (caddr_t)dev_type,
2473 &dev_len) == DDI_PROP_SUCCESS) {
2474 if ((strcmp(dev_type, "pci") == 0) ||
2475 (strcmp(dev_type, "pciex") == 0))
2476 parent_is_pci_or_pciex = 1;
2477 }
2478
2479 if (ddi_getlongprop_buf(DDI_DEV_T_ANY, dip,
2480 DDI_PROP_DONTPASS, "compatible", (caddr_t)dev_type,
2481 &dev_len) == DDI_PROP_SUCCESS) {
2482 if (strstr(dev_type, "pciex"))
2483 child_is_pciex = 1;
2484 }
2485
2486 mutex_enter(&airq_mutex);
2487
2488 if (parent_is_pci_or_pciex) {
2489 bustype = child_is_pciex ? BUS_PCIE : BUS_PCI;
2490 newirq = apix_intx_setup_pci(dip, inum, bustype, ispec);
2491 if (newirq != -1)
2492 goto done;
2493 bustype = 0;
2494 } else if (strcmp(dev_type, "isa") == 0)
2495 bustype = BUS_ISA;
2496 else if (strcmp(dev_type, "eisa") == 0)
2497 bustype = BUS_EISA;
2498
2499 nonpci:
2500 newirq = apix_intx_setup_nonpci(dip, inum, bustype, ispec);
2501 if (newirq != -1)
2502 goto done;
2503
2504 defconf:
2505 newirq = apix_intx_setup(dip, inum, irqno, NULL, ispec, NULL);
2506 if (newirq == -1) {
2507 mutex_exit(&airq_mutex);
2508 return (-1);
2509 }
2510 done:
2511 ASSERT(apic_irq_table[newirq]);
2512 mutex_exit(&airq_mutex);
2513 return (newirq);
2514 }
2515
2516 static int
2517 apix_intx_alloc_vector(dev_info_t *dip, ddi_intr_handle_impl_t *hdlp,
2518 struct intrspec *ispec)
2519 {
2520 int irqno;
2521 apix_vector_t *vecp;
2522
2523 if ((irqno = apix_intx_xlate_irq(dip, hdlp->ih_inum, ispec)) == -1)
2524 return (0);
2525
2526 if ((vecp = apix_alloc_intx(dip, hdlp->ih_inum, irqno)) == NULL)
2527 return (0);
2528
2529 hdlp->ih_irq = irqno;
2530
2531 DDI_INTR_IMPLDBG((CE_CONT, "apix_intx_alloc_vector: dip=0x%p name=%s "
2532 "irqno=0x%x cpuid=%d vector=0x%x\n",
2533 (void *)dip, ddi_driver_name(dip), irqno,
2534 vecp->v_cpuid, vecp->v_vector));
2535
2536 return (1);
2537 }
2538
2539 /*
2540 * Return the vector number if the translated IRQ for this device
2541 * has a vector mapping setup. If no IRQ setup exists or no vector is
2542 * allocated to it then return 0.
2543 */
2544 static apix_vector_t *
2545 apix_intx_xlate_vector(dev_info_t *dip, int inum, struct intrspec *ispec)
2546 {
2547 int irqno;
2548 apix_vector_t *vecp;
2549
2550 /* get the IRQ number */
2551 if ((irqno = apix_intx_xlate_irq(dip, inum, ispec)) == -1)
2552 return (NULL);
2553
2554 /* get the vector number if a vector is allocated to this irqno */
2555 vecp = apix_intx_get_vector(irqno);
2556
2557 return (vecp);
2558 }
2559
2560 /*
2561 * Switch between safe and x2APIC IPI sending method.
2562 * The CPU may power on in xapic mode or x2apic mode. If the CPU needs to send
2563 * an IPI to other CPUs before entering x2APIC mode, it still needs to use the
2564 * xAPIC method. Before sending a StartIPI to the target CPU, psm_send_ipi will
2565 * be changed to apic_common_send_ipi, which detects current local APIC mode and
2566 * use the right method to send an IPI. If some CPUs fail to start up,
2567 * apic_poweron_cnt won't return to zero, so apic_common_send_ipi will always be
2568 * used. psm_send_ipi can't be simply changed back to x2apic_send_ipi if some
2569 * CPUs failed to start up because those failed CPUs may recover itself later at
2570 * unpredictable time.
2571 */
2572 void
2573 apic_switch_ipi_callback(boolean_t enter)
2574 {
2575 ulong_t iflag;
2576 struct psm_ops *pops = psmops;
2577
2578 iflag = intr_clear();
2579 lock_set(&apic_mode_switch_lock);
2580 if (enter) {
2581 ASSERT(apic_poweron_cnt >= 0);
2582 if (apic_poweron_cnt == 0) {
2583 pops->psm_send_ipi = apic_common_send_ipi;
2584 send_dirintf = pops->psm_send_ipi;
2585 }
2586 apic_poweron_cnt++;
2587 } else {
2588 ASSERT(apic_poweron_cnt > 0);
2589 apic_poweron_cnt--;
2590 if (apic_poweron_cnt == 0) {
2591 pops->psm_send_ipi = x2apic_send_ipi;
2592 send_dirintf = pops->psm_send_ipi;
2593 }
2594 }
2595 lock_clear(&apic_mode_switch_lock);
2596 intr_restore(iflag);
2597 }
2598
2599 /* stub function */
2600 int
2601 apix_loaded(void)
2602 {
2603 return (apix_is_enabled);
2604 }