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3605 Xen HVM hangs during boot if apix is enabled
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--- old/usr/src/uts/common/sys/ddi_intr_impl.h
+++ new/usr/src/uts/common/sys/ddi_intr_impl.h
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21 /*
22 22 * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved.
23 23 */
24 24
25 25 #ifndef _SYS_DDI_INTR_IMPL_H
26 26 #define _SYS_DDI_INTR_IMPL_H
27 27
28 28 /*
29 29 * Sun DDI interrupt implementation specific definitions
30 30 */
31 31
32 32 #include <sys/list.h>
33 33 #include <sys/ksynch.h>
34 34
35 35 #ifdef __cplusplus
36 36 extern "C" {
37 37 #endif
38 38
39 39 #ifdef _KERNEL
40 40
41 41 /*
42 42 * Typedef for interrupt ops
43 43 */
44 44 typedef enum {
45 45 DDI_INTROP_SUPPORTED_TYPES = 1, /* 1 get supported interrupts types */
46 46 DDI_INTROP_NINTRS, /* 2 get num of interrupts supported */
47 47 DDI_INTROP_ALLOC, /* 3 allocate interrupt handle */
48 48 DDI_INTROP_GETPRI, /* 4 get priority */
49 49 DDI_INTROP_SETPRI, /* 5 set priority */
50 50 DDI_INTROP_ADDISR, /* 6 add interrupt handler */
51 51 DDI_INTROP_DUPVEC, /* 7 duplicate interrupt handler */
52 52 DDI_INTROP_ENABLE, /* 8 enable interrupt */
53 53 DDI_INTROP_BLOCKENABLE, /* 9 block enable interrupts */
54 54 DDI_INTROP_BLOCKDISABLE, /* 10 block disable interrupts */
55 55 DDI_INTROP_DISABLE, /* 11 disable interrupt */
56 56 DDI_INTROP_REMISR, /* 12 remove interrupt handler */
57 57 DDI_INTROP_FREE, /* 13 free interrupt handle */
58 58 DDI_INTROP_GETCAP, /* 14 get capacity */
59 59 DDI_INTROP_SETCAP, /* 15 set capacity */
60 60 DDI_INTROP_SETMASK, /* 16 set mask */
61 61 DDI_INTROP_CLRMASK, /* 17 clear mask */
62 62 DDI_INTROP_GETPENDING, /* 18 get pending interrupt */
63 63 DDI_INTROP_NAVAIL, /* 19 get num of available interrupts */
64 64 DDI_INTROP_GETPOOL, /* 20 get resource management pool */
65 65 DDI_INTROP_GETTARGET, /* 21 get target for a given intr(s) */
66 66 DDI_INTROP_SETTARGET /* 22 set target for a given intr(s) */
67 67 } ddi_intr_op_t;
68 68
69 69 /* Version number used in the handles */
70 70 #define DDI_INTR_VERSION_1 1
71 71 #define DDI_INTR_VERSION DDI_INTR_VERSION_1
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72 72
73 73 /*
74 74 * One such data structure is allocated per ddi_intr_handle_t
75 75 * This is the incore copy of the regular interrupt info.
76 76 */
77 77 typedef struct ddi_intr_handle_impl {
78 78 dev_info_t *ih_dip; /* dip associated with handle */
79 79 uint16_t ih_type; /* interrupt type being used */
80 80 ushort_t ih_inum; /* interrupt number */
81 81 uint32_t ih_vector; /* vector number */
82 + int ih_irq; /* irq number */
82 83 uint16_t ih_ver; /* Version */
83 84 uint_t ih_state; /* interrupt handle state */
84 85 uint_t ih_cap; /* interrupt capabilities */
85 86 uint_t ih_pri; /* priority - bus dependent */
86 87 krwlock_t ih_rwlock; /* read/write lock per handle */
87 88
88 89 uint_t (*ih_cb_func)(caddr_t, caddr_t);
89 90 void *ih_cb_arg1;
90 91 void *ih_cb_arg2;
91 92
92 93 /*
93 94 * The following 3 members are used to support MSI-X specific features
94 95 */
95 96 uint_t ih_flags; /* Misc flags */
96 97 uint_t ih_dup_cnt; /* # of dupped msi-x vectors */
97 98 struct ddi_intr_handle_impl *ih_main;
98 99 /* pntr to the main vector */
99 100 /*
100 101 * The next set of members are for 'scratch' purpose only.
101 102 * The DDI interrupt framework uses them internally and their
102 103 * interpretation is left to the framework. For now,
103 104 * scratch1 - used to send NINTRs information
104 105 * to various nexus drivers.
105 106 * scratch2 - used to send 'behavior' flag
106 107 * information to the nexus drivers
107 108 * from ddi_intr_alloc(). It is also
108 109 * used to send 'h_array' to the nexus drivers
109 110 * for ddi_intr_block_enable/disable() on x86.
110 111 * private - On X86 it usually carries a pointer to
111 112 * ihdl_plat_t. Not used on SPARC platforms.
112 113 */
113 114 void *ih_private; /* Platform specific data */
114 115 uint_t ih_scratch1; /* Scratch1: #interrupts */
115 116 void *ih_scratch2; /* Scratch2: flag/h_array */
116 117
117 118 /*
118 119 * The ih_target field may not reflect the actual target that is
119 120 * currently being used for the given interrupt. This field is just a
120 121 * snapshot taken either during ddi_intr_add_handler() or
121 122 * get/set_intr_affinity() calls.
122 123 */
123 124 processorid_t ih_target; /* Target ID */
124 125 } ddi_intr_handle_impl_t;
125 126
126 127 /* values for ih_state (strictly for interrupt handle) */
127 128 #define DDI_IHDL_STATE_ALLOC 0x01 /* Allocated. ddi_intr_alloc() called */
128 129 #define DDI_IHDL_STATE_ADDED 0x02 /* Added interrupt handler */
129 130 /* ddi_intr_add_handler() called */
130 131 #define DDI_IHDL_STATE_ENABLE 0x04 /* Enabled. ddi_intr_enable() called */
131 132
132 133 #define DDI_INTR_IS_MSI_OR_MSIX(type) \
133 134 ((type) == DDI_INTR_TYPE_MSI || (type) == DDI_INTR_TYPE_MSIX)
134 135
135 136 #define DDI_INTR_BEHAVIOR_FLAG_VALID(f) \
136 137 (((f) == DDI_INTR_ALLOC_NORMAL) || ((f) == DDI_INTR_ALLOC_STRICT))
137 138
138 139 #define DDI_INTR_TYPE_FLAG_VALID(t) \
139 140 (((t) == DDI_INTR_TYPE_FIXED) || \
140 141 ((t) == DDI_INTR_TYPE_MSI) || \
141 142 ((t) == DDI_INTR_TYPE_MSIX))
142 143
143 144 /* values for ih_flags */
144 145 #define DDI_INTR_MSIX_DUP 0x01 /* MSI-X vector which has been dupped */
145 146
146 147 /* Maximum number of MSI resources to allocate */
147 148 #define DDI_MAX_MSI_ALLOC 2
148 149
149 150 /* Default number of MSI-X resources to allocate */
150 151 #define DDI_DEFAULT_MSIX_ALLOC 2
151 152
152 153 #define DDI_MSIX_ALLOC_DIVIDER 32
153 154 #define DDI_MIN_MSIX_ALLOC 8
154 155 #define DDI_MAX_MSIX_ALLOC 2048
155 156
156 157 struct av_softinfo;
157 158
158 159 /*
159 160 * One such data structure is allocated per ddi_soft_intr_handle
160 161 * This is the incore copy of the softint info.
161 162 */
162 163 typedef struct ddi_softint_hdl_impl {
163 164 dev_info_t *ih_dip; /* dip associated with handle */
164 165 uint_t ih_pri; /* priority - bus dependent */
165 166 krwlock_t ih_rwlock; /* read/write lock per handle */
166 167 struct av_softinfo *ih_pending; /* whether softint is pending */
167 168
168 169 uint_t (*ih_cb_func)(caddr_t, caddr_t);
169 170 /* cb function for soft ints */
170 171 void *ih_cb_arg1; /* arg1 of callback function */
171 172 void *ih_cb_arg2; /* arg2 passed to "trigger" */
172 173
173 174 /*
174 175 * The next member is for 'scratch' purpose only.
175 176 * The DDI interrupt framework uses it internally and its
176 177 * interpretation is left to the framework.
177 178 * private - used by the DDI framework to pass back
178 179 * and forth 'softid' information on SPARC
179 180 * side only. Not used on X86 platform.
180 181 */
181 182 void *ih_private; /* Platform specific data */
182 183 } ddi_softint_hdl_impl_t;
183 184
184 185 /* Softint internal implementation defines */
185 186 #define DDI_SOFT_INTR_PRI_M 4
186 187 #define DDI_SOFT_INTR_PRI_H 6
187 188
188 189 /*
189 190 * One such data structure is allocated for MSI-X enabled
190 191 * device. If no MSI-X is enabled then it is NULL
191 192 */
192 193 typedef struct ddi_intr_msix {
193 194 /* MSI-X Table related information */
194 195 ddi_acc_handle_t msix_tbl_hdl; /* MSI-X table handle */
195 196 uint32_t *msix_tbl_addr; /* MSI-X table addr */
196 197 uint32_t msix_tbl_offset; /* MSI-X table offset */
197 198
198 199 /* MSI-X PBA Table related information */
199 200 ddi_acc_handle_t msix_pba_hdl; /* MSI-X PBA handle */
200 201 uint32_t *msix_pba_addr; /* MSI-X PBA addr */
201 202 uint32_t msix_pba_offset; /* MSI-X PBA offset */
202 203
203 204 ddi_device_acc_attr_t msix_dev_attr; /* MSI-X device attr */
204 205 } ddi_intr_msix_t;
205 206
206 207 /*
207 208 * Interrupt Resource Management (IRM).
208 209 */
209 210
210 211 #define DDI_IRM_POLICY_LARGE 1
211 212 #define DDI_IRM_POLICY_EVEN 2
212 213
213 214 #define DDI_IRM_POLICY_VALID(p) (((p) == DDI_IRM_POLICY_LARGE) || \
214 215 ((p) == DDI_IRM_POLICY_EVEN))
215 216
216 217 #define DDI_IRM_FLAG_ACTIVE 0x1 /* Pool is active */
217 218 #define DDI_IRM_FLAG_QUEUED 0x2 /* Pool is queued */
218 219 #define DDI_IRM_FLAG_WAITERS 0x4 /* Pool has waiters */
219 220 #define DDI_IRM_FLAG_EXIT 0x8 /* Balance thread must exit */
220 221 #define DDI_IRM_FLAG_NEW 0x10 /* Request is new */
221 222 #define DDI_IRM_FLAG_CALLBACK 0x20 /* Request has callback */
222 223
223 224 /*
224 225 * One such data structure for each supply of interrupt vectors.
225 226 * Contains information about the size and policies defining the
226 227 * supply, and a list of associated device-specific requests.
227 228 */
228 229 typedef struct ddi_irm_pool {
229 230 int ipool_flags; /* Status flags of the pool */
230 231 int ipool_types; /* Types of interrupts */
231 232 int ipool_policy; /* Rebalancing policy */
232 233 uint_t ipool_totsz; /* Total size of the pool */
233 234 uint_t ipool_defsz; /* Default allocation size */
234 235 uint_t ipool_minno; /* Minimum number consumed */
235 236 uint_t ipool_reqno; /* Total number requested */
236 237 uint_t ipool_resno; /* Total number reserved */
237 238 kmutex_t ipool_lock; /* Protects all pool usage */
238 239 kmutex_t ipool_navail_lock; /* Protects 'navail' of reqs */
239 240 kcondvar_t ipool_cv; /* Condition variable */
240 241 kthread_t *ipool_thread; /* Balancing thread */
241 242 dev_info_t *ipool_owner; /* Device that created pool */
242 243 list_t ipool_req_list; /* All requests in pool */
243 244 list_t ipool_scratch_list; /* Requests being reduced */
244 245 list_node_t ipool_link; /* Links in global pool list */
245 246 } ddi_irm_pool_t;
246 247
247 248 /*
248 249 * One such data structure for each dip's devinfo_intr_t.
249 250 * Contains information about vectors requested from IRM.
250 251 */
251 252 typedef struct ddi_irm_req {
252 253 int ireq_flags; /* Flags for request */
253 254 int ireq_type; /* Type requested */
254 255 uint_t ireq_nreq; /* Number requested */
255 256 uint_t ireq_navail; /* Number available */
256 257 uint_t ireq_scratch; /* Scratch value */
257 258 dev_info_t *ireq_dip; /* Requesting device */
258 259 ddi_irm_pool_t *ireq_pool_p; /* Supplying pool */
259 260 list_node_t ireq_link; /* Request list link */
260 261 list_node_t ireq_scratch_link; /* Scratch list link */
261 262 } ddi_irm_req_t;
262 263
263 264 /*
264 265 * This structure is used to pass parameters to ndi_create_irm(),
265 266 * and describes the operating parameters of an IRM pool.
266 267 */
267 268 typedef struct ddi_irm_params {
268 269 int iparams_types; /* Types of interrupts in pool */
269 270 uint_t iparams_total; /* Total size of the pool */
270 271 } ddi_irm_params_t;
271 272
272 273 /*
273 274 * One such data structure is allocated for each dip.
274 275 * It has interrupt related information that can be
275 276 * stored/retrieved for convenience.
276 277 */
277 278 typedef struct devinfo_intr {
278 279 /* These three fields show what the device is capable of */
279 280 uint_t devi_intr_sup_types; /* Intrs supported by device */
280 281
281 282 ddi_intr_msix_t *devi_msix_p; /* MSI-X info, if supported */
282 283
283 284 /* Next three fields show current status for the device */
284 285 uint_t devi_intr_curr_type; /* Interrupt type being used */
285 286 uint_t devi_intr_sup_nintrs; /* #intr supported */
286 287 uint_t devi_intr_curr_nintrs; /* #intr currently being used */
287 288 /*
288 289 * #intr currently being enabled
289 290 * (for MSI block enable, the valuse is either 1 or 0.)
290 291 */
291 292 uint_t devi_intr_curr_nenables;
292 293
293 294 ddi_intr_handle_t *devi_intr_handle_p; /* Hdl for legacy intr APIs */
294 295
295 296 #if defined(__i386) || defined(__amd64)
296 297 /* Save the PCI config space handle */
297 298 ddi_acc_handle_t devi_cfg_handle;
298 299 int devi_cap_ptr; /* MSI or MSI-X cap pointer */
299 300 #endif
300 301
301 302 ddi_irm_req_t *devi_irm_req_p; /* IRM request information */
302 303 } devinfo_intr_t;
303 304
304 305 #define NEXUS_HAS_INTR_OP(dip) \
305 306 ((DEVI(dip)->devi_ops->devo_bus_ops) && \
306 307 (DEVI(dip)->devi_ops->devo_bus_ops->busops_rev >= BUSO_REV_9) && \
307 308 (DEVI(dip)->devi_ops->devo_bus_ops->bus_intr_op))
308 309
309 310 int i_ddi_intr_ops(dev_info_t *dip, dev_info_t *rdip, ddi_intr_op_t op,
310 311 ddi_intr_handle_impl_t *hdlp, void *result);
311 312
312 313 int i_ddi_add_softint(ddi_softint_hdl_impl_t *);
313 314 void i_ddi_remove_softint(ddi_softint_hdl_impl_t *);
314 315 int i_ddi_trigger_softint(ddi_softint_hdl_impl_t *, void *);
315 316 int i_ddi_set_softint_pri(ddi_softint_hdl_impl_t *, uint_t);
316 317
317 318 void i_ddi_intr_devi_init(dev_info_t *dip);
318 319 void i_ddi_intr_devi_fini(dev_info_t *dip);
319 320
320 321 uint_t i_ddi_intr_get_supported_types(dev_info_t *dip);
321 322 void i_ddi_intr_set_supported_types(dev_info_t *dip, int sup_type);
322 323 uint_t i_ddi_intr_get_current_type(dev_info_t *dip);
323 324 void i_ddi_intr_set_current_type(dev_info_t *dip, int intr_type);
324 325 uint_t i_ddi_intr_get_supported_nintrs(dev_info_t *dip, int intr_type);
325 326 void i_ddi_intr_set_supported_nintrs(dev_info_t *dip, int nintrs);
326 327 uint_t i_ddi_intr_get_current_nintrs(dev_info_t *dip);
327 328 void i_ddi_intr_set_current_nintrs(dev_info_t *dip, int nintrs);
328 329 uint_t i_ddi_intr_get_current_nenables(dev_info_t *dip);
329 330 void i_ddi_intr_set_current_nenables(dev_info_t *dip, int nintrs);
330 331 uint_t i_ddi_intr_get_current_navail(dev_info_t *dip, int intr_type);
331 332 uint_t i_ddi_intr_get_limit(dev_info_t *dip, int intr_type,
332 333 ddi_irm_pool_t *pool_p);
333 334
334 335 ddi_irm_pool_t *i_ddi_intr_get_pool(dev_info_t *dip, int intr_type);
335 336
336 337 void irm_init(void);
337 338 int i_ddi_irm_insert(dev_info_t *dip, int intr_type, int count);
338 339 int i_ddi_irm_modify(dev_info_t *dip, int nreq);
339 340 int i_ddi_irm_remove(dev_info_t *dip);
340 341 void i_ddi_irm_set_cb(dev_info_t *dip, boolean_t cb_flag);
341 342 int i_ddi_irm_supported(dev_info_t *dip, int type);
342 343
343 344 ddi_intr_handle_t i_ddi_get_intr_handle(dev_info_t *dip, int inum);
344 345 void i_ddi_set_intr_handle(dev_info_t *dip, int inum, ddi_intr_handle_t hdl);
345 346
346 347 ddi_intr_msix_t *i_ddi_get_msix(dev_info_t *dip);
347 348 void i_ddi_set_msix(dev_info_t *dip, ddi_intr_msix_t *msix_p);
348 349
349 350 #if defined(__i386) || defined(__amd64)
350 351 ddi_acc_handle_t i_ddi_get_pci_config_handle(dev_info_t *dip);
351 352 void i_ddi_set_pci_config_handle(dev_info_t *dip, ddi_acc_handle_t handle);
352 353 int i_ddi_get_msi_msix_cap_ptr(dev_info_t *dip);
353 354 void i_ddi_set_msi_msix_cap_ptr(dev_info_t *dip, int cap_ptr);
354 355 #endif
355 356
356 357 int32_t i_ddi_get_intr_weight(dev_info_t *);
357 358 int32_t i_ddi_set_intr_weight(dev_info_t *, int32_t);
358 359
359 360 void i_ddi_alloc_intr_phdl(ddi_intr_handle_impl_t *);
360 361 void i_ddi_free_intr_phdl(ddi_intr_handle_impl_t *);
361 362
362 363 extern int irm_enable; /* global flag for IRM */
363 364
364 365 #define DDI_INTR_ASSIGN_HDLR_N_ARGS(hdlp, func, arg1, arg2) \
365 366 hdlp->ih_cb_func = func; \
366 367 hdlp->ih_cb_arg1 = arg1; \
367 368 hdlp->ih_cb_arg2 = arg2;
368 369
369 370 #ifdef DEBUG
370 371 #define I_DDI_VERIFY_MSIX_HANDLE(hdlp) \
371 372 if ((hdlp->ih_type == DDI_INTR_TYPE_MSIX) && \
372 373 (hdlp->ih_flags & DDI_INTR_MSIX_DUP)) { \
373 374 ASSERT(hdlp->ih_dip == hdlp->ih_main->ih_dip); \
374 375 ASSERT(hdlp->ih_type == hdlp->ih_main->ih_type); \
375 376 ASSERT(hdlp->ih_vector == hdlp->ih_main->ih_vector); \
376 377 ASSERT(hdlp->ih_ver == hdlp->ih_main->ih_ver); \
377 378 ASSERT(hdlp->ih_cap == hdlp->ih_main->ih_cap); \
378 379 ASSERT(hdlp->ih_pri == hdlp->ih_main->ih_pri); \
379 380 }
380 381 #else
381 382 #define I_DDI_VERIFY_MSIX_HANDLE(hdlp)
382 383 #endif
383 384
384 385 #else /* _KERNEL */
385 386
386 387 typedef struct devinfo_intr devinfo_intr_t;
387 388
388 389 #endif /* _KERNEL */
389 390
390 391 /*
391 392 * Used only by old DDI interrupt interfaces.
392 393 */
393 394
394 395 /*
395 396 * This structure represents one interrupt possible from the given
396 397 * device. It is used in an array for devices with multiple interrupts.
397 398 */
398 399 struct intrspec {
399 400 uint_t intrspec_pri; /* interrupt priority */
400 401 uint_t intrspec_vec; /* vector # (0 if none) */
401 402 uint_t (*intrspec_func)(); /* function to call for interrupt, */
402 403 /* If (uint_t (*)()) 0, none. */
403 404 /* If (uint_t (*)()) 1, then */
404 405 };
405 406
406 407 #ifdef _KERNEL
407 408
408 409 /*
409 410 * Figure out how many FIXED nintrs are supported
410 411 */
411 412 int i_ddi_get_intx_nintrs(dev_info_t *dip);
412 413
413 414 /*
414 415 * NOTE:
415 416 * The following 4 busops entry points are obsoleted with version
416 417 * 9 or greater. Use i_ddi_intr_op interface in place of these
417 418 * obsolete interfaces.
418 419 *
419 420 * Remove these busops entry points and all related data structures
420 421 * in future minor/major solaris release.
421 422 */
422 423 typedef enum {DDI_INTR_CTLOPS_NONE} ddi_intr_ctlop_t;
423 424
424 425 /*
425 426 * Interrupt get/set affinity functions
426 427 */
427 428 int get_intr_affinity(ddi_intr_handle_t h, processorid_t *tgt_p);
428 429 int set_intr_affinity(ddi_intr_handle_t h, processorid_t tgt);
429 430
430 431 /* The following are obsolete interfaces */
431 432 ddi_intrspec_t i_ddi_get_intrspec(dev_info_t *dip, dev_info_t *rdip,
432 433 uint_t inumber);
433 434
434 435 int i_ddi_add_intrspec(dev_info_t *dip, dev_info_t *rdip,
435 436 ddi_intrspec_t intrspec, ddi_iblock_cookie_t *iblock_cookiep,
436 437 ddi_idevice_cookie_t *idevice_cookiep,
437 438 uint_t (*int_handler)(caddr_t int_handler_arg),
438 439 caddr_t int_handler_arg, int kind);
439 440
440 441 void i_ddi_remove_intrspec(dev_info_t *dip, dev_info_t *rdip,
441 442 ddi_intrspec_t intrspec, ddi_iblock_cookie_t iblock_cookie);
442 443
443 444 int i_ddi_intr_ctlops(dev_info_t *dip, dev_info_t *rdip,
444 445 ddi_intr_ctlop_t op, void *arg, void *val);
445 446
446 447 #endif /* _KERNEL */
447 448
448 449 #ifdef __cplusplus
449 450 }
450 451 #endif
451 452
452 453 #endif /* _SYS_DDI_INTR_IMPL_H */
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