1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21 /*
22 * Copyright 2010 Sun Microsystems, Inc. All rights reserved.
23 * Use is subject to license terms.
24 */
25 /*
26 * Copyright 2012 Garrett D'Amore <garrett@damore.org>. All rights reserved.
27 */
28
29 /*
30 * PCI to PCI bus bridge nexus driver
31 */
32
33 #include <sys/conf.h>
34 #include <sys/kmem.h>
35 #include <sys/debug.h>
36 #include <sys/modctl.h>
37 #include <sys/autoconf.h>
38 #include <sys/ddi_impldefs.h>
39 #include <sys/pci.h>
40 #include <sys/pci_impl.h>
41 #include <sys/pcie_impl.h>
42 #include <sys/ddi.h>
43 #include <sys/sunddi.h>
44 #include <sys/sunndi.h>
45 #include <sys/ddifm.h>
46 #include <sys/ndifm.h>
47 #include <sys/fm/protocol.h>
48 #include <sys/hotplug/pci/pcie_hp.h>
49 #include <sys/hotplug/pci/pcihp.h>
50 #include <sys/pci_intr_lib.h>
51 #include <sys/psm.h>
52 #include <sys/pci_cap.h>
53
54 /*
55 * The variable controls the default setting of the command register
56 * for pci devices. See ppb_initchild() for details.
57 */
58 static ushort_t ppb_command_default = PCI_COMM_ME | PCI_COMM_MAE | PCI_COMM_IO;
59
60
61 static int ppb_bus_map(dev_info_t *, dev_info_t *, ddi_map_req_t *,
62 off_t, off_t, caddr_t *);
63 static int ppb_ctlops(dev_info_t *, dev_info_t *, ddi_ctl_enum_t,
64 void *, void *);
65 static int ppb_fm_init(dev_info_t *, dev_info_t *, int,
66 ddi_iblock_cookie_t *);
67 static int ppb_fm_callback(dev_info_t *, ddi_fm_error_t *, const void *);
68 static int ppb_intr_ops(dev_info_t *, dev_info_t *, ddi_intr_op_t,
69 ddi_intr_handle_impl_t *, void *);
70
71 /*
72 * ppb_support_msi: Flag that controls MSI support across P2P Bridges.
73 * By default, MSI is not supported except for special cases like HT
74 * bridges/tunnels that have HT MSI mapping enabled.
75 *
76 * However, MSI support behavior can be patched on a system by changing
77 * the value of this flag as shown below:-
78 * 0 = default value, MSI is allowed by this driver for special cases
79 * 1 = MSI supported without any checks for this driver
80 * -1 = MSI not supported at all
81 */
82 int ppb_support_msi = 0;
83
84 /*
85 * Controls the usage of the Hypertransport MSI mapping capability
86 * 0 = default value, leave hardware function as it is
87 * 1 = always enable HT MSI mapping
88 * -1 = always disable HT MSI mapping
89 */
90 int ppb_support_ht_msimap = 0;
91
92 struct bus_ops ppb_bus_ops = {
93 BUSO_REV,
94 ppb_bus_map,
95 0,
96 0,
97 0,
98 i_ddi_map_fault,
99 0,
100 ddi_dma_allochdl,
101 ddi_dma_freehdl,
102 ddi_dma_bindhdl,
103 ddi_dma_unbindhdl,
104 ddi_dma_flush,
105 ddi_dma_win,
106 ddi_dma_mctl,
107 ppb_ctlops,
108 ddi_bus_prop_op,
109 0, /* (*bus_get_eventcookie)(); */
110 0, /* (*bus_add_eventcall)(); */
111 0, /* (*bus_remove_eventcall)(); */
112 0, /* (*bus_post_event)(); */
113 0, /* (*bus_intr_ctl)(); */
114 0, /* (*bus_config)(); */
115 0, /* (*bus_unconfig)(); */
116 ppb_fm_init, /* (*bus_fm_init)(); */
117 NULL, /* (*bus_fm_fini)(); */
118 NULL, /* (*bus_fm_access_enter)(); */
119 NULL, /* (*bus_fm_access_exit)(); */
120 NULL, /* (*bus_power)(); */
121 ppb_intr_ops, /* (*bus_intr_op)(); */
122 pcie_hp_common_ops /* (*bus_hp_op)(); */
123 };
124
125 /*
126 * The goal here is to leverage off of the pcihp.c source without making
127 * changes to it. Call into it's cb_ops directly if needed.
128 */
129 static int ppb_open(dev_t *, int, int, cred_t *);
130 static int ppb_close(dev_t, int, int, cred_t *);
131 static int ppb_ioctl(dev_t, int, intptr_t, int, cred_t *, int *);
132 static int ppb_prop_op(dev_t, dev_info_t *, ddi_prop_op_t, int, char *,
133 caddr_t, int *);
134 static int ppb_info(dev_info_t *, ddi_info_cmd_t, void *, void **);
135 static void ppb_peekpoke_cb(dev_info_t *, ddi_fm_error_t *);
136
137 struct cb_ops ppb_cb_ops = {
138 ppb_open, /* open */
139 ppb_close, /* close */
140 nodev, /* strategy */
141 nodev, /* print */
142 nodev, /* dump */
143 nodev, /* read */
144 nodev, /* write */
145 ppb_ioctl, /* ioctl */
146 nodev, /* devmap */
147 nodev, /* mmap */
148 nodev, /* segmap */
149 nochpoll, /* poll */
150 ppb_prop_op, /* cb_prop_op */
151 NULL, /* streamtab */
152 D_NEW | D_MP | D_HOTPLUG, /* Driver compatibility flag */
153 CB_REV, /* rev */
154 nodev, /* int (*cb_aread)() */
155 nodev /* int (*cb_awrite)() */
156 };
157
158
159 static int ppb_probe(dev_info_t *);
160 static int ppb_attach(dev_info_t *devi, ddi_attach_cmd_t cmd);
161 static int ppb_detach(dev_info_t *devi, ddi_detach_cmd_t cmd);
162
163 struct dev_ops ppb_ops = {
164 DEVO_REV, /* devo_rev */
165 0, /* refcnt */
166 ppb_info, /* info */
167 nulldev, /* identify */
168 ppb_probe, /* probe */
169 ppb_attach, /* attach */
170 ppb_detach, /* detach */
171 nulldev, /* reset */
172 &ppb_cb_ops, /* driver operations */
173 &ppb_bus_ops, /* bus operations */
174 NULL, /* power */
175 ddi_quiesce_not_needed, /* quiesce */
176 };
177
178 /*
179 * Module linkage information for the kernel.
180 */
181
182 static struct modldrv modldrv = {
183 &mod_driverops, /* Type of module */
184 "Standard PCI to PCI bridge nexus driver",
185 &ppb_ops, /* driver ops */
186 };
187
188 static struct modlinkage modlinkage = {
189 MODREV_1,
190 { (void *)&modldrv, NULL }
191 };
192
193 /*
194 * soft state pointer and structure template:
195 */
196 static void *ppb_state;
197
198 typedef struct {
199 dev_info_t *dip;
200 int ppb_fmcap;
201 ddi_iblock_cookie_t ppb_fm_ibc;
202 kmutex_t ppb_mutex;
203 kmutex_t ppb_peek_poke_mutex;
204 kmutex_t ppb_err_mutex;
205
206 /*
207 * cpr support:
208 */
209 uint_t config_state_index;
210 struct {
211 dev_info_t *dip;
212 ushort_t command;
213 uchar_t cache_line_size;
214 uchar_t latency_timer;
215 uchar_t header_type;
216 uchar_t sec_latency_timer;
217 ushort_t bridge_control;
218 } config_state[PCI_MAX_CHILDREN];
219
220 uint16_t parent_bus;
221 } ppb_devstate_t;
222
223
224 /*
225 * forward function declarations:
226 */
227 static void ppb_removechild(dev_info_t *);
228 static int ppb_initchild(dev_info_t *child);
229 static void ppb_save_config_regs(ppb_devstate_t *ppb_p);
230 static void ppb_restore_config_regs(ppb_devstate_t *ppb_p);
231 static boolean_t ppb_ht_msimap_check(ddi_acc_handle_t cfg_hdl);
232 static int ppb_ht_msimap_set(ddi_acc_handle_t cfg_hdl, int cmd);
233
234 /*
235 * for <cmd> in ppb_ht_msimap_set
236 */
237 #define HT_MSIMAP_ENABLE 1
238 #define HT_MSIMAP_DISABLE 0
239
240
241 int
242 _init(void)
243 {
244 int e;
245
246 if ((e = ddi_soft_state_init(&ppb_state, sizeof (ppb_devstate_t),
247 1)) == 0 && (e = mod_install(&modlinkage)) != 0)
248 ddi_soft_state_fini(&ppb_state);
249 return (e);
250 }
251
252 int
253 _fini(void)
254 {
255 int e;
256
257 if ((e = mod_remove(&modlinkage)) == 0)
258 ddi_soft_state_fini(&ppb_state);
259 return (e);
260 }
261
262 int
263 _info(struct modinfo *modinfop)
264 {
265 return (mod_info(&modlinkage, modinfop));
266 }
267
268 /*ARGSUSED*/
269 static int
270 ppb_probe(dev_info_t *devi)
271 {
272 return (DDI_PROBE_SUCCESS);
273 }
274
275 /*ARGSUSED*/
276 static int
277 ppb_attach(dev_info_t *devi, ddi_attach_cmd_t cmd)
278 {
279 dev_info_t *root = ddi_root_node();
280 int instance;
281 ppb_devstate_t *ppb;
282 dev_info_t *pdip;
283 ddi_acc_handle_t config_handle;
284 char *bus;
285 int ret;
286
287 switch (cmd) {
288 case DDI_ATTACH:
289
290 /*
291 * Make sure the "device_type" property exists.
292 */
293 (void) ddi_prop_update_string(DDI_DEV_T_NONE, devi,
294 "device_type", "pci");
295
296 /*
297 * Allocate and get soft state structure.
298 */
299 instance = ddi_get_instance(devi);
300 if (ddi_soft_state_zalloc(ppb_state, instance) != DDI_SUCCESS)
301 return (DDI_FAILURE);
302 ppb = ddi_get_soft_state(ppb_state, instance);
303 ppb->dip = devi;
304
305 /*
306 * don't enable ereports if immediate child of npe
307 */
308 if (strcmp(ddi_driver_name(ddi_get_parent(devi)), "npe") == 0)
309 ppb->ppb_fmcap = DDI_FM_ERRCB_CAPABLE |
310 DDI_FM_ACCCHK_CAPABLE | DDI_FM_DMACHK_CAPABLE;
311 else
312 ppb->ppb_fmcap = DDI_FM_EREPORT_CAPABLE |
313 DDI_FM_ERRCB_CAPABLE | DDI_FM_ACCCHK_CAPABLE |
314 DDI_FM_DMACHK_CAPABLE;
315
316 ddi_fm_init(devi, &ppb->ppb_fmcap, &ppb->ppb_fm_ibc);
317 mutex_init(&ppb->ppb_mutex, NULL, MUTEX_DRIVER, NULL);
318 mutex_init(&ppb->ppb_err_mutex, NULL, MUTEX_DRIVER,
319 (void *)ppb->ppb_fm_ibc);
320 mutex_init(&ppb->ppb_peek_poke_mutex, NULL, MUTEX_DRIVER,
321 (void *)ppb->ppb_fm_ibc);
322
323 if (ppb->ppb_fmcap & (DDI_FM_ERRCB_CAPABLE |
324 DDI_FM_EREPORT_CAPABLE))
325 pci_ereport_setup(devi);
326 if (ppb->ppb_fmcap & DDI_FM_ERRCB_CAPABLE)
327 ddi_fm_handler_register(devi, ppb_fm_callback, NULL);
328
329 if (pci_config_setup(devi, &config_handle) != DDI_SUCCESS) {
330 if (ppb->ppb_fmcap & DDI_FM_ERRCB_CAPABLE)
331 ddi_fm_handler_unregister(devi);
332 if (ppb->ppb_fmcap & (DDI_FM_ERRCB_CAPABLE |
333 DDI_FM_EREPORT_CAPABLE))
334 pci_ereport_teardown(devi);
335 ddi_fm_fini(devi);
336 ddi_soft_state_free(ppb_state, instance);
337 return (DDI_FAILURE);
338 }
339
340 ppb->parent_bus = PCIE_PCIECAP_DEV_TYPE_PCI_PSEUDO;
341 for (pdip = ddi_get_parent(devi); pdip && (pdip != root) &&
342 (ppb->parent_bus != PCIE_PCIECAP_DEV_TYPE_PCIE_DEV);
343 pdip = ddi_get_parent(pdip)) {
344 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, pdip,
345 DDI_PROP_DONTPASS, "device_type", &bus) !=
346 DDI_PROP_SUCCESS)
347 break;
348
349 if (strcmp(bus, "pciex") == 0)
350 ppb->parent_bus =
351 PCIE_PCIECAP_DEV_TYPE_PCIE_DEV;
352
353 ddi_prop_free(bus);
354 }
355
356 if (ppb_support_ht_msimap == 1)
357 (void) ppb_ht_msimap_set(config_handle,
358 HT_MSIMAP_ENABLE);
359 else if (ppb_support_ht_msimap == -1)
360 (void) ppb_ht_msimap_set(config_handle,
361 HT_MSIMAP_DISABLE);
362
363 pci_config_teardown(&config_handle);
364
365 /*
366 * Initialize hotplug support on this bus.
367 */
368 if (ppb->parent_bus == PCIE_PCIECAP_DEV_TYPE_PCIE_DEV)
369 ret = pcie_init(devi, NULL);
370 else
371 ret = pcihp_init(devi);
372
373 if (ret != DDI_SUCCESS) {
374 cmn_err(CE_WARN,
375 "pci: Failed to setup hotplug framework");
376 (void) ppb_detach(devi, DDI_DETACH);
377 return (ret);
378 }
379
380 ddi_report_dev(devi);
381 return (DDI_SUCCESS);
382
383 case DDI_RESUME:
384
385 /*
386 * Get the soft state structure for the bridge.
387 */
388 ppb = ddi_get_soft_state(ppb_state, ddi_get_instance(devi));
389 ppb_restore_config_regs(ppb);
390 return (DDI_SUCCESS);
391
392 default:
393 break;
394 }
395 return (DDI_FAILURE);
396 }
397
398 /*ARGSUSED*/
399 static int
400 ppb_detach(dev_info_t *devi, ddi_detach_cmd_t cmd)
401 {
402 ppb_devstate_t *ppb;
403 int ret;
404
405 switch (cmd) {
406 case DDI_DETACH:
407 (void) ddi_prop_remove(DDI_DEV_T_NONE, devi, "device_type");
408
409 ppb = ddi_get_soft_state(ppb_state, ddi_get_instance(devi));
410 if (ppb->ppb_fmcap & DDI_FM_ERRCB_CAPABLE)
411 ddi_fm_handler_unregister(devi);
412 if (ppb->ppb_fmcap & (DDI_FM_ERRCB_CAPABLE |
413 DDI_FM_EREPORT_CAPABLE))
414 pci_ereport_teardown(devi);
415
416 /*
417 * Uninitialize hotplug support on this bus.
418 */
419 ret = (ppb->parent_bus == PCIE_PCIECAP_DEV_TYPE_PCIE_DEV) ?
420 pcie_uninit(devi) : pcihp_uninit(devi);
421 if (ret != DDI_SUCCESS)
422 return (DDI_FAILURE);
423
424 mutex_destroy(&ppb->ppb_peek_poke_mutex);
425 mutex_destroy(&ppb->ppb_err_mutex);
426 mutex_destroy(&ppb->ppb_mutex);
427 ddi_fm_fini(devi);
428
429 /*
430 * And finally free the per-pci soft state.
431 */
432 ddi_soft_state_free(ppb_state, ddi_get_instance(devi));
433
434 return (DDI_SUCCESS);
435
436 case DDI_SUSPEND:
437 ppb = ddi_get_soft_state(ppb_state, ddi_get_instance(devi));
438 ppb_save_config_regs(ppb);
439 return (DDI_SUCCESS);
440
441 default:
442 break;
443 }
444 return (DDI_FAILURE);
445 }
446
447 /*ARGSUSED*/
448 static int
449 ppb_bus_map(dev_info_t *dip, dev_info_t *rdip, ddi_map_req_t *mp,
450 off_t offset, off_t len, caddr_t *vaddrp)
451 {
452 dev_info_t *pdip;
453 ppb_devstate_t *ppb = ddi_get_soft_state(ppb_state,
454 ddi_get_instance(dip));
455
456 if (strcmp(ddi_driver_name(ddi_get_parent(dip)), "npe") == 0 &&
457 mp->map_handlep != NULL) {
458 ddi_acc_impl_t *hdlp =
459 (ddi_acc_impl_t *)(mp->map_handlep)->ah_platform_private;
460 hdlp->ahi_err_mutexp = &ppb->ppb_err_mutex;
461 hdlp->ahi_peekpoke_mutexp = &ppb->ppb_peek_poke_mutex;
462 hdlp->ahi_scan_dip = dip;
463 hdlp->ahi_scan = ppb_peekpoke_cb;
464 }
465 pdip = (dev_info_t *)DEVI(dip)->devi_parent;
466 return ((DEVI(pdip)->devi_ops->devo_bus_ops->bus_map)(pdip,
467 rdip, mp, offset, len, vaddrp));
468 }
469
470 /*ARGSUSED*/
471 static int
472 ppb_ctlops(dev_info_t *dip, dev_info_t *rdip,
473 ddi_ctl_enum_t ctlop, void *arg, void *result)
474 {
475 pci_regspec_t *drv_regp;
476 int reglen;
477 int rn;
478 int totreg;
479 ppb_devstate_t *ppb = ddi_get_soft_state(ppb_state,
480 ddi_get_instance(dip));
481 struct detachspec *dsp;
482 struct attachspec *asp;
483
484 switch (ctlop) {
485 case DDI_CTLOPS_REPORTDEV:
486 if (rdip == (dev_info_t *)0)
487 return (DDI_FAILURE);
488 cmn_err(CE_CONT, "?PCI-device: %s@%s, %s%d\n",
489 ddi_node_name(rdip), ddi_get_name_addr(rdip),
490 ddi_driver_name(rdip),
491 ddi_get_instance(rdip));
492 return (DDI_SUCCESS);
493
494 case DDI_CTLOPS_INITCHILD:
495 return (ppb_initchild((dev_info_t *)arg));
496
497 case DDI_CTLOPS_UNINITCHILD:
498 ppb_removechild((dev_info_t *)arg);
499 return (DDI_SUCCESS);
500
501 case DDI_CTLOPS_SIDDEV:
502 return (DDI_SUCCESS);
503
504 case DDI_CTLOPS_REGSIZE:
505 case DDI_CTLOPS_NREGS:
506 if (rdip == (dev_info_t *)0)
507 return (DDI_FAILURE);
508 break;
509
510 /* X86 systems support PME wakeup from suspend */
511 case DDI_CTLOPS_ATTACH:
512 if (!pcie_is_child(dip, rdip))
513 return (DDI_SUCCESS);
514
515 asp = (struct attachspec *)arg;
516 if ((ppb->parent_bus == PCIE_PCIECAP_DEV_TYPE_PCIE_DEV) &&
517 (asp->when == DDI_POST) && (asp->result == DDI_SUCCESS))
518 pf_init(rdip, (void *)ppb->ppb_fm_ibc, asp->cmd);
519
520 if (asp->cmd == DDI_RESUME && asp->when == DDI_PRE)
521 if (pci_pre_resume(rdip) != DDI_SUCCESS)
522 return (DDI_FAILURE);
523
524 return (DDI_SUCCESS);
525
526 case DDI_CTLOPS_DETACH:
527 if (!pcie_is_child(dip, rdip))
528 return (DDI_SUCCESS);
529
530 dsp = (struct detachspec *)arg;
531 if ((ppb->parent_bus == PCIE_PCIECAP_DEV_TYPE_PCIE_DEV) &&
532 (dsp->when == DDI_PRE))
533 pf_fini(rdip, dsp->cmd);
534
535 if (dsp->cmd == DDI_SUSPEND && dsp->when == DDI_POST)
536 if (pci_post_suspend(rdip) != DDI_SUCCESS)
537 return (DDI_FAILURE);
538
539 return (DDI_SUCCESS);
540
541 case DDI_CTLOPS_PEEK:
542 case DDI_CTLOPS_POKE:
543 if (strcmp(ddi_driver_name(ddi_get_parent(dip)), "npe") != 0)
544 return (ddi_ctlops(dip, rdip, ctlop, arg, result));
545 return (pci_peekpoke_check(dip, rdip, ctlop, arg, result,
546 ddi_ctlops, &ppb->ppb_err_mutex,
547 &ppb->ppb_peek_poke_mutex, ppb_peekpoke_cb));
548
549 default:
550 return (ddi_ctlops(dip, rdip, ctlop, arg, result));
551 }
552
553 *(int *)result = 0;
554 if (ddi_getlongprop(DDI_DEV_T_ANY, rdip,
555 DDI_PROP_DONTPASS | DDI_PROP_CANSLEEP, "reg",
556 (caddr_t)&drv_regp, ®len) != DDI_SUCCESS)
557 return (DDI_FAILURE);
558
559 totreg = reglen / sizeof (pci_regspec_t);
560 if (ctlop == DDI_CTLOPS_NREGS)
561 *(int *)result = totreg;
562 else if (ctlop == DDI_CTLOPS_REGSIZE) {
563 rn = *(int *)arg;
564 if (rn >= totreg) {
565 kmem_free(drv_regp, reglen);
566 return (DDI_FAILURE);
567 }
568 *(off_t *)result = drv_regp[rn].pci_size_low;
569 }
570
571 kmem_free(drv_regp, reglen);
572 return (DDI_SUCCESS);
573 }
574
575 static int
576 ppb_name_child(dev_info_t *child, char *name, int namelen)
577 {
578 pci_regspec_t *pci_rp;
579 uint_t slot, func;
580 char **unit_addr;
581 uint_t n;
582
583 /*
584 * For .conf nodes, use unit-address property as name
585 */
586 if (ndi_dev_is_persistent_node(child) == 0) {
587 if (ddi_prop_lookup_string_array(DDI_DEV_T_ANY, child,
588 DDI_PROP_DONTPASS, "unit-address", &unit_addr, &n) !=
589 DDI_PROP_SUCCESS) {
590 cmn_err(CE_WARN,
591 "cannot find unit-address in %s.conf",
592 ddi_driver_name(child));
593 return (DDI_FAILURE);
594 }
595 if (n != 1 || *unit_addr == NULL || **unit_addr == 0) {
596 cmn_err(CE_WARN, "unit-address property in %s.conf"
597 " not well-formed", ddi_driver_name(child));
598 ddi_prop_free(unit_addr);
599 return (DDI_SUCCESS);
600 }
601 (void) snprintf(name, namelen, "%s", *unit_addr);
602 ddi_prop_free(unit_addr);
603 return (DDI_SUCCESS);
604 }
605
606 /* get child "reg" property */
607 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, child,
608 DDI_PROP_DONTPASS, "reg", (int **)&pci_rp, &n) != DDI_SUCCESS) {
609 return (DDI_FAILURE);
610 }
611
612 /* copy the device identifications */
613 slot = PCI_REG_DEV_G(pci_rp->pci_phys_hi);
614 func = PCI_REG_FUNC_G(pci_rp->pci_phys_hi);
615
616 if (func != 0)
617 (void) snprintf(name, namelen, "%x,%x", slot, func);
618 else
619 (void) snprintf(name, namelen, "%x", slot);
620
621 ddi_prop_free(pci_rp);
622 return (DDI_SUCCESS);
623 }
624
625 static int
626 ppb_initchild(dev_info_t *child)
627 {
628 struct ddi_parent_private_data *pdptr;
629 ppb_devstate_t *ppb;
630 char name[MAXNAMELEN];
631 ddi_acc_handle_t config_handle;
632 ushort_t command_preserve, command;
633
634 ppb = (ppb_devstate_t *)ddi_get_soft_state(ppb_state,
635 ddi_get_instance(ddi_get_parent(child)));
636
637 if (ppb_name_child(child, name, MAXNAMELEN) != DDI_SUCCESS)
638 return (DDI_FAILURE);
639 ddi_set_name_addr(child, name);
640
641 /*
642 * Pseudo nodes indicate a prototype node with per-instance
643 * properties to be merged into the real h/w device node.
644 * The interpretation of the unit-address is DD[,F]
645 * where DD is the device id and F is the function.
646 */
647 if (ndi_dev_is_persistent_node(child) == 0) {
648 extern int pci_allow_pseudo_children;
649
650 ddi_set_parent_data(child, NULL);
651
652 /*
653 * Try to merge the properties from this prototype
654 * node into real h/w nodes.
655 */
656 if (ndi_merge_node(child, ppb_name_child) == DDI_SUCCESS) {
657 /*
658 * Merged ok - return failure to remove the node.
659 */
660 ddi_set_name_addr(child, NULL);
661 return (DDI_FAILURE);
662 }
663
664 /* workaround for ddivs to run under PCI */
665 if (pci_allow_pseudo_children)
666 return (DDI_SUCCESS);
667
668 /*
669 * The child was not merged into a h/w node,
670 * but there's not much we can do with it other
671 * than return failure to cause the node to be removed.
672 */
673 cmn_err(CE_WARN, "!%s@%s: %s.conf properties not merged",
674 ddi_driver_name(child), ddi_get_name_addr(child),
675 ddi_driver_name(child));
676 ddi_set_name_addr(child, NULL);
677 return (DDI_NOT_WELL_FORMED);
678 }
679
680 ddi_set_parent_data(child, NULL);
681
682 /*
683 * PCIe FMA specific
684 *
685 * Note: parent_data for parent is created only if this is PCI-E
686 * platform, for which, SG take a different route to handle device
687 * errors.
688 */
689 if (ppb->parent_bus == PCIE_PCIECAP_DEV_TYPE_PCIE_DEV) {
690 if (pcie_init_cfghdl(child) != DDI_SUCCESS)
691 return (DDI_FAILURE);
692 pcie_init_dom(child);
693 }
694
695 /* transfer select properties from PROM to kernel */
696 if (ddi_getprop(DDI_DEV_T_NONE, child, DDI_PROP_DONTPASS,
697 "interrupts", -1) != -1) {
698 pdptr = kmem_zalloc((sizeof (struct ddi_parent_private_data) +
699 sizeof (struct intrspec)), KM_SLEEP);
700 pdptr->par_intr = (struct intrspec *)(pdptr + 1);
701 pdptr->par_nintr = 1;
702 ddi_set_parent_data(child, pdptr);
703 } else
704 ddi_set_parent_data(child, NULL);
705
706 if (pci_config_setup(child, &config_handle) != DDI_SUCCESS) {
707 pcie_fini_dom(child);
708 return (DDI_FAILURE);
709 }
710
711 /*
712 * Support for the "command-preserve" property.
713 */
714 command_preserve = ddi_prop_get_int(DDI_DEV_T_ANY, child,
715 DDI_PROP_DONTPASS, "command-preserve", 0);
716 command = pci_config_get16(config_handle, PCI_CONF_COMM);
717 command &= (command_preserve | PCI_COMM_BACK2BACK_ENAB);
718 command |= (ppb_command_default & ~command_preserve);
719 pci_config_put16(config_handle, PCI_CONF_COMM, command);
720
721 pci_config_teardown(&config_handle);
722 return (DDI_SUCCESS);
723 }
724
725 static void
726 ppb_removechild(dev_info_t *dip)
727 {
728 struct ddi_parent_private_data *pdptr;
729 ppb_devstate_t *ppb;
730
731 ppb = (ppb_devstate_t *)ddi_get_soft_state(ppb_state,
732 ddi_get_instance(ddi_get_parent(dip)));
733
734 if (ppb->parent_bus == PCIE_PCIECAP_DEV_TYPE_PCIE_DEV) {
735 pcie_fini_dom(dip);
736 pcie_fini_cfghdl(dip);
737 } else if ((pdptr = ddi_get_parent_data(dip)) != NULL) {
738 kmem_free(pdptr, (sizeof (*pdptr) + sizeof (struct intrspec)));
739 ddi_set_parent_data(dip, NULL);
740 }
741 ddi_set_name_addr(dip, NULL);
742
743 /*
744 * Strip the node to properly convert it back to prototype form
745 */
746 ddi_remove_minor_node(dip, NULL);
747
748 impl_rem_dev_props(dip);
749 }
750
751 /*
752 * ppb_save_config_regs
753 *
754 * This routine saves the state of the configuration registers of all
755 * the child nodes of each PBM.
756 *
757 * used by: ppb_detach() on suspends
758 *
759 * return value: none
760 */
761 static void
762 ppb_save_config_regs(ppb_devstate_t *ppb_p)
763 {
764 int i;
765 dev_info_t *dip;
766 ddi_acc_handle_t config_handle;
767
768 for (i = 0, dip = ddi_get_child(ppb_p->dip); dip != NULL;
769 i++, dip = ddi_get_next_sibling(dip)) {
770
771 if (pci_config_setup(dip, &config_handle) != DDI_SUCCESS) {
772 cmn_err(CE_WARN, "%s%d: can't config space for %s%d\n",
773 ddi_driver_name(ppb_p->dip),
774 ddi_get_instance(ppb_p->dip),
775 ddi_driver_name(dip),
776 ddi_get_instance(dip));
777 continue;
778 }
779
780 ppb_p->config_state[i].dip = dip;
781 ppb_p->config_state[i].command =
782 pci_config_get16(config_handle, PCI_CONF_COMM);
783 pci_config_teardown(&config_handle);
784 }
785 ppb_p->config_state_index = i;
786 }
787
788
789 /*
790 * ppb_restore_config_regs
791 *
792 * This routine restores the state of the configuration registers of all
793 * the child nodes of each PBM.
794 *
795 * used by: ppb_attach() on resume
796 *
797 * return value: none
798 */
799 static void
800 ppb_restore_config_regs(ppb_devstate_t *ppb_p)
801 {
802 int i;
803 dev_info_t *dip;
804 ddi_acc_handle_t config_handle;
805
806 for (i = 0; i < ppb_p->config_state_index; i++) {
807 dip = ppb_p->config_state[i].dip;
808 if (pci_config_setup(dip, &config_handle) != DDI_SUCCESS) {
809 cmn_err(CE_WARN, "%s%d: can't config space for %s%d\n",
810 ddi_driver_name(ppb_p->dip),
811 ddi_get_instance(ppb_p->dip),
812 ddi_driver_name(dip),
813 ddi_get_instance(dip));
814 continue;
815 }
816 pci_config_put16(config_handle, PCI_CONF_COMM,
817 ppb_p->config_state[i].command);
818 pci_config_teardown(&config_handle);
819 }
820 }
821
822
823 static boolean_t
824 ppb_ht_msimap_check(ddi_acc_handle_t cfg_hdl)
825 {
826 uint16_t ptr;
827
828 if (pci_htcap_locate(cfg_hdl,
829 PCI_HTCAP_TYPE_MASK | PCI_HTCAP_MSIMAP_ENABLE_MASK,
830 PCI_HTCAP_MSIMAP_TYPE | PCI_HTCAP_MSIMAP_ENABLE, &ptr) !=
831 DDI_SUCCESS)
832 return (B_FALSE);
833
834 return (B_TRUE);
835 }
836
837
838 static int
839 ppb_ht_msimap_set(ddi_acc_handle_t cfg_hdl, int cmd)
840 {
841 uint16_t ptr;
842 uint16_t reg;
843
844 if (pci_htcap_locate(cfg_hdl, PCI_HTCAP_TYPE_MASK,
845 PCI_HTCAP_MSIMAP_TYPE, &ptr) != DDI_SUCCESS)
846 return (0);
847
848 reg = pci_config_get16(cfg_hdl, ptr + PCI_CAP_ID_REGS_OFF);
849 switch (cmd) {
850 case HT_MSIMAP_ENABLE:
851 reg |= PCI_HTCAP_MSIMAP_ENABLE;
852 break;
853 case HT_MSIMAP_DISABLE:
854 default:
855 reg &= ~(uint16_t)PCI_HTCAP_MSIMAP_ENABLE;
856 }
857
858 pci_config_put16(cfg_hdl, ptr + PCI_CAP_ID_REGS_OFF, reg);
859 return (1);
860 }
861
862
863 /*
864 * intercept certain interrupt services to handle special cases
865 */
866 static int
867 ppb_intr_ops(dev_info_t *pdip, dev_info_t *rdip, ddi_intr_op_t intr_op,
868 ddi_intr_handle_impl_t *hdlp, void *result)
869 {
870 ddi_acc_handle_t cfg_hdl;
871 int rv = DDI_SUCCESS;
872
873 if (intr_op != DDI_INTROP_SUPPORTED_TYPES)
874 return (i_ddi_intr_ops(pdip, rdip, intr_op, hdlp, result));
875
876 DDI_INTR_NEXDBG((CE_CONT,
877 "ppb_intr_ops: pdip 0x%p, rdip 0x%p, op %x handle 0x%p\n",
878 (void *)pdip, (void *)rdip, intr_op, (void *)hdlp));
879
880 /* Fixed interrupt is supported by default */
881 *(int *)result = DDI_INTR_TYPE_FIXED;
882
883 if (ppb_support_msi == -1) {
884 DDI_INTR_NEXDBG((CE_CONT,
885 "ppb_intr_ops: MSI is not allowed\n"));
886 goto OUT;
887 }
888
889 if (ppb_support_msi == 1) {
890 DDI_INTR_NEXDBG((CE_CONT,
891 "ppb_intr_ops: MSI is always allowed\n"));
892 rv = i_ddi_intr_ops(pdip, rdip, intr_op, hdlp, result);
893 goto OUT;
894 }
895
896 if (pci_config_setup(pdip, &cfg_hdl) != DDI_SUCCESS) {
897 DDI_INTR_NEXDBG((CE_CONT,
898 "ppb_intr_ops: pci_config_setup() failed\n"));
899 goto OUT;
900 }
901
902 /*
903 * check for hypertransport msi mapping capability
904 */
905 if (ppb_ht_msimap_check(cfg_hdl)) {
906 DDI_INTR_NEXDBG((CE_CONT,
907 "ppb_intr_ops: HT MSI mapping enabled\n"));
908 rv = i_ddi_intr_ops(pdip, rdip, intr_op, hdlp, result);
909 }
910
911 /*
912 * if we add failure conditions after pci_config_setup, move this to
913 * OUT and use an extra flag to indicate the need to teardown cfg_hdl
914 */
915 pci_config_teardown(&cfg_hdl);
916
917 OUT:
918 DDI_INTR_NEXDBG((CE_CONT,
919 "ppb_intr_ops: rdip 0x%p, returns supported types: 0x%x\n",
920 (void *)rdip, *(int *)result));
921 return (rv);
922 }
923
924 /* ARGSUSED */
925 static int
926 ppb_open(dev_t *devp, int flags, int otyp, cred_t *credp)
927 {
928 int instance = PCI_MINOR_NUM_TO_INSTANCE(getminor(*devp));
929 ppb_devstate_t *ppb_p = ddi_get_soft_state(ppb_state, instance);
930 int rv;
931
932 if (ppb_p == NULL)
933 return (ENXIO);
934
935 /*
936 * Ioctls will be handled by PCI Express framework for all
937 * PCIe platforms
938 */
939 if (ppb_p->parent_bus == PCIE_PCIECAP_DEV_TYPE_PCIE_DEV) {
940 mutex_enter(&ppb_p->ppb_mutex);
941 rv = pcie_open(ppb_p->dip, devp, flags, otyp, credp);
942 mutex_exit(&ppb_p->ppb_mutex);
943 return (rv);
944 }
945
946 return ((pcihp_get_cb_ops())->cb_open(devp, flags, otyp, credp));
947 }
948
949 /* ARGSUSED */
950 static int
951 ppb_close(dev_t dev, int flags, int otyp, cred_t *credp)
952 {
953 int instance = PCI_MINOR_NUM_TO_INSTANCE(getminor(dev));
954 ppb_devstate_t *ppb_p = ddi_get_soft_state(ppb_state, instance);
955 int rv;
956
957 if (ppb_p == NULL)
958 return (ENXIO);
959
960 mutex_enter(&ppb_p->ppb_mutex);
961 /*
962 * Ioctls will be handled by PCI Express framework for all
963 * PCIe platforms
964 */
965 if (ppb_p->parent_bus == PCIE_PCIECAP_DEV_TYPE_PCIE_DEV) {
966 rv = pcie_close(ppb_p->dip, dev, flags, otyp, credp);
967 mutex_exit(&ppb_p->ppb_mutex);
968 return (rv);
969 }
970
971 mutex_exit(&ppb_p->ppb_mutex);
972 return ((pcihp_get_cb_ops())->cb_close(dev, flags, otyp, credp));
973 }
974
975 /*
976 * ppb_ioctl: devctl hotplug controls
977 */
978 /* ARGSUSED */
979 static int
980 ppb_ioctl(dev_t dev, int cmd, intptr_t arg, int mode, cred_t *credp,
981 int *rvalp)
982 {
983 int instance = PCI_MINOR_NUM_TO_INSTANCE(getminor(dev));
984 ppb_devstate_t *ppb_p = ddi_get_soft_state(ppb_state, instance);
985
986 if (ppb_p == NULL)
987 return (ENXIO);
988
989 /*
990 * Ioctls will be handled by PCI Express framework for all
991 * PCIe platforms
992 */
993 if (ppb_p->parent_bus == PCIE_PCIECAP_DEV_TYPE_PCIE_DEV)
994 return (pcie_ioctl(ppb_p->dip, dev, cmd, arg, mode, credp,
995 rvalp));
996
997 return ((pcihp_get_cb_ops())->cb_ioctl(dev, cmd, arg, mode, credp,
998 rvalp));
999 }
1000
1001 static int
1002 ppb_prop_op(dev_t dev, dev_info_t *dip, ddi_prop_op_t prop_op, int flags,
1003 char *name, caddr_t valuep, int *lengthp)
1004 {
1005 int instance = PCI_MINOR_NUM_TO_INSTANCE(getminor(dev));
1006 ppb_devstate_t *ppb_p = ddi_get_soft_state(ppb_state, instance);
1007
1008 if (ppb_p == NULL)
1009 return (ENXIO);
1010
1011 if (ppb_p->parent_bus == PCIE_PCIECAP_DEV_TYPE_PCIE_DEV)
1012 return (pcie_prop_op(dev, dip, prop_op, flags, name,
1013 valuep, lengthp));
1014
1015 return ((pcihp_get_cb_ops())->cb_prop_op(dev, dip, prop_op, flags,
1016 name, valuep, lengthp));
1017 }
1018
1019 static int
1020 ppb_info(dev_info_t *dip, ddi_info_cmd_t cmd, void *arg, void **result)
1021 {
1022 minor_t minor = getminor((dev_t)arg);
1023 int instance = PCI_MINOR_NUM_TO_INSTANCE(minor);
1024 ppb_devstate_t *ppb_p = ddi_get_soft_state(ppb_state, instance);
1025
1026 if (ppb_p == NULL)
1027 return (DDI_FAILURE);
1028
1029 if (ppb_p->parent_bus != PCIE_PCIECAP_DEV_TYPE_PCIE_DEV)
1030 return (pcihp_info(dip, cmd, arg, result));
1031
1032 switch (cmd) {
1033 default:
1034 return (DDI_FAILURE);
1035
1036 case DDI_INFO_DEVT2INSTANCE:
1037 *result = (void *)(uintptr_t)instance;
1038 return (DDI_SUCCESS);
1039
1040 case DDI_INFO_DEVT2DEVINFO:
1041 if (ppb_p == NULL)
1042 return (DDI_FAILURE);
1043 *result = (void *)ppb_p->dip;
1044 return (DDI_SUCCESS);
1045 }
1046 }
1047
1048 void ppb_peekpoke_cb(dev_info_t *dip, ddi_fm_error_t *derr) {
1049 (void) pci_ereport_post(dip, derr, NULL);
1050 }
1051
1052 /*ARGSUSED*/
1053 static int
1054 ppb_fm_init(dev_info_t *dip, dev_info_t *tdip, int cap,
1055 ddi_iblock_cookie_t *ibc)
1056 {
1057 ppb_devstate_t *ppb = ddi_get_soft_state(ppb_state,
1058 ddi_get_instance(dip));
1059
1060 ASSERT(ibc != NULL);
1061 *ibc = ppb->ppb_fm_ibc;
1062
1063 return (ppb->ppb_fmcap);
1064 }
1065
1066 /*ARGSUSED*/
1067 static int
1068 ppb_fm_callback(dev_info_t *dip, ddi_fm_error_t *derr, const void *no_used)
1069 {
1070 ppb_devstate_t *ppb = ddi_get_soft_state(ppb_state,
1071 ddi_get_instance(dip));
1072
1073 mutex_enter(&ppb->ppb_err_mutex);
1074 pci_ereport_post(dip, derr, NULL);
1075 mutex_exit(&ppb->ppb_err_mutex);
1076 return (derr->fme_status);
1077 }