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7127 remove -Wno-missing-braces from Makefile.uts
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--- old/usr/src/uts/intel/io/intel_nb5000/intel_nbdrv.c
+++ new/usr/src/uts/intel/io/intel_nb5000/intel_nbdrv.c
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21
22 22 /*
23 23 * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
24 24 * Use is subject to license terms.
25 25 * Copyright (c) 2011 Bayard G. Bell. All rights reserved.
26 26 */
27 27
28 28 #include <sys/types.h>
29 29 #include <sys/time.h>
30 30 #include <sys/nvpair.h>
31 31 #include <sys/cmn_err.h>
32 32 #include <sys/cred.h>
33 33 #include <sys/open.h>
34 34 #include <sys/ddi.h>
35 35 #include <sys/sunddi.h>
36 36 #include <sys/conf.h>
37 37 #include <sys/modctl.h>
38 38 #include <sys/cyclic.h>
39 39 #include <sys/errorq.h>
40 40 #include <sys/stat.h>
41 41 #include <sys/cpuvar.h>
42 42 #include <sys/mc_intel.h>
43 43 #include <sys/mc.h>
44 44 #include <sys/fm/protocol.h>
45 45 #include "nb_log.h"
46 46 #include "nb5000.h"
47 47
48 48 nvlist_t *inb_mc_nvl;
49 49 krwlock_t inb_mc_lock;
50 50
51 51 char *inb_mc_snapshot;
52 52 uint_t nb_config_gen;
53 53 uint_t inb_mc_snapshotgen;
54 54 size_t inb_mc_snapshotsz;
55 55 static dev_info_t *inb_dip;
56 56 int nb_allow_detach = 0;
57 57 int nb_no_smbios;
58 58
59 59 static uint64_t
60 60 rank_to_base(uint8_t branch, uint8_t rank, uint8_t *interleave, uint64_t *limit,
61 61 uint64_t *hole_base, uint64_t *hole_size, uint8_t *wayp,
62 62 uint8_t *branch_interleavep)
63 63 {
64 64 uint8_t i, j;
65 65 uint64_t base = 0;
66 66 uint64_t lt = 0;
67 67 uint64_t h = 0;
68 68 uint64_t hs = 0;
69 69 uint8_t il = 1;
70 70 uint8_t way = 0;
71 71 uint8_t branch_interleave = 0;
72 72
73 73 for (i = 0; i < NB_MEM_RANK_SELECT; i++) {
74 74 for (j = 0; j < NB_RANKS_IN_SELECT; j++) {
75 75 if (nb_ranks[branch][i].rank[j] == rank) {
76 76 base = nb_ranks[branch][i].base;
77 77 lt = nb_ranks[branch][i].limit;
78 78 il = nb_ranks[branch][i].interleave;
79 79 h = nb_ranks[branch][i].hole_base;
80 80 hs = nb_ranks[branch][i].hole_size;
81 81 way = j;
82 82 branch_interleave =
83 83 nb_ranks[branch][i].branch_interleave;
84 84 i = NB_MEM_RANK_SELECT;
85 85 break;
86 86 }
87 87 }
88 88 }
89 89 if (lt == 0) {
90 90 for (i = 0; lt == 0 && i < NB_MEM_BRANCH_SELECT; i++) {
91 91 if (nb_banks[i].way[branch] &&
92 92 base >= nb_banks[i].base &&
93 93 base < nb_banks[i].base + nb_banks[i].limit) {
94 94 lt = nb_banks[i].limit;
95 95 break;
96 96 }
97 97 }
98 98 }
99 99 *interleave = il;
100 100 *limit = lt;
101 101 *hole_base = h;
102 102 *hole_size = hs;
103 103 *wayp = way;
104 104 *branch_interleavep = branch_interleave;
105 105 return (base);
106 106 }
107 107
108 108 /*ARGSUSED*/
109 109 void
110 110 inb_rank(nvlist_t *newdimm, nb_dimm_t *nb_dimm, uint8_t channel, uint32_t dimm)
111 111 {
112 112 nvlist_t **newrank;
113 113 int i;
114 114
115 115 newrank = kmem_zalloc(sizeof (nvlist_t *) * nb_dimm->nranks, KM_SLEEP);
116 116 for (i = 0; i < nb_dimm->nranks; i++) {
117 117 uint64_t dimm_base;
118 118 uint64_t limit;
119 119 uint8_t interleave;
120 120 uint8_t way;
121 121 uint8_t branch_interleave;
122 122 uint64_t hole_base;
123 123 uint64_t hole_size;
124 124
125 125 dimm_base = rank_to_base(channel/nb_channels_per_branch,
126 126 nb_dimm->start_rank + i, &interleave,
127 127 &limit, &hole_base, &hole_size, &way, &branch_interleave);
128 128 (void) nvlist_alloc(&newrank[i], NV_UNIQUE_NAME, KM_SLEEP);
129 129
130 130 (void) nvlist_add_uint64(newrank[i], "dimm-rank-base",
131 131 dimm_base);
132 132 if (hole_size) {
133 133 (void) nvlist_add_uint64(newrank[i], "dimm-hole",
134 134 hole_base);
135 135 (void) nvlist_add_uint64(newrank[i], "dimm-hole-size",
136 136 hole_size);
137 137 }
138 138 (void) nvlist_add_uint64(newrank[i], "dimm-rank-limit",
139 139 limit);
140 140 if (interleave > 1) {
141 141 (void) nvlist_add_uint32(newrank[i],
142 142 "dimm-rank-interleave", (uint32_t)interleave);
143 143 (void) nvlist_add_uint32(newrank[i],
144 144 "dimm-rank-interleave-way", (uint32_t)way);
145 145 if (branch_interleave) {
146 146 (void) nvlist_add_uint32(newrank[i],
147 147 "dimm-rank-interleave-branch", (uint32_t)1);
148 148 }
149 149 }
150 150 }
151 151 (void) nvlist_add_nvlist_array(newdimm, MCINTEL_NVLIST_RANKS, newrank,
152 152 nb_dimm->nranks);
153 153 for (i = 0; i < nb_dimm->nranks; i++)
154 154 nvlist_free(newrank[i]);
155 155 kmem_free(newrank, sizeof (nvlist_t *) * nb_dimm->nranks);
156 156 }
157 157
158 158 nvlist_t *
159 159 inb_dimm(nb_dimm_t *nb_dimm, uint8_t channel, uint32_t dimm)
160 160 {
161 161 nvlist_t *newdimm;
162 162 uint8_t t;
163 163 char sbuf[65];
164 164
165 165 (void) nvlist_alloc(&newdimm, NV_UNIQUE_NAME, KM_SLEEP);
166 166 (void) nvlist_add_uint32(newdimm, "dimm-number", dimm);
167 167
168 168 if (nb_dimm->dimm_size >= 1024*1024*1024) {
169 169 (void) snprintf(sbuf, sizeof (sbuf), "%dG",
170 170 (int)(nb_dimm->dimm_size / (1024*1024*1024)));
171 171 } else {
172 172 (void) snprintf(sbuf, sizeof (sbuf), "%dM",
173 173 (int)(nb_dimm->dimm_size / (1024*1024)));
174 174 }
175 175 (void) nvlist_add_string(newdimm, "dimm-size", sbuf);
176 176 (void) nvlist_add_uint64(newdimm, "size", nb_dimm->dimm_size);
177 177 (void) nvlist_add_uint32(newdimm, "nbanks", (uint32_t)nb_dimm->nbanks);
178 178 (void) nvlist_add_uint32(newdimm, "ncolumn",
179 179 (uint32_t)nb_dimm->ncolumn);
180 180 (void) nvlist_add_uint32(newdimm, "nrow", (uint32_t)nb_dimm->nrow);
181 181 (void) nvlist_add_uint32(newdimm, "width", (uint32_t)nb_dimm->width);
182 182 (void) nvlist_add_int32(newdimm, MCINTEL_NVLIST_1ST_RANK,
183 183 (int32_t)nb_dimm->start_rank);
184 184 (void) nvlist_add_uint32(newdimm, "ranks", (uint32_t)nb_dimm->nranks);
185 185 inb_rank(newdimm, nb_dimm, channel, dimm);
186 186 (void) nvlist_add_uint32(newdimm, "manufacture-id",
187 187 (uint32_t)nb_dimm->manufacture_id);
188 188 (void) nvlist_add_uint32(newdimm, "manufacture-location",
189 189 (uint32_t)nb_dimm->manufacture_location);
190 190 (void) nvlist_add_uint32(newdimm, "manufacture-week",
191 191 (uint32_t)nb_dimm->manufacture_week);
192 192 (void) nvlist_add_uint32(newdimm, "manufacture-year",
193 193 (uint32_t)nb_dimm->manufacture_year + 2000);
194 194 /* create Sun Serial number from SPD data */
195 195 (void) snprintf(sbuf, sizeof (sbuf), "%04x%02x%02x%02x%08x",
196 196 (uint32_t)nb_dimm->manufacture_id & 0x7fff,
197 197 (uint32_t)nb_dimm->manufacture_location,
198 198 (uint32_t)nb_dimm->manufacture_year,
199 199 (uint32_t)nb_dimm->manufacture_week,
200 200 nb_dimm->serial_number);
201 201 (void) nvlist_add_string(newdimm, FM_FMRI_HC_SERIAL_ID, sbuf);
202 202 if (nb_dimm->part_number && nb_dimm->part_number[0]) {
203 203 t = sizeof (nb_dimm->part_number);
204 204 (void) strncpy(sbuf, nb_dimm->part_number, t);
205 205 sbuf[t] = 0;
206 206 (void) nvlist_add_string(newdimm, FM_FMRI_HC_PART, sbuf);
207 207 }
208 208 if (nb_dimm->revision && nb_dimm->revision[0]) {
209 209 t = sizeof (nb_dimm->revision);
210 210 (void) strncpy(sbuf, nb_dimm->revision, t);
211 211 sbuf[t] = 0;
212 212 (void) nvlist_add_string(newdimm, FM_FMRI_HC_REVISION, sbuf);
213 213 }
214 214 t = sizeof (nb_dimm->label);
215 215 (void) strncpy(sbuf, nb_dimm->label, t);
216 216 sbuf[t] = 0;
217 217 (void) nvlist_add_string(newdimm, FM_FAULT_FRU_LABEL, sbuf);
218 218 return (newdimm);
219 219 }
220 220
221 221 static void
222 222 inb_dimmlist(nvlist_t *nvl)
223 223 {
224 224 nvlist_t **dimmlist;
225 225 nvlist_t **newchannel;
226 226 int nchannels = nb_number_memory_controllers * nb_channels_per_branch;
227 227 int nd;
228 228 uint8_t i, j;
229 229 nb_dimm_t **dimmpp;
230 230 nb_dimm_t *dimmp;
231 231
232 232 dimmlist = kmem_zalloc(sizeof (nvlist_t *) * nb_dimms_per_channel,
233 233 KM_SLEEP);
234 234 newchannel = kmem_zalloc(sizeof (nvlist_t *) * nchannels, KM_SLEEP);
235 235 dimmpp = nb_dimms;
236 236 for (i = 0; i < nchannels; i++) {
237 237 (void) nvlist_alloc(&newchannel[i], NV_UNIQUE_NAME, KM_SLEEP);
238 238 nd = 0;
239 239 for (j = 0; j < nb_dimms_per_channel; j++) {
240 240 dimmp = *dimmpp;
241 241 if (dimmp != NULL) {
242 242 dimmlist[nd] = inb_dimm(dimmp, i, (uint32_t)j);
243 243 nd++;
244 244 }
245 245 dimmpp++;
246 246 }
247 247 if (nd) {
248 248 (void) nvlist_add_nvlist_array(newchannel[i],
249 249 "memory-dimms", dimmlist, nd);
250 250 for (j = 0; j < nd; j++)
251 251 nvlist_free(dimmlist[j]);
252 252 }
253 253 }
254 254 (void) nvlist_add_nvlist_array(nvl, MCINTEL_NVLIST_MC, newchannel,
255 255 nchannels);
256 256 for (i = 0; i < nchannels; i++)
257 257 nvlist_free(newchannel[i]);
258 258 kmem_free(dimmlist, sizeof (nvlist_t *) * nb_dimms_per_channel);
259 259 kmem_free(newchannel, sizeof (nvlist_t *) * nchannels);
260 260 }
261 261
262 262 static char *
263 263 inb_mc_name()
264 264 {
265 265 char *mc;
266 266
267 267 switch (nb_chipset) {
268 268 case INTEL_NB_7300:
269 269 mc = "Intel 7300";
270 270 break;
271 271 case INTEL_NB_5400:
272 272 mc = "Intel 5400";
273 273 break;
274 274 case INTEL_NB_5400A:
275 275 mc = "Intel 5400A";
276 276 break;
277 277 case INTEL_NB_5400B:
278 278 mc = "Intel 5400B";
279 279 break;
280 280 case INTEL_NB_5100:
281 281 mc = "Intel 5100";
282 282 break;
283 283 case INTEL_NB_5000P:
284 284 mc = "Intel 5000P";
285 285 break;
286 286 case INTEL_NB_5000V:
287 287 mc = "Intel 5000V";
288 288 break;
289 289 case INTEL_NB_5000X:
290 290 mc = "Intel 5000X";
291 291 break;
292 292 case INTEL_NB_5000Z:
293 293 mc = "Intel 5000Z";
294 294 break;
295 295 default:
296 296 mc = "Intel 5000";
297 297 break;
298 298 }
299 299 return (mc);
300 300 }
301 301
302 302 static void
303 303 inb_create_nvl()
304 304 {
305 305 nvlist_t *nvl;
306 306
307 307 (void) nvlist_alloc(&nvl, NV_UNIQUE_NAME, KM_SLEEP);
308 308 (void) nvlist_add_uint8(nvl, MCINTEL_NVLIST_VERSTR,
309 309 MCINTEL_NVLIST_VERS);
310 310 (void) nvlist_add_string(nvl, "memory-controller", inb_mc_name());
311 311 if (nb_chipset == INTEL_NB_5100)
312 312 (void) nvlist_add_uint8(nvl, MCINTEL_NVLIST_NMEM,
313 313 (uint8_t)nb_number_memory_controllers);
314 314 inb_dimmlist(nvl);
315 315
316 316 nvlist_free(inb_mc_nvl);
317 317 inb_mc_nvl = nvl;
318 318 }
319 319
320 320 static void
321 321 inb_mc_snapshot_destroy()
322 322 {
323 323 ASSERT(RW_LOCK_HELD(&inb_mc_lock));
324 324
325 325 if (inb_mc_snapshot == NULL)
326 326 return;
327 327
328 328 kmem_free(inb_mc_snapshot, inb_mc_snapshotsz);
329 329 inb_mc_snapshot = NULL;
330 330 inb_mc_snapshotsz = 0;
331 331 inb_mc_snapshotgen++;
332 332 }
333 333
334 334 static int
335 335 inb_mc_snapshot_update()
336 336 {
337 337 ASSERT(RW_LOCK_HELD(&inb_mc_lock));
338 338
339 339 if (inb_mc_snapshot != NULL)
340 340 return (0);
341 341
342 342 if (nvlist_pack(inb_mc_nvl, &inb_mc_snapshot, &inb_mc_snapshotsz,
343 343 NV_ENCODE_XDR, KM_SLEEP) != 0)
344 344 return (-1);
345 345
346 346 return (0);
347 347 }
348 348
349 349 /*ARGSUSED*/
350 350 static int
351 351 inb_mc_ioctl(dev_t dev, int cmd, intptr_t arg, int mode, cred_t *credp,
352 352 int *rvalp)
353 353 {
354 354 int rc = 0;
355 355 mc_snapshot_info_t mcs;
356 356
357 357 if (cmd != MC_IOC_SNAPSHOT_INFO && cmd != MC_IOC_SNAPSHOT)
358 358 return (EINVAL);
359 359
360 360 rw_enter(&inb_mc_lock, RW_READER);
361 361 if (inb_mc_nvl == NULL || inb_mc_snapshotgen != nb_config_gen) {
362 362 if (!rw_tryupgrade(&inb_mc_lock)) {
363 363 rw_exit(&inb_mc_lock);
364 364 return (EAGAIN);
365 365 }
366 366 if (inb_mc_nvl)
367 367 inb_mc_snapshot_destroy();
368 368 inb_create_nvl();
369 369 nb_config_gen = inb_mc_snapshotgen;
370 370 (void) inb_mc_snapshot_update();
371 371 }
372 372 switch (cmd) {
373 373 case MC_IOC_SNAPSHOT_INFO:
374 374 mcs.mcs_size = (uint32_t)inb_mc_snapshotsz;
375 375 mcs.mcs_gen = inb_mc_snapshotgen;
376 376
377 377 if (ddi_copyout(&mcs, (void *)arg, sizeof (mc_snapshot_info_t),
378 378 mode) < 0)
379 379 rc = EFAULT;
380 380 break;
381 381 case MC_IOC_SNAPSHOT:
382 382 if (ddi_copyout(inb_mc_snapshot, (void *)arg, inb_mc_snapshotsz,
383 383 mode) < 0)
384 384 rc = EFAULT;
385 385 break;
386 386 }
387 387 rw_exit(&inb_mc_lock);
388 388 return (rc);
389 389 }
390 390
391 391 /*ARGSUSED*/
392 392 static int
393 393 inb_mc_getinfo(dev_info_t *dip, ddi_info_cmd_t infocmd, void *arg,
394 394 void **result)
395 395 {
396 396 if ((infocmd != DDI_INFO_DEVT2DEVINFO &&
397 397 infocmd != DDI_INFO_DEVT2INSTANCE) || inb_dip == NULL) {
398 398 *result = NULL;
399 399 return (DDI_FAILURE);
400 400 }
401 401 if (infocmd == DDI_INFO_DEVT2DEVINFO)
402 402 *result = inb_dip;
403 403 else
404 404 *result = (void *)(uintptr_t)ddi_get_instance(inb_dip);
405 405 return (0);
406 406 }
407 407
408 408 static int
409 409 inb_mc_attach(dev_info_t *dip, ddi_attach_cmd_t cmd)
410 410 {
411 411 if (cmd == DDI_RESUME) {
412 412 nb_dev_reinit();
413 413 return (DDI_SUCCESS);
414 414 }
415 415 if (cmd != DDI_ATTACH)
416 416 return (DDI_FAILURE);
417 417 if (inb_dip == NULL) {
418 418 inb_dip = dip;
419 419 nb_no_smbios = ddi_prop_get_int(DDI_DEV_T_ANY, dip,
420 420 DDI_PROP_DONTPASS, "no-smbios", 0);
421 421 nb_pci_cfg_setup(dip);
422 422 (void) ddi_prop_update_string(DDI_DEV_T_NONE, dip, "model",
423 423 inb_mc_name());
424 424 if (nb_dev_init()) {
425 425 nb_pci_cfg_free();
426 426 inb_dip = NULL;
427 427 return (DDI_FAILURE);
428 428 }
429 429 if (ddi_create_minor_node(dip, "mc-intel", S_IFCHR, 0,
430 430 "ddi_mem_ctrl", 0) != DDI_SUCCESS) {
431 431 cmn_err(CE_WARN, "failed to create minor node"
432 432 " for memory controller\n");
433 433 }
434 434 cmi_hdl_walk(inb_mc_register, NULL, NULL, NULL);
435 435 }
436 436
437 437 return (DDI_SUCCESS);
438 438 }
439 439
440 440 /*ARGSUSED*/
441 441 static int
442 442 inb_mc_detach(dev_info_t *dip, ddi_detach_cmd_t cmd)
443 443 {
444 444 if (nb_allow_detach && cmd == DDI_DETACH && dip == inb_dip) {
445 445 rw_enter(&inb_mc_lock, RW_WRITER);
446 446 inb_mc_snapshot_destroy();
447 447 rw_exit(&inb_mc_lock);
448 448 inb_dip = NULL;
449 449 return (DDI_SUCCESS);
450 450 } else if (cmd == DDI_SUSPEND || cmd == DDI_PM_SUSPEND) {
451 451 return (DDI_SUCCESS);
452 452 } else {
453 453 return (DDI_FAILURE);
454 454 }
455 455 }
456 456
457 457 /*ARGSUSED*/
458 458 static int
459 459 inb_mc_open(dev_t *devp, int flag, int otyp, cred_t *credp)
460 460 {
461 461 if (otyp != OTYP_CHR)
462 462 return (EINVAL);
463 463
464 464 rw_enter(&inb_mc_lock, RW_READER);
465 465 if (getminor(*devp) >= 1) {
466 466 rw_exit(&inb_mc_lock);
467 467 return (EINVAL);
468 468 }
469 469 rw_exit(&inb_mc_lock);
470 470
471 471 return (0);
472 472 }
473 473
474 474 /*ARGSUSED*/
475 475 static int
476 476 inb_mc_close(dev_t dev, int flag, int otyp, cred_t *credp)
477 477 {
478 478 return (0);
479 479 }
480 480
481 481
482 482 static struct cb_ops inb_mc_cb_ops = {
483 483 inb_mc_open,
484 484 inb_mc_close,
485 485 nodev, /* not a block driver */
486 486 nodev, /* no print routine */
487 487 nodev, /* no dump routine */
488 488 nodev, /* no read routine */
489 489 nodev, /* no write routine */
490 490 inb_mc_ioctl,
491 491 nodev, /* no devmap routine */
492 492 nodev, /* no mmap routine */
493 493 nodev, /* no segmap routine */
494 494 nochpoll, /* no chpoll routine */
495 495 ddi_prop_op,
496 496 0, /* not a STREAMS driver */
497 497 D_NEW | D_MP, /* safe for multi-thread/multi-processor */
498 498 };
499 499
500 500 static struct dev_ops inb_mc_ops = {
501 501 DEVO_REV, /* devo_rev */
502 502 0, /* devo_refcnt */
503 503 inb_mc_getinfo, /* devo_getinfo */
504 504 nulldev, /* devo_identify */
505 505 nulldev, /* devo_probe */
506 506 inb_mc_attach, /* devo_attach */
507 507 inb_mc_detach, /* devo_detach */
508 508 nodev, /* devo_reset */
509 509 &inb_mc_cb_ops, /* devo_cb_ops */
510 510 NULL, /* devo_bus_ops */
511 511 NULL, /* devo_power */
512 512 ddi_quiesce_not_needed, /* devo_quiesce */
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513 513 };
514 514
515 515 static struct modldrv modldrv = {
516 516 &mod_driverops,
517 517 "Intel 5000 Memory Controller Hub Module",
518 518 &inb_mc_ops
519 519 };
520 520
521 521 static struct modlinkage modlinkage = {
522 522 MODREV_1,
523 - (void *)&modldrv,
524 - NULL
523 + { (void *)&modldrv, NULL }
525 524 };
526 525
527 526 int
528 527 _init(void)
529 528 {
530 529 int err;
531 530
532 531 err = nb_init();
533 532 if (err == 0 && (err = mod_install(&modlinkage)) == 0)
534 533 rw_init(&inb_mc_lock, NULL, RW_DRIVER, NULL);
535 534
536 535 return (err);
537 536 }
538 537
539 538 int
540 539 _info(struct modinfo *modinfop)
541 540 {
542 541 return (mod_info(&modlinkage, modinfop));
543 542 }
544 543
545 544 int
546 545 _fini(void)
547 546 {
548 547 int err;
549 548
550 549 if ((err = mod_remove(&modlinkage)) == 0) {
551 550 nb_unload();
552 551 rw_destroy(&inb_mc_lock);
553 552 }
554 553
555 554 return (err);
556 555 }
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