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7127 remove -Wno-missing-braces from Makefile.uts
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--- old/usr/src/uts/i86pc/io/mp_platform_common.c
+++ new/usr/src/uts/i86pc/io/mp_platform_common.c
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21 /*
22 22 * Copyright (c) 2007, 2010, Oracle and/or its affiliates. All rights reserved.
23 23 * Copyright 2016 Nexenta Systems, Inc.
24 24 */
25 25 /*
26 26 * Copyright (c) 2010, Intel Corporation.
27 27 * All rights reserved.
28 28 */
29 29
30 30 /*
31 31 * PSMI 1.1 extensions are supported only in 2.6 and later versions.
32 32 * PSMI 1.2 extensions are supported only in 2.7 and later versions.
33 33 * PSMI 1.3 and 1.4 extensions are supported in Solaris 10.
34 34 * PSMI 1.5 extensions are supported in Solaris Nevada.
35 35 * PSMI 1.6 extensions are supported in Solaris Nevada.
36 36 * PSMI 1.7 extensions are supported in Solaris Nevada.
37 37 */
38 38 #define PSMI_1_7
39 39
40 40 #include <sys/processor.h>
41 41 #include <sys/time.h>
42 42 #include <sys/psm.h>
43 43 #include <sys/smp_impldefs.h>
44 44 #include <sys/cram.h>
45 45 #include <sys/acpi/acpi.h>
46 46 #include <sys/acpica.h>
47 47 #include <sys/psm_common.h>
48 48 #include <sys/apic.h>
49 49 #include <sys/apic_timer.h>
50 50 #include <sys/pit.h>
51 51 #include <sys/ddi.h>
52 52 #include <sys/sunddi.h>
53 53 #include <sys/ddi_impldefs.h>
54 54 #include <sys/pci.h>
55 55 #include <sys/promif.h>
56 56 #include <sys/x86_archext.h>
57 57 #include <sys/cpc_impl.h>
58 58 #include <sys/uadmin.h>
59 59 #include <sys/panic.h>
60 60 #include <sys/debug.h>
61 61 #include <sys/archsystm.h>
62 62 #include <sys/trap.h>
63 63 #include <sys/machsystm.h>
64 64 #include <sys/cpuvar.h>
65 65 #include <sys/rm_platter.h>
66 66 #include <sys/privregs.h>
67 67 #include <sys/cyclic.h>
68 68 #include <sys/note.h>
69 69 #include <sys/pci_intr_lib.h>
70 70 #include <sys/sunndi.h>
71 71 #if !defined(__xpv)
72 72 #include <sys/hpet.h>
73 73 #include <sys/clock.h>
74 74 #endif
75 75
76 76 /*
77 77 * Local Function Prototypes
78 78 */
79 79 static int apic_handle_defconf();
80 80 static int apic_parse_mpct(caddr_t mpct, int bypass);
81 81 static struct apic_mpfps_hdr *apic_find_fps_sig(caddr_t fptr, int size);
82 82 static int apic_checksum(caddr_t bptr, int len);
83 83 static int apic_find_bus_type(char *bus);
84 84 static int apic_find_bus(int busid);
85 85 static struct apic_io_intr *apic_find_io_intr(int irqno);
86 86 static int apic_find_free_irq(int start, int end);
87 87 struct apic_io_intr *apic_find_io_intr_w_busid(int irqno, int busid);
88 88 static void apic_set_pwroff_method_from_mpcnfhdr(struct apic_mp_cnf_hdr *hdrp);
89 89 static void apic_free_apic_cpus(void);
90 90 static boolean_t apic_is_ioapic_AMD_813x(uint32_t physaddr);
91 91 static int apic_acpi_enter_apicmode(void);
92 92
93 93 int apic_handle_pci_pci_bridge(dev_info_t *idip, int child_devno,
94 94 int child_ipin, struct apic_io_intr **intrp);
95 95 int apic_find_bus_id(int bustype);
96 96 int apic_find_intin(uchar_t ioapic, uchar_t intin);
97 97 void apic_record_rdt_entry(apic_irq_t *irqptr, int irq);
98 98
99 99 int apic_debug_mps_id = 0; /* 1 - print MPS ID strings */
100 100
101 101 /* ACPI SCI interrupt configuration; -1 if SCI not used */
102 102 int apic_sci_vect = -1;
103 103 iflag_t apic_sci_flags;
104 104
105 105 #if !defined(__xpv)
106 106 /* ACPI HPET interrupt configuration; -1 if HPET not used */
107 107 int apic_hpet_vect = -1;
108 108 iflag_t apic_hpet_flags;
109 109 #endif
110 110
111 111 /*
112 112 * psm name pointer
113 113 */
114 114 char *psm_name;
115 115
116 116 /* ACPI support routines */
117 117 static int acpi_probe(char *);
118 118 static int apic_acpi_irq_configure(acpi_psm_lnk_t *acpipsmlnkp, dev_info_t *dip,
119 119 int *pci_irqp, iflag_t *intr_flagp);
120 120
121 121 int apic_acpi_translate_pci_irq(dev_info_t *dip, int busid, int devid,
122 122 int ipin, int *pci_irqp, iflag_t *intr_flagp);
123 123 uchar_t acpi_find_ioapic(int irq);
124 124 static int acpi_intr_compatible(iflag_t iflag1, iflag_t iflag2);
125 125
126 126 /* Max wait time (in repetitions) for flags to clear in an RDT entry. */
127 127 int apic_max_reps_clear_pending = 1000;
128 128
129 129 int apic_intr_policy = INTR_ROUND_ROBIN;
130 130
131 131 int apic_next_bind_cpu = 1; /* For round robin assignment */
132 132 /* start with cpu 1 */
133 133
134 134 /*
135 135 * If enabled, the distribution works as follows:
136 136 * On every interrupt entry, the current ipl for the CPU is set in cpu_info
137 137 * and the irq corresponding to the ipl is also set in the aci_current array.
138 138 * interrupt exit and setspl (due to soft interrupts) will cause the current
139 139 * ipl to be be changed. This is cache friendly as these frequently used
140 140 * paths write into a per cpu structure.
141 141 *
142 142 * Sampling is done by checking the structures for all CPUs and incrementing
143 143 * the busy field of the irq (if any) executing on each CPU and the busy field
144 144 * of the corresponding CPU.
145 145 * In periodic mode this is done on every clock interrupt.
146 146 * In one-shot mode, this is done thru a cyclic with an interval of
147 147 * apic_redistribute_sample_interval (default 10 milli sec).
148 148 *
149 149 * Every apic_sample_factor_redistribution times we sample, we do computations
150 150 * to decide which interrupt needs to be migrated (see comments
151 151 * before apic_intr_redistribute().
152 152 */
153 153
154 154 /*
155 155 * Following 3 variables start as % and can be patched or set using an
156 156 * API to be defined in future. They will be scaled to
157 157 * sample_factor_redistribution which is in turn set to hertz+1 (in periodic
158 158 * mode), or 101 in one-shot mode to stagger it away from one sec processing
159 159 */
160 160
161 161 int apic_int_busy_mark = 60;
162 162 int apic_int_free_mark = 20;
163 163 int apic_diff_for_redistribution = 10;
164 164
165 165 /* sampling interval for interrupt redistribution for dynamic migration */
166 166 int apic_redistribute_sample_interval = NANOSEC / 100; /* 10 millisec */
167 167
168 168 /*
169 169 * number of times we sample before deciding to redistribute interrupts
170 170 * for dynamic migration
171 171 */
172 172 int apic_sample_factor_redistribution = 101;
173 173
174 174 int apic_redist_cpu_skip = 0;
175 175 int apic_num_imbalance = 0;
176 176 int apic_num_rebind = 0;
177 177
178 178 /*
179 179 * Maximum number of APIC CPUs in the system, -1 indicates that dynamic
180 180 * allocation of CPU ids is disabled.
181 181 */
182 182 int apic_max_nproc = -1;
183 183 int apic_nproc = 0;
184 184 size_t apic_cpus_size = 0;
185 185 int apic_defconf = 0;
186 186 int apic_irq_translate = 0;
187 187 int apic_spec_rev = 0;
188 188 int apic_imcrp = 0;
189 189
190 190 int apic_use_acpi = 1; /* 1 = use ACPI, 0 = don't use ACPI */
191 191 int apic_use_acpi_madt_only = 0; /* 1=ONLY use MADT from ACPI */
192 192
193 193 /*
194 194 * For interrupt link devices, if apic_unconditional_srs is set, an irq resource
195 195 * will be assigned (via _SRS). If it is not set, use the current
196 196 * irq setting (via _CRS), but only if that irq is in the set of possible
197 197 * irqs (returned by _PRS) for the device.
198 198 */
199 199 int apic_unconditional_srs = 1;
200 200
201 201 /*
202 202 * For interrupt link devices, if apic_prefer_crs is set when we are
203 203 * assigning an IRQ resource to a device, prefer the current IRQ setting
204 204 * over other possible irq settings under same conditions.
205 205 */
206 206
207 207 int apic_prefer_crs = 1;
208 208
209 209 uchar_t apic_io_id[MAX_IO_APIC];
210 210 volatile uint32_t *apicioadr[MAX_IO_APIC];
211 211 uchar_t apic_io_ver[MAX_IO_APIC];
212 212 uchar_t apic_io_vectbase[MAX_IO_APIC];
213 213 uchar_t apic_io_vectend[MAX_IO_APIC];
214 214 uchar_t apic_reserved_irqlist[MAX_ISA_IRQ + 1];
215 215 uint32_t apic_physaddr[MAX_IO_APIC];
216 216
217 217 boolean_t ioapic_mask_workaround[MAX_IO_APIC];
218 218
219 219 /*
220 220 * First available slot to be used as IRQ index into the apic_irq_table
221 221 * for those interrupts (like MSI/X) that don't have a physical IRQ.
222 222 */
223 223 int apic_first_avail_irq = APIC_FIRST_FREE_IRQ;
224 224
225 225 /*
226 226 * apic_ioapic_lock protects the ioapics (reg select), the status, temp_bound
227 227 * and bound elements of cpus_info and the temp_cpu element of irq_struct
228 228 */
229 229 lock_t apic_ioapic_lock;
230 230
231 231 int apic_io_max = 0; /* no. of i/o apics enabled */
232 232
233 233 struct apic_io_intr *apic_io_intrp = NULL;
234 234 static struct apic_bus *apic_busp;
235 235
236 236 uchar_t apic_resv_vector[MAXIPL+1];
237 237
238 238 char apic_level_intr[APIC_MAX_VECTOR+1];
239 239
240 240 uint32_t eisa_level_intr_mask = 0;
241 241 /* At least MSB will be set if EISA bus */
242 242
243 243 int apic_pci_bus_total = 0;
244 244 uchar_t apic_single_pci_busid = 0;
245 245
246 246 /*
247 247 * airq_mutex protects additions to the apic_irq_table - the first
248 248 * pointer and any airq_nexts off of that one. It also protects
249 249 * apic_max_device_irq & apic_min_device_irq. It also guarantees
250 250 * that share_id is unique as new ids are generated only when new
251 251 * irq_t structs are linked in. Once linked in the structs are never
252 252 * deleted. temp_cpu & mps_intr_index field indicate if it is programmed
253 253 * or allocated. Note that there is a slight gap between allocating in
254 254 * apic_introp_xlate and programming in addspl.
255 255 */
256 256 kmutex_t airq_mutex;
257 257 apic_irq_t *apic_irq_table[APIC_MAX_VECTOR+1];
258 258 int apic_max_device_irq = 0;
259 259 int apic_min_device_irq = APIC_MAX_VECTOR;
260 260
261 261 typedef struct prs_irq_list_ent {
262 262 int list_prio;
263 263 int32_t irq;
264 264 iflag_t intrflags;
265 265 acpi_prs_private_t prsprv;
266 266 struct prs_irq_list_ent *next;
267 267 } prs_irq_list_t;
268 268
269 269
270 270 /*
271 271 * ACPI variables
272 272 */
273 273 /* 1 = acpi is enabled & working, 0 = acpi is not enabled or not there */
274 274 int apic_enable_acpi = 0;
275 275
276 276 /* ACPI Multiple APIC Description Table ptr */
277 277 static ACPI_TABLE_MADT *acpi_mapic_dtp = NULL;
278 278
279 279 /* ACPI Interrupt Source Override Structure ptr */
280 280 ACPI_MADT_INTERRUPT_OVERRIDE *acpi_isop = NULL;
281 281 int acpi_iso_cnt = 0;
282 282
283 283 /* ACPI Non-maskable Interrupt Sources ptr */
284 284 static ACPI_MADT_NMI_SOURCE *acpi_nmi_sp = NULL;
285 285 static int acpi_nmi_scnt = 0;
286 286 static ACPI_MADT_LOCAL_APIC_NMI *acpi_nmi_cp = NULL;
287 287 static int acpi_nmi_ccnt = 0;
288 288
289 289 /*
290 290 * The following added to identify a software poweroff method if available.
291 291 */
292 292
293 293 static struct {
294 294 int poweroff_method;
295 295 char oem_id[APIC_MPS_OEM_ID_LEN + 1]; /* MAX + 1 for NULL */
296 296 char prod_id[APIC_MPS_PROD_ID_LEN + 1]; /* MAX + 1 for NULL */
297 297 } apic_mps_ids[] = {
298 298 { APIC_POWEROFF_VIA_RTC, "INTEL", "ALDER" }, /* 4300 */
299 299 { APIC_POWEROFF_VIA_RTC, "NCR", "AMC" }, /* 4300 */
300 300 { APIC_POWEROFF_VIA_ASPEN_BMC, "INTEL", "A450NX" }, /* 4400? */
301 301 { APIC_POWEROFF_VIA_ASPEN_BMC, "INTEL", "AD450NX" }, /* 4400 */
302 302 { APIC_POWEROFF_VIA_ASPEN_BMC, "INTEL", "AC450NX" }, /* 4400R */
303 303 { APIC_POWEROFF_VIA_SITKA_BMC, "INTEL", "S450NX" }, /* S50 */
304 304 { APIC_POWEROFF_VIA_SITKA_BMC, "INTEL", "SC450NX" } /* S50? */
305 305 };
306 306
307 307 int apic_poweroff_method = APIC_POWEROFF_NONE;
308 308
309 309 /*
310 310 * Auto-configuration routines
311 311 */
312 312
313 313 /*
314 314 * Look at MPSpec 1.4 (Intel Order # 242016-005) for details of what we do here
315 315 * May work with 1.1 - but not guaranteed.
316 316 * According to the MP Spec, the MP floating pointer structure
317 317 * will be searched in the order described below:
318 318 * 1. In the first kilobyte of Extended BIOS Data Area (EBDA)
319 319 * 2. Within the last kilobyte of system base memory
320 320 * 3. In the BIOS ROM address space between 0F0000h and 0FFFFh
321 321 * Once we find the right signature with proper checksum, we call
322 322 * either handle_defconf or parse_mpct to get all info necessary for
323 323 * subsequent operations.
324 324 */
325 325 int
326 326 apic_probe_common(char *modname)
327 327 {
328 328 uint32_t mpct_addr, ebda_start = 0, base_mem_end;
329 329 caddr_t biosdatap;
330 330 caddr_t mpct = 0;
331 331 caddr_t fptr;
332 332 int i, mpct_size, mapsize, retval = PSM_FAILURE;
333 333 ushort_t ebda_seg, base_mem_size;
334 334 struct apic_mpfps_hdr *fpsp;
335 335 struct apic_mp_cnf_hdr *hdrp;
336 336 int bypass_cpu_and_ioapics_in_mptables;
337 337 int acpi_user_options;
338 338
339 339 if (apic_forceload < 0)
340 340 return (retval);
341 341
342 342 /*
343 343 * Remember who we are
344 344 */
345 345 psm_name = modname;
346 346
347 347 /* Allow override for MADT-only mode */
348 348 acpi_user_options = ddi_prop_get_int(DDI_DEV_T_ANY, ddi_root_node(), 0,
349 349 "acpi-user-options", 0);
350 350 apic_use_acpi_madt_only = ((acpi_user_options & ACPI_OUSER_MADT) != 0);
351 351
352 352 /* Allow apic_use_acpi to override MADT-only mode */
353 353 if (!apic_use_acpi)
354 354 apic_use_acpi_madt_only = 0;
355 355
356 356 retval = acpi_probe(modname);
357 357
358 358 /*
359 359 * mapin the bios data area 40:0
360 360 * 40:13h - two-byte location reports the base memory size
361 361 * 40:0Eh - two-byte location for the exact starting address of
362 362 * the EBDA segment for EISA
363 363 */
364 364 biosdatap = psm_map_phys(0x400, 0x20, PROT_READ);
365 365 if (!biosdatap)
366 366 goto apic_ret;
367 367 fpsp = (struct apic_mpfps_hdr *)NULL;
368 368 mapsize = MPFPS_RAM_WIN_LEN;
369 369 /*LINTED: pointer cast may result in improper alignment */
370 370 ebda_seg = *((ushort_t *)(biosdatap+0xe));
371 371 /* check the 1k of EBDA */
372 372 if (ebda_seg) {
373 373 ebda_start = ((uint32_t)ebda_seg) << 4;
374 374 fptr = psm_map_phys(ebda_start, MPFPS_RAM_WIN_LEN, PROT_READ);
375 375 if (fptr) {
376 376 if (!(fpsp =
377 377 apic_find_fps_sig(fptr, MPFPS_RAM_WIN_LEN)))
378 378 psm_unmap_phys(fptr, MPFPS_RAM_WIN_LEN);
379 379 }
380 380 }
381 381 /* If not in EBDA, check the last k of system base memory */
382 382 if (!fpsp) {
383 383 /*LINTED: pointer cast may result in improper alignment */
384 384 base_mem_size = *((ushort_t *)(biosdatap + 0x13));
385 385
386 386 if (base_mem_size > 512)
387 387 base_mem_end = 639 * 1024;
388 388 else
389 389 base_mem_end = 511 * 1024;
390 390 /* if ebda == last k of base mem, skip to check BIOS ROM */
391 391 if (base_mem_end != ebda_start) {
392 392
393 393 fptr = psm_map_phys(base_mem_end, MPFPS_RAM_WIN_LEN,
394 394 PROT_READ);
395 395
396 396 if (fptr) {
397 397 if (!(fpsp = apic_find_fps_sig(fptr,
398 398 MPFPS_RAM_WIN_LEN)))
399 399 psm_unmap_phys(fptr, MPFPS_RAM_WIN_LEN);
400 400 }
401 401 }
402 402 }
403 403 psm_unmap_phys(biosdatap, 0x20);
404 404
405 405 /* If still cannot find it, check the BIOS ROM space */
406 406 if (!fpsp) {
407 407 mapsize = MPFPS_ROM_WIN_LEN;
408 408 fptr = psm_map_phys(MPFPS_ROM_WIN_START,
409 409 MPFPS_ROM_WIN_LEN, PROT_READ);
410 410 if (fptr) {
411 411 if (!(fpsp =
412 412 apic_find_fps_sig(fptr, MPFPS_ROM_WIN_LEN))) {
413 413 psm_unmap_phys(fptr, MPFPS_ROM_WIN_LEN);
414 414 goto apic_ret;
415 415 }
416 416 }
417 417 }
418 418
419 419 if (apic_checksum((caddr_t)fpsp, fpsp->mpfps_length * 16) != 0) {
420 420 psm_unmap_phys(fptr, MPFPS_ROM_WIN_LEN);
421 421 goto apic_ret;
422 422 }
423 423
424 424 apic_spec_rev = fpsp->mpfps_spec_rev;
425 425 if ((apic_spec_rev != 04) && (apic_spec_rev != 01)) {
426 426 psm_unmap_phys(fptr, MPFPS_ROM_WIN_LEN);
427 427 goto apic_ret;
428 428 }
429 429
430 430 /* check IMCR is present or not */
431 431 apic_imcrp = fpsp->mpfps_featinfo2 & MPFPS_FEATINFO2_IMCRP;
432 432
433 433 /* check default configuration (dual CPUs) */
434 434 if ((apic_defconf = fpsp->mpfps_featinfo1) != 0) {
435 435 psm_unmap_phys(fptr, mapsize);
436 436 if ((retval = apic_handle_defconf()) != PSM_SUCCESS)
437 437 return (retval);
438 438
439 439 goto apic_ret;
440 440 }
441 441
442 442 /* MP Configuration Table */
443 443 mpct_addr = (uint32_t)(fpsp->mpfps_mpct_paddr);
444 444
445 445 psm_unmap_phys(fptr, mapsize); /* unmap floating ptr struct */
446 446
447 447 /*
448 448 * Map in enough memory for the MP Configuration Table Header.
449 449 * Use this table to read the total length of the BIOS data and
450 450 * map in all the info
451 451 */
452 452 /*LINTED: pointer cast may result in improper alignment */
453 453 hdrp = (struct apic_mp_cnf_hdr *)psm_map_phys(mpct_addr,
454 454 sizeof (struct apic_mp_cnf_hdr), PROT_READ);
455 455 if (!hdrp)
456 456 goto apic_ret;
457 457
458 458 /* check mp configuration table signature PCMP */
459 459 if (hdrp->mpcnf_sig != 0x504d4350) {
460 460 psm_unmap_phys((caddr_t)hdrp, sizeof (struct apic_mp_cnf_hdr));
461 461 goto apic_ret;
462 462 }
463 463 mpct_size = (int)hdrp->mpcnf_tbl_length;
464 464
465 465 apic_set_pwroff_method_from_mpcnfhdr(hdrp);
466 466
467 467 psm_unmap_phys((caddr_t)hdrp, sizeof (struct apic_mp_cnf_hdr));
468 468
469 469 if ((retval == PSM_SUCCESS) && !apic_use_acpi_madt_only) {
470 470 /* This is an ACPI machine No need for further checks */
471 471 goto apic_ret;
472 472 }
473 473
474 474 /*
475 475 * Map in the entries for this machine, ie. Processor
476 476 * Entry Tables, Bus Entry Tables, etc.
477 477 * They are in fixed order following one another
478 478 */
479 479 mpct = psm_map_phys(mpct_addr, mpct_size, PROT_READ);
480 480 if (!mpct)
481 481 goto apic_ret;
482 482
483 483 if (apic_checksum(mpct, mpct_size) != 0)
484 484 goto apic_fail1;
485 485
486 486 /*LINTED: pointer cast may result in improper alignment */
487 487 hdrp = (struct apic_mp_cnf_hdr *)mpct;
488 488 apicadr = (uint32_t *)mapin_apic((uint32_t)hdrp->mpcnf_local_apic,
489 489 APIC_LOCAL_MEMLEN, PROT_READ | PROT_WRITE);
490 490 if (!apicadr)
491 491 goto apic_fail1;
492 492
493 493 /* Parse all information in the tables */
494 494 bypass_cpu_and_ioapics_in_mptables = (retval == PSM_SUCCESS);
495 495 if (apic_parse_mpct(mpct, bypass_cpu_and_ioapics_in_mptables) ==
496 496 PSM_SUCCESS) {
497 497 retval = PSM_SUCCESS;
498 498 goto apic_ret;
499 499 }
500 500
501 501 apic_fail1:
502 502 psm_unmap_phys(mpct, mpct_size);
503 503 mpct = NULL;
504 504
505 505 apic_ret:
506 506 if (retval == PSM_SUCCESS) {
507 507 extern int apic_ioapic_method_probe();
508 508
509 509 if ((retval = apic_ioapic_method_probe()) == PSM_SUCCESS)
510 510 return (PSM_SUCCESS);
511 511 }
512 512
513 513 for (i = 0; i < apic_io_max; i++)
514 514 mapout_ioapic((caddr_t)apicioadr[i], APIC_IO_MEMLEN);
515 515 if (apic_cpus) {
516 516 kmem_free(apic_cpus, apic_cpus_size);
517 517 apic_cpus = NULL;
518 518 }
519 519 if (apicadr) {
520 520 mapout_apic((caddr_t)apicadr, APIC_LOCAL_MEMLEN);
521 521 apicadr = NULL;
522 522 }
523 523 if (mpct)
524 524 psm_unmap_phys(mpct, mpct_size);
525 525
526 526 return (retval);
527 527 }
528 528
529 529 static void
530 530 apic_set_pwroff_method_from_mpcnfhdr(struct apic_mp_cnf_hdr *hdrp)
531 531 {
532 532 int i;
533 533
534 534 for (i = 0; i < (sizeof (apic_mps_ids) / sizeof (apic_mps_ids[0]));
535 535 i++) {
536 536 if ((strncmp(hdrp->mpcnf_oem_str, apic_mps_ids[i].oem_id,
537 537 strlen(apic_mps_ids[i].oem_id)) == 0) &&
538 538 (strncmp(hdrp->mpcnf_prod_str, apic_mps_ids[i].prod_id,
539 539 strlen(apic_mps_ids[i].prod_id)) == 0)) {
540 540
541 541 apic_poweroff_method = apic_mps_ids[i].poweroff_method;
542 542 break;
543 543 }
544 544 }
545 545
546 546 if (apic_debug_mps_id != 0) {
547 547 cmn_err(CE_CONT, "%s: MPS OEM ID = '%c%c%c%c%c%c%c%c'"
548 548 "Product ID = '%c%c%c%c%c%c%c%c%c%c%c%c'\n",
549 549 psm_name,
550 550 hdrp->mpcnf_oem_str[0],
551 551 hdrp->mpcnf_oem_str[1],
552 552 hdrp->mpcnf_oem_str[2],
553 553 hdrp->mpcnf_oem_str[3],
554 554 hdrp->mpcnf_oem_str[4],
555 555 hdrp->mpcnf_oem_str[5],
556 556 hdrp->mpcnf_oem_str[6],
557 557 hdrp->mpcnf_oem_str[7],
558 558 hdrp->mpcnf_prod_str[0],
559 559 hdrp->mpcnf_prod_str[1],
560 560 hdrp->mpcnf_prod_str[2],
561 561 hdrp->mpcnf_prod_str[3],
562 562 hdrp->mpcnf_prod_str[4],
563 563 hdrp->mpcnf_prod_str[5],
564 564 hdrp->mpcnf_prod_str[6],
565 565 hdrp->mpcnf_prod_str[7],
566 566 hdrp->mpcnf_prod_str[8],
567 567 hdrp->mpcnf_prod_str[9],
568 568 hdrp->mpcnf_prod_str[10],
569 569 hdrp->mpcnf_prod_str[11]);
570 570 }
571 571 }
572 572
573 573 static void
574 574 apic_free_apic_cpus(void)
575 575 {
576 576 if (apic_cpus != NULL) {
577 577 kmem_free(apic_cpus, apic_cpus_size);
578 578 apic_cpus = NULL;
579 579 apic_cpus_size = 0;
580 580 }
581 581 }
582 582
583 583 static int
584 584 acpi_probe(char *modname)
585 585 {
586 586 int i, intmax, index;
587 587 uint32_t id, ver;
588 588 int acpi_verboseflags = 0;
589 589 int madt_seen, madt_size;
590 590 ACPI_SUBTABLE_HEADER *ap;
591 591 ACPI_MADT_LOCAL_APIC *mpa;
592 592 ACPI_MADT_LOCAL_X2APIC *mpx2a;
593 593 ACPI_MADT_IO_APIC *mia;
594 594 ACPI_MADT_IO_SAPIC *misa;
595 595 ACPI_MADT_INTERRUPT_OVERRIDE *mio;
596 596 ACPI_MADT_NMI_SOURCE *mns;
597 597 ACPI_MADT_INTERRUPT_SOURCE *mis;
598 598 ACPI_MADT_LOCAL_APIC_NMI *mlan;
599 599 ACPI_MADT_LOCAL_X2APIC_NMI *mx2alan;
600 600 ACPI_MADT_LOCAL_APIC_OVERRIDE *mao;
601 601 int sci;
602 602 iflag_t sci_flags;
603 603 volatile uint32_t *ioapic;
604 604 int ioapic_ix;
605 605 uint32_t *local_ids;
606 606 uint32_t *proc_ids;
607 607 uchar_t hid;
608 608 int warned = 0;
609 609
610 610 if (!apic_use_acpi)
611 611 return (PSM_FAILURE);
612 612
613 613 if (AcpiGetTable(ACPI_SIG_MADT, 1,
614 614 (ACPI_TABLE_HEADER **) &acpi_mapic_dtp) != AE_OK)
615 615 return (PSM_FAILURE);
616 616
617 617 apicadr = mapin_apic((uint32_t)acpi_mapic_dtp->Address,
618 618 APIC_LOCAL_MEMLEN, PROT_READ | PROT_WRITE);
619 619 if (!apicadr)
620 620 return (PSM_FAILURE);
621 621
622 622 if ((local_ids = (uint32_t *)kmem_zalloc(NCPU * sizeof (uint32_t),
623 623 KM_NOSLEEP)) == NULL)
624 624 return (PSM_FAILURE);
625 625
626 626 if ((proc_ids = (uint32_t *)kmem_zalloc(NCPU * sizeof (uint32_t),
627 627 KM_NOSLEEP)) == NULL) {
628 628 kmem_free(local_ids, NCPU * sizeof (uint32_t));
629 629 return (PSM_FAILURE);
630 630 }
631 631
632 632 id = apic_reg_ops->apic_read(APIC_LID_REG);
633 633 local_ids[0] = (uchar_t)(id >> 24);
634 634 apic_nproc = index = 1;
635 635 apic_io_max = 0;
636 636
637 637 ap = (ACPI_SUBTABLE_HEADER *) (acpi_mapic_dtp + 1);
638 638 madt_size = acpi_mapic_dtp->Header.Length;
639 639 madt_seen = sizeof (*acpi_mapic_dtp);
640 640
641 641 while (madt_seen < madt_size) {
642 642 switch (ap->Type) {
643 643 case ACPI_MADT_TYPE_LOCAL_APIC:
644 644 mpa = (ACPI_MADT_LOCAL_APIC *) ap;
645 645 if (mpa->LapicFlags & ACPI_MADT_ENABLED) {
646 646 if (mpa->Id == local_ids[0]) {
647 647 ASSERT(index == 1);
648 648 proc_ids[0] = mpa->ProcessorId;
649 649 } else if (apic_nproc < NCPU && use_mp &&
650 650 apic_nproc < boot_ncpus) {
651 651 local_ids[index] = mpa->Id;
652 652 proc_ids[index] = mpa->ProcessorId;
653 653 index++;
654 654 apic_nproc++;
655 655 } else if (apic_nproc == NCPU && !warned) {
656 656 cmn_err(CE_WARN, "%s: CPU limit "
657 657 "exceeded"
658 658 #if !defined(__amd64)
659 659 " for 32-bit mode"
660 660 #endif
661 661 "; Solaris will use %d CPUs.",
662 662 psm_name, NCPU);
663 663 warned = 1;
664 664 }
665 665 }
666 666 break;
667 667
668 668 case ACPI_MADT_TYPE_IO_APIC:
669 669 mia = (ACPI_MADT_IO_APIC *) ap;
670 670 if (apic_io_max < MAX_IO_APIC) {
671 671 ioapic_ix = apic_io_max;
672 672 apic_io_id[apic_io_max] = mia->Id;
673 673 apic_io_vectbase[apic_io_max] =
674 674 mia->GlobalIrqBase;
675 675 apic_physaddr[apic_io_max] =
676 676 (uint32_t)mia->Address;
677 677 ioapic = apicioadr[apic_io_max] =
678 678 mapin_ioapic((uint32_t)mia->Address,
679 679 APIC_IO_MEMLEN, PROT_READ | PROT_WRITE);
680 680 if (!ioapic)
681 681 goto cleanup;
682 682 ioapic_mask_workaround[apic_io_max] =
683 683 apic_is_ioapic_AMD_813x(mia->Address);
684 684 apic_io_max++;
685 685 }
686 686 break;
687 687
688 688 case ACPI_MADT_TYPE_INTERRUPT_OVERRIDE:
689 689 mio = (ACPI_MADT_INTERRUPT_OVERRIDE *) ap;
690 690 if (acpi_isop == NULL)
691 691 acpi_isop = mio;
692 692 acpi_iso_cnt++;
693 693 break;
694 694
695 695 case ACPI_MADT_TYPE_NMI_SOURCE:
696 696 /* UNIMPLEMENTED */
697 697 mns = (ACPI_MADT_NMI_SOURCE *) ap;
698 698 if (acpi_nmi_sp == NULL)
699 699 acpi_nmi_sp = mns;
700 700 acpi_nmi_scnt++;
701 701
702 702 cmn_err(CE_NOTE, "!apic: nmi source: %d 0x%x\n",
703 703 mns->GlobalIrq, mns->IntiFlags);
704 704 break;
705 705
706 706 case ACPI_MADT_TYPE_LOCAL_APIC_NMI:
707 707 /* UNIMPLEMENTED */
708 708 mlan = (ACPI_MADT_LOCAL_APIC_NMI *) ap;
709 709 if (acpi_nmi_cp == NULL)
710 710 acpi_nmi_cp = mlan;
711 711 acpi_nmi_ccnt++;
712 712
713 713 cmn_err(CE_NOTE, "!apic: local nmi: %d 0x%x %d\n",
714 714 mlan->ProcessorId, mlan->IntiFlags,
715 715 mlan->Lint);
716 716 break;
717 717
718 718 case ACPI_MADT_TYPE_LOCAL_APIC_OVERRIDE:
719 719 /* UNIMPLEMENTED */
720 720 mao = (ACPI_MADT_LOCAL_APIC_OVERRIDE *) ap;
721 721 cmn_err(CE_NOTE, "!apic: address override: %lx\n",
722 722 (long)mao->Address);
723 723 break;
724 724
725 725 case ACPI_MADT_TYPE_IO_SAPIC:
726 726 /* UNIMPLEMENTED */
727 727 misa = (ACPI_MADT_IO_SAPIC *) ap;
728 728
729 729 cmn_err(CE_NOTE, "!apic: io sapic: %d %d %lx\n",
730 730 misa->Id, misa->GlobalIrqBase,
731 731 (long)misa->Address);
732 732 break;
733 733
734 734 case ACPI_MADT_TYPE_INTERRUPT_SOURCE:
735 735 /* UNIMPLEMENTED */
736 736 mis = (ACPI_MADT_INTERRUPT_SOURCE *) ap;
737 737
738 738 cmn_err(CE_NOTE,
739 739 "!apic: irq source: %d %d %d 0x%x %d %d\n",
740 740 mis->Id, mis->Eid, mis->GlobalIrq,
741 741 mis->IntiFlags, mis->Type,
742 742 mis->IoSapicVector);
743 743 break;
744 744
745 745 case ACPI_MADT_TYPE_LOCAL_X2APIC:
746 746 mpx2a = (ACPI_MADT_LOCAL_X2APIC *) ap;
747 747
748 748 /*
749 749 * All logical processors with APIC ID values
750 750 * of 255 and greater will have their APIC
751 751 * reported through Processor X2APIC structure.
752 752 * All logical processors with APIC ID less than
753 753 * 255 will have their APIC reported through
754 754 * Processor Local APIC.
755 755 *
756 756 * Some systems apparently don't care and report all
757 757 * processors through Processor X2APIC structures. We
758 758 * warn about that but don't ignore those CPUs.
759 759 */
760 760 if (mpx2a->LocalApicId < 255) {
761 761 cmn_err(CE_WARN, "!%s: ignoring invalid entry "
762 762 "in MADT: CPU %d has X2APIC Id %d (< 255)",
763 763 psm_name, mpx2a->Uid, mpx2a->LocalApicId);
764 764 }
765 765 if (mpx2a->LapicFlags & ACPI_MADT_ENABLED) {
766 766 if (mpx2a->LocalApicId == local_ids[0]) {
767 767 ASSERT(index == 1);
768 768 proc_ids[0] = mpx2a->Uid;
769 769 } else if (apic_nproc < NCPU && use_mp &&
770 770 apic_nproc < boot_ncpus) {
771 771 local_ids[index] = mpx2a->LocalApicId;
772 772 proc_ids[index] = mpx2a->Uid;
773 773 index++;
774 774 apic_nproc++;
775 775 } else if (apic_nproc == NCPU && !warned) {
776 776 cmn_err(CE_WARN, "%s: CPU limit "
777 777 "exceeded"
778 778 #if !defined(__amd64)
779 779 " for 32-bit mode"
780 780 #endif
781 781 "; Solaris will use %d CPUs.",
782 782 psm_name, NCPU);
783 783 warned = 1;
784 784 }
785 785 }
786 786
787 787 break;
788 788
789 789 case ACPI_MADT_TYPE_LOCAL_X2APIC_NMI:
790 790 /* UNIMPLEMENTED */
791 791 mx2alan = (ACPI_MADT_LOCAL_X2APIC_NMI *) ap;
792 792 if (mx2alan->Uid >> 8)
793 793 acpi_nmi_ccnt++;
794 794
795 795 #ifdef DEBUG
796 796 cmn_err(CE_NOTE,
797 797 "!apic: local x2apic nmi: %d 0x%x %d\n",
798 798 mx2alan->Uid, mx2alan->IntiFlags, mx2alan->Lint);
799 799 #endif
800 800
801 801 break;
802 802
803 803 case ACPI_MADT_TYPE_RESERVED:
804 804 default:
805 805 break;
806 806 }
807 807
808 808 /* advance to next entry */
809 809 madt_seen += ap->Length;
810 810 ap = (ACPI_SUBTABLE_HEADER *)(((char *)ap) + ap->Length);
811 811 }
812 812
813 813 /*
814 814 * allocate enough space for possible hot-adding of CPUs.
815 815 * max_ncpus may be less than apic_nproc if it's set by user.
816 816 */
817 817 if (plat_dr_support_cpu()) {
818 818 apic_max_nproc = max_ncpus;
819 819 }
820 820 apic_cpus_size = max(apic_nproc, max_ncpus) * sizeof (*apic_cpus);
821 821 if ((apic_cpus = kmem_zalloc(apic_cpus_size, KM_NOSLEEP)) == NULL)
822 822 goto cleanup;
823 823
824 824 /*
825 825 * ACPI doesn't provide the local apic ver, get it directly from the
826 826 * local apic
827 827 */
828 828 ver = apic_reg_ops->apic_read(APIC_VERS_REG);
829 829 for (i = 0; i < apic_nproc; i++) {
830 830 apic_cpus[i].aci_local_id = local_ids[i];
831 831 apic_cpus[i].aci_local_ver = (uchar_t)(ver & 0xFF);
832 832 apic_cpus[i].aci_processor_id = proc_ids[i];
833 833 /* Only build mapping info for CPUs present at boot. */
834 834 if (i < boot_ncpus)
835 835 (void) acpica_map_cpu(i, proc_ids[i]);
836 836 }
837 837
838 838 /*
839 839 * To support CPU dynamic reconfiguration, the apic CPU info structure
840 840 * for each possible CPU will be pre-allocated at boot time.
841 841 * The state for each apic CPU info structure will be assigned according
842 842 * to the following rules:
843 843 * Rule 1:
844 844 * Slot index range: [0, min(apic_nproc, boot_ncpus))
845 845 * State flags: 0
846 846 * Note: cpu exists and will be configured/enabled at boot time
847 847 * Rule 2:
848 848 * Slot index range: [boot_ncpus, apic_nproc)
849 849 * State flags: APIC_CPU_FREE | APIC_CPU_DIRTY
850 850 * Note: cpu exists but won't be configured/enabled at boot time
851 851 * Rule 3:
852 852 * Slot index range: [apic_nproc, boot_ncpus)
853 853 * State flags: APIC_CPU_FREE
854 854 * Note: cpu doesn't exist at boot time
855 855 * Rule 4:
856 856 * Slot index range: [max(apic_nproc, boot_ncpus), max_ncpus)
857 857 * State flags: APIC_CPU_FREE
858 858 * Note: cpu doesn't exist at boot time
859 859 */
860 860 CPUSET_ZERO(apic_cpumask);
861 861 for (i = 0; i < min(boot_ncpus, apic_nproc); i++) {
862 862 CPUSET_ADD(apic_cpumask, i);
863 863 apic_cpus[i].aci_status = 0;
864 864 }
865 865 for (i = boot_ncpus; i < apic_nproc; i++) {
866 866 apic_cpus[i].aci_status = APIC_CPU_FREE | APIC_CPU_DIRTY;
867 867 }
868 868 for (i = apic_nproc; i < boot_ncpus; i++) {
869 869 apic_cpus[i].aci_status = APIC_CPU_FREE;
870 870 }
871 871 for (i = max(boot_ncpus, apic_nproc); i < max_ncpus; i++) {
872 872 apic_cpus[i].aci_status = APIC_CPU_FREE;
873 873 }
874 874
875 875 for (i = 0; i < apic_io_max; i++) {
876 876 ioapic_ix = i;
877 877
878 878 /*
879 879 * need to check Sitka on the following acpi problem
880 880 * On the Sitka, the ioapic's apic_id field isn't reporting
881 881 * the actual io apic id. We have reported this problem
882 882 * to Intel. Until they fix the problem, we will get the
883 883 * actual id directly from the ioapic.
884 884 */
885 885 id = ioapic_read(ioapic_ix, APIC_ID_CMD);
886 886 hid = (uchar_t)(id >> 24);
887 887
888 888 if (hid != apic_io_id[i]) {
889 889 if (apic_io_id[i] == 0)
890 890 apic_io_id[i] = hid;
891 891 else { /* set ioapic id to whatever reported by ACPI */
892 892 id = ((uint32_t)apic_io_id[i]) << 24;
893 893 ioapic_write(ioapic_ix, APIC_ID_CMD, id);
894 894 }
895 895 }
896 896 ver = ioapic_read(ioapic_ix, APIC_VERS_CMD);
897 897 apic_io_ver[i] = (uchar_t)(ver & 0xff);
898 898 intmax = (ver >> 16) & 0xff;
899 899 apic_io_vectend[i] = apic_io_vectbase[i] + intmax;
900 900 if (apic_first_avail_irq <= apic_io_vectend[i])
901 901 apic_first_avail_irq = apic_io_vectend[i] + 1;
902 902 }
903 903
904 904
905 905 /*
906 906 * Process SCI configuration here
907 907 * An error may be returned here if
908 908 * acpi-user-options specifies legacy mode
909 909 * (no SCI, no ACPI mode)
910 910 */
911 911 if (acpica_get_sci(&sci, &sci_flags) != AE_OK)
912 912 sci = -1;
913 913
914 914 /*
915 915 * Now call acpi_init() to generate namespaces
916 916 * If this fails, we don't attempt to use ACPI
917 917 * even if we were able to get a MADT above
918 918 */
919 919 if (acpica_init() != AE_OK)
920 920 goto cleanup;
921 921
922 922 /*
923 923 * Call acpica_build_processor_map() now that we have
924 924 * ACPI namesspace access
925 925 */
926 926 (void) acpica_build_processor_map();
927 927
928 928 /*
929 929 * Squirrel away the SCI and flags for later on
930 930 * in apic_picinit() when we're ready
931 931 */
932 932 apic_sci_vect = sci;
933 933 apic_sci_flags = sci_flags;
934 934
935 935 if (apic_verbose & APIC_VERBOSE_IRQ_FLAG)
936 936 acpi_verboseflags |= PSM_VERBOSE_IRQ_FLAG;
937 937
938 938 if (apic_verbose & APIC_VERBOSE_POWEROFF_FLAG)
939 939 acpi_verboseflags |= PSM_VERBOSE_POWEROFF_FLAG;
940 940
941 941 if (apic_verbose & APIC_VERBOSE_POWEROFF_PAUSE_FLAG)
942 942 acpi_verboseflags |= PSM_VERBOSE_POWEROFF_PAUSE_FLAG;
943 943
944 944 if (acpi_psm_init(modname, acpi_verboseflags) == ACPI_PSM_FAILURE)
945 945 goto cleanup;
946 946
947 947 /* Enable ACPI APIC interrupt routing */
948 948 if (apic_acpi_enter_apicmode() != PSM_FAILURE) {
949 949 build_reserved_irqlist((uchar_t *)apic_reserved_irqlist);
950 950 apic_enable_acpi = 1;
951 951 if (apic_sci_vect > 0) {
952 952 acpica_set_core_feature(ACPI_FEATURE_SCI_EVENT);
953 953 }
954 954 if (apic_use_acpi_madt_only) {
955 955 cmn_err(CE_CONT,
956 956 "?Using ACPI for CPU/IOAPIC information ONLY\n");
957 957 }
958 958
959 959 #if !defined(__xpv)
960 960 /*
961 961 * probe ACPI for hpet information here which is used later
962 962 * in apic_picinit().
963 963 */
964 964 if (hpet_acpi_init(&apic_hpet_vect, &apic_hpet_flags) < 0) {
965 965 cmn_err(CE_NOTE, "!ACPI HPET table query failed\n");
966 966 }
967 967 #endif
968 968
969 969 kmem_free(local_ids, NCPU * sizeof (uint32_t));
970 970 kmem_free(proc_ids, NCPU * sizeof (uint32_t));
971 971 return (PSM_SUCCESS);
972 972 }
973 973 /* if setting APIC mode failed above, we fall through to cleanup */
974 974
975 975 cleanup:
976 976 apic_free_apic_cpus();
977 977 if (apicadr != NULL) {
978 978 mapout_apic((caddr_t)apicadr, APIC_LOCAL_MEMLEN);
979 979 apicadr = NULL;
980 980 }
981 981 apic_max_nproc = -1;
982 982 apic_nproc = 0;
983 983 for (i = 0; i < apic_io_max; i++) {
984 984 mapout_ioapic((caddr_t)apicioadr[i], APIC_IO_MEMLEN);
985 985 apicioadr[i] = NULL;
986 986 }
987 987 apic_io_max = 0;
988 988 acpi_isop = NULL;
989 989 acpi_iso_cnt = 0;
990 990 acpi_nmi_sp = NULL;
991 991 acpi_nmi_scnt = 0;
992 992 acpi_nmi_cp = NULL;
993 993 acpi_nmi_ccnt = 0;
994 994 kmem_free(local_ids, NCPU * sizeof (uint32_t));
995 995 kmem_free(proc_ids, NCPU * sizeof (uint32_t));
996 996 return (PSM_FAILURE);
997 997 }
998 998
999 999 /*
1000 1000 * Handle default configuration. Fill in reqd global variables & tables
1001 1001 * Fill all details as MP table does not give any more info
1002 1002 */
1003 1003 static int
1004 1004 apic_handle_defconf()
1005 1005 {
1006 1006 uint_t lid;
1007 1007
1008 1008 /* Failed to probe ACPI MADT tables, disable CPU DR. */
1009 1009 apic_max_nproc = -1;
1010 1010 apic_free_apic_cpus();
1011 1011 plat_dr_disable_cpu();
1012 1012
1013 1013 apicioadr[0] = (void *)mapin_ioapic(APIC_IO_ADDR,
1014 1014 APIC_IO_MEMLEN, PROT_READ | PROT_WRITE);
1015 1015 apicadr = (void *)psm_map_phys(APIC_LOCAL_ADDR,
1016 1016 APIC_LOCAL_MEMLEN, PROT_READ);
1017 1017 apic_cpus_size = 2 * sizeof (*apic_cpus);
1018 1018 apic_cpus = (apic_cpus_info_t *)
1019 1019 kmem_zalloc(apic_cpus_size, KM_NOSLEEP);
1020 1020 if ((!apicadr) || (!apicioadr[0]) || (!apic_cpus))
1021 1021 goto apic_handle_defconf_fail;
1022 1022 CPUSET_ONLY(apic_cpumask, 0);
1023 1023 CPUSET_ADD(apic_cpumask, 1);
1024 1024 apic_nproc = 2;
1025 1025 lid = apic_reg_ops->apic_read(APIC_LID_REG);
1026 1026 apic_cpus[0].aci_local_id = (uchar_t)(lid >> APIC_ID_BIT_OFFSET);
1027 1027 /*
1028 1028 * According to the PC+MP spec 1.1, the local ids
1029 1029 * for the default configuration has to be 0 or 1
1030 1030 */
1031 1031 if (apic_cpus[0].aci_local_id == 1)
1032 1032 apic_cpus[1].aci_local_id = 0;
1033 1033 else if (apic_cpus[0].aci_local_id == 0)
1034 1034 apic_cpus[1].aci_local_id = 1;
1035 1035 else
1036 1036 goto apic_handle_defconf_fail;
1037 1037
1038 1038 apic_io_id[0] = 2;
1039 1039 apic_io_max = 1;
1040 1040 if (apic_defconf >= 5) {
1041 1041 apic_cpus[0].aci_local_ver = APIC_INTEGRATED_VERS;
1042 1042 apic_cpus[1].aci_local_ver = APIC_INTEGRATED_VERS;
1043 1043 apic_io_ver[0] = APIC_INTEGRATED_VERS;
1044 1044 } else {
1045 1045 apic_cpus[0].aci_local_ver = 0; /* 82489 DX */
1046 1046 apic_cpus[1].aci_local_ver = 0;
1047 1047 apic_io_ver[0] = 0;
1048 1048 }
1049 1049 if (apic_defconf == 2 || apic_defconf == 3 || apic_defconf == 6)
1050 1050 eisa_level_intr_mask = (inb(EISA_LEVEL_CNTL + 1) << 8) |
1051 1051 inb(EISA_LEVEL_CNTL) | ((uint_t)INT32_MAX + 1);
1052 1052 return (PSM_SUCCESS);
1053 1053
1054 1054 apic_handle_defconf_fail:
1055 1055 if (apicadr)
1056 1056 mapout_apic((caddr_t)apicadr, APIC_LOCAL_MEMLEN);
1057 1057 if (apicioadr[0])
1058 1058 mapout_ioapic((caddr_t)apicioadr[0], APIC_IO_MEMLEN);
1059 1059 return (PSM_FAILURE);
1060 1060 }
1061 1061
1062 1062 /* Parse the entries in MP configuration table and collect info that we need */
1063 1063 static int
1064 1064 apic_parse_mpct(caddr_t mpct, int bypass_cpus_and_ioapics)
1065 1065 {
1066 1066 struct apic_procent *procp;
1067 1067 struct apic_bus *busp;
1068 1068 struct apic_io_entry *ioapicp;
1069 1069 struct apic_io_intr *intrp;
1070 1070 int ioapic_ix;
1071 1071 uint_t lid;
1072 1072 uint32_t id;
1073 1073 uchar_t hid;
1074 1074 int warned = 0;
1075 1075
1076 1076 /*LINTED: pointer cast may result in improper alignment */
1077 1077 procp = (struct apic_procent *)(mpct + sizeof (struct apic_mp_cnf_hdr));
1078 1078
1079 1079 /* No need to count cpu entries if we won't use them */
1080 1080 if (!bypass_cpus_and_ioapics) {
1081 1081
1082 1082 /* Find max # of CPUS and allocate structure accordingly */
1083 1083 apic_nproc = 0;
1084 1084 CPUSET_ZERO(apic_cpumask);
1085 1085 while (procp->proc_entry == APIC_CPU_ENTRY) {
1086 1086 if (procp->proc_cpuflags & CPUFLAGS_EN) {
1087 1087 if (apic_nproc < NCPU && use_mp &&
1088 1088 apic_nproc < boot_ncpus) {
1089 1089 CPUSET_ADD(apic_cpumask, apic_nproc);
1090 1090 apic_nproc++;
1091 1091 } else if (apic_nproc == NCPU && !warned) {
1092 1092 cmn_err(CE_WARN, "%s: CPU limit "
1093 1093 "exceeded"
1094 1094 #if !defined(__amd64)
1095 1095 " for 32-bit mode"
1096 1096 #endif
1097 1097 "; Solaris will use %d CPUs.",
1098 1098 psm_name, NCPU);
1099 1099 warned = 1;
1100 1100 }
1101 1101
1102 1102 }
1103 1103 procp++;
1104 1104 }
1105 1105 apic_cpus_size = apic_nproc * sizeof (*apic_cpus);
1106 1106 if (!apic_nproc || !(apic_cpus = (apic_cpus_info_t *)
1107 1107 kmem_zalloc(apic_cpus_size, KM_NOSLEEP)))
1108 1108 return (PSM_FAILURE);
1109 1109 }
1110 1110
1111 1111 /*LINTED: pointer cast may result in improper alignment */
1112 1112 procp = (struct apic_procent *)(mpct + sizeof (struct apic_mp_cnf_hdr));
1113 1113
1114 1114 /*
1115 1115 * start with index 1 as 0 needs to be filled in with Boot CPU, but
1116 1116 * if we're bypassing this information, it has already been filled
1117 1117 * in by acpi_probe(), so don't overwrite it.
1118 1118 */
1119 1119 if (!bypass_cpus_and_ioapics)
1120 1120 apic_nproc = 1;
1121 1121
1122 1122 while (procp->proc_entry == APIC_CPU_ENTRY) {
1123 1123 /* check whether the cpu exists or not */
1124 1124 if (!bypass_cpus_and_ioapics &&
1125 1125 procp->proc_cpuflags & CPUFLAGS_EN) {
1126 1126 if (procp->proc_cpuflags & CPUFLAGS_BP) { /* Boot CPU */
1127 1127 lid = apic_reg_ops->apic_read(APIC_LID_REG);
1128 1128 apic_cpus[0].aci_local_id = procp->proc_apicid;
1129 1129 if (apic_cpus[0].aci_local_id !=
1130 1130 (uchar_t)(lid >> APIC_ID_BIT_OFFSET)) {
1131 1131 return (PSM_FAILURE);
1132 1132 }
1133 1133 apic_cpus[0].aci_local_ver =
1134 1134 procp->proc_version;
1135 1135 } else if (apic_nproc < NCPU && use_mp &&
1136 1136 apic_nproc < boot_ncpus) {
1137 1137 apic_cpus[apic_nproc].aci_local_id =
1138 1138 procp->proc_apicid;
1139 1139
1140 1140 apic_cpus[apic_nproc].aci_local_ver =
1141 1141 procp->proc_version;
1142 1142 apic_nproc++;
1143 1143
1144 1144 }
1145 1145 }
1146 1146 procp++;
1147 1147 }
1148 1148
1149 1149 /*
1150 1150 * Save start of bus entries for later use.
1151 1151 * Get EISA level cntrl if EISA bus is present.
1152 1152 * Also get the CPI bus id for single CPI bus case
1153 1153 */
1154 1154 apic_busp = busp = (struct apic_bus *)procp;
1155 1155 while (busp->bus_entry == APIC_BUS_ENTRY) {
1156 1156 lid = apic_find_bus_type((char *)&busp->bus_str1);
1157 1157 if (lid == BUS_EISA) {
1158 1158 eisa_level_intr_mask = (inb(EISA_LEVEL_CNTL + 1) << 8) |
1159 1159 inb(EISA_LEVEL_CNTL) | ((uint_t)INT32_MAX + 1);
1160 1160 } else if (lid == BUS_PCI) {
1161 1161 /*
1162 1162 * apic_single_pci_busid will be used only if
1163 1163 * apic_pic_bus_total is equal to 1
1164 1164 */
1165 1165 apic_pci_bus_total++;
1166 1166 apic_single_pci_busid = busp->bus_id;
1167 1167 }
1168 1168 busp++;
1169 1169 }
1170 1170
1171 1171 ioapicp = (struct apic_io_entry *)busp;
1172 1172
1173 1173 if (!bypass_cpus_and_ioapics)
1174 1174 apic_io_max = 0;
1175 1175 do {
1176 1176 if (!bypass_cpus_and_ioapics && apic_io_max < MAX_IO_APIC) {
1177 1177 if (ioapicp->io_flags & IOAPIC_FLAGS_EN) {
1178 1178 apic_io_id[apic_io_max] = ioapicp->io_apicid;
1179 1179 apic_io_ver[apic_io_max] = ioapicp->io_version;
1180 1180 apicioadr[apic_io_max] =
1181 1181 (void *)mapin_ioapic(
1182 1182 (uint32_t)ioapicp->io_apic_addr,
1183 1183 APIC_IO_MEMLEN, PROT_READ | PROT_WRITE);
1184 1184
1185 1185 if (!apicioadr[apic_io_max])
1186 1186 return (PSM_FAILURE);
1187 1187
1188 1188 ioapic_mask_workaround[apic_io_max] =
1189 1189 apic_is_ioapic_AMD_813x(
1190 1190 ioapicp->io_apic_addr);
1191 1191
1192 1192 ioapic_ix = apic_io_max;
1193 1193 id = ioapic_read(ioapic_ix, APIC_ID_CMD);
1194 1194 hid = (uchar_t)(id >> 24);
1195 1195
1196 1196 if (hid != apic_io_id[apic_io_max]) {
1197 1197 if (apic_io_id[apic_io_max] == 0)
1198 1198 apic_io_id[apic_io_max] = hid;
1199 1199 else {
1200 1200 /*
1201 1201 * set ioapic id to whatever
1202 1202 * reported by MPS
1203 1203 *
1204 1204 * may not need to set index
1205 1205 * again ???
1206 1206 * take it out and try
1207 1207 */
1208 1208
1209 1209 id = ((uint32_t)
1210 1210 apic_io_id[apic_io_max]) <<
1211 1211 24;
1212 1212
1213 1213 ioapic_write(ioapic_ix,
1214 1214 APIC_ID_CMD, id);
1215 1215 }
1216 1216 }
1217 1217 apic_io_max++;
1218 1218 }
1219 1219 }
1220 1220 ioapicp++;
1221 1221 } while (ioapicp->io_entry == APIC_IO_ENTRY);
1222 1222
1223 1223 apic_io_intrp = (struct apic_io_intr *)ioapicp;
1224 1224
1225 1225 intrp = apic_io_intrp;
1226 1226 while (intrp->intr_entry == APIC_IO_INTR_ENTRY) {
1227 1227 if ((intrp->intr_irq > APIC_MAX_ISA_IRQ) ||
1228 1228 (apic_find_bus(intrp->intr_busid) == BUS_PCI)) {
1229 1229 apic_irq_translate = 1;
1230 1230 break;
1231 1231 }
1232 1232 intrp++;
1233 1233 }
1234 1234
1235 1235 return (PSM_SUCCESS);
1236 1236 }
1237 1237
1238 1238 boolean_t
1239 1239 apic_cpu_in_range(int cpu)
1240 1240 {
1241 1241 cpu &= ~IRQ_USER_BOUND;
1242 1242 /* Check whether cpu id is in valid range. */
1243 1243 if (cpu < 0 || cpu >= apic_nproc) {
1244 1244 return (B_FALSE);
1245 1245 } else if (apic_max_nproc != -1 && cpu >= apic_max_nproc) {
1246 1246 /*
1247 1247 * Check whether cpuid is in valid range if CPU DR is enabled.
1248 1248 */
1249 1249 return (B_FALSE);
1250 1250 } else if (!CPU_IN_SET(apic_cpumask, cpu)) {
1251 1251 return (B_FALSE);
1252 1252 }
1253 1253
1254 1254 return (B_TRUE);
1255 1255 }
1256 1256
1257 1257 processorid_t
1258 1258 apic_get_next_bind_cpu(void)
1259 1259 {
1260 1260 int i, count;
1261 1261 processorid_t cpuid = 0;
1262 1262
1263 1263 for (count = 0; count < apic_nproc; count++) {
1264 1264 if (apic_next_bind_cpu >= apic_nproc) {
1265 1265 apic_next_bind_cpu = 0;
1266 1266 }
1267 1267 i = apic_next_bind_cpu++;
1268 1268 if (apic_cpu_in_range(i)) {
1269 1269 cpuid = i;
1270 1270 break;
1271 1271 }
1272 1272 }
1273 1273
1274 1274 return (cpuid);
1275 1275 }
1276 1276
1277 1277 uint16_t
1278 1278 apic_get_apic_version()
1279 1279 {
1280 1280 int i;
1281 1281 uchar_t min_io_apic_ver = 0;
1282 1282 static uint16_t version; /* Cache as value is constant */
1283 1283 static boolean_t found = B_FALSE; /* Accomodate zero version */
1284 1284
1285 1285 if (found == B_FALSE) {
1286 1286 found = B_TRUE;
1287 1287
1288 1288 /*
1289 1289 * Don't assume all IO APICs in the system are the same.
1290 1290 *
1291 1291 * Set to the minimum version.
1292 1292 */
1293 1293 for (i = 0; i < apic_io_max; i++) {
1294 1294 if ((apic_io_ver[i] != 0) &&
1295 1295 ((min_io_apic_ver == 0) ||
1296 1296 (min_io_apic_ver >= apic_io_ver[i])))
1297 1297 min_io_apic_ver = apic_io_ver[i];
1298 1298 }
1299 1299
1300 1300 /* Assume all local APICs are of the same version. */
1301 1301 version = (min_io_apic_ver << 8) | apic_cpus[0].aci_local_ver;
1302 1302 }
1303 1303 return (version);
1304 1304 }
1305 1305
1306 1306 static struct apic_mpfps_hdr *
1307 1307 apic_find_fps_sig(caddr_t cptr, int len)
1308 1308 {
1309 1309 int i;
1310 1310
1311 1311 /* Look for the pattern "_MP_" */
1312 1312 for (i = 0; i < len; i += 16) {
1313 1313 if ((*(cptr+i) == '_') &&
1314 1314 (*(cptr+i+1) == 'M') &&
1315 1315 (*(cptr+i+2) == 'P') &&
1316 1316 (*(cptr+i+3) == '_'))
1317 1317 /*LINTED: pointer cast may result in improper alignment */
1318 1318 return ((struct apic_mpfps_hdr *)(cptr + i));
1319 1319 }
1320 1320 return (NULL);
1321 1321 }
1322 1322
1323 1323 static int
1324 1324 apic_checksum(caddr_t bptr, int len)
1325 1325 {
1326 1326 int i;
1327 1327 uchar_t cksum;
1328 1328
1329 1329 cksum = 0;
1330 1330 for (i = 0; i < len; i++)
1331 1331 cksum += *bptr++;
1332 1332 return ((int)cksum);
1333 1333 }
1334 1334
1335 1335 /*
1336 1336 * On machines with PCI-PCI bridges, a device behind a PCI-PCI bridge
1337 1337 * needs special handling. We may need to chase up the device tree,
1338 1338 * using the PCI-PCI Bridge specification's "rotating IPIN assumptions",
1339 1339 * to find the IPIN at the root bus that relates to the IPIN on the
1340 1340 * subsidiary bus (for ACPI or MP). We may, however, have an entry
1341 1341 * in the MP table or the ACPI namespace for this device itself.
1342 1342 * We handle both cases in the search below.
1343 1343 */
1344 1344 /* this is the non-acpi version */
1345 1345 int
1346 1346 apic_handle_pci_pci_bridge(dev_info_t *idip, int child_devno, int child_ipin,
1347 1347 struct apic_io_intr **intrp)
1348 1348 {
1349 1349 dev_info_t *dipp, *dip;
1350 1350 int pci_irq;
1351 1351 ddi_acc_handle_t cfg_handle;
1352 1352 int bridge_devno, bridge_bus;
1353 1353 int ipin;
1354 1354
1355 1355 dip = idip;
1356 1356
1357 1357 /*CONSTCOND*/
1358 1358 while (1) {
1359 1359 if (((dipp = ddi_get_parent(dip)) == (dev_info_t *)NULL) ||
1360 1360 (pci_config_setup(dipp, &cfg_handle) != DDI_SUCCESS))
1361 1361 return (-1);
1362 1362 if ((pci_config_get8(cfg_handle, PCI_CONF_BASCLASS) ==
1363 1363 PCI_CLASS_BRIDGE) && (pci_config_get8(cfg_handle,
1364 1364 PCI_CONF_SUBCLASS) == PCI_BRIDGE_PCI)) {
1365 1365 pci_config_teardown(&cfg_handle);
1366 1366 if (acpica_get_bdf(dipp, &bridge_bus, &bridge_devno,
1367 1367 NULL) != 0)
1368 1368 return (-1);
1369 1369 /*
1370 1370 * This is the rotating scheme documented in the
1371 1371 * PCI-to-PCI spec. If the PCI-to-PCI bridge is
1372 1372 * behind another PCI-to-PCI bridge, then it needs
1373 1373 * to keep ascending until an interrupt entry is
1374 1374 * found or the root is reached.
1375 1375 */
1376 1376 ipin = (child_devno + child_ipin) % PCI_INTD;
1377 1377 if (bridge_bus == 0 && apic_pci_bus_total == 1)
1378 1378 bridge_bus = (int)apic_single_pci_busid;
1379 1379 pci_irq = ((bridge_devno & 0x1f) << 2) |
1380 1380 (ipin & 0x3);
1381 1381 if ((*intrp = apic_find_io_intr_w_busid(pci_irq,
1382 1382 bridge_bus)) != NULL) {
1383 1383 return (pci_irq);
1384 1384 }
1385 1385 dip = dipp;
1386 1386 child_devno = bridge_devno;
1387 1387 child_ipin = ipin;
1388 1388 } else {
1389 1389 pci_config_teardown(&cfg_handle);
1390 1390 return (-1);
1391 1391 }
1392 1392 }
1393 1393 /*LINTED: function will not fall off the bottom */
1394 1394 }
1395 1395
1396 1396 uchar_t
1397 1397 acpi_find_ioapic(int irq)
1398 1398 {
1399 1399 int i;
1400 1400
1401 1401 for (i = 0; i < apic_io_max; i++) {
1402 1402 if (irq >= apic_io_vectbase[i] && irq <= apic_io_vectend[i])
1403 1403 return ((uchar_t)i);
1404 1404 }
1405 1405 return (0xFF); /* shouldn't happen */
1406 1406 }
1407 1407
1408 1408 /*
1409 1409 * See if two irqs are compatible for sharing a vector.
1410 1410 * Currently we only support sharing of PCI devices.
1411 1411 */
1412 1412 static int
1413 1413 acpi_intr_compatible(iflag_t iflag1, iflag_t iflag2)
1414 1414 {
1415 1415 uint_t level1, po1;
1416 1416 uint_t level2, po2;
1417 1417
1418 1418 /* Assume active high by default */
1419 1419 po1 = 0;
1420 1420 po2 = 0;
1421 1421
1422 1422 if (iflag1.bustype != iflag2.bustype || iflag1.bustype != BUS_PCI)
1423 1423 return (0);
1424 1424
1425 1425 if (iflag1.intr_el == INTR_EL_CONFORM)
1426 1426 level1 = AV_LEVEL;
1427 1427 else
1428 1428 level1 = (iflag1.intr_el == INTR_EL_LEVEL) ? AV_LEVEL : 0;
1429 1429
1430 1430 if (level1 && ((iflag1.intr_po == INTR_PO_ACTIVE_LOW) ||
1431 1431 (iflag1.intr_po == INTR_PO_CONFORM)))
1432 1432 po1 = AV_ACTIVE_LOW;
1433 1433
1434 1434 if (iflag2.intr_el == INTR_EL_CONFORM)
1435 1435 level2 = AV_LEVEL;
1436 1436 else
1437 1437 level2 = (iflag2.intr_el == INTR_EL_LEVEL) ? AV_LEVEL : 0;
1438 1438
1439 1439 if (level2 && ((iflag2.intr_po == INTR_PO_ACTIVE_LOW) ||
1440 1440 (iflag2.intr_po == INTR_PO_CONFORM)))
1441 1441 po2 = AV_ACTIVE_LOW;
1442 1442
1443 1443 if ((level1 == level2) && (po1 == po2))
1444 1444 return (1);
1445 1445
1446 1446 return (0);
1447 1447 }
1448 1448
1449 1449 struct apic_io_intr *
1450 1450 apic_find_io_intr_w_busid(int irqno, int busid)
1451 1451 {
1452 1452 struct apic_io_intr *intrp;
1453 1453
1454 1454 /*
1455 1455 * It can have more than 1 entry with same source bus IRQ,
1456 1456 * but unique with the source bus id
1457 1457 */
1458 1458 intrp = apic_io_intrp;
1459 1459 if (intrp != NULL) {
1460 1460 while (intrp->intr_entry == APIC_IO_INTR_ENTRY) {
1461 1461 if (intrp->intr_irq == irqno &&
1462 1462 intrp->intr_busid == busid &&
1463 1463 intrp->intr_type == IO_INTR_INT)
1464 1464 return (intrp);
1465 1465 intrp++;
1466 1466 }
1467 1467 }
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1468 1468 APIC_VERBOSE_IOAPIC((CE_NOTE, "Did not find io intr for irqno:"
1469 1469 "busid %x:%x\n", irqno, busid));
1470 1470 return ((struct apic_io_intr *)NULL);
1471 1471 }
1472 1472
1473 1473
1474 1474 struct mps_bus_info {
1475 1475 char *bus_name;
1476 1476 int bus_id;
1477 1477 } bus_info_array[] = {
1478 - "ISA ", BUS_ISA,
1479 - "PCI ", BUS_PCI,
1480 - "EISA ", BUS_EISA,
1481 - "XPRESS", BUS_XPRESS,
1482 - "PCMCIA", BUS_PCMCIA,
1483 - "VL ", BUS_VL,
1484 - "CBUS ", BUS_CBUS,
1485 - "CBUSII", BUS_CBUSII,
1486 - "FUTURE", BUS_FUTURE,
1487 - "INTERN", BUS_INTERN,
1488 - "MBI ", BUS_MBI,
1489 - "MBII ", BUS_MBII,
1490 - "MPI ", BUS_MPI,
1491 - "MPSA ", BUS_MPSA,
1492 - "NUBUS ", BUS_NUBUS,
1493 - "TC ", BUS_TC,
1494 - "VME ", BUS_VME,
1495 - "PCI-E ", BUS_PCIE
1478 + { "ISA ", BUS_ISA },
1479 + { "PCI ", BUS_PCI },
1480 + { "EISA ", BUS_EISA },
1481 + { "XPRESS", BUS_XPRESS },
1482 + { "PCMCIA", BUS_PCMCIA },
1483 + { "VL ", BUS_VL },
1484 + { "CBUS ", BUS_CBUS },
1485 + { "CBUSII", BUS_CBUSII },
1486 + { "FUTURE", BUS_FUTURE },
1487 + { "INTERN", BUS_INTERN },
1488 + { "MBI ", BUS_MBI },
1489 + { "MBII ", BUS_MBII },
1490 + { "MPI ", BUS_MPI },
1491 + { "MPSA ", BUS_MPSA },
1492 + { "NUBUS ", BUS_NUBUS },
1493 + { "TC ", BUS_TC },
1494 + { "VME ", BUS_VME },
1495 + { "PCI-E ", BUS_PCIE }
1496 1496 };
1497 1497
1498 1498 static int
1499 1499 apic_find_bus_type(char *bus)
1500 1500 {
1501 1501 int i = 0;
1502 1502
1503 1503 for (; i < sizeof (bus_info_array)/sizeof (struct mps_bus_info); i++)
1504 1504 if (strncmp(bus, bus_info_array[i].bus_name,
1505 1505 strlen(bus_info_array[i].bus_name)) == 0)
1506 1506 return (bus_info_array[i].bus_id);
1507 1507 APIC_VERBOSE_IOAPIC((CE_WARN, "Did not find bus type for bus %s", bus));
1508 1508 return (0);
1509 1509 }
1510 1510
1511 1511 static int
1512 1512 apic_find_bus(int busid)
1513 1513 {
1514 1514 struct apic_bus *busp;
1515 1515
1516 1516 busp = apic_busp;
1517 1517 while (busp->bus_entry == APIC_BUS_ENTRY) {
1518 1518 if (busp->bus_id == busid)
1519 1519 return (apic_find_bus_type((char *)&busp->bus_str1));
1520 1520 busp++;
1521 1521 }
1522 1522 APIC_VERBOSE_IOAPIC((CE_WARN, "Did not find bus for bus id %x", busid));
1523 1523 return (0);
1524 1524 }
1525 1525
1526 1526 int
1527 1527 apic_find_bus_id(int bustype)
1528 1528 {
1529 1529 struct apic_bus *busp;
1530 1530
1531 1531 busp = apic_busp;
1532 1532 while (busp->bus_entry == APIC_BUS_ENTRY) {
1533 1533 if (apic_find_bus_type((char *)&busp->bus_str1) == bustype)
1534 1534 return (busp->bus_id);
1535 1535 busp++;
1536 1536 }
1537 1537 APIC_VERBOSE_IOAPIC((CE_WARN, "Did not find bus id for bustype %x",
1538 1538 bustype));
1539 1539 return (-1);
1540 1540 }
1541 1541
1542 1542 /*
1543 1543 * Check if a particular irq need to be reserved for any io_intr
1544 1544 */
1545 1545 static struct apic_io_intr *
1546 1546 apic_find_io_intr(int irqno)
1547 1547 {
1548 1548 struct apic_io_intr *intrp;
1549 1549
1550 1550 intrp = apic_io_intrp;
1551 1551 if (intrp != NULL) {
1552 1552 while (intrp->intr_entry == APIC_IO_INTR_ENTRY) {
1553 1553 if (intrp->intr_irq == irqno &&
1554 1554 intrp->intr_type == IO_INTR_INT)
1555 1555 return (intrp);
1556 1556 intrp++;
1557 1557 }
1558 1558 }
1559 1559 return ((struct apic_io_intr *)NULL);
1560 1560 }
1561 1561
1562 1562 /*
1563 1563 * Check if the given ioapicindex intin combination has already been assigned
1564 1564 * an irq. If so return irqno. Else -1
1565 1565 */
1566 1566 int
1567 1567 apic_find_intin(uchar_t ioapic, uchar_t intin)
1568 1568 {
1569 1569 apic_irq_t *irqptr;
1570 1570 int i;
1571 1571
1572 1572 /* find ioapic and intin in the apic_irq_table[] and return the index */
1573 1573 for (i = apic_min_device_irq; i <= apic_max_device_irq; i++) {
1574 1574 irqptr = apic_irq_table[i];
1575 1575 while (irqptr) {
1576 1576 if ((irqptr->airq_mps_intr_index >= 0) &&
1577 1577 (irqptr->airq_intin_no == intin) &&
1578 1578 (irqptr->airq_ioapicindex == ioapic)) {
1579 1579 APIC_VERBOSE_IOAPIC((CE_NOTE, "!Found irq "
1580 1580 "entry for ioapic:intin %x:%x "
1581 1581 "shared interrupts ?", ioapic, intin));
1582 1582 return (i);
1583 1583 }
1584 1584 irqptr = irqptr->airq_next;
1585 1585 }
1586 1586 }
1587 1587 return (-1);
1588 1588 }
1589 1589
1590 1590 int
1591 1591 apic_allocate_irq(int irq)
1592 1592 {
1593 1593 int freeirq, i;
1594 1594
1595 1595 if ((freeirq = apic_find_free_irq(irq, (APIC_RESV_IRQ - 1))) == -1)
1596 1596 if ((freeirq = apic_find_free_irq(APIC_FIRST_FREE_IRQ,
1597 1597 (irq - 1))) == -1) {
1598 1598 /*
1599 1599 * if BIOS really defines every single irq in the mps
1600 1600 * table, then don't worry about conflicting with
1601 1601 * them, just use any free slot in apic_irq_table
1602 1602 */
1603 1603 for (i = APIC_FIRST_FREE_IRQ; i < APIC_RESV_IRQ; i++) {
1604 1604 if ((apic_irq_table[i] == NULL) ||
1605 1605 apic_irq_table[i]->airq_mps_intr_index ==
1606 1606 FREE_INDEX) {
1607 1607 freeirq = i;
1608 1608 break;
1609 1609 }
1610 1610 }
1611 1611 if (freeirq == -1) {
1612 1612 /* This shouldn't happen, but just in case */
1613 1613 cmn_err(CE_WARN, "%s: NO available IRQ", psm_name);
1614 1614 return (-1);
1615 1615 }
1616 1616 }
1617 1617 if (apic_irq_table[freeirq] == NULL) {
1618 1618 apic_irq_table[freeirq] =
1619 1619 kmem_zalloc(sizeof (apic_irq_t), KM_NOSLEEP);
1620 1620 if (apic_irq_table[freeirq] == NULL) {
1621 1621 cmn_err(CE_WARN, "%s: NO memory to allocate IRQ",
1622 1622 psm_name);
1623 1623 return (-1);
1624 1624 }
1625 1625 apic_irq_table[freeirq]->airq_temp_cpu = IRQ_UNINIT;
1626 1626 apic_irq_table[freeirq]->airq_mps_intr_index = FREE_INDEX;
1627 1627 }
1628 1628 return (freeirq);
1629 1629 }
1630 1630
1631 1631 static int
1632 1632 apic_find_free_irq(int start, int end)
1633 1633 {
1634 1634 int i;
1635 1635
1636 1636 for (i = start; i <= end; i++)
1637 1637 /* Check if any I/O entry needs this IRQ */
1638 1638 if (apic_find_io_intr(i) == NULL) {
1639 1639 /* Then see if it is free */
1640 1640 if ((apic_irq_table[i] == NULL) ||
1641 1641 (apic_irq_table[i]->airq_mps_intr_index ==
1642 1642 FREE_INDEX)) {
1643 1643 return (i);
1644 1644 }
1645 1645 }
1646 1646 return (-1);
1647 1647 }
1648 1648
1649 1649 /*
1650 1650 * compute the polarity, trigger mode and vector for programming into
1651 1651 * the I/O apic and record in airq_rdt_entry.
1652 1652 */
1653 1653 void
1654 1654 apic_record_rdt_entry(apic_irq_t *irqptr, int irq)
1655 1655 {
1656 1656 int ioapicindex, bus_type, vector;
1657 1657 short intr_index;
1658 1658 uint_t level, po, io_po;
1659 1659 struct apic_io_intr *iointrp;
1660 1660
1661 1661 intr_index = irqptr->airq_mps_intr_index;
1662 1662 DDI_INTR_IMPLDBG((CE_CONT, "apic_record_rdt_entry: intr_index=%d "
1663 1663 "irq = 0x%x dip = 0x%p vector = 0x%x\n", intr_index, irq,
1664 1664 (void *)irqptr->airq_dip, irqptr->airq_vector));
1665 1665
1666 1666 if (intr_index == RESERVE_INDEX) {
1667 1667 apic_error |= APIC_ERR_INVALID_INDEX;
1668 1668 return;
1669 1669 } else if (APIC_IS_MSI_OR_MSIX_INDEX(intr_index)) {
1670 1670 return;
1671 1671 }
1672 1672
1673 1673 vector = irqptr->airq_vector;
1674 1674 ioapicindex = irqptr->airq_ioapicindex;
1675 1675 /* Assume edge triggered by default */
1676 1676 level = 0;
1677 1677 /* Assume active high by default */
1678 1678 po = 0;
1679 1679
1680 1680 if (intr_index == DEFAULT_INDEX || intr_index == FREE_INDEX) {
1681 1681 ASSERT(irq < 16);
1682 1682 if (eisa_level_intr_mask & (1 << irq))
1683 1683 level = AV_LEVEL;
1684 1684 if (intr_index == FREE_INDEX && apic_defconf == 0)
1685 1685 apic_error |= APIC_ERR_INVALID_INDEX;
1686 1686 } else if (intr_index == ACPI_INDEX) {
1687 1687 bus_type = irqptr->airq_iflag.bustype;
1688 1688 if (irqptr->airq_iflag.intr_el == INTR_EL_CONFORM) {
1689 1689 if (bus_type == BUS_PCI)
1690 1690 level = AV_LEVEL;
1691 1691 } else
1692 1692 level = (irqptr->airq_iflag.intr_el == INTR_EL_LEVEL) ?
1693 1693 AV_LEVEL : 0;
1694 1694 if (level &&
1695 1695 ((irqptr->airq_iflag.intr_po == INTR_PO_ACTIVE_LOW) ||
1696 1696 (irqptr->airq_iflag.intr_po == INTR_PO_CONFORM &&
1697 1697 bus_type == BUS_PCI)))
1698 1698 po = AV_ACTIVE_LOW;
1699 1699 } else {
1700 1700 iointrp = apic_io_intrp + intr_index;
1701 1701 bus_type = apic_find_bus(iointrp->intr_busid);
1702 1702 if (iointrp->intr_el == INTR_EL_CONFORM) {
1703 1703 if ((irq < 16) && (eisa_level_intr_mask & (1 << irq)))
1704 1704 level = AV_LEVEL;
1705 1705 else if (bus_type == BUS_PCI)
1706 1706 level = AV_LEVEL;
1707 1707 } else
1708 1708 level = (iointrp->intr_el == INTR_EL_LEVEL) ?
1709 1709 AV_LEVEL : 0;
1710 1710 if (level && ((iointrp->intr_po == INTR_PO_ACTIVE_LOW) ||
1711 1711 (iointrp->intr_po == INTR_PO_CONFORM &&
1712 1712 bus_type == BUS_PCI)))
1713 1713 po = AV_ACTIVE_LOW;
1714 1714 }
1715 1715 if (level)
1716 1716 apic_level_intr[irq] = 1;
1717 1717 /*
1718 1718 * The 82489DX External APIC cannot do active low polarity interrupts.
1719 1719 */
1720 1720 if (po && (apic_io_ver[ioapicindex] != IOAPIC_VER_82489DX))
1721 1721 io_po = po;
1722 1722 else
1723 1723 io_po = 0;
1724 1724
1725 1725 if (apic_verbose & APIC_VERBOSE_IOAPIC_FLAG)
1726 1726 prom_printf("setio: ioapic=0x%x intin=0x%x level=0x%x po=0x%x "
1727 1727 "vector=0x%x cpu=0x%x\n\n", ioapicindex,
1728 1728 irqptr->airq_intin_no, level, io_po, vector,
1729 1729 irqptr->airq_cpu);
1730 1730
1731 1731 irqptr->airq_rdt_entry = level|io_po|vector;
1732 1732 }
1733 1733
1734 1734 int
1735 1735 apic_acpi_translate_pci_irq(dev_info_t *dip, int busid, int devid,
1736 1736 int ipin, int *pci_irqp, iflag_t *intr_flagp)
1737 1737 {
1738 1738
1739 1739 int status;
1740 1740 acpi_psm_lnk_t acpipsmlnk;
1741 1741
1742 1742 if ((status = acpi_get_irq_cache_ent(busid, devid, ipin, pci_irqp,
1743 1743 intr_flagp)) == ACPI_PSM_SUCCESS) {
1744 1744 APIC_VERBOSE_IRQ((CE_CONT, "!%s: Found irqno %d "
1745 1745 "from cache for device %s, instance #%d\n", psm_name,
1746 1746 *pci_irqp, ddi_get_name(dip), ddi_get_instance(dip)));
1747 1747 return (status);
1748 1748 }
1749 1749
1750 1750 bzero(&acpipsmlnk, sizeof (acpi_psm_lnk_t));
1751 1751
1752 1752 if ((status = acpi_translate_pci_irq(dip, ipin, pci_irqp, intr_flagp,
1753 1753 &acpipsmlnk)) == ACPI_PSM_FAILURE) {
1754 1754 APIC_VERBOSE_IRQ((CE_WARN, "%s: "
1755 1755 " acpi_translate_pci_irq failed for device %s, instance"
1756 1756 " #%d", psm_name, ddi_get_name(dip),
1757 1757 ddi_get_instance(dip)));
1758 1758 return (status);
1759 1759 }
1760 1760
1761 1761 if (status == ACPI_PSM_PARTIAL && acpipsmlnk.lnkobj != NULL) {
1762 1762 status = apic_acpi_irq_configure(&acpipsmlnk, dip, pci_irqp,
1763 1763 intr_flagp);
1764 1764 if (status != ACPI_PSM_SUCCESS) {
1765 1765 status = acpi_get_current_irq_resource(&acpipsmlnk,
1766 1766 pci_irqp, intr_flagp);
1767 1767 }
1768 1768 }
1769 1769
1770 1770 if (status == ACPI_PSM_SUCCESS) {
1771 1771 acpi_new_irq_cache_ent(busid, devid, ipin, *pci_irqp,
1772 1772 intr_flagp, &acpipsmlnk);
1773 1773
1774 1774 APIC_VERBOSE_IRQ((CE_CONT, "%s: [ACPI] "
1775 1775 "new irq %d for device %s, instance #%d\n", psm_name,
1776 1776 *pci_irqp, ddi_get_name(dip), ddi_get_instance(dip)));
1777 1777 }
1778 1778
1779 1779 return (status);
1780 1780 }
1781 1781
1782 1782 /*
1783 1783 * Adds an entry to the irq list passed in, and returns the new list.
1784 1784 * Entries are added in priority order (lower numerical priorities are
1785 1785 * placed closer to the head of the list)
1786 1786 */
1787 1787 static prs_irq_list_t *
1788 1788 acpi_insert_prs_irq_ent(prs_irq_list_t *listp, int priority, int irq,
1789 1789 iflag_t *iflagp, acpi_prs_private_t *prsprvp)
1790 1790 {
1791 1791 struct prs_irq_list_ent *newent, *prevp = NULL, *origlistp;
1792 1792
1793 1793 newent = kmem_zalloc(sizeof (struct prs_irq_list_ent), KM_SLEEP);
1794 1794
1795 1795 newent->list_prio = priority;
1796 1796 newent->irq = irq;
1797 1797 newent->intrflags = *iflagp;
1798 1798 newent->prsprv = *prsprvp;
1799 1799 /* ->next is NULL from kmem_zalloc */
1800 1800
1801 1801 /*
1802 1802 * New list -- return the new entry as the list.
1803 1803 */
1804 1804 if (listp == NULL)
1805 1805 return (newent);
1806 1806
1807 1807 /*
1808 1808 * Save original list pointer for return (since we're not modifying
1809 1809 * the head)
1810 1810 */
1811 1811 origlistp = listp;
1812 1812
1813 1813 /*
1814 1814 * Insertion sort, with entries with identical keys stored AFTER
1815 1815 * existing entries (the less-than-or-equal test of priority does
1816 1816 * this for us).
1817 1817 */
1818 1818 while (listp != NULL && listp->list_prio <= priority) {
1819 1819 prevp = listp;
1820 1820 listp = listp->next;
1821 1821 }
1822 1822
1823 1823 newent->next = listp;
1824 1824
1825 1825 if (prevp == NULL) { /* Add at head of list (newent is the new head) */
1826 1826 return (newent);
1827 1827 } else {
1828 1828 prevp->next = newent;
1829 1829 return (origlistp);
1830 1830 }
1831 1831 }
1832 1832
1833 1833 /*
1834 1834 * Frees the list passed in, deallocating all memory and leaving *listpp
1835 1835 * set to NULL.
1836 1836 */
1837 1837 static void
1838 1838 acpi_destroy_prs_irq_list(prs_irq_list_t **listpp)
1839 1839 {
1840 1840 struct prs_irq_list_ent *nextp;
1841 1841
1842 1842 ASSERT(listpp != NULL);
1843 1843
1844 1844 while (*listpp != NULL) {
1845 1845 nextp = (*listpp)->next;
1846 1846 kmem_free(*listpp, sizeof (struct prs_irq_list_ent));
1847 1847 *listpp = nextp;
1848 1848 }
1849 1849 }
1850 1850
1851 1851 /*
1852 1852 * apic_choose_irqs_from_prs returns a list of irqs selected from the list of
1853 1853 * irqs returned by the link device's _PRS method. The irqs are chosen
1854 1854 * to minimize contention in situations where the interrupt link device
1855 1855 * can be programmed to steer interrupts to different interrupt controller
1856 1856 * inputs (some of which may already be in use). The list is sorted in order
1857 1857 * of irqs to use, with the highest priority given to interrupt controller
1858 1858 * inputs that are not shared. When an interrupt controller input
1859 1859 * must be shared, apic_choose_irqs_from_prs adds the possible irqs to the
1860 1860 * returned list in the order that minimizes sharing (thereby ensuring lowest
1861 1861 * possible latency from interrupt trigger time to ISR execution time).
1862 1862 */
1863 1863 static prs_irq_list_t *
1864 1864 apic_choose_irqs_from_prs(acpi_irqlist_t *irqlistent, dev_info_t *dip,
1865 1865 int crs_irq)
1866 1866 {
1867 1867 int32_t irq;
1868 1868 int i;
1869 1869 prs_irq_list_t *prsirqlistp = NULL;
1870 1870 iflag_t iflags;
1871 1871
1872 1872 while (irqlistent != NULL) {
1873 1873 irqlistent->intr_flags.bustype = BUS_PCI;
1874 1874
1875 1875 for (i = 0; i < irqlistent->num_irqs; i++) {
1876 1876
1877 1877 irq = irqlistent->irqs[i];
1878 1878
1879 1879 if (irq <= 0) {
1880 1880 /* invalid irq number */
1881 1881 continue;
1882 1882 }
1883 1883
1884 1884 if ((irq < 16) && (apic_reserved_irqlist[irq]))
1885 1885 continue;
1886 1886
1887 1887 if ((apic_irq_table[irq] == NULL) ||
1888 1888 (apic_irq_table[irq]->airq_dip == dip)) {
1889 1889
1890 1890 prsirqlistp = acpi_insert_prs_irq_ent(
1891 1891 prsirqlistp, 0 /* Highest priority */, irq,
1892 1892 &irqlistent->intr_flags,
1893 1893 &irqlistent->acpi_prs_prv);
1894 1894
1895 1895 /*
1896 1896 * If we do not prefer the current irq from _CRS
1897 1897 * or if we do and this irq is the same as the
1898 1898 * current irq from _CRS, this is the one
1899 1899 * to pick.
1900 1900 */
1901 1901 if (!(apic_prefer_crs) || (irq == crs_irq)) {
1902 1902 return (prsirqlistp);
1903 1903 }
1904 1904 continue;
1905 1905 }
1906 1906
1907 1907 /*
1908 1908 * Edge-triggered interrupts cannot be shared
1909 1909 */
1910 1910 if (irqlistent->intr_flags.intr_el == INTR_EL_EDGE)
1911 1911 continue;
1912 1912
1913 1913 /*
1914 1914 * To work around BIOSes that contain incorrect
1915 1915 * interrupt polarity information in interrupt
1916 1916 * descriptors returned by _PRS, we assume that
1917 1917 * the polarity of the other device sharing this
1918 1918 * interrupt controller input is compatible.
1919 1919 * If it's not, the caller will catch it when
1920 1920 * the caller invokes the link device's _CRS method
1921 1921 * (after invoking its _SRS method).
1922 1922 */
1923 1923 iflags = irqlistent->intr_flags;
1924 1924 iflags.intr_po =
1925 1925 apic_irq_table[irq]->airq_iflag.intr_po;
1926 1926
1927 1927 if (!acpi_intr_compatible(iflags,
1928 1928 apic_irq_table[irq]->airq_iflag)) {
1929 1929 APIC_VERBOSE_IRQ((CE_CONT, "!%s: irq %d "
1930 1930 "not compatible [%x:%x:%x !~ %x:%x:%x]",
1931 1931 psm_name, irq,
1932 1932 iflags.intr_po,
1933 1933 iflags.intr_el,
1934 1934 iflags.bustype,
1935 1935 apic_irq_table[irq]->airq_iflag.intr_po,
1936 1936 apic_irq_table[irq]->airq_iflag.intr_el,
1937 1937 apic_irq_table[irq]->airq_iflag.bustype));
1938 1938 continue;
1939 1939 }
1940 1940
1941 1941 /*
1942 1942 * If we prefer the irq from _CRS, no need
1943 1943 * to search any further (and make sure
1944 1944 * to add this irq with the highest priority
1945 1945 * so it's tried first).
1946 1946 */
1947 1947 if (crs_irq == irq && apic_prefer_crs) {
1948 1948
1949 1949 return (acpi_insert_prs_irq_ent(
1950 1950 prsirqlistp,
1951 1951 0 /* Highest priority */,
1952 1952 irq, &iflags,
1953 1953 &irqlistent->acpi_prs_prv));
1954 1954 }
1955 1955
1956 1956 /*
1957 1957 * Priority is equal to the share count (lower
1958 1958 * share count is higher priority). Note that
1959 1959 * the intr flags passed in here are the ones we
1960 1960 * changed above -- if incorrect, it will be
1961 1961 * caught by the caller's _CRS flags comparison.
1962 1962 */
1963 1963 prsirqlistp = acpi_insert_prs_irq_ent(
1964 1964 prsirqlistp,
1965 1965 apic_irq_table[irq]->airq_share, irq,
1966 1966 &iflags, &irqlistent->acpi_prs_prv);
1967 1967 }
1968 1968
1969 1969 /* Go to the next irqlist entry */
1970 1970 irqlistent = irqlistent->next;
1971 1971 }
1972 1972
1973 1973 return (prsirqlistp);
1974 1974 }
1975 1975
1976 1976 /*
1977 1977 * Configures the irq for the interrupt link device identified by
1978 1978 * acpipsmlnkp.
1979 1979 *
1980 1980 * Gets the current and the list of possible irq settings for the
1981 1981 * device. If apic_unconditional_srs is not set, and the current
1982 1982 * resource setting is in the list of possible irq settings,
1983 1983 * current irq resource setting is passed to the caller.
1984 1984 *
1985 1985 * Otherwise, picks an irq number from the list of possible irq
1986 1986 * settings, and sets the irq of the device to this value.
1987 1987 * If prefer_crs is set, among a set of irq numbers in the list that have
1988 1988 * the least number of devices sharing the interrupt, we pick current irq
1989 1989 * resource setting if it is a member of this set.
1990 1990 *
1991 1991 * Passes the irq number in the value pointed to by pci_irqp, and
1992 1992 * polarity and sensitivity in the structure pointed to by dipintrflagp
1993 1993 * to the caller.
1994 1994 *
1995 1995 * Note that if setting the irq resource failed, but successfuly obtained
1996 1996 * the current irq resource settings, passes the current irq resources
1997 1997 * and considers it a success.
1998 1998 *
1999 1999 * Returns:
2000 2000 * ACPI_PSM_SUCCESS on success.
2001 2001 *
2002 2002 * ACPI_PSM_FAILURE if an error occured during the configuration or
2003 2003 * if a suitable irq was not found for this device, or if setting the
2004 2004 * irq resource and obtaining the current resource fails.
2005 2005 *
2006 2006 */
2007 2007 static int
2008 2008 apic_acpi_irq_configure(acpi_psm_lnk_t *acpipsmlnkp, dev_info_t *dip,
2009 2009 int *pci_irqp, iflag_t *dipintr_flagp)
2010 2010 {
2011 2011 int32_t irq;
2012 2012 int cur_irq = -1;
2013 2013 acpi_irqlist_t *irqlistp;
2014 2014 prs_irq_list_t *prs_irq_listp, *prs_irq_entp;
2015 2015 boolean_t found_irq = B_FALSE;
2016 2016
2017 2017 dipintr_flagp->bustype = BUS_PCI;
2018 2018
2019 2019 if ((acpi_get_possible_irq_resources(acpipsmlnkp, &irqlistp))
2020 2020 == ACPI_PSM_FAILURE) {
2021 2021 APIC_VERBOSE_IRQ((CE_WARN, "!%s: Unable to determine "
2022 2022 "or assign IRQ for device %s, instance #%d: The system was "
2023 2023 "unable to get the list of potential IRQs from ACPI.",
2024 2024 psm_name, ddi_get_name(dip), ddi_get_instance(dip)));
2025 2025
2026 2026 return (ACPI_PSM_FAILURE);
2027 2027 }
2028 2028
2029 2029 if ((acpi_get_current_irq_resource(acpipsmlnkp, &cur_irq,
2030 2030 dipintr_flagp) == ACPI_PSM_SUCCESS) && (!apic_unconditional_srs) &&
2031 2031 (cur_irq > 0)) {
2032 2032 /*
2033 2033 * If an IRQ is set in CRS and that IRQ exists in the set
2034 2034 * returned from _PRS, return that IRQ, otherwise print
2035 2035 * a warning
2036 2036 */
2037 2037
2038 2038 if (acpi_irqlist_find_irq(irqlistp, cur_irq, NULL)
2039 2039 == ACPI_PSM_SUCCESS) {
2040 2040
2041 2041 ASSERT(pci_irqp != NULL);
2042 2042 *pci_irqp = cur_irq;
2043 2043 acpi_free_irqlist(irqlistp);
2044 2044 return (ACPI_PSM_SUCCESS);
2045 2045 }
2046 2046
2047 2047 APIC_VERBOSE_IRQ((CE_WARN, "!%s: Could not find the "
2048 2048 "current irq %d for device %s, instance #%d in ACPI's "
2049 2049 "list of possible irqs for this device. Picking one from "
2050 2050 " the latter list.", psm_name, cur_irq, ddi_get_name(dip),
2051 2051 ddi_get_instance(dip)));
2052 2052 }
2053 2053
2054 2054 if ((prs_irq_listp = apic_choose_irqs_from_prs(irqlistp, dip,
2055 2055 cur_irq)) == NULL) {
2056 2056
2057 2057 APIC_VERBOSE_IRQ((CE_WARN, "!%s: Could not find a "
2058 2058 "suitable irq from the list of possible irqs for device "
2059 2059 "%s, instance #%d in ACPI's list of possible irqs",
2060 2060 psm_name, ddi_get_name(dip), ddi_get_instance(dip)));
2061 2061
2062 2062 acpi_free_irqlist(irqlistp);
2063 2063 return (ACPI_PSM_FAILURE);
2064 2064 }
2065 2065
2066 2066 acpi_free_irqlist(irqlistp);
2067 2067
2068 2068 for (prs_irq_entp = prs_irq_listp;
2069 2069 prs_irq_entp != NULL && found_irq == B_FALSE;
2070 2070 prs_irq_entp = prs_irq_entp->next) {
2071 2071
2072 2072 acpipsmlnkp->acpi_prs_prv = prs_irq_entp->prsprv;
2073 2073 irq = prs_irq_entp->irq;
2074 2074
2075 2075 APIC_VERBOSE_IRQ((CE_CONT, "!%s: Setting irq %d for "
2076 2076 "device %s instance #%d\n", psm_name, irq,
2077 2077 ddi_get_name(dip), ddi_get_instance(dip)));
2078 2078
2079 2079 if ((acpi_set_irq_resource(acpipsmlnkp, irq))
2080 2080 == ACPI_PSM_SUCCESS) {
2081 2081 /*
2082 2082 * setting irq was successful, check to make sure CRS
2083 2083 * reflects that. If CRS does not agree with what we
2084 2084 * set, return the irq that was set.
2085 2085 */
2086 2086
2087 2087 if (acpi_get_current_irq_resource(acpipsmlnkp, &cur_irq,
2088 2088 dipintr_flagp) == ACPI_PSM_SUCCESS) {
2089 2089
2090 2090 if (cur_irq != irq)
2091 2091 APIC_VERBOSE_IRQ((CE_WARN,
2092 2092 "!%s: IRQ resource set "
2093 2093 "(irqno %d) for device %s "
2094 2094 "instance #%d, differs from "
2095 2095 "current setting irqno %d",
2096 2096 psm_name, irq, ddi_get_name(dip),
2097 2097 ddi_get_instance(dip), cur_irq));
2098 2098 } else {
2099 2099 /*
2100 2100 * On at least one system, there was a bug in
2101 2101 * a DSDT method called by _STA, causing _STA to
2102 2102 * indicate that the link device was disabled
2103 2103 * (when, in fact, it was enabled). Since _SRS
2104 2104 * succeeded, assume that _CRS is lying and use
2105 2105 * the iflags from this _PRS interrupt choice.
2106 2106 * If we're wrong about the flags, the polarity
2107 2107 * will be incorrect and we may get an interrupt
2108 2108 * storm, but there's not much else we can do
2109 2109 * at this point.
2110 2110 */
2111 2111 *dipintr_flagp = prs_irq_entp->intrflags;
2112 2112 }
2113 2113
2114 2114 /*
2115 2115 * Return the irq that was set, and not what _CRS
2116 2116 * reports, since _CRS has been seen to return
2117 2117 * different IRQs than what was passed to _SRS on some
2118 2118 * systems (and just not return successfully on others).
2119 2119 */
2120 2120 cur_irq = irq;
2121 2121 found_irq = B_TRUE;
2122 2122 } else {
2123 2123 APIC_VERBOSE_IRQ((CE_WARN, "!%s: set resource "
2124 2124 "irq %d failed for device %s instance #%d",
2125 2125 psm_name, irq, ddi_get_name(dip),
2126 2126 ddi_get_instance(dip)));
2127 2127
2128 2128 if (cur_irq == -1) {
2129 2129 acpi_destroy_prs_irq_list(&prs_irq_listp);
2130 2130 return (ACPI_PSM_FAILURE);
2131 2131 }
2132 2132 }
2133 2133 }
2134 2134
2135 2135 acpi_destroy_prs_irq_list(&prs_irq_listp);
2136 2136
2137 2137 if (!found_irq)
2138 2138 return (ACPI_PSM_FAILURE);
2139 2139
2140 2140 ASSERT(pci_irqp != NULL);
2141 2141 *pci_irqp = cur_irq;
2142 2142 return (ACPI_PSM_SUCCESS);
2143 2143 }
2144 2144
2145 2145 void
2146 2146 ioapic_disable_redirection()
2147 2147 {
2148 2148 int ioapic_ix;
2149 2149 int intin_max;
2150 2150 int intin_ix;
2151 2151
2152 2152 /* Disable the I/O APIC redirection entries */
2153 2153 for (ioapic_ix = 0; ioapic_ix < apic_io_max; ioapic_ix++) {
2154 2154
2155 2155 /* Bits 23-16 define the maximum redirection entries */
2156 2156 intin_max = (ioapic_read(ioapic_ix, APIC_VERS_CMD) >> 16)
2157 2157 & 0xff;
2158 2158
2159 2159 for (intin_ix = 0; intin_ix <= intin_max; intin_ix++) {
2160 2160 /*
2161 2161 * The assumption here is that this is safe, even for
2162 2162 * systems with IOAPICs that suffer from the hardware
2163 2163 * erratum because all devices have been quiesced before
2164 2164 * this function is called from apic_shutdown()
2165 2165 * (or equivalent). If that assumption turns out to be
2166 2166 * false, this mask operation can induce the same
2167 2167 * erratum result we're trying to avoid.
2168 2168 */
2169 2169 ioapic_write(ioapic_ix, APIC_RDT_CMD + 2 * intin_ix,
2170 2170 AV_MASK);
2171 2171 }
2172 2172 }
2173 2173 }
2174 2174
2175 2175 /*
2176 2176 * Looks for an IOAPIC with the specified physical address in the /ioapics
2177 2177 * node in the device tree (created by the PCI enumerator).
2178 2178 */
2179 2179 static boolean_t
2180 2180 apic_is_ioapic_AMD_813x(uint32_t physaddr)
2181 2181 {
2182 2182 /*
2183 2183 * Look in /ioapics, for the ioapic with
2184 2184 * the physical address given
2185 2185 */
2186 2186 dev_info_t *ioapicsnode = ddi_find_devinfo(IOAPICS_NODE_NAME, -1, 0);
2187 2187 dev_info_t *ioapic_child;
2188 2188 boolean_t rv = B_FALSE;
2189 2189 int vid, did;
2190 2190 uint64_t ioapic_paddr;
2191 2191 boolean_t done = B_FALSE;
2192 2192
2193 2193 if (ioapicsnode == NULL)
2194 2194 return (B_FALSE);
2195 2195
2196 2196 /* Load first child: */
2197 2197 ioapic_child = ddi_get_child(ioapicsnode);
2198 2198 while (!done && ioapic_child != 0) { /* Iterate over children */
2199 2199
2200 2200 if ((ioapic_paddr = (uint64_t)ddi_prop_get_int64(DDI_DEV_T_ANY,
2201 2201 ioapic_child, DDI_PROP_DONTPASS, "reg", 0))
2202 2202 != 0 && physaddr == ioapic_paddr) {
2203 2203
2204 2204 vid = ddi_prop_get_int(DDI_DEV_T_ANY, ioapic_child,
2205 2205 DDI_PROP_DONTPASS, IOAPICS_PROP_VENID, 0);
2206 2206
2207 2207 if (vid == VENID_AMD) {
2208 2208
2209 2209 did = ddi_prop_get_int(DDI_DEV_T_ANY,
2210 2210 ioapic_child, DDI_PROP_DONTPASS,
2211 2211 IOAPICS_PROP_DEVID, 0);
2212 2212
2213 2213 if (did == DEVID_8131_IOAPIC ||
2214 2214 did == DEVID_8132_IOAPIC) {
2215 2215 rv = B_TRUE;
2216 2216 done = B_TRUE;
2217 2217 }
2218 2218 }
2219 2219 }
2220 2220
2221 2221 if (!done)
2222 2222 ioapic_child = ddi_get_next_sibling(ioapic_child);
2223 2223 }
2224 2224
2225 2225 /* The ioapics node was held by ddi_find_devinfo, so release it */
2226 2226 ndi_rele_devi(ioapicsnode);
2227 2227 return (rv);
2228 2228 }
2229 2229
2230 2230 struct apic_state {
2231 2231 int32_t as_task_reg;
2232 2232 int32_t as_dest_reg;
2233 2233 int32_t as_format_reg;
2234 2234 int32_t as_local_timer;
2235 2235 int32_t as_pcint_vect;
2236 2236 int32_t as_int_vect0;
2237 2237 int32_t as_int_vect1;
2238 2238 int32_t as_err_vect;
2239 2239 int32_t as_init_count;
2240 2240 int32_t as_divide_reg;
2241 2241 int32_t as_spur_int_reg;
2242 2242 uint32_t as_ioapic_ids[MAX_IO_APIC];
2243 2243 };
2244 2244
2245 2245
2246 2246 static int
2247 2247 apic_acpi_enter_apicmode(void)
2248 2248 {
2249 2249 ACPI_OBJECT_LIST arglist;
2250 2250 ACPI_OBJECT arg;
2251 2251 ACPI_STATUS status;
2252 2252
2253 2253 /* Setup parameter object */
2254 2254 arglist.Count = 1;
2255 2255 arglist.Pointer = &arg;
2256 2256 arg.Type = ACPI_TYPE_INTEGER;
2257 2257 arg.Integer.Value = ACPI_APIC_MODE;
2258 2258
2259 2259 status = AcpiEvaluateObject(NULL, "\\_PIC", &arglist, NULL);
2260 2260 if (ACPI_FAILURE(status))
2261 2261 return (PSM_FAILURE);
2262 2262 else
2263 2263 return (PSM_SUCCESS);
2264 2264 }
2265 2265
2266 2266
2267 2267 static void
2268 2268 apic_save_state(struct apic_state *sp)
2269 2269 {
2270 2270 int i, cpuid;
2271 2271 ulong_t iflag;
2272 2272
2273 2273 PMD(PMD_SX, ("apic_save_state %p\n", (void *)sp))
2274 2274 /*
2275 2275 * First the local APIC.
2276 2276 */
2277 2277 sp->as_task_reg = apic_reg_ops->apic_get_pri();
2278 2278 sp->as_dest_reg = apic_reg_ops->apic_read(APIC_DEST_REG);
2279 2279 if (apic_mode == LOCAL_APIC)
2280 2280 sp->as_format_reg = apic_reg_ops->apic_read(APIC_FORMAT_REG);
2281 2281 sp->as_local_timer = apic_reg_ops->apic_read(APIC_LOCAL_TIMER);
2282 2282 sp->as_pcint_vect = apic_reg_ops->apic_read(APIC_PCINT_VECT);
2283 2283 sp->as_int_vect0 = apic_reg_ops->apic_read(APIC_INT_VECT0);
2284 2284 sp->as_int_vect1 = apic_reg_ops->apic_read(APIC_INT_VECT1);
2285 2285 sp->as_err_vect = apic_reg_ops->apic_read(APIC_ERR_VECT);
2286 2286 sp->as_init_count = apic_reg_ops->apic_read(APIC_INIT_COUNT);
2287 2287 sp->as_divide_reg = apic_reg_ops->apic_read(APIC_DIVIDE_REG);
2288 2288 sp->as_spur_int_reg = apic_reg_ops->apic_read(APIC_SPUR_INT_REG);
2289 2289
2290 2290 /*
2291 2291 * If on the boot processor then save the IOAPICs' IDs
2292 2292 */
2293 2293 if ((cpuid = psm_get_cpu_id()) == 0) {
2294 2294
2295 2295 iflag = intr_clear();
2296 2296 lock_set(&apic_ioapic_lock);
2297 2297
2298 2298 for (i = 0; i < apic_io_max; i++)
2299 2299 sp->as_ioapic_ids[i] = ioapic_read(i, APIC_ID_CMD);
2300 2300
2301 2301 lock_clear(&apic_ioapic_lock);
2302 2302 intr_restore(iflag);
2303 2303 }
2304 2304
2305 2305 /* apic_state() is currently invoked only in Suspend/Resume */
2306 2306 apic_cpus[cpuid].aci_status |= APIC_CPU_SUSPEND;
2307 2307 }
2308 2308
2309 2309 static void
2310 2310 apic_restore_state(struct apic_state *sp)
2311 2311 {
2312 2312 int i;
2313 2313 ulong_t iflag;
2314 2314
2315 2315 /*
2316 2316 * First the local APIC.
2317 2317 */
2318 2318 apic_reg_ops->apic_write_task_reg(sp->as_task_reg);
2319 2319 if (apic_mode == LOCAL_APIC) {
2320 2320 apic_reg_ops->apic_write(APIC_DEST_REG, sp->as_dest_reg);
2321 2321 apic_reg_ops->apic_write(APIC_FORMAT_REG, sp->as_format_reg);
2322 2322 }
2323 2323 apic_reg_ops->apic_write(APIC_LOCAL_TIMER, sp->as_local_timer);
2324 2324 apic_reg_ops->apic_write(APIC_PCINT_VECT, sp->as_pcint_vect);
2325 2325 apic_reg_ops->apic_write(APIC_INT_VECT0, sp->as_int_vect0);
2326 2326 apic_reg_ops->apic_write(APIC_INT_VECT1, sp->as_int_vect1);
2327 2327 apic_reg_ops->apic_write(APIC_ERR_VECT, sp->as_err_vect);
2328 2328 apic_reg_ops->apic_write(APIC_INIT_COUNT, sp->as_init_count);
2329 2329 apic_reg_ops->apic_write(APIC_DIVIDE_REG, sp->as_divide_reg);
2330 2330 apic_reg_ops->apic_write(APIC_SPUR_INT_REG, sp->as_spur_int_reg);
2331 2331
2332 2332 /*
2333 2333 * the following only needs to be done once, so we do it on the
2334 2334 * boot processor, since we know that we only have one of those
2335 2335 */
2336 2336 if (psm_get_cpu_id() == 0) {
2337 2337
2338 2338 iflag = intr_clear();
2339 2339 lock_set(&apic_ioapic_lock);
2340 2340
2341 2341 /* Restore IOAPICs' APIC IDs */
2342 2342 for (i = 0; i < apic_io_max; i++) {
2343 2343 ioapic_write(i, APIC_ID_CMD, sp->as_ioapic_ids[i]);
2344 2344 }
2345 2345
2346 2346 lock_clear(&apic_ioapic_lock);
2347 2347 intr_restore(iflag);
2348 2348
2349 2349 /*
2350 2350 * Reenter APIC mode before restoring LNK devices
2351 2351 */
2352 2352 (void) apic_acpi_enter_apicmode();
2353 2353
2354 2354 /*
2355 2355 * restore acpi link device mappings
2356 2356 */
2357 2357 acpi_restore_link_devices();
2358 2358 }
2359 2359 }
2360 2360
2361 2361 /*
2362 2362 * Returns 0 on success
2363 2363 */
2364 2364 int
2365 2365 apic_state(psm_state_request_t *rp)
2366 2366 {
2367 2367 PMD(PMD_SX, ("apic_state "))
2368 2368 switch (rp->psr_cmd) {
2369 2369 case PSM_STATE_ALLOC:
2370 2370 rp->req.psm_state_req.psr_state =
2371 2371 kmem_zalloc(sizeof (struct apic_state), KM_NOSLEEP);
2372 2372 if (rp->req.psm_state_req.psr_state == NULL)
2373 2373 return (ENOMEM);
2374 2374 rp->req.psm_state_req.psr_state_size =
2375 2375 sizeof (struct apic_state);
2376 2376 PMD(PMD_SX, (":STATE_ALLOC: state %p, size %lx\n",
2377 2377 rp->req.psm_state_req.psr_state,
2378 2378 rp->req.psm_state_req.psr_state_size))
2379 2379 return (0);
2380 2380
2381 2381 case PSM_STATE_FREE:
2382 2382 kmem_free(rp->req.psm_state_req.psr_state,
2383 2383 rp->req.psm_state_req.psr_state_size);
2384 2384 PMD(PMD_SX, (" STATE_FREE: state %p, size %lx\n",
2385 2385 rp->req.psm_state_req.psr_state,
2386 2386 rp->req.psm_state_req.psr_state_size))
2387 2387 return (0);
2388 2388
2389 2389 case PSM_STATE_SAVE:
2390 2390 PMD(PMD_SX, (" STATE_SAVE: state %p, size %lx\n",
2391 2391 rp->req.psm_state_req.psr_state,
2392 2392 rp->req.psm_state_req.psr_state_size))
2393 2393 apic_save_state(rp->req.psm_state_req.psr_state);
2394 2394 return (0);
2395 2395
2396 2396 case PSM_STATE_RESTORE:
2397 2397 apic_restore_state(rp->req.psm_state_req.psr_state);
2398 2398 PMD(PMD_SX, (" STATE_RESTORE: state %p, size %lx\n",
2399 2399 rp->req.psm_state_req.psr_state,
2400 2400 rp->req.psm_state_req.psr_state_size))
2401 2401 return (0);
2402 2402
2403 2403 default:
2404 2404 return (EINVAL);
2405 2405 }
2406 2406 }
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