1 /*
2 * Copyright 2010 Sun Microsystems, Inc. All rights reserved.
3 * Use is subject to license terms.
4 */
5
6 /*
7 * Copyright (c) 2008 Weongyo Jeong
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 *
21 * NO WARRANTY
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
25 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
26 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
27 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
30 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
32 * THE POSSIBILITY OF SUCH DAMAGES.
33 */
34 #include <sys/sysmacros.h>
35 #include <sys/strsubr.h>
36 #include <sys/strsun.h>
37 #include <sys/mac_provider.h>
38 #include <sys/mac_wifi.h>
39 #include <sys/net80211.h>
40 #define USBDRV_MAJOR_VER 2
41 #define USBDRV_MINOR_VER 0
42 #include <sys/usb/usba.h>
43 #include <sys/usb/usba/usba_types.h>
44
45 #include "urtw_reg.h"
46 #include "urtw_var.h"
47
48 static void *urtw_soft_state_p = NULL;
49
50 #define URTW_TXBUF_SIZE (IEEE80211_MAX_LEN)
51 #define URTW_RXBUF_SIZE (URTW_TXBUF_SIZE)
52 /*
53 * device operations
54 */
55 static int urtw_attach(dev_info_t *, ddi_attach_cmd_t);
56 static int urtw_detach(dev_info_t *, ddi_detach_cmd_t);
57
58 /*
59 * Module Loading Data & Entry Points
60 */
61 DDI_DEFINE_STREAM_OPS(urtw_dev_ops, nulldev, nulldev, urtw_attach,
62 urtw_detach, nodev, NULL, D_MP, NULL, ddi_quiesce_not_needed);
63
64 static struct modldrv urtw_modldrv = {
65 &mod_driverops, /* Type of module. This one is a driver */
66 "RTL8187L/B driver v1.2", /* short description */
67 &urtw_dev_ops /* driver specific ops */
68 };
69
70 static struct modlinkage modlinkage = {
71 MODREV_1,
72 { (void *)&urtw_modldrv, NULL }
73 };
74
75 static int urtw_m_stat(void *, uint_t, uint64_t *);
76 static int urtw_m_start(void *);
77 static void urtw_m_stop(void *);
78 static int urtw_m_promisc(void *, boolean_t);
79 static int urtw_m_multicst(void *, boolean_t, const uint8_t *);
80 static int urtw_m_unicst(void *, const uint8_t *);
81 static mblk_t *urtw_m_tx(void *, mblk_t *);
82 static void urtw_m_ioctl(void *, queue_t *, mblk_t *);
83 static int urtw_m_setprop(void *, const char *, mac_prop_id_t,
84 uint_t, const void *);
85 static int urtw_m_getprop(void *, const char *, mac_prop_id_t,
86 uint_t, void *);
87 static void urtw_m_propinfo(void *, const char *, mac_prop_id_t,
88 mac_prop_info_handle_t);
89
90 static mac_callbacks_t urtw_m_callbacks = {
91 MC_IOCTL | MC_SETPROP | MC_GETPROP | MC_PROPINFO,
92 urtw_m_stat,
93 urtw_m_start,
94 urtw_m_stop,
95 urtw_m_promisc,
96 urtw_m_multicst,
97 urtw_m_unicst,
98 urtw_m_tx,
99 NULL,
100 urtw_m_ioctl,
101 NULL,
102 NULL,
103 NULL,
104 urtw_m_setprop,
105 urtw_m_getprop,
106 urtw_m_propinfo
107 };
108
109 static int urtw_tx_start(struct urtw_softc *, mblk_t *, int);
110 static int urtw_rx_start(struct urtw_softc *);
111
112
113 /*
114 * Supported rates for 802.11b/g modes (in 500Kbps unit).
115 */
116 static const struct ieee80211_rateset urtw_rateset_11b =
117 { 4, { 2, 4, 11, 22 } };
118
119 static const struct ieee80211_rateset urtw_rateset_11g =
120 { 12, { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 } };
121
122 #define USB_VENDOR_DICKSMITH 0x1371 /* Dick Smith Electronics */
123 #define USB_VENDOR_LOGITEC 0x0789 /* Logitec */
124 #define USB_VENDOR_NETGEAR 0x0846 /* BayNETGEAR */
125 #define USB_VENDOR_REALTEK 0x0bda /* Realtek */
126 #define USB_VENDOR_SPHAIRON 0x114b /* Sphairon Access Systems */
127 #define USB_VENDOR_SURECOM 0x0769 /* Surecom Technology */
128 #define USB_VENDOR_BELKIN 0x050d /* Belkin Components */
129 #define USB_VENDOR_SITECOMEU 0x0df6 /* Sitecom Europe */
130
131 #define USB_PRODUCT_SPHAIRON_RTL8187 0x0150 /* RTL8187 */
132 #define USB_PRODUCT_DICKSMITH_RTL8187 0x9401 /* RTL8187 */
133 #define USB_PRODUCT_LOGITEC_RTL8187 0x010c /* RTL8187 */
134 #define USB_PRODUCT_REALTEK_RTL8187 0x8187 /* RTL8187 */
135 #define USB_PRODUCT_NETGEAR_WG111V2 0x6a00 /* WG111v2 */
136 #define USB_PRODUCT_SURECOM_EP9001G2A 0x11f2 /* EP-9001-G rev 2A */
137 #define USB_PRODUCT_BELKIN_F5D7050E 0x705e /* F5D705E 54g */
138 #define USB_PRODUCT_NETGEAR_WG111V3 0x4260 /* WG111v3 */
139 #define USB_PRODUCT_REALTEK_RTL8187B_0 0x8189 /* RTL8187B */
140 #define USB_PRODUCT_REALTEK_RTL8187B_1 0x8197 /* RTL8187B */
141 #define USB_PRODUCT_REALTEK_RTL8187B_2 0x8198 /* RTL8187B */
142 #define USB_PRODUCT_SITECOMEU_WL168 0x0028 /* WL-168 */
143
144 #define USB_PRODUCT_ANY 0xffff
145
146 struct usb_devno {
147 uint16_t v;
148 uint16_t p;
149 };
150
151 /*
152 * Recognized device vendors/products.
153 */
154 static struct urtw_type {
155 struct usb_devno dev;
156 uint8_t rev;
157 } urtw_devs[] = {
158 #define URTW_DEV_RTL8187(v, p) \
159 { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, URTW_HWREV_8187 }
160 #define URTW_DEV_RTL8187B(v, p) \
161 { { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }, URTW_HWREV_8187B }
162 /* Realtek RTL8187 devices. */
163 URTW_DEV_RTL8187(DICKSMITH, RTL8187),
164 URTW_DEV_RTL8187(LOGITEC, RTL8187),
165 URTW_DEV_RTL8187(NETGEAR, WG111V2),
166 URTW_DEV_RTL8187(REALTEK, RTL8187),
167 URTW_DEV_RTL8187(SPHAIRON, RTL8187),
168 URTW_DEV_RTL8187(SURECOM, EP9001G2A),
169 /* Realtek RTL8187B devices. */
170 URTW_DEV_RTL8187B(BELKIN, F5D7050E),
171 URTW_DEV_RTL8187B(NETGEAR, WG111V3),
172 URTW_DEV_RTL8187B(REALTEK, RTL8187B_0),
173 URTW_DEV_RTL8187B(REALTEK, RTL8187B_1),
174 URTW_DEV_RTL8187B(REALTEK, RTL8187B_2),
175 URTW_DEV_RTL8187B(SITECOMEU, WL168)
176 #undef URTW_DEV_RTL8187
177 #undef URTW_DEV_RTL8187B
178 };
179
180 /*
181 * Search for a vendor/product pair in an array. The item size is
182 * given as an argument.
183 */
184 struct urtw_type *
185 usb_match_device(struct urtw_type *tbl, uint32_t nentries,
186 uint16_t vendor, uint16_t product)
187 {
188 while (nentries-- > 0) {
189 uint16_t tproduct = tbl[nentries].dev.p;
190 if (tbl[nentries].dev.v == vendor &&
191 (tproduct == product || tproduct == USB_PRODUCT_ANY))
192 return (&tbl[nentries]);
193 }
194 return (NULL);
195 }
196
197 #define usb_lookup(tbl, vendor, product) \
198 usb_match_device(tbl, sizeof (tbl) / sizeof ((tbl)[0]), \
199 (vendor), (product))
200
201 #define urtw_lookup(v, p) (usb_lookup(urtw_devs, v, p))
202
203 struct urtw_pair {
204 uint32_t reg;
205 uint32_t val;
206 };
207
208 struct urtw_pair_idx {
209 uint8_t reg;
210 uint8_t val;
211 uint8_t idx;
212 };
213
214 static struct urtw_pair_idx urtw_8187b_regtbl[] = {
215 { 0xf0, 0x32, 0 }, { 0xf1, 0x32, 0 }, { 0xf2, 0x00, 0 },
216 { 0xf3, 0x00, 0 }, { 0xf4, 0x32, 0 }, { 0xf5, 0x43, 0 },
217 { 0xf6, 0x00, 0 }, { 0xf7, 0x00, 0 }, { 0xf8, 0x46, 0 },
218 { 0xf9, 0xa4, 0 }, { 0xfa, 0x00, 0 }, { 0xfb, 0x00, 0 },
219 { 0xfc, 0x96, 0 }, { 0xfd, 0xa4, 0 }, { 0xfe, 0x00, 0 },
220 { 0xff, 0x00, 0 },
221
222 { 0x58, 0x4b, 1 }, { 0x59, 0x00, 1 }, { 0x5a, 0x4b, 1 },
223 { 0x5b, 0x00, 1 }, { 0x60, 0x4b, 1 }, { 0x61, 0x09, 1 },
224 { 0x62, 0x4b, 1 }, { 0x63, 0x09, 1 }, { 0xce, 0x0f, 1 },
225 { 0xcf, 0x00, 1 }, { 0xe0, 0xff, 1 }, { 0xe1, 0x0f, 1 },
226 { 0xe2, 0x00, 1 }, { 0xf0, 0x4e, 1 }, { 0xf1, 0x01, 1 },
227 { 0xf2, 0x02, 1 }, { 0xf3, 0x03, 1 }, { 0xf4, 0x04, 1 },
228 { 0xf5, 0x05, 1 }, { 0xf6, 0x06, 1 }, { 0xf7, 0x07, 1 },
229 { 0xf8, 0x08, 1 },
230
231 { 0x4e, 0x00, 2 }, { 0x0c, 0x04, 2 }, { 0x21, 0x61, 2 },
232 { 0x22, 0x68, 2 }, { 0x23, 0x6f, 2 }, { 0x24, 0x76, 2 },
233 { 0x25, 0x7d, 2 }, { 0x26, 0x84, 2 }, { 0x27, 0x8d, 2 },
234 { 0x4d, 0x08, 2 }, { 0x50, 0x05, 2 }, { 0x51, 0xf5, 2 },
235 { 0x52, 0x04, 2 }, { 0x53, 0xa0, 2 }, { 0x54, 0x1f, 2 },
236 { 0x55, 0x23, 2 }, { 0x56, 0x45, 2 }, { 0x57, 0x67, 2 },
237 { 0x58, 0x08, 2 }, { 0x59, 0x08, 2 }, { 0x5a, 0x08, 2 },
238 { 0x5b, 0x08, 2 }, { 0x60, 0x08, 2 }, { 0x61, 0x08, 2 },
239 { 0x62, 0x08, 2 }, { 0x63, 0x08, 2 }, { 0x64, 0xcf, 2 },
240 { 0x72, 0x56, 2 }, { 0x73, 0x9a, 2 },
241
242 { 0x34, 0xf0, 0 }, { 0x35, 0x0f, 0 }, { 0x5b, 0x40, 0 },
243 { 0x84, 0x88, 0 }, { 0x85, 0x24, 0 }, { 0x88, 0x54, 0 },
244 { 0x8b, 0xb8, 0 }, { 0x8c, 0x07, 0 }, { 0x8d, 0x00, 0 },
245 { 0x94, 0x1b, 0 }, { 0x95, 0x12, 0 }, { 0x96, 0x00, 0 },
246 { 0x97, 0x06, 0 }, { 0x9d, 0x1a, 0 }, { 0x9f, 0x10, 0 },
247 { 0xb4, 0x22, 0 }, { 0xbe, 0x80, 0 }, { 0xdb, 0x00, 0 },
248 { 0xee, 0x00, 0 }, { 0x91, 0x03, 0 },
249
250 { 0x4c, 0x00, 2 }, { 0x9f, 0x00, 3 }, { 0x8c, 0x01, 0 },
251 { 0x8d, 0x10, 0 }, { 0x8e, 0x08, 0 }, { 0x8f, 0x00, 0 }
252 };
253
254 static uint8_t urtw_8225_agc[] = {
255 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9d, 0x9c, 0x9b,
256 0x9a, 0x99, 0x98, 0x97, 0x96, 0x95, 0x94, 0x93, 0x92, 0x91, 0x90,
257 0x8f, 0x8e, 0x8d, 0x8c, 0x8b, 0x8a, 0x89, 0x88, 0x87, 0x86, 0x85,
258 0x84, 0x83, 0x82, 0x81, 0x80, 0x3f, 0x3e, 0x3d, 0x3c, 0x3b, 0x3a,
259 0x39, 0x38, 0x37, 0x36, 0x35, 0x34, 0x33, 0x32, 0x31, 0x30, 0x2f,
260 0x2e, 0x2d, 0x2c, 0x2b, 0x2a, 0x29, 0x28, 0x27, 0x26, 0x25, 0x24,
261 0x23, 0x22, 0x21, 0x20, 0x1f, 0x1e, 0x1d, 0x1c, 0x1b, 0x1a, 0x19,
262 0x18, 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e,
263 0x0d, 0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x07, 0x06, 0x05, 0x04, 0x03,
264 0x02, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
265 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
266 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01
267 };
268
269 static uint8_t urtw_8225v2_agc[] = {
270 0x5e, 0x5e, 0x5e, 0x5e, 0x5d, 0x5b, 0x59, 0x57,
271 0x55, 0x53, 0x51, 0x4f, 0x4d, 0x4b, 0x49, 0x47,
272 0x45, 0x43, 0x41, 0x3f, 0x3d, 0x3b, 0x39, 0x37,
273 0x35, 0x33, 0x31, 0x2f, 0x2d, 0x2b, 0x29, 0x27,
274 0x25, 0x23, 0x21, 0x1f, 0x1d, 0x1b, 0x19, 0x17,
275 0x15, 0x13, 0x11, 0x0f, 0x0d, 0x0b, 0x09, 0x07,
276 0x05, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
277 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
278 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19,
279 0x19, 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26,
280 0x26, 0x27, 0x27, 0x28, 0x28, 0x29, 0x2a, 0x2a,
281 0x2a, 0x2b, 0x2b, 0x2b, 0x2c, 0x2c, 0x2c, 0x2d,
282 0x2d, 0x2d, 0x2d, 0x2e, 0x2e, 0x2e, 0x2e, 0x2f,
283 0x2f, 0x2f, 0x30, 0x30, 0x31, 0x31, 0x31, 0x31,
284 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31,
285 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31
286 };
287
288 static uint8_t urtw_8225v2_ofdm[] = {
289 0x10, 0x0d, 0x01, 0x00, 0x14, 0xfb, 0xfb, 0x60,
290 0x00, 0x60, 0x00, 0x00, 0x00, 0x5c, 0x00, 0x00,
291 0x40, 0x00, 0x40, 0x00, 0x00, 0x00, 0xa8, 0x26,
292 0x32, 0x33, 0x07, 0xa5, 0x6f, 0x55, 0xc8, 0xb3,
293 0x0a, 0xe1, 0x2c, 0x8a, 0x86, 0x83, 0x34, 0x0f,
294 0x4f, 0x24, 0x6f, 0xc2, 0x6b, 0x40, 0x80, 0x00,
295 0xc0, 0xc1, 0x58, 0xf1, 0x00, 0xe4, 0x90, 0x3e,
296 0x6d, 0x3c, 0xfb, 0x07
297 };
298
299 static uint32_t urtw_8225_channel[] = {
300 0x0000, /* dummy channel 0 */
301 0x085c, /* 1 */
302 0x08dc, /* 2 */
303 0x095c, /* 3 */
304 0x09dc, /* 4 */
305 0x0a5c, /* 5 */
306 0x0adc, /* 6 */
307 0x0b5c, /* 7 */
308 0x0bdc, /* 8 */
309 0x0c5c, /* 9 */
310 0x0cdc, /* 10 */
311 0x0d5c, /* 11 */
312 0x0ddc, /* 12 */
313 0x0e5c, /* 13 */
314 0x0f72, /* 14 */
315 };
316
317 static uint8_t urtw_8225_gain[] = {
318 0x23, 0x88, 0x7c, 0xa5, /* -82dbm */
319 0x23, 0x88, 0x7c, 0xb5, /* -82dbm */
320 0x23, 0x88, 0x7c, 0xc5, /* -82dbm */
321 0x33, 0x80, 0x79, 0xc5, /* -78dbm */
322 0x43, 0x78, 0x76, 0xc5, /* -74dbm */
323 0x53, 0x60, 0x73, 0xc5, /* -70dbm */
324 0x63, 0x58, 0x70, 0xc5, /* -66dbm */
325 };
326
327 static struct urtw_pair urtw_8225_rf_part1[] = {
328 { 0x00, 0x0067 }, { 0x01, 0x0fe0 }, { 0x02, 0x044d }, { 0x03, 0x0441 },
329 { 0x04, 0x0486 }, { 0x05, 0x0bc0 }, { 0x06, 0x0ae6 }, { 0x07, 0x082a },
330 { 0x08, 0x001f }, { 0x09, 0x0334 }, { 0x0a, 0x0fd4 }, { 0x0b, 0x0391 },
331 { 0x0c, 0x0050 }, { 0x0d, 0x06db }, { 0x0e, 0x0029 }, { 0x0f, 0x0914 },
332 };
333
334 static struct urtw_pair urtw_8225_rf_part2[] = {
335 { 0x00, 0x01 }, { 0x01, 0x02 }, { 0x02, 0x42 }, { 0x03, 0x00 },
336 { 0x04, 0x00 }, { 0x05, 0x00 }, { 0x06, 0x40 }, { 0x07, 0x00 },
337 { 0x08, 0x40 }, { 0x09, 0xfe }, { 0x0a, 0x09 }, { 0x0b, 0x80 },
338 { 0x0c, 0x01 }, { 0x0e, 0xd3 }, { 0x0f, 0x38 }, { 0x10, 0x84 },
339 { 0x11, 0x06 }, { 0x12, 0x20 }, { 0x13, 0x20 }, { 0x14, 0x00 },
340 { 0x15, 0x40 }, { 0x16, 0x00 }, { 0x17, 0x40 }, { 0x18, 0xef },
341 { 0x19, 0x19 }, { 0x1a, 0x20 }, { 0x1b, 0x76 }, { 0x1c, 0x04 },
342 { 0x1e, 0x95 }, { 0x1f, 0x75 }, { 0x20, 0x1f }, { 0x21, 0x27 },
343 { 0x22, 0x16 }, { 0x24, 0x46 }, { 0x25, 0x20 }, { 0x26, 0x90 },
344 { 0x27, 0x88 }
345 };
346
347 static struct urtw_pair urtw_8225_rf_part3[] = {
348 { 0x00, 0x98 }, { 0x03, 0x20 }, { 0x04, 0x7e }, { 0x05, 0x12 },
349 { 0x06, 0xfc }, { 0x07, 0x78 }, { 0x08, 0x2e }, { 0x10, 0x9b },
350 { 0x11, 0x88 }, { 0x12, 0x47 }, { 0x13, 0xd0 }, { 0x19, 0x00 },
351 { 0x1a, 0xa0 }, { 0x1b, 0x08 }, { 0x40, 0x86 }, { 0x41, 0x8d },
352 { 0x42, 0x15 }, { 0x43, 0x18 }, { 0x44, 0x1f }, { 0x45, 0x1e },
353 { 0x46, 0x1a }, { 0x47, 0x15 }, { 0x48, 0x10 }, { 0x49, 0x0a },
354 { 0x4a, 0x05 }, { 0x4b, 0x02 }, { 0x4c, 0x05 }
355 };
356
357 static uint16_t urtw_8225_rxgain[] = {
358 0x0400, 0x0401, 0x0402, 0x0403, 0x0404, 0x0405, 0x0408, 0x0409,
359 0x040a, 0x040b, 0x0502, 0x0503, 0x0504, 0x0505, 0x0540, 0x0541,
360 0x0542, 0x0543, 0x0544, 0x0545, 0x0580, 0x0581, 0x0582, 0x0583,
361 0x0584, 0x0585, 0x0588, 0x0589, 0x058a, 0x058b, 0x0643, 0x0644,
362 0x0645, 0x0680, 0x0681, 0x0682, 0x0683, 0x0684, 0x0685, 0x0688,
363 0x0689, 0x068a, 0x068b, 0x068c, 0x0742, 0x0743, 0x0744, 0x0745,
364 0x0780, 0x0781, 0x0782, 0x0783, 0x0784, 0x0785, 0x0788, 0x0789,
365 0x078a, 0x078b, 0x078c, 0x078d, 0x0790, 0x0791, 0x0792, 0x0793,
366 0x0794, 0x0795, 0x0798, 0x0799, 0x079a, 0x079b, 0x079c, 0x079d,
367 0x07a0, 0x07a1, 0x07a2, 0x07a3, 0x07a4, 0x07a5, 0x07a8, 0x07a9,
368 0x07aa, 0x07ab, 0x07ac, 0x07ad, 0x07b0, 0x07b1, 0x07b2, 0x07b3,
369 0x07b4, 0x07b5, 0x07b8, 0x07b9, 0x07ba, 0x07bb, 0x07bb
370 };
371
372 static uint8_t urtw_8225_threshold[] = {
373 0x8d, 0x8d, 0x8d, 0x8d, 0x9d, 0xad, 0xbd,
374 };
375
376 static uint8_t urtw_8225_tx_gain_cck_ofdm[] = {
377 0x02, 0x06, 0x0e, 0x1e, 0x3e, 0x7e
378 };
379
380 static uint8_t urtw_8225_txpwr_cck[] = {
381 0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02,
382 0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02,
383 0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02,
384 0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02,
385 0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03,
386 0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03
387 };
388
389 static uint8_t urtw_8225_txpwr_cck_ch14[] = {
390 0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00,
391 0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00,
392 0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00,
393 0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00,
394 0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00,
395 0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00
396 };
397
398 static uint8_t urtw_8225_txpwr_ofdm[] = {
399 0x80, 0x90, 0xa2, 0xb5, 0xcb, 0xe4
400 };
401
402 static uint8_t urtw_8225v2_gain_bg[] = {
403 0x23, 0x15, 0xa5, /* -82-1dbm */
404 0x23, 0x15, 0xb5, /* -82-2dbm */
405 0x23, 0x15, 0xc5, /* -82-3dbm */
406 0x33, 0x15, 0xc5, /* -78dbm */
407 0x43, 0x15, 0xc5, /* -74dbm */
408 0x53, 0x15, 0xc5, /* -70dbm */
409 0x63, 0x15, 0xc5, /* -66dbm */
410 };
411
412 static struct urtw_pair urtw_8225v2_rf_part1[] = {
413 { 0x00, 0x02bf }, { 0x01, 0x0ee0 }, { 0x02, 0x044d }, { 0x03, 0x0441 },
414 { 0x04, 0x08c3 }, { 0x05, 0x0c72 }, { 0x06, 0x00e6 }, { 0x07, 0x082a },
415 { 0x08, 0x003f }, { 0x09, 0x0335 }, { 0x0a, 0x09d4 }, { 0x0b, 0x07bb },
416 { 0x0c, 0x0850 }, { 0x0d, 0x0cdf }, { 0x0e, 0x002b }, { 0x0f, 0x0114 }
417 };
418
419 static struct urtw_pair urtw_8225v2_rf_part2[] = {
420 { 0x00, 0x01 }, { 0x01, 0x02 }, { 0x02, 0x42 }, { 0x03, 0x00 },
421 { 0x04, 0x00 }, { 0x05, 0x00 }, { 0x06, 0x40 }, { 0x07, 0x00 },
422 { 0x08, 0x40 }, { 0x09, 0xfe }, { 0x0a, 0x08 }, { 0x0b, 0x80 },
423 { 0x0c, 0x01 }, { 0x0d, 0x43 }, { 0x0e, 0xd3 }, { 0x0f, 0x38 },
424 { 0x10, 0x84 }, { 0x11, 0x07 }, { 0x12, 0x20 }, { 0x13, 0x20 },
425 { 0x14, 0x00 }, { 0x15, 0x40 }, { 0x16, 0x00 }, { 0x17, 0x40 },
426 { 0x18, 0xef }, { 0x19, 0x19 }, { 0x1a, 0x20 }, { 0x1b, 0x15 },
427 { 0x1c, 0x04 }, { 0x1d, 0xc5 }, { 0x1e, 0x95 }, { 0x1f, 0x75 },
428 { 0x20, 0x1f }, { 0x21, 0x17 }, { 0x22, 0x16 }, { 0x23, 0x80 },
429 { 0x24, 0x46 }, { 0x25, 0x00 }, { 0x26, 0x90 }, { 0x27, 0x88 }
430 };
431
432 static struct urtw_pair urtw_8225v2_rf_part3[] = {
433 { 0x00, 0x98 }, { 0x03, 0x20 }, { 0x04, 0x7e }, { 0x05, 0x12 },
434 { 0x06, 0xfc }, { 0x07, 0x78 }, { 0x08, 0x2e }, { 0x09, 0x11 },
435 { 0x0a, 0x17 }, { 0x0b, 0x11 }, { 0x10, 0x9b }, { 0x11, 0x88 },
436 { 0x12, 0x47 }, { 0x13, 0xd0 }, { 0x19, 0x00 }, { 0x1a, 0xa0 },
437 { 0x1b, 0x08 }, { 0x1d, 0x00 }, { 0x40, 0x86 }, { 0x41, 0x9d },
438 { 0x42, 0x15 }, { 0x43, 0x18 }, { 0x44, 0x36 }, { 0x45, 0x35 },
439 { 0x46, 0x2e }, { 0x47, 0x25 }, { 0x48, 0x1c }, { 0x49, 0x12 },
440 { 0x4a, 0x09 }, { 0x4b, 0x04 }, { 0x4c, 0x05 }
441 };
442
443 static uint16_t urtw_8225v2_rxgain[] = {
444 0x0400, 0x0401, 0x0402, 0x0403, 0x0404, 0x0405, 0x0408, 0x0409,
445 0x040a, 0x040b, 0x0502, 0x0503, 0x0504, 0x0505, 0x0540, 0x0541,
446 0x0542, 0x0543, 0x0544, 0x0545, 0x0580, 0x0581, 0x0582, 0x0583,
447 0x0584, 0x0585, 0x0588, 0x0589, 0x058a, 0x058b, 0x0643, 0x0644,
448 0x0645, 0x0680, 0x0681, 0x0682, 0x0683, 0x0684, 0x0685, 0x0688,
449 0x0689, 0x068a, 0x068b, 0x068c, 0x0742, 0x0743, 0x0744, 0x0745,
450 0x0780, 0x0781, 0x0782, 0x0783, 0x0784, 0x0785, 0x0788, 0x0789,
451 0x078a, 0x078b, 0x078c, 0x078d, 0x0790, 0x0791, 0x0792, 0x0793,
452 0x0794, 0x0795, 0x0798, 0x0799, 0x079a, 0x079b, 0x079c, 0x079d,
453 0x07a0, 0x07a1, 0x07a2, 0x07a3, 0x07a4, 0x07a5, 0x07a8, 0x07a9,
454 0x03aa, 0x03ab, 0x03ac, 0x03ad, 0x03b0, 0x03b1, 0x03b2, 0x03b3,
455 0x03b4, 0x03b5, 0x03b8, 0x03b9, 0x03ba, 0x03bb, 0x03bb
456 };
457
458 static uint8_t urtw_8225v2_tx_gain_cck_ofdm[] = {
459 0x00, 0x01, 0x02, 0x03, 0x04, 0x05,
460 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b,
461 0x0c, 0x0d, 0x0e, 0x0f, 0x10, 0x11,
462 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
463 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d,
464 0x1e, 0x1f, 0x20, 0x21, 0x22, 0x23,
465 };
466
467 static uint8_t urtw_8225v2_txpwr_cck[] = {
468 0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04,
469 0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03,
470 0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03,
471 0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03
472 };
473
474 static uint8_t urtw_8225v2_txpwr_cck_ch14[] = {
475 0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00,
476 0x30, 0x2f, 0x29, 0x15, 0x00, 0x00, 0x00, 0x00,
477 0x30, 0x2f, 0x29, 0x15, 0x00, 0x00, 0x00, 0x00,
478 0x30, 0x2f, 0x29, 0x15, 0x00, 0x00, 0x00, 0x00
479 };
480
481 static struct urtw_pair urtw_8225v2_b_rf[] = {
482 { 0x00, 0x00b7 }, { 0x01, 0x0ee0 }, { 0x02, 0x044d }, { 0x03, 0x0441 },
483 { 0x04, 0x08c3 }, { 0x05, 0x0c72 }, { 0x06, 0x00e6 }, { 0x07, 0x082a },
484 { 0x08, 0x003f }, { 0x09, 0x0335 }, { 0x0a, 0x09d4 }, { 0x0b, 0x07bb },
485 { 0x0c, 0x0850 }, { 0x0d, 0x0cdf }, { 0x0e, 0x002b }, { 0x0f, 0x0114 },
486 { 0x00, 0x01b7 }
487 };
488
489 static struct urtw_pair urtw_ratetable[] = {
490 { 2, 0 }, { 4, 1 }, { 11, 2 }, { 12, 4 }, { 18, 5 },
491 { 22, 3 }, { 24, 6 }, { 36, 7 }, { 48, 8 }, { 72, 9 },
492 { 96, 10 }, { 108, 11 }
493 };
494
495 static int urtw_8187_init(void *);
496 static void urtw_stop(struct urtw_softc *);
497 static int urtw_set_channel(struct urtw_softc *);
498 static void
499 urtw_rxeof(usb_pipe_handle_t, usb_bulk_req_t *);
500 static int
501 urtw_newstate(struct ieee80211com *, enum ieee80211_state, int);
502 static usbd_status
503 urtw_read8_c(struct urtw_softc *, int, uint8_t *, uint8_t);
504 static usbd_status
505 urtw_read16_c(struct urtw_softc *, int, uint16_t *, uint8_t);
506 static usbd_status
507 urtw_read32_c(struct urtw_softc *, int, uint32_t *, uint8_t);
508 static usbd_status
509 urtw_write8_c(struct urtw_softc *, int, uint8_t, uint8_t);
510 static usbd_status
511 urtw_write16_c(struct urtw_softc *, int, uint16_t, uint8_t);
512 static usbd_status
513 urtw_write32_c(struct urtw_softc *, int, uint32_t, uint8_t);
514 static usbd_status urtw_eprom_cs(struct urtw_softc *, int);
515 static usbd_status urtw_eprom_ck(struct urtw_softc *);
516 static usbd_status urtw_eprom_sendbits(struct urtw_softc *, int16_t *,
517 int);
518 static usbd_status urtw_eprom_read32(struct urtw_softc *, uint32_t,
519 uint32_t *);
520 static usbd_status urtw_eprom_readbit(struct urtw_softc *, int16_t *);
521 static usbd_status urtw_eprom_writebit(struct urtw_softc *, int16_t);
522 static usbd_status urtw_get_macaddr(struct urtw_softc *);
523 static usbd_status urtw_get_txpwr(struct urtw_softc *);
524 static usbd_status urtw_get_rfchip(struct urtw_softc *);
525 static usbd_status urtw_led_init(struct urtw_softc *);
526 static usbd_status
527 urtw_8225_read(struct urtw_softc *, uint8_t, uint32_t *);
528 static usbd_status urtw_8225_rf_init(struct urtw_rf *);
529 static usbd_status urtw_8225_rf_set_chan(struct urtw_rf *, int);
530 static usbd_status urtw_8225_rf_set_sens(struct urtw_rf *);
531 static usbd_status urtw_8225v2_rf_init(struct urtw_rf *);
532 static usbd_status urtw_8225v2_rf_set_chan(struct urtw_rf *, int);
533 static usbd_status urtw_open_pipes(struct urtw_softc *);
534 static void urtw_close_pipes(struct urtw_softc *);
535 static void urtw_led_launch(void *);
536
537 static void urtw_8187b_update_wmm(struct urtw_softc *);
538 static usbd_status urtw_8187b_reset(struct urtw_softc *);
539 static int urtw_8187b_init(void *);
540 static void urtw_8225v2_b_config_mac(struct urtw_softc *);
541 static void urtw_8225v2_b_init_rfe(struct urtw_softc *);
542 static usbd_status urtw_8225v2_b_update_chan(struct urtw_softc *);
543 static usbd_status urtw_8225v2_b_rf_init(struct urtw_rf *);
544 static usbd_status urtw_8225v2_b_rf_set_chan(struct urtw_rf *, int);
545 static void urtw_8225v2_b_set_txpwrlvl(struct urtw_softc *, int);
546
547 #ifdef DEBUG
548
549 #define URTW_DEBUG_XMIT 0x00000001
550 #define URTW_DEBUG_RECV 0x00000002
551 #define URTW_DEBUG_LED 0x00000004
552 #define URTW_DEBUG_GLD 0x00000008
553 #define URTW_DEBUG_RF 0x00000010
554 #define URTW_DEBUG_ATTACH 0x00000020
555 #define URTW_DEBUG_ACTIVE 0x00000040
556 #define URTW_DEBUG_HWTYPE 0x00000080
557 #define URTW_DEBUG_DEVREQ 0x00000100
558 #define URTW_DEBUG_HOTPLUG 0x00000200
559 #define URTW_DEBUG_STATE 0x00000400
560 #define URTW_DEBUG_TX_PROC 0x00000800
561 #define URTW_DEBUG_RX_PROC 0x00001000
562 #define URTW_DEBUG_EEPROM 0x00002000
563 #define URTW_DEBUG_RESET 0x00004000
564 #define URTW_DEBUG_ANY 0xffffffff
565
566 uint32_t urtw8187_dbg_flags = 0;
567 static void
568 urtw8187_dbg(dev_info_t *dip, int level, const char *fmt, ...)
569 {
570 char msg_buffer[255];
571 va_list ap;
572
573 if (dip == NULL) {
574 return;
575 }
576
577 va_start(ap, fmt);
578 (void) vsprintf(msg_buffer, fmt, ap);
579 cmn_err(level, "%s%d: %s", ddi_get_name(dip),
580 ddi_get_instance(dip), msg_buffer);
581 va_end(ap);
582 }
583
584 #define URTW8187_DBG(l, x) do {\
585 _NOTE(CONSTANTCONDITION) \
586 if ((l) & urtw8187_dbg_flags) \
587 urtw8187_dbg x;\
588 _NOTE(CONSTANTCONDITION) \
589 } while (0)
590 #else
591 #define URTW8187_DBG(l, x)
592 #endif
593
594 static usbd_status
595 urtw_led_init(struct urtw_softc *sc)
596 {
597 uint32_t rev;
598 usbd_status error;
599
600 if (error = urtw_read8_c(sc, URTW_PSR, &sc->sc_psr, 0))
601 goto fail;
602 error = urtw_eprom_read32(sc, URTW_EPROM_SWREV, &rev);
603 if (error != 0)
604 goto fail;
605
606 switch (rev & URTW_EPROM_CID_MASK) {
607 case URTW_EPROM_CID_ALPHA0:
608 sc->sc_strategy = URTW_SW_LED_MODE1;
609 break;
610 case URTW_EPROM_CID_SERCOMM_PS:
611 sc->sc_strategy = URTW_SW_LED_MODE3;
612 break;
613 case URTW_EPROM_CID_HW_LED:
614 sc->sc_strategy = URTW_HW_LED;
615 break;
616 case URTW_EPROM_CID_RSVD0:
617 case URTW_EPROM_CID_RSVD1:
618 default:
619 sc->sc_strategy = URTW_SW_LED_MODE0;
620 break;
621 }
622
623 sc->sc_gpio_ledpin = URTW_LED_PIN_GPIO0;
624
625 fail:
626 return (error);
627 }
628
629 static usbd_status
630 urtw_8225_write_s16(struct urtw_softc *sc, uint8_t addr, int index,
631 uint16_t *data)
632 {
633 usb_ctrl_setup_t req;
634 usb_cr_t cr;
635 usb_cb_flags_t cf;
636 mblk_t *mp = 0;
637 uint16_t data16;
638 usbd_status error;
639
640 data16 = *data;
641 bzero(&req, sizeof (req));
642 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
643 req.bRequest = URTW_8187_SETREGS_REQ;
644 req.wValue = addr;
645 req.wIndex = (uint16_t)index;
646 req.wLength = sizeof (uint16_t);
647 req.attrs = USB_ATTRS_NONE;
648
649 mp = allocb(sizeof (uint16_t), BPRI_MED);
650 if (mp == 0) {
651 cmn_err(CE_WARN, "urtw_8225_write_s16: allocb failed\n");
652 return (-1);
653 }
654 *(mp->b_rptr) = (data16 & 0x00ff);
655 *(mp->b_rptr + 1) = (data16 & 0xff00) >> 8;
656 mp->b_wptr += sizeof (uint16_t);
657 error = usb_pipe_ctrl_xfer_wait(sc->sc_udev->dev_default_ph, &req, &mp,
658 &cr, &cf, 0);
659 if (error != USB_SUCCESS) {
660 URTW8187_DBG(URTW_DEBUG_DEVREQ, (sc->sc_dev, CE_CONT,
661 "urtw_8225_write_s16: could not set regs:"
662 "cr:%s(%d), cf:(%x)\n", usb_str_cr(cr), cr, cf));
663 }
664 if (mp)
665 freemsg(mp);
666 return (error);
667
668 }
669
670 static usbd_status
671 urtw_8225_read(struct urtw_softc *sc, uint8_t addr, uint32_t *data)
672 {
673 int i;
674 int16_t bit;
675 uint8_t rlen = 12, wlen = 6;
676 uint16_t o1, o2, o3, tmp;
677 uint32_t d2w = ((uint32_t)(addr & 0x1f)) << 27;
678 uint32_t mask = 0x80000000, value = 0;
679 usbd_status error;
680
681 if (error = urtw_read16_c(sc, URTW_RF_PINS_OUTPUT, &o1, 0))
682 goto fail;
683 if (error = urtw_read16_c(sc, URTW_RF_PINS_ENABLE, &o2, 0))
684 goto fail;
685 if (error = urtw_read16_c(sc, URTW_RF_PINS_SELECT, &o3, 0))
686 goto fail;
687 if (error = urtw_write16_c(sc, URTW_RF_PINS_ENABLE, o2 | 0xf, 0))
688 goto fail;
689 if (error = urtw_write16_c(sc, URTW_RF_PINS_SELECT, o3 | 0xf, 0))
690 goto fail;
691 o1 &= ~0xf;
692 if (error = urtw_write16_c(sc, URTW_RF_PINS_OUTPUT,
693 o1 | URTW_BB_HOST_BANG_EN, 0))
694 goto fail;
695 DELAY(5);
696 if (error = urtw_write16_c(sc, URTW_RF_PINS_OUTPUT, o1, 0))
697 goto fail;
698 DELAY(5);
699
700 for (i = 0; i < (wlen / 2); i++, mask = mask >> 1) {
701 bit = ((d2w & mask) != 0) ? 1 : 0;
702
703 if (error = urtw_write16_c(sc, URTW_RF_PINS_OUTPUT,
704 bit | o1, 0))
705 goto fail;
706 DELAY(2);
707 if (error = urtw_write16_c(sc, URTW_RF_PINS_OUTPUT,
708 bit | o1 | URTW_BB_HOST_BANG_CLK, 0))
709 goto fail;
710 DELAY(2);
711 if (error = urtw_write16_c(sc, URTW_RF_PINS_OUTPUT,
712 bit | o1 | URTW_BB_HOST_BANG_CLK, 0))
713 goto fail;
714 DELAY(2);
715 mask = mask >> 1;
716 if (i == 2)
717 break;
718 bit = ((d2w & mask) != 0) ? 1 : 0;
719 if (error = urtw_write16_c(sc, URTW_RF_PINS_OUTPUT,
720 bit | o1 | URTW_BB_HOST_BANG_CLK, 0))
721 goto fail;
722 DELAY(2);
723 if (error = urtw_write16_c(sc, URTW_RF_PINS_OUTPUT,
724 bit | o1 | URTW_BB_HOST_BANG_CLK, 0))
725 goto fail;
726 DELAY(2);
727 if (error = urtw_write16_c(sc, URTW_RF_PINS_OUTPUT,
728 bit | o1, 0))
729 goto fail;
730 DELAY(1);
731 }
732 if (error = urtw_write16_c(sc, URTW_RF_PINS_OUTPUT,
733 bit | o1 | URTW_BB_HOST_BANG_RW | URTW_BB_HOST_BANG_CLK, 0))
734 goto fail;
735 DELAY(2);
736 if (error = urtw_write16_c(sc, URTW_RF_PINS_OUTPUT,
737 bit | o1 | URTW_BB_HOST_BANG_RW, 0))
738 goto fail;
739 DELAY(2);
740 if (error = urtw_write16_c(sc, URTW_RF_PINS_OUTPUT,
741 o1 | URTW_BB_HOST_BANG_RW, 0))
742 goto fail;
743 DELAY(2);
744
745 mask = 0x800;
746 for (i = 0; i < rlen; i++, mask = mask >> 1) {
747 if (error = urtw_write16_c(sc, URTW_RF_PINS_OUTPUT,
748 o1 | URTW_BB_HOST_BANG_RW, 0))
749 goto fail;
750 DELAY(2);
751 if (error = urtw_write16_c(sc, URTW_RF_PINS_OUTPUT,
752 o1 | URTW_BB_HOST_BANG_RW | URTW_BB_HOST_BANG_CLK, 0))
753 goto fail;
754 DELAY(2);
755 if (error = urtw_write16_c(sc, URTW_RF_PINS_OUTPUT,
756 o1 | URTW_BB_HOST_BANG_RW | URTW_BB_HOST_BANG_CLK, 0))
757 goto fail;
758 DELAY(2);
759 if (error = urtw_write16_c(sc, URTW_RF_PINS_OUTPUT,
760 o1 | URTW_BB_HOST_BANG_RW | URTW_BB_HOST_BANG_CLK, 0))
761 goto fail;
762 DELAY(2);
763
764 if (error = urtw_read16_c(sc, URTW_RF_PINS_INPUT, &tmp, 0))
765 goto fail;
766 value |= ((tmp & URTW_BB_HOST_BANG_CLK) ? mask : 0);
767 if (error = urtw_write16_c(sc, URTW_RF_PINS_OUTPUT,
768 o1 | URTW_BB_HOST_BANG_RW, 0))
769 goto fail;
770 DELAY(2);
771 }
772
773 if (error = urtw_write16_c(sc, URTW_RF_PINS_OUTPUT,
774 o1 | URTW_BB_HOST_BANG_EN |
775 URTW_BB_HOST_BANG_RW, 0))
776 goto fail;
777 DELAY(2);
778
779 if (error = urtw_write16_c(sc, URTW_RF_PINS_ENABLE, o2, 0))
780 goto fail;
781 if (error = urtw_write16_c(sc, URTW_RF_PINS_SELECT, o3, 0))
782 goto fail;
783 error = urtw_write16_c(sc, URTW_RF_PINS_OUTPUT, 0x3a0, 0);
784
785 if (data != NULL)
786 *data = value;
787 fail:
788 return (error);
789 }
790
791 static void
792 urtw_delay_ms(int t)
793 {
794 DELAY(t * 1000);
795 }
796
797 static usbd_status
798 urtw_8225_write_c(struct urtw_softc *sc, uint8_t addr, uint16_t data)
799 {
800 uint16_t d80, d82, d84;
801 usbd_status error;
802
803 if (error = urtw_read16_c(sc, URTW_RF_PINS_OUTPUT, &d80, 0))
804 goto fail;
805 d80 &= 0xfff3;
806 if (error = urtw_read16_c(sc, URTW_RF_PINS_ENABLE, &d82, 0))
807 goto fail;
808 if (error = urtw_read16_c(sc, URTW_RF_PINS_SELECT, &d84, 0))
809 goto fail;
810 d84 &= 0xfff0;
811 if (error = urtw_write16_c(sc, URTW_RF_PINS_ENABLE,
812 d82 | 0x0007, 0))
813 goto fail;
814 if (error = urtw_write16_c(sc, URTW_RF_PINS_SELECT,
815 d84 | 0x0007, 0))
816 goto fail;
817
818 if (error = urtw_write16_c(sc, URTW_RF_PINS_OUTPUT,
819 d80 | URTW_BB_HOST_BANG_EN, 0))
820 goto fail;
821 urtw_delay_ms(2);
822 if (error = urtw_write16_c(sc, URTW_RF_PINS_OUTPUT, d80, 0))
823 goto fail;
824
825 error = urtw_8225_write_s16(sc, addr, 0x8225, &data);
826 if (error != 0)
827 goto fail;
828
829 if (error = urtw_write16_c(sc, URTW_RF_PINS_OUTPUT,
830 d80 | URTW_BB_HOST_BANG_EN, 0))
831 goto fail;
832 if (error = urtw_write16_c(sc, URTW_RF_PINS_OUTPUT,
833 d80 | URTW_BB_HOST_BANG_EN, 0))
834 goto fail;
835 error = urtw_write16_c(sc, URTW_RF_PINS_SELECT, d84, 0);
836 urtw_delay_ms(2);
837 fail:
838 return (error);
839 }
840
841 static usbd_status
842 urtw_8225_isv2(struct urtw_softc *sc, int *ret)
843 {
844 uint32_t data;
845 usbd_status error;
846
847 *ret = 1;
848
849 if (error = urtw_write16_c(sc, URTW_RF_PINS_OUTPUT, 0x0080, 0))
850 goto fail;
851 if (error = urtw_write16_c(sc, URTW_RF_PINS_SELECT, 0x0080, 0))
852 goto fail;
853 if (error = urtw_write16_c(sc, URTW_RF_PINS_ENABLE, 0x0080, 0))
854 goto fail;
855 urtw_delay_ms(300);
856
857 if (error = urtw_8225_write_c(sc, 0x0, 0x1b7))
858 goto fail;
859
860 error = urtw_8225_read(sc, 0x8, &data);
861 if (error != 0)
862 goto fail;
863 if (data != 0x588)
864 *ret = 0;
865 else {
866 error = urtw_8225_read(sc, 0x9, &data);
867 if (error != 0)
868 goto fail;
869 if (data != 0x700)
870 *ret = 0;
871 }
872
873 error = urtw_8225_write_c(sc, 0x0, 0xb7);
874 fail:
875 return (error);
876 }
877
878 static usbd_status
879 urtw_get_rfchip(struct urtw_softc *sc)
880 {
881 struct urtw_rf *rf = &sc->sc_rf;
882 int ret;
883 uint32_t data;
884 usbd_status error;
885
886 rf->rf_sc = sc;
887
888 if (sc->sc_hwrev & URTW_HWREV_8187) {
889 error = urtw_eprom_read32(sc, URTW_EPROM_RFCHIPID, &data);
890 if (error != 0) {
891 cmn_err(CE_WARN, "RF ID read failed\n");
892 return (-1);
893 }
894 switch (data & 0xff) {
895 case URTW_EPROM_RFCHIPID_RTL8225U:
896 error = urtw_8225_isv2(sc, &ret);
897 if (error != 0) {
898 URTW8187_DBG(URTW_DEBUG_HWTYPE,
899 (sc->sc_dev, CE_CONT,
900 "8225 version check failed\n"));
901 goto fail;
902 }
903 if (ret == 0) {
904 URTW8187_DBG(URTW_DEBUG_HWTYPE,
905 (sc->sc_dev, CE_CONT,
906 "8225 detected\n"));
907 rf->init = urtw_8225_rf_init;
908 rf->set_chan = urtw_8225_rf_set_chan;
909 rf->set_sens = urtw_8225_rf_set_sens;
910 } else {
911 URTW8187_DBG(URTW_DEBUG_HWTYPE,
912 (sc->sc_dev, CE_CONT,
913 "8225 v2 detected\n"));
914 rf->init = urtw_8225v2_rf_init;
915 rf->set_chan = urtw_8225v2_rf_set_chan;
916 rf->set_sens = NULL;
917 }
918 break;
919 default:
920 goto fail;
921 }
922 } else {
923 URTW8187_DBG(URTW_DEBUG_HWTYPE,
924 (sc->sc_dev, CE_CONT,
925 "8225 v2 [b] detected\n"));
926 rf->init = urtw_8225v2_b_rf_init;
927 rf->set_chan = urtw_8225v2_b_rf_set_chan;
928 rf->set_sens = NULL;
929 }
930
931 rf->max_sens = URTW_8225_RF_MAX_SENS;
932 rf->sens = URTW_8225_RF_DEF_SENS;
933
934 return (0);
935
936 fail:
937 cmn_err(CE_WARN, "unsupported RF chip %d\n", data & 0xff);
938 return (-1);
939 }
940
941 static usbd_status
942 urtw_get_txpwr(struct urtw_softc *sc)
943 {
944 int i, j;
945 uint32_t data;
946 usbd_status error;
947
948 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW_BASE, &data);
949 if (error != 0)
950 goto fail;
951 sc->sc_txpwr_cck_base = data & 0xf;
952 sc->sc_txpwr_ofdm_base = (data >> 4) & 0xf;
953
954 for (i = 1, j = 0; i < 6; i += 2, j++) {
955 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW0 + j, &data);
956 if (error != 0)
957 goto fail;
958 sc->sc_txpwr_cck[i] = data & 0xf;
959 sc->sc_txpwr_cck[i + 1] = (data & 0xf00) >> 8;
960 sc->sc_txpwr_ofdm[i] = (data & 0xf0) >> 4;
961 sc->sc_txpwr_ofdm[i + 1] = (data & 0xf000) >> 12;
962 }
963 for (i = 1, j = 0; i < 4; i += 2, j++) {
964 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW1 + j, &data);
965 if (error != 0)
966 goto fail;
967 sc->sc_txpwr_cck[i + 6] = data & 0xf;
968 sc->sc_txpwr_cck[i + 6 + 1] = (data & 0xf00) >> 8;
969 sc->sc_txpwr_ofdm[i + 6] = (data & 0xf0) >> 4;
970 sc->sc_txpwr_ofdm[i + 6 + 1] = (data & 0xf000) >> 12;
971 }
972 if (sc->sc_hwrev & URTW_HWREV_8187) {
973 for (i = 1, j = 0; i < 4; i += 2, j++) {
974 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW2 + j,
975 &data);
976 if (error != 0)
977 goto fail;
978 sc->sc_txpwr_cck[i + 6 + 4] = data & 0xf;
979 sc->sc_txpwr_cck[i + 6 + 4 + 1] = (data & 0xf00) >> 8;
980 sc->sc_txpwr_ofdm[i + 6 + 4] = (data & 0xf0) >> 4;
981 sc->sc_txpwr_ofdm[i + 6 + 4 + 1] =
982 (data & 0xf000) >> 12;
983 }
984 } else {
985 /* Channel 11. */
986 error = urtw_eprom_read32(sc, 0x1b, &data);
987 if (error != 0)
988 goto fail;
989 sc->sc_txpwr_cck[11] = data & 0xf;
990 sc->sc_txpwr_ofdm[11] = (data & 0xf0) >> 4;
991
992 /* Channel 12. */
993 error = urtw_eprom_read32(sc, 0xa, &data);
994 if (error != 0)
995 goto fail;
996 sc->sc_txpwr_cck[12] = data & 0xf;
997 sc->sc_txpwr_ofdm[12] = (data & 0xf0) >> 4;
998
999 /* Channel 13, 14. */
1000 error = urtw_eprom_read32(sc, 0x1c, &data);
1001 if (error != 0)
1002 goto fail;
1003 sc->sc_txpwr_cck[13] = data & 0xf;
1004 sc->sc_txpwr_ofdm[13] = (data & 0xf0) >> 4;
1005 sc->sc_txpwr_cck[14] = (data & 0xf00) >> 8;
1006 sc->sc_txpwr_ofdm[14] = (data & 0xf000) >> 12;
1007 }
1008 fail:
1009 return (error);
1010 }
1011
1012
1013 static usbd_status
1014 urtw_get_macaddr(struct urtw_softc *sc)
1015 {
1016 uint32_t data;
1017 usbd_status error;
1018 uint8_t *m = 0;
1019
1020 error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR, &data);
1021 if (error != 0)
1022 goto fail;
1023 sc->sc_bssid[0] = data & 0xff;
1024 sc->sc_bssid[1] = (data & 0xff00) >> 8;
1025 error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR + 1, &data);
1026 if (error != 0)
1027 goto fail;
1028 sc->sc_bssid[2] = data & 0xff;
1029 sc->sc_bssid[3] = (data & 0xff00) >> 8;
1030 error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR + 2, &data);
1031 if (error != 0)
1032 goto fail;
1033 sc->sc_bssid[4] = data & 0xff;
1034 sc->sc_bssid[5] = (data & 0xff00) >> 8;
1035 bcopy(sc->sc_bssid, sc->sc_ic.ic_macaddr, IEEE80211_ADDR_LEN);
1036 m = sc->sc_bssid;
1037 URTW8187_DBG(URTW_DEBUG_HWTYPE, (sc->sc_dev, CE_CONT,
1038 "MAC: %x:%x:%x:%x:%x:%x\n",
1039 m[0], m[1], m[2], m[3], m[4], m[5]));
1040 fail:
1041 return (error);
1042 }
1043
1044 static usbd_status
1045 urtw_eprom_read32(struct urtw_softc *sc, uint32_t addr, uint32_t *data)
1046 {
1047 #define URTW_READCMD_LEN 3
1048 int addrlen, i;
1049 int16_t addrstr[8], data16, readcmd[] = { 1, 1, 0 };
1050 usbd_status error;
1051
1052 /* NB: make sure the buffer is initialized */
1053 *data = 0;
1054
1055 /* enable EPROM programming */
1056 if (error = urtw_write8_c(sc, URTW_EPROM_CMD,
1057 URTW_EPROM_CMD_PROGRAM_MODE, 0))
1058 goto fail;
1059 DELAY(URTW_EPROM_DELAY);
1060
1061 error = urtw_eprom_cs(sc, URTW_EPROM_ENABLE);
1062 if (error != 0)
1063 goto fail;
1064 error = urtw_eprom_ck(sc);
1065 if (error != 0)
1066 goto fail;
1067 error = urtw_eprom_sendbits(sc, readcmd, URTW_READCMD_LEN);
1068 if (error != 0)
1069 goto fail;
1070 if (sc->sc_epromtype == URTW_EEPROM_93C56) {
1071 addrlen = 8;
1072 addrstr[0] = addr & (1 << 7);
1073 addrstr[1] = addr & (1 << 6);
1074 addrstr[2] = addr & (1 << 5);
1075 addrstr[3] = addr & (1 << 4);
1076 addrstr[4] = addr & (1 << 3);
1077 addrstr[5] = addr & (1 << 2);
1078 addrstr[6] = addr & (1 << 1);
1079 addrstr[7] = addr & (1 << 0);
1080 } else {
1081 addrlen = 6;
1082 addrstr[0] = addr & (1 << 5);
1083 addrstr[1] = addr & (1 << 4);
1084 addrstr[2] = addr & (1 << 3);
1085 addrstr[3] = addr & (1 << 2);
1086 addrstr[4] = addr & (1 << 1);
1087 addrstr[5] = addr & (1 << 0);
1088 }
1089 error = urtw_eprom_sendbits(sc, addrstr, addrlen);
1090 if (error != 0)
1091 goto fail;
1092
1093 error = urtw_eprom_writebit(sc, 0);
1094 if (error != 0)
1095 goto fail;
1096
1097 for (i = 0; i < 16; i++) {
1098 error = urtw_eprom_ck(sc);
1099 if (error != 0)
1100 goto fail;
1101 error = urtw_eprom_readbit(sc, &data16);
1102 if (error != 0)
1103 goto fail;
1104
1105 (*data) |= (data16 << (15 - i));
1106 }
1107
1108 error = urtw_eprom_cs(sc, URTW_EPROM_DISABLE);
1109 if (error != 0)
1110 goto fail;
1111 error = urtw_eprom_ck(sc);
1112 if (error != 0)
1113 goto fail;
1114
1115 /* now disable EPROM programming */
1116 error = urtw_write8_c(sc, URTW_EPROM_CMD,
1117 URTW_EPROM_CMD_NORMAL_MODE, 0);
1118 fail:
1119 return (error);
1120 #undef URTW_READCMD_LEN
1121 }
1122
1123 static usbd_status
1124 urtw_eprom_readbit(struct urtw_softc *sc, int16_t *data)
1125 {
1126 uint8_t data8;
1127 usbd_status error;
1128
1129 error = urtw_read8_c(sc, URTW_EPROM_CMD, &data8, 0);
1130 *data = (data8 & URTW_EPROM_READBIT) ? 1 : 0;
1131 DELAY(URTW_EPROM_DELAY);
1132 return (error);
1133 }
1134
1135 static usbd_status
1136 urtw_eprom_sendbits(struct urtw_softc *sc, int16_t *buf, int buflen)
1137 {
1138 int i = 0;
1139 usbd_status error;
1140
1141 for (i = 0; i < buflen; i++) {
1142 error = urtw_eprom_writebit(sc, buf[i]);
1143 if (error != 0)
1144 goto fail;
1145 error = urtw_eprom_ck(sc);
1146 if (error != 0)
1147 goto fail;
1148 }
1149 fail:
1150 return (error);
1151 }
1152
1153 static usbd_status
1154 urtw_eprom_writebit(struct urtw_softc *sc, int16_t bit)
1155 {
1156 uint8_t data;
1157 usbd_status error;
1158
1159 if (error = urtw_read8_c(sc, URTW_EPROM_CMD, &data, 0))
1160 goto fail;
1161 if (bit != 0)
1162 error = urtw_write8_c(sc, URTW_EPROM_CMD,
1163 data | URTW_EPROM_WRITEBIT, 0);
1164 else
1165 error = urtw_write8_c(sc, URTW_EPROM_CMD,
1166 data & ~URTW_EPROM_WRITEBIT, 0);
1167 DELAY(URTW_EPROM_DELAY);
1168 fail:
1169 return (error);
1170 }
1171
1172 static usbd_status
1173 urtw_eprom_ck(struct urtw_softc *sc)
1174 {
1175 uint8_t data;
1176 usbd_status error;
1177
1178 /* masking */
1179 if (error = urtw_read8_c(sc, URTW_EPROM_CMD, &data, 0))
1180 goto fail;
1181 if (error = urtw_write8_c(sc, URTW_EPROM_CMD, data | URTW_EPROM_CK, 0))
1182 goto fail;
1183 DELAY(URTW_EPROM_DELAY);
1184 /* unmasking */
1185 if (error = urtw_read8_c(sc, URTW_EPROM_CMD, &data, 0))
1186 goto fail;
1187 error = urtw_write8_c(sc, URTW_EPROM_CMD, data & ~URTW_EPROM_CK, 0);
1188 DELAY(URTW_EPROM_DELAY);
1189 fail:
1190 return (error);
1191 }
1192
1193 static usbd_status
1194 urtw_eprom_cs(struct urtw_softc *sc, int able)
1195 {
1196 uint8_t data;
1197 usbd_status error;
1198
1199 if (error = urtw_read8_c(sc, URTW_EPROM_CMD, &data, 0))
1200 goto fail;
1201 if (able == URTW_EPROM_ENABLE)
1202 error = urtw_write8_c(sc, URTW_EPROM_CMD,
1203 data | URTW_EPROM_CS, 0);
1204 else
1205 error = urtw_write8_c(sc, URTW_EPROM_CMD,
1206 data & ~URTW_EPROM_CS, 0);
1207 DELAY(URTW_EPROM_DELAY);
1208 fail:
1209 return (error);
1210 }
1211
1212 static usbd_status
1213 urtw_read8_c(struct urtw_softc *sc, int val, uint8_t *data, uint8_t idx)
1214 {
1215 usb_ctrl_setup_t req;
1216 usb_cr_t cr;
1217 usb_cb_flags_t cf;
1218 mblk_t *mp = NULL;
1219 usbd_status error;
1220
1221 bzero(&req, sizeof (req));
1222 req.bmRequestType = UT_READ_VENDOR_DEVICE;
1223 req.bRequest = URTW_8187_GETREGS_REQ;
1224 req.wValue = val | 0xff00;
1225 req.wIndex = idx & 0x03;
1226 req.wLength = sizeof (uint8_t);
1227
1228 error = usb_pipe_ctrl_xfer_wait(sc->sc_udev->dev_default_ph, &req, &mp,
1229 &cr, &cf, 0);
1230
1231 if (error != USB_SUCCESS) {
1232 URTW8187_DBG(URTW_DEBUG_DEVREQ, (sc->sc_dev, CE_CONT,
1233 "urtw_read8_c: get regs req failed :"
1234 " cr:%s(%d), cf:(%x)\n", usb_str_cr(cr), cr, cf));
1235 return (error);
1236 }
1237 bcopy(mp->b_rptr, data, sizeof (uint8_t));
1238 if (mp)
1239 freemsg(mp);
1240 return (error);
1241 }
1242
1243 static usbd_status
1244 urtw_read8e(struct urtw_softc *sc, int val, uint8_t *data)
1245 {
1246 usb_ctrl_setup_t req;
1247 usb_cr_t cr;
1248 usb_cb_flags_t cf;
1249 mblk_t *mp = NULL;
1250 usbd_status error;
1251
1252 bzero(&req, sizeof (req));
1253 req.bmRequestType = UT_READ_VENDOR_DEVICE;
1254 req.bRequest = URTW_8187_GETREGS_REQ;
1255 req.wValue = val | 0xfe00;
1256 req.wIndex = 0;
1257 req.wLength = sizeof (uint8_t);
1258 req.attrs = USB_ATTRS_AUTOCLEARING;
1259 error = usb_pipe_ctrl_xfer_wait(sc->sc_udev->dev_default_ph, &req, &mp,
1260 &cr, &cf, 0);
1261
1262 if (error != USB_SUCCESS) {
1263 URTW8187_DBG(URTW_DEBUG_DEVREQ, (sc->sc_dev, CE_CONT,
1264 "urtw_read8e: get regs req failed :"
1265 " cr:%s(%d), cf:(%x)\n", usb_str_cr(cr), cr, cf));
1266 return (error);
1267 }
1268
1269 if (mp) {
1270 bcopy(mp->b_rptr, data, sizeof (uint8_t));
1271 freemsg(mp);
1272 }
1273 return (error);
1274 }
1275
1276 static usbd_status
1277 urtw_read16_c(struct urtw_softc *sc, int val, uint16_t *data, uint8_t idx)
1278 {
1279 usb_ctrl_setup_t req;
1280 usb_cr_t cr;
1281 usb_cb_flags_t cf;
1282 mblk_t *mp = NULL;
1283 usbd_status error;
1284
1285 bzero(&req, sizeof (req));
1286 req.bmRequestType = UT_READ_VENDOR_DEVICE;
1287 req.bRequest = URTW_8187_GETREGS_REQ;
1288 req.wValue = val | 0xff00;
1289 req.wIndex = idx & 0x03;
1290 req.wLength = sizeof (uint16_t);
1291 req.attrs = USB_ATTRS_AUTOCLEARING;
1292 error = usb_pipe_ctrl_xfer_wait(sc->sc_udev->dev_default_ph, &req, &mp,
1293 &cr, &cf, 0);
1294
1295 if (error != USB_SUCCESS) {
1296 URTW8187_DBG(URTW_DEBUG_DEVREQ, (sc->sc_dev, CE_CONT,
1297 "urtw_read16_c: get regs req failed :"
1298 " cr:%s(%d), cf:(%x)\n",
1299 usb_str_cr(cr), cr, cf));
1300 return (error);
1301 }
1302 if (mp) {
1303 bcopy(mp->b_rptr, data, sizeof (uint16_t));
1304 freemsg(mp);
1305 }
1306 return (error);
1307 }
1308
1309 static usbd_status
1310 urtw_read32_c(struct urtw_softc *sc, int val, uint32_t *data, uint8_t idx)
1311 {
1312 usb_ctrl_setup_t req;
1313 usb_cr_t cr;
1314 usb_cb_flags_t cf;
1315 mblk_t *mp = NULL;
1316 usbd_status error;
1317
1318 bzero(&req, sizeof (req));
1319 req.bmRequestType = UT_READ_VENDOR_DEVICE;
1320 req.bRequest = URTW_8187_GETREGS_REQ;
1321 req.wValue = val | 0xff00;
1322 req.wIndex = idx & 0x03;
1323 req.wLength = sizeof (uint32_t);
1324 req.attrs = USB_ATTRS_AUTOCLEARING;
1325
1326 error = usb_pipe_ctrl_xfer_wait(sc->sc_udev->dev_default_ph, &req, &mp,
1327 &cr, &cf, 0);
1328
1329 if (error != USB_SUCCESS) {
1330 URTW8187_DBG(URTW_DEBUG_DEVREQ, (sc->sc_dev, CE_CONT,
1331 "urtw_read32_c: get regs req failed :"
1332 " cr:%s(%d), cf:(%x)\n", usb_str_cr(cr), cr, cf));
1333 return (error);
1334 }
1335
1336 if (mp) {
1337 bcopy(mp->b_rptr, data, sizeof (uint32_t));
1338 freemsg(mp);
1339 }
1340 return (error);
1341 }
1342
1343 static usbd_status
1344 urtw_write8_c(struct urtw_softc *sc, int val, uint8_t data, uint8_t idx)
1345 {
1346 usb_ctrl_setup_t req;
1347 usb_cr_t cr;
1348 usb_cb_flags_t cf;
1349 mblk_t *mp = 0;
1350 int error;
1351
1352 bzero(&req, sizeof (req));
1353 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
1354 req.bRequest = URTW_8187_SETREGS_REQ;
1355 req.wValue = val | 0xff00;
1356 req.wIndex = idx & 0x03;
1357 req.wLength = sizeof (uint8_t);
1358 req.attrs = USB_ATTRS_NONE;
1359
1360 mp = allocb(sizeof (uint32_t), BPRI_MED);
1361 if (mp == NULL) {
1362 cmn_err(CE_CONT, "urtw_write8_c: failed alloc mblk.");
1363 return (-1);
1364 }
1365 *(uint8_t *)(mp->b_rptr) = data;
1366 mp->b_wptr += sizeof (uint8_t);
1367 error = usb_pipe_ctrl_xfer_wait(sc->sc_udev->dev_default_ph, &req, &mp,
1368 &cr, &cf, 0);
1369 if (error != USB_SUCCESS) {
1370 URTW8187_DBG(URTW_DEBUG_DEVREQ, (sc->sc_dev, CE_CONT,
1371 "urtw_write8_c: could not set regs:"
1372 "cr:%s(%d), cf:(%x)\n", usb_str_cr(cr), cr, cf));
1373 }
1374 if (mp)
1375 freemsg(mp);
1376 return (error);
1377 }
1378
1379 static usbd_status
1380 urtw_write8e(struct urtw_softc *sc, int val, uint8_t data)
1381 {
1382 usb_ctrl_setup_t req;
1383 usb_cr_t cr;
1384 usb_cb_flags_t cf;
1385 mblk_t *mp = 0;
1386 int error;
1387
1388 bzero(&req, sizeof (req));
1389 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
1390 req.bRequest = URTW_8187_SETREGS_REQ;
1391 req.wValue = val | 0xfe00;
1392 req.wIndex = 0;
1393 req.wLength = sizeof (uint8_t);
1394 req.attrs = USB_ATTRS_NONE;
1395
1396 mp = allocb(sizeof (uint8_t), BPRI_MED);
1397 if (mp == NULL) {
1398 cmn_err(CE_CONT, "urtw_write8e: failed alloc mblk.");
1399 return (-1);
1400 }
1401 *(mp->b_rptr) = data;
1402 mp->b_wptr += sizeof (uint8_t);
1403
1404 error = usb_pipe_ctrl_xfer_wait(sc->sc_udev->dev_default_ph, &req, &mp,
1405 &cr, &cf, 0);
1406 if (error != USB_SUCCESS) {
1407 URTW8187_DBG(URTW_DEBUG_DEVREQ, (sc->sc_dev, CE_CONT,
1408 "urtw_write8e: could not set regs:"
1409 "cr:%s(%d), cf:(%x)\n",
1410 usb_str_cr(cr), cr, cf));
1411 }
1412 if (mp)
1413 freemsg(mp);
1414 return (error);
1415 }
1416
1417 static usbd_status
1418 urtw_write16_c(struct urtw_softc *sc, int val, uint16_t data, uint8_t idx)
1419 {
1420 usb_ctrl_setup_t req;
1421 usb_cr_t cr;
1422 usb_cb_flags_t cf;
1423 mblk_t *mp = 0;
1424 int error;
1425
1426 bzero(&req, sizeof (req));
1427 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
1428 req.bRequest = URTW_8187_SETREGS_REQ;
1429 req.wValue = val | 0xff00;
1430 req.wIndex = idx & 0x03;
1431 req.wLength = sizeof (uint16_t);
1432 req.attrs = USB_ATTRS_NONE;
1433
1434 mp = allocb(sizeof (uint16_t), BPRI_MED);
1435 if (mp == NULL) {
1436 cmn_err(CE_CONT, "urtw_write16_c: failed alloc mblk.");
1437 return (-1);
1438 }
1439 *(uint16_t *)(uintptr_t)(mp->b_rptr) = data;
1440 mp->b_wptr += sizeof (uint16_t);
1441 error = usb_pipe_ctrl_xfer_wait(sc->sc_udev->dev_default_ph, &req, &mp,
1442 &cr, &cf, 0);
1443 if (error != USB_SUCCESS) {
1444 URTW8187_DBG(URTW_DEBUG_DEVREQ, (sc->sc_dev, CE_CONT,
1445 "urtw_write16_c: could not set regs:"
1446 "cr:%s(%d), cf:(%x)\n",
1447 usb_str_cr(cr), cr, cf));
1448 }
1449 if (mp)
1450 freemsg(mp);
1451 return (error);
1452 }
1453
1454 static usbd_status
1455 urtw_write32_c(struct urtw_softc *sc, int val, uint32_t data, uint8_t idx)
1456 {
1457 usb_ctrl_setup_t req;
1458 usb_cr_t cr;
1459 usb_cb_flags_t cf;
1460 mblk_t *mp = 0;
1461 int error;
1462
1463 bzero(&req, sizeof (req));
1464 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
1465 req.bRequest = URTW_8187_SETREGS_REQ;
1466 req.wValue = val | 0xff00;
1467 req.wIndex = idx & 0x03;
1468 req.wLength = sizeof (uint32_t);
1469 req.attrs = USB_ATTRS_NONE;
1470
1471 mp = allocb(sizeof (uint32_t), BPRI_MED);
1472 if (mp == NULL) {
1473 cmn_err(CE_CONT, "urtw_write32_c: failed alloc mblk.");
1474 return (-1);
1475 }
1476 *(uint32_t *)(uintptr_t)(mp->b_rptr) = data;
1477 mp->b_wptr += sizeof (uint32_t);
1478 error = usb_pipe_ctrl_xfer_wait(sc->sc_udev->dev_default_ph, &req, &mp,
1479 &cr, &cf, 0);
1480 if (error != USB_SUCCESS) {
1481 URTW8187_DBG(URTW_DEBUG_DEVREQ, (sc->sc_dev, CE_CONT,
1482 "urtw_write32_c: could not set regs:"
1483 "cr:%s(%d), cf:(%x)\n",
1484 usb_str_cr(cr), cr, cf));
1485 }
1486
1487 if (mp)
1488 freemsg(mp);
1489 return (error);
1490 }
1491
1492 static usbd_status
1493 urtw_set_mode(struct urtw_softc *sc, uint32_t mode)
1494 {
1495 uint8_t data;
1496 usbd_status error;
1497
1498 if (error = urtw_read8_c(sc, URTW_EPROM_CMD, &data, 0))
1499 goto fail;
1500 data = (data & ~URTW_EPROM_CMD_MASK) | (mode << URTW_EPROM_CMD_SHIFT);
1501 data = data & ~(URTW_EPROM_CS | URTW_EPROM_CK);
1502 error = urtw_write8_c(sc, URTW_EPROM_CMD, data, 0);
1503 fail:
1504 return (error);
1505 }
1506
1507 static usbd_status
1508 urtw_8180_set_anaparam(struct urtw_softc *sc, uint32_t val)
1509 {
1510 uint8_t data;
1511 usbd_status error;
1512
1513 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
1514 if (error)
1515 goto fail;
1516
1517 if (error = urtw_read8_c(sc, URTW_CONFIG3, &data, 0))
1518 goto fail;
1519 if (error = urtw_write8_c(sc, URTW_CONFIG3,
1520 data | URTW_CONFIG3_ANAPARAM_WRITE, 0))
1521 goto fail;
1522 if (error = urtw_write32_c(sc, URTW_ANAPARAM, val, 0))
1523 goto fail;
1524 if (error = urtw_read8_c(sc, URTW_CONFIG3, &data, 0))
1525 goto fail;
1526 if (error = urtw_write8_c(sc, URTW_CONFIG3,
1527 data & ~URTW_CONFIG3_ANAPARAM_WRITE, 0))
1528 goto fail;
1529
1530 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
1531 if (error)
1532 goto fail;
1533 fail:
1534 return (error);
1535 }
1536
1537 static usbd_status
1538 urtw_8185_set_anaparam2(struct urtw_softc *sc, uint32_t val)
1539 {
1540 uint8_t data;
1541 usbd_status error;
1542
1543 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
1544 if (error)
1545 goto fail;
1546
1547 if (error = urtw_read8_c(sc, URTW_CONFIG3, &data, 0))
1548 goto fail;
1549 if (error = urtw_write8_c(sc, URTW_CONFIG3,
1550 data | URTW_CONFIG3_ANAPARAM_WRITE, 0))
1551 goto fail;
1552 if (error = urtw_write32_c(sc, URTW_ANAPARAM2, val, 0))
1553 goto fail;
1554 if (error = urtw_read8_c(sc, URTW_CONFIG3, &data, 0))
1555 goto fail;
1556 if (error = urtw_write8_c(sc, URTW_CONFIG3,
1557 data & ~URTW_CONFIG3_ANAPARAM_WRITE, 0))
1558 goto fail;
1559
1560 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
1561 if (error)
1562 goto fail;
1563 fail:
1564 return (error);
1565 }
1566
1567 static usbd_status
1568 urtw_intr_disable(struct urtw_softc *sc)
1569 {
1570 usbd_status error;
1571
1572 error = urtw_write16_c(sc, URTW_INTR_MASK, 0, 0);
1573 return (error);
1574 }
1575
1576 static usbd_status
1577 urtw_8187_reset(struct urtw_softc *sc)
1578 {
1579 uint8_t data;
1580 usbd_status error;
1581
1582 error = urtw_8180_set_anaparam(sc, URTW_8187_8225_ANAPARAM_ON);
1583 if (error)
1584 goto fail;
1585 error = urtw_8185_set_anaparam2(sc, URTW_8187_8225_ANAPARAM2_ON);
1586 if (error)
1587 goto fail;
1588
1589 error = urtw_intr_disable(sc);
1590 if (error)
1591 goto fail;
1592 urtw_delay_ms(50);
1593
1594 error = urtw_write8e(sc, 0x18, 0x10);
1595 if (error != 0)
1596 goto fail;
1597 error = urtw_write8e(sc, 0x18, 0x11);
1598 if (error != 0)
1599 goto fail;
1600 error = urtw_write8e(sc, 0x18, 0x00);
1601 if (error != 0)
1602 goto fail;
1603 urtw_delay_ms(50);
1604
1605 if (error = urtw_read8_c(sc, URTW_CMD, &data, 0))
1606 goto fail;
1607 data = (data & 2) | URTW_CMD_RST;
1608 if (error = urtw_write8_c(sc, URTW_CMD, data, 0))
1609 goto fail;
1610 urtw_delay_ms(50);
1611
1612 if (error = urtw_read8_c(sc, URTW_CMD, &data, 0))
1613 goto fail;
1614 if (data & URTW_CMD_RST) {
1615 cmn_err(CE_CONT, "urtw reset timeout\n");
1616 goto fail;
1617 }
1618 error = urtw_set_mode(sc, URTW_EPROM_CMD_LOAD);
1619 if (error)
1620 goto fail;
1621 urtw_delay_ms(50);
1622
1623 error = urtw_8180_set_anaparam(sc, URTW_8187_8225_ANAPARAM_ON);
1624 if (error)
1625 goto fail;
1626 error = urtw_8185_set_anaparam2(sc, URTW_8187_8225_ANAPARAM2_ON);
1627 if (error)
1628 goto fail;
1629 fail:
1630 return (error);
1631 }
1632
1633 static usbd_status
1634 urtw_led_on(struct urtw_softc *sc, int type)
1635 {
1636 if (type == URTW_LED_GPIO) {
1637 switch (sc->sc_gpio_ledpin) {
1638 case URTW_LED_PIN_GPIO0:
1639 (void) urtw_write8_c(sc, URTW_GPIO, 0x01, 0);
1640 (void) urtw_write8_c(sc, URTW_GP_ENABLE, 0x00, 0);
1641 break;
1642 default:
1643 cmn_err(CE_WARN, "unsupported LED PIN type 0x%x",
1644 sc->sc_gpio_ledpin);
1645 /* never reach */
1646 }
1647 } else {
1648 cmn_err(CE_WARN, "unsupported LED type 0x%x", type);
1649 /* never reach */
1650 }
1651
1652 sc->sc_gpio_ledon = 1;
1653 return (0);
1654 }
1655
1656 static usbd_status
1657 urtw_led_off(struct urtw_softc *sc, int type)
1658 {
1659 if (type == URTW_LED_GPIO) {
1660 switch (sc->sc_gpio_ledpin) {
1661 case URTW_LED_PIN_GPIO0:
1662 (void) urtw_write8_c(sc, URTW_GPIO, 0x01, 0);
1663 (void) urtw_write8_c(sc, URTW_GP_ENABLE, 0x01, 0);
1664 break;
1665 default:
1666 cmn_err(CE_WARN, "unsupported LED PIN type 0x%x",
1667 sc->sc_gpio_ledpin);
1668 /* never reach */
1669 }
1670 } else {
1671 cmn_err(CE_WARN, "unsupported LED type 0x%x", type);
1672 /* never reach */
1673 }
1674
1675 sc->sc_gpio_ledon = 0;
1676 return (0);
1677 }
1678
1679 static usbd_status
1680 urtw_led_mode0(struct urtw_softc *sc, int mode)
1681 {
1682 URTW8187_DBG(URTW_DEBUG_LED, (sc->sc_dev, CE_CONT,
1683 "urtw_led_mode0: mode = %d\n", mode));
1684 switch (mode) {
1685 case URTW_LED_CTL_POWER_ON:
1686 sc->sc_gpio_ledstate = URTW_LED_POWER_ON_BLINK;
1687 break;
1688 case URTW_LED_CTL_TX:
1689 if (sc->sc_gpio_ledinprogress == 1)
1690 return (0);
1691 sc->sc_gpio_ledstate = URTW_LED_BLINK_NORMAL;
1692 sc->sc_gpio_blinktime =
1693 (sc->sc_ic.ic_state == IEEE80211_S_RUN ? 4:2);
1694 break;
1695 case URTW_LED_CTL_LINK:
1696 sc->sc_gpio_ledstate = URTW_LED_ON;
1697 break;
1698 default:
1699 cmn_err(CE_CONT, "unsupported LED mode 0x%x", mode);
1700 /* never reach */
1701 }
1702
1703 switch (sc->sc_gpio_ledstate) {
1704 case URTW_LED_ON:
1705 if (sc->sc_gpio_ledinprogress != 0)
1706 break;
1707 (void) urtw_led_on(sc, URTW_LED_GPIO);
1708 break;
1709 case URTW_LED_BLINK_NORMAL:
1710 if (sc->sc_gpio_ledinprogress != 0)
1711 break;
1712 sc->sc_gpio_ledinprogress = 1;
1713 sc->sc_gpio_blinkstate = (sc->sc_gpio_ledon != 0) ?
1714 URTW_LED_OFF : URTW_LED_ON;
1715 URTW_LEDLOCK(sc);
1716 if (sc->sc_led_ch == 0) {
1717 URTW8187_DBG(URTW_DEBUG_LED, (sc->sc_dev, CE_CONT,
1718 "urtw_led_mode0: restart led timer\n"));
1719 sc->sc_led_ch = timeout(urtw_led_launch,
1720 (void *)sc,
1721 drv_usectohz((sc->sc_ic.ic_state ==
1722 IEEE80211_S_RUN) ?
1723 URTW_LED_LINKON_BLINK :
1724 URTW_LED_LINKOFF_BLINK));
1725 sc->sc_gpio_ledinprogress = 0;
1726 }
1727 URTW_LEDUNLOCK(sc);
1728 break;
1729 case URTW_LED_POWER_ON_BLINK:
1730 (void) urtw_led_on(sc, URTW_LED_GPIO);
1731 urtw_delay_ms(100);
1732 (void) urtw_led_off(sc, URTW_LED_GPIO);
1733 break;
1734 default:
1735 URTW8187_DBG(URTW_DEBUG_LED, (sc->sc_dev, CE_CONT,
1736 "urtw_led_mode0: unknown LED status 0x%x",
1737 sc->sc_gpio_ledstate));
1738 }
1739 return (0);
1740 }
1741
1742 static usbd_status
1743 urtw_led_mode1(struct urtw_softc *sc, int mode)
1744 {
1745 cmn_err(CE_WARN, "urtw sc %p, mode %d not supported", (void *)sc, mode);
1746 return (USBD_INVAL);
1747 }
1748
1749 static usbd_status
1750 urtw_led_mode2(struct urtw_softc *sc, int mode)
1751 {
1752 cmn_err(CE_WARN, "urtw sc %p, mode %d not supported", (void *)sc, mode);
1753 return (USBD_INVAL);
1754 }
1755
1756 static usbd_status
1757 urtw_led_mode3(struct urtw_softc *sc, int mode)
1758 {
1759 cmn_err(CE_WARN, "urtw sc %p, mode %d not supported", (void *)sc, mode);
1760 return (USBD_INVAL);
1761 }
1762
1763 static usbd_status
1764 urtw_led_blink(struct urtw_softc *sc)
1765 {
1766 uint8_t ing = 0;
1767
1768 URTW8187_DBG(URTW_DEBUG_LED, (sc->sc_dev, CE_CONT,
1769 "urtw_led_blink: gpio_blinkstate %d\n",
1770 sc->sc_gpio_blinkstate));
1771 if (sc->sc_gpio_blinkstate == URTW_LED_ON)
1772 (void) urtw_led_on(sc, URTW_LED_GPIO);
1773 else
1774 (void) urtw_led_off(sc, URTW_LED_GPIO);
1775 sc->sc_gpio_blinktime--;
1776 if (sc->sc_gpio_blinktime == 0)
1777 ing = 1;
1778 else {
1779 if (sc->sc_gpio_ledstate != URTW_LED_BLINK_NORMAL &&
1780 sc->sc_gpio_ledstate != URTW_LED_BLINK_SLOWLY &&
1781 sc->sc_gpio_ledstate != URTW_LED_BLINK_CM3)
1782 ing = 1;
1783 }
1784 if (ing == 1) {
1785 if (sc->sc_gpio_ledstate == URTW_LED_ON &&
1786 sc->sc_gpio_ledon == 0)
1787 (void) urtw_led_on(sc, URTW_LED_GPIO);
1788 else if (sc->sc_gpio_ledstate == URTW_LED_OFF &&
1789 sc->sc_gpio_ledon == 1)
1790 (void) urtw_led_off(sc, URTW_LED_GPIO);
1791
1792 sc->sc_gpio_blinktime = 0;
1793 sc->sc_gpio_ledinprogress = 0;
1794 return (0);
1795 }
1796
1797 sc->sc_gpio_blinkstate = (sc->sc_gpio_blinkstate != URTW_LED_ON) ?
1798 URTW_LED_ON : URTW_LED_OFF;
1799
1800 switch (sc->sc_gpio_ledstate) {
1801 case URTW_LED_BLINK_NORMAL:
1802 URTW8187_DBG(URTW_DEBUG_LED, (sc->sc_dev, CE_CONT,
1803 "URTW_LED_BLINK_NORMAL\n"));
1804 return (1);
1805 default:
1806 URTW8187_DBG(URTW_DEBUG_LED, (sc->sc_dev, CE_CONT,
1807 "unknown LED status 0x%x", sc->sc_gpio_ledstate));
1808 }
1809 return (0);
1810 }
1811
1812 static usbd_status
1813 urtw_led_ctl(struct urtw_softc *sc, int mode)
1814 {
1815 usbd_status error = 0;
1816
1817 switch (sc->sc_strategy) {
1818 case URTW_SW_LED_MODE0:
1819 error = urtw_led_mode0(sc, mode);
1820 break;
1821 case URTW_SW_LED_MODE1:
1822 error = urtw_led_mode1(sc, mode);
1823 break;
1824 case URTW_SW_LED_MODE2:
1825 error = urtw_led_mode2(sc, mode);
1826 break;
1827 case URTW_SW_LED_MODE3:
1828 error = urtw_led_mode3(sc, mode);
1829 break;
1830 default:
1831 cmn_err(CE_CONT, "unsupported LED mode %d\n", sc->sc_strategy);
1832 /* never reach */
1833 return (-1);
1834 }
1835
1836 return (error);
1837 }
1838
1839 static usbd_status
1840 urtw_update_msr(struct urtw_softc *sc, int nstate)
1841 {
1842 struct ieee80211com *ic = &sc->sc_ic;
1843 uint8_t data;
1844 usbd_status error;
1845
1846 if (error = urtw_read8_c(sc, URTW_MSR, &data, 0))
1847 goto fail;
1848 data &= ~URTW_MSR_LINK_MASK;
1849
1850 /* Should always be set. */
1851 if (sc->sc_hwrev & URTW_HWREV_8187B)
1852 data |= URTW_MSR_LINK_ENEDCA;
1853
1854 if (nstate == IEEE80211_S_RUN) {
1855 switch (ic->ic_opmode) {
1856 case IEEE80211_M_STA:
1857 case IEEE80211_M_MONITOR:
1858 data |= URTW_MSR_LINK_STA;
1859 break;
1860 case IEEE80211_M_IBSS:
1861 data |= URTW_MSR_LINK_ADHOC;
1862 break;
1863 case IEEE80211_M_HOSTAP:
1864 data |= URTW_MSR_LINK_HOSTAP;
1865 break;
1866 default:
1867 cmn_err(CE_CONT, "unsupported operation mode 0x%x\n",
1868 ic->ic_opmode);
1869 return (-1);
1870 }
1871 } else
1872 data |= URTW_MSR_LINK_NONE;
1873
1874 error = urtw_write8_c(sc, URTW_MSR, data, 0);
1875 fail:
1876 return (error);
1877 }
1878
1879 static uint16_t
1880 urtw_rate2rtl(int rate)
1881 {
1882 #define N(a) (sizeof (a) / sizeof ((a)[0]))
1883 int i;
1884
1885 for (i = 0; i < N(urtw_ratetable); i++) {
1886 if (rate == urtw_ratetable[i].reg)
1887 return (urtw_ratetable[i].val);
1888 }
1889 return (3);
1890 #undef N
1891 }
1892
1893 static uint16_t
1894 urtw_rtl2rate(int rate)
1895 {
1896 #define N(a) (sizeof (a) / sizeof ((a)[0]))
1897 int i;
1898
1899 for (i = 0; i < N(urtw_ratetable); i++) {
1900 if (rate == urtw_ratetable[i].val)
1901 return (urtw_ratetable[i].reg);
1902 }
1903
1904 return (0);
1905 #undef N
1906 }
1907
1908 static usbd_status
1909 urtw_set_rate(struct urtw_softc *sc)
1910 {
1911 int i, basic_rate, min_rr_rate, max_rr_rate;
1912 uint16_t data;
1913 usbd_status error;
1914
1915 basic_rate = urtw_rate2rtl(48);
1916 min_rr_rate = urtw_rate2rtl(12);
1917 max_rr_rate = urtw_rate2rtl(48);
1918 if (error = urtw_write8_c(sc, URTW_RESP_RATE,
1919 max_rr_rate << URTW_RESP_MAX_RATE_SHIFT |
1920 min_rr_rate << URTW_RESP_MIN_RATE_SHIFT, 0))
1921 goto fail;
1922
1923 if (error = urtw_read16_c(sc, URTW_BRSR, &data, 0))
1924 goto fail;
1925 data &= ~URTW_BRSR_MBR_8185;
1926
1927 for (i = 0; i <= basic_rate; i++)
1928 data |= (1 << i);
1929
1930 error = urtw_write16_c(sc, URTW_BRSR, data, 0);
1931 fail:
1932 return (error);
1933 }
1934
1935 static usbd_status
1936 urtw_intr_enable(struct urtw_softc *sc)
1937 {
1938 usbd_status error;
1939
1940 error = urtw_write16_c(sc, URTW_INTR_MASK, 0xffff, 0);
1941 return (error);
1942 }
1943
1944 static usbd_status
1945 urtw_rx_setconf(struct urtw_softc *sc)
1946 {
1947 struct ieee80211com *ic = &sc->sc_ic;
1948 uint32_t data, a, b;
1949 usbd_status error;
1950
1951 if (urtw_read32_c(sc, URTW_RX, &data, 0))
1952 goto fail;
1953 data = data &~ URTW_RX_FILTER_MASK;
1954 data = data | URTW_RX_FILTER_MNG | URTW_RX_FILTER_DATA;
1955 data = data | URTW_RX_FILTER_BCAST | URTW_RX_FILTER_MCAST;
1956
1957 if (ic->ic_opmode == IEEE80211_M_MONITOR) {
1958 data = data | URTW_RX_FILTER_ICVERR;
1959 data = data | URTW_RX_FILTER_PWR;
1960 }
1961 if (sc->sc_crcmon == 1 && ic->ic_opmode == IEEE80211_M_MONITOR)
1962 data = data | URTW_RX_FILTER_CRCERR;
1963 data = data | URTW_RX_FILTER_NICMAC;
1964 data = data | URTW_RX_CHECK_BSSID;
1965 data = data &~ URTW_RX_FIFO_THRESHOLD_MASK;
1966 data = data | URTW_RX_FIFO_THRESHOLD_NONE | URTW_RX_AUTORESETPHY;
1967 data = data &~ URTW_MAX_RX_DMA_MASK;
1968 a = URTW_MAX_RX_DMA_2048;
1969 b = 0x80000000;
1970 data = data | a | b;
1971
1972 error = urtw_write32_c(sc, URTW_RX, data, 0);
1973 fail:
1974 return (error);
1975 }
1976
1977 static usbd_status
1978 urtw_rx_enable(struct urtw_softc *sc)
1979 {
1980 int i;
1981 usbd_status error;
1982 uint8_t data;
1983
1984 sc->rx_queued = 0;
1985 for (i = 0; i < URTW_RX_DATA_LIST_COUNT; i++) {
1986 if (urtw_rx_start(sc) != 0) {
1987 return (USB_FAILURE);
1988 }
1989 }
1990
1991 error = urtw_rx_setconf(sc);
1992 if (error != 0)
1993 goto fail;
1994
1995 if (error = urtw_read8_c(sc, URTW_CMD, &data, 0))
1996 goto fail;
1997 error = urtw_write8_c(sc, URTW_CMD, data | URTW_CMD_RX_ENABLE, 0);
1998 fail:
1999 return (error);
2000 }
2001
2002 void
2003 urtw_tx_enable(struct urtw_softc *sc)
2004 {
2005 uint8_t data8;
2006 uint32_t data;
2007
2008 if (sc->sc_hwrev & URTW_HWREV_8187) {
2009 (void) urtw_read8_c(sc, URTW_CW_CONF, &data8, 0);
2010 data8 &= ~(URTW_CW_CONF_PERPACKET_CW |
2011 URTW_CW_CONF_PERPACKET_RETRY);
2012 (void) urtw_write8_c(sc, URTW_CW_CONF, data8, 0);
2013 (void) urtw_read8_c(sc, URTW_TX_AGC_CTL, &data8, 0);
2014 data8 &= ~URTW_TX_AGC_CTL_PERPACKET_GAIN;
2015 data8 &= ~URTW_TX_AGC_CTL_PERPACKET_ANTSEL;
2016 data8 &= ~URTW_TX_AGC_CTL_FEEDBACK_ANT;
2017 (void) urtw_write8_c(sc, URTW_TX_AGC_CTL, data8, 0);
2018
2019 (void) urtw_read32_c(sc, URTW_TX_CONF, &data, 0);
2020 data &= ~URTW_TX_LOOPBACK_MASK;
2021 data |= URTW_TX_LOOPBACK_NONE;
2022 data &= ~(URTW_TX_DPRETRY_MASK | URTW_TX_RTSRETRY_MASK);
2023 data |= sc->sc_tx_retry << URTW_TX_DPRETRY_SHIFT;
2024 data |= sc->sc_rts_retry << URTW_TX_RTSRETRY_SHIFT;
2025 data &= ~(URTW_TX_NOCRC | URTW_TX_MXDMA_MASK);
2026 data |= URTW_TX_MXDMA_2048 | URTW_TX_CWMIN | URTW_TX_DISCW;
2027 data &= ~URTW_TX_SWPLCPLEN;
2028 data |= URTW_TX_NOICV;
2029 (void) urtw_write32_c(sc, URTW_TX_CONF, data, 0);
2030 } else {
2031 data = URTW_TX_DURPROCMODE | URTW_TX_DISREQQSIZE |
2032 URTW_TX_MXDMA_2048 | URTW_TX_SHORTRETRY |
2033 URTW_TX_LONGRETRY;
2034 (void) urtw_write32_c(sc, URTW_TX_CONF, data, 0);
2035 }
2036
2037 (void) urtw_read8_c(sc, URTW_CMD, &data8, 0);
2038 (void) urtw_write8_c(sc, URTW_CMD, data8 | URTW_CMD_TX_ENABLE, 0);
2039 }
2040
2041 static int
2042 urtw_8187_init(void *arg)
2043 {
2044 struct urtw_softc *sc = arg;
2045 usbd_status error;
2046 struct urtw_rf *rf = &sc->sc_rf;
2047 int i;
2048
2049 urtw_stop(sc);
2050 URTW_LOCK(sc);
2051 error = urtw_8187_reset(sc);
2052 if (error)
2053 goto fail;
2054
2055 (void) urtw_write8_c(sc, 0x85, 0, 0);
2056 (void) urtw_write8_c(sc, URTW_GPIO, 0, 0);
2057
2058 /* for led */
2059 (void) urtw_write8_c(sc, 0x85, 4, 0);
2060 error = urtw_led_ctl(sc, URTW_LED_CTL_POWER_ON);
2061 if (error != 0)
2062 goto fail;
2063
2064 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
2065 if (error)
2066 goto fail;
2067
2068 /* applying MAC address again. */
2069 for (i = 0; i < IEEE80211_ADDR_LEN; i++)
2070 (void) urtw_write8_c(sc, URTW_MAC0 + i,
2071 sc->sc_ic.ic_macaddr[i], 0);
2072 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
2073 if (error)
2074 goto fail;
2075
2076 error = urtw_update_msr(sc, IEEE80211_S_INIT);
2077 if (error)
2078 goto fail;
2079
2080 (void) urtw_write32_c(sc, URTW_INT_TIMEOUT, 0, 0);
2081 (void) urtw_write8_c(sc, URTW_WPA_CONFIG, 0, 0);
2082 (void) urtw_write8_c(sc, URTW_RATE_FALLBACK, 0x81, 0);
2083 error = urtw_set_rate(sc);
2084 if (error != 0)
2085 goto fail;
2086
2087 error = rf->init(rf);
2088 if (error != 0)
2089 goto fail;
2090 if (rf->set_sens != NULL)
2091 rf->set_sens(rf);
2092
2093 (void) urtw_write16_c(sc, 0x5e, 1, 0);
2094 (void) urtw_write16_c(sc, 0xfe, 0x10, 0);
2095 (void) urtw_write8_c(sc, URTW_TALLY_SEL, 0x80, 0);
2096 (void) urtw_write8_c(sc, 0xff, 0x60, 0);
2097 (void) urtw_write16_c(sc, 0x5e, 0, 0);
2098 (void) urtw_write8_c(sc, 0x85, 4, 0);
2099
2100 error = urtw_intr_enable(sc);
2101 if (error != 0)
2102 goto fail;
2103
2104 error = urtw_open_pipes(sc);
2105 if (error != 0)
2106 goto fail;
2107 sc->sc_tx_low_queued = 0;
2108 sc->sc_tx_normal_queued = 0;
2109 error = urtw_rx_enable(sc);
2110 if (error != 0)
2111 goto fail;
2112 urtw_tx_enable(sc);
2113
2114 if (error == 0) {
2115 URTW8187_DBG(URTW_DEBUG_ACTIVE, (sc->sc_dev,
2116 CE_CONT, "urtw_8187_init: succesfully done\n"));
2117 sc->sc_flags |= URTW_FLAG_RUNNING;
2118 URTW_UNLOCK(sc);
2119 return (error);
2120 }
2121
2122 fail:
2123 URTW_UNLOCK(sc);
2124 urtw_stop(sc);
2125 return (EIO);
2126 }
2127
2128
2129 static usbd_status
2130 urtw_8225_usb_init(struct urtw_softc *sc)
2131 {
2132 uint8_t data;
2133 usbd_status error;
2134
2135 if (error = urtw_write8_c(sc, URTW_RF_PINS_SELECT + 1, 0, 0))
2136 goto fail;
2137 if (error = urtw_write8_c(sc, URTW_GPIO, 0, 0))
2138 goto fail;
2139 if (error = urtw_read8e(sc, 0x53, &data))
2140 goto fail;
2141 if (error = urtw_write8e(sc, 0x53, data | (1 << 7)))
2142 goto fail;
2143 if (error = urtw_write8_c(sc, URTW_RF_PINS_SELECT + 1, 4, 0))
2144 goto fail;
2145 if (error = urtw_write8_c(sc, URTW_GPIO, 0x20, 0))
2146 goto fail;
2147 if (error = urtw_write8_c(sc, URTW_GP_ENABLE, 0, 0))
2148 goto fail;
2149 if (error = urtw_write16_c(sc, URTW_RF_PINS_OUTPUT, 0x80, 0))
2150 goto fail;
2151 if (error = urtw_write16_c(sc, URTW_RF_PINS_SELECT, 0x80, 0))
2152 goto fail;
2153 error = urtw_write16_c(sc, URTW_RF_PINS_ENABLE, 0x80, 0);
2154
2155 urtw_delay_ms(100);
2156 fail:
2157 return (error);
2158 }
2159
2160 static usbd_status
2161 urtw_8185_rf_pins_enable(struct urtw_softc *sc)
2162 {
2163 usbd_status error = 0;
2164
2165 error = urtw_write16_c(sc, URTW_RF_PINS_ENABLE, 0x1ff7, 0);
2166 return (error);
2167 }
2168
2169 static usbd_status
2170 urtw_8187_write_phy(struct urtw_softc *sc, uint8_t addr, uint32_t data)
2171 {
2172 uint32_t phyw;
2173 usbd_status error;
2174
2175 phyw = ((data << 8) | (addr | 0x80));
2176 if (error = urtw_write8_c(sc, 0x7f, ((phyw & 0xff000000) >> 24), 0))
2177 goto fail;
2178 if (error = urtw_write8_c(sc, 0x7e, ((phyw & 0x00ff0000) >> 16), 0))
2179 goto fail;
2180 if (error = urtw_write8_c(sc, 0x7d, ((phyw & 0x0000ff00) >> 8), 0))
2181 goto fail;
2182 error = urtw_write8_c(sc, 0x7c, (phyw & 0x000000ff), 0);
2183 /*
2184 * Delay removed from 8185 to 8187.
2185 * usbd_delay_ms(sc->sc_udev, 1);
2186 */
2187 fail:
2188 return (error);
2189 }
2190
2191 static usbd_status
2192 urtw_8187_write_phy_ofdm_c(struct urtw_softc *sc, uint8_t addr, uint32_t data)
2193 {
2194 data = data & 0xff;
2195 return (urtw_8187_write_phy(sc, addr, data));
2196 }
2197
2198 static usbd_status
2199 urtw_8187_write_phy_cck_c(struct urtw_softc *sc, uint8_t addr, uint32_t data)
2200 {
2201 data = data & 0xff;
2202 return (urtw_8187_write_phy(sc, addr, (data | 0x10000)));
2203 }
2204
2205 static usbd_status
2206 urtw_8225_setgain(struct urtw_softc *sc, int16_t gain)
2207 {
2208 usbd_status error;
2209
2210 if (error = urtw_8187_write_phy_ofdm_c(sc, 0x0d,
2211 urtw_8225_gain[gain * 4]))
2212 goto fail;
2213 if (error = urtw_8187_write_phy_ofdm_c(sc, 0x1b,
2214 urtw_8225_gain[gain * 4 + 2]))
2215 goto fail;
2216 if (error = urtw_8187_write_phy_ofdm_c(sc, 0x1d,
2217 urtw_8225_gain[gain * 4 + 3]))
2218 goto fail;
2219 error = urtw_8187_write_phy_ofdm_c(sc, 0x23,
2220 urtw_8225_gain[gain * 4 + 1]);
2221 fail:
2222 return (error);
2223 }
2224
2225 static usbd_status
2226 urtw_8225_set_txpwrlvl(struct urtw_softc *sc, int chan)
2227 {
2228 int i, idx, set;
2229 uint8_t *cck_pwltable;
2230 uint8_t cck_pwrlvl_max, ofdm_pwrlvl_min, ofdm_pwrlvl_max;
2231 uint8_t cck_pwrlvl = sc->sc_txpwr_cck[chan] & 0xff;
2232 uint8_t ofdm_pwrlvl = sc->sc_txpwr_ofdm[chan] & 0xff;
2233 usbd_status error;
2234
2235 cck_pwrlvl_max = 11;
2236 ofdm_pwrlvl_max = 25; /* 12 -> 25 */
2237 ofdm_pwrlvl_min = 10;
2238
2239 /* CCK power setting */
2240 cck_pwrlvl = (cck_pwrlvl > cck_pwrlvl_max) ?
2241 cck_pwrlvl_max : cck_pwrlvl;
2242 idx = cck_pwrlvl % 6;
2243 set = cck_pwrlvl / 6;
2244 cck_pwltable = (chan == 14) ? urtw_8225_txpwr_cck_ch14 :
2245 urtw_8225_txpwr_cck;
2246
2247 if (error = urtw_write8_c(sc, URTW_TX_GAIN_CCK,
2248 urtw_8225_tx_gain_cck_ofdm[set] >> 1, 0))
2249 goto fail;
2250 for (i = 0; i < 8; i++) {
2251 if (error = urtw_8187_write_phy_cck_c(sc, 0x44 + i,
2252 cck_pwltable[idx * 8 + i]))
2253 goto fail;
2254 }
2255 urtw_delay_ms(1);
2256 /* OFDM power setting */
2257 ofdm_pwrlvl = (ofdm_pwrlvl > (ofdm_pwrlvl_max - ofdm_pwrlvl_min)) ?
2258 ofdm_pwrlvl_max : ofdm_pwrlvl + ofdm_pwrlvl_min;
2259 ofdm_pwrlvl = (ofdm_pwrlvl > 35) ? 35 : ofdm_pwrlvl;
2260 idx = ofdm_pwrlvl % 6;
2261 set = ofdm_pwrlvl / 6;
2262
2263 error = urtw_8185_set_anaparam2(sc, URTW_8187_8225_ANAPARAM2_ON);
2264 if (error)
2265 goto fail;
2266 if (error = urtw_8187_write_phy_ofdm_c(sc, 2, 0x42))
2267 goto fail;
2268 if (error = urtw_8187_write_phy_ofdm_c(sc, 6, 0))
2269 goto fail;
2270 if (error = urtw_8187_write_phy_ofdm_c(sc, 8, 0))
2271 goto fail;
2272
2273 if (error = urtw_write8_c(sc, URTW_TX_GAIN_OFDM,
2274 urtw_8225_tx_gain_cck_ofdm[set] >> 1, 0))
2275 goto fail;
2276 if (error = urtw_8187_write_phy_ofdm_c(sc, 0x5,
2277 urtw_8225_txpwr_ofdm[idx]))
2278 goto fail;
2279 error = urtw_8187_write_phy_ofdm_c(sc, 0x7,
2280 urtw_8225_txpwr_ofdm[idx]);
2281 urtw_delay_ms(1);
2282 fail:
2283 return (error);
2284 }
2285
2286 static usbd_status
2287 urtw_8185_tx_antenna(struct urtw_softc *sc, uint8_t ant)
2288 {
2289 usbd_status error;
2290
2291 error = urtw_write8_c(sc, URTW_TX_ANTENNA, ant, 0);
2292 urtw_delay_ms(1);
2293 return (error);
2294 }
2295
2296 static usbd_status
2297 urtw_8225_rf_init(struct urtw_rf *rf)
2298 {
2299 #define N(a) (sizeof (a) / sizeof ((a)[0]))
2300 int i;
2301 uint16_t data;
2302 usbd_status error;
2303 struct urtw_softc *sc = rf->rf_sc;
2304
2305 error = urtw_8180_set_anaparam(sc, URTW_8187_8225_ANAPARAM_ON);
2306 if (error)
2307 goto fail;
2308
2309 if (error = urtw_8225_usb_init(sc))
2310 goto fail;
2311 if (error = urtw_write32_c(sc, URTW_RF_TIMING, 0x000a8008, 0))
2312 goto fail;
2313 if (error = urtw_read16_c(sc, URTW_BRSR, &data, 0))
2314 goto fail;
2315 if (error = urtw_write16_c(sc, URTW_BRSR, 0xffff, 0))
2316 goto fail;
2317 if (error = urtw_write32_c(sc, URTW_RF_PARA, 0x100044, 0))
2318 goto fail;
2319
2320 if (error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG))
2321 goto fail;
2322 if (error = urtw_write8_c(sc, URTW_CONFIG3, 0x44, 0))
2323 goto fail;
2324 if (error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL))
2325 goto fail;
2326 if (error = urtw_8185_rf_pins_enable(sc))
2327 goto fail;
2328 urtw_delay_ms(100);
2329
2330 for (i = 0; i < N(urtw_8225_rf_part1); i++) {
2331 if (error = urtw_8225_write_c(sc, urtw_8225_rf_part1[i].reg,
2332 urtw_8225_rf_part1[i].val))
2333 goto fail;
2334 urtw_delay_ms(1);
2335 }
2336 urtw_delay_ms(50);
2337 if (error = urtw_8225_write_c(sc, 0x2, 0xc4d))
2338 goto fail;
2339 urtw_delay_ms(50);
2340 if (error = urtw_8225_write_c(sc, 0x2, 0x44d))
2341 goto fail;
2342 urtw_delay_ms(50);
2343 if (error = urtw_8225_write_c(sc, 0x0, 0x127))
2344 goto fail;
2345
2346 for (i = 0; i < 95; i++) {
2347 if (error = urtw_8225_write_c(sc, 0x1, (uint8_t)(i + 1)))
2348 goto fail;
2349 if (error = urtw_8225_write_c(sc, 0x2, urtw_8225_rxgain[i]))
2350 goto fail;
2351 }
2352
2353 if (error = urtw_8225_write_c(sc, 0x0, 0x27))
2354 goto fail;
2355 if (error = urtw_8225_write_c(sc, 0x0, 0x22f))
2356 goto fail;
2357
2358 for (i = 0; i < 128; i++) {
2359 if (error = urtw_8187_write_phy_ofdm_c(sc, 0xb,
2360 urtw_8225_agc[i]))
2361 goto fail;
2362 urtw_delay_ms(1);
2363 if (error = urtw_8187_write_phy_ofdm_c(sc, 0xa,
2364 (uint8_t)i + 0x80))
2365 goto fail;
2366 urtw_delay_ms(1);
2367 }
2368
2369 for (i = 0; i < N(urtw_8225_rf_part2); i++) {
2370 if (error = urtw_8187_write_phy_ofdm_c(sc,
2371 urtw_8225_rf_part2[i].reg,
2372 urtw_8225_rf_part2[i].val))
2373 goto fail;
2374 urtw_delay_ms(1);
2375 }
2376 error = urtw_8225_setgain(sc, 4);
2377 if (error)
2378 goto fail;
2379
2380 for (i = 0; i < N(urtw_8225_rf_part3); i++) {
2381 if (error = urtw_8187_write_phy_cck_c(sc,
2382 urtw_8225_rf_part3[i].reg,
2383 urtw_8225_rf_part3[i].val))
2384 goto fail;
2385 urtw_delay_ms(1);
2386 }
2387
2388 if (error = urtw_write8_c(sc, 0x5b, 0x0d, 0))
2389 goto fail;
2390 if (error = urtw_8225_set_txpwrlvl(sc, 1))
2391 goto fail;
2392 if (error = urtw_8187_write_phy_cck_c(sc, 0x10, 0x9b))
2393 goto fail;
2394 urtw_delay_ms(1);
2395 if (error = urtw_8187_write_phy_ofdm_c(sc, 0x26, 0x90))
2396 goto fail;
2397 urtw_delay_ms(1);
2398
2399 /* TX ant A, 0x0 for B */
2400 if (error = urtw_8185_tx_antenna(sc, 0x3))
2401 goto fail;
2402 if (error = urtw_write32_c(sc, 0x94, 0x3dc00002, 0))
2403 goto fail;
2404
2405 error = urtw_8225_rf_set_chan(rf,
2406 ieee80211_chan2ieee(&sc->sc_ic, sc->sc_ic.ic_curchan));
2407 fail:
2408 return (error);
2409 #undef N
2410 }
2411
2412 static usbd_status
2413 urtw_8225_rf_set_chan(struct urtw_rf *rf, int chan)
2414 {
2415 #define IEEE80211_CHAN_G \
2416 (IEEE80211_CHAN_2GHZ | IEEE80211_CHAN_DYN)
2417 #define IEEE80211_IS_CHAN_G(_c) \
2418 (((_c)->ich_flags & IEEE80211_CHAN_G) == IEEE80211_CHAN_G)
2419
2420 struct urtw_softc *sc = rf->rf_sc;
2421 struct ieee80211com *ic = &sc->sc_ic;
2422 struct ieee80211_channel *c = ic->ic_curchan;
2423 short gset = (IEEE80211_IS_CHAN_G(c)) ? 1 : 0;
2424 usbd_status error;
2425
2426 if (error = urtw_8225_set_txpwrlvl(sc, chan))
2427 goto fail;
2428 if (urtw_8225_write_c(sc, 0x7, urtw_8225_channel[chan]))
2429 goto fail;
2430 urtw_delay_ms(10);
2431
2432 if (error = urtw_write8_c(sc, URTW_SIFS, 0x22, 0))
2433 goto fail;
2434
2435 if (ic->ic_state == IEEE80211_S_ASSOC &&
2436 ic->ic_flags & IEEE80211_F_SHSLOT)
2437 if (error = urtw_write8_c(sc, URTW_SLOT, 0x9, 0))
2438 goto fail;
2439 else
2440 if (error = urtw_write8_c(sc, URTW_SLOT, 0x14, 0))
2441 goto fail;
2442 if (gset) {
2443 /* for G */
2444 if (error = urtw_write8_c(sc, URTW_DIFS, 0x14, 0))
2445 goto fail;
2446 if (error = urtw_write8_c(sc, URTW_EIFS, 0x5b - 0x14, 0))
2447 goto fail;
2448 error = urtw_write8_c(sc, URTW_CW_VAL, 0x73, 0);
2449 } else {
2450 /* for B */
2451 if (error = urtw_write8_c(sc, URTW_DIFS, 0x24, 0))
2452 goto fail;
2453 if (error = urtw_write8_c(sc, URTW_EIFS, 0x5b - 0x24, 0))
2454 goto fail;
2455 error = urtw_write8_c(sc, URTW_CW_VAL, 0xa5, 0);
2456 }
2457
2458 fail:
2459 return (error);
2460 }
2461
2462 static usbd_status
2463 urtw_8225_rf_set_sens(struct urtw_rf *rf)
2464 {
2465 usbd_status error;
2466 struct urtw_softc *sc = rf->rf_sc;
2467
2468 if (rf->sens < 0 || rf->sens > 6)
2469 return (-1);
2470
2471 if (rf->sens > 4)
2472 if (error = urtw_8225_write_c(sc, 0x0c, 0x850))
2473 goto fail;
2474 else
2475 if (error = urtw_8225_write_c(sc, 0x0c, 0x50))
2476 goto fail;
2477
2478 rf->sens = 6 - rf->sens;
2479 if (error = urtw_8225_setgain(sc, rf->sens))
2480 goto fail;
2481 error = urtw_8187_write_phy_cck_c(sc, 0x41,
2482 urtw_8225_threshold[rf->sens]);
2483 fail:
2484 return (error);
2485 }
2486
2487 static void
2488 urtw_stop(struct urtw_softc *sc)
2489 {
2490 URTW_LOCK(sc);
2491 sc->sc_flags &= ~URTW_FLAG_RUNNING;
2492 URTW_UNLOCK(sc);
2493 urtw_close_pipes(sc);
2494 }
2495
2496 static int
2497 urtw_isbmode(uint16_t rate)
2498 {
2499
2500 rate = urtw_rtl2rate(rate);
2501
2502 return ((rate <= 22 && rate != 12 && rate != 18)?(1) : (0));
2503 }
2504
2505 /* ARGSUSED */
2506 static void
2507 urtw_rxeof(usb_pipe_handle_t pipe, usb_bulk_req_t *req)
2508 {
2509 struct urtw_softc *sc = (struct urtw_softc *)req->bulk_client_private;
2510 struct ieee80211com *ic = &sc->sc_ic;
2511 int actlen, len, flen, rssi;
2512 uint8_t *desc, rate;
2513 struct ieee80211_frame *wh;
2514 struct ieee80211_node *ni = 0;
2515 mblk_t *mp = 0;
2516 uint8_t *rxbuf;
2517
2518 mp = req->bulk_data;
2519 req->bulk_data = NULL;
2520 if (req->bulk_completion_reason != USB_CR_OK ||
2521 mp == NULL) {
2522 sc->sc_rx_err++;
2523 URTW8187_DBG(URTW_DEBUG_RX_PROC, (sc->sc_dev, CE_CONT,
2524 "urtw_rxeof failed! %d, mp %p\n",
2525 req->bulk_completion_reason, mp));
2526 req->bulk_data = mp;
2527 goto fail;
2528 }
2529
2530 actlen = MBLKL(mp);
2531 rxbuf = (uint8_t *)mp->b_rptr;
2532
2533 if (sc->sc_hwrev & URTW_HWREV_8187)
2534 /* 4 dword and 4 byte CRC */
2535 len = actlen - (4 * 4);
2536 else
2537 /* 5 dword and 4 byte CRC */
2538 len = actlen - (4 * 5);
2539
2540 desc = rxbuf + len;
2541 flen = ((desc[1] & 0x0f) << 8) + (desc[0] & 0xff);
2542 if (flen > actlen) {
2543 cmn_err(CE_CONT, "urtw_rxeof: impossible: flen %d, actlen %d\n",
2544 flen, actlen);
2545 sc->sc_rx_err++;
2546 req->bulk_data = mp;
2547 goto fail;
2548 }
2549
2550 rate = (desc[2] & 0xf0) >> 4;
2551 if (sc->sc_hwrev & URTW_HWREV_8187) {
2552 rssi = (desc[6] & 0xfe) >> 1;
2553
2554 /* XXX correct? */
2555 if (!urtw_isbmode(rate)) {
2556 rssi = (rssi > 90) ? 90 : ((rssi < 25) ? 25 : rssi);
2557 rssi = ((90 - rssi) * 100) / 65;
2558 } else {
2559 rssi = (rssi > 90) ? 95 : ((rssi < 30) ? 30 : rssi);
2560 rssi = ((95 - rssi) * 100) / 65;
2561 }
2562 } else {
2563 rssi = 14 + desc[13]/2;
2564 if (rssi >= 95)
2565 rssi = 95;
2566 URTW8187_DBG(URTW_DEBUG_RX_PROC, (sc->sc_dev, CE_CONT,
2567 "urtw_rxeof: rssi %u\n", rssi));
2568 }
2569
2570 mp->b_wptr = mp->b_rptr + flen - 4;
2571 wh = (struct ieee80211_frame *)mp->b_rptr;
2572 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK)
2573 == IEEE80211_FC0_TYPE_DATA) {
2574 sc->sc_currate = (rate > 0) ? rate : sc->sc_currate;
2575 URTW8187_DBG(URTW_DEBUG_RX_PROC, (sc->sc_dev, CE_CONT,
2576 "urtw_rxeof: update sc_currate to %u\n",
2577 sc->sc_currate));
2578 }
2579 ni = ieee80211_find_rxnode(ic, wh);
2580
2581 /* send the frame to the 802.11 layer */
2582 (void) ieee80211_input(ic, mp, ni, rssi, 0);
2583
2584 /* node is no longer needed */
2585 ieee80211_free_node(ni);
2586 fail:
2587 mutex_enter(&sc->rx_lock);
2588 sc->rx_queued--;
2589 mutex_exit(&sc->rx_lock);
2590 usb_free_bulk_req(req);
2591 if (URTW_IS_RUNNING(sc) && !URTW_IS_SUSPENDING(sc))
2592 (void) urtw_rx_start(sc);
2593 }
2594
2595 static usbd_status
2596 urtw_8225v2_setgain(struct urtw_softc *sc, int16_t gain)
2597 {
2598 uint8_t *gainp;
2599 usbd_status error;
2600
2601 /* XXX for A? */
2602 gainp = urtw_8225v2_gain_bg;
2603 if (error = urtw_8187_write_phy_ofdm_c(sc, 0x0d, gainp[gain * 3]))
2604 goto fail;
2605 urtw_delay_ms(1);
2606 if (error = urtw_8187_write_phy_ofdm_c(sc, 0x1b, gainp[gain * 3 + 1]))
2607 urtw_delay_ms(1);
2608 if (error = urtw_8187_write_phy_ofdm_c(sc, 0x1d, gainp[gain * 3 + 2]))
2609 goto fail;
2610 urtw_delay_ms(1);
2611 if (error = urtw_8187_write_phy_ofdm_c(sc, 0x21, 0x17))
2612 goto fail;
2613 urtw_delay_ms(1);
2614 fail:
2615 return (error);
2616 }
2617
2618 static usbd_status
2619 urtw_8225v2_set_txpwrlvl(struct urtw_softc *sc, int chan)
2620 {
2621 int i;
2622 uint8_t *cck_pwrtable;
2623 uint8_t cck_pwrlvl_max = 15, ofdm_pwrlvl_max = 25, ofdm_pwrlvl_min = 10;
2624 uint8_t cck_pwrlvl = sc->sc_txpwr_cck[chan] & 0xff;
2625 uint8_t ofdm_pwrlvl = sc->sc_txpwr_ofdm[chan] & 0xff;
2626 usbd_status error;
2627
2628 /* CCK power setting */
2629 cck_pwrlvl = (cck_pwrlvl > cck_pwrlvl_max) ?
2630 cck_pwrlvl_max : cck_pwrlvl;
2631 cck_pwrlvl += sc->sc_txpwr_cck_base;
2632 cck_pwrlvl = (cck_pwrlvl > 35) ? 35 : cck_pwrlvl;
2633 cck_pwrtable = (chan == 14) ? urtw_8225v2_txpwr_cck_ch14 :
2634 urtw_8225v2_txpwr_cck;
2635
2636 for (i = 0; i < 8; i++) {
2637 if (error = urtw_8187_write_phy_cck_c(sc, 0x44 + i,
2638 cck_pwrtable[i]))
2639 goto fail;
2640 }
2641 if (error = urtw_write8_c(sc, URTW_TX_GAIN_CCK,
2642 urtw_8225v2_tx_gain_cck_ofdm[cck_pwrlvl], 0))
2643 goto fail;
2644 urtw_delay_ms(1);
2645
2646 /* OFDM power setting */
2647 ofdm_pwrlvl = (ofdm_pwrlvl > (ofdm_pwrlvl_max - ofdm_pwrlvl_min)) ?
2648 ofdm_pwrlvl_max : ofdm_pwrlvl + ofdm_pwrlvl_min;
2649 ofdm_pwrlvl += sc->sc_txpwr_ofdm_base;
2650 ofdm_pwrlvl = (ofdm_pwrlvl > 35) ? 35 : ofdm_pwrlvl;
2651
2652 error = urtw_8185_set_anaparam2(sc, URTW_8187_8225_ANAPARAM2_ON);
2653 if (error)
2654 goto fail;
2655
2656 if (error = urtw_8187_write_phy_ofdm_c(sc, 2, 0x42))
2657 goto fail;
2658 if (error = urtw_8187_write_phy_ofdm_c(sc, 5, 0x0))
2659 goto fail;
2660 if (error = urtw_8187_write_phy_ofdm_c(sc, 6, 0x40))
2661 goto fail;
2662 if (error = urtw_8187_write_phy_ofdm_c(sc, 7, 0x0))
2663 goto fail;
2664 if (error = urtw_8187_write_phy_ofdm_c(sc, 8, 0x40))
2665 goto fail;
2666
2667 error = urtw_write8_c(sc, URTW_TX_GAIN_OFDM,
2668 urtw_8225v2_tx_gain_cck_ofdm[ofdm_pwrlvl], 0);
2669 urtw_delay_ms(1);
2670 fail:
2671 return (error);
2672 }
2673
2674 static usbd_status
2675 urtw_8225v2_rf_init(struct urtw_rf *rf)
2676 {
2677 #define N(a) (sizeof (a)/ sizeof ((a)[0]))
2678 int i;
2679 uint16_t data;
2680 uint32_t data32;
2681 usbd_status error;
2682 struct urtw_softc *sc = rf->rf_sc;
2683
2684 if (error = urtw_8180_set_anaparam(sc, URTW_8187_8225_ANAPARAM_ON))
2685 goto fail;
2686 if (error = urtw_8225_usb_init(sc))
2687 goto fail;
2688 if (error = urtw_write32_c(sc, URTW_RF_TIMING, 0x000a8008, 0))
2689 goto fail;
2690 if (error = urtw_read16_c(sc, URTW_BRSR, &data, 0))
2691 goto fail;
2692 if (error = urtw_write16_c(sc, URTW_BRSR, 0xffff, 0))
2693 goto fail;
2694 if (error = urtw_write32_c(sc, URTW_RF_PARA, 0x100044, 0))
2695 goto fail;
2696 if (error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG))
2697 goto fail;
2698 if (error = urtw_write8_c(sc, URTW_CONFIG3, 0x44, 0))
2699 goto fail;
2700 if (error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL))
2701 goto fail;
2702 if (error = urtw_8185_rf_pins_enable(sc))
2703 goto fail;
2704
2705 urtw_delay_ms(500);
2706
2707 for (i = 0; i < N(urtw_8225v2_rf_part1); i++) {
2708 if (error = urtw_8225_write_c(sc, urtw_8225v2_rf_part1[i].reg,
2709 urtw_8225v2_rf_part1[i].val))
2710 goto fail;
2711 urtw_delay_ms(1);
2712 }
2713 urtw_delay_ms(100);
2714
2715 if (error = urtw_8225_write_c(sc, 0x0, 0x1b7))
2716 goto fail;
2717
2718 for (i = 0; i < 95; i++) {
2719 if (error = urtw_8225_write_c(sc, 0x1, (uint8_t)(i + 1)))
2720 goto fail;
2721 urtw_delay_ms(1);
2722 if (error = urtw_8225_write_c(sc, 0x2, urtw_8225v2_rxgain[i]))
2723 goto fail;
2724 urtw_delay_ms(1);
2725 }
2726
2727 if (error = urtw_8225_write_c(sc, 0x3, 0x2))
2728 goto fail;
2729 urtw_delay_ms(1);
2730 if (error = urtw_8225_write_c(sc, 0x5, 0x4))
2731 goto fail;
2732 urtw_delay_ms(1);
2733 if (error = urtw_8225_write_c(sc, 0x0, 0xb7))
2734 goto fail;
2735 urtw_delay_ms(1);
2736 if (error = urtw_8225_write_c(sc, 0x2, 0xc4d))
2737 goto fail;
2738 urtw_delay_ms(100);
2739 if (error = urtw_8225_write_c(sc, 0x2, 0x44d))
2740 goto fail;
2741 urtw_delay_ms(100);
2742
2743 if (error = urtw_8225_read(sc, 0x6, &data32))
2744 goto fail;
2745 if (data32 != 0xe6) {
2746 error = (-1);
2747 cmn_err(CE_WARN, "expect 0xe6!! (0x%x)\n", data32);
2748 goto fail;
2749 }
2750 if (!(data32 & 0x80)) {
2751 if (error = urtw_8225_write_c(sc, 0x02, 0x0c4d))
2752 goto fail;
2753 urtw_delay_ms(200);
2754 if (error = urtw_8225_write_c(sc, 0x02, 0x044d))
2755 goto fail;
2756 urtw_delay_ms(100);
2757 if (error = urtw_8225_read(sc, 0x6, &data32))
2758 goto fail;
2759 if (!(data32 & 0x80))
2760 cmn_err(CE_CONT, "RF calibration failed\n");
2761 }
2762 urtw_delay_ms(200);
2763
2764 if (error = urtw_8225_write_c(sc, 0x0, 0x2bf))
2765 goto fail;
2766 for (i = 0; i < 128; i++) {
2767 if (error = urtw_8187_write_phy_ofdm_c(sc, 0xb,
2768 urtw_8225_agc[i]))
2769 goto fail;
2770 urtw_delay_ms(1);
2771 if (error = urtw_8187_write_phy_ofdm_c(sc, 0xa,
2772 (uint8_t)i + 0x80))
2773 goto fail;
2774 urtw_delay_ms(1);
2775 }
2776 urtw_delay_ms(1);
2777
2778 for (i = 0; i < N(urtw_8225v2_rf_part2); i++) {
2779 if (error = urtw_8187_write_phy_ofdm_c(sc,
2780 urtw_8225v2_rf_part2[i].reg,
2781 urtw_8225v2_rf_part2[i].val))
2782 goto fail;
2783 urtw_delay_ms(1);
2784 }
2785 error = urtw_8225v2_setgain(sc, 4);
2786 if (error)
2787 goto fail;
2788
2789 for (i = 0; i < N(urtw_8225v2_rf_part3); i++) {
2790 if (error = urtw_8187_write_phy_cck_c(sc,
2791 urtw_8225v2_rf_part3[i].reg,
2792 urtw_8225v2_rf_part3[i].val))
2793 goto fail;
2794 urtw_delay_ms(1);
2795 }
2796
2797 if (error = urtw_write8_c(sc, 0x5b, 0x0d, 0))
2798 goto fail;
2799 if (error = urtw_8225v2_set_txpwrlvl(sc, 1))
2800 goto fail;
2801 if (error = urtw_8187_write_phy_cck_c(sc, 0x10, 0x9b))
2802 goto fail;
2803 urtw_delay_ms(1);
2804 if (error = urtw_8187_write_phy_ofdm_c(sc, 0x26, 0x90))
2805 goto fail;
2806 urtw_delay_ms(1);
2807
2808 /* TX ant A, 0x0 for B */
2809 if (error = urtw_8185_tx_antenna(sc, 0x3))
2810 goto fail;
2811 if (error = urtw_write32_c(sc, 0x94, 0x3dc00002, 0))
2812 goto fail;
2813
2814 error = urtw_8225_rf_set_chan(rf,
2815 ieee80211_chan2ieee(&sc->sc_ic, sc->sc_ic.ic_curchan));
2816 fail:
2817 return (error);
2818 #undef N
2819 }
2820
2821 static usbd_status
2822 urtw_8225v2_rf_set_chan(struct urtw_rf *rf, int chan)
2823 {
2824 struct urtw_softc *sc = rf->rf_sc;
2825 struct ieee80211com *ic = &sc->sc_ic;
2826 struct ieee80211_channel *c = ic->ic_curchan;
2827 short gset = (IEEE80211_IS_CHAN_G(c)) ? 1 : 0;
2828 usbd_status error;
2829
2830 if (error = urtw_8225v2_set_txpwrlvl(sc, chan))
2831 goto fail;
2832
2833 if (error = urtw_8225_write_c(sc, 0x7, urtw_8225_channel[chan]))
2834 goto fail;
2835
2836 urtw_delay_ms(10);
2837
2838 if (error = urtw_write8_c(sc, URTW_SIFS, 0x22, 0))
2839 goto fail;
2840
2841 if (ic->ic_state == IEEE80211_S_ASSOC &&
2842 ic->ic_flags & IEEE80211_F_SHSLOT) {
2843 if (error = urtw_write8_c(sc, URTW_SLOT, 0x9, 0))
2844 goto fail;
2845 } else
2846 if (error = urtw_write8_c(sc, URTW_SLOT, 0x14, 0))
2847 goto fail;
2848 if (gset) {
2849 /* for G */
2850 if (error = urtw_write8_c(sc, URTW_DIFS, 0x14, 0))
2851 goto fail;
2852 if (error = urtw_write8_c(sc, URTW_EIFS, 0x5b - 0x14, 0))
2853 goto fail;
2854 if (error = urtw_write8_c(sc, URTW_CW_VAL, 0x73, 0))
2855 goto fail;
2856 } else {
2857 /* for B */
2858 if (error = urtw_write8_c(sc, URTW_DIFS, 0x24, 0))
2859 goto fail;
2860 if (error = urtw_write8_c(sc, URTW_EIFS, 0x5b - 0x24, 0))
2861 goto fail;
2862 if (error = urtw_write8_c(sc, URTW_CW_VAL, 0xa5, 0))
2863 goto fail;
2864 }
2865
2866 fail:
2867 return (error);
2868 }
2869
2870 static int
2871 urtw_set_channel(struct urtw_softc *sc)
2872 {
2873 struct ieee80211com *ic = &sc->sc_ic;
2874 struct urtw_rf *rf = &sc->sc_rf;
2875 uint32_t data;
2876 usbd_status error;
2877
2878 if (error = urtw_read32_c(sc, URTW_TX_CONF, &data, 0))
2879 goto fail;
2880 data &= ~URTW_TX_LOOPBACK_MASK;
2881 if (error = urtw_write32_c(sc, URTW_TX_CONF,
2882 data | URTW_TX_LOOPBACK_MAC, 0))
2883 goto fail;
2884 error = rf->set_chan(rf, ieee80211_chan2ieee(ic, ic->ic_curchan));
2885 if (error)
2886 goto fail;
2887 urtw_delay_ms(20);
2888 error = urtw_write32_c(sc, URTW_TX_CONF,
2889 data | URTW_TX_LOOPBACK_NONE, 0);
2890 fail:
2891 return (error);
2892 }
2893
2894 /* ARGSUSED */
2895 static void
2896 urtw_txeof_low(usb_pipe_handle_t pipe, usb_bulk_req_t *req)
2897 {
2898 struct urtw_softc *sc = (struct urtw_softc *)req->bulk_client_private;
2899 struct ieee80211com *ic = &sc->sc_ic;
2900
2901 URTW8187_DBG(URTW_DEBUG_TX_PROC, (sc->sc_dev, CE_CONT,
2902 "urtw_txeof_low(): cr:%s(%d), flags:0x%x, tx_queued:%d",
2903 usb_str_cr(req->bulk_completion_reason),
2904 req->bulk_completion_reason,
2905 req->bulk_cb_flags,
2906 sc->sc_tx_low_queued));
2907 mutex_enter(&sc->tx_lock);
2908 if (req->bulk_completion_reason != USB_CR_OK) {
2909 ic->ic_stats.is_tx_failed++;
2910 goto fail;
2911 }
2912
2913 if (sc->sc_need_sched) {
2914 sc->sc_need_sched = 0;
2915 mac_tx_update(ic->ic_mach);
2916 }
2917 fail:
2918 sc->sc_tx_low_queued--;
2919 mutex_exit(&sc->tx_lock);
2920 usb_free_bulk_req(req);
2921 }
2922
2923 /* ARGSUSED */
2924 static void
2925 urtw_txeof_normal(usb_pipe_handle_t pipe, usb_bulk_req_t *req)
2926 {
2927 struct urtw_softc *sc = (struct urtw_softc *)req->bulk_client_private;
2928 struct ieee80211com *ic = &sc->sc_ic;
2929
2930 URTW8187_DBG(URTW_DEBUG_ACTIVE, (sc->sc_dev, CE_CONT,
2931 "urtw_txeof_normal(): cr:%s(%d), flags:0x%x, tx_queued:%d",
2932 usb_str_cr(req->bulk_completion_reason),
2933 req->bulk_completion_reason,
2934 req->bulk_cb_flags,
2935 sc->sc_tx_normal_queued));
2936
2937 mutex_enter(&sc->tx_lock);
2938 if (req->bulk_completion_reason != USB_CR_OK) {
2939 ic->ic_stats.is_tx_failed++;
2940 goto fail;
2941 }
2942
2943 if (sc->sc_need_sched) {
2944 sc->sc_need_sched = 0;
2945 mac_tx_update(ic->ic_mach);
2946 }
2947 fail:
2948 sc->sc_tx_normal_queued--;
2949 mutex_exit(&sc->tx_lock);
2950 usb_free_bulk_req(req);
2951 }
2952
2953
2954 static int
2955 urtw_get_rate(struct ieee80211com *ic)
2956 {
2957 uint8_t (*rates)[IEEE80211_RATE_MAXSIZE];
2958 int rate;
2959
2960 rates = &ic->ic_bss->in_rates.ir_rates;
2961
2962 if (ic->ic_fixed_rate != IEEE80211_FIXED_RATE_NONE)
2963 rate = ic->ic_fixed_rate;
2964 else if (ic->ic_state == IEEE80211_S_RUN)
2965 rate = (*rates)[ic->ic_bss->in_txrate];
2966 else
2967 rate = 0;
2968 return (rate & IEEE80211_RATE_VAL);
2969 }
2970
2971 void
2972 urtw_8187b_update_wmm(struct urtw_softc *sc)
2973 {
2974 struct ieee80211com *ic = &sc->sc_ic;
2975 struct ieee80211_channel *c = ic->ic_curchan;
2976 uint32_t data;
2977 uint8_t aifs, sifs, slot, ecwmin, ecwmax;
2978
2979 sifs = 0xa;
2980 if (IEEE80211_IS_CHAN_G(c))
2981 slot = 0x9;
2982 else
2983 slot = 0x14;
2984
2985 aifs = (2 * slot) + sifs;
2986 ecwmin = 3;
2987 ecwmax = 7;
2988
2989 data = ((uint32_t)aifs << 0) | /* AIFS, offset 0 */
2990 ((uint32_t)ecwmin << 8) | /* ECW minimum, offset 8 */
2991 ((uint32_t)ecwmax << 12); /* ECW maximum, offset 16 */
2992
2993 (void) urtw_write32_c(sc, URTW_AC_VO, data, 0);
2994 (void) urtw_write32_c(sc, URTW_AC_VI, data, 0);
2995 (void) urtw_write32_c(sc, URTW_AC_BE, data, 0);
2996 (void) urtw_write32_c(sc, URTW_AC_BK, data, 0);
2997 }
2998
2999 usbd_status
3000 urtw_8187b_reset(struct urtw_softc *sc)
3001 {
3002 uint8_t data;
3003 usbd_status error;
3004
3005 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
3006 if (error)
3007 goto fail;
3008
3009 (void) urtw_read8_c(sc, URTW_CONFIG3, &data, 0);
3010 (void) urtw_write8_c(sc, URTW_CONFIG3,
3011 data | URTW_CONFIG3_ANAPARAM_WRITE |
3012 URTW_CONFIG3_GNT_SELECT, 0);
3013
3014 (void) urtw_write32_c(sc, URTW_ANAPARAM2,
3015 URTW_8187B_8225_ANAPARAM2_ON, 0);
3016 (void) urtw_write32_c(sc, URTW_ANAPARAM,
3017 URTW_8187B_8225_ANAPARAM_ON, 0);
3018 (void) urtw_write8_c(sc, URTW_ANAPARAM3,
3019 URTW_8187B_8225_ANAPARAM3_ON, 0);
3020
3021 (void) urtw_write8_c(sc, 0x61, 0x10, 0);
3022 (void) urtw_read8_c(sc, 0x62, &data, 0);
3023 (void) urtw_write8_c(sc, 0x62, data & ~(1 << 5), 0);
3024 (void) urtw_write8_c(sc, 0x62, data | (1 << 5), 0);
3025
3026 (void) urtw_read8_c(sc, URTW_CONFIG3, &data, 0);
3027 (void) urtw_write8_c(sc, URTW_CONFIG3,
3028 data & ~URTW_CONFIG3_ANAPARAM_WRITE, 0);
3029
3030 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
3031 if (error)
3032 goto fail;
3033
3034 (void) urtw_read8_c(sc, URTW_CMD, &data, 0);
3035 data = (data & 2) | URTW_CMD_RST;
3036 (void) urtw_write8_c(sc, URTW_CMD, data, 0);
3037 urtw_delay_ms(100);
3038
3039 (void) urtw_read8_c(sc, URTW_CMD, &data, 0);
3040 if (data & URTW_CMD_RST) {
3041 cmn_err(CE_WARN, "urtw: 8187b reset timeout\n");
3042 goto fail;
3043 }
3044
3045 fail:
3046 return (error);
3047 }
3048
3049 static int
3050 urtw_8187b_init(void *arg)
3051 {
3052 struct urtw_softc *sc = arg;
3053 struct urtw_rf *rf = &sc->sc_rf;
3054 struct ieee80211com *ic = &sc->sc_ic;
3055 int i;
3056 uint8_t data;
3057 usbd_status error;
3058
3059 urtw_stop(sc);
3060 URTW_LOCK(sc);
3061 urtw_8187b_update_wmm(sc);
3062 error = urtw_8187b_reset(sc);
3063 if (error)
3064 goto fail;
3065
3066 error = urtw_open_pipes(sc);
3067 if (error != 0)
3068 goto fail;
3069 /* Applying MAC address again. */
3070 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
3071 if (error)
3072 goto fail;
3073 for (i = 0; i < IEEE80211_ADDR_LEN; i++)
3074 (void) urtw_write8_c(sc, URTW_MAC0 + i,
3075 ic->ic_macaddr[i], 0);
3076 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
3077 if (error)
3078 goto fail;
3079
3080 error = urtw_update_msr(sc, IEEE80211_S_INIT);
3081 if (error)
3082 goto fail;
3083
3084 error = rf->init(rf);
3085 if (error != 0)
3086 goto fail;
3087 error = urtw_intr_enable(sc);
3088 if (error != 0)
3089 goto fail;
3090
3091 error = urtw_write8e(sc, 0x41, 0xf4);
3092 if (error != 0)
3093 goto fail;
3094 error = urtw_write8e(sc, 0x40, 0x00);
3095 if (error != 0)
3096 goto fail;
3097 error = urtw_write8e(sc, 0x42, 0x00);
3098 if (error != 0)
3099 goto fail;
3100 error = urtw_write8e(sc, 0x42, 0x01);
3101 if (error != 0)
3102 goto fail;
3103 error = urtw_write8e(sc, 0x40, 0x0f);
3104 if (error != 0)
3105 goto fail;
3106 error = urtw_write8e(sc, 0x42, 0x00);
3107 if (error != 0)
3108 goto fail;
3109 error = urtw_write8e(sc, 0x42, 0x01);
3110 if (error != 0)
3111 goto fail;
3112
3113 (void) urtw_read8_c(sc, 0xdb, &data, 0);
3114 (void) urtw_write8_c(sc, 0xdb, data | (1 << 2), 0);
3115 (void) urtw_write16_c(sc, 0x72, 0x59fa, 3);
3116 (void) urtw_write16_c(sc, 0x74, 0x59d2, 3);
3117 (void) urtw_write16_c(sc, 0x76, 0x59d2, 3);
3118 (void) urtw_write16_c(sc, 0x78, 0x19fa, 3);
3119 (void) urtw_write16_c(sc, 0x7a, 0x19fa, 3);
3120 (void) urtw_write16_c(sc, 0x7c, 0x00d0, 3);
3121 (void) urtw_write8_c(sc, 0x61, 0, 0);
3122 (void) urtw_write8_c(sc, 0x80, 0x0f, 1);
3123 (void) urtw_write8_c(sc, 0x83, 0x03, 1);
3124 (void) urtw_write8_c(sc, 0xda, 0x10, 0);
3125 (void) urtw_write8_c(sc, 0x4d, 0x08, 2);
3126
3127 (void) urtw_write32_c(sc, URTW_HSSI_PARA, 0x0600321b, 0);
3128 (void) urtw_write16_c(sc, 0xec, 0x0800, 1);
3129 (void) urtw_write8_c(sc, URTW_ACM_CONTROL, 0, 0);
3130
3131 sc->sc_tx_low_queued = 0;
3132 sc->sc_tx_normal_queued = 0;
3133 error = urtw_rx_enable(sc);
3134 if (error != 0)
3135 goto fail;
3136 urtw_tx_enable(sc);
3137
3138 if (error == 0) {
3139 URTW8187_DBG(URTW_DEBUG_ACTIVE, (sc->sc_dev,
3140 CE_CONT, "urtw_8187b_init: done\n"));
3141 sc->sc_flags |= URTW_FLAG_RUNNING;
3142 URTW_UNLOCK(sc);
3143 return (error);
3144 }
3145
3146 fail:
3147 cmn_err(CE_WARN, "urtw_8187b_init failed\n");
3148 URTW_UNLOCK(sc);
3149 urtw_stop(sc);
3150 return (EIO);
3151 }
3152
3153 void
3154 urtw_8225v2_b_config_mac(struct urtw_softc *sc)
3155 {
3156 int i;
3157 int nitems = sizeof (urtw_8187b_regtbl)
3158 / sizeof ((urtw_8187b_regtbl)[0]);
3159
3160 for (i = 0; i < nitems; i++) {
3161 (void) urtw_write8_c(sc, urtw_8187b_regtbl[i].reg,
3162 urtw_8187b_regtbl[i].val, urtw_8187b_regtbl[i].idx);
3163 }
3164
3165 (void) urtw_write16_c(sc, URTW_TID_AC_MAP, 0xfa50, 0);
3166 (void) urtw_write16_c(sc, URTW_INT_MIG, 0, 0);
3167
3168 (void) urtw_write32_c(sc, 0xf0, 0, 1);
3169 (void) urtw_write32_c(sc, 0xf4, 0, 1);
3170 (void) urtw_write8_c(sc, 0xf8, 0, 1);
3171
3172 (void) urtw_write32_c(sc, URTW_RF_TIMING, 0x00004001, 0);
3173 }
3174
3175 void
3176 urtw_8225v2_b_init_rfe(struct urtw_softc *sc)
3177 {
3178 (void) urtw_write16_c(sc, URTW_RF_PINS_OUTPUT, 0x0480, 0);
3179 (void) urtw_write16_c(sc, URTW_RF_PINS_SELECT, 0x2488, 0);
3180 (void) urtw_write16_c(sc, URTW_RF_PINS_ENABLE, 0x1fff, 0);
3181 urtw_delay_ms(100);
3182 }
3183
3184 usbd_status
3185 urtw_8225v2_b_update_chan(struct urtw_softc *sc)
3186 {
3187 struct ieee80211com *ic = &sc->sc_ic;
3188 struct ieee80211_channel *c = ic->ic_curchan;
3189 uint8_t aifs, difs, eifs, sifs, slot;
3190
3191 (void) urtw_write8_c(sc, URTW_SIFS, 0x22, 0);
3192
3193 sifs = 0xa;
3194 if (IEEE80211_IS_CHAN_G(c)) {
3195 slot = 0x9;
3196 difs = 0x1c;
3197 eifs = 0x5b;
3198 } else {
3199 slot = 0x14;
3200 difs = 0x32;
3201 eifs = 0x5b;
3202 }
3203 aifs = (2 * slot) + sifs;
3204
3205 (void) urtw_write8_c(sc, URTW_SLOT, slot, 0);
3206
3207 (void) urtw_write8_c(sc, URTW_AC_VO, aifs, 0);
3208 (void) urtw_write8_c(sc, URTW_AC_VI, aifs, 0);
3209 (void) urtw_write8_c(sc, URTW_AC_BE, aifs, 0);
3210 (void) urtw_write8_c(sc, URTW_AC_BK, aifs, 0);
3211
3212 (void) urtw_write8_c(sc, URTW_DIFS, difs, 0);
3213 (void) urtw_write8_c(sc, URTW_8187B_EIFS, eifs, 0);
3214 return (0);
3215 }
3216
3217 usbd_status
3218 urtw_8225v2_b_rf_init(struct urtw_rf *rf)
3219 {
3220 struct urtw_softc *sc = rf->rf_sc;
3221 int i, nitems;
3222 uint8_t data;
3223 usbd_status error;
3224
3225 /* Set up ACK rate, retry limit, TX AGC, TX antenna. */
3226 (void) urtw_write16_c(sc, URTW_8187B_BRSR, 0x0fff, 0);
3227 (void) urtw_read8_c(sc, URTW_CW_CONF, &data, 0);
3228 (void) urtw_write8_c(sc, URTW_CW_CONF, data |
3229 URTW_CW_CONF_PERPACKET_RETRY, 0);
3230 (void) urtw_read8_c(sc, URTW_TX_AGC_CTL, &data, 0);
3231 (void) urtw_write8_c(sc, URTW_TX_AGC_CTL, data |
3232 URTW_TX_AGC_CTL_PERPACKET_GAIN |
3233 URTW_TX_AGC_CTL_PERPACKET_ANTSEL, 0);
3234
3235 /* Auto rate fallback control. */
3236 (void) urtw_write16_c(sc, URTW_ARFR, 0x0fff, 1); /* 1M ~ 54M */
3237 (void) urtw_read8_c(sc, URTW_RATE_FALLBACK, &data, 0);
3238 (void) urtw_write8_c(sc, URTW_RATE_FALLBACK, data |
3239 URTW_RATE_FALLBACK_ENABLE, 0);
3240
3241 (void) urtw_write16_c(sc, URTW_BEACON_INTERVAL, 0x3ff, 0);
3242 (void) urtw_write16_c(sc, URTW_ATIM_WND, 2, 0);
3243 (void) urtw_write16_c(sc, URTW_FEMR, 0xffff, 1);
3244
3245 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
3246 if (error)
3247 goto fail;
3248 (void) urtw_read8_c(sc, URTW_CONFIG1, &data, 0);
3249 (void) urtw_write8_c(sc, URTW_CONFIG1, (data & 0x3f) | 0x80, 0);
3250 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
3251 if (error)
3252 goto fail;
3253
3254 (void) urtw_write8_c(sc, URTW_WPA_CONFIG, 0, 0);
3255 urtw_8225v2_b_config_mac(sc);
3256 (void) urtw_write16_c(sc, URTW_RFSW_CTRL, 0x569a, 2);
3257
3258 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
3259 if (error)
3260 goto fail;
3261 (void) urtw_read8_c(sc, URTW_CONFIG3, &data, 0);
3262 (void) urtw_write8_c(sc, URTW_CONFIG3,
3263 data | URTW_CONFIG3_ANAPARAM_WRITE, 0);
3264 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
3265 if (error)
3266 goto fail;
3267
3268 urtw_8225v2_b_init_rfe(sc);
3269
3270 nitems = sizeof (urtw_8225v2_b_rf) / sizeof ((urtw_8225v2_b_rf)[0]);
3271 for (i = 0; i < nitems; i++) {
3272 (void) urtw_8225_write_c(sc, urtw_8225v2_b_rf[i].reg,
3273 urtw_8225v2_b_rf[i].val);
3274 }
3275
3276 nitems = sizeof (urtw_8225v2_rxgain) / sizeof ((urtw_8225v2_rxgain)[0]);
3277 for (i = 0; i < nitems; i++) {
3278 (void) urtw_8225_write_c(sc, 0x1, (uint8_t)(i + 1));
3279 (void) urtw_8225_write_c(sc, 0x2, urtw_8225v2_rxgain[i]);
3280 }
3281
3282 (void) urtw_8225_write_c(sc, 0x03, 0x080);
3283 (void) urtw_8225_write_c(sc, 0x05, 0x004);
3284 (void) urtw_8225_write_c(sc, 0x00, 0x0b7);
3285 (void) urtw_8225_write_c(sc, 0x02, 0xc4d);
3286 urtw_delay_ms(10);
3287 (void) urtw_8225_write_c(sc, 0x02, 0x44d);
3288 urtw_delay_ms(10);
3289 (void) urtw_8225_write_c(sc, 0x00, 0x2bf);
3290 urtw_delay_ms(10);
3291
3292 (void) urtw_write8_c(sc, URTW_TX_GAIN_CCK, 0x03, 0);
3293 (void) urtw_write8_c(sc, URTW_TX_GAIN_OFDM, 0x07, 0);
3294 (void) urtw_write8_c(sc, URTW_TX_ANTENNA, 0x03, 0);
3295
3296 (void) urtw_8187_write_phy_ofdm_c(sc, 0x80, 0x12);
3297 nitems = sizeof (urtw_8225v2_agc) / sizeof ((urtw_8225v2_agc)[0]);
3298 for (i = 0; i < nitems; i++) {
3299 (void) urtw_8187_write_phy_ofdm_c(sc, 0x0f, urtw_8225v2_agc[i]);
3300 (void) urtw_8187_write_phy_ofdm_c(sc, 0x0e, (uint8_t)i + 0x80);
3301 (void) urtw_8187_write_phy_ofdm_c(sc, 0x0e, 0);
3302 }
3303 (void) urtw_8187_write_phy_ofdm_c(sc, 0x80, 0x10);
3304
3305 nitems = sizeof (urtw_8225v2_ofdm) / sizeof ((urtw_8225v2_ofdm)[0]);
3306 for (i = 0; i < nitems; i++) {
3307 (void) urtw_8187_write_phy_ofdm_c(sc, i, urtw_8225v2_ofdm[i]);
3308 }
3309 (void) urtw_8225v2_b_update_chan(sc);
3310
3311 (void) urtw_8187_write_phy_ofdm_c(sc, 0x97, 0x46);
3312 (void) urtw_8187_write_phy_ofdm_c(sc, 0xa4, 0xb6);
3313 (void) urtw_8187_write_phy_ofdm_c(sc, 0x85, 0xfc);
3314 (void) urtw_8187_write_phy_cck_c(sc, 0xc1, 0x88);
3315
3316 error = urtw_8225v2_b_rf_set_chan(rf,
3317 ieee80211_chan2ieee(&sc->sc_ic, sc->sc_ic.ic_curchan));
3318 fail:
3319 return (error);
3320 }
3321
3322 static usbd_status
3323 urtw_8225v2_b_rf_set_chan(struct urtw_rf *rf, int chan)
3324 {
3325 struct urtw_softc *sc = rf->rf_sc;
3326 int error = 0;
3327
3328 urtw_8225v2_b_set_txpwrlvl(sc, chan);
3329 error = urtw_8225_write_c(sc, 0x7, urtw_8225_channel[chan]);
3330 if (error)
3331 goto fail;
3332 /*
3333 * Delay removed from 8185 to 8187.
3334 * usbd_delay_ms(sc->sc_udev, 10);
3335 */
3336
3337 error = urtw_write16_c(sc, URTW_AC_VO, 0x5114, 0);
3338 if (error)
3339 goto fail;
3340 error = urtw_write16_c(sc, URTW_AC_VI, 0x5114, 0);
3341 if (error)
3342 goto fail;
3343 error = urtw_write16_c(sc, URTW_AC_BE, 0x5114, 0);
3344 if (error)
3345 goto fail;
3346 error = urtw_write16_c(sc, URTW_AC_BK, 0x5114, 0);
3347 fail:
3348 return (error);
3349 }
3350
3351 void
3352 urtw_8225v2_b_set_txpwrlvl(struct urtw_softc *sc, int chan)
3353 {
3354 int i;
3355 uint8_t *cck_pwrtable;
3356 uint8_t cck_pwrlvl_min, cck_pwrlvl_max, ofdm_pwrlvl_min,
3357 ofdm_pwrlvl_max;
3358 int8_t cck_pwrlvl = sc->sc_txpwr_cck[chan] & 0xff;
3359 int8_t ofdm_pwrlvl = sc->sc_txpwr_ofdm[chan] & 0xff;
3360
3361 if (sc->sc_hwrev & URTW_HWREV_8187B_B) {
3362 cck_pwrlvl_min = 0;
3363 cck_pwrlvl_max = 15;
3364 ofdm_pwrlvl_min = 2;
3365 ofdm_pwrlvl_max = 17;
3366 } else {
3367 cck_pwrlvl_min = 7;
3368 cck_pwrlvl_max = 22;
3369 ofdm_pwrlvl_min = 10;
3370 ofdm_pwrlvl_max = 25;
3371 }
3372
3373 /* CCK power setting */
3374 cck_pwrlvl = (cck_pwrlvl > (cck_pwrlvl_max - cck_pwrlvl_min)) ?
3375 cck_pwrlvl_max : (cck_pwrlvl + cck_pwrlvl_min);
3376
3377 cck_pwrlvl += sc->sc_txpwr_cck_base;
3378 cck_pwrlvl = (cck_pwrlvl > 35) ? 35 : cck_pwrlvl;
3379 cck_pwrlvl = (cck_pwrlvl < 0) ? 0 : cck_pwrlvl;
3380
3381 cck_pwrtable = (chan == 14) ? urtw_8225v2_txpwr_cck_ch14 :
3382 urtw_8225v2_txpwr_cck;
3383
3384 if (sc->sc_hwrev & URTW_HWREV_8187B_B) {
3385 if (cck_pwrlvl > 7 && cck_pwrlvl <= 11)
3386 cck_pwrtable += 8;
3387 if (cck_pwrlvl > 11)
3388 cck_pwrtable += 16;
3389 } else {
3390 if (cck_pwrlvl > 5 && cck_pwrlvl <= 11)
3391 cck_pwrtable += 8;
3392 if (cck_pwrlvl > 12 && cck_pwrlvl <= 17)
3393 cck_pwrtable += 16;
3394 if (cck_pwrlvl > 17)
3395 cck_pwrtable += 24;
3396 }
3397
3398 for (i = 0; i < 8; i++) {
3399 (void) urtw_8187_write_phy_cck_c(sc, 0x44 + i, cck_pwrtable[i]);
3400 }
3401
3402 (void) urtw_write8_c(sc, URTW_TX_GAIN_CCK,
3403 urtw_8225v2_tx_gain_cck_ofdm[cck_pwrlvl] << 1, 0);
3404 /*
3405 * Delay removed from 8185 to 8187.
3406 * usbd_delay_ms(sc->sc_udev, 1);
3407 */
3408
3409 /* OFDM power setting */
3410 ofdm_pwrlvl = (ofdm_pwrlvl > (ofdm_pwrlvl_max - ofdm_pwrlvl_min)) ?
3411 ofdm_pwrlvl_max : ofdm_pwrlvl + ofdm_pwrlvl_min;
3412
3413 ofdm_pwrlvl += sc->sc_txpwr_ofdm_base;
3414 ofdm_pwrlvl = (ofdm_pwrlvl > 35) ? 35 : ofdm_pwrlvl;
3415 ofdm_pwrlvl = (ofdm_pwrlvl < 0) ? 0 : ofdm_pwrlvl;
3416
3417 (void) urtw_write8_c(sc, URTW_TX_GAIN_OFDM,
3418 urtw_8225v2_tx_gain_cck_ofdm[ofdm_pwrlvl] << 1, 0);
3419
3420 if (sc->sc_hwrev & URTW_HWREV_8187B_B) {
3421 if (ofdm_pwrlvl <= 11) {
3422 (void) urtw_8187_write_phy_ofdm_c(sc, 0x87, 0x60);
3423 (void) urtw_8187_write_phy_ofdm_c(sc, 0x89, 0x60);
3424 } else {
3425 (void) urtw_8187_write_phy_ofdm_c(sc, 0x87, 0x5c);
3426 (void) urtw_8187_write_phy_ofdm_c(sc, 0x89, 0x5c);
3427 }
3428 } else {
3429 if (ofdm_pwrlvl <= 11) {
3430 (void) urtw_8187_write_phy_ofdm_c(sc, 0x87, 0x5c);
3431 (void) urtw_8187_write_phy_ofdm_c(sc, 0x89, 0x5c);
3432 } else if (ofdm_pwrlvl <= 17) {
3433 (void) urtw_8187_write_phy_ofdm_c(sc, 0x87, 0x54);
3434 (void) urtw_8187_write_phy_ofdm_c(sc, 0x89, 0x54);
3435 } else {
3436 (void) urtw_8187_write_phy_ofdm_c(sc, 0x87, 0x50);
3437 (void) urtw_8187_write_phy_ofdm_c(sc, 0x89, 0x50);
3438 }
3439 }
3440
3441 /*
3442 * Delay removed from 8185 to 8187.
3443 * usbd_delay_ms(sc->sc_udev, 1);
3444 */
3445 }
3446
3447
3448 static int
3449 urtw_send(ieee80211com_t *ic, mblk_t *mp, uint8_t type)
3450 {
3451 struct urtw_softc *sc = (struct urtw_softc *)ic;
3452 struct ieee80211_frame *wh;
3453 struct ieee80211_key *k;
3454 struct ieee80211_node *ni = NULL;
3455 uint8_t *buf;
3456 mblk_t *m = 0, *m0, *mtx;
3457 int off, mblen, xferlen, err = 0, priority = 0;
3458
3459 mutex_enter(&sc->tx_lock);
3460 priority = (type == IEEE80211_FC0_TYPE_DATA) ?
3461 LOW_PRIORITY_PIPE: NORMAL_PRIORITY_PIPE;
3462
3463 if (URTW_IS_SUSPENDING(sc)) {
3464 err = 0;
3465 goto failed;
3466 }
3467
3468 if (((priority)? sc->sc_tx_normal_queued : sc->sc_tx_low_queued) >=
3469 URTW_TX_DATA_LIST_COUNT) {
3470 URTW8187_DBG(URTW_DEBUG_XMIT, (sc->sc_dev, CE_CONT,
3471 "urtw_send(): no TX buffer!\n"));
3472 sc->sc_tx_nobuf++;
3473 err = ENOMEM;
3474 goto failed;
3475 }
3476
3477 m = allocb(URTW_TXBUF_SIZE, BPRI_MED);
3478 if (m == NULL) {
3479 cmn_err(CE_WARN, "urtw_send(): can't alloc mblk.\n");
3480 err = ENOMEM;
3481 goto failed;
3482 }
3483
3484 for (off = 0, m0 = mp; m0 != NULL; m0 = m0->b_cont) {
3485 mblen = (uintptr_t)m0->b_wptr - (uintptr_t)m0->b_rptr;
3486 (void) bcopy(m0->b_rptr, m->b_rptr + off, mblen);
3487 off += mblen;
3488 }
3489 m->b_wptr += off;
3490
3491 wh = (struct ieee80211_frame *)m->b_rptr;
3492
3493 ni = ieee80211_find_txnode(ic, wh->i_addr1);
3494 if (ni == NULL) {
3495 err = ENXIO;
3496 ic->ic_stats.is_tx_failed++;
3497 goto failed;
3498 }
3499
3500 if ((type & IEEE80211_FC0_TYPE_MASK) ==
3501 IEEE80211_FC0_TYPE_DATA) {
3502 (void) ieee80211_encap(ic, m, ni);
3503 }
3504
3505 if (wh->i_fc[1] & IEEE80211_FC1_WEP) {
3506 k = ieee80211_crypto_encap(ic, m);
3507 if (k == NULL) {
3508 ic->ic_stats.is_tx_failed++;
3509 err = ENXIO;
3510 goto failed;
3511 }
3512 /* packet header may have moved, reset our local pointer */
3513 wh = (struct ieee80211_frame *)m->b_rptr;
3514 }
3515
3516 if (sc->sc_hwrev & URTW_HWREV_8187)
3517 xferlen = MBLKL(m) + 4 * 3;
3518 else
3519 xferlen = MBLKL(m) + 4 * 8;
3520
3521 if ((0 == xferlen % 64) || (0 == xferlen % 512))
3522 xferlen += 1;
3523
3524 mtx = allocb(xferlen, BPRI_MED);
3525 buf = mtx->b_rptr;
3526
3527 bzero(buf, xferlen);
3528 buf[0] = MBLKL(m) & 0xff;
3529 buf[1] = (MBLKL(m) & 0x0f00) >> 8;
3530 buf[1] |= (1 << 7);
3531
3532 /* XXX sc_preamble_mode is always 2. */
3533 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG)
3534 buf[2] |= (1 << 1);
3535 /* RTS rate - 10 means we use a basic rate. */
3536 buf[2] |= (urtw_rate2rtl(2) << 3);
3537 /*
3538 * XXX currently TX rate control depends on the rate value of
3539 * RX descriptor because I don't know how to we can control TX rate
3540 * in more smart way. Please fix me you find a thing.
3541 */
3542 if ((type & IEEE80211_FC0_TYPE_MASK) == IEEE80211_FC0_TYPE_DATA) {
3543 buf[3] = urtw_rate2rtl(MAX(2, urtw_get_rate(ic)));
3544 } else
3545 buf[3] = 0;
3546
3547 if (sc->sc_hwrev & URTW_HWREV_8187) {
3548 buf[8] = 3; /* CW minimum */
3549 buf[8] |= (7 << 4); /* CW maximum */
3550 buf[9] |= 11; /* retry limitation */
3551 bcopy(m->b_rptr, &buf[12], MBLKL(m));
3552 } else {
3553 buf[21] |= 11; /* retry limitation */
3554 bcopy(m->b_rptr, &buf[32], MBLKL(m));
3555 }
3556
3557 (void) urtw_led_ctl(sc, URTW_LED_CTL_TX);
3558 mtx->b_wptr = mtx->b_rptr + xferlen;
3559
3560 URTW8187_DBG(URTW_DEBUG_XMIT, (sc->sc_dev, CE_CONT,
3561 "sending frame len=%u rate=%u xfer len=%u\n",
3562 MBLKL(m), buf[3], xferlen));
3563
3564 err = urtw_tx_start(sc, mtx, priority);
3565 if (!err) {
3566 ic->ic_stats.is_tx_frags++;
3567 ic->ic_stats.is_tx_bytes += MBLKL(m);
3568 } else {
3569 ic->ic_stats.is_tx_failed++;
3570 }
3571
3572 failed:
3573 if (ni != NULL)
3574 ieee80211_free_node(ni);
3575
3576 if ((mp) &&
3577 ((type & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_DATA ||
3578 err == DDI_SUCCESS)) {
3579 freemsg(mp);
3580 }
3581 if (m) freemsg(m);
3582
3583 if (((type & IEEE80211_FC0_TYPE_MASK) == IEEE80211_FC0_TYPE_DATA) &&
3584 (err != 0)) {
3585 sc->sc_need_sched = 1;
3586 }
3587 mutex_exit(&sc->tx_lock);
3588 return (err);
3589 }
3590
3591 static void
3592 urtw_next_scan(void *arg)
3593 {
3594 ieee80211com_t *ic = arg;
3595 struct urtw_softc *sc = (struct urtw_softc *)arg;
3596
3597 if (URTW_IS_NOT_RUNNING(sc)) {
3598 sc->sc_scan_id = 0;
3599 return;
3600 }
3601
3602 if (ic->ic_state == IEEE80211_S_SCAN) {
3603 (void) ieee80211_next_scan(ic);
3604 }
3605 sc->sc_scan_id = 0;
3606 }
3607
3608 static void
3609 urtw_led_launch(void *arg)
3610 {
3611 struct urtw_softc *sc = arg;
3612 ieee80211com_t *ic = &sc->sc_ic;
3613 int error = 0;
3614
3615 URTW_LEDLOCK(sc);
3616 if ((sc->sc_strategy != URTW_SW_LED_MODE0) ||
3617 URTW_IS_NOT_RUNNING(sc) ||
3618 URTW_IS_SUSPENDING(sc)) {
3619 URTW8187_DBG(URTW_DEBUG_LED, (sc->sc_dev, CE_CONT,
3620 "failed process LED strategy 0x%x, run?%d",
3621 sc->sc_strategy,
3622 sc->sc_flags));
3623 sc->sc_led_ch = 0;
3624 sc->sc_gpio_ledinprogress = 0;
3625 URTW_LEDUNLOCK(sc);
3626 return;
3627 }
3628 error = urtw_led_blink(sc);
3629 if (error) {
3630 sc->sc_led_ch = timeout(urtw_led_launch, (void *)sc,
3631 drv_usectohz((ic->ic_state == IEEE80211_S_RUN) ?
3632 URTW_LED_LINKON_BLINK: URTW_LED_LINKOFF_BLINK));
3633 URTW8187_DBG(URTW_DEBUG_LED, (sc->sc_dev, CE_CONT,
3634 "try again led launch"));
3635 } else {
3636 sc->sc_led_ch = 0;
3637 URTW8187_DBG(URTW_DEBUG_LED, (sc->sc_dev, CE_CONT,
3638 "exit led launch"));
3639 }
3640 URTW_LEDUNLOCK(sc);
3641 }
3642
3643 static int
3644 urtw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg)
3645 {
3646 struct urtw_softc *sc = (struct urtw_softc *)ic;
3647 struct ieee80211_node *ni;
3648 int error = 0;
3649
3650 if (sc->sc_scan_id != 0) {
3651 (void) untimeout(sc->sc_scan_id);
3652 sc->sc_scan_id = 0;
3653 }
3654 URTW_LOCK(sc);
3655 switch (nstate) {
3656 case IEEE80211_S_INIT:
3657 URTW8187_DBG(URTW_DEBUG_STATE,
3658 (sc->sc_dev, CE_CONT, "-> IEEE80211_S_INIT...arg(%d)\n",
3659 arg));
3660 if (sc->sc_flags & URTW_FLAG_HP)
3661 break;
3662 (void) urtw_update_msr(sc, nstate);
3663 (void) urtw_led_off(sc, URTW_LED_GPIO);
3664 break;
3665
3666 case IEEE80211_S_SCAN:
3667 URTW8187_DBG(URTW_DEBUG_STATE,
3668 (sc->sc_dev, CE_CONT,
3669 "-> IEEE80211_S_SCAN...arg(%d)...[%d]\n",
3670 arg, ieee80211_chan2ieee(ic, ic->ic_curchan)));
3671 error = urtw_set_channel(sc);
3672 if (error) {
3673 URTW8187_DBG(URTW_DEBUG_STATE,
3674 (sc->sc_dev, CE_CONT, "scan setchan failed"));
3675 break;
3676 }
3677 sc->sc_scan_id = timeout(urtw_next_scan, (void *)sc,
3678 drv_usectohz(sc->dwelltime * 1000));
3679 break;
3680
3681 case IEEE80211_S_AUTH:
3682 URTW8187_DBG(URTW_DEBUG_STATE, (sc->sc_dev, CE_CONT,
3683 "-> IEEE80211_S_AUTH ...arg(%d), chan (%d)\n", arg,
3684 ieee80211_chan2ieee(ic, ic->ic_curchan)));
3685 error = urtw_set_channel(sc);
3686 if (error) {
3687 URTW8187_DBG(URTW_DEBUG_STATE,
3688 (sc->sc_dev, CE_CONT, "auth setchan failed"));
3689 }
3690 break;
3691
3692 case IEEE80211_S_ASSOC:
3693 URTW8187_DBG(URTW_DEBUG_STATE, (sc->sc_dev, CE_CONT,
3694 "-> IEEE80211_S_ASSOC ...arg(%d), chan (%d)\n", arg,
3695 ieee80211_chan2ieee(ic, ic->ic_curchan)));
3696 error = urtw_set_channel(sc);
3697 if (error) {
3698 URTW8187_DBG(URTW_DEBUG_STATE,
3699 (sc->sc_dev, CE_CONT, "assoc setchan failed"));
3700 }
3701 break;
3702
3703 case IEEE80211_S_RUN:
3704 URTW8187_DBG(URTW_DEBUG_STATE,
3705 (sc->sc_dev, CE_CONT,
3706 "-> IEEE80211_S_RUN ...arg(%d), chan (%d)\n",
3707 arg, ieee80211_chan2ieee(ic, ic->ic_curchan)));
3708 error = urtw_set_channel(sc);
3709 if (error) {
3710 URTW8187_DBG(URTW_DEBUG_STATE,
3711 (sc->sc_dev, CE_CONT, "run setchan failed"));
3712 goto fail;
3713 }
3714 ni = ic->ic_bss;
3715 /* setting bssid. */
3716 (void) urtw_write32_c(sc, URTW_BSSID,
3717 ((uint32_t *)(uintptr_t)ni->in_bssid)[0], 0);
3718 (void) urtw_write16_c(sc, URTW_BSSID + 4,
3719 ((uint16_t *)(uintptr_t)ni->in_bssid)[2], 0);
3720 (void) urtw_update_msr(sc, nstate);
3721
3722 ni->in_txrate = ni->in_rates.ir_nrates - 1;
3723 break;
3724 }
3725 fail:
3726 URTW_UNLOCK(sc);
3727
3728 if (error) {
3729 URTW8187_DBG(URTW_DEBUG_STATE, (sc->sc_dev, CE_CONT,
3730 "-> newstate error...arg(%d)\n", error));
3731 return (EIO);
3732 }
3733 error = sc->sc_newstate(ic, nstate, arg);
3734 return (error);
3735 }
3736
3737 static void
3738 urtw_close_pipes(struct urtw_softc *sc)
3739 {
3740 usb_flags_t flags = USB_FLAGS_SLEEP;
3741
3742 if (sc->sc_rxpipe != NULL) {
3743 usb_pipe_reset(sc->sc_dev,
3744 sc->sc_rxpipe, flags, NULL, 0);
3745 usb_pipe_close(sc->sc_dev,
3746 sc->sc_rxpipe, flags, NULL, 0);
3747 sc->sc_rxpipe = NULL;
3748 }
3749
3750 if (sc->sc_txpipe_low != NULL) {
3751 usb_pipe_reset(sc->sc_dev,
3752 sc->sc_txpipe_low, flags, NULL, 0);
3753 usb_pipe_close(sc->sc_dev,
3754 sc->sc_txpipe_low, flags, NULL, 0);
3755 sc->sc_txpipe_low = NULL;
3756 }
3757
3758 if (sc->sc_txpipe_normal != NULL) {
3759 usb_pipe_reset(sc->sc_dev,
3760 sc->sc_txpipe_normal, flags, NULL, 0);
3761 usb_pipe_close(sc->sc_dev,
3762 sc->sc_txpipe_normal, flags, NULL, 0);
3763 sc->sc_txpipe_normal = NULL;
3764 }
3765 }
3766
3767 static int
3768 urtw_open_pipes(struct urtw_softc *sc)
3769 {
3770 usb_ep_data_t *ep_node;
3771 usb_pipe_policy_t policy;
3772 int err;
3773 uint_t skip = 0;
3774
3775 if (sc->sc_rxpipe || sc->sc_txpipe_low || sc->sc_txpipe_normal)
3776 return (USB_SUCCESS);
3777
3778 if ((sc->sc_hwrev & URTW_HWREV_8187) == 0) {
3779 skip = 2;
3780 }
3781 ep_node = usb_lookup_ep_data(sc->sc_dev, sc->sc_udev, 0, 0,
3782 LOW_PRIORITY_PIPE + skip, USB_EP_ATTR_BULK, USB_EP_DIR_OUT);
3783
3784 bzero(&policy, sizeof (usb_pipe_policy_t));
3785 policy.pp_max_async_reqs = URTW_TX_DATA_LIST_COUNT;
3786
3787 if ((err = usb_pipe_open(sc->sc_dev,
3788 &ep_node->ep_descr, &policy, USB_FLAGS_SLEEP,
3789 &sc->sc_txpipe_low)) != USB_SUCCESS) {
3790 URTW8187_DBG(URTW_DEBUG_ACTIVE, (sc->sc_dev, CE_CONT,
3791 "urtw_open_pipes(): %x low priority pipe open failed\n",
3792 err));
3793 goto fail;
3794 }
3795
3796 ep_node = usb_lookup_ep_data(sc->sc_dev, sc->sc_udev, 0, 0,
3797 NORMAL_PRIORITY_PIPE + skip, USB_EP_ATTR_BULK, USB_EP_DIR_OUT);
3798
3799 bzero(&policy, sizeof (usb_pipe_policy_t));
3800 policy.pp_max_async_reqs = URTW_TX_DATA_LIST_COUNT;
3801
3802 if ((err = usb_pipe_open(sc->sc_dev,
3803 &ep_node->ep_descr, &policy, USB_FLAGS_SLEEP,
3804 &sc->sc_txpipe_normal)) != USB_SUCCESS) {
3805 URTW8187_DBG(URTW_DEBUG_ACTIVE, (sc->sc_dev, CE_CONT,
3806 "urtw_open_pipes(): %x failed to open high tx pipe\n",
3807 err));
3808 goto fail;
3809 }
3810
3811 ep_node = usb_lookup_ep_data(sc->sc_dev, sc->sc_udev, 0, 0, 0,
3812 USB_EP_ATTR_BULK, USB_EP_DIR_IN);
3813
3814 bzero(&policy, sizeof (usb_pipe_policy_t));
3815 policy.pp_max_async_reqs = URTW_RX_DATA_LIST_COUNT;
3816
3817 if ((err = usb_pipe_open(sc->sc_dev,
3818 &ep_node->ep_descr, &policy, USB_FLAGS_SLEEP,
3819 &sc->sc_rxpipe)) != USB_SUCCESS) {
3820 URTW8187_DBG(URTW_DEBUG_ACTIVE, (sc->sc_dev, CE_CONT,
3821 "urtw_open_pipes(): %x failed to open rx pipe\n", err));
3822 goto fail;
3823 }
3824
3825 return (USB_SUCCESS);
3826
3827 fail:
3828 urtw_close_pipes(sc);
3829 return (USB_FAILURE);
3830 }
3831
3832 static int
3833 urtw_tx_start(struct urtw_softc *sc, mblk_t *mp, int priority)
3834 {
3835 usb_bulk_req_t *req;
3836 int err;
3837
3838 req = usb_alloc_bulk_req(sc->sc_dev, 0, USB_FLAGS_SLEEP);
3839 if (req == NULL) {
3840 URTW8187_DBG(URTW_DEBUG_TX_PROC, (sc->sc_dev, CE_CONT,
3841 "urtw_tx_start(): failed to allocate req"));
3842 freemsg(mp);
3843 return (-1);
3844 }
3845
3846 req->bulk_len = MBLKL(mp);
3847 req->bulk_data = mp;
3848 req->bulk_client_private = (usb_opaque_t)sc;
3849 req->bulk_timeout = URTW_TX_TIMEOUT;
3850 req->bulk_attributes = USB_ATTRS_AUTOCLEARING;
3851 req->bulk_cb = (priority)?urtw_txeof_normal : urtw_txeof_low;
3852 req->bulk_exc_cb = (priority)?urtw_txeof_normal: urtw_txeof_low;
3853 req->bulk_completion_reason = 0;
3854 req->bulk_cb_flags = 0;
3855
3856 if ((err = usb_pipe_bulk_xfer(
3857 (priority)?sc->sc_txpipe_normal:sc->sc_txpipe_low, req, 0))
3858 != USB_SUCCESS) {
3859 sc->sc_ic.ic_stats.is_tx_failed++;
3860 URTW8187_DBG(URTW_DEBUG_TX_PROC, (sc->sc_dev, CE_CONT,
3861 "urtw_tx_start: failed to do tx xfer, %d", err));
3862 usb_free_bulk_req(req);
3863 return (EIO);
3864 }
3865
3866 if (priority) {
3867 sc->sc_tx_normal_queued++;
3868 } else {
3869 sc->sc_tx_low_queued++;
3870 }
3871
3872 return (0);
3873 }
3874
3875 static int
3876 urtw_rx_start(struct urtw_softc *sc)
3877 {
3878 usb_bulk_req_t *req;
3879 int err;
3880
3881 req = usb_alloc_bulk_req(sc->sc_dev, URTW_RXBUF_SIZE, USB_FLAGS_SLEEP);
3882 if (req == NULL) {
3883 URTW8187_DBG(URTW_DEBUG_RECV, (sc->sc_dev, CE_CONT,
3884 "urtw_rx_start(): failed to allocate req"));
3885 return (-1);
3886 }
3887
3888 req->bulk_len = URTW_RXBUF_SIZE;
3889 req->bulk_client_private = (usb_opaque_t)sc;
3890 req->bulk_timeout = 0;
3891 req->bulk_attributes = USB_ATTRS_SHORT_XFER_OK |
3892 USB_ATTRS_AUTOCLEARING;
3893 req->bulk_cb = urtw_rxeof;
3894 req->bulk_exc_cb = urtw_rxeof;
3895 req->bulk_completion_reason = 0;
3896 req->bulk_cb_flags = 0;
3897
3898 err = usb_pipe_bulk_xfer(sc->sc_rxpipe, req, 0);
3899
3900 if (err != USB_SUCCESS) {
3901 URTW8187_DBG(URTW_DEBUG_RECV, (sc->sc_dev, CE_CONT,
3902 "urtw_rx_start: failed to do rx xfer, %d", err));
3903 usb_free_bulk_req(req);
3904 return (-1);
3905 }
3906
3907 mutex_enter(&sc->rx_lock);
3908 sc->rx_queued++;
3909 mutex_exit(&sc->rx_lock);
3910
3911 return (0);
3912 }
3913
3914 static int
3915 urtw_disconnect(dev_info_t *devinfo)
3916 {
3917 struct urtw_softc *sc;
3918
3919 sc = ddi_get_soft_state(urtw_soft_state_p, ddi_get_instance(devinfo));
3920 URTW8187_DBG(URTW_DEBUG_HOTPLUG,
3921 (sc->sc_dev, CE_CONT, "urtw_offline()\n"));
3922
3923 if (URTW_IS_RUNNING(sc)) {
3924 urtw_stop(sc);
3925 URTW_LOCK(sc);
3926 sc->sc_flags |= URTW_FLAG_PLUGIN_ONLINE;
3927 URTW_UNLOCK(sc);
3928 }
3929 sc->sc_flags |= URTW_FLAG_HP;
3930 ieee80211_new_state(&sc->sc_ic, IEEE80211_S_INIT, -1);
3931 ieee80211_stop_watchdog(&sc->sc_ic);
3932 return (DDI_SUCCESS);
3933 }
3934
3935 static int
3936 urtw_reconnect(dev_info_t *devinfo)
3937 {
3938 struct urtw_softc *sc;
3939 int error = 0;
3940 sc = ddi_get_soft_state(urtw_soft_state_p, ddi_get_instance(devinfo));
3941 if (usb_check_same_device(sc->sc_dev, NULL, USB_LOG_L2, -1,
3942 USB_CHK_ALL, NULL) != USB_SUCCESS)
3943 return (DDI_FAILURE);
3944 URTW8187_DBG(URTW_DEBUG_HOTPLUG, (sc->sc_dev, CE_CONT,
3945 "urtw_online()\n"));
3946 sc->sc_flags &= ~URTW_FLAG_HP;
3947 if (URTW_IS_PLUGIN_ONLINE(sc)) {
3948 error = sc->urtw_init(sc);
3949 if (!error) {
3950 URTW_LOCK(sc);
3951 sc->sc_flags &= ~URTW_FLAG_PLUGIN_ONLINE;
3952 URTW_UNLOCK(sc);
3953 }
3954 }
3955 return (error? DDI_FAILURE: DDI_SUCCESS);
3956 }
3957
3958 static mblk_t *
3959 urtw_m_tx(void *arg, mblk_t *mp)
3960 {
3961 struct urtw_softc *sc = (struct urtw_softc *)arg;
3962 struct ieee80211com *ic = &sc->sc_ic;
3963 mblk_t *next;
3964
3965 if ((ic->ic_state != IEEE80211_S_RUN) ||
3966 URTW_IS_SUSPENDING(sc)) {
3967 freemsgchain(mp);
3968 return (NULL);
3969 }
3970
3971 while (mp != NULL) {
3972 next = mp->b_next;
3973 mp->b_next = NULL;
3974 if (urtw_send(ic, mp, IEEE80211_FC0_TYPE_DATA) != DDI_SUCCESS) {
3975 mp->b_next = next;
3976 break;
3977 }
3978 mp = next;
3979 }
3980 return (mp);
3981 }
3982
3983 static int
3984 urtw_m_start(void *arg)
3985 {
3986 struct urtw_softc *sc = (struct urtw_softc *)arg;
3987 int error = 0;
3988
3989 URTW8187_DBG(URTW_DEBUG_ACTIVE,
3990 (sc->sc_dev, CE_CONT, "urtw_m_start\n"));
3991 error = sc->urtw_init(sc);
3992 return (error);
3993 }
3994
3995 static void
3996 urtw_m_stop(void *arg)
3997 {
3998 struct urtw_softc *sc = (struct urtw_softc *)arg;
3999
4000 URTW8187_DBG(URTW_DEBUG_ACTIVE, (sc->sc_dev, CE_CONT,
4001 "urtw_m_stop()\n"));
4002 ieee80211_new_state(&sc->sc_ic, IEEE80211_S_INIT, -1);
4003 ieee80211_stop_watchdog(&sc->sc_ic);
4004 (void) urtw_stop(sc);
4005 }
4006
4007 /*ARGSUSED*/
4008 static int
4009 urtw_m_unicst(void *arg, const uint8_t *macaddr)
4010 {
4011 return (ENOTSUP);
4012 }
4013
4014 /*ARGSUSED*/
4015 static int
4016 urtw_m_multicst(void *arg, boolean_t add, const uint8_t *macaddr)
4017 {
4018 return (ENOTSUP);
4019 }
4020
4021 /*ARGSUSED*/
4022 static int
4023 urtw_m_promisc(void *arg, boolean_t on)
4024 {
4025 return (0);
4026 }
4027
4028 static int
4029 urtw_m_getprop(void *arg, const char *pr_name, mac_prop_id_t wldp_pr_num,
4030 uint_t wldp_length, void *wldp_buf)
4031 {
4032 struct urtw_softc *sc = (struct urtw_softc *)arg;
4033 int err = 0;
4034
4035 err = ieee80211_getprop(&sc->sc_ic, pr_name, wldp_pr_num,
4036 wldp_length, wldp_buf);
4037 return (err);
4038 }
4039
4040 static void
4041 urtw_m_propinfo(void *arg, const char *pr_name, mac_prop_id_t wldp_pr_num,
4042 mac_prop_info_handle_t mph)
4043 {
4044 struct urtw_softc *sc = (struct urtw_softc *)arg;
4045
4046 ieee80211_propinfo(&sc->sc_ic, pr_name, wldp_pr_num, mph);
4047 }
4048
4049 static int
4050 urtw_m_setprop(void *arg, const char *pr_name, mac_prop_id_t wldp_pr_num,
4051 uint_t wldp_length, const void *wldp_buf)
4052 {
4053 struct urtw_softc *sc = (struct urtw_softc *)arg;
4054 struct ieee80211com *ic = &sc->sc_ic;
4055 int err;
4056
4057 err = ieee80211_setprop(ic, pr_name, wldp_pr_num,
4058 wldp_length, wldp_buf);
4059 URTW_LOCK(sc);
4060 if (err == ENETRESET) {
4061 if (URTW_IS_RUNNING(sc) && ic->ic_des_esslen) {
4062 URTW_UNLOCK(sc);
4063 err = sc->urtw_init(sc);
4064 if (err) {
4065 URTW8187_DBG(URTW_DEBUG_ACTIVE,
4066 (sc->sc_dev, CE_CONT,
4067 "urtw: setprop failed\n"));
4068 return (err);
4069 }
4070 (void) ieee80211_new_state(ic, IEEE80211_S_SCAN, -1);
4071 URTW_LOCK(sc);
4072 }
4073 err = 0;
4074 }
4075 URTW_UNLOCK(sc);
4076 return (err);
4077 }
4078
4079 static void
4080 urtw_m_ioctl(void* arg, queue_t *wq, mblk_t *mp)
4081 {
4082 struct urtw_softc *sc = (struct urtw_softc *)arg;
4083 struct ieee80211com *ic = &sc->sc_ic;
4084 int err;
4085
4086 err = ieee80211_ioctl(ic, wq, mp);
4087 URTW_LOCK(sc);
4088 if (err == ENETRESET) {
4089 if (URTW_IS_RUNNING(sc) && ic->ic_des_esslen) {
4090 URTW_UNLOCK(sc);
4091 err = sc->urtw_init(sc);
4092 if (err) {
4093 URTW8187_DBG(URTW_DEBUG_ACTIVE,
4094 (sc->sc_dev,
4095 CE_CONT, "urtw: dev init failed\n"));
4096 return;
4097 }
4098 (void) ieee80211_new_state(ic, IEEE80211_S_SCAN, -1);
4099 URTW_LOCK(sc);
4100 }
4101 }
4102 URTW_UNLOCK(sc);
4103 }
4104
4105 static int
4106 urtw_m_stat(void *arg, uint_t stat, uint64_t *val)
4107 {
4108 struct urtw_softc *sc = (struct urtw_softc *)arg;
4109 ieee80211com_t *ic = &sc->sc_ic;
4110 ieee80211_node_t *ni = 0;
4111 struct ieee80211_rateset *rs = 0;
4112
4113 URTW_LOCK(sc);
4114 switch (stat) {
4115 case MAC_STAT_IFSPEED:
4116 ni = ic->ic_bss;
4117 rs = &ni->in_rates;
4118 *val = ((ic->ic_fixed_rate == IEEE80211_FIXED_RATE_NONE) ?
4119 (rs->ir_rates[ni->in_txrate] & IEEE80211_RATE_VAL)
4120 : ic->ic_fixed_rate) / 2 * 1000000;
4121 break;
4122 case MAC_STAT_NOXMTBUF:
4123 *val = sc->sc_tx_nobuf;
4124 break;
4125 case MAC_STAT_NORCVBUF:
4126 *val = sc->sc_rx_nobuf;
4127 break;
4128 case MAC_STAT_IERRORS:
4129 *val = sc->sc_rx_err;
4130 break;
4131 case MAC_STAT_RBYTES:
4132 *val = ic->ic_stats.is_rx_bytes;
4133 break;
4134 case MAC_STAT_IPACKETS:
4135 *val = ic->ic_stats.is_rx_frags;
4136 break;
4137 case MAC_STAT_OBYTES:
4138 *val = ic->ic_stats.is_tx_bytes;
4139 break;
4140 case MAC_STAT_OPACKETS:
4141 *val = ic->ic_stats.is_tx_frags;
4142 break;
4143 case MAC_STAT_OERRORS:
4144 *val = ic->ic_stats.is_tx_failed;
4145 break;
4146 case WIFI_STAT_TX_FRAGS:
4147 case WIFI_STAT_MCAST_TX:
4148 case WIFI_STAT_TX_FAILED:
4149 case WIFI_STAT_TX_RETRANS:
4150 case WIFI_STAT_RTS_SUCCESS:
4151 case WIFI_STAT_RTS_FAILURE:
4152 case WIFI_STAT_ACK_FAILURE:
4153 case WIFI_STAT_RX_FRAGS:
4154 case WIFI_STAT_MCAST_RX:
4155 case WIFI_STAT_FCS_ERRORS:
4156 case WIFI_STAT_WEP_ERRORS:
4157 case WIFI_STAT_RX_DUPS:
4158 URTW_UNLOCK(sc);
4159 return (ieee80211_stat(ic, stat, val));
4160 default:
4161 URTW_UNLOCK(sc);
4162 return (ENOTSUP);
4163 }
4164 URTW_UNLOCK(sc);
4165
4166 return (0);
4167 }
4168
4169 static void
4170 urtw_watchdog(void *arg)
4171 {
4172 struct urtw_softc *sc = arg;
4173 struct ieee80211com *ic = &sc->sc_ic;
4174
4175 ieee80211_stop_watchdog(ic);
4176
4177 URTW_LOCK(sc);
4178 if (URTW_IS_NOT_RUNNING(sc)) {
4179 URTW_UNLOCK(sc);
4180 return;
4181 }
4182
4183 URTW_UNLOCK(sc);
4184 switch (ic->ic_state) {
4185 case IEEE80211_S_AUTH:
4186 case IEEE80211_S_ASSOC:
4187 if (ic->ic_bss->in_fails > 0) {
4188 ieee80211_new_state(ic, IEEE80211_S_INIT, -1);
4189 URTW8187_DBG(URTW_DEBUG_ACTIVE,
4190 (sc->sc_dev, CE_CONT,
4191 "urtw: watchdog begin\n"));
4192 } else
4193 ieee80211_watchdog(ic);
4194 break;
4195 }
4196 }
4197
4198
4199 static int
4200 urtw_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd)
4201 {
4202 struct urtw_softc *sc;
4203 struct ieee80211com *ic;
4204 int error, i, instance;
4205 uint32_t data = 0;
4206 uint8_t data8 = 0;
4207 char strbuf[32];
4208 wifi_data_t wd = { 0 };
4209 mac_register_t *macp;
4210 struct urtw_type *e = 0;
4211 char *urtw_name = NULL;
4212
4213 switch (cmd) {
4214 case DDI_ATTACH:
4215 break;
4216 case DDI_RESUME:
4217 sc = ddi_get_soft_state(urtw_soft_state_p,
4218 ddi_get_instance(devinfo));
4219 ASSERT(sc != NULL);
4220 URTW8187_DBG(URTW_DEBUG_ACTIVE,
4221 (sc->sc_dev, CE_CONT, "urtw: resume\n"));
4222 URTW_LOCK(sc);
4223 sc->sc_flags &= ~URTW_FLAG_SUSPEND;
4224 URTW_UNLOCK(sc);
4225 if (URTW_IS_PLUGIN_ONLINE(sc)) {
4226 error = sc->urtw_init(sc);
4227 if (error == 0) {
4228 URTW_LOCK(sc);
4229 sc->sc_flags &= ~URTW_FLAG_PLUGIN_ONLINE;
4230 URTW_UNLOCK(sc);
4231 }
4232 }
4233 return (DDI_SUCCESS);
4234 default:
4235 return (DDI_FAILURE);
4236 }
4237
4238 instance = ddi_get_instance(devinfo);
4239
4240 if (ddi_soft_state_zalloc(urtw_soft_state_p, instance) != DDI_SUCCESS) {
4241 cmn_err(CE_WARN, "urtw_attach:unable to alloc soft_state_p\n");
4242 return (DDI_FAILURE);
4243 }
4244
4245 sc = ddi_get_soft_state(urtw_soft_state_p, instance);
4246 ic = (ieee80211com_t *)&sc->sc_ic;
4247 sc->sc_dev = devinfo;
4248
4249 if (usb_client_attach(devinfo, USBDRV_VERSION, 0) != USB_SUCCESS) {
4250 cmn_err(CE_WARN, "urtw_attach: usb_client_attach failed\n");
4251 goto fail1;
4252 }
4253
4254 if (usb_get_dev_data(devinfo, &sc->sc_udev,
4255 USB_PARSE_LVL_ALL, 0) != USB_SUCCESS) {
4256 sc->sc_udev = NULL;
4257 goto fail2;
4258 }
4259
4260 mutex_init(&sc->sc_genlock, NULL, MUTEX_DRIVER, NULL);
4261 mutex_init(&sc->tx_lock, NULL, MUTEX_DRIVER, NULL);
4262 mutex_init(&sc->rx_lock, NULL, MUTEX_DRIVER, NULL);
4263 mutex_init(&sc->sc_ledlock, NULL, MUTEX_DRIVER, NULL);
4264
4265 e = urtw_lookup(sc->sc_udev->dev_descr->idVendor,
4266 sc->sc_udev->dev_descr->idProduct);
4267 if (e == NULL) {
4268 cmn_err(CE_WARN, "(urtw) unknown device\n");
4269 goto fail2;
4270 }
4271 sc->sc_hwrev = e->rev;
4272
4273 if (sc->sc_hwrev & URTW_HWREV_8187) {
4274 (void) urtw_read32_c(sc, URTW_TX_CONF, &data, 0);
4275 data &= URTW_TX_HWREV_MASK;
4276 switch (data) {
4277 case URTW_TX_HWREV_8187_D:
4278 sc->sc_hwrev |= URTW_HWREV_8187_D;
4279 urtw_name = "RTL8187 rev. D";
4280 break;
4281 case URTW_TX_HWREV_8187B_D:
4282 /*
4283 * Detect Realtek RTL8187B devices that use
4284 * USB IDs of RTL8187.
4285 */
4286 sc->sc_hwrev = URTW_HWREV_8187B | URTW_HWREV_8187B_B;
4287 urtw_name = "RTL8187B rev. B (early)";
4288 break;
4289 default:
4290 sc->sc_hwrev |= URTW_HWREV_8187_B;
4291 urtw_name = "RTL8187 rev. B (default)";
4292 break;
4293 }
4294 } else {
4295 /* RTL8187B hwrev register. */
4296 (void) urtw_read8_c(sc, URTW_8187B_HWREV, &data8, 0);
4297 switch (data8) {
4298 case URTW_8187B_HWREV_8187B_B:
4299 sc->sc_hwrev |= URTW_HWREV_8187B_B;
4300 urtw_name = "RTL8187B rev. B";
4301 break;
4302 case URTW_8187B_HWREV_8187B_D:
4303 sc->sc_hwrev |= URTW_HWREV_8187B_D;
4304 urtw_name = "RTL8187B rev. D";
4305 break;
4306 case URTW_8187B_HWREV_8187B_E:
4307 sc->sc_hwrev |= URTW_HWREV_8187B_E;
4308 urtw_name = "RTL8187B rev. E";
4309 break;
4310 default:
4311 sc->sc_hwrev |= URTW_HWREV_8187B_B;
4312 urtw_name = "RTL8187B rev. B (default)";
4313 break;
4314 }
4315 }
4316
4317 URTW8187_DBG(URTW_DEBUG_HWTYPE, (sc->sc_dev, CE_CONT,
4318 "urtw_attach: actual device is %s\n", urtw_name));
4319 if (sc->sc_hwrev & URTW_HWREV_8187) {
4320 sc->urtw_init = urtw_8187_init;
4321 } else {
4322 sc->urtw_init = urtw_8187b_init;
4323 }
4324
4325 if (urtw_read32_c(sc, URTW_RX, &data, 0))
4326 goto fail3;
4327 sc->sc_epromtype = (data & URTW_RX_9356SEL) ? URTW_EEPROM_93C56 :
4328 URTW_EEPROM_93C46;
4329 if (sc->sc_epromtype == URTW_EEPROM_93C56)
4330 URTW8187_DBG(URTW_DEBUG_HWTYPE, (sc->sc_dev, CE_CONT,
4331 "urtw_attach: eprom is 93C56\n"));
4332 else
4333 URTW8187_DBG(URTW_DEBUG_HWTYPE, (sc->sc_dev, CE_CONT,
4334 "urtw_attach: eprom is 93C46\n"));
4335 error = urtw_get_rfchip(sc);
4336 if (error != 0)
4337 goto fail3;
4338 error = urtw_get_macaddr(sc);
4339 if (error != 0)
4340 goto fail3;
4341 error = urtw_get_txpwr(sc);
4342 if (error != 0)
4343 goto fail3;
4344 error = urtw_led_init(sc); /* XXX incompleted */
4345 if (error != 0)
4346 goto fail3;
4347
4348 sc->sc_rts_retry = URTW_DEFAULT_RTS_RETRY;
4349 sc->sc_tx_retry = URTW_DEFAULT_TX_RETRY;
4350 sc->sc_currate = 3;
4351 /* XXX for what? */
4352 sc->sc_preamble_mode = 2;
4353
4354 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */
4355 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */
4356 ic->ic_state = IEEE80211_S_INIT;
4357
4358 ic->ic_maxrssi = 95;
4359 ic->ic_xmit = urtw_send;
4360
4361 ic->ic_caps |= IEEE80211_C_WPA | /* Support WPA/WPA2 */
4362 IEEE80211_C_TXPMGT | /* tx power management */
4363 IEEE80211_C_SHPREAMBLE | /* short preamble supported */
4364 IEEE80211_C_SHSLOT; /* short slot time supported */
4365 /* set supported .11b and .11g rates */
4366 ic->ic_sup_rates[IEEE80211_MODE_11B] = urtw_rateset_11b;
4367 ic->ic_sup_rates[IEEE80211_MODE_11G] = urtw_rateset_11g;
4368
4369 /* set supported .11b and .11g channels (1 through 11) */
4370 for (i = 1; i <= 11; i++) {
4371 ic->ic_sup_channels[i].ich_freq =
4372 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ);
4373 ic->ic_sup_channels[i].ich_flags =
4374 IEEE80211_CHAN_CCK | IEEE80211_CHAN_DYN |
4375 IEEE80211_CHAN_2GHZ | IEEE80211_CHAN_OFDM;
4376 }
4377
4378 ieee80211_attach(ic);
4379 ic->ic_ibss_chan = &ic->ic_sup_channels[1];
4380 ic->ic_curchan = ic->ic_ibss_chan;
4381
4382 /* register WPA door */
4383 ieee80211_register_door(ic, ddi_driver_name(devinfo),
4384 ddi_get_instance(devinfo));
4385
4386 /* override state transition machine */
4387 sc->sc_newstate = ic->ic_newstate;
4388 ic->ic_newstate = urtw_newstate;
4389 ic->ic_watchdog = urtw_watchdog;
4390 ieee80211_media_init(ic);
4391 ic->ic_def_txkey = 0;
4392
4393 sc->dwelltime = 250;
4394 sc->sc_flags = 0;
4395
4396 /*
4397 * Provide initial settings for the WiFi plugin; whenever this
4398 * information changes, we need to call mac_plugindata_update()
4399 */
4400 wd.wd_opmode = ic->ic_opmode;
4401 wd.wd_secalloc = WIFI_SEC_NONE;
4402 IEEE80211_ADDR_COPY(wd.wd_bssid, ic->ic_bss->in_bssid);
4403
4404 if ((macp = mac_alloc(MAC_VERSION)) == NULL) {
4405 URTW8187_DBG(URTW_DEBUG_ATTACH, (sc->sc_dev, CE_CONT,
4406 "MAC version alloc failed\n"));
4407 goto fail4;
4408 }
4409
4410 macp->m_type_ident = MAC_PLUGIN_IDENT_WIFI;
4411 macp->m_driver = sc;
4412 macp->m_dip = devinfo;
4413 macp->m_src_addr = ic->ic_macaddr;
4414 macp->m_callbacks = &urtw_m_callbacks;
4415 macp->m_min_sdu = 0;
4416 macp->m_max_sdu = IEEE80211_MTU;
4417 macp->m_pdata = &wd;
4418 macp->m_pdata_size = sizeof (wd);
4419
4420 error = mac_register(macp, &ic->ic_mach);
4421 mac_free(macp);
4422 if (error != 0) {
4423 cmn_err(CE_WARN, "urtw_attach: mac_register() err %x\n", error);
4424 goto fail4;
4425 }
4426
4427 if (usb_register_hotplug_cbs(devinfo, urtw_disconnect,
4428 urtw_reconnect) != USB_SUCCESS) {
4429 cmn_err(CE_WARN, "urtw_attach: failed to register events");
4430 goto fail5;
4431 }
4432
4433 /*
4434 * Create minor node of type DDI_NT_NET_WIFI
4435 */
4436 (void) snprintf(strbuf, sizeof (strbuf), "%s%d",
4437 "urtw", instance);
4438 error = ddi_create_minor_node(devinfo, strbuf, S_IFCHR,
4439 instance + 1, DDI_NT_NET_WIFI, 0);
4440
4441 if (error != DDI_SUCCESS)
4442 cmn_err(CE_WARN, "urtw: ddi_create_minor_node() failed\n");
4443 /*
4444 * Notify link is down now
4445 */
4446 mac_link_update(ic->ic_mach, LINK_STATE_DOWN);
4447
4448 URTW8187_DBG(URTW_DEBUG_ATTACH, (sc->sc_dev, CE_CONT,
4449 "urtw_attach: successfully.\n"));
4450 return (DDI_SUCCESS);
4451 fail5:
4452 (void) mac_disable(ic->ic_mach);
4453 (void) mac_unregister(ic->ic_mach);
4454 fail4:
4455 ieee80211_detach(ic);
4456 fail3:
4457 mutex_destroy(&sc->sc_genlock);
4458 mutex_destroy(&sc->tx_lock);
4459 mutex_destroy(&sc->rx_lock);
4460 mutex_destroy(&sc->sc_ledlock);
4461 fail2:
4462 usb_client_detach(sc->sc_dev, sc->sc_udev);
4463 fail1:
4464 ddi_soft_state_free(urtw_soft_state_p, ddi_get_instance(devinfo));
4465
4466 return (DDI_FAILURE);
4467 }
4468
4469 static int
4470 urtw_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd)
4471 {
4472 struct urtw_softc *sc;
4473
4474 sc = ddi_get_soft_state(urtw_soft_state_p, ddi_get_instance(devinfo));
4475 URTW8187_DBG(URTW_DEBUG_ATTACH, (sc->sc_dev,
4476 CE_CONT, "urtw_detach()\n"));
4477
4478 switch (cmd) {
4479 case DDI_DETACH:
4480 break;
4481 case DDI_SUSPEND:
4482 URTW8187_DBG(URTW_DEBUG_ATTACH,
4483 (sc->sc_dev, CE_CONT, "urtw: suspend\n"));
4484
4485 ieee80211_new_state(&sc->sc_ic, IEEE80211_S_INIT, -1);
4486 ieee80211_stop_watchdog(&sc->sc_ic);
4487
4488 URTW_LOCK(sc);
4489 sc->sc_flags |= URTW_FLAG_SUSPEND;
4490 URTW_UNLOCK(sc);
4491 if (URTW_IS_RUNNING(sc)) {
4492 urtw_stop(sc);
4493 URTW_LOCK(sc);
4494 sc->sc_flags |= URTW_FLAG_PLUGIN_ONLINE;
4495 URTW_UNLOCK(sc);
4496 }
4497 return (DDI_SUCCESS);
4498 default:
4499 return (DDI_FAILURE);
4500 }
4501
4502 if (mac_disable(sc->sc_ic.ic_mach) != 0)
4503 return (DDI_FAILURE);
4504 urtw_stop(sc);
4505 /*
4506 * Unregister from the MAC layer subsystem
4507 */
4508 (void) mac_unregister(sc->sc_ic.ic_mach);
4509
4510 ieee80211_detach(&sc->sc_ic);
4511 usb_unregister_hotplug_cbs(devinfo);
4512 usb_client_detach(devinfo, sc->sc_udev);
4513 mutex_destroy(&sc->sc_genlock);
4514 mutex_destroy(&sc->tx_lock);
4515 mutex_destroy(&sc->rx_lock);
4516 mutex_destroy(&sc->sc_ledlock);
4517 sc->sc_udev = NULL;
4518
4519 ddi_remove_minor_node(devinfo, NULL);
4520 ddi_soft_state_free(urtw_soft_state_p, ddi_get_instance(devinfo));
4521
4522 return (DDI_SUCCESS);
4523 }
4524
4525 int
4526 _info(struct modinfo *modinfop)
4527 {
4528 return (mod_info(&modlinkage, modinfop));
4529 }
4530
4531 int
4532 _init(void)
4533 {
4534 int status;
4535
4536 status = ddi_soft_state_init(&urtw_soft_state_p,
4537 sizeof (struct urtw_softc), 1);
4538 if (status != 0)
4539 return (status);
4540
4541 mac_init_ops(&urtw_dev_ops, "urtw");
4542 status = mod_install(&modlinkage);
4543 if (status != 0) {
4544 mac_fini_ops(&urtw_dev_ops);
4545 ddi_soft_state_fini(&urtw_soft_state_p);
4546 }
4547 return (status);
4548 }
4549
4550 int
4551 _fini(void)
4552 {
4553 int status;
4554
4555 status = mod_remove(&modlinkage);
4556 if (status == 0) {
4557 mac_fini_ops(&urtw_dev_ops);
4558 ddi_soft_state_fini(&urtw_soft_state_p);
4559 }
4560 return (status);
4561 }