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7127 remove -Wno-missing-braces from Makefile.uts
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--- old/usr/src/uts/common/io/ral/rt2560.c
+++ new/usr/src/uts/common/io/ral/rt2560.c
1 1 /*
2 2 * Copyright 2010 Sun Microsystems, Inc. All rights reserved.
3 3 * Use is subject to license terms.
4 4 */
5 5
6 6 /*
7 7 * Copyright (c) 2005, 2006
8 8 * Damien Bergamini <damien.bergamini@free.fr>
9 9 *
10 10 * Permission to use, copy, modify, and distribute this software for any
11 11 * purpose with or without fee is hereby granted, provided that the above
12 12 * copyright notice and this permission notice appear in all copies.
13 13 *
14 14 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
15 15 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
16 16 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
17 17 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
18 18 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
19 19 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
20 20 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
21 21 */
22 22
23 23 /*
24 24 * Ralink Technology RT2560 chipset driver
25 25 * http://www.ralinktech.com/
26 26 */
27 27
28 28 #include <sys/types.h>
29 29 #include <sys/byteorder.h>
30 30 #include <sys/cmn_err.h>
31 31 #include <sys/stat.h>
32 32 #include <sys/pci.h>
33 33 #include <sys/ddi.h>
34 34 #include <sys/sunddi.h>
35 35 #include <sys/strsubr.h>
36 36 #include <inet/common.h>
37 37 #include <sys/note.h>
38 38 #include <sys/strsun.h>
39 39 #include <sys/modctl.h>
40 40 #include <sys/devops.h>
41 41 #include <sys/mac_provider.h>
42 42 #include <sys/mac_wifi.h>
43 43 #include <sys/net80211.h>
44 44
45 45 #include "ral_rate.h"
46 46 #include "rt2560_reg.h"
47 47 #include "rt2560_var.h"
48 48
49 49 static void *ral_soft_state_p = NULL;
50 50
51 51 #define RAL_TXBUF_SIZE (IEEE80211_MAX_LEN)
52 52 #define RAL_RXBUF_SIZE (IEEE80211_MAX_LEN)
53 53
54 54 /* quickly determine if a given rate is CCK or OFDM */
55 55 #define RAL_RATE_IS_OFDM(rate) ((rate) >= 12 && (rate) != 22)
56 56 #define RAL_ACK_SIZE 14 /* 10 + 4(FCS) */
57 57 #define RAL_CTS_SIZE 14 /* 10 + 4(FCS) */
58 58 #define RAL_SIFS 10 /* us */
59 59 #define RT2560_TXRX_TURNAROUND 10 /* us */
60 60
61 61 /*
62 62 * Supported rates for 802.11a/b/g modes (in 500Kbps unit).
63 63 */
64 64 static const struct ieee80211_rateset rt2560_rateset_11a =
65 65 { 8, { 12, 18, 24, 36, 48, 72, 96, 108 } };
66 66
67 67 static const struct ieee80211_rateset rt2560_rateset_11b =
68 68 { 4, { 2, 4, 11, 22 } };
69 69
70 70 static const struct ieee80211_rateset rt2560_rateset_11g =
71 71 { 12, { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 } };
72 72
73 73 static const struct {
74 74 uint32_t reg;
75 75 uint32_t val;
76 76 } rt2560_def_mac[] = {
77 77 RT2560_DEF_MAC
78 78 };
79 79
80 80 static const struct {
81 81 uint8_t reg;
82 82 uint8_t val;
83 83 } rt2560_def_bbp[] = {
84 84 RT2560_DEF_BBP
85 85 };
86 86
87 87 static const uint32_t rt2560_rf2522_r2[] = RT2560_RF2522_R2;
88 88 static const uint32_t rt2560_rf2523_r2[] = RT2560_RF2523_R2;
89 89 static const uint32_t rt2560_rf2524_r2[] = RT2560_RF2524_R2;
90 90 static const uint32_t rt2560_rf2525_r2[] = RT2560_RF2525_R2;
91 91 static const uint32_t rt2560_rf2525_hi_r2[] = RT2560_RF2525_HI_R2;
92 92 static const uint32_t rt2560_rf2525e_r2[] = RT2560_RF2525E_R2;
93 93 static const uint32_t rt2560_rf2526_r2[] = RT2560_RF2526_R2;
94 94 static const uint32_t rt2560_rf2526_hi_r2[] = RT2560_RF2526_HI_R2;
95 95
96 96 static const struct {
97 97 uint8_t chan;
98 98 uint32_t r1, r2, r4;
99 99 } rt2560_rf5222[] = {
100 100 RT2560_RF5222
101 101 };
102 102
103 103 /*
104 104 * PIO access attributes for registers
105 105 */
106 106 static ddi_device_acc_attr_t ral_csr_accattr = {
107 107 DDI_DEVICE_ATTR_V0,
108 108 DDI_STRUCTURE_LE_ACC,
109 109 DDI_STRICTORDER_ACC
110 110 };
111 111
112 112 /*
113 113 * DMA access attributes for descriptors: NOT to be byte swapped.
114 114 */
115 115 static ddi_device_acc_attr_t ral_desc_accattr = {
116 116 DDI_DEVICE_ATTR_V0,
117 117 DDI_STRUCTURE_LE_ACC,
118 118 DDI_STRICTORDER_ACC
119 119 };
120 120
121 121 /*
122 122 * Describes the chip's DMA engine
123 123 */
124 124 static ddi_dma_attr_t ral_dma_attr = {
125 125 DMA_ATTR_V0, /* dma_attr version */
126 126 0x0000000000000000ull, /* dma_attr_addr_lo */
127 127 0xFFFFFFFF, /* dma_attr_addr_hi */
128 128 0x00000000FFFFFFFFull, /* dma_attr_count_max */
129 129 0x0000000000000001ull, /* dma_attr_align */
130 130 0x00000FFF, /* dma_attr_burstsizes */
131 131 0x00000001, /* dma_attr_minxfer */
132 132 0x000000000000FFFFull, /* dma_attr_maxxfer */
133 133 0xFFFFFFFFFFFFFFFFull, /* dma_attr_seg */
134 134 1, /* dma_attr_sgllen */
135 135 0x00000001, /* dma_attr_granular */
136 136 0 /* dma_attr_flags */
137 137 };
138 138
139 139 /*
140 140 * device operations
141 141 */
142 142 static int rt2560_attach(dev_info_t *, ddi_attach_cmd_t);
143 143 static int rt2560_detach(dev_info_t *, ddi_detach_cmd_t);
144 144 static int32_t rt2560_quiesce(dev_info_t *);
145 145
146 146 /*
147 147 * Module Loading Data & Entry Points
148 148 */
149 149 DDI_DEFINE_STREAM_OPS(ral_dev_ops, nulldev, nulldev, rt2560_attach,
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149 lines elided |
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150 150 rt2560_detach, nodev, NULL, D_MP, NULL, rt2560_quiesce);
151 151
152 152 static struct modldrv ral_modldrv = {
153 153 &mod_driverops, /* Type of module. This one is a driver */
154 154 "Ralink RT2500 driver v1.6", /* short description */
155 155 &ral_dev_ops /* driver specific ops */
156 156 };
157 157
158 158 static struct modlinkage modlinkage = {
159 159 MODREV_1,
160 - (void *)&ral_modldrv,
161 - NULL
160 + { (void *)&ral_modldrv, NULL }
162 161 };
163 162
164 163 static int rt2560_m_stat(void *, uint_t, uint64_t *);
165 164 static int rt2560_m_start(void *);
166 165 static void rt2560_m_stop(void *);
167 166 static int rt2560_m_promisc(void *, boolean_t);
168 167 static int rt2560_m_multicst(void *, boolean_t, const uint8_t *);
169 168 static int rt2560_m_unicst(void *, const uint8_t *);
170 169 static mblk_t *rt2560_m_tx(void *, mblk_t *);
171 170 static void rt2560_m_ioctl(void *, queue_t *, mblk_t *);
172 171 static int rt2560_m_setprop(void *, const char *, mac_prop_id_t,
173 172 uint_t, const void *);
174 173 static int rt2560_m_getprop(void *, const char *, mac_prop_id_t,
175 174 uint_t, void *);
176 175 static void rt2560_m_propinfo(void *, const char *, mac_prop_id_t,
177 176 mac_prop_info_handle_t);
178 177
179 178 static mac_callbacks_t rt2560_m_callbacks = {
180 179 MC_IOCTL | MC_SETPROP | MC_GETPROP | MC_PROPINFO,
181 180 rt2560_m_stat,
182 181 rt2560_m_start,
183 182 rt2560_m_stop,
184 183 rt2560_m_promisc,
185 184 rt2560_m_multicst,
186 185 rt2560_m_unicst,
187 186 rt2560_m_tx,
188 187 NULL,
189 188 rt2560_m_ioctl,
190 189 NULL, /* mc_getcapab */
191 190 NULL,
192 191 NULL,
193 192 rt2560_m_setprop,
194 193 rt2560_m_getprop,
195 194 rt2560_m_propinfo
196 195 };
197 196
198 197 uint32_t ral_dbg_flags = 0;
199 198
200 199 void
201 200 ral_debug(uint32_t dbg_flags, const int8_t *fmt, ...)
202 201 {
203 202 va_list args;
204 203
205 204 if (dbg_flags & ral_dbg_flags) {
206 205 va_start(args, fmt);
207 206 vcmn_err(CE_CONT, fmt, args);
208 207 va_end(args);
209 208 }
210 209 }
211 210
212 211 static void
213 212 rt2560_set_basicrates(struct rt2560_softc *sc)
214 213 {
215 214 struct ieee80211com *ic = &sc->sc_ic;
216 215
217 216 /* update basic rate set */
218 217 if (ic->ic_curmode == IEEE80211_MODE_11B) {
219 218 /* 11b basic rates: 1, 2Mbps */
220 219 RAL_WRITE(sc, RT2560_ARSP_PLCP_1, 0x3);
221 220 } else if (IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan)) {
222 221 /* 11a basic rates: 6, 12, 24Mbps */
223 222 RAL_WRITE(sc, RT2560_ARSP_PLCP_1, 0x150);
224 223 } else {
225 224 /* 11g basic rates: 1, 2, 5.5, 11, 6, 12, 24Mbps */
226 225 RAL_WRITE(sc, RT2560_ARSP_PLCP_1, 0x15f);
227 226 }
228 227 }
229 228
230 229 static void
231 230 rt2560_update_led(struct rt2560_softc *sc, int led1, int led2)
232 231 {
233 232 uint32_t tmp;
234 233
235 234 /* set ON period to 70ms and OFF period to 30ms */
236 235 tmp = led1 << 16 | led2 << 17 | 70 << 8 | 30;
237 236 RAL_WRITE(sc, RT2560_LEDCSR, tmp);
238 237 }
239 238
240 239 static void
241 240 rt2560_set_bssid(struct rt2560_softc *sc, uint8_t *bssid)
242 241 {
243 242 uint32_t tmp;
244 243
245 244 tmp = bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24;
246 245 RAL_WRITE(sc, RT2560_CSR5, tmp);
247 246
248 247 tmp = bssid[4] | bssid[5] << 8;
249 248 RAL_WRITE(sc, RT2560_CSR6, tmp);
250 249
251 250 ral_debug(RAL_DBG_HW, "setting BSSID to " MACSTR "\n", MAC2STR(bssid));
252 251 }
253 252
254 253
255 254 static void
256 255 rt2560_bbp_write(struct rt2560_softc *sc, uint8_t reg, uint8_t val)
257 256 {
258 257 uint32_t tmp;
259 258 int ntries;
260 259
261 260 for (ntries = 0; ntries < 100; ntries++) {
262 261 if (!(RAL_READ(sc, RT2560_BBPCSR) & RT2560_BBP_BUSY))
263 262 break;
264 263 drv_usecwait(1);
265 264 }
266 265 if (ntries == 100) {
267 266 ral_debug(RAL_DBG_HW, "could not write to BBP\n");
268 267 return;
269 268 }
270 269
271 270 tmp = RT2560_BBP_WRITE | RT2560_BBP_BUSY | reg << 8 | val;
272 271 RAL_WRITE(sc, RT2560_BBPCSR, tmp);
273 272
274 273 ral_debug(RAL_DBG_HW, "BBP R%u <- 0x%02x\n", reg, val);
275 274 }
276 275
277 276 static uint8_t
278 277 rt2560_bbp_read(struct rt2560_softc *sc, uint8_t reg)
279 278 {
280 279 uint32_t val;
281 280 int ntries;
282 281
283 282 val = RT2560_BBP_BUSY | reg << 8;
284 283 RAL_WRITE(sc, RT2560_BBPCSR, val);
285 284
286 285 for (ntries = 0; ntries < 100; ntries++) {
287 286 val = RAL_READ(sc, RT2560_BBPCSR);
288 287 if (!(val & RT2560_BBP_BUSY))
289 288 return (val & 0xff);
290 289 drv_usecwait(1);
291 290 }
292 291
293 292 ral_debug(RAL_DBG_HW, "could not read from BBP\n");
294 293 return (0);
295 294 }
296 295
297 296 static void
298 297 rt2560_rf_write(struct rt2560_softc *sc, uint8_t reg, uint32_t val)
299 298 {
300 299 uint32_t tmp;
301 300 int ntries;
302 301
303 302 for (ntries = 0; ntries < 100; ntries++) {
304 303 if (!(RAL_READ(sc, RT2560_RFCSR) & RT2560_RF_BUSY))
305 304 break;
306 305 drv_usecwait(1);
307 306 }
308 307 if (ntries == 100) {
309 308 ral_debug(RAL_DBG_HW, "could not write to RF\n");
310 309 return;
311 310 }
312 311
313 312 tmp = RT2560_RF_BUSY | RT2560_RF_20BIT | (val & 0xfffff) << 2 |
314 313 (reg & 0x3);
315 314 RAL_WRITE(sc, RT2560_RFCSR, tmp);
316 315
317 316 /* remember last written value in sc */
318 317 sc->rf_regs[reg] = val;
319 318
320 319 ral_debug(RAL_DBG_HW, "RF R[%u] <- 0x%05x\n", reg & 0x3, val & 0xfffff);
321 320 }
322 321
323 322 static void
324 323 rt2560_set_chan(struct rt2560_softc *sc, struct ieee80211_channel *c)
325 324 {
326 325 struct ieee80211com *ic = &sc->sc_ic;
327 326 uint8_t power, tmp;
328 327 uint_t i, chan;
329 328
330 329 chan = ieee80211_chan2ieee(ic, c);
331 330 if (chan == 0 || chan == IEEE80211_CHAN_ANY)
332 331 return;
333 332
334 333 if (IEEE80211_IS_CHAN_2GHZ(c))
335 334 power = min(sc->txpow[chan - 1], 31);
336 335 else
337 336 power = 31;
338 337
339 338 /* adjust txpower using ifconfig settings */
340 339 power -= (100 - ic->ic_txpowlimit) / 8;
341 340
342 341 ral_debug(RAL_DBG_CHAN, "setting channel to %u, txpower to %u\n",
343 342 chan, power);
344 343
345 344 switch (sc->rf_rev) {
346 345 case RT2560_RF_2522:
347 346 rt2560_rf_write(sc, RAL_RF1, 0x00814);
348 347 rt2560_rf_write(sc, RAL_RF2, rt2560_rf2522_r2[chan - 1]);
349 348 rt2560_rf_write(sc, RAL_RF3, power << 7 | 0x00040);
350 349 break;
351 350
352 351 case RT2560_RF_2523:
353 352 rt2560_rf_write(sc, RAL_RF1, 0x08804);
354 353 rt2560_rf_write(sc, RAL_RF2, rt2560_rf2523_r2[chan - 1]);
355 354 rt2560_rf_write(sc, RAL_RF3, power << 7 | 0x38044);
356 355 rt2560_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286);
357 356 break;
358 357
359 358 case RT2560_RF_2524:
360 359 rt2560_rf_write(sc, RAL_RF1, 0x0c808);
361 360 rt2560_rf_write(sc, RAL_RF2, rt2560_rf2524_r2[chan - 1]);
362 361 rt2560_rf_write(sc, RAL_RF3, power << 7 | 0x00040);
363 362 rt2560_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286);
364 363 break;
365 364
366 365 case RT2560_RF_2525:
367 366 rt2560_rf_write(sc, RAL_RF1, 0x08808);
368 367 rt2560_rf_write(sc, RAL_RF2, rt2560_rf2525_hi_r2[chan - 1]);
369 368 rt2560_rf_write(sc, RAL_RF3, power << 7 | 0x18044);
370 369 rt2560_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286);
371 370
372 371 rt2560_rf_write(sc, RAL_RF1, 0x08808);
373 372 rt2560_rf_write(sc, RAL_RF2, rt2560_rf2525_r2[chan - 1]);
374 373 rt2560_rf_write(sc, RAL_RF3, power << 7 | 0x18044);
375 374 rt2560_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286);
376 375 break;
377 376
378 377 case RT2560_RF_2525E:
379 378 rt2560_rf_write(sc, RAL_RF1, 0x08808);
380 379 rt2560_rf_write(sc, RAL_RF2, rt2560_rf2525e_r2[chan - 1]);
381 380 rt2560_rf_write(sc, RAL_RF3, power << 7 | 0x18044);
382 381 rt2560_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00286 : 0x00282);
383 382 break;
384 383
385 384 case RT2560_RF_2526:
386 385 rt2560_rf_write(sc, RAL_RF2, rt2560_rf2526_hi_r2[chan - 1]);
387 386 rt2560_rf_write(sc, RAL_RF4, (chan & 1) ? 0x00386 : 0x00381);
388 387 rt2560_rf_write(sc, RAL_RF1, 0x08804);
389 388
390 389 rt2560_rf_write(sc, RAL_RF2, rt2560_rf2526_r2[chan - 1]);
391 390 rt2560_rf_write(sc, RAL_RF3, power << 7 | 0x18044);
392 391 rt2560_rf_write(sc, RAL_RF4, (chan & 1) ? 0x00386 : 0x00381);
393 392 break;
394 393
395 394 /* dual-band RF */
396 395 case RT2560_RF_5222:
397 396 for (i = 0; rt2560_rf5222[i].chan != chan; i++) {
398 397 }
399 398
400 399 rt2560_rf_write(sc, RAL_RF1, rt2560_rf5222[i].r1);
401 400 rt2560_rf_write(sc, RAL_RF2, rt2560_rf5222[i].r2);
402 401 rt2560_rf_write(sc, RAL_RF3, power << 7 | 0x00040);
403 402 rt2560_rf_write(sc, RAL_RF4, rt2560_rf5222[i].r4);
404 403 break;
405 404 }
406 405
407 406 if (ic->ic_state != IEEE80211_S_SCAN) {
408 407 /* set Japan filter bit for channel 14 */
409 408 tmp = rt2560_bbp_read(sc, 70);
410 409
411 410 tmp &= ~RT2560_JAPAN_FILTER;
412 411 if (chan == 14)
413 412 tmp |= RT2560_JAPAN_FILTER;
414 413
415 414 rt2560_bbp_write(sc, 70, tmp);
416 415
417 416 /* clear CRC errors */
418 417 (void) RAL_READ(sc, RT2560_CNT0);
419 418 }
420 419 }
421 420
422 421 /*
423 422 * Refer to IEEE Std 802.11-1999 pp. 123 for more information on TSF
424 423 * synchronization.
425 424 */
426 425 static void
427 426 rt2560_enable_tsf_sync(struct rt2560_softc *sc)
428 427 {
429 428 struct ieee80211com *ic = &sc->sc_ic;
430 429 uint16_t logcwmin, preload;
431 430 uint32_t tmp;
432 431
433 432 /* first, disable TSF synchronization */
434 433 RAL_WRITE(sc, RT2560_CSR14, 0);
435 434
436 435 tmp = 16 * ic->ic_bss->in_intval;
437 436 RAL_WRITE(sc, RT2560_CSR12, tmp);
438 437
439 438 RAL_WRITE(sc, RT2560_CSR13, 0);
440 439
441 440 logcwmin = 5;
442 441 preload = (ic->ic_opmode == IEEE80211_M_STA) ? 384 : 1024;
443 442 tmp = logcwmin << 16 | preload;
444 443 RAL_WRITE(sc, RT2560_BCNOCSR, tmp);
445 444
446 445 /* finally, enable TSF synchronization */
447 446 tmp = RT2560_ENABLE_TSF | RT2560_ENABLE_TBCN;
448 447 if (ic->ic_opmode == IEEE80211_M_STA)
449 448 tmp |= RT2560_ENABLE_TSF_SYNC(1);
450 449 else
451 450 tmp |= RT2560_ENABLE_TSF_SYNC(2) |
452 451 RT2560_ENABLE_BEACON_GENERATOR;
453 452 RAL_WRITE(sc, RT2560_CSR14, tmp);
454 453
455 454 ral_debug(RAL_DBG_HW, "enabling TSF synchronization\n");
456 455 }
457 456
458 457 static void
459 458 rt2560_update_plcp(struct rt2560_softc *sc)
460 459 {
461 460 struct ieee80211com *ic = &sc->sc_ic;
462 461
463 462 /* no short preamble for 1Mbps */
464 463 RAL_WRITE(sc, RT2560_PLCP1MCSR, 0x00700400);
465 464
466 465 if (!(ic->ic_flags & IEEE80211_F_SHPREAMBLE)) {
467 466 /* values taken from the reference driver */
468 467 RAL_WRITE(sc, RT2560_PLCP2MCSR, 0x00380401);
469 468 RAL_WRITE(sc, RT2560_PLCP5p5MCSR, 0x00150402);
470 469 RAL_WRITE(sc, RT2560_PLCP11MCSR, 0x000b8403);
471 470 } else {
472 471 /* same values as above or'ed 0x8 */
473 472 RAL_WRITE(sc, RT2560_PLCP2MCSR, 0x00380409);
474 473 RAL_WRITE(sc, RT2560_PLCP5p5MCSR, 0x0015040a);
475 474 RAL_WRITE(sc, RT2560_PLCP11MCSR, 0x000b840b);
476 475 }
477 476
478 477 ral_debug(RAL_DBG_HW, "updating PLCP for %s preamble\n",
479 478 (ic->ic_flags & IEEE80211_F_SHPREAMBLE) ? "short" : "long");
480 479 }
481 480
482 481 /*
483 482 * This function can be called by ieee80211_set_shortslottime(). Refer to
484 483 * IEEE Std 802.11-1999 pp. 85 to know how these values are computed.
485 484 */
486 485 void
487 486 rt2560_update_slot(struct ieee80211com *ic, int onoff)
488 487 {
489 488 struct rt2560_softc *sc = (struct rt2560_softc *)ic;
490 489 uint8_t slottime;
491 490 uint16_t tx_sifs, tx_pifs, tx_difs, eifs;
492 491 uint32_t tmp;
493 492
494 493 /* slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; */
495 494 slottime = (onoff ? 9 : 20);
496 495
497 496 /* update the MAC slot boundaries */
498 497 tx_sifs = RAL_SIFS - RT2560_TXRX_TURNAROUND;
499 498 tx_pifs = tx_sifs + slottime;
500 499 tx_difs = tx_sifs + 2 * slottime;
501 500 eifs = (ic->ic_curmode == IEEE80211_MODE_11B) ? 364 : 60;
502 501
503 502 tmp = RAL_READ(sc, RT2560_CSR11);
504 503 tmp = (tmp & ~0x1f00) | slottime << 8;
505 504 RAL_WRITE(sc, RT2560_CSR11, tmp);
506 505
507 506 tmp = tx_pifs << 16 | tx_sifs;
508 507 RAL_WRITE(sc, RT2560_CSR18, tmp);
509 508
510 509 tmp = eifs << 16 | tx_difs;
511 510 RAL_WRITE(sc, RT2560_CSR19, tmp);
512 511
513 512 ral_debug(RAL_DBG_HW, "setting slottime to %uus\n", slottime);
514 513 }
515 514
516 515 int
517 516 ral_dma_region_alloc(struct rt2560_softc *sc, struct dma_region *dr,
518 517 size_t size, uint_t alloc_flags, uint_t bind_flags)
519 518 {
520 519 dev_info_t *dip = sc->sc_dev;
521 520 int err;
522 521
523 522 err = ddi_dma_alloc_handle(dip, &ral_dma_attr, DDI_DMA_SLEEP, NULL,
524 523 &dr->dr_hnd);
525 524 if (err != DDI_SUCCESS)
526 525 goto fail1;
527 526
528 527 err = ddi_dma_mem_alloc(dr->dr_hnd, size, &ral_desc_accattr,
529 528 alloc_flags, DDI_DMA_SLEEP, NULL,
530 529 &dr->dr_base, &dr->dr_size, &dr->dr_acc);
531 530 if (err != DDI_SUCCESS)
532 531 goto fail2;
533 532
534 533 err = ddi_dma_addr_bind_handle(dr->dr_hnd, NULL,
535 534 dr->dr_base, dr->dr_size,
536 535 bind_flags, DDI_DMA_SLEEP, NULL, &dr->dr_cookie, &dr->dr_ccnt);
537 536 if (err != DDI_SUCCESS)
538 537 goto fail3;
539 538
540 539 if (dr->dr_ccnt != 1) {
541 540 err = DDI_FAILURE;
542 541 goto fail4;
543 542 }
544 543
545 544 dr->dr_pbase = dr->dr_cookie.dmac_address;
546 545 ral_debug(RAL_DBG_DMA, "get physical-base=0x%08x\n", dr->dr_pbase);
547 546
548 547 return (DDI_SUCCESS);
549 548
550 549 fail4:
551 550 (void) ddi_dma_unbind_handle(dr->dr_hnd);
552 551 fail3:
553 552 ddi_dma_mem_free(&dr->dr_acc);
554 553 fail2:
555 554 ddi_dma_free_handle(&dr->dr_hnd);
556 555 fail1:
557 556 return (err);
558 557 }
559 558
560 559 /* ARGSUSED */
561 560 void
562 561 ral_dma_region_free(struct rt2560_softc *sc, struct dma_region *dr)
563 562 {
564 563 (void) ddi_dma_unbind_handle(dr->dr_hnd);
565 564 ddi_dma_mem_free(&dr->dr_acc);
566 565 ddi_dma_free_handle(&dr->dr_hnd);
567 566 }
568 567
569 568 int
570 569 rt2560_alloc_tx_ring(struct rt2560_softc *sc, struct rt2560_tx_ring *ring,
571 570 int count)
572 571 {
573 572 int i, err;
574 573 int size;
575 574
576 575 ring->count = count;
577 576 ring->queued = 0;
578 577 ring->cur = ring->next = 0;
579 578 ring->cur_encrypt = ring->next_encrypt = 0;
580 579
581 580 ring->data = kmem_zalloc(count * (sizeof (struct rt2560_tx_data)),
582 581 KM_SLEEP);
583 582 ring->dr_txbuf = kmem_zalloc(count * (sizeof (struct dma_region)),
584 583 KM_SLEEP);
585 584
586 585 err = ral_dma_region_alloc(sc, &ring->dr_desc,
587 586 count * (sizeof (struct rt2560_tx_desc)),
588 587 DDI_DMA_CONSISTENT, DDI_DMA_RDWR | DDI_DMA_CONSISTENT);
589 588
590 589 if (err != DDI_SUCCESS)
591 590 goto fail1;
592 591
593 592 size = roundup(RAL_TXBUF_SIZE, sc->sc_cachelsz);
594 593 for (i = 0; i < count; i++) {
595 594 err = ral_dma_region_alloc(sc, &ring->dr_txbuf[i], size,
596 595 DDI_DMA_STREAMING, DDI_DMA_WRITE | DDI_DMA_STREAMING);
597 596 if (err != DDI_SUCCESS) {
598 597 while (i >= 0) {
599 598 ral_dma_region_free(sc, &ring->dr_txbuf[i]);
600 599 i--;
601 600 }
602 601 goto fail2;
603 602 }
604 603 }
605 604
606 605 ring->physaddr = LE_32(ring->dr_desc.dr_pbase);
607 606 ring->desc = (struct rt2560_tx_desc *)ring->dr_desc.dr_base;
608 607
609 608 for (i = 0; i < count; i++) {
610 609 ring->desc[i].physaddr = LE_32(ring->dr_txbuf[i].dr_pbase);
611 610 ring->data[i].buf = ring->dr_txbuf[i].dr_base;
612 611 }
613 612
614 613 return (DDI_SUCCESS);
615 614 fail2:
616 615 ral_dma_region_free(sc, &ring->dr_desc);
617 616 fail1:
618 617 return (err);
619 618 }
620 619
621 620 /* ARGSUSED */
622 621 void
623 622 rt2560_reset_tx_ring(struct rt2560_softc *sc, struct rt2560_tx_ring *ring)
624 623 {
625 624 struct rt2560_tx_desc *desc;
626 625 struct rt2560_tx_data *data;
627 626 int i;
628 627
629 628 for (i = 0; i < ring->count; i++) {
630 629 desc = &ring->desc[i];
631 630 data = &ring->data[i];
632 631
633 632 if (data->ni != NULL) {
634 633 ieee80211_free_node(data->ni);
635 634 data->ni = NULL;
636 635 }
637 636
638 637 desc->flags = 0;
639 638 }
640 639
641 640 (void) ddi_dma_sync(ring->dr_desc.dr_hnd, 0,
642 641 ring->count * sizeof (struct rt2560_tx_desc), DDI_DMA_SYNC_FORDEV);
643 642
644 643 ring->queued = 0;
645 644 ring->cur = ring->next = 0;
646 645 ring->cur_encrypt = ring->next_encrypt = 0;
647 646 }
648 647
649 648 void
650 649 rt2560_free_tx_ring(struct rt2560_softc *sc, struct rt2560_tx_ring *ring)
651 650 {
652 651 struct rt2560_tx_data *data;
653 652 int i;
654 653
655 654 ral_dma_region_free(sc, &ring->dr_desc);
656 655 /* tx buf */
657 656 for (i = 0; i < ring->count; i++) {
658 657 data = &ring->data[i];
659 658 if (data->ni != NULL) {
660 659 ieee80211_free_node(data->ni);
661 660 data->ni = NULL;
662 661 }
663 662
664 663 ral_dma_region_free(sc, &ring->dr_txbuf[i]);
665 664 }
666 665
667 666 kmem_free(ring->data, ring->count * (sizeof (struct rt2560_tx_data)));
668 667 kmem_free(ring->dr_txbuf, ring->count * (sizeof (struct dma_region)));
669 668 }
670 669
671 670 void
672 671 rt2560_ring_hwsetup(struct rt2560_softc *sc)
673 672 {
674 673 uint32_t tmp;
675 674
676 675 /* setup tx rings */
677 676 tmp = ((uint32_t)RT2560_PRIO_RING_COUNT << 24) |
678 677 RT2560_ATIM_RING_COUNT << 16 |
679 678 RT2560_TX_RING_COUNT << 8 |
680 679 RT2560_TX_DESC_SIZE;
681 680
682 681 /* rings must be initialized in this exact order */
683 682 RAL_WRITE(sc, RT2560_TXCSR2, tmp);
684 683 RAL_WRITE(sc, RT2560_TXCSR3, sc->txq.physaddr);
685 684 RAL_WRITE(sc, RT2560_TXCSR5, sc->prioq.physaddr);
686 685
687 686 /* setup rx ring */
688 687 tmp = RT2560_RX_RING_COUNT << 8 | RT2560_RX_DESC_SIZE;
689 688
690 689 RAL_WRITE(sc, RT2560_RXCSR1, tmp);
691 690 RAL_WRITE(sc, RT2560_RXCSR2, sc->rxq.physaddr);
692 691 }
693 692
694 693 int
695 694 rt2560_alloc_rx_ring(struct rt2560_softc *sc, struct rt2560_rx_ring *ring,
696 695 int count)
697 696 {
698 697 struct rt2560_rx_desc *desc;
699 698 struct rt2560_rx_data *data;
700 699 int i, err;
701 700 int size;
702 701
703 702 ring->count = count;
704 703 ring->cur = ring->next = 0;
705 704 ring->cur_decrypt = 0;
706 705
707 706 ring->data = kmem_zalloc(count * (sizeof (struct rt2560_rx_data)),
708 707 KM_SLEEP);
709 708 ring->dr_rxbuf = kmem_zalloc(count * (sizeof (struct dma_region)),
710 709 KM_SLEEP);
711 710
712 711 err = ral_dma_region_alloc(sc, &ring->dr_desc,
713 712 count * (sizeof (struct rt2560_rx_desc)),
714 713 DDI_DMA_CONSISTENT, DDI_DMA_RDWR | DDI_DMA_CONSISTENT);
715 714
716 715 if (err != DDI_SUCCESS)
717 716 goto fail1;
718 717
719 718 size = roundup(RAL_RXBUF_SIZE, sc->sc_cachelsz);
720 719 for (i = 0; i < count; i++) {
721 720 err = ral_dma_region_alloc(sc, &ring->dr_rxbuf[i], size,
722 721 DDI_DMA_STREAMING, DDI_DMA_READ | DDI_DMA_STREAMING);
723 722 if (err != DDI_SUCCESS) {
724 723 while (i >= 0) {
725 724 ral_dma_region_free(sc, &ring->dr_rxbuf[i]);
726 725 i--;
727 726 }
728 727 goto fail2;
729 728 }
730 729 }
731 730
732 731 ring->physaddr = ring->dr_desc.dr_pbase;
733 732 ring->desc = (struct rt2560_rx_desc *)ring->dr_desc.dr_base;
734 733
735 734 for (i = 0; i < count; i++) {
736 735 desc = &ring->desc[i];
737 736 data = &ring->data[i];
738 737
739 738 desc->physaddr = LE_32(ring->dr_rxbuf[i].dr_pbase);
740 739 desc->flags = LE_32(RT2560_RX_BUSY);
741 740
742 741 data->buf = ring->dr_rxbuf[i].dr_base;
743 742 }
744 743
745 744 return (DDI_SUCCESS);
746 745 fail2:
747 746 ral_dma_region_free(sc, &ring->dr_desc);
748 747 fail1:
749 748 return (err);
750 749 }
751 750
752 751 /* ARGSUSED */
753 752 static void
754 753 rt2560_reset_rx_ring(struct rt2560_softc *sc, struct rt2560_rx_ring *ring)
755 754 {
756 755 int i;
757 756
758 757 for (i = 0; i < ring->count; i++) {
759 758 ring->desc[i].flags = LE_32(RT2560_RX_BUSY);
760 759 ring->data[i].drop = 0;
761 760 }
762 761
763 762 (void) ddi_dma_sync(ring->dr_desc.dr_hnd, 0,
764 763 ring->count * sizeof (struct rt2560_rx_desc),
765 764 DDI_DMA_SYNC_FORKERNEL);
766 765
767 766 ring->cur = ring->next = 0;
768 767 ring->cur_decrypt = 0;
769 768 }
770 769
771 770 static void
772 771 rt2560_free_rx_ring(struct rt2560_softc *sc, struct rt2560_rx_ring *ring)
773 772 {
774 773 int i;
775 774
776 775 ral_dma_region_free(sc, &ring->dr_desc);
777 776 /* rx buf */
778 777 for (i = 0; i < ring->count; i++)
779 778 ral_dma_region_free(sc, &ring->dr_rxbuf[i]);
780 779
781 780 kmem_free(ring->data, ring->count * (sizeof (struct rt2560_rx_data)));
782 781 kmem_free(ring->dr_rxbuf, ring->count * (sizeof (struct dma_region)));
783 782 }
784 783
785 784 /* ARGSUSED */
786 785 static struct ieee80211_node *
787 786 rt2560_node_alloc(ieee80211com_t *ic)
788 787 {
789 788 struct rt2560_node *rn;
790 789
791 790 rn = kmem_zalloc(sizeof (struct rt2560_node), KM_SLEEP);
792 791 return ((rn != NULL) ? &rn->ni : NULL);
793 792 }
794 793
795 794 static void
796 795 rt2560_node_free(struct ieee80211_node *in)
797 796 {
798 797 ieee80211com_t *ic = in->in_ic;
799 798
800 799 ic->ic_node_cleanup(in);
801 800 if (in->in_wpa_ie != NULL)
802 801 ieee80211_free(in->in_wpa_ie);
803 802 kmem_free(in, sizeof (struct rt2560_node));
804 803 }
805 804
806 805 /*
807 806 * This function is called periodically (every 200ms) during scanning to
808 807 * switch from one channel to another.
809 808 */
810 809 static void
811 810 rt2560_next_scan(void *arg)
812 811 {
813 812 struct rt2560_softc *sc = arg;
814 813 struct ieee80211com *ic = &sc->sc_ic;
815 814
816 815 if (ic->ic_state == IEEE80211_S_SCAN)
817 816 (void) ieee80211_next_scan(ic);
818 817 }
819 818
820 819 /*
821 820 * This function is called for each node present in the node station table.
822 821 */
823 822 /* ARGSUSED */
824 823 static void
825 824 rt2560_iter_func(void *arg, struct ieee80211_node *ni)
826 825 {
827 826 struct rt2560_node *rn = (struct rt2560_node *)ni;
828 827
829 828 ral_rssadapt_updatestats(&rn->rssadapt);
830 829 }
831 830
832 831 /*
833 832 * This function is called periodically (every 100ms) in RUN state to update
834 833 * the rate adaptation statistics.
835 834 */
836 835 static void
837 836 rt2560_update_rssadapt(void *arg)
838 837 {
839 838 struct rt2560_softc *sc = arg;
840 839 struct ieee80211com *ic = &sc->sc_ic;
841 840
842 841 ieee80211_iterate_nodes(&ic->ic_sta, rt2560_iter_func, arg);
843 842 sc->sc_rssadapt_id = timeout(rt2560_update_rssadapt, (void *)sc,
844 843 drv_usectohz(100 * 1000));
845 844 }
846 845
847 846 static void
848 847 rt2560_statedog(void *arg)
849 848 {
850 849 struct rt2560_softc *sc = arg;
851 850 struct ieee80211com *ic = &sc->sc_ic;
852 851 enum ieee80211_state state;
853 852
854 853 RAL_LOCK(sc);
855 854
856 855 sc->sc_state_id = 0;
857 856 state = ic->ic_state;
858 857 ic->ic_state = sc->sc_ostate;
859 858
860 859 RAL_UNLOCK(sc);
861 860
862 861 ieee80211_new_state(ic, state, -1);
863 862
864 863 }
865 864
866 865 static int
867 866 rt2560_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg)
868 867 {
869 868 struct rt2560_softc *sc = (struct rt2560_softc *)ic;
870 869 enum ieee80211_state ostate;
871 870 struct ieee80211_node *ni;
872 871 int err;
873 872
874 873 RAL_LOCK(sc);
875 874
876 875 ostate = ic->ic_state;
877 876 sc->sc_ostate = ostate;
878 877
879 878 if (sc->sc_scan_id != 0) {
880 879 (void) untimeout(sc->sc_scan_id);
881 880 sc->sc_scan_id = 0;
882 881 }
883 882
884 883 if (sc->sc_rssadapt_id != 0) {
885 884 (void) untimeout(sc->sc_rssadapt_id);
886 885 sc->sc_rssadapt_id = 0;
887 886 }
888 887
889 888 if (sc->sc_state_id != 0) {
890 889 (void) untimeout(sc->sc_state_id);
891 890 sc->sc_state_id = 0;
892 891 }
893 892
894 893 switch (nstate) {
895 894 case IEEE80211_S_INIT:
896 895 if (ostate == IEEE80211_S_RUN) {
897 896 /* abort TSF synchronization */
898 897 RAL_WRITE(sc, RT2560_CSR14, 0);
899 898 /* turn association led off */
900 899 rt2560_update_led(sc, 0, 0);
901 900 }
902 901 break;
903 902
904 903 case IEEE80211_S_SCAN:
905 904 rt2560_set_chan(sc, ic->ic_curchan);
906 905 sc->sc_scan_id = timeout(rt2560_next_scan, (void *)sc,
907 906 drv_usectohz(sc->dwelltime * 1000));
908 907 break;
909 908
910 909 case IEEE80211_S_AUTH:
911 910 rt2560_set_chan(sc, ic->ic_curchan);
912 911 break;
913 912
914 913 case IEEE80211_S_ASSOC:
915 914 rt2560_set_chan(sc, ic->ic_curchan);
916 915
917 916 drv_usecwait(10 * 1000); /* dlink */
918 917 sc->sc_state_id = timeout(rt2560_statedog, (void *)sc,
919 918 drv_usectohz(300 * 1000)); /* ap7-3 */
920 919 break;
921 920
922 921 case IEEE80211_S_RUN:
923 922 rt2560_set_chan(sc, ic->ic_curchan);
924 923
925 924 ni = ic->ic_bss;
926 925
927 926 if (ic->ic_opmode != IEEE80211_M_MONITOR) {
928 927 rt2560_update_plcp(sc);
929 928 rt2560_set_basicrates(sc);
930 929 rt2560_set_bssid(sc, ni->in_bssid);
931 930 }
932 931
933 932 /* turn assocation led on */
934 933 rt2560_update_led(sc, 1, 0);
935 934 if (ic->ic_opmode != IEEE80211_M_MONITOR) {
936 935 sc->sc_rssadapt_id = timeout(rt2560_update_rssadapt,
937 936 (void *)sc, drv_usectohz(100 * 1000));
938 937 rt2560_enable_tsf_sync(sc);
939 938 }
940 939 break;
941 940 }
942 941
943 942 RAL_UNLOCK(sc);
944 943
945 944 err = sc->sc_newstate(ic, nstate, arg);
946 945 /*
947 946 * Finally, start any timers.
948 947 */
949 948 if (nstate == IEEE80211_S_RUN)
950 949 ieee80211_start_watchdog(ic, 1);
951 950
952 951 return (err);
953 952 }
954 953
955 954 /*
956 955 * Read 16 bits at address 'addr' from the serial EEPROM (either 93C46 or
957 956 * 93C66).
958 957 */
959 958 static uint16_t
960 959 rt2560_eeprom_read(struct rt2560_softc *sc, uint8_t addr)
961 960 {
962 961 uint32_t tmp;
963 962 uint16_t val;
964 963 int n;
965 964
966 965 /* clock C once before the first command */
967 966 RT2560_EEPROM_CTL(sc, 0);
968 967
969 968 RT2560_EEPROM_CTL(sc, RT2560_S);
970 969 RT2560_EEPROM_CTL(sc, RT2560_S | RT2560_C);
971 970 RT2560_EEPROM_CTL(sc, RT2560_S);
972 971
973 972 /* write start bit (1) */
974 973 RT2560_EEPROM_CTL(sc, RT2560_S | RT2560_D);
975 974 RT2560_EEPROM_CTL(sc, RT2560_S | RT2560_D | RT2560_C);
976 975
977 976 /* write READ opcode (10) */
978 977 RT2560_EEPROM_CTL(sc, RT2560_S | RT2560_D);
979 978 RT2560_EEPROM_CTL(sc, RT2560_S | RT2560_D | RT2560_C);
980 979 RT2560_EEPROM_CTL(sc, RT2560_S);
981 980 RT2560_EEPROM_CTL(sc, RT2560_S | RT2560_C);
982 981
983 982 /* write address (A5-A0 or A7-A0) */
984 983 n = (RAL_READ(sc, RT2560_CSR21) & RT2560_93C46) ? 5 : 7;
985 984 for (; n >= 0; n--) {
986 985 RT2560_EEPROM_CTL(sc, RT2560_S |
987 986 (((addr >> n) & 1) << RT2560_SHIFT_D));
988 987 RT2560_EEPROM_CTL(sc, RT2560_S |
989 988 (((addr >> n) & 1) << RT2560_SHIFT_D) | RT2560_C);
990 989 }
991 990
992 991 RT2560_EEPROM_CTL(sc, RT2560_S);
993 992
994 993 /* read data Q15-Q0 */
995 994 val = 0;
996 995 for (n = 15; n >= 0; n--) {
997 996 RT2560_EEPROM_CTL(sc, RT2560_S | RT2560_C);
998 997 tmp = RAL_READ(sc, RT2560_CSR21);
999 998 val |= ((tmp & RT2560_Q) >> RT2560_SHIFT_Q) << n;
1000 999 RT2560_EEPROM_CTL(sc, RT2560_S);
1001 1000 }
1002 1001
1003 1002 RT2560_EEPROM_CTL(sc, 0);
1004 1003
1005 1004 /* clear Chip Select and clock C */
1006 1005 RT2560_EEPROM_CTL(sc, RT2560_S);
1007 1006 RT2560_EEPROM_CTL(sc, 0);
1008 1007 RT2560_EEPROM_CTL(sc, RT2560_C);
1009 1008
1010 1009 return (val);
1011 1010 }
1012 1011
1013 1012 static void
1014 1013 rt2560_tx_intr(struct rt2560_softc *sc)
1015 1014 {
1016 1015 struct ieee80211com *ic = &sc->sc_ic;
1017 1016 struct rt2560_tx_desc *desc;
1018 1017 struct rt2560_tx_data *data;
1019 1018 struct rt2560_node *rn;
1020 1019
1021 1020 struct dma_region *dr;
1022 1021 int count;
1023 1022
1024 1023 dr = &sc->txq.dr_desc;
1025 1024 count = sc->txq.count;
1026 1025
1027 1026 (void) ddi_dma_sync(dr->dr_hnd, 0, count * RT2560_TX_DESC_SIZE,
1028 1027 DDI_DMA_SYNC_FORKERNEL);
1029 1028
1030 1029 mutex_enter(&sc->txq.tx_lock);
1031 1030
1032 1031 for (;;) {
1033 1032 desc = &sc->txq.desc[sc->txq.next];
1034 1033 data = &sc->txq.data[sc->txq.next];
1035 1034
1036 1035 if ((LE_32(desc->flags) & RT2560_TX_BUSY) ||
1037 1036 (LE_32(desc->flags) & RT2560_TX_CIPHER_BUSY) ||
1038 1037 !(LE_32(desc->flags) & RT2560_TX_VALID))
1039 1038 break;
1040 1039
1041 1040 rn = (struct rt2560_node *)data->ni;
1042 1041
1043 1042 switch (LE_32(desc->flags) & RT2560_TX_RESULT_MASK) {
1044 1043 case RT2560_TX_SUCCESS:
1045 1044 ral_debug(RAL_DBG_INTR, "data frame sent success\n");
1046 1045 if (data->id.id_node != NULL) {
1047 1046 ral_rssadapt_raise_rate(ic, &rn->rssadapt,
1048 1047 &data->id);
1049 1048 }
1050 1049 break;
1051 1050
1052 1051 case RT2560_TX_SUCCESS_RETRY:
1053 1052 ral_debug(RAL_DBG_INTR,
1054 1053 "data frame sent after %u retries\n",
1055 1054 (LE_32(desc->flags) >> 5) & 0x7);
1056 1055 sc->sc_tx_retries++;
1057 1056 break;
1058 1057
1059 1058 case RT2560_TX_FAIL_RETRY:
1060 1059 ral_debug(RAL_DBG_INTR,
1061 1060 "sending data frame failed (too much retries)\n");
1062 1061 if (data->id.id_node != NULL) {
1063 1062 ral_rssadapt_lower_rate(ic, data->ni,
1064 1063 &rn->rssadapt, &data->id);
1065 1064 }
1066 1065 break;
1067 1066
1068 1067 case RT2560_TX_FAIL_INVALID:
1069 1068 case RT2560_TX_FAIL_OTHER:
1070 1069 default:
1071 1070 ral_debug(RAL_DBG_INTR, "sending data frame failed "
1072 1071 "0x%08x\n", LE_32(desc->flags));
1073 1072 break;
1074 1073 }
1075 1074
1076 1075 ieee80211_free_node(data->ni);
1077 1076 data->ni = NULL;
1078 1077
1079 1078 /* descriptor is no longer valid */
1080 1079 desc->flags &= ~LE_32(RT2560_TX_VALID);
1081 1080
1082 1081 ral_debug(RAL_DBG_INTR, "tx done idx=%u\n", sc->txq.next);
1083 1082
1084 1083 sc->txq.queued--;
1085 1084 sc->txq.next = (sc->txq.next + 1) % RT2560_TX_RING_COUNT;
1086 1085
1087 1086 if (sc->sc_need_sched &&
1088 1087 sc->txq.queued < (RT2560_TX_RING_COUNT - 32)) {
1089 1088 sc->sc_need_sched = 0;
1090 1089 mac_tx_update(ic->ic_mach);
1091 1090 }
1092 1091 }
1093 1092
1094 1093 (void) ddi_dma_sync(dr->dr_hnd, 0, count * RT2560_TX_DESC_SIZE,
1095 1094 DDI_DMA_SYNC_FORDEV);
1096 1095
1097 1096 sc->sc_tx_timer = 0;
1098 1097 mutex_exit(&sc->txq.tx_lock);
1099 1098 }
1100 1099
1101 1100 static void
1102 1101 rt2560_prio_intr(struct rt2560_softc *sc)
1103 1102 {
1104 1103 struct rt2560_tx_desc *desc;
1105 1104 struct rt2560_tx_data *data;
1106 1105
1107 1106 struct dma_region *dr;
1108 1107 int count;
1109 1108
1110 1109 dr = &sc->prioq.dr_desc;
1111 1110 count = sc->prioq.count;
1112 1111
1113 1112 (void) ddi_dma_sync(dr->dr_hnd, 0, count * RT2560_TX_DESC_SIZE,
1114 1113 DDI_DMA_SYNC_FORKERNEL);
1115 1114
1116 1115 mutex_enter(&sc->prioq.tx_lock);
1117 1116
1118 1117 for (;;) {
1119 1118 desc = &sc->prioq.desc[sc->prioq.next];
1120 1119 data = &sc->prioq.data[sc->prioq.next];
1121 1120
1122 1121 if ((LE_32(desc->flags) & RT2560_TX_BUSY) ||
1123 1122 !(LE_32(desc->flags) & RT2560_TX_VALID))
1124 1123 break;
1125 1124
1126 1125 switch (LE_32(desc->flags) & RT2560_TX_RESULT_MASK) {
1127 1126 case RT2560_TX_SUCCESS:
1128 1127 ral_debug(RAL_DBG_INTR, "mgt frame sent success\n");
1129 1128 break;
1130 1129
1131 1130 case RT2560_TX_SUCCESS_RETRY:
1132 1131 ral_debug(RAL_DBG_INTR,
1133 1132 "mgt frame sent after %u retries\n",
1134 1133 (LE_32(desc->flags) >> 5) & 0x7);
1135 1134 break;
1136 1135
1137 1136 case RT2560_TX_FAIL_RETRY:
1138 1137 ral_debug(RAL_DBG_INTR,
1139 1138 "sending mgt frame failed (too much " "retries)\n");
1140 1139 break;
1141 1140
1142 1141 case RT2560_TX_FAIL_INVALID:
1143 1142 case RT2560_TX_FAIL_OTHER:
1144 1143 default:
1145 1144 ral_debug(RAL_DBG_INTR, "sending mgt frame failed "
1146 1145 "0x%08x\n", LE_32(desc->flags));
1147 1146 }
1148 1147
1149 1148 ieee80211_free_node(data->ni);
1150 1149 data->ni = NULL;
1151 1150
1152 1151 /* descriptor is no longer valid */
1153 1152 desc->flags &= ~LE_32(RT2560_TX_VALID);
1154 1153
1155 1154 ral_debug(RAL_DBG_INTR, "prio done idx=%u\n", sc->prioq.next);
1156 1155
1157 1156 sc->prioq.queued--;
1158 1157 sc->prioq.next = (sc->prioq.next + 1) % RT2560_PRIO_RING_COUNT;
1159 1158 }
1160 1159
1161 1160 (void) ddi_dma_sync(dr->dr_hnd, 0, count * RT2560_TX_DESC_SIZE,
1162 1161 DDI_DMA_SYNC_FORDEV);
1163 1162
1164 1163 sc->sc_tx_timer = 0;
1165 1164 mutex_exit(&sc->prioq.tx_lock);
1166 1165 }
1167 1166
1168 1167 /*
1169 1168 * Some frames were received. Pass them to the hardware cipher engine before
1170 1169 * sending them to the 802.11 layer.
1171 1170 */
1172 1171 void
1173 1172 rt2560_rx_intr(struct rt2560_softc *sc)
1174 1173 {
1175 1174 struct ieee80211com *ic = &sc->sc_ic;
1176 1175 struct rt2560_rx_desc *desc;
1177 1176 struct rt2560_rx_data *data;
1178 1177 struct ieee80211_frame *wh;
1179 1178 struct ieee80211_node *ni;
1180 1179 struct rt2560_node *rn;
1181 1180
1182 1181 mblk_t *m;
1183 1182 uint32_t len;
1184 1183 char *rxbuf;
1185 1184
1186 1185 struct dma_region *dr, *dr_bf;
1187 1186 int count;
1188 1187
1189 1188 dr = &sc->rxq.dr_desc;
1190 1189 count = sc->rxq.count;
1191 1190
1192 1191 mutex_enter(&sc->rxq.rx_lock);
1193 1192
1194 1193 (void) ddi_dma_sync(dr->dr_hnd, 0, count * RT2560_RX_DESC_SIZE,
1195 1194 DDI_DMA_SYNC_FORKERNEL);
1196 1195
1197 1196 for (;;) {
1198 1197 desc = &sc->rxq.desc[sc->rxq.cur];
1199 1198 data = &sc->rxq.data[sc->rxq.cur];
1200 1199
1201 1200 if ((LE_32(desc->flags) & RT2560_RX_BUSY) ||
1202 1201 (LE_32(desc->flags) & RT2560_RX_CIPHER_BUSY))
1203 1202 break;
1204 1203
1205 1204 data->drop = 0;
1206 1205
1207 1206 if ((LE_32(desc->flags) & RT2560_RX_PHY_ERROR) ||
1208 1207 (LE_32(desc->flags) & RT2560_RX_CRC_ERROR)) {
1209 1208 /*
1210 1209 * This should not happen since we did not request
1211 1210 * to receive those frames when we filled RXCSR0.
1212 1211 */
1213 1212 ral_debug(RAL_DBG_RX, "PHY or CRC error flags 0x%08x\n",
1214 1213 LE_32(desc->flags));
1215 1214 data->drop = 1;
1216 1215 }
1217 1216
1218 1217 if (((LE_32(desc->flags) >> 16) & 0xfff) > RAL_RXBUF_SIZE) {
1219 1218 ral_debug(RAL_DBG_RX, "bad length\n");
1220 1219 data->drop = 1;
1221 1220 }
1222 1221
1223 1222 if (data->drop) {
1224 1223 sc->sc_rx_err++;
1225 1224 goto skip;
1226 1225 }
1227 1226
1228 1227 rxbuf = data->buf;
1229 1228 len = (LE_32(desc->flags) >> 16) & 0xfff;
1230 1229
1231 1230 if ((len < sizeof (struct ieee80211_frame_min)) ||
1232 1231 (len > RAL_RXBUF_SIZE)) {
1233 1232 ral_debug(RAL_DBG_RX, "bad frame length=%u\n", len);
1234 1233 sc->sc_rx_err++;
1235 1234 goto skip;
1236 1235 }
1237 1236
1238 1237 if ((m = allocb(len, BPRI_MED)) == NULL) {
1239 1238 ral_debug(RAL_DBG_RX, "rt2560_rx_intr():"
1240 1239 " allocate mblk failed.\n");
1241 1240 sc->sc_rx_nobuf++;
1242 1241 goto skip;
1243 1242 }
1244 1243
1245 1244 dr_bf = &sc->rxq.dr_rxbuf[sc->rxq.cur];
1246 1245 (void) ddi_dma_sync(dr_bf->dr_hnd, 0, dr_bf->dr_size,
1247 1246 DDI_DMA_SYNC_FORCPU);
1248 1247
1249 1248 bcopy(rxbuf, m->b_rptr, len);
1250 1249 m->b_wptr += len;
1251 1250
1252 1251 wh = (struct ieee80211_frame *)m->b_rptr;
1253 1252 ni = ieee80211_find_rxnode(ic, wh);
1254 1253
1255 1254 /* give rssi to the rate adatation algorithm */
1256 1255 rn = (struct rt2560_node *)ni;
1257 1256 ral_rssadapt_input(ic, ni, &rn->rssadapt, desc->rssi);
1258 1257
1259 1258 /* send the frame to the 802.11 layer */
1260 1259 (void) ieee80211_input(ic, m, ni, desc->rssi, 0);
1261 1260
1262 1261 /* node is no longer needed */
1263 1262 ieee80211_free_node(ni);
1264 1263
1265 1264 skip: desc->flags = LE_32(RT2560_RX_BUSY);
1266 1265 ral_debug(RAL_DBG_RX, "rx done idx=%u\n", sc->rxq.cur);
1267 1266
1268 1267 sc->rxq.cur = (sc->rxq.cur + 1) % RT2560_RX_RING_COUNT;
1269 1268 }
1270 1269 mutex_exit(&sc->rxq.rx_lock);
1271 1270
1272 1271 (void) ddi_dma_sync(dr->dr_hnd, 0, count * RT2560_TX_DESC_SIZE,
1273 1272 DDI_DMA_SYNC_FORDEV);
1274 1273 }
1275 1274
1276 1275 uint_t
1277 1276 ral_softint_handler(caddr_t data)
1278 1277 {
1279 1278 /* LINTED E_BAD_PTR_CAST_ALIGN */
1280 1279 struct rt2560_softc *sc = (struct rt2560_softc *)data;
1281 1280
1282 1281 /*
1283 1282 * Check if the soft interrupt is triggered by another
1284 1283 * driver at the same level.
1285 1284 */
1286 1285 RAL_LOCK(sc);
1287 1286 if (sc->sc_rx_pend) {
1288 1287 sc->sc_rx_pend = 0;
1289 1288 RAL_UNLOCK(sc);
1290 1289 rt2560_rx_intr(sc);
1291 1290 return (DDI_INTR_CLAIMED);
1292 1291 }
1293 1292 RAL_UNLOCK(sc);
1294 1293 return (DDI_INTR_UNCLAIMED);
1295 1294 }
1296 1295
1297 1296 /*
1298 1297 * Return the expected ack rate for a frame transmitted at rate `rate'.
1299 1298 * XXX: this should depend on the destination node basic rate set.
1300 1299 */
1301 1300 static int
1302 1301 rt2560_ack_rate(struct ieee80211com *ic, int rate)
1303 1302 {
1304 1303 switch (rate) {
1305 1304 /* CCK rates */
1306 1305 case 2:
1307 1306 return (2);
1308 1307 case 4:
1309 1308 case 11:
1310 1309 case 22:
1311 1310 return ((ic->ic_curmode == IEEE80211_MODE_11B) ? 4 : rate);
1312 1311
1313 1312 /* OFDM rates */
1314 1313 case 12:
1315 1314 case 18:
1316 1315 return (12);
1317 1316 case 24:
1318 1317 case 36:
1319 1318 return (24);
1320 1319 case 48:
1321 1320 case 72:
1322 1321 case 96:
1323 1322 case 108:
1324 1323 return (48);
1325 1324 }
1326 1325
1327 1326 /* default to 1Mbps */
1328 1327 return (2);
1329 1328 }
1330 1329
1331 1330 /*
1332 1331 * Compute the duration (in us) needed to transmit `len' bytes at rate `rate'.
1333 1332 * The function automatically determines the operating mode depending on the
1334 1333 * given rate. `flags' indicates whether short preamble is in use or not.
1335 1334 */
1336 1335 static uint16_t
1337 1336 rt2560_txtime(int len, int rate, uint32_t flags)
1338 1337 {
1339 1338 uint16_t txtime;
1340 1339
1341 1340 if (RAL_RATE_IS_OFDM(rate)) {
1342 1341 /* IEEE Std 802.11a-1999, pp. 37 */
1343 1342 txtime = (8 + 4 * len + 3 + rate - 1) / rate;
1344 1343 txtime = 16 + 4 + 4 * txtime + 6;
1345 1344 } else {
1346 1345 /* IEEE Std 802.11b-1999, pp. 28 */
1347 1346 txtime = (16 * len + rate - 1) / rate;
1348 1347 if (rate != 2 && (flags & IEEE80211_F_SHPREAMBLE))
1349 1348 txtime += 72 + 24;
1350 1349 else
1351 1350 txtime += 144 + 48;
1352 1351 }
1353 1352
1354 1353 return (txtime);
1355 1354 }
1356 1355
1357 1356 static uint8_t
1358 1357 rt2560_plcp_signal(int rate)
1359 1358 {
1360 1359 switch (rate) {
1361 1360 /* CCK rates (returned values are device-dependent) */
1362 1361 case 2: return (0x0);
1363 1362 case 4: return (0x1);
1364 1363 case 11: return (0x2);
1365 1364 case 22: return (0x3);
1366 1365
1367 1366 /* OFDM rates (cf IEEE Std 802.11a-1999, pp. 14 Table 80) */
1368 1367 case 12: return (0xb);
1369 1368 case 18: return (0xf);
1370 1369 case 24: return (0xa);
1371 1370 case 36: return (0xe);
1372 1371 case 48: return (0x9);
1373 1372 case 72: return (0xd);
1374 1373 case 96: return (0x8);
1375 1374 case 108: return (0xc);
1376 1375
1377 1376 /* unsupported rates (should not get there) */
1378 1377 default: return (0xff);
1379 1378 }
1380 1379 }
1381 1380
1382 1381 void
1383 1382 rt2560_setup_tx_desc(struct rt2560_softc *sc, struct rt2560_tx_desc *desc,
1384 1383 uint32_t flags, int len, int rate, int encrypt)
1385 1384 {
1386 1385 struct ieee80211com *ic = &sc->sc_ic;
1387 1386 uint16_t plcp_length;
1388 1387 int remainder;
1389 1388
1390 1389 desc->flags = LE_32(flags);
1391 1390 desc->flags |= LE_32(len << 16);
1392 1391 desc->flags |= encrypt ? LE_32(RT2560_TX_CIPHER_BUSY) :
1393 1392 LE_32(RT2560_TX_BUSY | RT2560_TX_VALID);
1394 1393
1395 1394 desc->wme = LE_16(
1396 1395 RT2560_AIFSN(2) |
1397 1396 RT2560_LOGCWMIN(3) |
1398 1397 RT2560_LOGCWMAX(8));
1399 1398
1400 1399 /* setup PLCP fields */
1401 1400 desc->plcp_signal = rt2560_plcp_signal(rate);
1402 1401 desc->plcp_service = 4;
1403 1402
1404 1403 len += IEEE80211_CRC_LEN;
1405 1404 if (RAL_RATE_IS_OFDM(rate)) {
1406 1405 desc->flags |= LE_32(RT2560_TX_OFDM);
1407 1406
1408 1407 plcp_length = len & 0xfff;
1409 1408 desc->plcp_length_hi = plcp_length >> 6;
1410 1409 desc->plcp_length_lo = plcp_length & 0x3f;
1411 1410 } else {
1412 1411 plcp_length = (16 * len + rate - 1) / rate;
1413 1412 if (rate == 22) {
1414 1413 remainder = (16 * len) % 22;
1415 1414 if (remainder != 0 && remainder < 7)
1416 1415 desc->plcp_service |= RT2560_PLCP_LENGEXT;
1417 1416 }
1418 1417 desc->plcp_length_hi = plcp_length >> 8;
1419 1418 desc->plcp_length_lo = plcp_length & 0xff;
1420 1419
1421 1420 if (rate != 2 && (ic->ic_flags & IEEE80211_F_SHPREAMBLE))
1422 1421 desc->plcp_signal |= 0x08;
1423 1422 }
1424 1423 }
1425 1424
1426 1425 /* ARGSUSED */
1427 1426 int
1428 1427 rt2560_mgmt_send(ieee80211com_t *ic, mblk_t *mp, uint8_t type)
1429 1428 {
1430 1429 struct rt2560_softc *sc = (struct rt2560_softc *)ic;
1431 1430 struct rt2560_tx_desc *desc;
1432 1431 struct rt2560_tx_data *data;
1433 1432 struct ieee80211_frame *wh;
1434 1433 uint16_t dur;
1435 1434 uint32_t flags = 0;
1436 1435 int rate, err = DDI_SUCCESS;
1437 1436
1438 1437 int off, pktlen, mblen;
1439 1438 caddr_t dest;
1440 1439 mblk_t *m, *m0;
1441 1440
1442 1441 struct dma_region *dr;
1443 1442 uint32_t idx;
1444 1443 struct ieee80211_node *ni;
1445 1444 struct ieee80211_key *k;
1446 1445
1447 1446 mutex_enter(&sc->prioq.tx_lock);
1448 1447
1449 1448 if (!RAL_IS_RUNNING(sc)) {
1450 1449 err = ENXIO;
1451 1450 goto fail1;
1452 1451 }
1453 1452
1454 1453 if (sc->prioq.queued >= RT2560_PRIO_RING_COUNT) {
1455 1454 err = ENOMEM;
1456 1455 sc->sc_tx_nobuf++;
1457 1456 goto fail1;
1458 1457 }
1459 1458
1460 1459 m = allocb(msgdsize(mp) + 32, BPRI_MED);
1461 1460 if (m == NULL) {
1462 1461 ral_debug(RAL_DBG_TX, "rt2560_mgmt_send: can't alloc mblk.\n");
1463 1462 err = DDI_FAILURE;
1464 1463 goto fail1;
1465 1464 }
1466 1465
1467 1466 for (off = 0, m0 = mp; m0 != NULL; m0 = m0->b_cont) {
1468 1467 mblen = MBLKL(m0);
1469 1468 (void) memcpy(m->b_rptr + off, m0->b_rptr, mblen);
1470 1469 off += mblen;
1471 1470 }
1472 1471 m->b_wptr += off;
1473 1472
1474 1473 wh = (struct ieee80211_frame *)m->b_rptr;
1475 1474 ni = ieee80211_find_txnode(ic, wh->i_addr1);
1476 1475
1477 1476 if (ni == NULL) {
1478 1477 err = DDI_FAILURE;
1479 1478 sc->sc_tx_err++;
1480 1479 goto fail2;
1481 1480 }
1482 1481
1483 1482 /* to support shared_key auth mode */
1484 1483 if (wh->i_fc[1] & IEEE80211_FC1_WEP) {
1485 1484 k = ieee80211_crypto_encap(ic, m);
1486 1485 if (k == NULL) {
1487 1486 err = DDI_FAILURE;
1488 1487 sc->sc_tx_err++;
1489 1488 goto fail3;
1490 1489 }
1491 1490 /* packet header may have moved, reset our local pointer */
1492 1491 wh = (struct ieee80211_frame *)m->b_rptr;
1493 1492 }
1494 1493
1495 1494 desc = &sc->prioq.desc[sc->prioq.cur];
1496 1495 data = &sc->prioq.data[sc->prioq.cur];
1497 1496
1498 1497 rate = IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan) ? 12 : 2;
1499 1498 data->ni = ieee80211_ref_node(ni);
1500 1499
1501 1500 pktlen = msgdsize(m);
1502 1501 dest = data->buf;
1503 1502 bcopy(m->b_rptr, dest, pktlen);
1504 1503
1505 1504 wh = (struct ieee80211_frame *)m->b_rptr;
1506 1505 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) {
1507 1506 flags |= RT2560_TX_ACK;
1508 1507
1509 1508 dur = rt2560_txtime(RAL_ACK_SIZE, rate, ic->ic_flags) +
1510 1509 RAL_SIFS;
1511 1510 /* LINTED E_BAD_PTR_CAST_ALIGN */
1512 1511 *(uint16_t *)wh->i_dur = LE_16(dur);
1513 1512
1514 1513 /* tell hardware to add timestamp for probe responses */
1515 1514 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) ==
1516 1515 IEEE80211_FC0_TYPE_MGT &&
1517 1516 (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) ==
1518 1517 IEEE80211_FC0_SUBTYPE_PROBE_RESP)
1519 1518 flags |= RT2560_TX_TIMESTAMP;
1520 1519 }
1521 1520
1522 1521 rt2560_setup_tx_desc(sc, desc, flags, pktlen, rate, 0);
1523 1522
1524 1523 idx = sc->prioq.cur;
1525 1524
1526 1525 dr = &sc->prioq.dr_txbuf[idx];
1527 1526 (void) ddi_dma_sync(dr->dr_hnd, 0, RAL_TXBUF_SIZE, DDI_DMA_SYNC_FORDEV);
1528 1527
1529 1528 dr = &sc->prioq.dr_desc;
1530 1529 (void) ddi_dma_sync(dr->dr_hnd, idx * RT2560_TX_DESC_SIZE,
1531 1530 RT2560_TX_DESC_SIZE, DDI_DMA_SYNC_FORDEV);
1532 1531
1533 1532 ral_debug(RAL_DBG_MGMT, "sending mgt frame len=%u idx=%u rate=%u\n",
1534 1533 pktlen, sc->prioq.cur, rate);
1535 1534
1536 1535 /* kick prio */
1537 1536 sc->prioq.queued++; /* IF > RT2560_PRIO_RING_COUNT? FULL */
1538 1537 sc->prioq.cur = (sc->prioq.cur + 1) % RT2560_PRIO_RING_COUNT;
1539 1538 RAL_WRITE(sc, RT2560_TXCSR0, RT2560_KICK_PRIO);
1540 1539
1541 1540 sc->sc_tx_timer = 5;
1542 1541
1543 1542 ic->ic_stats.is_tx_frags++;
1544 1543 ic->ic_stats.is_tx_bytes += pktlen;
1545 1544
1546 1545 fail3:
1547 1546 ieee80211_free_node(ni);
1548 1547 fail2:
1549 1548 freemsg(m);
1550 1549 fail1:
1551 1550 freemsg(mp);
1552 1551 mutex_exit(&sc->prioq.tx_lock);
1553 1552
1554 1553 return (err);
1555 1554 }
1556 1555
1557 1556 static int
1558 1557 rt2560_send(ieee80211com_t *ic, mblk_t *mp)
1559 1558 {
1560 1559 struct rt2560_softc *sc = (struct rt2560_softc *)ic;
1561 1560 struct rt2560_tx_desc *desc;
1562 1561 struct rt2560_tx_data *data;
1563 1562 struct rt2560_node *rn;
1564 1563 struct ieee80211_rateset *rs;
1565 1564 struct ieee80211_frame *wh;
1566 1565 struct ieee80211_key *k;
1567 1566 uint16_t dur;
1568 1567 uint32_t flags = 0;
1569 1568 int rate, err = DDI_SUCCESS;
1570 1569
1571 1570 struct ieee80211_node *ni;
1572 1571 mblk_t *m, *m0;
1573 1572 int off, mblen, pktlen;
1574 1573 caddr_t dest;
1575 1574
1576 1575 struct dma_region *dr;
1577 1576 uint32_t idx;
1578 1577
1579 1578 mutex_enter(&sc->txq.tx_lock);
1580 1579
1581 1580 if (sc->txq.queued >= RT2560_TX_RING_COUNT - 1) {
1582 1581 ral_debug(RAL_DBG_TX, "ral: rt2560_tx_data(): "
1583 1582 "no TX DMA buffer available!\n");
1584 1583 sc->sc_need_sched = 1;
1585 1584 sc->sc_tx_nobuf++;
1586 1585 err = ENOMEM;
1587 1586 goto fail1;
1588 1587 }
1589 1588
1590 1589 m = allocb(msgdsize(mp) + 32, BPRI_MED);
1591 1590 if (m == NULL) {
1592 1591 ral_debug(RAL_DBG_TX, "rt2560_xmit(): can't alloc mblk.\n");
1593 1592 err = DDI_FAILURE;
1594 1593 goto fail1;
1595 1594 }
1596 1595
1597 1596 for (off = 0, m0 = mp; m0 != NULL; m0 = m0->b_cont) {
1598 1597 mblen = MBLKL(m0);
1599 1598 (void) memcpy(m->b_rptr + off, m0->b_rptr, mblen);
1600 1599 off += mblen;
1601 1600 }
1602 1601 m->b_wptr += off;
1603 1602
1604 1603 wh = (struct ieee80211_frame *)m->b_rptr;
1605 1604 ni = ieee80211_find_txnode(ic, wh->i_addr1);
1606 1605
1607 1606 if (ni == NULL) {
1608 1607 err = DDI_FAILURE;
1609 1608 sc->sc_tx_err++;
1610 1609 goto fail2;
1611 1610 }
1612 1611
1613 1612 (void) ieee80211_encap(ic, m, ni);
1614 1613
1615 1614 if (wh->i_fc[1] & IEEE80211_FC1_WEP) {
1616 1615 k = ieee80211_crypto_encap(ic, m);
1617 1616 if (k == NULL) {
1618 1617 sc->sc_tx_err++;
1619 1618 err = DDI_FAILURE;
1620 1619 goto fail3;
1621 1620 }
1622 1621 /* packet header may have moved, reset our local pointer */
1623 1622 wh = (struct ieee80211_frame *)m->b_rptr;
1624 1623 }
1625 1624
1626 1625 /*
1627 1626 * RTS/CTS exchange ignore, since the max packet will less than
1628 1627 * the rtsthreshold (2346)
1629 1628 * Unnecessary codes deleted.
1630 1629 */
1631 1630
1632 1631 data = &sc->txq.data[sc->txq.cur];
1633 1632 desc = &sc->txq.desc[sc->txq.cur];
1634 1633
1635 1634 data->ni = ieee80211_ref_node(ni);
1636 1635
1637 1636 pktlen = msgdsize(m);
1638 1637 dest = data->buf;
1639 1638 bcopy(m->b_rptr, dest, pktlen);
1640 1639
1641 1640 if (ic->ic_fixed_rate != IEEE80211_FIXED_RATE_NONE) {
1642 1641 rs = &ic->ic_sup_rates[ic->ic_curmode];
1643 1642 rate = rs->ir_rates[ic->ic_fixed_rate];
1644 1643 } else {
1645 1644 rs = &ni->in_rates;
1646 1645 rn = (struct rt2560_node *)ni;
1647 1646 ni->in_txrate = ral_rssadapt_choose(&rn->rssadapt, rs, wh,
1648 1647 pktlen, NULL, 0);
1649 1648 rate = rs->ir_rates[ni->in_txrate];
1650 1649 }
1651 1650
1652 1651 rate &= IEEE80211_RATE_VAL;
1653 1652 if (rate <= 0) {
1654 1653 rate = 2; /* basic rate */
1655 1654 }
1656 1655
1657 1656 /* remember link conditions for rate adaptation algorithm */
1658 1657 if (ic->ic_fixed_rate == IEEE80211_FIXED_RATE_NONE) {
1659 1658 data->id.id_len = pktlen;
1660 1659 data->id.id_rateidx = ni->in_txrate;
1661 1660 data->id.id_node = ni;
1662 1661 data->id.id_rssi = ni->in_rssi;
1663 1662 } else
1664 1663 data->id.id_node = NULL;
1665 1664
1666 1665 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) {
1667 1666 flags |= RT2560_TX_ACK;
1668 1667
1669 1668 dur = rt2560_txtime(RAL_ACK_SIZE, rt2560_ack_rate(ic, rate),
1670 1669 ic->ic_flags) + RAL_SIFS;
1671 1670 /* LINTED E_BAD_PTR_CAST_ALIGN */
1672 1671 *(uint16_t *)wh->i_dur = LE_16(dur);
1673 1672 }
1674 1673
1675 1674 /* flags |= RT2560_TX_CIPHER_NONE; */
1676 1675 rt2560_setup_tx_desc(sc, desc, flags, pktlen, rate, 0);
1677 1676
1678 1677 idx = sc->txq.cur;
1679 1678
1680 1679 dr = &sc->txq.dr_txbuf[idx];
1681 1680 (void) ddi_dma_sync(dr->dr_hnd, 0, RAL_TXBUF_SIZE, DDI_DMA_SYNC_FORDEV);
1682 1681
1683 1682 dr = &sc->txq.dr_desc;
1684 1683 (void) ddi_dma_sync(dr->dr_hnd, idx * RT2560_TX_DESC_SIZE,
1685 1684 RT2560_TX_DESC_SIZE, DDI_DMA_SYNC_FORDEV);
1686 1685
1687 1686 ral_debug(RAL_DBG_TX, "sending data frame len=%u idx=%u rate=%u\n",
1688 1687 pktlen, sc->txq.cur, rate);
1689 1688
1690 1689 /* kick tx */
1691 1690 sc->txq.queued++;
1692 1691 sc->txq.cur = (sc->txq.cur + 1) % RT2560_TX_RING_COUNT;
1693 1692 RAL_WRITE(sc, RT2560_TXCSR0, RT2560_KICK_TX);
1694 1693
1695 1694 sc->sc_tx_timer = 5;
1696 1695
1697 1696 ic->ic_stats.is_tx_frags++;
1698 1697 ic->ic_stats.is_tx_bytes += pktlen;
1699 1698
1700 1699 freemsg(mp);
1701 1700 fail3:
1702 1701 ieee80211_free_node(ni);
1703 1702 fail2:
1704 1703 freemsg(m);
1705 1704 fail1:
1706 1705 mutex_exit(&sc->txq.tx_lock);
1707 1706 return (err);
1708 1707 }
1709 1708
1710 1709 static mblk_t *
1711 1710 rt2560_m_tx(void *arg, mblk_t *mp)
1712 1711 {
1713 1712 struct rt2560_softc *sc = (struct rt2560_softc *)arg;
1714 1713 struct ieee80211com *ic = &sc->sc_ic;
1715 1714 mblk_t *next;
1716 1715
1717 1716 if (!RAL_IS_RUNNING(sc)) {
1718 1717 freemsgchain(mp);
1719 1718 return (NULL);
1720 1719 }
1721 1720 /*
1722 1721 * No data frames go out unless we're associated; this
1723 1722 * should not happen as the 802.11 layer does not enable
1724 1723 * the xmit queue until we enter the RUN state.
1725 1724 */
1726 1725 if (ic->ic_state != IEEE80211_S_RUN) {
1727 1726 ral_debug(RAL_DBG_TX, "ral: rt2560_m_tx(): "
1728 1727 "discard, state %u\n", ic->ic_state);
1729 1728 freemsgchain(mp);
1730 1729 return (NULL);
1731 1730 }
1732 1731
1733 1732 while (mp != NULL) {
1734 1733 next = mp->b_next;
1735 1734 mp->b_next = NULL;
1736 1735 if (rt2560_send(ic, mp) != DDI_SUCCESS) {
1737 1736 mp->b_next = next;
1738 1737 freemsgchain(mp);
1739 1738 return (NULL);
1740 1739 }
1741 1740 mp = next;
1742 1741 }
1743 1742 return (mp);
1744 1743 }
1745 1744
1746 1745 static void
1747 1746 rt2560_set_macaddr(struct rt2560_softc *sc, uint8_t *addr)
1748 1747 {
1749 1748 uint32_t tmp;
1750 1749
1751 1750 tmp = addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24;
1752 1751 RAL_WRITE(sc, RT2560_CSR3, tmp);
1753 1752
1754 1753 tmp = addr[4] | addr[5] << 8;
1755 1754 RAL_WRITE(sc, RT2560_CSR4, tmp);
1756 1755
1757 1756 ral_debug(RAL_DBG_HW,
1758 1757 "setting MAC address to " MACSTR "\n", MAC2STR(addr));
1759 1758 }
1760 1759
1761 1760 static void
1762 1761 rt2560_get_macaddr(struct rt2560_softc *sc, uint8_t *addr)
1763 1762 {
1764 1763 uint32_t tmp;
1765 1764
1766 1765 tmp = RAL_READ(sc, RT2560_CSR3);
1767 1766 addr[0] = tmp & 0xff;
1768 1767 addr[1] = (tmp >> 8) & 0xff;
1769 1768 addr[2] = (tmp >> 16) & 0xff;
1770 1769 addr[3] = (tmp >> 24);
1771 1770
1772 1771 tmp = RAL_READ(sc, RT2560_CSR4);
1773 1772 addr[4] = tmp & 0xff;
1774 1773 addr[5] = (tmp >> 8) & 0xff;
1775 1774 }
1776 1775
1777 1776 static void
1778 1777 rt2560_update_promisc(struct rt2560_softc *sc)
1779 1778 {
1780 1779 uint32_t tmp;
1781 1780
1782 1781 tmp = RAL_READ(sc, RT2560_RXCSR0);
1783 1782 tmp &= ~RT2560_DROP_NOT_TO_ME;
1784 1783 if (!(sc->sc_rcr & RAL_RCR_PROMISC))
1785 1784 tmp |= RT2560_DROP_NOT_TO_ME;
1786 1785
1787 1786 RAL_WRITE(sc, RT2560_RXCSR0, tmp);
1788 1787 ral_debug(RAL_DBG_HW, "%s promiscuous mode\n",
1789 1788 (sc->sc_rcr & RAL_RCR_PROMISC) ? "entering" : "leaving");
1790 1789 }
1791 1790
1792 1791 static const char *
1793 1792 rt2560_get_rf(int rev)
1794 1793 {
1795 1794 switch (rev) {
1796 1795 case RT2560_RF_2522: return ("RT2522");
1797 1796 case RT2560_RF_2523: return ("RT2523");
1798 1797 case RT2560_RF_2524: return ("RT2524");
1799 1798 case RT2560_RF_2525: return ("RT2525");
1800 1799 case RT2560_RF_2525E: return ("RT2525e");
1801 1800 case RT2560_RF_2526: return ("RT2526");
1802 1801 case RT2560_RF_5222: return ("RT5222");
1803 1802 default: return ("unknown");
1804 1803 }
1805 1804 }
1806 1805
1807 1806 static void
1808 1807 rt2560_read_eeprom(struct rt2560_softc *sc)
1809 1808 {
1810 1809 uint16_t val;
1811 1810 int i;
1812 1811
1813 1812 val = rt2560_eeprom_read(sc, RT2560_EEPROM_CONFIG0);
1814 1813 sc->rf_rev = (val >> 11) & 0x7;
1815 1814 sc->hw_radio = (val >> 10) & 0x1;
1816 1815 sc->led_mode = (val >> 6) & 0x7;
1817 1816 sc->rx_ant = (val >> 4) & 0x3;
1818 1817 sc->tx_ant = (val >> 2) & 0x3;
1819 1818 sc->nb_ant = val & 0x3;
1820 1819
1821 1820 /* read default values for BBP registers */
1822 1821 for (i = 0; i < 16; i++) {
1823 1822 val = rt2560_eeprom_read(sc, RT2560_EEPROM_BBP_BASE + i);
1824 1823 sc->bbp_prom[i].reg = val >> 8;
1825 1824 sc->bbp_prom[i].val = val & 0xff;
1826 1825 }
1827 1826
1828 1827 /* read Tx power for all b/g channels */
1829 1828 for (i = 0; i < 14 / 2; i++) {
1830 1829 val = rt2560_eeprom_read(sc, RT2560_EEPROM_TXPOWER + i);
1831 1830 sc->txpow[i * 2] = val >> 8;
1832 1831 sc->txpow[i * 2 + 1] = val & 0xff;
1833 1832 }
1834 1833 }
1835 1834
1836 1835 static int
1837 1836 rt2560_bbp_init(struct rt2560_softc *sc)
1838 1837 {
1839 1838 #define N(a) (sizeof (a) / sizeof ((a)[0]))
1840 1839 int i, ntries;
1841 1840
1842 1841 /* wait for BBP to be ready */
1843 1842 for (ntries = 0; ntries < 100; ntries++) {
1844 1843 if (rt2560_bbp_read(sc, RT2560_BBP_VERSION) != 0)
1845 1844 break;
1846 1845 drv_usecwait(1);
1847 1846 }
1848 1847 if (ntries == 100) {
1849 1848 ral_debug(RAL_DBG_HW, "timeout waiting for BBP\n");
1850 1849 return (EIO);
1851 1850 }
1852 1851 /* initialize BBP registers to default values */
1853 1852 for (i = 0; i < N(rt2560_def_bbp); i++) {
1854 1853 rt2560_bbp_write(sc, rt2560_def_bbp[i].reg,
1855 1854 rt2560_def_bbp[i].val);
1856 1855 }
1857 1856
1858 1857 return (0);
1859 1858 #undef N
1860 1859 }
1861 1860
1862 1861 static void
1863 1862 rt2560_set_txantenna(struct rt2560_softc *sc, int antenna)
1864 1863 {
1865 1864 uint32_t tmp;
1866 1865 uint8_t tx;
1867 1866
1868 1867 tx = rt2560_bbp_read(sc, RT2560_BBP_TX) & ~RT2560_BBP_ANTMASK;
1869 1868 if (antenna == 1)
1870 1869 tx |= RT2560_BBP_ANTA;
1871 1870 else if (antenna == 2)
1872 1871 tx |= RT2560_BBP_ANTB;
1873 1872 else
1874 1873 tx |= RT2560_BBP_DIVERSITY;
1875 1874
1876 1875 /* need to force I/Q flip for RF 2525e, 2526 and 5222 */
1877 1876 if (sc->rf_rev == RT2560_RF_2525E || sc->rf_rev == RT2560_RF_2526 ||
1878 1877 sc->rf_rev == RT2560_RF_5222)
1879 1878 tx |= RT2560_BBP_FLIPIQ;
1880 1879
1881 1880 rt2560_bbp_write(sc, RT2560_BBP_TX, tx);
1882 1881
1883 1882 /* update values for CCK and OFDM in BBPCSR1 */
1884 1883 tmp = RAL_READ(sc, RT2560_BBPCSR1) & ~0x00070007;
1885 1884 tmp |= (tx & 0x7) << 16 | (tx & 0x7);
1886 1885 RAL_WRITE(sc, RT2560_BBPCSR1, tmp);
1887 1886 }
1888 1887
1889 1888 static void
1890 1889 rt2560_set_rxantenna(struct rt2560_softc *sc, int antenna)
1891 1890 {
1892 1891 uint8_t rx;
1893 1892
1894 1893 rx = rt2560_bbp_read(sc, RT2560_BBP_RX) & ~RT2560_BBP_ANTMASK;
1895 1894 if (antenna == 1)
1896 1895 rx |= RT2560_BBP_ANTA;
1897 1896 else if (antenna == 2)
1898 1897 rx |= RT2560_BBP_ANTB;
1899 1898 else
1900 1899 rx |= RT2560_BBP_DIVERSITY;
1901 1900
1902 1901 /* need to force no I/Q flip for RF 2525e and 2526 */
1903 1902 if (sc->rf_rev == RT2560_RF_2525E || sc->rf_rev == RT2560_RF_2526)
1904 1903 rx &= ~RT2560_BBP_FLIPIQ;
1905 1904
1906 1905 rt2560_bbp_write(sc, RT2560_BBP_RX, rx);
1907 1906 }
1908 1907
1909 1908 static void
1910 1909 rt2560_stop(struct rt2560_softc *sc)
1911 1910 {
1912 1911 struct ieee80211com *ic = &sc->sc_ic;
1913 1912
1914 1913 ieee80211_new_state(ic, IEEE80211_S_INIT, -1);
1915 1914 ieee80211_stop_watchdog(ic); /* stop the watchdog */
1916 1915
1917 1916 RAL_LOCK(sc);
1918 1917 sc->sc_tx_timer = 0;
1919 1918
1920 1919 /* abort Tx */
1921 1920 RAL_WRITE(sc, RT2560_TXCSR0, RT2560_ABORT_TX);
1922 1921
1923 1922 /* disable Rx */
1924 1923 RAL_WRITE(sc, RT2560_RXCSR0, RT2560_DISABLE_RX);
1925 1924
1926 1925 /* reset ASIC (imply reset BBP) */
1927 1926 RAL_WRITE(sc, RT2560_CSR1, RT2560_RESET_ASIC);
1928 1927 RAL_WRITE(sc, RT2560_CSR1, 0);
1929 1928
1930 1929 /* disable interrupts */
1931 1930 RAL_WRITE(sc, RT2560_CSR8, 0xffffffff);
1932 1931
1933 1932 /* reset Tx and Rx rings */
1934 1933 rt2560_reset_tx_ring(sc, &sc->txq);
1935 1934 rt2560_reset_tx_ring(sc, &sc->prioq);
1936 1935 rt2560_reset_rx_ring(sc, &sc->rxq);
1937 1936 RAL_UNLOCK(sc);
1938 1937 }
1939 1938
1940 1939 static int
1941 1940 rt2560_init(struct rt2560_softc *sc)
1942 1941 {
1943 1942 #define N(a) (sizeof (a) / sizeof ((a)[0]))
1944 1943 /* struct rt2560_softc *sc = priv; */
1945 1944 struct ieee80211com *ic = &sc->sc_ic;
1946 1945 uint32_t tmp;
1947 1946 int i;
1948 1947
1949 1948 rt2560_stop(sc);
1950 1949
1951 1950 RAL_LOCK(sc);
1952 1951 /* setup tx/rx ring */
1953 1952 rt2560_ring_hwsetup(sc);
1954 1953
1955 1954 /* initialize MAC registers to default values */
1956 1955 for (i = 0; i < N(rt2560_def_mac); i++)
1957 1956 RAL_WRITE(sc, rt2560_def_mac[i].reg, rt2560_def_mac[i].val);
1958 1957
1959 1958 rt2560_set_macaddr(sc, ic->ic_macaddr);
1960 1959
1961 1960 /* set basic rate set (will be updated later) */
1962 1961 RAL_WRITE(sc, RT2560_ARSP_PLCP_1, 0x153);
1963 1962
1964 1963 rt2560_set_txantenna(sc, sc->tx_ant);
1965 1964 rt2560_set_rxantenna(sc, sc->rx_ant);
1966 1965 rt2560_update_slot(ic, 1);
1967 1966 rt2560_update_plcp(sc);
1968 1967 rt2560_update_led(sc, 0, 0);
1969 1968
1970 1969 RAL_WRITE(sc, RT2560_CSR1, RT2560_RESET_ASIC);
1971 1970 RAL_WRITE(sc, RT2560_CSR1, RT2560_HOST_READY);
1972 1971
1973 1972 if (rt2560_bbp_init(sc) != 0) {
1974 1973 RAL_UNLOCK(sc);
1975 1974 rt2560_stop(sc);
1976 1975 return (DDI_FAILURE);
1977 1976 }
1978 1977
1979 1978 /* set default BSS channel */
1980 1979 rt2560_set_chan(sc, ic->ic_curchan);
1981 1980
1982 1981 /* kick Rx */
1983 1982 tmp = RT2560_DROP_PHY_ERROR | RT2560_DROP_CRC_ERROR;
1984 1983 if (ic->ic_opmode != IEEE80211_M_MONITOR) {
1985 1984 tmp |= RT2560_DROP_CTL | RT2560_DROP_VERSION_ERROR;
1986 1985 if (ic->ic_opmode != IEEE80211_M_HOSTAP)
1987 1986 tmp |= RT2560_DROP_TODS;
1988 1987 if (!(sc->sc_rcr & RAL_RCR_PROMISC))
1989 1988 tmp |= RT2560_DROP_NOT_TO_ME;
1990 1989
1991 1990 }
1992 1991 RAL_WRITE(sc, RT2560_RXCSR0, tmp);
1993 1992
1994 1993 /* clear old FCS and Rx FIFO errors */
1995 1994 (void) RAL_READ(sc, RT2560_CNT0);
1996 1995 (void) RAL_READ(sc, RT2560_CNT4);
1997 1996
1998 1997 /* clear any pending interrupts */
1999 1998 RAL_WRITE(sc, RT2560_CSR7, 0xffffffff);
2000 1999 /* enable interrupts */
2001 2000 RAL_WRITE(sc, RT2560_CSR8, RT2560_INTR_MASK);
2002 2001
2003 2002 RAL_UNLOCK(sc);
2004 2003 #undef N
2005 2004 return (DDI_SUCCESS);
2006 2005 }
2007 2006
2008 2007 void
2009 2008 rt2560_watchdog(void *arg)
2010 2009 {
2011 2010 struct rt2560_softc *sc = arg;
2012 2011 struct ieee80211com *ic = &sc->sc_ic;
2013 2012 int ntimer = 0;
2014 2013
2015 2014 RAL_LOCK(sc);
2016 2015 ic->ic_watchdog_timer = 0;
2017 2016
2018 2017 if (!RAL_IS_RUNNING(sc)) {
2019 2018 RAL_UNLOCK(sc);
2020 2019 return;
2021 2020 }
2022 2021
2023 2022 if (sc->sc_tx_timer > 0) {
2024 2023 if (--sc->sc_tx_timer == 0) {
2025 2024 ral_debug(RAL_DBG_MSG, "tx timer timeout\n");
2026 2025 RAL_UNLOCK(sc);
2027 2026 (void) rt2560_init(sc);
2028 2027 (void) ieee80211_new_state(ic, IEEE80211_S_SCAN, -1);
2029 2028 return;
2030 2029 }
2031 2030 }
2032 2031
2033 2032 if (ic->ic_state == IEEE80211_S_RUN)
2034 2033 ntimer = 1;
2035 2034
2036 2035 RAL_UNLOCK(sc);
2037 2036
2038 2037 ieee80211_watchdog(ic);
2039 2038
2040 2039 if (ntimer)
2041 2040 ieee80211_start_watchdog(ic, ntimer);
2042 2041 }
2043 2042
2044 2043 static int
2045 2044 rt2560_m_start(void *arg)
2046 2045 {
2047 2046 struct rt2560_softc *sc = (struct rt2560_softc *)arg;
2048 2047 int err;
2049 2048
2050 2049 /*
2051 2050 * initialize rt2560 hardware
2052 2051 */
2053 2052 err = rt2560_init(sc);
2054 2053 if (err != DDI_SUCCESS) {
2055 2054 ral_debug(RAL_DBG_GLD, "device configuration failed\n");
2056 2055 goto fail;
2057 2056 }
2058 2057 sc->sc_flags |= RAL_FLAG_RUNNING; /* RUNNING */
2059 2058 return (err);
2060 2059
2061 2060 fail:
2062 2061 rt2560_stop(sc);
2063 2062 return (err);
2064 2063 }
2065 2064
2066 2065 static void
2067 2066 rt2560_m_stop(void *arg)
2068 2067 {
2069 2068 struct rt2560_softc *sc = (struct rt2560_softc *)arg;
2070 2069
2071 2070 (void) rt2560_stop(sc);
2072 2071 sc->sc_flags &= ~RAL_FLAG_RUNNING; /* STOP */
2073 2072 }
2074 2073
2075 2074 static int
2076 2075 rt2560_m_unicst(void *arg, const uint8_t *macaddr)
2077 2076 {
2078 2077 struct rt2560_softc *sc = (struct rt2560_softc *)arg;
2079 2078 struct ieee80211com *ic = &sc->sc_ic;
2080 2079
2081 2080 ral_debug(RAL_DBG_GLD, "rt2560_m_unicst(): " MACSTR "\n",
2082 2081 MAC2STR(macaddr));
2083 2082
2084 2083 IEEE80211_ADDR_COPY(ic->ic_macaddr, macaddr);
2085 2084 (void) rt2560_set_macaddr(sc, (uint8_t *)macaddr);
2086 2085 (void) rt2560_init(sc);
2087 2086
2088 2087 return (0);
2089 2088 }
2090 2089
2091 2090 /*ARGSUSED*/
2092 2091 static int
2093 2092 rt2560_m_multicst(void *arg, boolean_t add, const uint8_t *mca)
2094 2093 {
2095 2094 return (0);
2096 2095 }
2097 2096
2098 2097 static int
2099 2098 rt2560_m_promisc(void *arg, boolean_t on)
2100 2099 {
2101 2100 struct rt2560_softc *sc = (struct rt2560_softc *)arg;
2102 2101
2103 2102 if (on) {
2104 2103 sc->sc_rcr |= RAL_RCR_PROMISC;
2105 2104 sc->sc_rcr |= RAL_RCR_MULTI;
2106 2105 } else {
2107 2106 sc->sc_rcr &= ~RAL_RCR_PROMISC;
2108 2107 sc->sc_rcr &= ~RAL_RCR_PROMISC;
2109 2108 }
2110 2109
2111 2110 rt2560_update_promisc(sc);
2112 2111 return (0);
2113 2112 }
2114 2113
2115 2114 /*
2116 2115 * callback functions for /get/set properties
2117 2116 */
2118 2117 static int
2119 2118 rt2560_m_setprop(void *arg, const char *pr_name, mac_prop_id_t wldp_pr_num,
2120 2119 uint_t wldp_length, const void *wldp_buf)
2121 2120 {
2122 2121 struct rt2560_softc *sc = arg;
2123 2122 struct ieee80211com *ic = &sc->sc_ic;
2124 2123 int err;
2125 2124
2126 2125 err = ieee80211_setprop(ic, pr_name, wldp_pr_num,
2127 2126 wldp_length, wldp_buf);
2128 2127 RAL_LOCK(sc);
2129 2128 if (err == ENETRESET) {
2130 2129 if (RAL_IS_RUNNING(sc)) {
2131 2130 RAL_UNLOCK(sc);
2132 2131 (void) rt2560_init(sc);
2133 2132 (void) ieee80211_new_state(ic, IEEE80211_S_SCAN, -1);
2134 2133 RAL_LOCK(sc);
2135 2134 }
2136 2135 err = 0;
2137 2136 }
2138 2137 RAL_UNLOCK(sc);
2139 2138
2140 2139 return (err);
2141 2140 }
2142 2141
2143 2142 static int
2144 2143 rt2560_m_getprop(void *arg, const char *pr_name, mac_prop_id_t wldp_pr_num,
2145 2144 uint_t wldp_length, void *wldp_buf)
2146 2145 {
2147 2146 struct rt2560_softc *sc = arg;
2148 2147 int err;
2149 2148
2150 2149 err = ieee80211_getprop(&sc->sc_ic, pr_name, wldp_pr_num,
2151 2150 wldp_length, wldp_buf);
2152 2151
2153 2152 return (err);
2154 2153 }
2155 2154
2156 2155 static void
2157 2156 rt2560_m_propinfo(void *arg, const char *pr_name, mac_prop_id_t wldp_pr_num,
2158 2157 mac_prop_info_handle_t prh)
2159 2158 {
2160 2159 struct rt2560_softc *sc = arg;
2161 2160
2162 2161 ieee80211_propinfo(&sc->sc_ic, pr_name, wldp_pr_num, prh);
2163 2162 }
2164 2163
2165 2164 static void
2166 2165 rt2560_m_ioctl(void* arg, queue_t *wq, mblk_t *mp)
2167 2166 {
2168 2167 struct rt2560_softc *sc = (struct rt2560_softc *)arg;
2169 2168 struct ieee80211com *ic = &sc->sc_ic;
2170 2169 int err;
2171 2170
2172 2171 err = ieee80211_ioctl(ic, wq, mp);
2173 2172 RAL_LOCK(sc);
2174 2173 if (err == ENETRESET) {
2175 2174 if (RAL_IS_RUNNING(sc)) {
2176 2175 RAL_UNLOCK(sc);
2177 2176 (void) rt2560_init(sc);
2178 2177 (void) ieee80211_new_state(ic, IEEE80211_S_SCAN, -1);
2179 2178 RAL_LOCK(sc);
2180 2179 }
2181 2180 }
2182 2181 RAL_UNLOCK(sc);
2183 2182 }
2184 2183
2185 2184 static int
2186 2185 rt2560_m_stat(void *arg, uint_t stat, uint64_t *val)
2187 2186 {
2188 2187 struct rt2560_softc *sc = (struct rt2560_softc *)arg;
2189 2188 ieee80211com_t *ic = &sc->sc_ic;
2190 2189 ieee80211_node_t *ni = ic->ic_bss;
2191 2190 struct ieee80211_rateset *rs = &ni->in_rates;
2192 2191
2193 2192 RAL_LOCK(sc);
2194 2193 switch (stat) {
2195 2194 case MAC_STAT_IFSPEED:
2196 2195 *val = ((ic->ic_fixed_rate == IEEE80211_FIXED_RATE_NONE) ?
2197 2196 (rs->ir_rates[ni->in_txrate] & IEEE80211_RATE_VAL)
2198 2197 : ic->ic_fixed_rate) / 2 * 1000000;
2199 2198 break;
2200 2199 case MAC_STAT_NOXMTBUF:
2201 2200 *val = sc->sc_tx_nobuf;
2202 2201 break;
2203 2202 case MAC_STAT_NORCVBUF:
2204 2203 *val = sc->sc_rx_nobuf;
2205 2204 break;
2206 2205 case MAC_STAT_IERRORS:
2207 2206 *val = sc->sc_rx_err;
2208 2207 break;
2209 2208 case MAC_STAT_RBYTES:
2210 2209 *val = ic->ic_stats.is_rx_bytes;
2211 2210 break;
2212 2211 case MAC_STAT_IPACKETS:
2213 2212 *val = ic->ic_stats.is_rx_frags;
2214 2213 break;
2215 2214 case MAC_STAT_OBYTES:
2216 2215 *val = ic->ic_stats.is_tx_bytes;
2217 2216 break;
2218 2217 case MAC_STAT_OPACKETS:
2219 2218 *val = ic->ic_stats.is_tx_frags;
2220 2219 break;
2221 2220 case MAC_STAT_OERRORS:
2222 2221 case WIFI_STAT_TX_FAILED:
2223 2222 *val = sc->sc_tx_err;
2224 2223 break;
2225 2224 case WIFI_STAT_TX_RETRANS:
2226 2225 *val = sc->sc_tx_retries;
2227 2226 break;
2228 2227 case WIFI_STAT_FCS_ERRORS:
2229 2228 case WIFI_STAT_WEP_ERRORS:
2230 2229 case WIFI_STAT_TX_FRAGS:
2231 2230 case WIFI_STAT_MCAST_TX:
2232 2231 case WIFI_STAT_RTS_SUCCESS:
2233 2232 case WIFI_STAT_RTS_FAILURE:
2234 2233 case WIFI_STAT_ACK_FAILURE:
2235 2234 case WIFI_STAT_RX_FRAGS:
2236 2235 case WIFI_STAT_MCAST_RX:
2237 2236 case WIFI_STAT_RX_DUPS:
2238 2237 RAL_UNLOCK(sc);
2239 2238 return (ieee80211_stat(ic, stat, val));
2240 2239 default:
2241 2240 RAL_UNLOCK(sc);
2242 2241 return (ENOTSUP);
2243 2242 }
2244 2243 RAL_UNLOCK(sc);
2245 2244
2246 2245 return (0);
2247 2246 }
2248 2247
2249 2248 static uint_t
2250 2249 rt2560_intr(caddr_t arg)
2251 2250 {
2252 2251 /* LINTED E_BAD_PTR_CAST_ALIGN */
2253 2252 struct rt2560_softc *sc = (struct rt2560_softc *)arg;
2254 2253 uint32_t r;
2255 2254
2256 2255 RAL_LOCK(sc);
2257 2256
2258 2257 if (!RAL_IS_RUNNING(sc)) {
2259 2258 /*
2260 2259 * The hardware is not ready/present, don't touch anything.
2261 2260 * Note this can happen early on if the IRQ is shared.
2262 2261 */
2263 2262 RAL_UNLOCK(sc);
2264 2263 return (DDI_INTR_UNCLAIMED);
2265 2264 }
2266 2265
2267 2266 r = RAL_READ(sc, RT2560_CSR7);
2268 2267 RAL_WRITE(sc, RT2560_CSR7, r);
2269 2268
2270 2269 if (r == 0xffffffff) {
2271 2270 RAL_UNLOCK(sc);
2272 2271 return (DDI_INTR_UNCLAIMED);
2273 2272 }
2274 2273
2275 2274 if (!(r & RT2560_INTR_ALL)) {
2276 2275 RAL_UNLOCK(sc);
2277 2276 return (DDI_INTR_UNCLAIMED);
2278 2277 }
2279 2278
2280 2279 /* disable interrupts */
2281 2280 RAL_WRITE(sc, RT2560_CSR8, 0xffffffff);
2282 2281
2283 2282 if (r & RT2560_TX_DONE) {
2284 2283 RAL_UNLOCK(sc);
2285 2284 rt2560_tx_intr(sc);
2286 2285 RAL_LOCK(sc);
2287 2286 }
2288 2287
2289 2288 if (r & RT2560_PRIO_DONE) {
2290 2289 RAL_UNLOCK(sc);
2291 2290 rt2560_prio_intr(sc);
2292 2291 RAL_LOCK(sc);
2293 2292 }
2294 2293
2295 2294 if (r & RT2560_RX_DONE) {
2296 2295 sc->sc_rx_pend = 1;
2297 2296 ddi_trigger_softintr(sc->sc_softint_id);
2298 2297 }
2299 2298
2300 2299 /* re-enable interrupts */
2301 2300 RAL_WRITE(sc, RT2560_CSR8, RT2560_INTR_MASK);
2302 2301 RAL_UNLOCK(sc);
2303 2302
2304 2303 return (DDI_INTR_CLAIMED);
2305 2304 }
2306 2305
2307 2306 /*
2308 2307 * quiesce(9E) entry point.
2309 2308 *
2310 2309 * This function is called when the system is single-threaded at high
2311 2310 * PIL with preemption disabled. Therefore, this function must not be
2312 2311 * blocked.
2313 2312 *
2314 2313 * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure.
2315 2314 * DDI_FAILURE indicates an error condition and should almost never happen.
2316 2315 */
2317 2316 static int32_t
2318 2317 rt2560_quiesce(dev_info_t *devinfo)
2319 2318 {
2320 2319 struct rt2560_softc *sc;
2321 2320
2322 2321 sc = ddi_get_soft_state(ral_soft_state_p, ddi_get_instance(devinfo));
2323 2322 if (sc == NULL)
2324 2323 return (DDI_FAILURE);
2325 2324
2326 2325 /* abort Tx */
2327 2326 RAL_WRITE(sc, RT2560_TXCSR0, RT2560_ABORT_TX);
2328 2327
2329 2328 /* disable Rx */
2330 2329 RAL_WRITE(sc, RT2560_RXCSR0, RT2560_DISABLE_RX);
2331 2330
2332 2331 /* reset ASIC (imply reset BBP) */
2333 2332 RAL_WRITE(sc, RT2560_CSR1, RT2560_RESET_ASIC);
2334 2333 RAL_WRITE(sc, RT2560_CSR1, 0);
2335 2334
2336 2335 /* disable interrupts */
2337 2336 RAL_WRITE(sc, RT2560_CSR8, 0xffffffff);
2338 2337
2339 2338 return (DDI_SUCCESS);
2340 2339 }
2341 2340
2342 2341 static int
2343 2342 rt2560_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd)
2344 2343 {
2345 2344 struct rt2560_softc *sc;
2346 2345 struct ieee80211com *ic;
2347 2346 int err, i;
2348 2347 int instance;
2349 2348
2350 2349 ddi_acc_handle_t ioh;
2351 2350 caddr_t regs;
2352 2351 uint16_t vendor_id, device_id, command;
2353 2352 uint8_t cachelsz;
2354 2353 char strbuf[32];
2355 2354
2356 2355 wifi_data_t wd = { 0 };
2357 2356 mac_register_t *macp;
2358 2357
2359 2358 switch (cmd) {
2360 2359 case DDI_ATTACH:
2361 2360 break;
2362 2361 case DDI_RESUME:
2363 2362 sc = ddi_get_soft_state(ral_soft_state_p,
2364 2363 ddi_get_instance(devinfo));
2365 2364 sc->sc_flags &= ~RAL_FLAG_SUSPENDING;
2366 2365 if (RAL_IS_INITED(sc))
2367 2366 (void) rt2560_init(sc);
2368 2367 return (DDI_SUCCESS);
2369 2368 default:
2370 2369 return (DDI_FAILURE);
2371 2370 }
2372 2371
2373 2372 instance = ddi_get_instance(devinfo);
2374 2373
2375 2374 if (ddi_soft_state_zalloc(ral_soft_state_p, instance) != DDI_SUCCESS) {
2376 2375 ral_debug(RAL_DBG_GLD, "ral: rt2560_attach(): "
2377 2376 "unable to alloc soft_state_p\n");
2378 2377 return (DDI_FAILURE);
2379 2378 }
2380 2379
2381 2380 sc = ddi_get_soft_state(ral_soft_state_p, instance);
2382 2381 ic = (ieee80211com_t *)&sc->sc_ic;
2383 2382 sc->sc_dev = devinfo;
2384 2383
2385 2384 /* pci configuration */
2386 2385 err = ddi_regs_map_setup(devinfo, 0, ®s, 0, 0, &ral_csr_accattr,
2387 2386 &ioh);
2388 2387 if (err != DDI_SUCCESS) {
2389 2388 ral_debug(RAL_DBG_GLD, "ral: rt2560_attach(): "
2390 2389 "ddi_regs_map_setup() failed");
2391 2390 goto fail1;
2392 2391 }
2393 2392
2394 2393 cachelsz = ddi_get8(ioh, (uint8_t *)(regs + PCI_CONF_CACHE_LINESZ));
2395 2394 if (cachelsz == 0)
2396 2395 cachelsz = 0x10;
2397 2396 sc->sc_cachelsz = cachelsz << 2;
2398 2397
2399 2398 vendor_id = ddi_get16(ioh,
2400 2399 (uint16_t *)((uintptr_t)regs + PCI_CONF_VENID));
2401 2400 device_id = ddi_get16(ioh,
2402 2401 (uint16_t *)((uintptr_t)regs + PCI_CONF_DEVID));
2403 2402
2404 2403 ral_debug(RAL_DBG_GLD, "ral: rt2560_attach(): vendor 0x%x, "
2405 2404 "device id 0x%x, cache size %d\n", vendor_id, device_id, cachelsz);
2406 2405
2407 2406 /*
2408 2407 * Enable response to memory space accesses,
2409 2408 * and enabe bus master.
2410 2409 */
2411 2410 command = PCI_COMM_MAE | PCI_COMM_ME;
2412 2411 ddi_put16(ioh, (uint16_t *)((uintptr_t)regs + PCI_CONF_COMM), command);
2413 2412 ral_debug(RAL_DBG_GLD, "ral: rt2560_attach(): "
2414 2413 "set command reg to 0x%x \n", command);
2415 2414
2416 2415 ddi_put8(ioh, (uint8_t *)(regs + PCI_CONF_LATENCY_TIMER), 0xa8);
2417 2416 ddi_put8(ioh, (uint8_t *)(regs + PCI_CONF_ILINE), 0x10);
2418 2417 ddi_regs_map_free(&ioh);
2419 2418
2420 2419 /* pci i/o space */
2421 2420 err = ddi_regs_map_setup(devinfo, 1,
2422 2421 &sc->sc_rbase, 0, 0, &ral_csr_accattr, &sc->sc_ioh);
2423 2422 ral_debug(RAL_DBG_GLD, "ral: rt2560_attach(): "
2424 2423 "regs map1 = %x err=%d\n", regs, err);
2425 2424 if (err != DDI_SUCCESS) {
2426 2425 ral_debug(RAL_DBG_GLD, "ral: rt2560_attach(): "
2427 2426 "ddi_regs_map_setup() failed");
2428 2427 goto fail1;
2429 2428 }
2430 2429
2431 2430 /* initialize the ral rate */
2432 2431 ral_rate_init();
2433 2432
2434 2433 /* retrieve RT2560 rev. no */
2435 2434 sc->asic_rev = RAL_READ(sc, RT2560_CSR0);
2436 2435
2437 2436 /* retrieve MAC address */
2438 2437 rt2560_get_macaddr(sc, ic->ic_macaddr);
2439 2438
2440 2439 /* retrieve RF rev. no and various other things from EEPROM */
2441 2440 rt2560_read_eeprom(sc);
2442 2441
2443 2442 ral_debug(RAL_DBG_GLD, "MAC/BBP RT2560 (rev 0x%02x), RF %s\n",
2444 2443 sc->asic_rev, rt2560_get_rf(sc->rf_rev));
2445 2444
2446 2445 /*
2447 2446 * Allocate Tx and Rx rings.
2448 2447 */
2449 2448 err = rt2560_alloc_tx_ring(sc, &sc->txq, RT2560_TX_RING_COUNT);
2450 2449 if (err != DDI_SUCCESS) {
2451 2450 ral_debug(RAL_DBG_GLD, "could not allocate Tx ring\n");
2452 2451 goto fail2;
2453 2452 }
2454 2453 err = rt2560_alloc_tx_ring(sc, &sc->prioq, RT2560_PRIO_RING_COUNT);
2455 2454 if (err != DDI_SUCCESS) {
2456 2455 ral_debug(RAL_DBG_GLD, "could not allocate Prio ring\n");
2457 2456 goto fail3;
2458 2457 }
2459 2458 err = rt2560_alloc_rx_ring(sc, &sc->rxq, RT2560_RX_RING_COUNT);
2460 2459 if (err != DDI_SUCCESS) {
2461 2460 ral_debug(RAL_DBG_GLD, "could not allocate Rx ring\n");
2462 2461 goto fail4;
2463 2462 }
2464 2463
2465 2464 mutex_init(&sc->sc_genlock, NULL, MUTEX_DRIVER, NULL);
2466 2465 mutex_init(&sc->txq.tx_lock, NULL, MUTEX_DRIVER, NULL);
2467 2466 mutex_init(&sc->prioq.tx_lock, NULL, MUTEX_DRIVER, NULL);
2468 2467 mutex_init(&sc->rxq.rx_lock, NULL, MUTEX_DRIVER, NULL);
2469 2468
2470 2469
2471 2470 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */
2472 2471 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */
2473 2472 ic->ic_state = IEEE80211_S_INIT;
2474 2473
2475 2474 ic->ic_maxrssi = 63;
2476 2475 ic->ic_set_shortslot = rt2560_update_slot;
2477 2476 ic->ic_xmit = rt2560_mgmt_send;
2478 2477
2479 2478 /* set device capabilities */
2480 2479 ic->ic_caps =
2481 2480 IEEE80211_C_TXPMGT | /* tx power management */
2482 2481 IEEE80211_C_SHPREAMBLE | /* short preamble supported */
2483 2482 IEEE80211_C_SHSLOT; /* short slot time supported */
2484 2483
2485 2484 ic->ic_caps |= IEEE80211_C_WPA; /* Support WPA/WPA2 */
2486 2485
2487 2486 #define IEEE80211_CHAN_A \
2488 2487 (IEEE80211_CHAN_5GHZ | IEEE80211_CHAN_OFDM)
2489 2488
2490 2489 if (sc->rf_rev == RT2560_RF_5222) {
2491 2490 /* set supported .11a rates */
2492 2491 ic->ic_sup_rates[IEEE80211_MODE_11A] = rt2560_rateset_11a;
2493 2492
2494 2493 /* set supported .11a channels */
2495 2494 for (i = 36; i <= 64; i += 4) {
2496 2495 ic->ic_sup_channels[i].ich_freq =
2497 2496 ieee80211_ieee2mhz(i, IEEE80211_CHAN_5GHZ);
2498 2497 ic->ic_sup_channels[i].ich_flags = IEEE80211_CHAN_A;
2499 2498 }
2500 2499 for (i = 100; i <= 140; i += 4) {
2501 2500 ic->ic_sup_channels[i].ich_freq =
2502 2501 ieee80211_ieee2mhz(i, IEEE80211_CHAN_5GHZ);
2503 2502 ic->ic_sup_channels[i].ich_flags = IEEE80211_CHAN_A;
2504 2503 }
2505 2504 for (i = 149; i <= 161; i += 4) {
2506 2505 ic->ic_sup_channels[i].ich_freq =
2507 2506 ieee80211_ieee2mhz(i, IEEE80211_CHAN_5GHZ);
2508 2507 ic->ic_sup_channels[i].ich_flags = IEEE80211_CHAN_A;
2509 2508 }
2510 2509 }
2511 2510
2512 2511 /* set supported .11b and .11g rates */
2513 2512 ic->ic_sup_rates[IEEE80211_MODE_11B] = rt2560_rateset_11b;
2514 2513 ic->ic_sup_rates[IEEE80211_MODE_11G] = rt2560_rateset_11g;
2515 2514
2516 2515 /* set supported .11b and .11g channels (1 through 14) */
2517 2516 for (i = 1; i <= 14; i++) {
2518 2517 ic->ic_sup_channels[i].ich_freq =
2519 2518 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ);
2520 2519 ic->ic_sup_channels[i].ich_flags =
2521 2520 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM |
2522 2521 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ;
2523 2522 }
2524 2523
2525 2524 ieee80211_attach(ic);
2526 2525
2527 2526 /* register WPA door */
2528 2527 ieee80211_register_door(ic, ddi_driver_name(devinfo),
2529 2528 ddi_get_instance(devinfo));
2530 2529
2531 2530 ic->ic_node_alloc = rt2560_node_alloc;
2532 2531 ic->ic_node_free = rt2560_node_free;
2533 2532
2534 2533 /* override state transition machine */
2535 2534 sc->sc_newstate = ic->ic_newstate;
2536 2535 ic->ic_newstate = rt2560_newstate;
2537 2536 ic->ic_watchdog = rt2560_watchdog;
2538 2537 ieee80211_media_init(ic);
2539 2538 ic->ic_def_txkey = 0;
2540 2539
2541 2540 sc->sc_rcr = 0;
2542 2541 sc->sc_rx_pend = 0;
2543 2542 sc->dwelltime = 300;
2544 2543 sc->sc_flags &= ~RAL_FLAG_RUNNING;
2545 2544
2546 2545 err = ddi_add_softintr(devinfo, DDI_SOFTINT_LOW,
2547 2546 &sc->sc_softint_id, NULL, 0, ral_softint_handler, (caddr_t)sc);
2548 2547 if (err != DDI_SUCCESS) {
2549 2548 ral_debug(RAL_DBG_GLD, "ral: rt2560_attach(): "
2550 2549 "ddi_add_softintr() failed");
2551 2550 goto fail5;
2552 2551 }
2553 2552
2554 2553 err = ddi_get_iblock_cookie(devinfo, 0, &sc->sc_iblock);
2555 2554 if (err != DDI_SUCCESS) {
2556 2555 ral_debug(RAL_DBG_GLD, "ral: rt2560_attach(): "
2557 2556 "Can not get iblock cookie for INT\n");
2558 2557 goto fail6;
2559 2558 }
2560 2559
2561 2560 err = ddi_add_intr(devinfo, 0, NULL, NULL, rt2560_intr, (caddr_t)sc);
2562 2561 if (err != DDI_SUCCESS) {
2563 2562 ral_debug(RAL_DBG_GLD,
2564 2563 "unable to add device interrupt handler\n");
2565 2564 goto fail6;
2566 2565 }
2567 2566
2568 2567 /*
2569 2568 * Provide initial settings for the WiFi plugin; whenever this
2570 2569 * information changes, we need to call mac_plugindata_update()
2571 2570 */
2572 2571 wd.wd_opmode = ic->ic_opmode;
2573 2572 wd.wd_secalloc = WIFI_SEC_NONE;
2574 2573 IEEE80211_ADDR_COPY(wd.wd_bssid, ic->ic_bss->in_bssid);
2575 2574
2576 2575 if ((macp = mac_alloc(MAC_VERSION)) == NULL) {
2577 2576 ral_debug(RAL_DBG_GLD, "ral: rt2560_attach(): "
2578 2577 "MAC version mismatch\n");
2579 2578 goto fail7;
2580 2579 }
2581 2580
2582 2581 macp->m_type_ident = MAC_PLUGIN_IDENT_WIFI;
2583 2582 macp->m_driver = sc;
2584 2583 macp->m_dip = devinfo;
2585 2584 macp->m_src_addr = ic->ic_macaddr;
2586 2585 macp->m_callbacks = &rt2560_m_callbacks;
2587 2586 macp->m_min_sdu = 0;
2588 2587 macp->m_max_sdu = IEEE80211_MTU;
2589 2588 macp->m_pdata = &wd;
2590 2589 macp->m_pdata_size = sizeof (wd);
2591 2590
2592 2591 err = mac_register(macp, &ic->ic_mach);
2593 2592 mac_free(macp);
2594 2593 if (err != 0) {
2595 2594 ral_debug(RAL_DBG_GLD, "ral: rt2560_attach(): "
2596 2595 "mac_register err %x\n", err);
2597 2596 goto fail7;
2598 2597 }
2599 2598
2600 2599 /*
2601 2600 * Create minor node of type DDI_NT_NET_WIFI
2602 2601 */
2603 2602 (void) snprintf(strbuf, sizeof (strbuf), "%s%d",
2604 2603 "ral", instance);
2605 2604 err = ddi_create_minor_node(devinfo, strbuf, S_IFCHR,
2606 2605 instance + 1, DDI_NT_NET_WIFI, 0);
2607 2606
2608 2607 if (err != DDI_SUCCESS)
2609 2608 ral_debug(RAL_DBG_GLD, "ddi_create_minor_node() failed\n");
2610 2609
2611 2610 /*
2612 2611 * Notify link is down now
2613 2612 */
2614 2613 mac_link_update(ic->ic_mach, LINK_STATE_DOWN);
2615 2614
2616 2615 return (DDI_SUCCESS);
2617 2616 fail7:
2618 2617 ddi_remove_intr(devinfo, 0, sc->sc_iblock);
2619 2618 fail6:
2620 2619 ddi_remove_softintr(sc->sc_softint_id);
2621 2620 fail5:
2622 2621 mutex_destroy(&sc->sc_genlock);
2623 2622 mutex_destroy(&sc->txq.tx_lock);
2624 2623 mutex_destroy(&sc->prioq.tx_lock);
2625 2624 mutex_destroy(&sc->rxq.rx_lock);
2626 2625
2627 2626 rt2560_free_rx_ring(sc, &sc->rxq);
2628 2627 fail4:
2629 2628 rt2560_free_tx_ring(sc, &sc->prioq);
2630 2629 fail3:
2631 2630 rt2560_free_tx_ring(sc, &sc->txq);
2632 2631 fail2:
2633 2632 ddi_regs_map_free(&sc->sc_ioh);
2634 2633 fail1:
2635 2634 ddi_soft_state_free(ral_soft_state_p, ddi_get_instance(devinfo));
2636 2635
2637 2636 return (DDI_FAILURE);
2638 2637 }
2639 2638
2640 2639 static int
2641 2640 rt2560_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd)
2642 2641 {
2643 2642 struct rt2560_softc *sc;
2644 2643
2645 2644 sc = ddi_get_soft_state(ral_soft_state_p, ddi_get_instance(devinfo));
2646 2645 ASSERT(sc != NULL);
2647 2646
2648 2647 switch (cmd) {
2649 2648 case DDI_DETACH:
2650 2649 break;
2651 2650 case DDI_SUSPEND:
2652 2651 if (RAL_IS_INITED(sc))
2653 2652 (void) rt2560_stop(sc);
2654 2653 sc->sc_flags |= RAL_FLAG_SUSPENDING;
2655 2654 return (DDI_SUCCESS);
2656 2655 default:
2657 2656 return (DDI_FAILURE);
2658 2657 }
2659 2658
2660 2659 if (mac_disable(sc->sc_ic.ic_mach) != 0)
2661 2660 return (DDI_FAILURE);
2662 2661
2663 2662 rt2560_stop(sc);
2664 2663
2665 2664 /*
2666 2665 * Unregister from the MAC layer subsystem
2667 2666 */
2668 2667 (void) mac_unregister(sc->sc_ic.ic_mach);
2669 2668
2670 2669 ddi_remove_intr(devinfo, 0, sc->sc_iblock);
2671 2670 ddi_remove_softintr(sc->sc_softint_id);
2672 2671
2673 2672 /*
2674 2673 * detach ieee80211 layer
2675 2674 */
2676 2675 ieee80211_detach(&sc->sc_ic);
2677 2676
2678 2677 rt2560_free_tx_ring(sc, &sc->txq);
2679 2678 rt2560_free_tx_ring(sc, &sc->prioq);
2680 2679 rt2560_free_rx_ring(sc, &sc->rxq);
2681 2680
2682 2681 ddi_regs_map_free(&sc->sc_ioh);
2683 2682
2684 2683 mutex_destroy(&sc->sc_genlock);
2685 2684 mutex_destroy(&sc->txq.tx_lock);
2686 2685 mutex_destroy(&sc->prioq.tx_lock);
2687 2686 mutex_destroy(&sc->rxq.rx_lock);
2688 2687
2689 2688 ddi_remove_minor_node(devinfo, NULL);
2690 2689 ddi_soft_state_free(ral_soft_state_p, ddi_get_instance(devinfo));
2691 2690
2692 2691 return (DDI_SUCCESS);
2693 2692 }
2694 2693
2695 2694 int
2696 2695 _info(struct modinfo *modinfop)
2697 2696 {
2698 2697 return (mod_info(&modlinkage, modinfop));
2699 2698 }
2700 2699
2701 2700 int
2702 2701 _init(void)
2703 2702 {
2704 2703 int status;
2705 2704
2706 2705 status = ddi_soft_state_init(&ral_soft_state_p,
2707 2706 sizeof (struct rt2560_softc), 1);
2708 2707 if (status != 0)
2709 2708 return (status);
2710 2709
2711 2710 mac_init_ops(&ral_dev_ops, "ral");
2712 2711 status = mod_install(&modlinkage);
2713 2712 if (status != 0) {
2714 2713 mac_fini_ops(&ral_dev_ops);
2715 2714 ddi_soft_state_fini(&ral_soft_state_p);
2716 2715 }
2717 2716 return (status);
2718 2717 }
2719 2718
2720 2719 int
2721 2720 _fini(void)
2722 2721 {
2723 2722 int status;
2724 2723
2725 2724 status = mod_remove(&modlinkage);
2726 2725 if (status == 0) {
2727 2726 mac_fini_ops(&ral_dev_ops);
2728 2727 ddi_soft_state_fini(&ral_soft_state_p);
2729 2728 }
2730 2729 return (status);
2731 2730 }
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