Print this page
7127 remove -Wno-missing-braces from Makefile.uts
| Split |
Close |
| Expand all |
| Collapse all |
--- old/usr/src/uts/common/io/pciex/pcieb.c
+++ new/usr/src/uts/common/io/pciex/pcieb.c
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21 /*
22 22 * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved.
23 23 */
24 24 /*
25 25 * Copyright 2012 Garrett D'Amore <garrett@damore.org>. All rights reserved.
26 26 */
27 27
28 28 /*
29 29 * Common x86 and SPARC PCI-E to PCI bus bridge nexus driver
30 30 */
31 31
32 32 #include <sys/sysmacros.h>
33 33 #include <sys/conf.h>
34 34 #include <sys/kmem.h>
35 35 #include <sys/debug.h>
36 36 #include <sys/modctl.h>
37 37 #include <sys/autoconf.h>
38 38 #include <sys/ddi_impldefs.h>
39 39 #include <sys/pci.h>
40 40 #include <sys/ddi.h>
41 41 #include <sys/sunddi.h>
42 42 #include <sys/sunndi.h>
43 43 #include <sys/fm/util.h>
44 44 #include <sys/pci_cap.h>
45 45 #include <sys/pci_impl.h>
46 46 #include <sys/pcie_impl.h>
47 47 #include <sys/open.h>
48 48 #include <sys/stat.h>
49 49 #include <sys/file.h>
50 50 #include <sys/promif.h> /* prom_printf */
51 51 #include <sys/disp.h>
52 52 #include <sys/pcie_pwr.h>
53 53 #include <sys/hotplug/pci/pcie_hp.h>
54 54 #include "pcieb.h"
55 55 #ifdef PX_PLX
56 56 #include <io/pciex/pcieb_plx.h>
57 57 #endif /* PX_PLX */
58 58
59 59 /*LINTLIBRARY*/
60 60
61 61 /* panic flag */
62 62 int pcieb_die = PF_ERR_FATAL_FLAGS;
63 63 int pcieb_disable_41210_wkarnd = 0;
64 64
65 65 /* flag to turn on MSI support */
66 66 int pcieb_enable_msi = 1;
67 67
68 68 #if defined(DEBUG)
69 69 uint_t pcieb_dbg_print = 0;
70 70
71 71 static char *pcieb_debug_sym [] = { /* same sequence as pcieb_debug_bit */
72 72 /* 0 */ "attach",
73 73 /* 1 */ "pwr",
74 74 /* 2 */ "intr"
75 75 };
76 76 #endif /* DEBUG */
77 77
78 78 static int pcieb_bus_map(dev_info_t *, dev_info_t *, ddi_map_req_t *, off_t,
79 79 off_t, caddr_t *);
80 80 static int pcieb_ctlops(dev_info_t *, dev_info_t *, ddi_ctl_enum_t, void *,
81 81 void *);
82 82 static int pcieb_fm_init(pcieb_devstate_t *pcieb_p);
83 83 static void pcieb_fm_fini(pcieb_devstate_t *pcieb_p);
84 84 static int pcieb_fm_init_child(dev_info_t *dip, dev_info_t *cdip, int cap,
85 85 ddi_iblock_cookie_t *ibc_p);
86 86 static int pcieb_dma_allochdl(dev_info_t *dip, dev_info_t *rdip,
87 87 ddi_dma_attr_t *attr_p, int (*waitfp)(caddr_t), caddr_t arg,
88 88 ddi_dma_handle_t *handlep);
89 89 static int pcieb_dma_mctl(dev_info_t *dip, dev_info_t *rdip,
90 90 ddi_dma_handle_t handle, enum ddi_dma_ctlops cmd, off_t *offp,
91 91 size_t *lenp, caddr_t *objp, uint_t cache_flags);
92 92 static int pcieb_intr_ops(dev_info_t *dip, dev_info_t *rdip,
93 93 ddi_intr_op_t intr_op, ddi_intr_handle_impl_t *hdlp, void *result);
94 94
95 95 static struct bus_ops pcieb_bus_ops = {
96 96 BUSO_REV,
97 97 pcieb_bus_map,
98 98 0,
99 99 0,
100 100 0,
101 101 i_ddi_map_fault,
102 102 0,
103 103 pcieb_dma_allochdl,
104 104 ddi_dma_freehdl,
105 105 ddi_dma_bindhdl,
106 106 ddi_dma_unbindhdl,
107 107 ddi_dma_flush,
108 108 ddi_dma_win,
109 109 pcieb_dma_mctl,
110 110 pcieb_ctlops,
111 111 ddi_bus_prop_op,
112 112 ndi_busop_get_eventcookie, /* (*bus_get_eventcookie)(); */
113 113 ndi_busop_add_eventcall, /* (*bus_add_eventcall)(); */
114 114 ndi_busop_remove_eventcall, /* (*bus_remove_eventcall)(); */
115 115 ndi_post_event, /* (*bus_post_event)(); */
116 116 NULL, /* (*bus_intr_ctl)(); */
117 117 NULL, /* (*bus_config)(); */
118 118 NULL, /* (*bus_unconfig)(); */
119 119 pcieb_fm_init_child, /* (*bus_fm_init)(); */
120 120 NULL, /* (*bus_fm_fini)(); */
121 121 i_ndi_busop_access_enter, /* (*bus_fm_access_enter)(); */
122 122 i_ndi_busop_access_exit, /* (*bus_fm_access_exit)(); */
123 123 pcie_bus_power, /* (*bus_power)(); */
124 124 pcieb_intr_ops, /* (*bus_intr_op)(); */
125 125 pcie_hp_common_ops /* (*bus_hp_op)(); */
126 126 };
127 127
128 128 static int pcieb_open(dev_t *, int, int, cred_t *);
129 129 static int pcieb_close(dev_t, int, int, cred_t *);
130 130 static int pcieb_ioctl(dev_t, int, intptr_t, int, cred_t *, int *);
131 131 static int pcieb_info(dev_info_t *, ddi_info_cmd_t, void *, void **);
132 132 static uint_t pcieb_intr_handler(caddr_t arg1, caddr_t arg2);
133 133
134 134 /* PM related functions */
135 135 static int pcieb_pwr_setup(dev_info_t *dip);
136 136 static int pcieb_pwr_init_and_raise(dev_info_t *dip, pcie_pwr_t *pwr_p);
137 137 static void pcieb_pwr_teardown(dev_info_t *dip);
138 138 static int pcieb_pwr_disable(dev_info_t *dip);
139 139
140 140 /* Hotplug related functions */
141 141 static void pcieb_id_props(pcieb_devstate_t *pcieb);
142 142
143 143 /*
144 144 * soft state pointer
145 145 */
146 146 void *pcieb_state;
147 147
148 148 static struct cb_ops pcieb_cb_ops = {
149 149 pcieb_open, /* open */
150 150 pcieb_close, /* close */
151 151 nodev, /* strategy */
152 152 nodev, /* print */
153 153 nodev, /* dump */
154 154 nodev, /* read */
155 155 nodev, /* write */
156 156 pcieb_ioctl, /* ioctl */
157 157 nodev, /* devmap */
158 158 nodev, /* mmap */
159 159 nodev, /* segmap */
160 160 nochpoll, /* poll */
161 161 pcie_prop_op, /* cb_prop_op */
162 162 NULL, /* streamtab */
163 163 D_NEW | D_MP | D_HOTPLUG, /* Driver compatibility flag */
164 164 CB_REV, /* rev */
165 165 nodev, /* int (*cb_aread)() */
166 166 nodev /* int (*cb_awrite)() */
167 167 };
168 168
169 169 static int pcieb_probe(dev_info_t *);
170 170 static int pcieb_attach(dev_info_t *devi, ddi_attach_cmd_t cmd);
171 171 static int pcieb_detach(dev_info_t *devi, ddi_detach_cmd_t cmd);
172 172
173 173 static struct dev_ops pcieb_ops = {
174 174 DEVO_REV, /* devo_rev */
175 175 0, /* refcnt */
176 176 pcieb_info, /* info */
177 177 nulldev, /* identify */
178 178 pcieb_probe, /* probe */
179 179 pcieb_attach, /* attach */
180 180 pcieb_detach, /* detach */
181 181 nulldev, /* reset */
182 182 &pcieb_cb_ops, /* driver operations */
183 183 &pcieb_bus_ops, /* bus operations */
184 184 pcie_power, /* power */
185 185 ddi_quiesce_not_needed, /* quiesce */
186 186 };
187 187
188 188 /*
189 189 * Module linkage information for the kernel.
|
↓ open down ↓ |
189 lines elided |
↑ open up ↑ |
190 190 */
191 191
192 192 static struct modldrv modldrv = {
193 193 &mod_driverops, /* Type of module */
194 194 "PCIe bridge/switch driver",
195 195 &pcieb_ops, /* driver ops */
196 196 };
197 197
198 198 static struct modlinkage modlinkage = {
199 199 MODREV_1,
200 - (void *)&modldrv,
201 - NULL
200 + { (void *)&modldrv, NULL }
202 201 };
203 202
204 203 /*
205 204 * forward function declarations:
206 205 */
207 206 static void pcieb_uninitchild(dev_info_t *);
208 207 static int pcieb_initchild(dev_info_t *child);
209 208 static void pcieb_create_ranges_prop(dev_info_t *, ddi_acc_handle_t);
210 209 static boolean_t pcieb_is_pcie_device_type(dev_info_t *dip);
211 210
212 211 /* interrupt related declarations */
213 212 static int pcieb_msi_supported(dev_info_t *);
214 213 static int pcieb_intr_attach(pcieb_devstate_t *pcieb);
215 214 static int pcieb_intr_init(pcieb_devstate_t *pcieb_p, int intr_type);
216 215 static void pcieb_intr_fini(pcieb_devstate_t *pcieb_p);
217 216
218 217 int
219 218 _init(void)
220 219 {
221 220 int e;
222 221
223 222 if ((e = ddi_soft_state_init(&pcieb_state, sizeof (pcieb_devstate_t),
224 223 1)) == 0 && (e = mod_install(&modlinkage)) != 0)
225 224 ddi_soft_state_fini(&pcieb_state);
226 225 return (e);
227 226 }
228 227
229 228 int
230 229 _fini(void)
231 230 {
232 231 int e;
233 232
234 233 if ((e = mod_remove(&modlinkage)) == 0) {
235 234 ddi_soft_state_fini(&pcieb_state);
236 235 }
237 236 return (e);
238 237 }
239 238
240 239 int
241 240 _info(struct modinfo *modinfop)
242 241 {
243 242 return (mod_info(&modlinkage, modinfop));
244 243 }
245 244
246 245 /* ARGSUSED */
247 246 static int
248 247 pcieb_info(dev_info_t *dip, ddi_info_cmd_t infocmd, void *arg, void **result)
249 248 {
250 249 minor_t minor = getminor((dev_t)arg);
251 250 int instance = PCI_MINOR_NUM_TO_INSTANCE(minor);
252 251 pcieb_devstate_t *pcieb = ddi_get_soft_state(pcieb_state, instance);
253 252 int ret = DDI_SUCCESS;
254 253
255 254 switch (infocmd) {
256 255 case DDI_INFO_DEVT2INSTANCE:
257 256 *result = (void *)(intptr_t)instance;
258 257 break;
259 258 case DDI_INFO_DEVT2DEVINFO:
260 259 if (pcieb == NULL) {
261 260 ret = DDI_FAILURE;
262 261 break;
263 262 }
264 263
265 264 *result = (void *)pcieb->pcieb_dip;
266 265 break;
267 266 default:
268 267 ret = DDI_FAILURE;
269 268 break;
270 269 }
271 270
272 271 return (ret);
273 272 }
274 273
275 274
276 275 /*ARGSUSED*/
277 276 static int
278 277 pcieb_probe(dev_info_t *devi)
279 278 {
280 279 return (DDI_PROBE_SUCCESS);
281 280 }
282 281
283 282 /*
284 283 * This is a workaround for an undocumented HW erratum with the
285 284 * multi-function, F0 and F2, Intel 41210 PCIe-to-PCI bridge. When
286 285 * Fn (cdip) attaches, this workaround is called to initialize Fn's
287 286 * sibling (sdip) with MPS/MRRS if it isn't already configured.
288 287 * Doing so prevents a malformed TLP panic.
289 288 */
290 289 static void
291 290 pcieb_41210_mps_wkrnd(dev_info_t *cdip)
292 291 {
293 292 dev_info_t *sdip;
294 293 ddi_acc_handle_t cfg_hdl;
295 294 uint16_t cdip_dev_ctrl, cdip_mrrs_mps;
296 295 pcie_bus_t *cdip_bus_p = PCIE_DIP2BUS(cdip);
297 296
298 297 /* Get cdip's MPS/MRRS already setup by pcie_initchild_mps() */
299 298 ASSERT(cdip_bus_p);
300 299 cdip_dev_ctrl = PCIE_CAP_GET(16, cdip_bus_p, PCIE_DEVCTL);
301 300 cdip_mrrs_mps = cdip_dev_ctrl &
302 301 (PCIE_DEVCTL_MAX_READ_REQ_MASK | PCIE_DEVCTL_MAX_PAYLOAD_MASK);
303 302
304 303 /* Locate sdip and set its MPS/MRRS when applicable */
305 304 for (sdip = ddi_get_child(ddi_get_parent(cdip)); sdip;
306 305 sdip = ddi_get_next_sibling(sdip)) {
307 306 uint16_t sdip_dev_ctrl, sdip_mrrs_mps, cap_ptr;
308 307 uint32_t bus_dev_ven_id;
309 308
310 309 if (sdip == cdip || pci_config_setup(sdip, &cfg_hdl)
311 310 != DDI_SUCCESS)
312 311 continue;
313 312
314 313 /* must be an Intel 41210 bridge */
315 314 bus_dev_ven_id = pci_config_get32(cfg_hdl, PCI_CONF_VENID);
316 315 if (!PCIEB_IS_41210_BRIDGE(bus_dev_ven_id)) {
317 316 pci_config_teardown(&cfg_hdl);
318 317 continue;
319 318 }
320 319
321 320 if (PCI_CAP_LOCATE(cfg_hdl, PCI_CAP_ID_PCI_E, &cap_ptr)
322 321 != DDI_SUCCESS) {
323 322 pci_config_teardown(&cfg_hdl);
324 323 continue;
325 324 }
326 325
327 326 /* get sdip's MPS/MRRS to compare to cdip's */
328 327 sdip_dev_ctrl = PCI_CAP_GET16(cfg_hdl, NULL, cap_ptr,
329 328 PCIE_DEVCTL);
330 329 sdip_mrrs_mps = sdip_dev_ctrl &
331 330 (PCIE_DEVCTL_MAX_READ_REQ_MASK |
332 331 PCIE_DEVCTL_MAX_PAYLOAD_MASK);
333 332
334 333 /* if sdip already attached then its MPS/MRRS is configured */
335 334 if (i_ddi_devi_attached(sdip)) {
336 335 ASSERT(sdip_mrrs_mps == cdip_mrrs_mps);
337 336 pci_config_teardown(&cfg_hdl);
338 337 continue;
339 338 }
340 339
341 340 /* otherwise, update sdip's MPS/MRRS if different from cdip's */
342 341 if (sdip_mrrs_mps != cdip_mrrs_mps) {
343 342 sdip_dev_ctrl = (sdip_dev_ctrl &
344 343 ~(PCIE_DEVCTL_MAX_READ_REQ_MASK |
345 344 PCIE_DEVCTL_MAX_PAYLOAD_MASK)) | cdip_mrrs_mps;
346 345
347 346 PCI_CAP_PUT16(cfg_hdl, NULL, cap_ptr, PCIE_DEVCTL,
348 347 sdip_dev_ctrl);
349 348 }
350 349
351 350 /*
352 351 * note: sdip's bus_mps will be updated by
353 352 * pcie_initchild_mps()
354 353 */
355 354
356 355 pci_config_teardown(&cfg_hdl);
357 356
358 357 break;
359 358 }
360 359 }
361 360
362 361 static int
363 362 pcieb_attach(dev_info_t *devi, ddi_attach_cmd_t cmd)
364 363 {
365 364 int instance;
366 365 char device_type[8];
367 366 pcieb_devstate_t *pcieb;
368 367 pcie_bus_t *bus_p = PCIE_DIP2UPBUS(devi);
369 368 ddi_acc_handle_t config_handle = bus_p->bus_cfg_hdl;
370 369
371 370 switch (cmd) {
372 371 case DDI_RESUME:
373 372 (void) pcie_pwr_resume(devi);
374 373 return (DDI_SUCCESS);
375 374
376 375 default:
377 376 return (DDI_FAILURE);
378 377
379 378 case DDI_ATTACH:
380 379 break;
381 380 }
382 381
383 382 if (!(PCIE_IS_BDG(bus_p))) {
384 383 PCIEB_DEBUG(DBG_ATTACH, devi, "This is not a switch or"
385 384 " bridge\n");
386 385 return (DDI_FAILURE);
387 386 }
388 387
389 388 /*
390 389 * If PCIE_LINKCTL_LINK_DISABLE bit in the PCIe Config
391 390 * Space (PCIe Capability Link Control Register) is set,
392 391 * then do not bind the driver.
393 392 */
394 393 if (PCIE_CAP_GET(16, bus_p, PCIE_LINKCTL) & PCIE_LINKCTL_LINK_DISABLE)
395 394 return (DDI_FAILURE);
396 395
397 396 /*
398 397 * Allocate and get soft state structure.
399 398 */
400 399 instance = ddi_get_instance(devi);
401 400 if (ddi_soft_state_zalloc(pcieb_state, instance) != DDI_SUCCESS)
402 401 return (DDI_FAILURE);
403 402 pcieb = ddi_get_soft_state(pcieb_state, instance);
404 403 pcieb->pcieb_dip = devi;
405 404
406 405 if ((pcieb_fm_init(pcieb)) != DDI_SUCCESS) {
407 406 PCIEB_DEBUG(DBG_ATTACH, devi, "Failed in pcieb_fm_init\n");
408 407 goto fail;
409 408 }
410 409 pcieb->pcieb_init_flags |= PCIEB_INIT_FM;
411 410
412 411 mutex_init(&pcieb->pcieb_mutex, NULL, MUTEX_DRIVER, NULL);
413 412 mutex_init(&pcieb->pcieb_err_mutex, NULL, MUTEX_DRIVER,
414 413 (void *)pcieb->pcieb_fm_ibc);
415 414 mutex_init(&pcieb->pcieb_peek_poke_mutex, NULL, MUTEX_DRIVER,
416 415 (void *)pcieb->pcieb_fm_ibc);
417 416
418 417 /* create special properties for device identification */
419 418 pcieb_id_props(pcieb);
420 419
421 420 /*
422 421 * Power management setup. This also makes sure that switch/bridge
423 422 * is at D0 during attach.
424 423 */
425 424 if (pwr_common_setup(devi) != DDI_SUCCESS) {
426 425 PCIEB_DEBUG(DBG_PWR, devi, "pwr_common_setup failed\n");
427 426 goto fail;
428 427 }
429 428
430 429 if (pcieb_pwr_setup(devi) != DDI_SUCCESS) {
431 430 PCIEB_DEBUG(DBG_PWR, devi, "pxb_pwr_setup failed \n");
432 431 goto fail;
433 432 }
434 433
435 434 /*
436 435 * Make sure the "device_type" property exists.
437 436 */
438 437 if (pcieb_is_pcie_device_type(devi))
439 438 (void) strcpy(device_type, "pciex");
440 439 else
441 440 (void) strcpy(device_type, "pci");
442 441
443 442 (void) ddi_prop_update_string(DDI_DEV_T_NONE, devi,
444 443 "device_type", device_type);
445 444
446 445 /*
447 446 * Check whether the "ranges" property is present.
448 447 * Otherwise create the ranges property by reading
449 448 * the configuration registers
450 449 */
451 450 if (ddi_prop_exists(DDI_DEV_T_ANY, devi, DDI_PROP_DONTPASS,
452 451 "ranges") == 0) {
453 452 pcieb_create_ranges_prop(devi, config_handle);
454 453 }
455 454
456 455 if (PCIE_IS_PCI_BDG(bus_p))
457 456 pcieb_set_pci_perf_parameters(devi, config_handle);
458 457
459 458 #ifdef PX_PLX
460 459 pcieb_attach_plx_workarounds(pcieb);
461 460 #endif /* PX_PLX */
462 461
463 462 if (pcie_init(devi, NULL) != DDI_SUCCESS)
464 463 goto fail;
465 464
466 465 /* Intel PCIe-to-PCI 41210 bridge workaround -- if applicable */
467 466 if (pcieb_disable_41210_wkarnd == 0 &&
468 467 PCIEB_IS_41210_BRIDGE(bus_p->bus_dev_ven_id))
469 468 pcieb_41210_mps_wkrnd(devi);
470 469
471 470 /*
472 471 * Initialize interrupt handlers. Ignore return value.
473 472 */
474 473 (void) pcieb_intr_attach(pcieb);
475 474
476 475 (void) pcie_hpintr_enable(devi);
477 476
478 477 /* Do any platform specific workarounds needed at this time */
479 478 pcieb_plat_attach_workaround(devi);
480 479
481 480 /*
482 481 * If this is a root port, determine and set the max payload size.
483 482 * Since this will involve scanning the fabric, all error enabling
484 483 * and sw workarounds should be in place before doing this.
485 484 */
486 485 if (PCIE_IS_RP(bus_p))
487 486 pcie_init_root_port_mps(devi);
488 487
489 488 ddi_report_dev(devi);
490 489 return (DDI_SUCCESS);
491 490
492 491 fail:
493 492 (void) pcieb_detach(devi, DDI_DETACH);
494 493 return (DDI_FAILURE);
495 494 }
496 495
497 496 static int
498 497 pcieb_detach(dev_info_t *devi, ddi_detach_cmd_t cmd)
499 498 {
500 499 pcieb_devstate_t *pcieb;
501 500 int error = DDI_SUCCESS;
502 501
503 502 switch (cmd) {
504 503 case DDI_SUSPEND:
505 504 error = pcie_pwr_suspend(devi);
506 505 return (error);
507 506
508 507 case DDI_DETACH:
509 508 break;
510 509
511 510 default:
512 511 return (DDI_FAILURE);
513 512 }
514 513
515 514 pcieb = ddi_get_soft_state(pcieb_state, ddi_get_instance(devi));
516 515
517 516 /* disable hotplug interrupt */
518 517 (void) pcie_hpintr_disable(devi);
519 518
520 519 /* remove interrupt handlers */
521 520 pcieb_intr_fini(pcieb);
522 521
523 522 /* uninitialize inband PCI-E HPC if present */
524 523 (void) pcie_uninit(devi);
525 524
526 525 (void) ddi_prop_remove(DDI_DEV_T_NONE, devi, "device_type");
527 526
528 527 (void) ndi_prop_remove(DDI_DEV_T_NONE, pcieb->pcieb_dip,
529 528 "pcie_ce_mask");
530 529
531 530 if (pcieb->pcieb_init_flags & PCIEB_INIT_FM)
532 531 pcieb_fm_fini(pcieb);
533 532
534 533 pcieb_pwr_teardown(devi);
535 534 pwr_common_teardown(devi);
536 535
537 536 mutex_destroy(&pcieb->pcieb_peek_poke_mutex);
538 537 mutex_destroy(&pcieb->pcieb_err_mutex);
539 538 mutex_destroy(&pcieb->pcieb_mutex);
540 539
541 540 /*
542 541 * And finally free the per-pci soft state.
543 542 */
544 543 ddi_soft_state_free(pcieb_state, ddi_get_instance(devi));
545 544
546 545 return (DDI_SUCCESS);
547 546 }
548 547
549 548 static int
550 549 pcieb_bus_map(dev_info_t *dip, dev_info_t *rdip, ddi_map_req_t *mp,
551 550 off_t offset, off_t len, caddr_t *vaddrp)
552 551 {
553 552 dev_info_t *pdip;
554 553
555 554 if (PCIE_IS_RP(PCIE_DIP2BUS(dip)) && mp->map_handlep != NULL) {
556 555 ddi_acc_impl_t *hdlp =
557 556 (ddi_acc_impl_t *)(mp->map_handlep)->ah_platform_private;
558 557
559 558 pcieb_set_prot_scan(dip, hdlp);
560 559 }
561 560 pdip = (dev_info_t *)DEVI(dip)->devi_parent;
562 561 return ((DEVI(pdip)->devi_ops->devo_bus_ops->bus_map)(pdip, rdip, mp,
563 562 offset, len, vaddrp));
564 563 }
565 564
566 565 static int
567 566 pcieb_ctlops(dev_info_t *dip, dev_info_t *rdip, ddi_ctl_enum_t ctlop,
568 567 void *arg, void *result)
569 568 {
570 569 pci_regspec_t *drv_regp;
571 570 int reglen;
572 571 int rn;
573 572 int totreg;
574 573 pcieb_devstate_t *pcieb = ddi_get_soft_state(pcieb_state,
575 574 ddi_get_instance(dip));
576 575 struct detachspec *ds;
577 576 struct attachspec *as;
578 577
579 578 switch (ctlop) {
580 579 case DDI_CTLOPS_REPORTDEV:
581 580 if (rdip == (dev_info_t *)0)
582 581 return (DDI_FAILURE);
583 582
584 583 if (ddi_get_parent(rdip) == dip) {
585 584 cmn_err(CE_CONT, "?PCIE-device: %s@%s, %s%d\n",
586 585 ddi_node_name(rdip), ddi_get_name_addr(rdip),
587 586 ddi_driver_name(rdip), ddi_get_instance(rdip));
588 587 }
589 588
590 589 /* Pass it up for fabric sync */
591 590 (void) ddi_ctlops(dip, rdip, ctlop, arg, result);
592 591 return (DDI_SUCCESS);
593 592
594 593 case DDI_CTLOPS_INITCHILD:
595 594 return (pcieb_initchild((dev_info_t *)arg));
596 595
597 596 case DDI_CTLOPS_UNINITCHILD:
598 597 pcieb_uninitchild((dev_info_t *)arg);
599 598 return (DDI_SUCCESS);
600 599
601 600 case DDI_CTLOPS_SIDDEV:
602 601 return (DDI_SUCCESS);
603 602
604 603 case DDI_CTLOPS_REGSIZE:
605 604 case DDI_CTLOPS_NREGS:
606 605 if (rdip == (dev_info_t *)0)
607 606 return (DDI_FAILURE);
608 607 break;
609 608
610 609 case DDI_CTLOPS_PEEK:
611 610 case DDI_CTLOPS_POKE:
612 611 return (pcieb_plat_peekpoke(dip, rdip, ctlop, arg, result));
613 612 case DDI_CTLOPS_ATTACH:
614 613 if (!pcie_is_child(dip, rdip))
615 614 return (DDI_SUCCESS);
616 615
617 616 as = (struct attachspec *)arg;
618 617 switch (as->when) {
619 618 case DDI_PRE:
620 619 if (as->cmd == DDI_RESUME) {
621 620 pcie_clear_errors(rdip);
622 621 if (pcieb_plat_ctlops(rdip, ctlop, arg) !=
623 622 DDI_SUCCESS)
624 623 return (DDI_FAILURE);
625 624 }
626 625
627 626 if (as->cmd == DDI_ATTACH)
628 627 return (pcie_pm_hold(dip));
629 628
630 629 return (DDI_SUCCESS);
631 630
632 631 case DDI_POST:
633 632 if (as->cmd == DDI_ATTACH &&
634 633 as->result != DDI_SUCCESS) {
635 634 /*
636 635 * Attach failed for the child device. The child
637 636 * driver may have made PM calls before the
638 637 * attach failed. pcie_pm_remove_child() should
639 638 * cleanup PM state and holds (if any)
640 639 * associated with the child device.
641 640 */
642 641 return (pcie_pm_remove_child(dip, rdip));
643 642 }
644 643
645 644 if (as->result == DDI_SUCCESS) {
646 645 pf_init(rdip, (void *)pcieb->pcieb_fm_ibc,
647 646 as->cmd);
648 647
649 648 (void) pcieb_plat_ctlops(rdip, ctlop, arg);
650 649 }
651 650
652 651 /*
653 652 * For empty hotplug-capable slots, we should explicitly
654 653 * disable the errors, so that we won't panic upon
655 654 * unsupported hotplug messages.
656 655 */
657 656 if ((!ddi_prop_exists(DDI_DEV_T_ANY, rdip,
658 657 DDI_PROP_DONTPASS, "hotplug-capable")) ||
659 658 ddi_get_child(rdip)) {
660 659 (void) pcie_postattach_child(rdip);
661 660 return (DDI_SUCCESS);
662 661 }
663 662
664 663 pcie_disable_errors(rdip);
665 664
666 665 return (DDI_SUCCESS);
667 666 default:
668 667 break;
669 668 }
670 669 return (DDI_SUCCESS);
671 670
672 671 case DDI_CTLOPS_DETACH:
673 672 if (!pcie_is_child(dip, rdip))
674 673 return (DDI_SUCCESS);
675 674
676 675 ds = (struct detachspec *)arg;
677 676 switch (ds->when) {
678 677 case DDI_PRE:
679 678 pf_fini(rdip, ds->cmd);
680 679 return (DDI_SUCCESS);
681 680
682 681 case DDI_POST:
683 682 if (pcieb_plat_ctlops(rdip, ctlop, arg) != DDI_SUCCESS)
684 683 return (DDI_FAILURE);
685 684 if (ds->cmd == DDI_DETACH &&
686 685 ds->result == DDI_SUCCESS) {
687 686 return (pcie_pm_remove_child(dip, rdip));
688 687 }
689 688 return (DDI_SUCCESS);
690 689 default:
691 690 break;
692 691 }
693 692 return (DDI_SUCCESS);
694 693 default:
695 694 return (ddi_ctlops(dip, rdip, ctlop, arg, result));
696 695 }
697 696
698 697 *(int *)result = 0;
699 698 if (ddi_getlongprop(DDI_DEV_T_ANY, rdip,
700 699 DDI_PROP_DONTPASS | DDI_PROP_CANSLEEP, "reg", (caddr_t)&drv_regp,
701 700 ®len) != DDI_SUCCESS)
702 701 return (DDI_FAILURE);
703 702
704 703 totreg = reglen / sizeof (pci_regspec_t);
705 704 if (ctlop == DDI_CTLOPS_NREGS)
706 705 *(int *)result = totreg;
707 706 else if (ctlop == DDI_CTLOPS_REGSIZE) {
708 707 rn = *(int *)arg;
709 708 if (rn >= totreg) {
710 709 kmem_free(drv_regp, reglen);
711 710 return (DDI_FAILURE);
712 711 }
713 712
714 713 *(off_t *)result = drv_regp[rn].pci_size_low |
715 714 ((uint64_t)drv_regp[rn].pci_size_hi << 32);
716 715 }
717 716
718 717 kmem_free(drv_regp, reglen);
719 718 return (DDI_SUCCESS);
720 719 }
721 720
722 721 /*
723 722 * name_child
724 723 *
725 724 * This function is called from init_child to name a node. It is
726 725 * also passed as a callback for node merging functions.
727 726 *
728 727 * return value: DDI_SUCCESS, DDI_FAILURE
729 728 */
730 729 static int
731 730 pcieb_name_child(dev_info_t *child, char *name, int namelen)
732 731 {
733 732 pci_regspec_t *pci_rp;
734 733 uint_t device, func;
735 734 char **unit_addr;
736 735 uint_t n;
737 736
738 737 /*
739 738 * For .conf nodes, use unit-address property as name
740 739 */
741 740 if (ndi_dev_is_persistent_node(child) == 0) {
742 741 if (ddi_prop_lookup_string_array(DDI_DEV_T_ANY, child,
743 742 DDI_PROP_DONTPASS, "unit-address", &unit_addr, &n) !=
744 743 DDI_PROP_SUCCESS) {
745 744 cmn_err(CE_WARN,
746 745 "cannot find unit-address in %s.conf",
747 746 ddi_driver_name(child));
748 747 return (DDI_FAILURE);
749 748 }
750 749 if (n != 1 || *unit_addr == NULL || **unit_addr == 0) {
751 750 cmn_err(CE_WARN, "unit-address property in %s.conf"
752 751 " not well-formed", ddi_driver_name(child));
753 752 ddi_prop_free(unit_addr);
754 753 return (DDI_FAILURE);
755 754 }
756 755 (void) snprintf(name, namelen, "%s", *unit_addr);
757 756 ddi_prop_free(unit_addr);
758 757 return (DDI_SUCCESS);
759 758 }
760 759
761 760 /*
762 761 * Get the address portion of the node name based on
763 762 * the function and device number.
764 763 */
765 764 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, child,
766 765 DDI_PROP_DONTPASS, "reg", (int **)&pci_rp, &n) != DDI_SUCCESS) {
767 766 return (DDI_FAILURE);
768 767 }
769 768
770 769 /* copy the device identifications */
771 770 device = PCI_REG_DEV_G(pci_rp[0].pci_phys_hi);
772 771 func = PCI_REG_FUNC_G(pci_rp[0].pci_phys_hi);
773 772
774 773 if (pcie_ari_is_enabled(ddi_get_parent(child))
775 774 == PCIE_ARI_FORW_ENABLED) {
776 775 func = (device << 3) | func;
777 776 device = 0;
778 777 }
779 778
780 779 if (func != 0)
781 780 (void) snprintf(name, namelen, "%x,%x", device, func);
782 781 else
783 782 (void) snprintf(name, namelen, "%x", device);
784 783
785 784 ddi_prop_free(pci_rp);
786 785 return (DDI_SUCCESS);
787 786 }
788 787
789 788 static int
790 789 pcieb_initchild(dev_info_t *child)
791 790 {
792 791 char name[MAXNAMELEN];
793 792 int result = DDI_FAILURE;
794 793 pcieb_devstate_t *pcieb =
795 794 (pcieb_devstate_t *)ddi_get_soft_state(pcieb_state,
796 795 ddi_get_instance(ddi_get_parent(child)));
797 796
798 797 /*
799 798 * Name the child
800 799 */
801 800 if (pcieb_name_child(child, name, MAXNAMELEN) != DDI_SUCCESS) {
802 801 result = DDI_FAILURE;
803 802 goto done;
804 803 }
805 804 ddi_set_name_addr(child, name);
806 805
807 806 /*
808 807 * Pseudo nodes indicate a prototype node with per-instance
809 808 * properties to be merged into the real h/w device node.
810 809 * The interpretation of the unit-address is DD[,F]
811 810 * where DD is the device id and F is the function.
812 811 */
813 812 if (ndi_dev_is_persistent_node(child) == 0) {
814 813 extern int pci_allow_pseudo_children;
815 814
816 815 /*
817 816 * Try to merge the properties from this prototype
818 817 * node into real h/w nodes.
819 818 */
820 819 if (ndi_merge_node(child, pcieb_name_child) == DDI_SUCCESS) {
821 820 /*
822 821 * Merged ok - return failure to remove the node.
823 822 */
824 823 ddi_set_name_addr(child, NULL);
825 824 result = DDI_FAILURE;
826 825 goto done;
827 826 }
828 827
829 828 /* workaround for ddivs to run under PCI-E */
830 829 if (pci_allow_pseudo_children) {
831 830 result = DDI_SUCCESS;
832 831 goto done;
833 832 }
834 833
835 834 /*
836 835 * The child was not merged into a h/w node,
837 836 * but there's not much we can do with it other
838 837 * than return failure to cause the node to be removed.
839 838 */
840 839 cmn_err(CE_WARN, "!%s@%s: %s.conf properties not merged",
841 840 ddi_driver_name(child), ddi_get_name_addr(child),
842 841 ddi_driver_name(child));
843 842 ddi_set_name_addr(child, NULL);
844 843 result = DDI_NOT_WELL_FORMED;
845 844 goto done;
846 845 }
847 846
848 847 /* platform specific initchild */
849 848 pcieb_plat_initchild(child);
850 849
851 850 if (pcie_pm_hold(pcieb->pcieb_dip) != DDI_SUCCESS) {
852 851 PCIEB_DEBUG(DBG_PWR, pcieb->pcieb_dip,
853 852 "INITCHILD: px_pm_hold failed\n");
854 853 result = DDI_FAILURE;
855 854 goto done;
856 855 }
857 856 /* Any return from here must call pcie_pm_release */
858 857
859 858 /*
860 859 * If configuration registers were previously saved by
861 860 * child (before it entered D3), then let the child do the
862 861 * restore to set up the config regs as it'll first need to
863 862 * power the device out of D3.
864 863 */
865 864 if (ddi_prop_exists(DDI_DEV_T_ANY, child, DDI_PROP_DONTPASS,
866 865 "config-regs-saved-by-child") == 1) {
867 866 PCIEB_DEBUG(DBG_PWR, ddi_get_parent(child),
868 867 "INITCHILD: config regs to be restored by child"
869 868 " for %s@%s\n", ddi_node_name(child),
870 869 ddi_get_name_addr(child));
871 870
872 871 result = DDI_SUCCESS;
873 872 goto cleanup;
874 873 }
875 874
876 875 PCIEB_DEBUG(DBG_PWR, ddi_get_parent(child),
877 876 "INITCHILD: config regs setup for %s@%s\n",
878 877 ddi_node_name(child), ddi_get_name_addr(child));
879 878
880 879 pcie_init_dom(child);
881 880
882 881 if (pcie_initchild(child) != DDI_SUCCESS) {
883 882 result = DDI_FAILURE;
884 883 pcie_fini_dom(child);
885 884 goto cleanup;
886 885 }
887 886
888 887 #ifdef PX_PLX
889 888 if (pcieb_init_plx_workarounds(pcieb, child) == DDI_FAILURE) {
890 889 result = DDI_FAILURE;
891 890 pcie_fini_dom(child);
892 891 goto cleanup;
893 892 }
894 893 #endif /* PX_PLX */
895 894
896 895 result = DDI_SUCCESS;
897 896 cleanup:
898 897 pcie_pm_release(pcieb->pcieb_dip);
899 898 done:
900 899 return (result);
901 900 }
902 901
903 902 static void
904 903 pcieb_uninitchild(dev_info_t *dip)
905 904 {
906 905
907 906 pcie_uninitchild(dip);
908 907
909 908 pcieb_plat_uninitchild(dip);
910 909
911 910 ddi_set_name_addr(dip, NULL);
912 911
913 912 /*
914 913 * Strip the node to properly convert it back to prototype form
915 914 */
916 915 ddi_remove_minor_node(dip, NULL);
917 916
918 917 ddi_prop_remove_all(dip);
919 918 }
920 919
921 920 static boolean_t
922 921 pcieb_is_pcie_device_type(dev_info_t *dip)
923 922 {
924 923 pcie_bus_t *bus_p = PCIE_DIP2BUS(dip);
925 924
926 925 if (PCIE_IS_SW(bus_p) || PCIE_IS_RP(bus_p) || PCIE_IS_PCI2PCIE(bus_p))
927 926 return (B_TRUE);
928 927
929 928 return (B_FALSE);
930 929 }
931 930
932 931 static int
933 932 pcieb_intr_attach(pcieb_devstate_t *pcieb)
934 933 {
935 934 int intr_types;
936 935 dev_info_t *dip = pcieb->pcieb_dip;
937 936
938 937 /* Allow platform specific code to do any initialization first */
939 938 pcieb_plat_intr_attach(pcieb);
940 939
941 940 /*
942 941 * Initialize interrupt handlers.
943 942 * If both MSI and FIXED are supported, try to attach MSI first.
944 943 * If MSI fails for any reason, then try FIXED, but only allow one
945 944 * type to be attached.
946 945 */
947 946 if (ddi_intr_get_supported_types(dip, &intr_types) != DDI_SUCCESS) {
948 947 PCIEB_DEBUG(DBG_ATTACH, dip, "ddi_intr_get_supported_types"
949 948 " failed\n");
950 949 goto FAIL;
951 950 }
952 951
953 952 if ((intr_types & DDI_INTR_TYPE_MSI) &&
954 953 (pcieb_msi_supported(dip) == DDI_SUCCESS)) {
955 954 if (pcieb_intr_init(pcieb, DDI_INTR_TYPE_MSI) == DDI_SUCCESS)
956 955 intr_types = DDI_INTR_TYPE_MSI;
957 956 else {
958 957 PCIEB_DEBUG(DBG_ATTACH, dip, "Unable to attach MSI"
959 958 " handler\n");
960 959 }
961 960 }
962 961
963 962 if (intr_types != DDI_INTR_TYPE_MSI) {
964 963 /*
965 964 * MSIs are not supported or MSI initialization failed. For Root
966 965 * Ports mark this so error handling might try to fallback to
967 966 * some other mechanism if available (machinecheck etc.).
968 967 */
969 968 if (PCIE_IS_RP(PCIE_DIP2UPBUS(dip)))
970 969 pcieb->pcieb_no_aer_msi = B_TRUE;
971 970 }
972 971
973 972 if (intr_types & DDI_INTR_TYPE_FIXED) {
974 973 if (pcieb_intr_init(pcieb, DDI_INTR_TYPE_FIXED) !=
975 974 DDI_SUCCESS) {
976 975 PCIEB_DEBUG(DBG_ATTACH, dip,
977 976 "Unable to attach INTx handler\n");
978 977 goto FAIL;
979 978 }
980 979 }
981 980 return (DDI_SUCCESS);
982 981
983 982 FAIL:
984 983 return (DDI_FAILURE);
985 984 }
986 985
987 986 /*
988 987 * This function initializes internally generated interrupts only.
989 988 * It does not affect any interrupts generated by downstream devices
990 989 * or the forwarding of them.
991 990 *
992 991 * Enable Device Specific Interrupts or Hotplug features here.
993 992 * Enabling features may change how many interrupts are requested
994 993 * by the device. If features are not enabled first, the
995 994 * device might not ask for any interrupts.
996 995 */
997 996
998 997 static int
999 998 pcieb_intr_init(pcieb_devstate_t *pcieb, int intr_type)
1000 999 {
1001 1000 dev_info_t *dip = pcieb->pcieb_dip;
1002 1001 int nintrs, request, count, x;
1003 1002 int intr_cap = 0;
1004 1003 int inum = 0;
1005 1004 int ret, hp_msi_off;
1006 1005 pcie_bus_t *bus_p = PCIE_DIP2UPBUS(dip);
1007 1006 uint16_t vendorid = bus_p->bus_dev_ven_id & 0xFFFF;
1008 1007 boolean_t is_hp = B_FALSE;
1009 1008 boolean_t is_pme = B_FALSE;
1010 1009
1011 1010 PCIEB_DEBUG(DBG_ATTACH, dip, "pcieb_intr_init: Attaching %s handler\n",
1012 1011 (intr_type == DDI_INTR_TYPE_MSI) ? "MSI" : "INTx");
1013 1012
1014 1013 request = 0;
1015 1014 if (PCIE_IS_HOTPLUG_ENABLED(dip)) {
1016 1015 request++;
1017 1016 is_hp = B_TRUE;
1018 1017 }
1019 1018
1020 1019 /*
1021 1020 * Hotplug and PME share the same MSI vector. If hotplug is not
1022 1021 * supported check if MSI is needed for PME.
1023 1022 */
1024 1023 if ((intr_type == DDI_INTR_TYPE_MSI) && PCIE_IS_RP(bus_p) &&
1025 1024 (vendorid == NVIDIA_VENDOR_ID)) {
1026 1025 is_pme = B_TRUE;
1027 1026 if (!is_hp)
1028 1027 request++;
1029 1028 }
1030 1029
1031 1030 /*
1032 1031 * Setup MSI if this device is a Rootport and has AER. Currently no
1033 1032 * SPARC Root Port supports fabric errors being reported through it.
1034 1033 */
1035 1034 if (intr_type == DDI_INTR_TYPE_MSI) {
1036 1035 if (PCIE_IS_RP(bus_p) && PCIE_HAS_AER(bus_p))
1037 1036 request++;
1038 1037 }
1039 1038
1040 1039 if (request == 0)
1041 1040 return (DDI_SUCCESS);
1042 1041
1043 1042 /*
1044 1043 * Get number of supported interrupts.
1045 1044 *
1046 1045 * Several Bridges/Switches will not have this property set, resulting
1047 1046 * in a FAILURE, if the device is not configured in a way that
1048 1047 * interrupts are needed. (eg. hotplugging)
1049 1048 */
1050 1049 ret = ddi_intr_get_nintrs(dip, intr_type, &nintrs);
1051 1050 if ((ret != DDI_SUCCESS) || (nintrs == 0)) {
1052 1051 PCIEB_DEBUG(DBG_ATTACH, dip, "ddi_intr_get_nintrs ret:%d"
1053 1052 " req:%d\n", ret, nintrs);
1054 1053 return (DDI_FAILURE);
1055 1054 }
1056 1055
1057 1056 PCIEB_DEBUG(DBG_ATTACH, dip, "bdf 0x%x: ddi_intr_get_nintrs: nintrs %d",
1058 1057 " request %d\n", bus_p->bus_bdf, nintrs, request);
1059 1058
1060 1059 if (request > nintrs)
1061 1060 request = nintrs;
1062 1061
1063 1062 /* Allocate an array of interrupt handlers */
1064 1063 pcieb->pcieb_htable_size = sizeof (ddi_intr_handle_t) * request;
1065 1064 pcieb->pcieb_htable = kmem_zalloc(pcieb->pcieb_htable_size,
1066 1065 KM_SLEEP);
1067 1066 pcieb->pcieb_init_flags |= PCIEB_INIT_HTABLE;
1068 1067
1069 1068 ret = ddi_intr_alloc(dip, pcieb->pcieb_htable, intr_type, inum,
1070 1069 request, &count, DDI_INTR_ALLOC_NORMAL);
1071 1070 if ((ret != DDI_SUCCESS) || (count == 0)) {
1072 1071 PCIEB_DEBUG(DBG_ATTACH, dip, "ddi_intr_alloc() ret: %d ask: %d"
1073 1072 " actual: %d\n", ret, request, count);
1074 1073 goto FAIL;
1075 1074 }
1076 1075 pcieb->pcieb_init_flags |= PCIEB_INIT_ALLOC;
1077 1076
1078 1077 /* Save the actual number of interrupts allocated */
1079 1078 pcieb->pcieb_intr_count = count;
1080 1079 if (count < request) {
1081 1080 PCIEB_DEBUG(DBG_ATTACH, dip, "bdf 0%x: Requested Intr: %d"
1082 1081 " Received: %d\n", bus_p->bus_bdf, request, count);
1083 1082 }
1084 1083
1085 1084 /*
1086 1085 * NVidia (MCP55 and other) chipsets have a errata that if the number
1087 1086 * of requested MSI intrs is not allocated we have to fall back to INTx.
1088 1087 */
1089 1088 if (intr_type == DDI_INTR_TYPE_MSI) {
1090 1089 if (PCIE_IS_RP(bus_p) && (vendorid == NVIDIA_VENDOR_ID)) {
1091 1090 if (request != count)
1092 1091 goto FAIL;
1093 1092 }
1094 1093 }
1095 1094
1096 1095 /* Get interrupt priority */
1097 1096 ret = ddi_intr_get_pri(pcieb->pcieb_htable[0],
1098 1097 &pcieb->pcieb_intr_priority);
1099 1098 if (ret != DDI_SUCCESS) {
1100 1099 PCIEB_DEBUG(DBG_ATTACH, dip, "ddi_intr_get_pri() ret: %d\n",
1101 1100 ret);
1102 1101 goto FAIL;
1103 1102 }
1104 1103
1105 1104 if (pcieb->pcieb_intr_priority >= LOCK_LEVEL) {
1106 1105 pcieb->pcieb_intr_priority = LOCK_LEVEL - 1;
1107 1106 ret = ddi_intr_set_pri(pcieb->pcieb_htable[0],
1108 1107 pcieb->pcieb_intr_priority);
1109 1108 if (ret != DDI_SUCCESS) {
1110 1109 PCIEB_DEBUG(DBG_ATTACH, dip, "ddi_intr_set_pri() ret:"
1111 1110 " %d\n", ret);
1112 1111
1113 1112 goto FAIL;
1114 1113 }
1115 1114 }
1116 1115
1117 1116 mutex_init(&pcieb->pcieb_intr_mutex, NULL, MUTEX_DRIVER, NULL);
1118 1117
1119 1118 pcieb->pcieb_init_flags |= PCIEB_INIT_MUTEX;
1120 1119
1121 1120 for (count = 0; count < pcieb->pcieb_intr_count; count++) {
1122 1121 ret = ddi_intr_add_handler(pcieb->pcieb_htable[count],
1123 1122 pcieb_intr_handler, (caddr_t)pcieb,
1124 1123 (caddr_t)(uintptr_t)(inum + count));
1125 1124
1126 1125 if (ret != DDI_SUCCESS) {
1127 1126 PCIEB_DEBUG(DBG_ATTACH, dip, "Cannot add "
1128 1127 "interrupt(%d)\n", ret);
1129 1128 break;
1130 1129 }
1131 1130 }
1132 1131
1133 1132 /* If unsucessful, remove the added handlers */
1134 1133 if (ret != DDI_SUCCESS) {
1135 1134 for (x = 0; x < count; x++) {
1136 1135 (void) ddi_intr_remove_handler(pcieb->pcieb_htable[x]);
1137 1136 }
1138 1137 goto FAIL;
1139 1138 }
1140 1139
1141 1140 pcieb->pcieb_init_flags |= PCIEB_INIT_HANDLER;
1142 1141
1143 1142 (void) ddi_intr_get_cap(pcieb->pcieb_htable[0], &intr_cap);
1144 1143
1145 1144 /*
1146 1145 * Get this intr lock because we are not quite ready to handle
1147 1146 * interrupts immediately after enabling it. The MSI multi register
1148 1147 * gets programmed in ddi_intr_enable after which we need to get the
1149 1148 * MSI offsets for Hotplug/AER.
1150 1149 */
1151 1150 mutex_enter(&pcieb->pcieb_intr_mutex);
1152 1151
1153 1152 if (intr_cap & DDI_INTR_FLAG_BLOCK) {
1154 1153 (void) ddi_intr_block_enable(pcieb->pcieb_htable,
1155 1154 pcieb->pcieb_intr_count);
1156 1155 pcieb->pcieb_init_flags |= PCIEB_INIT_BLOCK;
1157 1156 } else {
1158 1157 for (count = 0; count < pcieb->pcieb_intr_count; count++) {
1159 1158 (void) ddi_intr_enable(pcieb->pcieb_htable[count]);
1160 1159 }
1161 1160 }
1162 1161 pcieb->pcieb_init_flags |= PCIEB_INIT_ENABLE;
1163 1162
1164 1163 /* Save the interrupt type */
1165 1164 pcieb->pcieb_intr_type = intr_type;
1166 1165
1167 1166 /* Get the MSI offset for hotplug/PME from the PCIe cap reg */
1168 1167 if (intr_type == DDI_INTR_TYPE_MSI) {
1169 1168 hp_msi_off = PCI_CAP_GET16(bus_p->bus_cfg_hdl, NULL,
1170 1169 bus_p->bus_pcie_off, PCIE_PCIECAP) &
1171 1170 PCIE_PCIECAP_INT_MSG_NUM;
1172 1171
1173 1172 if (hp_msi_off >= count) {
1174 1173 PCIEB_DEBUG(DBG_ATTACH, dip, "MSI number %d in PCIe "
1175 1174 "cap > max allocated %d\n", hp_msi_off, count);
1176 1175 mutex_exit(&pcieb->pcieb_intr_mutex);
1177 1176 goto FAIL;
1178 1177 }
1179 1178
1180 1179 if (is_hp)
1181 1180 pcieb->pcieb_isr_tab[hp_msi_off] |= PCIEB_INTR_SRC_HP;
1182 1181
1183 1182 if (is_pme)
1184 1183 pcieb->pcieb_isr_tab[hp_msi_off] |= PCIEB_INTR_SRC_PME;
1185 1184 } else {
1186 1185 /* INTx handles only Hotplug interrupts */
1187 1186 if (is_hp)
1188 1187 pcieb->pcieb_isr_tab[0] |= PCIEB_INTR_SRC_HP;
1189 1188 }
1190 1189
1191 1190
1192 1191 /*
1193 1192 * Get the MSI offset for errors from the AER Root Error status
1194 1193 * register.
1195 1194 */
1196 1195 if ((intr_type == DDI_INTR_TYPE_MSI) && PCIE_IS_RP(bus_p)) {
1197 1196 if (PCIE_HAS_AER(bus_p)) {
1198 1197 int aer_msi_off;
1199 1198 aer_msi_off = (PCI_XCAP_GET32(bus_p->bus_cfg_hdl, NULL,
1200 1199 bus_p->bus_aer_off, PCIE_AER_RE_STS) >>
1201 1200 PCIE_AER_RE_STS_MSG_NUM_SHIFT) &
1202 1201 PCIE_AER_RE_STS_MSG_NUM_MASK;
1203 1202
1204 1203 if (aer_msi_off >= count) {
1205 1204 PCIEB_DEBUG(DBG_ATTACH, dip, "MSI number %d in"
1206 1205 " AER cap > max allocated %d\n",
1207 1206 aer_msi_off, count);
1208 1207 mutex_exit(&pcieb->pcieb_intr_mutex);
1209 1208 goto FAIL;
1210 1209 }
1211 1210 pcieb->pcieb_isr_tab[aer_msi_off] |= PCIEB_INTR_SRC_AER;
1212 1211 } else {
1213 1212 /*
1214 1213 * This RP does not have AER. Fallback to the
1215 1214 * SERR+Machinecheck approach if available.
1216 1215 */
1217 1216 pcieb->pcieb_no_aer_msi = B_TRUE;
1218 1217 }
1219 1218 }
1220 1219
1221 1220 mutex_exit(&pcieb->pcieb_intr_mutex);
1222 1221 return (DDI_SUCCESS);
1223 1222
1224 1223 FAIL:
1225 1224 pcieb_intr_fini(pcieb);
1226 1225 return (DDI_FAILURE);
1227 1226 }
1228 1227
1229 1228 static void
1230 1229 pcieb_intr_fini(pcieb_devstate_t *pcieb)
1231 1230 {
1232 1231 int x;
1233 1232 int count = pcieb->pcieb_intr_count;
1234 1233 int flags = pcieb->pcieb_init_flags;
1235 1234
1236 1235 if ((flags & PCIEB_INIT_ENABLE) &&
1237 1236 (flags & PCIEB_INIT_BLOCK)) {
1238 1237 (void) ddi_intr_block_disable(pcieb->pcieb_htable, count);
1239 1238 flags &= ~(PCIEB_INIT_ENABLE |
1240 1239 PCIEB_INIT_BLOCK);
1241 1240 }
1242 1241
1243 1242 if (flags & PCIEB_INIT_MUTEX)
1244 1243 mutex_destroy(&pcieb->pcieb_intr_mutex);
1245 1244
1246 1245 for (x = 0; x < count; x++) {
1247 1246 if (flags & PCIEB_INIT_ENABLE)
1248 1247 (void) ddi_intr_disable(pcieb->pcieb_htable[x]);
1249 1248
1250 1249 if (flags & PCIEB_INIT_HANDLER)
1251 1250 (void) ddi_intr_remove_handler(pcieb->pcieb_htable[x]);
1252 1251
1253 1252 if (flags & PCIEB_INIT_ALLOC)
1254 1253 (void) ddi_intr_free(pcieb->pcieb_htable[x]);
1255 1254 }
1256 1255
1257 1256 flags &= ~(PCIEB_INIT_ENABLE | PCIEB_INIT_HANDLER | PCIEB_INIT_ALLOC |
1258 1257 PCIEB_INIT_MUTEX);
1259 1258
1260 1259 if (flags & PCIEB_INIT_HTABLE)
1261 1260 kmem_free(pcieb->pcieb_htable, pcieb->pcieb_htable_size);
1262 1261
1263 1262 flags &= ~PCIEB_INIT_HTABLE;
1264 1263
1265 1264 pcieb->pcieb_init_flags &= flags;
1266 1265 }
1267 1266
1268 1267 /*
1269 1268 * Checks if this device needs MSIs enabled or not.
1270 1269 */
1271 1270 /*ARGSUSED*/
1272 1271 static int
1273 1272 pcieb_msi_supported(dev_info_t *dip)
1274 1273 {
1275 1274 return ((pcieb_enable_msi && pcieb_plat_msi_supported(dip)) ?
1276 1275 DDI_SUCCESS: DDI_FAILURE);
1277 1276 }
1278 1277
1279 1278 /*ARGSUSED*/
1280 1279 static int
1281 1280 pcieb_fm_init_child(dev_info_t *dip, dev_info_t *tdip, int cap,
1282 1281 ddi_iblock_cookie_t *ibc)
1283 1282 {
1284 1283 pcieb_devstate_t *pcieb = ddi_get_soft_state(pcieb_state,
1285 1284 ddi_get_instance(dip));
1286 1285
1287 1286 ASSERT(ibc != NULL);
1288 1287 *ibc = pcieb->pcieb_fm_ibc;
1289 1288
1290 1289 return (DEVI(dip)->devi_fmhdl->fh_cap | DDI_FM_ACCCHK_CAPABLE |
1291 1290 DDI_FM_DMACHK_CAPABLE);
1292 1291 }
1293 1292
1294 1293 static int
1295 1294 pcieb_fm_init(pcieb_devstate_t *pcieb_p)
1296 1295 {
1297 1296 dev_info_t *dip = pcieb_p->pcieb_dip;
1298 1297 int fm_cap = DDI_FM_EREPORT_CAPABLE;
1299 1298
1300 1299 /*
1301 1300 * Request our capability level and get our parents capability
1302 1301 * and ibc.
1303 1302 */
1304 1303 ddi_fm_init(dip, &fm_cap, &pcieb_p->pcieb_fm_ibc);
1305 1304
1306 1305 return (DDI_SUCCESS);
1307 1306 }
1308 1307
1309 1308 /*
1310 1309 * Breakdown our FMA resources
1311 1310 */
1312 1311 static void
1313 1312 pcieb_fm_fini(pcieb_devstate_t *pcieb_p)
1314 1313 {
1315 1314 /*
1316 1315 * Clean up allocated fm structures
1317 1316 */
1318 1317 ddi_fm_fini(pcieb_p->pcieb_dip);
1319 1318 }
1320 1319
1321 1320 static int
1322 1321 pcieb_open(dev_t *devp, int flags, int otyp, cred_t *credp)
1323 1322 {
1324 1323 int inst = PCI_MINOR_NUM_TO_INSTANCE(getminor(*devp));
1325 1324 pcieb_devstate_t *pcieb = ddi_get_soft_state(pcieb_state, inst);
1326 1325 int rv;
1327 1326
1328 1327 if (pcieb == NULL)
1329 1328 return (ENXIO);
1330 1329
1331 1330 mutex_enter(&pcieb->pcieb_mutex);
1332 1331 rv = pcie_open(pcieb->pcieb_dip, devp, flags, otyp, credp);
1333 1332 mutex_exit(&pcieb->pcieb_mutex);
1334 1333
1335 1334 return (rv);
1336 1335 }
1337 1336
1338 1337 static int
1339 1338 pcieb_close(dev_t dev, int flags, int otyp, cred_t *credp)
1340 1339 {
1341 1340 int inst = PCI_MINOR_NUM_TO_INSTANCE(getminor(dev));
1342 1341 pcieb_devstate_t *pcieb = ddi_get_soft_state(pcieb_state, inst);
1343 1342 int rv;
1344 1343
1345 1344 if (pcieb == NULL)
1346 1345 return (ENXIO);
1347 1346
1348 1347 mutex_enter(&pcieb->pcieb_mutex);
1349 1348 rv = pcie_close(pcieb->pcieb_dip, dev, flags, otyp, credp);
1350 1349 mutex_exit(&pcieb->pcieb_mutex);
1351 1350
1352 1351 return (rv);
1353 1352 }
1354 1353
1355 1354 static int
1356 1355 pcieb_ioctl(dev_t dev, int cmd, intptr_t arg, int mode, cred_t *credp,
1357 1356 int *rvalp)
1358 1357 {
1359 1358 int inst = PCI_MINOR_NUM_TO_INSTANCE(getminor(dev));
1360 1359 pcieb_devstate_t *pcieb = ddi_get_soft_state(pcieb_state, inst);
1361 1360 int rv;
1362 1361
1363 1362 if (pcieb == NULL)
1364 1363 return (ENXIO);
1365 1364
1366 1365 /* To handle devctl and hotplug related ioctls */
1367 1366 rv = pcie_ioctl(pcieb->pcieb_dip, dev, cmd, arg, mode, credp, rvalp);
1368 1367
1369 1368 return (rv);
1370 1369 }
1371 1370
1372 1371 /*
1373 1372 * Common interrupt handler for hotplug, PME and errors.
1374 1373 */
1375 1374 static uint_t
1376 1375 pcieb_intr_handler(caddr_t arg1, caddr_t arg2)
1377 1376 {
1378 1377 pcieb_devstate_t *pcieb_p = (pcieb_devstate_t *)arg1;
1379 1378 dev_info_t *dip = pcieb_p->pcieb_dip;
1380 1379 ddi_fm_error_t derr;
1381 1380 int sts = 0;
1382 1381 int ret = DDI_INTR_UNCLAIMED;
1383 1382 int isrc;
1384 1383
1385 1384 if (!(pcieb_p->pcieb_init_flags & PCIEB_INIT_ENABLE))
1386 1385 goto FAIL;
1387 1386
1388 1387 mutex_enter(&pcieb_p->pcieb_intr_mutex);
1389 1388 isrc = pcieb_p->pcieb_isr_tab[(int)(uintptr_t)arg2];
1390 1389 mutex_exit(&pcieb_p->pcieb_intr_mutex);
1391 1390
1392 1391 PCIEB_DEBUG(DBG_INTR, dip, "Received intr number %d\n",
1393 1392 (int)(uintptr_t)arg2);
1394 1393
1395 1394 if (isrc == PCIEB_INTR_SRC_UNKNOWN)
1396 1395 goto FAIL;
1397 1396
1398 1397 if (isrc & PCIEB_INTR_SRC_HP)
1399 1398 ret = pcie_intr(dip);
1400 1399
1401 1400 if (isrc & PCIEB_INTR_SRC_PME)
1402 1401 ret = DDI_INTR_CLAIMED;
1403 1402
1404 1403 /* AER Error */
1405 1404 if (isrc & PCIEB_INTR_SRC_AER) {
1406 1405 /*
1407 1406 * If MSI is shared with PME/hotplug then check Root Error
1408 1407 * Status Reg before claiming it. For now it's ok since
1409 1408 * we know we get 2 MSIs.
1410 1409 */
1411 1410 ret = DDI_INTR_CLAIMED;
1412 1411 bzero(&derr, sizeof (ddi_fm_error_t));
1413 1412 derr.fme_version = DDI_FME_VERSION;
1414 1413 mutex_enter(&pcieb_p->pcieb_peek_poke_mutex);
1415 1414 mutex_enter(&pcieb_p->pcieb_err_mutex);
1416 1415
1417 1416 pf_eh_enter(PCIE_DIP2BUS(dip));
1418 1417 PCIE_ROOT_EH_SRC(PCIE_DIP2PFD(dip))->intr_type =
1419 1418 PF_INTR_TYPE_AER;
1420 1419
1421 1420 if ((DEVI(dip)->devi_fmhdl->fh_cap) & DDI_FM_EREPORT_CAPABLE)
1422 1421 sts = pf_scan_fabric(dip, &derr, NULL);
1423 1422 pf_eh_exit(PCIE_DIP2BUS(dip));
1424 1423
1425 1424 mutex_exit(&pcieb_p->pcieb_err_mutex);
1426 1425 mutex_exit(&pcieb_p->pcieb_peek_poke_mutex);
1427 1426 if (pcieb_die & sts)
1428 1427 fm_panic("%s-%d: PCI(-X) Express Fatal Error. (0x%x)",
1429 1428 ddi_driver_name(dip), ddi_get_instance(dip), sts);
1430 1429 }
1431 1430 FAIL:
1432 1431 return (ret);
1433 1432 }
1434 1433
1435 1434 /*
1436 1435 * Some PCI-X to PCI-E bridges do not support full 64-bit addressing on the
1437 1436 * PCI-X side of the bridge. We build a special version of this driver for
1438 1437 * those bridges, which uses PCIEB_ADDR_LIMIT_LO and/or PCIEB_ADDR_LIMIT_HI
1439 1438 * to define the range of values which the chip can handle. The code below
1440 1439 * then clamps the DMA address range supplied by the driver, preventing the
1441 1440 * PCI-E nexus driver from allocating any memory the bridge can't deal
1442 1441 * with.
1443 1442 */
1444 1443 static int
1445 1444 pcieb_dma_allochdl(dev_info_t *dip, dev_info_t *rdip,
1446 1445 ddi_dma_attr_t *attr_p, int (*waitfp)(caddr_t), caddr_t arg,
1447 1446 ddi_dma_handle_t *handlep)
1448 1447 {
1449 1448 int ret;
1450 1449 #ifdef PCIEB_BCM
1451 1450 uint64_t lim;
1452 1451
1453 1452 /*
1454 1453 * If the leaf device's limits are outside than what the Broadcom
1455 1454 * bridge can handle, we need to clip the values passed up the chain.
1456 1455 */
1457 1456 lim = attr_p->dma_attr_addr_lo;
1458 1457 attr_p->dma_attr_addr_lo = MAX(lim, PCIEB_ADDR_LIMIT_LO);
1459 1458
1460 1459 lim = attr_p->dma_attr_addr_hi;
1461 1460 attr_p->dma_attr_addr_hi = MIN(lim, PCIEB_ADDR_LIMIT_HI);
1462 1461
1463 1462 #endif /* PCIEB_BCM */
1464 1463
1465 1464 /*
1466 1465 * This is a software workaround to fix the Broadcom 5714/5715 PCIe-PCI
1467 1466 * bridge prefetch bug. Intercept the DMA alloc handle request and set
1468 1467 * PX_DMAI_FLAGS_MAP_BUFZONE flag in the handle. If this flag is set,
1469 1468 * the px nexus driver will allocate an extra page & make it valid one,
1470 1469 * for any DVMA request that comes from any of the Broadcom bridge child
1471 1470 * devices.
1472 1471 */
1473 1472 if ((ret = ddi_dma_allochdl(dip, rdip, attr_p, waitfp, arg,
1474 1473 handlep)) == DDI_SUCCESS) {
1475 1474 ddi_dma_impl_t *mp = (ddi_dma_impl_t *)*handlep;
1476 1475 #ifdef PCIEB_BCM
1477 1476 mp->dmai_inuse |= PX_DMAI_FLAGS_MAP_BUFZONE;
1478 1477 #endif /* PCIEB_BCM */
1479 1478 /*
1480 1479 * For a given rdip, update mp->dmai_bdf with the bdf value
1481 1480 * of pcieb's immediate child or secondary bus-id of the
1482 1481 * PCIe2PCI bridge.
1483 1482 */
1484 1483 mp->dmai_minxfer = pcie_get_bdf_for_dma_xfer(dip, rdip);
1485 1484 }
1486 1485
1487 1486 return (ret);
1488 1487 }
1489 1488
1490 1489 /*
1491 1490 * FDVMA feature is not supported for any child device of Broadcom 5714/5715
1492 1491 * PCIe-PCI bridge due to prefetch bug. Return failure immediately, so that
1493 1492 * these drivers will switch to regular DVMA path.
1494 1493 */
1495 1494 /*ARGSUSED*/
1496 1495 static int
1497 1496 pcieb_dma_mctl(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle,
1498 1497 enum ddi_dma_ctlops cmd, off_t *offp, size_t *lenp, caddr_t *objp,
1499 1498 uint_t cache_flags)
1500 1499 {
1501 1500 int ret;
1502 1501
1503 1502 #ifdef PCIEB_BCM
1504 1503 if (cmd == DDI_DMA_RESERVE)
1505 1504 return (DDI_FAILURE);
1506 1505 #endif /* PCIEB_BCM */
1507 1506
1508 1507 if (((ret = ddi_dma_mctl(dip, rdip, handle, cmd, offp, lenp, objp,
1509 1508 cache_flags)) == DDI_SUCCESS) && (cmd == DDI_DMA_RESERVE)) {
1510 1509 ddi_dma_impl_t *mp = (ddi_dma_impl_t *)*objp;
1511 1510
1512 1511 /*
1513 1512 * For a given rdip, update mp->dmai_bdf with the bdf value
1514 1513 * of pcieb's immediate child or secondary bus-id of the
1515 1514 * PCIe2PCI bridge.
1516 1515 */
1517 1516 mp->dmai_minxfer = pcie_get_bdf_for_dma_xfer(dip, rdip);
1518 1517 }
1519 1518
1520 1519 return (ret);
1521 1520 }
1522 1521
1523 1522 static int
1524 1523 pcieb_intr_ops(dev_info_t *dip, dev_info_t *rdip, ddi_intr_op_t intr_op,
1525 1524 ddi_intr_handle_impl_t *hdlp, void *result)
1526 1525 {
1527 1526 return (pcieb_plat_intr_ops(dip, rdip, intr_op, hdlp, result));
1528 1527
1529 1528 }
1530 1529
1531 1530 /*
1532 1531 * Power management related initialization specific to pcieb.
1533 1532 * Called by pcieb_attach()
1534 1533 */
1535 1534 static int
1536 1535 pcieb_pwr_setup(dev_info_t *dip)
1537 1536 {
1538 1537 char *comp_array[5];
1539 1538 int i;
1540 1539 ddi_acc_handle_t conf_hdl;
1541 1540 uint16_t pmcap, cap_ptr;
1542 1541 pcie_pwr_t *pwr_p;
1543 1542
1544 1543 /* Some platforms/devices may choose to disable PM */
1545 1544 if (pcieb_plat_pwr_disable(dip)) {
1546 1545 (void) pcieb_pwr_disable(dip);
1547 1546 return (DDI_SUCCESS);
1548 1547 }
1549 1548
1550 1549 ASSERT(PCIE_PMINFO(dip));
1551 1550 pwr_p = PCIE_NEXUS_PMINFO(dip);
1552 1551 ASSERT(pwr_p);
1553 1552
1554 1553 /* Code taken from pci_pci driver */
1555 1554 if (pci_config_setup(dip, &pwr_p->pwr_conf_hdl) != DDI_SUCCESS) {
1556 1555 PCIEB_DEBUG(DBG_PWR, dip, "pcieb_pwr_setup: pci_config_setup "
1557 1556 "failed\n");
1558 1557 return (DDI_FAILURE);
1559 1558 }
1560 1559 conf_hdl = pwr_p->pwr_conf_hdl;
1561 1560
1562 1561 /*
1563 1562 * Walk the capabilities searching for a PM entry.
1564 1563 */
1565 1564 if ((PCI_CAP_LOCATE(conf_hdl, PCI_CAP_ID_PM, &cap_ptr)) ==
1566 1565 DDI_FAILURE) {
1567 1566 PCIEB_DEBUG(DBG_PWR, dip, "switch/bridge does not support PM. "
1568 1567 " PCI PM data structure not found in config header\n");
1569 1568 pci_config_teardown(&conf_hdl);
1570 1569 return (DDI_SUCCESS);
1571 1570 }
1572 1571 /*
1573 1572 * Save offset to pmcsr for future references.
1574 1573 */
1575 1574 pwr_p->pwr_pmcsr_offset = cap_ptr + PCI_PMCSR;
1576 1575 pmcap = PCI_CAP_GET16(conf_hdl, NULL, cap_ptr, PCI_PMCAP);
1577 1576 if (pmcap & PCI_PMCAP_D1) {
1578 1577 PCIEB_DEBUG(DBG_PWR, dip, "D1 state supported\n");
1579 1578 pwr_p->pwr_pmcaps |= PCIE_SUPPORTS_D1;
1580 1579 }
1581 1580 if (pmcap & PCI_PMCAP_D2) {
1582 1581 PCIEB_DEBUG(DBG_PWR, dip, "D2 state supported\n");
1583 1582 pwr_p->pwr_pmcaps |= PCIE_SUPPORTS_D2;
1584 1583 }
1585 1584
1586 1585 i = 0;
1587 1586 comp_array[i++] = "NAME=PCIe switch/bridge PM";
1588 1587 comp_array[i++] = "0=Power Off (D3)";
1589 1588 if (pwr_p->pwr_pmcaps & PCIE_SUPPORTS_D2)
1590 1589 comp_array[i++] = "1=D2";
1591 1590 if (pwr_p->pwr_pmcaps & PCIE_SUPPORTS_D1)
1592 1591 comp_array[i++] = "2=D1";
1593 1592 comp_array[i++] = "3=Full Power D0";
1594 1593
1595 1594 /*
1596 1595 * Create pm-components property, if it does not exist already.
1597 1596 */
1598 1597 if (ddi_prop_update_string_array(DDI_DEV_T_NONE, dip,
1599 1598 "pm-components", comp_array, i) != DDI_PROP_SUCCESS) {
1600 1599 PCIEB_DEBUG(DBG_PWR, dip, "could not create pm-components "
1601 1600 " prop\n");
1602 1601 pci_config_teardown(&conf_hdl);
1603 1602 return (DDI_FAILURE);
1604 1603 }
1605 1604 return (pcieb_pwr_init_and_raise(dip, pwr_p));
1606 1605 }
1607 1606
1608 1607 /*
1609 1608 * undo whatever is done in pcieb_pwr_setup. called by pcieb_detach()
1610 1609 */
1611 1610 static void
1612 1611 pcieb_pwr_teardown(dev_info_t *dip)
1613 1612 {
1614 1613 pcie_pwr_t *pwr_p;
1615 1614
1616 1615 if (!PCIE_PMINFO(dip) || !(pwr_p = PCIE_NEXUS_PMINFO(dip)))
1617 1616 return;
1618 1617
1619 1618 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "pm-components");
1620 1619 if (pwr_p->pwr_conf_hdl)
1621 1620 pci_config_teardown(&pwr_p->pwr_conf_hdl);
1622 1621 }
1623 1622
1624 1623 /*
1625 1624 * Initializes the power level and raise the power to D0, if it is
1626 1625 * not at D0.
1627 1626 */
1628 1627 static int
1629 1628 pcieb_pwr_init_and_raise(dev_info_t *dip, pcie_pwr_t *pwr_p)
1630 1629 {
1631 1630 uint16_t pmcsr;
1632 1631 int ret = DDI_SUCCESS;
1633 1632
1634 1633 /*
1635 1634 * Intialize our power level from PMCSR. The common code initializes
1636 1635 * this to UNKNOWN. There is no guarantee that we will be at full
1637 1636 * power at attach. If we are not at D0, raise the power.
1638 1637 */
1639 1638 pmcsr = pci_config_get16(pwr_p->pwr_conf_hdl, pwr_p->pwr_pmcsr_offset);
1640 1639 pmcsr &= PCI_PMCSR_STATE_MASK;
1641 1640 switch (pmcsr) {
1642 1641 case PCI_PMCSR_D0:
1643 1642 pwr_p->pwr_func_lvl = PM_LEVEL_D0;
1644 1643 break;
1645 1644
1646 1645 case PCI_PMCSR_D1:
1647 1646 pwr_p->pwr_func_lvl = PM_LEVEL_D1;
1648 1647 break;
1649 1648
1650 1649 case PCI_PMCSR_D2:
1651 1650 pwr_p->pwr_func_lvl = PM_LEVEL_D2;
1652 1651 break;
1653 1652
1654 1653 case PCI_PMCSR_D3HOT:
1655 1654 pwr_p->pwr_func_lvl = PM_LEVEL_D3;
1656 1655 break;
1657 1656
1658 1657 default:
1659 1658 break;
1660 1659 }
1661 1660
1662 1661 /* Raise the power to D0. */
1663 1662 if (pwr_p->pwr_func_lvl != PM_LEVEL_D0 &&
1664 1663 ((ret = pm_raise_power(dip, 0, PM_LEVEL_D0)) != DDI_SUCCESS)) {
1665 1664 /*
1666 1665 * Read PMCSR again. If it is at D0, ignore the return
1667 1666 * value from pm_raise_power.
1668 1667 */
1669 1668 pmcsr = pci_config_get16(pwr_p->pwr_conf_hdl,
1670 1669 pwr_p->pwr_pmcsr_offset);
1671 1670 if ((pmcsr & PCI_PMCSR_STATE_MASK) == PCI_PMCSR_D0)
1672 1671 ret = DDI_SUCCESS;
1673 1672 else {
1674 1673 PCIEB_DEBUG(DBG_PWR, dip, "pcieb_pwr_setup: could not "
1675 1674 "raise power to D0 \n");
1676 1675 }
1677 1676 }
1678 1677 if (ret == DDI_SUCCESS)
1679 1678 pwr_p->pwr_func_lvl = PM_LEVEL_D0;
1680 1679 return (ret);
1681 1680 }
1682 1681
1683 1682 /*
1684 1683 * Disable PM for x86 and PLX 8532 switch.
1685 1684 * For PLX Transitioning one port on this switch to low power causes links
1686 1685 * on other ports on the same station to die. Due to PLX erratum #34, we
1687 1686 * can't allow the downstream device go to non-D0 state.
1688 1687 */
1689 1688 static int
1690 1689 pcieb_pwr_disable(dev_info_t *dip)
1691 1690 {
1692 1691 pcie_pwr_t *pwr_p;
1693 1692
1694 1693 ASSERT(PCIE_PMINFO(dip));
1695 1694 pwr_p = PCIE_NEXUS_PMINFO(dip);
1696 1695 ASSERT(pwr_p);
1697 1696 PCIEB_DEBUG(DBG_PWR, dip, "pcieb_pwr_disable: disabling PM\n");
1698 1697 pwr_p->pwr_func_lvl = PM_LEVEL_D0;
1699 1698 pwr_p->pwr_flags = PCIE_NO_CHILD_PM;
1700 1699 return (DDI_SUCCESS);
1701 1700 }
1702 1701
1703 1702 #ifdef DEBUG
1704 1703 int pcieb_dbg_intr_print = 0;
1705 1704 void
1706 1705 pcieb_dbg(uint_t bit, dev_info_t *dip, char *fmt, ...)
1707 1706 {
1708 1707 va_list ap;
1709 1708
1710 1709 if (!pcieb_dbg_print)
1711 1710 return;
1712 1711
1713 1712 if (dip)
1714 1713 prom_printf("%s(%d): %s", ddi_driver_name(dip),
1715 1714 ddi_get_instance(dip), pcieb_debug_sym[bit]);
1716 1715
1717 1716 va_start(ap, fmt);
1718 1717 if (servicing_interrupt()) {
1719 1718 if (pcieb_dbg_intr_print)
1720 1719 prom_vprintf(fmt, ap);
1721 1720 } else {
1722 1721 prom_vprintf(fmt, ap);
1723 1722 }
1724 1723
1725 1724 va_end(ap);
1726 1725 }
1727 1726 #endif
1728 1727
1729 1728 static void
1730 1729 pcieb_id_props(pcieb_devstate_t *pcieb)
1731 1730 {
1732 1731 uint64_t serialid = 0; /* 40b field of EUI-64 serial no. register */
1733 1732 uint16_t cap_ptr;
1734 1733 uint8_t fic = 0; /* 1 = first in chassis device */
1735 1734 pcie_bus_t *bus_p = PCIE_DIP2BUS(pcieb->pcieb_dip);
1736 1735 ddi_acc_handle_t config_handle = bus_p->bus_cfg_hdl;
1737 1736
1738 1737 /*
1739 1738 * Identify first in chassis. In the special case of a Sun branded
1740 1739 * PLX device, it obviously is first in chassis. Otherwise, in the
1741 1740 * general case, look for an Expansion Slot Register and check its
1742 1741 * first-in-chassis bit.
1743 1742 */
1744 1743 #ifdef PX_PLX
1745 1744 uint16_t vendor_id = bus_p->bus_dev_ven_id & 0xFFFF;
1746 1745 uint16_t device_id = bus_p->bus_dev_ven_id >> 16;
1747 1746 if ((vendor_id == PXB_VENDOR_SUN) &&
1748 1747 ((device_id == PXB_DEVICE_PLX_PCIX) ||
1749 1748 (device_id == PXB_DEVICE_PLX_PCIE))) {
1750 1749 fic = 1;
1751 1750 }
1752 1751 #endif /* PX_PLX */
1753 1752 if ((fic == 0) && ((PCI_CAP_LOCATE(config_handle,
1754 1753 PCI_CAP_ID_SLOT_ID, &cap_ptr)) != DDI_FAILURE)) {
1755 1754 uint8_t esr = PCI_CAP_GET8(config_handle, NULL,
1756 1755 cap_ptr, PCI_CAP_ID_REGS_OFF);
1757 1756 if (PCI_CAPSLOT_FIC(esr))
1758 1757 fic = 1;
1759 1758 }
1760 1759
1761 1760 if ((PCI_CAP_LOCATE(config_handle,
1762 1761 PCI_CAP_XCFG_SPC(PCIE_EXT_CAP_ID_SER), &cap_ptr)) != DDI_FAILURE) {
1763 1762 /* Serialid can be 0 thru a full 40b number */
1764 1763 serialid = PCI_XCAP_GET32(config_handle, NULL,
1765 1764 cap_ptr, PCIE_SER_SID_UPPER_DW);
1766 1765 serialid <<= 32;
1767 1766 serialid |= PCI_XCAP_GET32(config_handle, NULL,
1768 1767 cap_ptr, PCIE_SER_SID_LOWER_DW);
1769 1768 }
1770 1769
1771 1770 if (fic)
1772 1771 (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, pcieb->pcieb_dip,
1773 1772 "first-in-chassis");
1774 1773 if (serialid)
1775 1774 (void) ddi_prop_update_int64(DDI_DEV_T_NONE, pcieb->pcieb_dip,
1776 1775 "serialid#", serialid);
1777 1776 }
1778 1777
1779 1778 static void
1780 1779 pcieb_create_ranges_prop(dev_info_t *dip,
1781 1780 ddi_acc_handle_t config_handle)
1782 1781 {
1783 1782 uint32_t base, limit;
1784 1783 ppb_ranges_t ranges[PCIEB_RANGE_LEN];
1785 1784 uint8_t io_base_lo, io_limit_lo;
1786 1785 uint16_t io_base_hi, io_limit_hi, mem_base, mem_limit;
1787 1786 int i = 0, rangelen = sizeof (ppb_ranges_t)/sizeof (int);
1788 1787
1789 1788 io_base_lo = pci_config_get8(config_handle, PCI_BCNF_IO_BASE_LOW);
1790 1789 io_limit_lo = pci_config_get8(config_handle, PCI_BCNF_IO_LIMIT_LOW);
1791 1790 io_base_hi = pci_config_get16(config_handle, PCI_BCNF_IO_BASE_HI);
1792 1791 io_limit_hi = pci_config_get16(config_handle, PCI_BCNF_IO_LIMIT_HI);
1793 1792 mem_base = pci_config_get16(config_handle, PCI_BCNF_MEM_BASE);
1794 1793 mem_limit = pci_config_get16(config_handle, PCI_BCNF_MEM_LIMIT);
1795 1794
1796 1795 /*
1797 1796 * Create ranges for IO space
1798 1797 */
1799 1798 ranges[i].size_low = ranges[i].size_high = 0;
1800 1799 ranges[i].parent_mid = ranges[i].child_mid = ranges[i].parent_high = 0;
1801 1800 ranges[i].child_high = ranges[i].parent_high |=
1802 1801 (PCI_REG_REL_M | PCI_ADDR_IO);
1803 1802 base = PCIEB_16bit_IOADDR(io_base_lo);
1804 1803 limit = PCIEB_16bit_IOADDR(io_limit_lo);
1805 1804
1806 1805 if ((io_base_lo & 0xf) == PCIEB_32BIT_IO) {
1807 1806 base = PCIEB_LADDR(base, io_base_hi);
1808 1807 }
1809 1808 if ((io_limit_lo & 0xf) == PCIEB_32BIT_IO) {
1810 1809 limit = PCIEB_LADDR(limit, io_limit_hi);
1811 1810 }
1812 1811
1813 1812 if ((io_base_lo & PCIEB_32BIT_IO) && (io_limit_hi > 0)) {
1814 1813 base = PCIEB_LADDR(base, io_base_hi);
1815 1814 limit = PCIEB_LADDR(limit, io_limit_hi);
1816 1815 }
1817 1816
1818 1817 /*
1819 1818 * Create ranges for 32bit memory space
1820 1819 */
1821 1820 base = PCIEB_32bit_MEMADDR(mem_base);
1822 1821 limit = PCIEB_32bit_MEMADDR(mem_limit);
1823 1822 ranges[i].size_low = ranges[i].size_high = 0;
1824 1823 ranges[i].parent_mid = ranges[i].child_mid = ranges[i].parent_high = 0;
1825 1824 ranges[i].child_high = ranges[i].parent_high |=
1826 1825 (PCI_REG_REL_M | PCI_ADDR_MEM32);
1827 1826 ranges[i].child_low = ranges[i].parent_low = base;
1828 1827 if (limit >= base) {
1829 1828 ranges[i].size_low = limit - base + PCIEB_MEMGRAIN;
1830 1829 i++;
1831 1830 }
1832 1831
1833 1832 if (i) {
1834 1833 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "ranges",
1835 1834 (int *)ranges, i * rangelen);
1836 1835 }
1837 1836 }
1838 1837
1839 1838 /*
1840 1839 * For PCI and PCI-X devices including PCIe2PCI bridge, initialize
1841 1840 * cache-line-size and latency timer configuration registers.
1842 1841 */
1843 1842 void
1844 1843 pcieb_set_pci_perf_parameters(dev_info_t *dip, ddi_acc_handle_t cfg_hdl)
1845 1844 {
1846 1845 uint_t n;
1847 1846
1848 1847 /* Initialize cache-line-size configuration register if needed */
1849 1848 if (ddi_getprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS,
1850 1849 "cache-line-size", 0) == 0) {
1851 1850 pci_config_put8(cfg_hdl, PCI_CONF_CACHE_LINESZ,
1852 1851 PCIEB_CACHE_LINE_SIZE);
1853 1852 n = pci_config_get8(cfg_hdl, PCI_CONF_CACHE_LINESZ);
1854 1853 if (n != 0) {
1855 1854 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
1856 1855 "cache-line-size", n);
1857 1856 }
1858 1857 }
1859 1858
1860 1859 /* Initialize latency timer configuration registers if needed */
1861 1860 if (ddi_getprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS,
1862 1861 "latency-timer", 0) == 0) {
1863 1862 uchar_t min_gnt, latency_timer;
1864 1863 uchar_t header_type;
1865 1864
1866 1865 /* Determine the configuration header type */
1867 1866 header_type = pci_config_get8(cfg_hdl, PCI_CONF_HEADER);
1868 1867
1869 1868 if ((header_type & PCI_HEADER_TYPE_M) == PCI_HEADER_ONE) {
1870 1869 latency_timer = PCIEB_LATENCY_TIMER;
1871 1870 pci_config_put8(cfg_hdl, PCI_BCNF_LATENCY_TIMER,
1872 1871 latency_timer);
1873 1872 } else {
1874 1873 min_gnt = pci_config_get8(cfg_hdl, PCI_CONF_MIN_G);
1875 1874 latency_timer = min_gnt * 8;
1876 1875 }
1877 1876
1878 1877 pci_config_put8(cfg_hdl, PCI_CONF_LATENCY_TIMER,
1879 1878 latency_timer);
1880 1879 n = pci_config_get8(cfg_hdl, PCI_CONF_LATENCY_TIMER);
1881 1880 if (n != 0) {
1882 1881 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
1883 1882 "latency-timer", n);
1884 1883 }
1885 1884 }
1886 1885 }
|
↓ open down ↓ |
1675 lines elided |
↑ open up ↑ |
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX