Print this page
7127 remove -Wno-missing-braces from Makefile.uts
| Split |
Close |
| Expand all |
| Collapse all |
--- old/usr/src/uts/common/io/iwk/iwk2.c
+++ new/usr/src/uts/common/io/iwk/iwk2.c
1 1 /*
2 2 * Copyright 2010 Sun Microsystems, Inc. All rights reserved.
3 3 * Use is subject to license terms.
4 4 */
5 5
6 6 /*
7 7 * Copyright (c) 2007, Intel Corporation
8 8 * All rights reserved.
9 9 */
10 10
11 11 /*
12 12 * Copyright (c) 2006
13 13 * Copyright (c) 2007
14 14 * Damien Bergamini <damien.bergamini@free.fr>
15 15 *
16 16 * Permission to use, copy, modify, and distribute this software for any
17 17 * purpose with or without fee is hereby granted, provided that the above
18 18 * copyright notice and this permission notice appear in all copies.
19 19 *
20 20 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
21 21 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
22 22 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
23 23 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
24 24 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
25 25 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
26 26 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
27 27 */
28 28
29 29 /*
30 30 * Driver for Intel PRO/Wireless 4965AGN(kedron) 802.11 network adapters.
31 31 */
32 32
33 33 #include <sys/types.h>
34 34 #include <sys/byteorder.h>
35 35 #include <sys/conf.h>
36 36 #include <sys/cmn_err.h>
37 37 #include <sys/stat.h>
38 38 #include <sys/ddi.h>
39 39 #include <sys/sunddi.h>
40 40 #include <sys/strsubr.h>
41 41 #include <sys/ethernet.h>
42 42 #include <inet/common.h>
43 43 #include <inet/nd.h>
44 44 #include <inet/mi.h>
45 45 #include <sys/note.h>
46 46 #include <sys/stream.h>
47 47 #include <sys/strsun.h>
48 48 #include <sys/modctl.h>
49 49 #include <sys/devops.h>
50 50 #include <sys/dlpi.h>
51 51 #include <sys/mac_provider.h>
52 52 #include <sys/mac_wifi.h>
53 53 #include <sys/net80211.h>
54 54 #include <sys/net80211_proto.h>
55 55 #include <sys/varargs.h>
56 56 #include <sys/policy.h>
57 57 #include <sys/pci.h>
58 58
59 59 #include "iwk_calibration.h"
60 60 #include "iwk_hw.h"
61 61 #include "iwk_eeprom.h"
62 62 #include "iwk2_var.h"
63 63 #include <inet/wifi_ioctl.h>
64 64
65 65 #ifdef DEBUG
66 66 #define IWK_DEBUG_80211 (1 << 0)
67 67 #define IWK_DEBUG_CMD (1 << 1)
68 68 #define IWK_DEBUG_DMA (1 << 2)
69 69 #define IWK_DEBUG_EEPROM (1 << 3)
70 70 #define IWK_DEBUG_FW (1 << 4)
71 71 #define IWK_DEBUG_HW (1 << 5)
72 72 #define IWK_DEBUG_INTR (1 << 6)
73 73 #define IWK_DEBUG_MRR (1 << 7)
74 74 #define IWK_DEBUG_PIO (1 << 8)
75 75 #define IWK_DEBUG_RX (1 << 9)
76 76 #define IWK_DEBUG_SCAN (1 << 10)
77 77 #define IWK_DEBUG_TX (1 << 11)
78 78 #define IWK_DEBUG_RATECTL (1 << 12)
79 79 #define IWK_DEBUG_RADIO (1 << 13)
80 80 #define IWK_DEBUG_RESUME (1 << 14)
81 81 #define IWK_DEBUG_CALIBRATION (1 << 15)
82 82 uint32_t iwk_dbg_flags = 0;
83 83 #define IWK_DBG(x) \
84 84 iwk_dbg x
85 85 #else
86 86 #define IWK_DBG(x)
87 87 #endif
88 88
89 89 static void *iwk_soft_state_p = NULL;
90 90 static uint8_t iwk_fw_bin [] = {
91 91 #include "fw-iw/iw4965.ucode.hex"
92 92 };
93 93
94 94 /* DMA attributes for a shared page */
95 95 static ddi_dma_attr_t sh_dma_attr = {
96 96 DMA_ATTR_V0, /* version of this structure */
97 97 0, /* lowest usable address */
98 98 0xffffffffU, /* highest usable address */
99 99 0xffffffffU, /* maximum DMAable byte count */
100 100 0x1000, /* alignment in bytes */
101 101 0x1000, /* burst sizes (any?) */
102 102 1, /* minimum transfer */
103 103 0xffffffffU, /* maximum transfer */
104 104 0xffffffffU, /* maximum segment length */
105 105 1, /* maximum number of segments */
106 106 1, /* granularity */
107 107 0, /* flags (reserved) */
108 108 };
109 109
110 110 /* DMA attributes for a keep warm DRAM descriptor */
111 111 static ddi_dma_attr_t kw_dma_attr = {
112 112 DMA_ATTR_V0, /* version of this structure */
113 113 0, /* lowest usable address */
114 114 0xffffffffU, /* highest usable address */
115 115 0xffffffffU, /* maximum DMAable byte count */
116 116 0x1000, /* alignment in bytes */
117 117 0x1000, /* burst sizes (any?) */
118 118 1, /* minimum transfer */
119 119 0xffffffffU, /* maximum transfer */
120 120 0xffffffffU, /* maximum segment length */
121 121 1, /* maximum number of segments */
122 122 1, /* granularity */
123 123 0, /* flags (reserved) */
124 124 };
125 125
126 126 /* DMA attributes for a ring descriptor */
127 127 static ddi_dma_attr_t ring_desc_dma_attr = {
128 128 DMA_ATTR_V0, /* version of this structure */
129 129 0, /* lowest usable address */
130 130 0xffffffffU, /* highest usable address */
131 131 0xffffffffU, /* maximum DMAable byte count */
132 132 0x100, /* alignment in bytes */
133 133 0x100, /* burst sizes (any?) */
134 134 1, /* minimum transfer */
135 135 0xffffffffU, /* maximum transfer */
136 136 0xffffffffU, /* maximum segment length */
137 137 1, /* maximum number of segments */
138 138 1, /* granularity */
139 139 0, /* flags (reserved) */
140 140 };
141 141
142 142 /* DMA attributes for a cmd */
143 143 static ddi_dma_attr_t cmd_dma_attr = {
144 144 DMA_ATTR_V0, /* version of this structure */
145 145 0, /* lowest usable address */
146 146 0xffffffffU, /* highest usable address */
147 147 0xffffffffU, /* maximum DMAable byte count */
148 148 4, /* alignment in bytes */
149 149 0x100, /* burst sizes (any?) */
150 150 1, /* minimum transfer */
151 151 0xffffffffU, /* maximum transfer */
152 152 0xffffffffU, /* maximum segment length */
153 153 1, /* maximum number of segments */
154 154 1, /* granularity */
155 155 0, /* flags (reserved) */
156 156 };
157 157
158 158 /* DMA attributes for a rx buffer */
159 159 static ddi_dma_attr_t rx_buffer_dma_attr = {
160 160 DMA_ATTR_V0, /* version of this structure */
161 161 0, /* lowest usable address */
162 162 0xffffffffU, /* highest usable address */
163 163 0xffffffffU, /* maximum DMAable byte count */
164 164 0x100, /* alignment in bytes */
165 165 0x100, /* burst sizes (any?) */
166 166 1, /* minimum transfer */
167 167 0xffffffffU, /* maximum transfer */
168 168 0xffffffffU, /* maximum segment length */
169 169 1, /* maximum number of segments */
170 170 1, /* granularity */
171 171 0, /* flags (reserved) */
172 172 };
173 173
174 174 /*
175 175 * DMA attributes for a tx buffer.
176 176 * the maximum number of segments is 4 for the hardware.
177 177 * now all the wifi drivers put the whole frame in a single
178 178 * descriptor, so we define the maximum number of segments 1,
179 179 * just the same as the rx_buffer. we consider leverage the HW
180 180 * ability in the future, that is why we don't define rx and tx
181 181 * buffer_dma_attr as the same.
182 182 */
183 183 static ddi_dma_attr_t tx_buffer_dma_attr = {
184 184 DMA_ATTR_V0, /* version of this structure */
185 185 0, /* lowest usable address */
186 186 0xffffffffU, /* highest usable address */
187 187 0xffffffffU, /* maximum DMAable byte count */
188 188 4, /* alignment in bytes */
189 189 0x100, /* burst sizes (any?) */
190 190 1, /* minimum transfer */
191 191 0xffffffffU, /* maximum transfer */
192 192 0xffffffffU, /* maximum segment length */
193 193 1, /* maximum number of segments */
194 194 1, /* granularity */
195 195 0, /* flags (reserved) */
196 196 };
197 197
198 198 /* DMA attributes for text and data part in the firmware */
199 199 static ddi_dma_attr_t fw_dma_attr = {
200 200 DMA_ATTR_V0, /* version of this structure */
201 201 0, /* lowest usable address */
202 202 0xffffffffU, /* highest usable address */
203 203 0x7fffffff, /* maximum DMAable byte count */
204 204 0x10, /* alignment in bytes */
205 205 0x100, /* burst sizes (any?) */
206 206 1, /* minimum transfer */
207 207 0xffffffffU, /* maximum transfer */
208 208 0xffffffffU, /* maximum segment length */
209 209 1, /* maximum number of segments */
210 210 1, /* granularity */
211 211 0, /* flags (reserved) */
212 212 };
213 213
214 214
215 215 /* regs access attributes */
216 216 static ddi_device_acc_attr_t iwk_reg_accattr = {
217 217 DDI_DEVICE_ATTR_V0,
218 218 DDI_STRUCTURE_LE_ACC,
219 219 DDI_STRICTORDER_ACC,
220 220 DDI_DEFAULT_ACC
221 221 };
222 222
223 223 /* DMA access attributes for Descriptor */
224 224 static ddi_device_acc_attr_t iwk_dma_descattr = {
225 225 DDI_DEVICE_ATTR_V0,
226 226 DDI_STRUCTURE_LE_ACC,
227 227 DDI_STRICTORDER_ACC,
228 228 DDI_DEFAULT_ACC
229 229 };
230 230
231 231 /* DMA access attributes */
232 232 static ddi_device_acc_attr_t iwk_dma_accattr = {
233 233 DDI_DEVICE_ATTR_V0,
234 234 DDI_NEVERSWAP_ACC,
235 235 DDI_STRICTORDER_ACC,
236 236 DDI_DEFAULT_ACC
237 237 };
238 238
239 239 static int iwk_ring_init(iwk_sc_t *);
240 240 static void iwk_ring_free(iwk_sc_t *);
241 241 static int iwk_alloc_shared(iwk_sc_t *);
242 242 static void iwk_free_shared(iwk_sc_t *);
243 243 static int iwk_alloc_kw(iwk_sc_t *);
244 244 static void iwk_free_kw(iwk_sc_t *);
245 245 static int iwk_alloc_fw_dma(iwk_sc_t *);
246 246 static void iwk_free_fw_dma(iwk_sc_t *);
247 247 static int iwk_alloc_rx_ring(iwk_sc_t *);
248 248 static void iwk_reset_rx_ring(iwk_sc_t *);
249 249 static void iwk_free_rx_ring(iwk_sc_t *);
250 250 static int iwk_alloc_tx_ring(iwk_sc_t *, iwk_tx_ring_t *,
251 251 int, int);
252 252 static void iwk_reset_tx_ring(iwk_sc_t *, iwk_tx_ring_t *);
253 253 static void iwk_free_tx_ring(iwk_sc_t *, iwk_tx_ring_t *);
254 254
255 255 static ieee80211_node_t *iwk_node_alloc(ieee80211com_t *);
256 256 static void iwk_node_free(ieee80211_node_t *);
257 257 static int iwk_newstate(ieee80211com_t *, enum ieee80211_state, int);
258 258 static int iwk_key_set(ieee80211com_t *, const struct ieee80211_key *,
259 259 const uint8_t mac[IEEE80211_ADDR_LEN]);
260 260 static void iwk_mac_access_enter(iwk_sc_t *);
261 261 static void iwk_mac_access_exit(iwk_sc_t *);
262 262 static uint32_t iwk_reg_read(iwk_sc_t *, uint32_t);
263 263 static void iwk_reg_write(iwk_sc_t *, uint32_t, uint32_t);
264 264 static void iwk_reg_write_region_4(iwk_sc_t *, uint32_t,
265 265 uint32_t *, int);
266 266 static int iwk_load_firmware(iwk_sc_t *);
267 267 static void iwk_rx_intr(iwk_sc_t *, iwk_rx_desc_t *,
268 268 iwk_rx_data_t *);
269 269 static void iwk_tx_intr(iwk_sc_t *, iwk_rx_desc_t *,
270 270 iwk_rx_data_t *);
271 271 static void iwk_cmd_intr(iwk_sc_t *, iwk_rx_desc_t *);
272 272 static uint_t iwk_intr(caddr_t, caddr_t);
273 273 static int iwk_eep_load(iwk_sc_t *sc);
274 274 static void iwk_get_mac_from_eep(iwk_sc_t *sc);
275 275 static int iwk_eep_sem_down(iwk_sc_t *sc);
276 276 static void iwk_eep_sem_up(iwk_sc_t *sc);
277 277 static uint_t iwk_rx_softintr(caddr_t, caddr_t);
278 278 static uint8_t iwk_rate_to_plcp(int);
279 279 static int iwk_cmd(iwk_sc_t *, int, const void *, int, int);
280 280 static void iwk_set_led(iwk_sc_t *, uint8_t, uint8_t, uint8_t);
281 281 static int iwk_hw_set_before_auth(iwk_sc_t *);
282 282 static int iwk_scan(iwk_sc_t *);
283 283 static int iwk_config(iwk_sc_t *);
284 284 static void iwk_stop_master(iwk_sc_t *);
285 285 static int iwk_power_up(iwk_sc_t *);
286 286 static int iwk_preinit(iwk_sc_t *);
287 287 static int iwk_init(iwk_sc_t *);
288 288 static void iwk_stop(iwk_sc_t *);
289 289 static void iwk_amrr_init(iwk_amrr_t *);
290 290 static void iwk_amrr_timeout(iwk_sc_t *);
291 291 static void iwk_amrr_ratectl(void *, ieee80211_node_t *);
292 292 static int32_t iwk_curr_tempera(iwk_sc_t *sc);
293 293 static int iwk_tx_power_calibration(iwk_sc_t *sc);
294 294 static inline int iwk_is_24G_band(iwk_sc_t *sc);
295 295 static inline int iwk_is_fat_channel(iwk_sc_t *sc);
296 296 static int iwk_txpower_grp(uint16_t channel);
297 297 static struct iwk_eep_channel *iwk_get_eep_channel(iwk_sc_t *sc,
298 298 uint16_t channel,
299 299 int is_24G, int is_fat, int is_hi_chan);
300 300 static int32_t iwk_band_number(iwk_sc_t *sc, uint16_t channel);
301 301 static int iwk_division(int32_t num, int32_t denom, int32_t *res);
302 302 static int32_t iwk_interpolate_value(int32_t x, int32_t x1, int32_t y1,
303 303 int32_t x2, int32_t y2);
304 304 static int iwk_channel_interpolate(iwk_sc_t *sc, uint16_t channel,
305 305 struct iwk_eep_calib_channel_info *chan_info);
306 306 static int32_t iwk_voltage_compensation(int32_t eep_voltage,
307 307 int32_t curr_voltage);
308 308 static int32_t iwk_min_power_index(int32_t rate_pow_idx, int32_t is_24G);
309 309 static int iwk_txpower_table_cmd_init(iwk_sc_t *sc,
310 310 struct iwk_tx_power_db *tp_db);
311 311 static void iwk_statistics_notify(iwk_sc_t *sc, iwk_rx_desc_t *desc);
312 312 static int iwk_is_associated(iwk_sc_t *sc);
313 313 static int iwk_rxgain_diff_init(iwk_sc_t *sc);
314 314 static int iwk_rxgain_diff(iwk_sc_t *sc);
315 315 static int iwk_rx_sens_init(iwk_sc_t *sc);
316 316 static int iwk_rx_sens(iwk_sc_t *sc);
317 317 static int iwk_cck_sens(iwk_sc_t *sc, uint32_t actual_rx_time);
318 318 static int iwk_ofdm_sens(iwk_sc_t *sc, uint32_t actual_rx_time);
319 319 static void iwk_recv_mgmt(struct ieee80211com *ic, mblk_t *mp,
320 320 struct ieee80211_node *in, int subtype, int rssi, uint32_t rstamp);
321 321
322 322 static void iwk_write_event_log(iwk_sc_t *);
323 323 static void iwk_write_error_log(iwk_sc_t *);
324 324
325 325 static int iwk_attach(dev_info_t *dip, ddi_attach_cmd_t cmd);
326 326 static int iwk_detach(dev_info_t *dip, ddi_detach_cmd_t cmd);
327 327 static int iwk_quiesce(dev_info_t *dip);
328 328
329 329 /*
330 330 * GLD specific operations
331 331 */
332 332 static int iwk_m_stat(void *arg, uint_t stat, uint64_t *val);
333 333 static int iwk_m_start(void *arg);
334 334 static void iwk_m_stop(void *arg);
335 335 static int iwk_m_unicst(void *arg, const uint8_t *macaddr);
336 336 static int iwk_m_multicst(void *arg, boolean_t add, const uint8_t *m);
337 337 static int iwk_m_promisc(void *arg, boolean_t on);
338 338 static mblk_t *iwk_m_tx(void *arg, mblk_t *mp);
339 339 static void iwk_m_ioctl(void *arg, queue_t *wq, mblk_t *mp);
340 340 static int iwk_m_setprop(void *arg, const char *pr_name,
341 341 mac_prop_id_t wldp_pr_name, uint_t wldp_length, const void *wldp_buf);
342 342 static int iwk_m_getprop(void *arg, const char *pr_name,
343 343 mac_prop_id_t wldp_pr_name, uint_t wldp_length, void *wldp_buf);
344 344 static void iwk_m_propinfo(void *arg, const char *pr_name,
345 345 mac_prop_id_t wldp_pr_num, mac_prop_info_handle_t mph);
346 346 static void iwk_destroy_locks(iwk_sc_t *sc);
347 347 static int iwk_send(ieee80211com_t *ic, mblk_t *mp, uint8_t type);
348 348 static void iwk_thread(iwk_sc_t *sc);
349 349 static void iwk_watchdog(void *arg);
350 350 static int iwk_run_state_config_ibss(ieee80211com_t *ic);
351 351 static int iwk_run_state_config_sta(ieee80211com_t *ic);
352 352 static int iwk_fast_recover(iwk_sc_t *sc);
353 353 static int iwk_start_tx_beacon(ieee80211com_t *ic);
354 354 static int iwk_clean_add_node_ibss(struct ieee80211com *ic,
355 355 uint8_t addr[IEEE80211_ADDR_LEN], uint8_t *index2);
356 356
357 357 /*
358 358 * Supported rates for 802.11b/g modes (in 500Kbps unit).
359 359 * 11a and 11n support will be added later.
360 360 */
361 361 static const struct ieee80211_rateset iwk_rateset_11b =
362 362 { 4, { 2, 4, 11, 22 } };
363 363
364 364 static const struct ieee80211_rateset iwk_rateset_11g =
365 365 { 12, { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 } };
366 366
367 367 /*
368 368 * For mfthread only
369 369 */
370 370 extern pri_t minclsyspri;
371 371
372 372 #define DRV_NAME_4965 "iwk"
373 373
374 374 /*
375 375 * Module Loading Data & Entry Points
376 376 */
377 377 DDI_DEFINE_STREAM_OPS(iwk_devops, nulldev, nulldev, iwk_attach,
|
↓ open down ↓ |
377 lines elided |
↑ open up ↑ |
378 378 iwk_detach, nodev, NULL, D_MP, NULL, iwk_quiesce);
379 379
380 380 static struct modldrv iwk_modldrv = {
381 381 &mod_driverops,
382 382 "Intel(R) 4965AGN driver(N)",
383 383 &iwk_devops
384 384 };
385 385
386 386 static struct modlinkage iwk_modlinkage = {
387 387 MODREV_1,
388 - &iwk_modldrv,
389 - NULL
388 + { &iwk_modldrv, NULL }
390 389 };
391 390
392 391 int
393 392 _init(void)
394 393 {
395 394 int status;
396 395
397 396 status = ddi_soft_state_init(&iwk_soft_state_p,
398 397 sizeof (iwk_sc_t), 1);
399 398 if (status != DDI_SUCCESS)
400 399 return (status);
401 400
402 401 mac_init_ops(&iwk_devops, DRV_NAME_4965);
403 402 status = mod_install(&iwk_modlinkage);
404 403 if (status != DDI_SUCCESS) {
405 404 mac_fini_ops(&iwk_devops);
406 405 ddi_soft_state_fini(&iwk_soft_state_p);
407 406 }
408 407
409 408 return (status);
410 409 }
411 410
412 411 int
413 412 _fini(void)
414 413 {
415 414 int status;
416 415
417 416 status = mod_remove(&iwk_modlinkage);
418 417 if (status == DDI_SUCCESS) {
419 418 mac_fini_ops(&iwk_devops);
420 419 ddi_soft_state_fini(&iwk_soft_state_p);
421 420 }
422 421
423 422 return (status);
424 423 }
425 424
426 425 int
427 426 _info(struct modinfo *mip)
428 427 {
429 428 return (mod_info(&iwk_modlinkage, mip));
430 429 }
431 430
432 431 /*
433 432 * Mac Call Back entries
434 433 */
435 434 mac_callbacks_t iwk_m_callbacks = {
436 435 MC_IOCTL | MC_SETPROP | MC_GETPROP | MC_PROPINFO,
437 436 iwk_m_stat,
438 437 iwk_m_start,
439 438 iwk_m_stop,
440 439 iwk_m_promisc,
441 440 iwk_m_multicst,
442 441 iwk_m_unicst,
443 442 iwk_m_tx,
444 443 NULL,
445 444 iwk_m_ioctl,
446 445 NULL,
447 446 NULL,
448 447 NULL,
449 448 iwk_m_setprop,
450 449 iwk_m_getprop,
451 450 iwk_m_propinfo
452 451 };
453 452
454 453 #ifdef DEBUG
455 454 void
456 455 iwk_dbg(uint32_t flags, const char *fmt, ...)
457 456 {
458 457 va_list ap;
459 458
460 459 if (flags & iwk_dbg_flags) {
461 460 va_start(ap, fmt);
462 461 vcmn_err(CE_NOTE, fmt, ap);
463 462 va_end(ap);
464 463 }
465 464 }
466 465 #endif
467 466
468 467 /*
469 468 * device operations
470 469 */
471 470 int
472 471 iwk_attach(dev_info_t *dip, ddi_attach_cmd_t cmd)
473 472 {
474 473 iwk_sc_t *sc;
475 474 ieee80211com_t *ic;
476 475 int instance, err, i;
477 476 char strbuf[32];
478 477 wifi_data_t wd = { 0 };
479 478 mac_register_t *macp;
480 479
481 480 int intr_type;
482 481 int intr_count;
483 482 int intr_actual;
484 483
485 484 switch (cmd) {
486 485 case DDI_ATTACH:
487 486 break;
488 487 case DDI_RESUME:
489 488 sc = ddi_get_soft_state(iwk_soft_state_p,
490 489 ddi_get_instance(dip));
491 490 ASSERT(sc != NULL);
492 491
493 492 mutex_enter(&sc->sc_glock);
494 493 sc->sc_flags &= ~IWK_F_SUSPEND;
495 494 mutex_exit(&sc->sc_glock);
496 495
497 496 if (sc->sc_flags & IWK_F_RUNNING)
498 497 (void) iwk_init(sc);
499 498
500 499 mutex_enter(&sc->sc_glock);
501 500 sc->sc_flags |= IWK_F_LAZY_RESUME;
502 501 mutex_exit(&sc->sc_glock);
503 502
504 503 IWK_DBG((IWK_DEBUG_RESUME, "iwk: resume\n"));
505 504 return (DDI_SUCCESS);
506 505 default:
507 506 err = DDI_FAILURE;
508 507 goto attach_fail1;
509 508 }
510 509
511 510 instance = ddi_get_instance(dip);
512 511 err = ddi_soft_state_zalloc(iwk_soft_state_p, instance);
513 512 if (err != DDI_SUCCESS) {
514 513 cmn_err(CE_WARN,
515 514 "iwk_attach(): failed to allocate soft state\n");
516 515 goto attach_fail1;
517 516 }
518 517 sc = ddi_get_soft_state(iwk_soft_state_p, instance);
519 518 sc->sc_dip = dip;
520 519
521 520 err = ddi_regs_map_setup(dip, 0, &sc->sc_cfg_base, 0, 0,
522 521 &iwk_reg_accattr, &sc->sc_cfg_handle);
523 522 if (err != DDI_SUCCESS) {
524 523 cmn_err(CE_WARN,
525 524 "iwk_attach(): failed to map config spaces regs\n");
526 525 goto attach_fail2;
527 526 }
528 527 sc->sc_rev = ddi_get8(sc->sc_cfg_handle,
529 528 (uint8_t *)(sc->sc_cfg_base + PCI_CONF_REVID));
530 529 ddi_put8(sc->sc_cfg_handle, (uint8_t *)(sc->sc_cfg_base + 0x41), 0);
531 530 sc->sc_clsz = ddi_get16(sc->sc_cfg_handle,
532 531 (uint16_t *)(sc->sc_cfg_base + PCI_CONF_CACHE_LINESZ));
533 532 if (!sc->sc_clsz)
534 533 sc->sc_clsz = 16;
535 534 sc->sc_clsz = (sc->sc_clsz << 2);
536 535 sc->sc_dmabuf_sz = roundup(0x1000 + sizeof (struct ieee80211_frame) +
537 536 IEEE80211_MTU + IEEE80211_CRC_LEN +
538 537 (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN +
539 538 IEEE80211_WEP_CRCLEN), sc->sc_clsz);
540 539 /*
541 540 * Map operating registers
542 541 */
543 542 err = ddi_regs_map_setup(dip, 1, &sc->sc_base,
544 543 0, 0, &iwk_reg_accattr, &sc->sc_handle);
545 544 if (err != DDI_SUCCESS) {
546 545 cmn_err(CE_WARN,
547 546 "iwk_attach(): failed to map device regs\n");
548 547 goto attach_fail2a;
549 548 }
550 549
551 550 err = ddi_intr_get_supported_types(dip, &intr_type);
552 551 if ((err != DDI_SUCCESS) || (!(intr_type & DDI_INTR_TYPE_FIXED))) {
553 552 cmn_err(CE_WARN, "iwk_attach(): "
554 553 "Fixed type interrupt is not supported\n");
555 554 goto attach_fail_intr_a;
556 555 }
557 556
558 557 err = ddi_intr_get_nintrs(dip, DDI_INTR_TYPE_FIXED, &intr_count);
559 558 if ((err != DDI_SUCCESS) || (intr_count != 1)) {
560 559 cmn_err(CE_WARN, "iwk_attach(): "
561 560 "No fixed interrupts\n");
562 561 goto attach_fail_intr_a;
563 562 }
564 563
565 564 sc->sc_intr_htable = kmem_zalloc(sizeof (ddi_intr_handle_t), KM_SLEEP);
566 565
567 566 err = ddi_intr_alloc(dip, sc->sc_intr_htable, DDI_INTR_TYPE_FIXED, 0,
568 567 intr_count, &intr_actual, 0);
569 568 if ((err != DDI_SUCCESS) || (intr_actual != 1)) {
570 569 cmn_err(CE_WARN, "iwk_attach(): "
571 570 "ddi_intr_alloc() failed 0x%x\n", err);
572 571 goto attach_fail_intr_b;
573 572 }
574 573
575 574 err = ddi_intr_get_pri(sc->sc_intr_htable[0], &sc->sc_intr_pri);
576 575 if (err != DDI_SUCCESS) {
577 576 cmn_err(CE_WARN, "iwk_attach(): "
578 577 "ddi_intr_get_pri() failed 0x%x\n", err);
579 578 goto attach_fail_intr_c;
580 579 }
581 580
582 581 mutex_init(&sc->sc_glock, NULL, MUTEX_DRIVER,
583 582 DDI_INTR_PRI(sc->sc_intr_pri));
584 583 mutex_init(&sc->sc_tx_lock, NULL, MUTEX_DRIVER,
585 584 DDI_INTR_PRI(sc->sc_intr_pri));
586 585 mutex_init(&sc->sc_mt_lock, NULL, MUTEX_DRIVER,
587 586 DDI_INTR_PRI(sc->sc_intr_pri));
588 587 mutex_init(&sc->sc_ibss.node_tb_lock, NULL, MUTEX_DRIVER,
589 588 DDI_INTR_PRI(sc->sc_intr_pri));
590 589
591 590 cv_init(&sc->sc_fw_cv, NULL, CV_DRIVER, NULL);
592 591 cv_init(&sc->sc_cmd_cv, NULL, CV_DRIVER, NULL);
593 592 cv_init(&sc->sc_tx_cv, "tx-ring", CV_DRIVER, NULL);
594 593 /*
595 594 * initialize the mfthread
596 595 */
597 596 cv_init(&sc->sc_mt_cv, NULL, CV_DRIVER, NULL);
598 597 sc->sc_mf_thread = NULL;
599 598 sc->sc_mf_thread_switch = 0;
600 599
601 600 /*
602 601 * Allocate shared page.
603 602 */
604 603 err = iwk_alloc_shared(sc);
605 604 if (err != DDI_SUCCESS) {
606 605 cmn_err(CE_WARN, "iwk_attach(): "
607 606 "failed to allocate shared page\n");
608 607 goto attach_fail3;
609 608 }
610 609
611 610 /*
612 611 * Allocate keep warm page.
613 612 */
614 613 err = iwk_alloc_kw(sc);
615 614 if (err != DDI_SUCCESS) {
616 615 cmn_err(CE_WARN, "iwk_attach(): "
617 616 "failed to allocate keep warm page\n");
618 617 goto attach_fail3a;
619 618 }
620 619
621 620 /*
622 621 * Do some necessary hardware initializations.
623 622 */
624 623 err = iwk_preinit(sc);
625 624 if (err != DDI_SUCCESS) {
626 625 cmn_err(CE_WARN, "iwk_attach(): "
627 626 "failed to init hardware\n");
628 627 goto attach_fail4;
629 628 }
630 629
631 630 /* initialize EEPROM */
632 631 err = iwk_eep_load(sc); /* get hardware configurations from eeprom */
633 632 if (err != 0) {
634 633 cmn_err(CE_WARN, "iwk_attach(): failed to load eeprom\n");
635 634 goto attach_fail4;
636 635 }
637 636
638 637 if (LE_16(sc->sc_eep_map.calib_version) < EEP_TX_POWER_VERSION_NEW) {
639 638 cmn_err(CE_WARN, "older EEPROM detected\n");
640 639 goto attach_fail4;
641 640 }
642 641
643 642 iwk_get_mac_from_eep(sc);
644 643
645 644 err = iwk_ring_init(sc);
646 645 if (err != DDI_SUCCESS) {
647 646 cmn_err(CE_WARN, "iwk_attach(): "
648 647 "failed to allocate and initialize ring\n");
649 648 goto attach_fail4;
650 649 }
651 650
652 651 sc->sc_hdr = (iwk_firmware_hdr_t *)iwk_fw_bin;
653 652
654 653 err = iwk_alloc_fw_dma(sc);
655 654 if (err != DDI_SUCCESS) {
656 655 cmn_err(CE_WARN, "iwk_attach(): "
657 656 "failed to allocate firmware dma\n");
658 657 goto attach_fail5;
659 658 }
660 659
661 660 /*
662 661 * Initialize the wifi part, which will be used by
663 662 * generic layer
664 663 */
665 664 ic = &sc->sc_ic;
666 665 ic->ic_phytype = IEEE80211_T_OFDM;
667 666 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */
668 667 ic->ic_state = IEEE80211_S_INIT;
669 668 ic->ic_maxrssi = 100; /* experimental number */
670 669 ic->ic_caps = IEEE80211_C_SHPREAMBLE | IEEE80211_C_TXPMGT |
671 670 IEEE80211_C_PMGT | IEEE80211_C_SHSLOT;
672 671 /*
673 672 * use software WEP and TKIP, hardware CCMP;
674 673 */
675 674 ic->ic_caps |= IEEE80211_C_AES_CCM;
676 675 /*
677 676 * Support WPA/WPA2
678 677 */
679 678 ic->ic_caps |= IEEE80211_C_WPA;
680 679 /*
681 680 * support Adhoc mode
682 681 */
683 682 ic->ic_caps |= IEEE80211_C_IBSS;
684 683
685 684 /* set supported .11b and .11g rates */
686 685 ic->ic_sup_rates[IEEE80211_MODE_11B] = iwk_rateset_11b;
687 686 ic->ic_sup_rates[IEEE80211_MODE_11G] = iwk_rateset_11g;
688 687
689 688 /* set supported .11b and .11g channels (1 through 11) */
690 689 for (i = 1; i <= 11; i++) {
691 690 ic->ic_sup_channels[i].ich_freq =
692 691 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ);
693 692 ic->ic_sup_channels[i].ich_flags =
694 693 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM |
695 694 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ |
696 695 IEEE80211_CHAN_PASSIVE;
697 696 }
698 697 ic->ic_ibss_chan = &ic->ic_sup_channels[0];
699 698
700 699 ic->ic_xmit = iwk_send;
701 700 /*
702 701 * init Wifi layer
703 702 */
704 703 ieee80211_attach(ic);
705 704
706 705 /*
707 706 * different instance has different WPA door
708 707 */
709 708 (void) snprintf(ic->ic_wpadoor, MAX_IEEE80211STR, "%s_%s%d", WPA_DOOR,
710 709 ddi_driver_name(dip),
711 710 ddi_get_instance(dip));
712 711
713 712 /*
714 713 * Override 80211 default routines
715 714 */
716 715 sc->sc_newstate = ic->ic_newstate;
717 716 ic->ic_newstate = iwk_newstate;
718 717 ic->ic_watchdog = iwk_watchdog;
719 718 sc->sc_recv_mgmt = ic->ic_recv_mgmt;
720 719 ic->ic_recv_mgmt = iwk_recv_mgmt;
721 720 ic->ic_node_alloc = iwk_node_alloc;
722 721 ic->ic_node_free = iwk_node_free;
723 722 ic->ic_crypto.cs_key_set = iwk_key_set;
724 723 ieee80211_media_init(ic);
725 724 /*
726 725 * initialize default tx key
727 726 */
728 727 ic->ic_def_txkey = 0;
729 728 err = ddi_intr_add_softint(dip, &sc->sc_soft_hdl, DDI_INTR_SOFTPRI_MAX,
730 729 iwk_rx_softintr, (caddr_t)sc);
731 730 if (err != DDI_SUCCESS) {
732 731 cmn_err(CE_WARN, "iwk_attach(): "
733 732 "add soft interrupt failed\n");
734 733 goto attach_fail7;
735 734 }
736 735
737 736 /*
738 737 * Add the interrupt handler
739 738 */
740 739 err = ddi_intr_add_handler(sc->sc_intr_htable[0], iwk_intr,
741 740 (caddr_t)sc, NULL);
742 741 if (err != DDI_SUCCESS) {
743 742 cmn_err(CE_WARN, "iwk_attach(): "
744 743 "ddi_intr_add_handle() failed\n");
745 744 goto attach_fail8;
746 745 }
747 746
748 747 err = ddi_intr_enable(sc->sc_intr_htable[0]);
749 748 if (err != DDI_SUCCESS) {
750 749 cmn_err(CE_WARN, "iwk_attach(): "
751 750 "ddi_intr_enable() failed\n");
752 751 goto attach_fail_intr_d;
753 752 }
754 753
755 754 /*
756 755 * Initialize pointer to device specific functions
757 756 */
758 757 wd.wd_secalloc = WIFI_SEC_NONE;
759 758 wd.wd_opmode = ic->ic_opmode;
760 759 IEEE80211_ADDR_COPY(wd.wd_bssid, ic->ic_macaddr);
761 760
762 761 macp = mac_alloc(MAC_VERSION);
763 762 if (macp == NULL) {
764 763 cmn_err(CE_WARN,
765 764 "iwk_attach(): failed to do mac_alloc()\n");
766 765 goto attach_fail9;
767 766 }
768 767
769 768 macp->m_type_ident = MAC_PLUGIN_IDENT_WIFI;
770 769 macp->m_driver = sc;
771 770 macp->m_dip = dip;
772 771 macp->m_src_addr = ic->ic_macaddr;
773 772 macp->m_callbacks = &iwk_m_callbacks;
774 773 macp->m_min_sdu = 0;
775 774 macp->m_max_sdu = IEEE80211_MTU;
776 775 macp->m_pdata = &wd;
777 776 macp->m_pdata_size = sizeof (wd);
778 777
779 778 /*
780 779 * Register the macp to mac
781 780 */
782 781 err = mac_register(macp, &ic->ic_mach);
783 782 mac_free(macp);
784 783 if (err != DDI_SUCCESS) {
785 784 cmn_err(CE_WARN,
786 785 "iwk_attach(): failed to do mac_register()\n");
787 786 goto attach_fail9;
788 787 }
789 788
790 789 /*
791 790 * Create minor node of type DDI_NT_NET_WIFI
792 791 */
793 792 (void) snprintf(strbuf, sizeof (strbuf), DRV_NAME_4965"%d", instance);
794 793 err = ddi_create_minor_node(dip, strbuf, S_IFCHR,
795 794 instance + 1, DDI_NT_NET_WIFI, 0);
796 795 if (err != DDI_SUCCESS)
797 796 cmn_err(CE_WARN,
798 797 "iwk_attach(): failed to do ddi_create_minor_node()\n");
799 798
800 799 /*
801 800 * Notify link is down now
802 801 */
803 802 mac_link_update(ic->ic_mach, LINK_STATE_DOWN);
804 803
805 804 /*
806 805 * create the mf thread to handle the link status,
807 806 * recovery fatal error, etc.
808 807 */
809 808 sc->sc_mf_thread_switch = 1;
810 809 if (sc->sc_mf_thread == NULL)
811 810 sc->sc_mf_thread = thread_create((caddr_t)NULL, 0,
812 811 iwk_thread, sc, 0, &p0, TS_RUN, minclsyspri);
813 812
814 813 sc->sc_flags |= IWK_F_ATTACHED;
815 814
816 815 return (DDI_SUCCESS);
817 816 attach_fail9:
818 817 (void) ddi_intr_disable(sc->sc_intr_htable[0]);
819 818 attach_fail_intr_d:
820 819 (void) ddi_intr_remove_handler(sc->sc_intr_htable[0]);
821 820
822 821 attach_fail8:
823 822 (void) ddi_intr_remove_softint(sc->sc_soft_hdl);
824 823 sc->sc_soft_hdl = NULL;
825 824 attach_fail7:
826 825 ieee80211_detach(ic);
827 826 attach_fail6:
828 827 iwk_free_fw_dma(sc);
829 828 attach_fail5:
830 829 iwk_ring_free(sc);
831 830 attach_fail4:
832 831 iwk_free_kw(sc);
833 832 attach_fail3a:
834 833 iwk_free_shared(sc);
835 834 attach_fail3:
836 835 iwk_destroy_locks(sc);
837 836 attach_fail_intr_c:
838 837 (void) ddi_intr_free(sc->sc_intr_htable[0]);
839 838 attach_fail_intr_b:
840 839 kmem_free(sc->sc_intr_htable, sizeof (ddi_intr_handle_t));
841 840 attach_fail_intr_a:
842 841 ddi_regs_map_free(&sc->sc_handle);
843 842 attach_fail2a:
844 843 ddi_regs_map_free(&sc->sc_cfg_handle);
845 844 attach_fail2:
846 845 ddi_soft_state_free(iwk_soft_state_p, instance);
847 846 attach_fail1:
848 847 return (err);
849 848 }
850 849
851 850 int
852 851 iwk_detach(dev_info_t *dip, ddi_detach_cmd_t cmd)
853 852 {
854 853 iwk_sc_t *sc;
855 854 int err;
856 855
857 856 sc = ddi_get_soft_state(iwk_soft_state_p, ddi_get_instance(dip));
858 857 ASSERT(sc != NULL);
859 858
860 859 switch (cmd) {
861 860 case DDI_DETACH:
862 861 break;
863 862 case DDI_SUSPEND:
864 863 mutex_enter(&sc->sc_glock);
865 864 sc->sc_flags |= IWK_F_SUSPEND;
866 865 mutex_exit(&sc->sc_glock);
867 866 if (sc->sc_flags & IWK_F_RUNNING) {
868 867 iwk_stop(sc);
869 868 }
870 869
871 870 IWK_DBG((IWK_DEBUG_RESUME, "iwk: suspend\n"));
872 871 return (DDI_SUCCESS);
873 872 default:
874 873 return (DDI_FAILURE);
875 874 }
876 875
877 876 if (!(sc->sc_flags & IWK_F_ATTACHED))
878 877 return (DDI_FAILURE);
879 878
880 879 err = mac_disable(sc->sc_ic.ic_mach);
881 880 if (err != DDI_SUCCESS)
882 881 return (err);
883 882
884 883 /*
885 884 * Destroy the mf_thread
886 885 */
887 886 mutex_enter(&sc->sc_mt_lock);
888 887 sc->sc_mf_thread_switch = 0;
889 888 while (sc->sc_mf_thread != NULL) {
890 889 if (cv_wait_sig(&sc->sc_mt_cv, &sc->sc_mt_lock) == 0)
891 890 break;
892 891 }
893 892 mutex_exit(&sc->sc_mt_lock);
894 893
895 894 iwk_stop(sc);
896 895 DELAY(500000);
897 896
898 897 /*
899 898 * Unregiste from the MAC layer subsystem
900 899 */
901 900 (void) mac_unregister(sc->sc_ic.ic_mach);
902 901
903 902 mutex_enter(&sc->sc_glock);
904 903 iwk_free_fw_dma(sc);
905 904 iwk_ring_free(sc);
906 905 iwk_free_kw(sc);
907 906 iwk_free_shared(sc);
908 907 mutex_exit(&sc->sc_glock);
909 908
910 909 (void) ddi_intr_disable(sc->sc_intr_htable[0]);
911 910 (void) ddi_intr_remove_handler(sc->sc_intr_htable[0]);
912 911 (void) ddi_intr_free(sc->sc_intr_htable[0]);
913 912 kmem_free(sc->sc_intr_htable, sizeof (ddi_intr_handle_t));
914 913
915 914 (void) ddi_intr_remove_softint(sc->sc_soft_hdl);
916 915 sc->sc_soft_hdl = NULL;
917 916
918 917 /*
919 918 * detach ieee80211
920 919 */
921 920 ieee80211_detach(&sc->sc_ic);
922 921
923 922 iwk_destroy_locks(sc);
924 923
925 924 ddi_regs_map_free(&sc->sc_handle);
926 925 ddi_regs_map_free(&sc->sc_cfg_handle);
927 926 ddi_remove_minor_node(dip, NULL);
928 927 ddi_soft_state_free(iwk_soft_state_p, ddi_get_instance(dip));
929 928
930 929 return (DDI_SUCCESS);
931 930 }
932 931
933 932 /*
934 933 * quiesce(9E) entry point.
935 934 *
936 935 * This function is called when the system is single-threaded at high
937 936 * PIL with preemption disabled. Therefore, this function must not be
938 937 * blocked.
939 938 *
940 939 * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure.
941 940 * DDI_FAILURE indicates an error condition and should almost never happen.
942 941 */
943 942 int
944 943 iwk_quiesce(dev_info_t *dip)
945 944 {
946 945 iwk_sc_t *sc;
947 946
948 947 sc = ddi_get_soft_state(iwk_soft_state_p, ddi_get_instance(dip));
949 948 ASSERT(sc != NULL);
950 949
951 950 /* no message prints and no lock accquisition */
952 951 #ifdef DEBUG
953 952 iwk_dbg_flags = 0;
954 953 #endif
955 954 sc->sc_flags |= IWK_F_QUIESCED;
956 955
957 956 iwk_stop(sc);
958 957
959 958 return (DDI_SUCCESS);
960 959 }
961 960
962 961 static void
963 962 iwk_destroy_locks(iwk_sc_t *sc)
964 963 {
965 964 cv_destroy(&sc->sc_mt_cv);
966 965 mutex_destroy(&sc->sc_mt_lock);
967 966 cv_destroy(&sc->sc_tx_cv);
968 967 cv_destroy(&sc->sc_cmd_cv);
969 968 cv_destroy(&sc->sc_fw_cv);
970 969 mutex_destroy(&sc->sc_tx_lock);
971 970 mutex_destroy(&sc->sc_glock);
972 971 }
973 972
974 973 /*
975 974 * Allocate an area of memory and a DMA handle for accessing it
976 975 */
977 976 static int
978 977 iwk_alloc_dma_mem(iwk_sc_t *sc, size_t memsize,
979 978 ddi_dma_attr_t *dma_attr_p, ddi_device_acc_attr_t *acc_attr_p,
980 979 uint_t dma_flags, iwk_dma_t *dma_p)
981 980 {
982 981 caddr_t vaddr;
983 982 int err;
984 983
985 984 /*
986 985 * Allocate handle
987 986 */
988 987 err = ddi_dma_alloc_handle(sc->sc_dip, dma_attr_p,
989 988 DDI_DMA_SLEEP, NULL, &dma_p->dma_hdl);
990 989 if (err != DDI_SUCCESS) {
991 990 dma_p->dma_hdl = NULL;
992 991 return (DDI_FAILURE);
993 992 }
994 993
995 994 /*
996 995 * Allocate memory
997 996 */
998 997 err = ddi_dma_mem_alloc(dma_p->dma_hdl, memsize, acc_attr_p,
999 998 dma_flags & (DDI_DMA_CONSISTENT | DDI_DMA_STREAMING),
1000 999 DDI_DMA_SLEEP, NULL, &vaddr, &dma_p->alength, &dma_p->acc_hdl);
1001 1000 if (err != DDI_SUCCESS) {
1002 1001 ddi_dma_free_handle(&dma_p->dma_hdl);
1003 1002 dma_p->dma_hdl = NULL;
1004 1003 dma_p->acc_hdl = NULL;
1005 1004 return (DDI_FAILURE);
1006 1005 }
1007 1006
1008 1007 /*
1009 1008 * Bind the two together
1010 1009 */
1011 1010 dma_p->mem_va = vaddr;
1012 1011 err = ddi_dma_addr_bind_handle(dma_p->dma_hdl, NULL,
1013 1012 vaddr, dma_p->alength, dma_flags, DDI_DMA_SLEEP, NULL,
1014 1013 &dma_p->cookie, &dma_p->ncookies);
1015 1014 if (err != DDI_DMA_MAPPED) {
1016 1015 ddi_dma_mem_free(&dma_p->acc_hdl);
1017 1016 ddi_dma_free_handle(&dma_p->dma_hdl);
1018 1017 dma_p->acc_hdl = NULL;
1019 1018 dma_p->dma_hdl = NULL;
1020 1019 return (DDI_FAILURE);
1021 1020 }
1022 1021
1023 1022 dma_p->nslots = ~0U;
1024 1023 dma_p->size = ~0U;
1025 1024 dma_p->token = ~0U;
1026 1025 dma_p->offset = 0;
1027 1026 return (DDI_SUCCESS);
1028 1027 }
1029 1028
1030 1029 /*
1031 1030 * Free one allocated area of DMAable memory
1032 1031 */
1033 1032 static void
1034 1033 iwk_free_dma_mem(iwk_dma_t *dma_p)
1035 1034 {
1036 1035 if (dma_p->dma_hdl != NULL) {
1037 1036 if (dma_p->ncookies) {
1038 1037 (void) ddi_dma_unbind_handle(dma_p->dma_hdl);
1039 1038 dma_p->ncookies = 0;
1040 1039 }
1041 1040 ddi_dma_free_handle(&dma_p->dma_hdl);
1042 1041 dma_p->dma_hdl = NULL;
1043 1042 }
1044 1043
1045 1044 if (dma_p->acc_hdl != NULL) {
1046 1045 ddi_dma_mem_free(&dma_p->acc_hdl);
1047 1046 dma_p->acc_hdl = NULL;
1048 1047 }
1049 1048 }
1050 1049
1051 1050 /*
1052 1051 *
1053 1052 */
1054 1053 static int
1055 1054 iwk_alloc_fw_dma(iwk_sc_t *sc)
1056 1055 {
1057 1056 int err = DDI_SUCCESS;
1058 1057 iwk_dma_t *dma_p;
1059 1058 char *t;
1060 1059
1061 1060 /*
1062 1061 * firmware image layout:
1063 1062 * |HDR|<-TEXT->|<-DATA->|<-INIT_TEXT->|<-INIT_DATA->|<-BOOT->|
1064 1063 */
1065 1064 t = (char *)(sc->sc_hdr + 1);
1066 1065 err = iwk_alloc_dma_mem(sc, LE_32(sc->sc_hdr->textsz),
1067 1066 &fw_dma_attr, &iwk_dma_accattr,
1068 1067 DDI_DMA_RDWR | DDI_DMA_CONSISTENT,
1069 1068 &sc->sc_dma_fw_text);
1070 1069 dma_p = &sc->sc_dma_fw_text;
1071 1070 IWK_DBG((IWK_DEBUG_DMA, "text[ncookies:%d addr:%lx size:%lx]\n",
1072 1071 dma_p->ncookies, dma_p->cookie.dmac_address,
1073 1072 dma_p->cookie.dmac_size));
1074 1073 if (err != DDI_SUCCESS) {
1075 1074 cmn_err(CE_WARN, "iwk_alloc_fw_dma(): failed to alloc"
1076 1075 " text dma memory");
1077 1076 goto fail;
1078 1077 }
1079 1078 (void) memcpy(dma_p->mem_va, t, LE_32(sc->sc_hdr->textsz));
1080 1079
1081 1080 t += LE_32(sc->sc_hdr->textsz);
1082 1081 err = iwk_alloc_dma_mem(sc, LE_32(sc->sc_hdr->datasz),
1083 1082 &fw_dma_attr, &iwk_dma_accattr,
1084 1083 DDI_DMA_RDWR | DDI_DMA_CONSISTENT,
1085 1084 &sc->sc_dma_fw_data);
1086 1085 dma_p = &sc->sc_dma_fw_data;
1087 1086 IWK_DBG((IWK_DEBUG_DMA, "data[ncookies:%d addr:%lx size:%lx]\n",
1088 1087 dma_p->ncookies, dma_p->cookie.dmac_address,
1089 1088 dma_p->cookie.dmac_size));
1090 1089 if (err != DDI_SUCCESS) {
1091 1090 cmn_err(CE_WARN, "iwk_alloc_fw_dma(): failed to alloc"
1092 1091 " data dma memory");
1093 1092 goto fail;
1094 1093 }
1095 1094 (void) memcpy(dma_p->mem_va, t, LE_32(sc->sc_hdr->datasz));
1096 1095
1097 1096 err = iwk_alloc_dma_mem(sc, LE_32(sc->sc_hdr->datasz),
1098 1097 &fw_dma_attr, &iwk_dma_accattr,
1099 1098 DDI_DMA_RDWR | DDI_DMA_CONSISTENT,
1100 1099 &sc->sc_dma_fw_data_bak);
1101 1100 dma_p = &sc->sc_dma_fw_data_bak;
1102 1101 IWK_DBG((IWK_DEBUG_DMA, "data_bak[ncookies:%d addr:%lx "
1103 1102 "size:%lx]\n",
1104 1103 dma_p->ncookies, dma_p->cookie.dmac_address,
1105 1104 dma_p->cookie.dmac_size));
1106 1105 if (err != DDI_SUCCESS) {
1107 1106 cmn_err(CE_WARN, "iwk_alloc_fw_dma(): failed to alloc"
1108 1107 " data bakeup dma memory");
1109 1108 goto fail;
1110 1109 }
1111 1110 (void) memcpy(dma_p->mem_va, t, LE_32(sc->sc_hdr->datasz));
1112 1111
1113 1112 t += LE_32(sc->sc_hdr->datasz);
1114 1113 err = iwk_alloc_dma_mem(sc, LE_32(sc->sc_hdr->init_textsz),
1115 1114 &fw_dma_attr, &iwk_dma_accattr,
1116 1115 DDI_DMA_RDWR | DDI_DMA_CONSISTENT,
1117 1116 &sc->sc_dma_fw_init_text);
1118 1117 dma_p = &sc->sc_dma_fw_init_text;
1119 1118 IWK_DBG((IWK_DEBUG_DMA, "init_text[ncookies:%d addr:%lx "
1120 1119 "size:%lx]\n",
1121 1120 dma_p->ncookies, dma_p->cookie.dmac_address,
1122 1121 dma_p->cookie.dmac_size));
1123 1122 if (err != DDI_SUCCESS) {
1124 1123 cmn_err(CE_WARN, "iwk_alloc_fw_dma(): failed to alloc"
1125 1124 "init text dma memory");
1126 1125 goto fail;
1127 1126 }
1128 1127 (void) memcpy(dma_p->mem_va, t, LE_32(sc->sc_hdr->init_textsz));
1129 1128
1130 1129 t += LE_32(sc->sc_hdr->init_textsz);
1131 1130 err = iwk_alloc_dma_mem(sc, LE_32(sc->sc_hdr->init_datasz),
1132 1131 &fw_dma_attr, &iwk_dma_accattr,
1133 1132 DDI_DMA_RDWR | DDI_DMA_CONSISTENT,
1134 1133 &sc->sc_dma_fw_init_data);
1135 1134 dma_p = &sc->sc_dma_fw_init_data;
1136 1135 IWK_DBG((IWK_DEBUG_DMA, "init_data[ncookies:%d addr:%lx "
1137 1136 "size:%lx]\n",
1138 1137 dma_p->ncookies, dma_p->cookie.dmac_address,
1139 1138 dma_p->cookie.dmac_size));
1140 1139 if (err != DDI_SUCCESS) {
1141 1140 cmn_err(CE_WARN, "iwk_alloc_fw_dma(): failed to alloc"
1142 1141 "init data dma memory");
1143 1142 goto fail;
1144 1143 }
1145 1144 (void) memcpy(dma_p->mem_va, t, LE_32(sc->sc_hdr->init_datasz));
1146 1145
1147 1146 sc->sc_boot = t + LE_32(sc->sc_hdr->init_datasz);
1148 1147 fail:
1149 1148 return (err);
1150 1149 }
1151 1150
1152 1151 static void
1153 1152 iwk_free_fw_dma(iwk_sc_t *sc)
1154 1153 {
1155 1154 iwk_free_dma_mem(&sc->sc_dma_fw_text);
1156 1155 iwk_free_dma_mem(&sc->sc_dma_fw_data);
1157 1156 iwk_free_dma_mem(&sc->sc_dma_fw_data_bak);
1158 1157 iwk_free_dma_mem(&sc->sc_dma_fw_init_text);
1159 1158 iwk_free_dma_mem(&sc->sc_dma_fw_init_data);
1160 1159 }
1161 1160
1162 1161 /*
1163 1162 * Allocate a shared page between host and NIC.
1164 1163 */
1165 1164 static int
1166 1165 iwk_alloc_shared(iwk_sc_t *sc)
1167 1166 {
1168 1167 iwk_dma_t *dma_p;
1169 1168 int err = DDI_SUCCESS;
1170 1169
1171 1170 /* must be aligned on a 4K-page boundary */
1172 1171 err = iwk_alloc_dma_mem(sc, sizeof (iwk_shared_t),
1173 1172 &sh_dma_attr, &iwk_dma_descattr,
1174 1173 DDI_DMA_RDWR | DDI_DMA_CONSISTENT,
1175 1174 &sc->sc_dma_sh);
1176 1175 if (err != DDI_SUCCESS)
1177 1176 goto fail;
1178 1177 sc->sc_shared = (iwk_shared_t *)sc->sc_dma_sh.mem_va;
1179 1178
1180 1179 dma_p = &sc->sc_dma_sh;
1181 1180 IWK_DBG((IWK_DEBUG_DMA, "sh[ncookies:%d addr:%lx size:%lx]\n",
1182 1181 dma_p->ncookies, dma_p->cookie.dmac_address,
1183 1182 dma_p->cookie.dmac_size));
1184 1183
1185 1184 return (err);
1186 1185 fail:
1187 1186 iwk_free_shared(sc);
1188 1187 return (err);
1189 1188 }
1190 1189
1191 1190 static void
1192 1191 iwk_free_shared(iwk_sc_t *sc)
1193 1192 {
1194 1193 iwk_free_dma_mem(&sc->sc_dma_sh);
1195 1194 }
1196 1195
1197 1196 /*
1198 1197 * Allocate a keep warm page.
1199 1198 */
1200 1199 static int
1201 1200 iwk_alloc_kw(iwk_sc_t *sc)
1202 1201 {
1203 1202 iwk_dma_t *dma_p;
1204 1203 int err = DDI_SUCCESS;
1205 1204
1206 1205 /* must be aligned on a 4K-page boundary */
1207 1206 err = iwk_alloc_dma_mem(sc, IWK_KW_SIZE,
1208 1207 &kw_dma_attr, &iwk_dma_accattr,
1209 1208 DDI_DMA_RDWR | DDI_DMA_CONSISTENT,
1210 1209 &sc->sc_dma_kw);
1211 1210 if (err != DDI_SUCCESS)
1212 1211 goto fail;
1213 1212
1214 1213 dma_p = &sc->sc_dma_kw;
1215 1214 IWK_DBG((IWK_DEBUG_DMA, "kw[ncookies:%d addr:%lx size:%lx]\n",
1216 1215 dma_p->ncookies, dma_p->cookie.dmac_address,
1217 1216 dma_p->cookie.dmac_size));
1218 1217
1219 1218 return (err);
1220 1219 fail:
1221 1220 iwk_free_kw(sc);
1222 1221 return (err);
1223 1222 }
1224 1223
1225 1224 static void
1226 1225 iwk_free_kw(iwk_sc_t *sc)
1227 1226 {
1228 1227 iwk_free_dma_mem(&sc->sc_dma_kw);
1229 1228 }
1230 1229
1231 1230 static int
1232 1231 iwk_alloc_rx_ring(iwk_sc_t *sc)
1233 1232 {
1234 1233 iwk_rx_ring_t *ring;
1235 1234 iwk_rx_data_t *data;
1236 1235 iwk_dma_t *dma_p;
1237 1236 int i, err = DDI_SUCCESS;
1238 1237
1239 1238 ring = &sc->sc_rxq;
1240 1239 ring->cur = 0;
1241 1240
1242 1241 err = iwk_alloc_dma_mem(sc, RX_QUEUE_SIZE * sizeof (uint32_t),
1243 1242 &ring_desc_dma_attr, &iwk_dma_descattr,
1244 1243 DDI_DMA_RDWR | DDI_DMA_CONSISTENT,
1245 1244 &ring->dma_desc);
1246 1245 if (err != DDI_SUCCESS) {
1247 1246 cmn_err(CE_WARN, "dma alloc rx ring desc failed\n");
1248 1247 goto fail;
1249 1248 }
1250 1249 ring->desc = (uint32_t *)ring->dma_desc.mem_va;
1251 1250 dma_p = &ring->dma_desc;
1252 1251 IWK_DBG((IWK_DEBUG_DMA, "rx bd[ncookies:%d addr:%lx size:%lx]\n",
1253 1252 dma_p->ncookies, dma_p->cookie.dmac_address,
1254 1253 dma_p->cookie.dmac_size));
1255 1254
1256 1255 /*
1257 1256 * Allocate Rx buffers.
1258 1257 */
1259 1258 for (i = 0; i < RX_QUEUE_SIZE; i++) {
1260 1259 data = &ring->data[i];
1261 1260 err = iwk_alloc_dma_mem(sc, sc->sc_dmabuf_sz,
1262 1261 &rx_buffer_dma_attr, &iwk_dma_accattr,
1263 1262 DDI_DMA_READ | DDI_DMA_STREAMING,
1264 1263 &data->dma_data);
1265 1264 if (err != DDI_SUCCESS) {
1266 1265 cmn_err(CE_WARN, "dma alloc rx ring buf[%d] "
1267 1266 "failed\n", i);
1268 1267 goto fail;
1269 1268 }
1270 1269 /*
1271 1270 * the physical address bit [8-36] are used,
1272 1271 * instead of bit [0-31] in 3945.
1273 1272 */
1274 1273 ring->desc[i] = (uint32_t)
1275 1274 (data->dma_data.cookie.dmac_address >> 8);
1276 1275 }
1277 1276 dma_p = &ring->data[0].dma_data;
1278 1277 IWK_DBG((IWK_DEBUG_DMA, "rx buffer[0][ncookies:%d addr:%lx "
1279 1278 "size:%lx]\n",
1280 1279 dma_p->ncookies, dma_p->cookie.dmac_address,
1281 1280 dma_p->cookie.dmac_size));
1282 1281
1283 1282 IWK_DMA_SYNC(ring->dma_desc, DDI_DMA_SYNC_FORDEV);
1284 1283
1285 1284 return (err);
1286 1285
1287 1286 fail:
1288 1287 iwk_free_rx_ring(sc);
1289 1288 return (err);
1290 1289 }
1291 1290
1292 1291 static void
1293 1292 iwk_reset_rx_ring(iwk_sc_t *sc)
1294 1293 {
1295 1294 int n;
1296 1295
1297 1296 iwk_mac_access_enter(sc);
1298 1297 IWK_WRITE(sc, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
1299 1298 for (n = 0; n < 2000; n++) {
1300 1299 if (IWK_READ(sc, FH_MEM_RSSR_RX_STATUS_REG) & (1 << 24))
1301 1300 break;
1302 1301 DELAY(1000);
1303 1302 }
1304 1303
1305 1304 if (n == 2000)
1306 1305 IWK_DBG((IWK_DEBUG_DMA, "timeout resetting Rx ring\n"));
1307 1306
1308 1307 iwk_mac_access_exit(sc);
1309 1308
1310 1309 sc->sc_rxq.cur = 0;
1311 1310 }
1312 1311
1313 1312 static void
1314 1313 iwk_free_rx_ring(iwk_sc_t *sc)
1315 1314 {
1316 1315 int i;
1317 1316
1318 1317 for (i = 0; i < RX_QUEUE_SIZE; i++) {
1319 1318 if (sc->sc_rxq.data[i].dma_data.dma_hdl)
1320 1319 IWK_DMA_SYNC(sc->sc_rxq.data[i].dma_data,
1321 1320 DDI_DMA_SYNC_FORCPU);
1322 1321 iwk_free_dma_mem(&sc->sc_rxq.data[i].dma_data);
1323 1322 }
1324 1323
1325 1324 if (sc->sc_rxq.dma_desc.dma_hdl)
1326 1325 IWK_DMA_SYNC(sc->sc_rxq.dma_desc, DDI_DMA_SYNC_FORDEV);
1327 1326 iwk_free_dma_mem(&sc->sc_rxq.dma_desc);
1328 1327 }
1329 1328
1330 1329 static int
1331 1330 iwk_alloc_tx_ring(iwk_sc_t *sc, iwk_tx_ring_t *ring,
1332 1331 int slots, int qid)
1333 1332 {
1334 1333 iwk_tx_data_t *data;
1335 1334 iwk_tx_desc_t *desc_h;
1336 1335 uint32_t paddr_desc_h;
1337 1336 iwk_cmd_t *cmd_h;
1338 1337 uint32_t paddr_cmd_h;
1339 1338 iwk_dma_t *dma_p;
1340 1339 int i, err = DDI_SUCCESS;
1341 1340
1342 1341 ring->qid = qid;
1343 1342 ring->count = TFD_QUEUE_SIZE_MAX;
1344 1343 ring->window = slots;
1345 1344 ring->queued = 0;
1346 1345 ring->cur = 0;
1347 1346
1348 1347 err = iwk_alloc_dma_mem(sc,
1349 1348 TFD_QUEUE_SIZE_MAX * sizeof (iwk_tx_desc_t),
1350 1349 &ring_desc_dma_attr, &iwk_dma_descattr,
1351 1350 DDI_DMA_RDWR | DDI_DMA_CONSISTENT,
1352 1351 &ring->dma_desc);
1353 1352 if (err != DDI_SUCCESS) {
1354 1353 cmn_err(CE_WARN, "dma alloc tx ring desc[%d] "
1355 1354 "failed\n", qid);
1356 1355 goto fail;
1357 1356 }
1358 1357 dma_p = &ring->dma_desc;
1359 1358 IWK_DBG((IWK_DEBUG_DMA, "tx bd[ncookies:%d addr:%lx size:%lx]\n",
1360 1359 dma_p->ncookies, dma_p->cookie.dmac_address,
1361 1360 dma_p->cookie.dmac_size));
1362 1361
1363 1362 desc_h = (iwk_tx_desc_t *)ring->dma_desc.mem_va;
1364 1363 paddr_desc_h = ring->dma_desc.cookie.dmac_address;
1365 1364
1366 1365 err = iwk_alloc_dma_mem(sc,
1367 1366 TFD_QUEUE_SIZE_MAX * sizeof (iwk_cmd_t),
1368 1367 &cmd_dma_attr, &iwk_dma_accattr,
1369 1368 DDI_DMA_RDWR | DDI_DMA_CONSISTENT,
1370 1369 &ring->dma_cmd);
1371 1370 if (err != DDI_SUCCESS) {
1372 1371 cmn_err(CE_WARN, "dma alloc tx ring cmd[%d] "
1373 1372 "failed\n", qid);
1374 1373 goto fail;
1375 1374 }
1376 1375 dma_p = &ring->dma_cmd;
1377 1376 IWK_DBG((IWK_DEBUG_DMA, "tx cmd[ncookies:%d addr:%lx size:%lx]\n",
1378 1377 dma_p->ncookies, dma_p->cookie.dmac_address,
1379 1378 dma_p->cookie.dmac_size));
1380 1379
1381 1380 cmd_h = (iwk_cmd_t *)ring->dma_cmd.mem_va;
1382 1381 paddr_cmd_h = ring->dma_cmd.cookie.dmac_address;
1383 1382
1384 1383 /*
1385 1384 * Allocate Tx buffers.
1386 1385 */
1387 1386 ring->data = kmem_zalloc(sizeof (iwk_tx_data_t) * TFD_QUEUE_SIZE_MAX,
1388 1387 KM_NOSLEEP);
1389 1388 if (ring->data == NULL) {
1390 1389 cmn_err(CE_WARN, "could not allocate tx data slots\n");
1391 1390 goto fail;
1392 1391 }
1393 1392
1394 1393 for (i = 0; i < TFD_QUEUE_SIZE_MAX; i++) {
1395 1394 data = &ring->data[i];
1396 1395 err = iwk_alloc_dma_mem(sc, sc->sc_dmabuf_sz,
1397 1396 &tx_buffer_dma_attr, &iwk_dma_accattr,
1398 1397 DDI_DMA_WRITE | DDI_DMA_STREAMING,
1399 1398 &data->dma_data);
1400 1399 if (err != DDI_SUCCESS) {
1401 1400 cmn_err(CE_WARN, "dma alloc tx ring "
1402 1401 "buf[%d] failed\n", i);
1403 1402 goto fail;
1404 1403 }
1405 1404
1406 1405 data->desc = desc_h + i;
1407 1406 data->paddr_desc = paddr_desc_h +
1408 1407 _PTRDIFF(data->desc, desc_h);
1409 1408 data->cmd = cmd_h + i; /* (i % slots); */
1410 1409 /* ((i % slots) * sizeof (iwk_cmd_t)); */
1411 1410 data->paddr_cmd = paddr_cmd_h +
1412 1411 _PTRDIFF(data->cmd, cmd_h);
1413 1412 }
1414 1413 dma_p = &ring->data[0].dma_data;
1415 1414 IWK_DBG((IWK_DEBUG_DMA, "tx buffer[0][ncookies:%d addr:%lx "
1416 1415 "size:%lx]\n",
1417 1416 dma_p->ncookies, dma_p->cookie.dmac_address,
1418 1417 dma_p->cookie.dmac_size));
1419 1418
1420 1419 return (err);
1421 1420
1422 1421 fail:
1423 1422 if (ring->data)
1424 1423 kmem_free(ring->data,
1425 1424 sizeof (iwk_tx_data_t) * TFD_QUEUE_SIZE_MAX);
1426 1425 iwk_free_tx_ring(sc, ring);
1427 1426 return (err);
1428 1427 }
1429 1428
1430 1429 static void
1431 1430 iwk_reset_tx_ring(iwk_sc_t *sc, iwk_tx_ring_t *ring)
1432 1431 {
1433 1432 iwk_tx_data_t *data;
1434 1433 int i, n;
1435 1434
1436 1435 iwk_mac_access_enter(sc);
1437 1436
1438 1437 IWK_WRITE(sc, IWK_FH_TCSR_CHNL_TX_CONFIG_REG(ring->qid), 0);
1439 1438 for (n = 0; n < 200; n++) {
1440 1439 if (IWK_READ(sc, IWK_FH_TSSR_TX_STATUS_REG) &
1441 1440 IWK_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ring->qid))
1442 1441 break;
1443 1442 DELAY(10);
1444 1443 }
1445 1444 if (n == 200) {
1446 1445 IWK_DBG((IWK_DEBUG_DMA, "timeout reset tx ring %d\n",
1447 1446 ring->qid));
1448 1447 }
1449 1448 iwk_mac_access_exit(sc);
1450 1449
1451 1450 for (i = 0; i < ring->count; i++) {
1452 1451 data = &ring->data[i];
1453 1452 IWK_DMA_SYNC(data->dma_data, DDI_DMA_SYNC_FORDEV);
1454 1453 }
1455 1454
1456 1455 ring->queued = 0;
1457 1456 ring->cur = 0;
1458 1457 }
1459 1458
1460 1459 /*ARGSUSED*/
1461 1460 static void
1462 1461 iwk_free_tx_ring(iwk_sc_t *sc, iwk_tx_ring_t *ring)
1463 1462 {
1464 1463 int i;
1465 1464
1466 1465 if (ring->dma_desc.dma_hdl != NULL)
1467 1466 IWK_DMA_SYNC(ring->dma_desc, DDI_DMA_SYNC_FORDEV);
1468 1467 iwk_free_dma_mem(&ring->dma_desc);
1469 1468
1470 1469 if (ring->dma_cmd.dma_hdl != NULL)
1471 1470 IWK_DMA_SYNC(ring->dma_cmd, DDI_DMA_SYNC_FORDEV);
1472 1471 iwk_free_dma_mem(&ring->dma_cmd);
1473 1472
1474 1473 if (ring->data != NULL) {
1475 1474 for (i = 0; i < ring->count; i++) {
1476 1475 if (ring->data[i].dma_data.dma_hdl)
1477 1476 IWK_DMA_SYNC(ring->data[i].dma_data,
1478 1477 DDI_DMA_SYNC_FORDEV);
1479 1478 iwk_free_dma_mem(&ring->data[i].dma_data);
1480 1479 }
1481 1480 kmem_free(ring->data, ring->count * sizeof (iwk_tx_data_t));
1482 1481 }
1483 1482 }
1484 1483
1485 1484 static int
1486 1485 iwk_ring_init(iwk_sc_t *sc)
1487 1486 {
1488 1487 int i, err = DDI_SUCCESS;
1489 1488
1490 1489 for (i = 0; i < IWK_NUM_QUEUES; i++) {
1491 1490 if (i == IWK_CMD_QUEUE_NUM)
1492 1491 continue;
1493 1492 err = iwk_alloc_tx_ring(sc, &sc->sc_txq[i], TFD_TX_CMD_SLOTS,
1494 1493 i);
1495 1494 if (err != DDI_SUCCESS)
1496 1495 goto fail;
1497 1496 }
1498 1497 err = iwk_alloc_tx_ring(sc, &sc->sc_txq[IWK_CMD_QUEUE_NUM],
1499 1498 TFD_CMD_SLOTS, IWK_CMD_QUEUE_NUM);
1500 1499 if (err != DDI_SUCCESS)
1501 1500 goto fail;
1502 1501 err = iwk_alloc_rx_ring(sc);
1503 1502 if (err != DDI_SUCCESS)
1504 1503 goto fail;
1505 1504 return (err);
1506 1505
1507 1506 fail:
1508 1507 return (err);
1509 1508 }
1510 1509
1511 1510 static void
1512 1511 iwk_ring_free(iwk_sc_t *sc)
1513 1512 {
1514 1513 int i = IWK_NUM_QUEUES;
1515 1514
1516 1515 iwk_free_rx_ring(sc);
1517 1516 while (--i >= 0) {
1518 1517 iwk_free_tx_ring(sc, &sc->sc_txq[i]);
1519 1518 }
1520 1519 }
1521 1520
1522 1521 /* ARGSUSED */
1523 1522 static ieee80211_node_t *
1524 1523 iwk_node_alloc(ieee80211com_t *ic)
1525 1524 {
1526 1525 iwk_amrr_t *amrr;
1527 1526
1528 1527 amrr = kmem_zalloc(sizeof (iwk_amrr_t), KM_SLEEP);
1529 1528 if (amrr != NULL)
1530 1529 iwk_amrr_init(amrr);
1531 1530 return (&amrr->in);
1532 1531 }
1533 1532
1534 1533 static void
1535 1534 iwk_node_free(ieee80211_node_t *in)
1536 1535 {
1537 1536 ieee80211com_t *ic = in->in_ic;
1538 1537
1539 1538 ic->ic_node_cleanup(in);
1540 1539 if (in->in_wpa_ie != NULL)
1541 1540 ieee80211_free(in->in_wpa_ie);
1542 1541 kmem_free(in, sizeof (iwk_amrr_t));
1543 1542 }
1544 1543
1545 1544 /*ARGSUSED*/
1546 1545 static int
1547 1546 iwk_newstate(ieee80211com_t *ic, enum ieee80211_state nstate, int arg)
1548 1547 {
1549 1548 iwk_sc_t *sc = (iwk_sc_t *)ic;
1550 1549 ieee80211_node_t *in = ic->ic_bss;
1551 1550 enum ieee80211_state ostate = ic->ic_state;
1552 1551 int i, err = IWK_SUCCESS;
1553 1552
1554 1553 mutex_enter(&sc->sc_glock);
1555 1554 switch (nstate) {
1556 1555 case IEEE80211_S_SCAN:
1557 1556 switch (ostate) {
1558 1557 case IEEE80211_S_INIT:
1559 1558 {
1560 1559 iwk_add_sta_t node;
1561 1560
1562 1561 sc->sc_flags |= IWK_F_SCANNING;
1563 1562 sc->sc_scan_pending = 0;
1564 1563 iwk_set_led(sc, 2, 10, 2);
1565 1564
1566 1565 /*
1567 1566 * clear association to receive beacons from
1568 1567 * all BSS'es
1569 1568 */
1570 1569 sc->sc_config.assoc_id = 0;
1571 1570 sc->sc_config.filter_flags &=
1572 1571 ~LE_32(RXON_FILTER_ASSOC_MSK);
1573 1572
1574 1573 IWK_DBG((IWK_DEBUG_80211, "config chan %d "
1575 1574 "flags %x filter_flags %x\n", sc->sc_config.chan,
1576 1575 sc->sc_config.flags, sc->sc_config.filter_flags));
1577 1576
1578 1577 err = iwk_cmd(sc, REPLY_RXON, &sc->sc_config,
1579 1578 sizeof (iwk_rxon_cmd_t), 1);
1580 1579 if (err != IWK_SUCCESS) {
1581 1580 cmn_err(CE_WARN,
1582 1581 "could not clear association\n");
1583 1582 sc->sc_flags &= ~IWK_F_SCANNING;
1584 1583 mutex_exit(&sc->sc_glock);
1585 1584 return (err);
1586 1585 }
1587 1586
1588 1587 /* add broadcast node to send probe request */
1589 1588 (void) memset(&node, 0, sizeof (node));
1590 1589 (void) memset(&node.bssid, 0xff, IEEE80211_ADDR_LEN);
1591 1590 node.id = IWK_BROADCAST_ID;
1592 1591 err = iwk_cmd(sc, REPLY_ADD_STA, &node,
1593 1592 sizeof (node), 1);
1594 1593 if (err != IWK_SUCCESS) {
1595 1594 cmn_err(CE_WARN, "could not add "
1596 1595 "broadcast node\n");
1597 1596 sc->sc_flags &= ~IWK_F_SCANNING;
1598 1597 mutex_exit(&sc->sc_glock);
1599 1598 return (err);
1600 1599 }
1601 1600 break;
1602 1601 }
1603 1602
1604 1603 case IEEE80211_S_AUTH:
1605 1604 case IEEE80211_S_ASSOC:
1606 1605 case IEEE80211_S_RUN:
1607 1606 sc->sc_flags |= IWK_F_SCANNING;
1608 1607 sc->sc_scan_pending = 0;
1609 1608
1610 1609 iwk_set_led(sc, 2, 10, 2);
1611 1610 /* FALLTHRU */
1612 1611 case IEEE80211_S_SCAN:
1613 1612 mutex_exit(&sc->sc_glock);
1614 1613 /* step to next channel before actual FW scan */
1615 1614 err = sc->sc_newstate(ic, nstate, arg);
1616 1615 mutex_enter(&sc->sc_glock);
1617 1616 if ((err != 0) || ((err = iwk_scan(sc)) != 0)) {
1618 1617 cmn_err(CE_WARN,
1619 1618 "could not initiate scan\n");
1620 1619 sc->sc_flags &= ~IWK_F_SCANNING;
1621 1620 ieee80211_cancel_scan(ic);
1622 1621 }
1623 1622 mutex_exit(&sc->sc_glock);
1624 1623 return (err);
1625 1624 default:
1626 1625 break;
1627 1626
1628 1627 }
1629 1628 sc->sc_clk = 0;
1630 1629 break;
1631 1630
1632 1631 case IEEE80211_S_AUTH:
1633 1632 if (ostate == IEEE80211_S_SCAN) {
1634 1633 sc->sc_flags &= ~IWK_F_SCANNING;
1635 1634 }
1636 1635
1637 1636 /* reset state to handle reassociations correctly */
1638 1637 sc->sc_config.assoc_id = 0;
1639 1638 sc->sc_config.filter_flags &= ~LE_32(RXON_FILTER_ASSOC_MSK);
1640 1639
1641 1640 /*
1642 1641 * before sending authentication and association request frame,
1643 1642 * we need do something in the hardware, such as setting the
1644 1643 * channel same to the target AP...
1645 1644 */
1646 1645 if ((err = iwk_hw_set_before_auth(sc)) != 0) {
1647 1646 cmn_err(CE_WARN, "could not setup firmware for "
1648 1647 "authentication\n");
1649 1648 mutex_exit(&sc->sc_glock);
1650 1649 return (err);
1651 1650 }
1652 1651 break;
1653 1652
1654 1653 case IEEE80211_S_RUN:
1655 1654 if (ostate == IEEE80211_S_SCAN) {
1656 1655 sc->sc_flags &= ~IWK_F_SCANNING;
1657 1656 }
1658 1657
1659 1658 if (ic->ic_opmode == IEEE80211_M_MONITOR) {
1660 1659 /* let LED blink when monitoring */
1661 1660 iwk_set_led(sc, 2, 10, 10);
1662 1661 break;
1663 1662 }
1664 1663 IWK_DBG((IWK_DEBUG_80211, "iwk: associated."));
1665 1664
1666 1665 /* IBSS mode */
1667 1666 if (ic->ic_opmode == IEEE80211_M_IBSS) {
1668 1667 /*
1669 1668 * clean all nodes in ibss node table
1670 1669 * in order to be consistent with hardware
1671 1670 */
1672 1671 err = iwk_run_state_config_ibss(ic);
1673 1672 if (err != IWK_SUCCESS) {
1674 1673 cmn_err(CE_WARN, "iwk_newstate(): "
1675 1674 "failed to update configuration "
1676 1675 "in IBSS mode\n");
1677 1676 mutex_exit(&sc->sc_glock);
1678 1677 return (err);
1679 1678 }
1680 1679 }
1681 1680
1682 1681 /* none IBSS mode */
1683 1682 if (ic->ic_opmode != IEEE80211_M_IBSS) {
1684 1683 /* update adapter's configuration */
1685 1684 err = iwk_run_state_config_sta(ic);
1686 1685 if (err != IWK_SUCCESS) {
1687 1686 cmn_err(CE_WARN, "iwk_newstate(): "
1688 1687 "failed to update configuration "
1689 1688 "in none IBSS mode\n");
1690 1689 mutex_exit(&sc->sc_glock);
1691 1690 return (err);
1692 1691 }
1693 1692 }
1694 1693
1695 1694 /* obtain current temperature of chipset */
1696 1695 sc->sc_tempera = iwk_curr_tempera(sc);
1697 1696
1698 1697 /*
1699 1698 * make Tx power calibration to determine
1700 1699 * the gains of DSP and radio
1701 1700 */
1702 1701 err = iwk_tx_power_calibration(sc);
1703 1702 if (err) {
1704 1703 cmn_err(CE_WARN, "iwk_newstate(): "
1705 1704 "failed to set tx power table\n");
1706 1705 mutex_exit(&sc->sc_glock);
1707 1706 return (err);
1708 1707 }
1709 1708
1710 1709 if (ic->ic_opmode == IEEE80211_M_IBSS) {
1711 1710
1712 1711 /*
1713 1712 * allocate and transmit beacon frames
1714 1713 */
1715 1714 err = iwk_start_tx_beacon(ic);
1716 1715 if (err != IWK_SUCCESS) {
1717 1716 cmn_err(CE_WARN, "iwk_newstate(): "
1718 1717 "can't transmit beacon frames\n");
1719 1718 mutex_exit(&sc->sc_glock);
1720 1719 return (err);
1721 1720 }
1722 1721 }
1723 1722
1724 1723 /* start automatic rate control */
1725 1724 mutex_enter(&sc->sc_mt_lock);
1726 1725 if (ic->ic_fixed_rate == IEEE80211_FIXED_RATE_NONE) {
1727 1726 sc->sc_flags |= IWK_F_RATE_AUTO_CTL;
1728 1727 /* set rate to some reasonable initial value */
1729 1728 i = in->in_rates.ir_nrates - 1;
1730 1729 while (i > 0 && IEEE80211_RATE(i) > 72)
1731 1730 i--;
1732 1731 in->in_txrate = i;
1733 1732 } else {
1734 1733 sc->sc_flags &= ~IWK_F_RATE_AUTO_CTL;
1735 1734 }
1736 1735 mutex_exit(&sc->sc_mt_lock);
1737 1736
1738 1737 /* set LED on after associated */
1739 1738 iwk_set_led(sc, 2, 0, 1);
1740 1739 break;
1741 1740
1742 1741 case IEEE80211_S_INIT:
1743 1742 if (ostate == IEEE80211_S_SCAN) {
1744 1743 sc->sc_flags &= ~IWK_F_SCANNING;
1745 1744 }
1746 1745
1747 1746 /* set LED off after init */
1748 1747 iwk_set_led(sc, 2, 1, 0);
1749 1748 break;
1750 1749 case IEEE80211_S_ASSOC:
1751 1750 if (ostate == IEEE80211_S_SCAN) {
1752 1751 sc->sc_flags &= ~IWK_F_SCANNING;
1753 1752 }
1754 1753
1755 1754 break;
1756 1755 }
1757 1756
1758 1757 mutex_exit(&sc->sc_glock);
1759 1758
1760 1759 err = sc->sc_newstate(ic, nstate, arg);
1761 1760
1762 1761 if (nstate == IEEE80211_S_RUN) {
1763 1762
1764 1763 mutex_enter(&sc->sc_glock);
1765 1764
1766 1765 /*
1767 1766 * make initialization for Receiver
1768 1767 * sensitivity calibration
1769 1768 */
1770 1769 err = iwk_rx_sens_init(sc);
1771 1770 if (err) {
1772 1771 cmn_err(CE_WARN, "iwk_newstate(): "
1773 1772 "failed to init RX sensitivity\n");
1774 1773 mutex_exit(&sc->sc_glock);
1775 1774 return (err);
1776 1775 }
1777 1776
1778 1777 /* make initialization for Receiver gain balance */
1779 1778 err = iwk_rxgain_diff_init(sc);
1780 1779 if (err) {
1781 1780 cmn_err(CE_WARN, "iwk_newstate(): "
1782 1781 "failed to init phy calibration\n");
1783 1782 mutex_exit(&sc->sc_glock);
1784 1783 return (err);
1785 1784 }
1786 1785
1787 1786 mutex_exit(&sc->sc_glock);
1788 1787
1789 1788 }
1790 1789
1791 1790 return (err);
1792 1791 }
1793 1792
1794 1793 static void
1795 1794 iwk_watchdog(void *arg)
1796 1795 {
1797 1796 iwk_sc_t *sc = arg;
1798 1797 struct ieee80211com *ic = &sc->sc_ic;
1799 1798 #ifdef DEBUG
1800 1799 timeout_id_t timeout_id = ic->ic_watchdog_timer;
1801 1800 #endif
1802 1801
1803 1802 ieee80211_stop_watchdog(ic);
1804 1803
1805 1804 if ((ic->ic_state != IEEE80211_S_AUTH) &&
1806 1805 (ic->ic_state != IEEE80211_S_ASSOC))
1807 1806 return;
1808 1807
1809 1808 if (ic->ic_bss->in_fails > 0) {
1810 1809 IWK_DBG((IWK_DEBUG_80211, "watchdog (0x%x) reset: "
1811 1810 "node (0x%x)\n", timeout_id, &ic->ic_bss));
1812 1811 ieee80211_new_state(ic, IEEE80211_S_INIT, -1);
1813 1812 } else {
1814 1813 IWK_DBG((IWK_DEBUG_80211, "watchdog (0x%x) timeout: "
1815 1814 "node (0x%x), retry (%d)\n",
1816 1815 timeout_id, &ic->ic_bss, ic->ic_bss->in_fails + 1));
1817 1816 ieee80211_watchdog(ic);
1818 1817 }
1819 1818 }
1820 1819
1821 1820 /*ARGSUSED*/
1822 1821 static int iwk_key_set(ieee80211com_t *ic, const struct ieee80211_key *k,
1823 1822 const uint8_t mac[IEEE80211_ADDR_LEN])
1824 1823 {
1825 1824 iwk_sc_t *sc = (iwk_sc_t *)ic;
1826 1825 iwk_add_sta_t node;
1827 1826 int err;
1828 1827 uint8_t index1;
1829 1828
1830 1829 switch (k->wk_cipher->ic_cipher) {
1831 1830 case IEEE80211_CIPHER_WEP:
1832 1831 case IEEE80211_CIPHER_TKIP:
1833 1832 return (1); /* sofeware do it. */
1834 1833 case IEEE80211_CIPHER_AES_CCM:
1835 1834 break;
1836 1835 default:
1837 1836 return (0);
1838 1837 }
1839 1838 sc->sc_config.filter_flags &= ~LE_32(RXON_FILTER_DIS_DECRYPT_MSK |
1840 1839 RXON_FILTER_DIS_GRP_DECRYPT_MSK);
1841 1840
1842 1841 mutex_enter(&sc->sc_glock);
1843 1842
1844 1843 /* update ap/multicast node */
1845 1844 (void) memset(&node, 0, sizeof (node));
1846 1845 if (IEEE80211_IS_MULTICAST(mac)) {
1847 1846 (void) memset(node.bssid, 0xff, 6);
1848 1847 node.id = IWK_BROADCAST_ID;
1849 1848 } else if (ic->ic_opmode == IEEE80211_M_IBSS) {
1850 1849 mutex_exit(&sc->sc_glock);
1851 1850 mutex_enter(&sc->sc_ibss.node_tb_lock);
1852 1851
1853 1852 /*
1854 1853 * search for node in ibss node table
1855 1854 */
1856 1855 for (index1 = IWK_STA_ID; index1 < IWK_STATION_COUNT;
1857 1856 index1++) {
1858 1857 if (sc->sc_ibss.ibss_node_tb[index1].used &&
1859 1858 IEEE80211_ADDR_EQ(sc->sc_ibss.
1860 1859 ibss_node_tb[index1].node.bssid,
1861 1860 mac)) {
1862 1861 break;
1863 1862 }
1864 1863 }
1865 1864 if (index1 >= IWK_BROADCAST_ID) {
1866 1865 cmn_err(CE_WARN, "iwk_key_set(): "
1867 1866 "have no this node in hardware node table\n");
1868 1867 mutex_exit(&sc->sc_ibss.node_tb_lock);
1869 1868 return (0);
1870 1869 } else {
1871 1870 /*
1872 1871 * configure key for given node in hardware
1873 1872 */
1874 1873 if (k->wk_flags & IEEE80211_KEY_XMIT) {
1875 1874 sc->sc_ibss.ibss_node_tb[index1].
1876 1875 node.key_flags = 0;
1877 1876 sc->sc_ibss.ibss_node_tb[index1].
1878 1877 node.keyp = k->wk_keyix;
1879 1878 } else {
1880 1879 sc->sc_ibss.ibss_node_tb[index1].
1881 1880 node.key_flags = (1 << 14);
1882 1881 sc->sc_ibss.ibss_node_tb[index1].
1883 1882 node.keyp = k->wk_keyix + 4;
1884 1883 }
1885 1884
1886 1885 (void) memcpy(sc->sc_ibss.ibss_node_tb[index1].node.key,
1887 1886 k->wk_key, k->wk_keylen);
1888 1887 sc->sc_ibss.ibss_node_tb[index1].node.key_flags |=
1889 1888 (STA_KEY_FLG_CCMP | (1 << 3) | (k->wk_keyix << 8));
1890 1889 sc->sc_ibss.ibss_node_tb[index1].node.key_flags =
1891 1890 LE_16(sc->sc_ibss.ibss_node_tb[index1].
1892 1891 node.key_flags);
1893 1892 sc->sc_ibss.ibss_node_tb[index1].node.sta_mask =
1894 1893 STA_MODIFY_KEY_MASK;
1895 1894 sc->sc_ibss.ibss_node_tb[index1].node.control = 1;
1896 1895
1897 1896 mutex_enter(&sc->sc_glock);
1898 1897 err = iwk_cmd(sc, REPLY_ADD_STA,
1899 1898 &sc->sc_ibss.ibss_node_tb[index1].node,
1900 1899 sizeof (iwk_add_sta_t), 1);
1901 1900 if (err != IWK_SUCCESS) {
1902 1901 cmn_err(CE_WARN, "iwk_key_set(): "
1903 1902 "failed to update IBSS node in hardware\n");
1904 1903 mutex_exit(&sc->sc_glock);
1905 1904 mutex_exit(&sc->sc_ibss.node_tb_lock);
1906 1905 return (0);
1907 1906 }
1908 1907 mutex_exit(&sc->sc_glock);
1909 1908 }
1910 1909 mutex_exit(&sc->sc_ibss.node_tb_lock);
1911 1910 return (1);
1912 1911 } else {
1913 1912 IEEE80211_ADDR_COPY(node.bssid, ic->ic_bss->in_bssid);
1914 1913 node.id = IWK_AP_ID;
1915 1914 }
1916 1915 if (k->wk_flags & IEEE80211_KEY_XMIT) {
1917 1916 node.key_flags = 0;
1918 1917 node.keyp = k->wk_keyix;
1919 1918 } else {
1920 1919 node.key_flags = (1 << 14);
1921 1920 node.keyp = k->wk_keyix + 4;
1922 1921 }
1923 1922 (void) memcpy(node.key, k->wk_key, k->wk_keylen);
1924 1923 node.key_flags |= (STA_KEY_FLG_CCMP | (1 << 3) | (k->wk_keyix << 8));
1925 1924 node.key_flags = LE_16(node.key_flags);
1926 1925 node.sta_mask = STA_MODIFY_KEY_MASK;
1927 1926 node.control = 1;
1928 1927 err = iwk_cmd(sc, REPLY_ADD_STA, &node, sizeof (node), 1);
1929 1928 if (err != IWK_SUCCESS) {
1930 1929 cmn_err(CE_WARN, "iwk_key_set():"
1931 1930 "failed to update ap node\n");
1932 1931 mutex_exit(&sc->sc_glock);
1933 1932 return (0);
1934 1933 }
1935 1934 mutex_exit(&sc->sc_glock);
1936 1935 return (1);
1937 1936 }
1938 1937
1939 1938 /*
1940 1939 * exclusive access to mac begin.
1941 1940 */
1942 1941 static void
1943 1942 iwk_mac_access_enter(iwk_sc_t *sc)
1944 1943 {
1945 1944 uint32_t tmp;
1946 1945 int n;
1947 1946
1948 1947 tmp = IWK_READ(sc, CSR_GP_CNTRL);
1949 1948 IWK_WRITE(sc, CSR_GP_CNTRL,
1950 1949 tmp | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1951 1950
1952 1951 /* wait until we succeed */
1953 1952 for (n = 0; n < 1000; n++) {
1954 1953 if ((IWK_READ(sc, CSR_GP_CNTRL) &
1955 1954 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
1956 1955 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP)) ==
1957 1956 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN)
1958 1957 break;
1959 1958 DELAY(10);
1960 1959 }
1961 1960 if (n == 1000)
1962 1961 IWK_DBG((IWK_DEBUG_PIO, "could not lock memory\n"));
1963 1962 }
1964 1963
1965 1964 /*
1966 1965 * exclusive access to mac end.
1967 1966 */
1968 1967 static void
1969 1968 iwk_mac_access_exit(iwk_sc_t *sc)
1970 1969 {
1971 1970 uint32_t tmp = IWK_READ(sc, CSR_GP_CNTRL);
1972 1971 IWK_WRITE(sc, CSR_GP_CNTRL,
1973 1972 tmp & ~CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1974 1973 }
1975 1974
1976 1975 static uint32_t
1977 1976 iwk_mem_read(iwk_sc_t *sc, uint32_t addr)
1978 1977 {
1979 1978 IWK_WRITE(sc, HBUS_TARG_MEM_RADDR, addr);
1980 1979 return (IWK_READ(sc, HBUS_TARG_MEM_RDAT));
1981 1980 }
1982 1981
1983 1982 static void
1984 1983 iwk_mem_write(iwk_sc_t *sc, uint32_t addr, uint32_t data)
1985 1984 {
1986 1985 IWK_WRITE(sc, HBUS_TARG_MEM_WADDR, addr);
1987 1986 IWK_WRITE(sc, HBUS_TARG_MEM_WDAT, data);
1988 1987 }
1989 1988
1990 1989 static uint32_t
1991 1990 iwk_reg_read(iwk_sc_t *sc, uint32_t addr)
1992 1991 {
1993 1992 IWK_WRITE(sc, HBUS_TARG_PRPH_RADDR, addr | (3 << 24));
1994 1993 return (IWK_READ(sc, HBUS_TARG_PRPH_RDAT));
1995 1994 }
1996 1995
1997 1996 static void
1998 1997 iwk_reg_write(iwk_sc_t *sc, uint32_t addr, uint32_t data)
1999 1998 {
2000 1999 IWK_WRITE(sc, HBUS_TARG_PRPH_WADDR, addr | (3 << 24));
2001 2000 IWK_WRITE(sc, HBUS_TARG_PRPH_WDAT, data);
2002 2001 }
2003 2002
2004 2003 static void
2005 2004 iwk_reg_write_region_4(iwk_sc_t *sc, uint32_t addr,
2006 2005 uint32_t *data, int wlen)
2007 2006 {
2008 2007 for (; wlen > 0; wlen--, data++, addr += 4)
2009 2008 iwk_reg_write(sc, addr, LE_32(*data));
2010 2009 }
2011 2010
2012 2011
2013 2012 /*
2014 2013 * ucode load/initialization steps:
2015 2014 * 1) load Bootstrap State Machine (BSM) with "bootstrap" uCode image.
2016 2015 * BSM contains a small memory that *always* stays powered up, so it can
2017 2016 * retain the bootstrap program even when the card is in a power-saving
2018 2017 * power-down state. The BSM loads the small program into ARC processor's
2019 2018 * instruction memory when triggered by power-up.
2020 2019 * 2) load Initialize image via bootstrap program.
2021 2020 * The Initialize image sets up regulatory and calibration data for the
2022 2021 * Runtime/Protocol uCode. This sends a REPLY_ALIVE notification when completed.
2023 2022 * The 4965 reply contains calibration data for temperature, voltage and tx gain
2024 2023 * correction.
2025 2024 */
2026 2025 static int
2027 2026 iwk_load_firmware(iwk_sc_t *sc)
2028 2027 {
2029 2028 uint32_t *boot_fw = (uint32_t *)sc->sc_boot;
2030 2029 uint32_t size = LE_32(sc->sc_hdr->bootsz);
2031 2030 int n, err = IWK_SUCCESS;
2032 2031
2033 2032 /*
2034 2033 * The physical address bit [4-35] of the initialize uCode.
2035 2034 * In the initialize alive notify interrupt the physical address of
2036 2035 * the runtime ucode will be set for loading.
2037 2036 */
2038 2037 iwk_mac_access_enter(sc);
2039 2038
2040 2039 iwk_reg_write(sc, BSM_DRAM_INST_PTR_REG,
2041 2040 sc->sc_dma_fw_init_text.cookie.dmac_address >> 4);
2042 2041 iwk_reg_write(sc, BSM_DRAM_DATA_PTR_REG,
2043 2042 sc->sc_dma_fw_init_data.cookie.dmac_address >> 4);
2044 2043 iwk_reg_write(sc, BSM_DRAM_INST_BYTECOUNT_REG,
2045 2044 sc->sc_dma_fw_init_text.cookie.dmac_size);
2046 2045 iwk_reg_write(sc, BSM_DRAM_DATA_BYTECOUNT_REG,
2047 2046 sc->sc_dma_fw_init_data.cookie.dmac_size);
2048 2047
2049 2048 /* load bootstrap code into BSM memory */
2050 2049 iwk_reg_write_region_4(sc, BSM_SRAM_LOWER_BOUND, boot_fw,
2051 2050 size / sizeof (uint32_t));
2052 2051
2053 2052 iwk_reg_write(sc, BSM_WR_MEM_SRC_REG, 0);
2054 2053 iwk_reg_write(sc, BSM_WR_MEM_DST_REG, RTC_INST_LOWER_BOUND);
2055 2054 iwk_reg_write(sc, BSM_WR_DWCOUNT_REG, size / sizeof (uint32_t));
2056 2055
2057 2056 /*
2058 2057 * prepare to load initialize uCode
2059 2058 */
2060 2059 iwk_reg_write(sc, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START);
2061 2060
2062 2061 /* wait while the adapter is busy loading the firmware */
2063 2062 for (n = 0; n < 1000; n++) {
2064 2063 if (!(iwk_reg_read(sc, BSM_WR_CTRL_REG) &
2065 2064 BSM_WR_CTRL_REG_BIT_START))
2066 2065 break;
2067 2066 DELAY(10);
2068 2067 }
2069 2068 if (n == 1000) {
2070 2069 cmn_err(CE_WARN, "timeout transferring firmware\n");
2071 2070 err = ETIMEDOUT;
2072 2071 return (err);
2073 2072 }
2074 2073
2075 2074 /* for future power-save mode use */
2076 2075 iwk_reg_write(sc, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START_EN);
2077 2076
2078 2077 iwk_mac_access_exit(sc);
2079 2078
2080 2079 return (err);
2081 2080 }
2082 2081
2083 2082 /*ARGSUSED*/
2084 2083 static void
2085 2084 iwk_rx_intr(iwk_sc_t *sc, iwk_rx_desc_t *desc, iwk_rx_data_t *data)
2086 2085 {
2087 2086 ieee80211com_t *ic = &sc->sc_ic;
2088 2087 iwk_rx_ring_t *ring = &sc->sc_rxq;
2089 2088 iwk_rx_phy_res_t *stat;
2090 2089 ieee80211_node_t *in;
2091 2090 uint32_t *tail;
2092 2091 struct ieee80211_frame *wh;
2093 2092 mblk_t *mp;
2094 2093 uint16_t len, rssi, mrssi, agc;
2095 2094 int16_t t;
2096 2095 uint32_t ants, i;
2097 2096 struct iwk_rx_non_cfg_phy *phyinfo;
2098 2097 uint32_t crc;
2099 2098
2100 2099 /* assuming not 11n here. cope with 11n in phase-II */
2101 2100 stat = (iwk_rx_phy_res_t *)(desc + 1);
2102 2101 if (stat->cfg_phy_cnt > 20) {
2103 2102 return;
2104 2103 }
2105 2104
2106 2105 for (i = 0; i < RX_RES_PHY_CNT; i++)
2107 2106 stat->non_cfg_phy[i] = LE_16(stat->non_cfg_phy[i]);
2108 2107
2109 2108 phyinfo = (struct iwk_rx_non_cfg_phy *)stat->non_cfg_phy;
2110 2109 agc = (phyinfo->agc_info & IWK_AGC_DB_MASK) >> IWK_AGC_DB_POS;
2111 2110 mrssi = 0;
2112 2111 ants = (LE_16(stat->phy_flags) & RX_PHY_FLAGS_ANTENNAE_MASK) >>
2113 2112 RX_PHY_FLAGS_ANTENNAE_OFFSET;
2114 2113 for (i = 0; i < 3; i++) {
2115 2114 if (ants & (1 << i))
2116 2115 mrssi = MAX(mrssi, phyinfo->rssi_info[i << 1]);
2117 2116 }
2118 2117 t = mrssi - agc - 44; /* t is the dBM value */
2119 2118 /*
2120 2119 * convert dBm to percentage ???
2121 2120 */
2122 2121 rssi = (100 * 75 * 75 - (-20 - t) * (15 * 75 + 62 * (-20 - t))) /
2123 2122 (75 * 75);
2124 2123 if (rssi > 100)
2125 2124 rssi = 100;
2126 2125 if (rssi < 1)
2127 2126 rssi = 1;
2128 2127 len = LE_16(stat->byte_count);
2129 2128 tail = (uint32_t *)((caddr_t)(stat + 1) + stat->cfg_phy_cnt + len);
2130 2129 bcopy(tail, &crc, 4);
2131 2130
2132 2131 IWK_DBG((IWK_DEBUG_RX, "rx intr: idx=%d phy_len=%x len=%d "
2133 2132 "rate=%x chan=%d tstamp=%x non_cfg_phy_count=%x "
2134 2133 "cfg_phy_count=%x tail=%x", ring->cur, sizeof (*stat),
2135 2134 len, stat->rate.r.s.rate, LE_16(stat->channel),
2136 2135 LE_32(stat->timestampl), stat->non_cfg_phy_cnt,
2137 2136 stat->cfg_phy_cnt, LE_32(crc)));
2138 2137
2139 2138 if ((len < 16) || (len > sc->sc_dmabuf_sz)) {
2140 2139 IWK_DBG((IWK_DEBUG_RX, "rx frame oversize\n"));
2141 2140 return;
2142 2141 }
2143 2142
2144 2143 /*
2145 2144 * discard Rx frames with bad CRC
2146 2145 */
2147 2146 if ((LE_32(crc) &
2148 2147 (RX_RES_STATUS_NO_CRC32_ERROR | RX_RES_STATUS_NO_RXE_OVERFLOW)) !=
2149 2148 (RX_RES_STATUS_NO_CRC32_ERROR | RX_RES_STATUS_NO_RXE_OVERFLOW)) {
2150 2149 IWK_DBG((IWK_DEBUG_RX, "rx crc error tail: %x\n",
2151 2150 LE_32(crc)));
2152 2151 sc->sc_rx_err++;
2153 2152 return;
2154 2153 }
2155 2154
2156 2155 wh = (struct ieee80211_frame *)
2157 2156 ((uint8_t *)(stat + 1)+ stat->cfg_phy_cnt);
2158 2157 if (*(uint8_t *)wh == IEEE80211_FC0_SUBTYPE_ASSOC_RESP) {
2159 2158 sc->sc_assoc_id = *((uint16_t *)(wh + 1) + 2);
2160 2159 IWK_DBG((IWK_DEBUG_RX, "rx : association id = %x\n",
2161 2160 sc->sc_assoc_id));
2162 2161 }
2163 2162 #ifdef DEBUG
2164 2163 if (iwk_dbg_flags & IWK_DEBUG_RX)
2165 2164 ieee80211_dump_pkt((uint8_t *)wh, len, 0, 0);
2166 2165 #endif
2167 2166 in = ieee80211_find_rxnode(ic, wh);
2168 2167 mp = allocb(len, BPRI_MED);
2169 2168 if (mp) {
2170 2169 (void) memcpy(mp->b_wptr, wh, len);
2171 2170 mp->b_wptr += len;
2172 2171
2173 2172 /* send the frame to the 802.11 layer */
2174 2173 (void) ieee80211_input(ic, mp, in, rssi, 0);
2175 2174 } else {
2176 2175 sc->sc_rx_nobuf++;
2177 2176 IWK_DBG((IWK_DEBUG_RX,
2178 2177 "iwk_rx_intr(): alloc rx buf failed\n"));
2179 2178 }
2180 2179 /* release node reference */
2181 2180 ieee80211_free_node(in);
2182 2181 }
2183 2182
2184 2183 /*ARGSUSED*/
2185 2184 static void
2186 2185 iwk_tx_intr(iwk_sc_t *sc, iwk_rx_desc_t *desc, iwk_rx_data_t *data)
2187 2186 {
2188 2187 ieee80211com_t *ic = &sc->sc_ic;
2189 2188 iwk_tx_ring_t *ring = &sc->sc_txq[desc->hdr.qid & 0x3];
2190 2189 iwk_tx_stat_t *stat = (iwk_tx_stat_t *)(desc + 1);
2191 2190 iwk_amrr_t *amrr = (iwk_amrr_t *)ic->ic_bss;
2192 2191
2193 2192 IWK_DBG((IWK_DEBUG_TX, "tx done: qid=%d idx=%d"
2194 2193 " retries=%d frame_count=%x nkill=%d "
2195 2194 "rate=%x duration=%d status=%x\n",
2196 2195 desc->hdr.qid, desc->hdr.idx, stat->ntries, stat->frame_count,
2197 2196 stat->bt_kill_count, stat->rate.r.s.rate,
2198 2197 LE_16(stat->duration), LE_32(stat->status)));
2199 2198
2200 2199 amrr->txcnt++;
2201 2200 IWK_DBG((IWK_DEBUG_RATECTL, "tx: %d cnt\n", amrr->txcnt));
2202 2201 if (stat->ntries > 0) {
2203 2202 amrr->retrycnt++;
2204 2203 sc->sc_tx_retries++;
2205 2204 IWK_DBG((IWK_DEBUG_TX, "tx: %d retries\n",
2206 2205 sc->sc_tx_retries));
2207 2206 }
2208 2207
2209 2208 sc->sc_tx_timer = 0;
2210 2209
2211 2210 mutex_enter(&sc->sc_tx_lock);
2212 2211 ring->queued--;
2213 2212 if (ring->queued < 0)
2214 2213 ring->queued = 0;
2215 2214 if ((sc->sc_need_reschedule) && (ring->queued <= (ring->count << 3))) {
2216 2215 sc->sc_need_reschedule = 0;
2217 2216 mutex_exit(&sc->sc_tx_lock);
2218 2217 mac_tx_update(ic->ic_mach);
2219 2218 mutex_enter(&sc->sc_tx_lock);
2220 2219 }
2221 2220 mutex_exit(&sc->sc_tx_lock);
2222 2221 }
2223 2222
2224 2223 static void
2225 2224 iwk_cmd_intr(iwk_sc_t *sc, iwk_rx_desc_t *desc)
2226 2225 {
2227 2226 if ((desc->hdr.qid & 7) != 4) {
2228 2227 return;
2229 2228 }
2230 2229 mutex_enter(&sc->sc_glock);
2231 2230 sc->sc_flags |= IWK_F_CMD_DONE;
2232 2231 cv_signal(&sc->sc_cmd_cv);
2233 2232 mutex_exit(&sc->sc_glock);
2234 2233 IWK_DBG((IWK_DEBUG_CMD, "rx cmd: "
2235 2234 "qid=%x idx=%d flags=%x type=0x%x\n",
2236 2235 desc->hdr.qid, desc->hdr.idx, desc->hdr.flags,
2237 2236 desc->hdr.type));
2238 2237 }
2239 2238
2240 2239 static void
2241 2240 iwk_ucode_alive(iwk_sc_t *sc, iwk_rx_desc_t *desc)
2242 2241 {
2243 2242 uint32_t base, i;
2244 2243 struct iwk_alive_resp *ar =
2245 2244 (struct iwk_alive_resp *)(desc + 1);
2246 2245
2247 2246 /* the microcontroller is ready */
2248 2247 IWK_DBG((IWK_DEBUG_FW,
2249 2248 "microcode alive notification minor: %x major: %x type:"
2250 2249 " %x subtype: %x\n",
2251 2250 ar->ucode_minor, ar->ucode_minor, ar->ver_type, ar->ver_subtype));
2252 2251
2253 2252 if (LE_32(ar->is_valid) != UCODE_VALID_OK) {
2254 2253 IWK_DBG((IWK_DEBUG_FW,
2255 2254 "microcontroller initialization failed\n"));
2256 2255 }
2257 2256 if (ar->ver_subtype == INITIALIZE_SUBTYPE) {
2258 2257 IWK_DBG((IWK_DEBUG_FW,
2259 2258 "initialization alive received.\n"));
2260 2259 (void) memcpy(&sc->sc_card_alive_init, ar,
2261 2260 sizeof (struct iwk_init_alive_resp));
2262 2261 /* XXX get temperature */
2263 2262 iwk_mac_access_enter(sc);
2264 2263 iwk_reg_write(sc, BSM_DRAM_INST_PTR_REG,
2265 2264 sc->sc_dma_fw_text.cookie.dmac_address >> 4);
2266 2265 iwk_reg_write(sc, BSM_DRAM_DATA_PTR_REG,
2267 2266 sc->sc_dma_fw_data_bak.cookie.dmac_address >> 4);
2268 2267 iwk_reg_write(sc, BSM_DRAM_DATA_BYTECOUNT_REG,
2269 2268 sc->sc_dma_fw_data.cookie.dmac_size);
2270 2269 iwk_reg_write(sc, BSM_DRAM_INST_BYTECOUNT_REG,
2271 2270 sc->sc_dma_fw_text.cookie.dmac_size | 0x80000000);
2272 2271 iwk_mac_access_exit(sc);
2273 2272 } else {
2274 2273 IWK_DBG((IWK_DEBUG_FW, "runtime alive received.\n"));
2275 2274 (void) memcpy(&sc->sc_card_alive_run, ar,
2276 2275 sizeof (struct iwk_alive_resp));
2277 2276
2278 2277 /*
2279 2278 * Init SCD related registers to make Tx work. XXX
2280 2279 */
2281 2280 iwk_mac_access_enter(sc);
2282 2281
2283 2282 /* read sram address of data base */
2284 2283 sc->sc_scd_base = iwk_reg_read(sc, SCD_SRAM_BASE_ADDR);
2285 2284
2286 2285 /* clear and init SCD_CONTEXT_DATA_OFFSET area. 128 bytes */
2287 2286 for (base = sc->sc_scd_base + SCD_CONTEXT_DATA_OFFSET, i = 0;
2288 2287 i < 128; i += 4)
2289 2288 iwk_mem_write(sc, base + i, 0);
2290 2289
2291 2290 /* clear and init SCD_TX_STTS_BITMAP_OFFSET area. 256 bytes */
2292 2291 for (base = sc->sc_scd_base + SCD_TX_STTS_BITMAP_OFFSET;
2293 2292 i < 256; i += 4)
2294 2293 iwk_mem_write(sc, base + i, 0);
2295 2294
2296 2295 /* clear and init SCD_TRANSLATE_TBL_OFFSET area. 32 bytes */
2297 2296 for (base = sc->sc_scd_base + SCD_TRANSLATE_TBL_OFFSET;
2298 2297 i < sizeof (uint16_t) * IWK_NUM_QUEUES; i += 4)
2299 2298 iwk_mem_write(sc, base + i, 0);
2300 2299
2301 2300 iwk_reg_write(sc, SCD_DRAM_BASE_ADDR,
2302 2301 sc->sc_dma_sh.cookie.dmac_address >> 10);
2303 2302 iwk_reg_write(sc, SCD_QUEUECHAIN_SEL, 0);
2304 2303
2305 2304 /* initiate the tx queues */
2306 2305 for (i = 0; i < IWK_NUM_QUEUES; i++) {
2307 2306 iwk_reg_write(sc, SCD_QUEUE_RDPTR(i), 0);
2308 2307 IWK_WRITE(sc, HBUS_TARG_WRPTR, (i << 8));
2309 2308 iwk_mem_write(sc, sc->sc_scd_base +
2310 2309 SCD_CONTEXT_QUEUE_OFFSET(i),
2311 2310 (SCD_WIN_SIZE & 0x7f));
2312 2311 iwk_mem_write(sc, sc->sc_scd_base +
2313 2312 SCD_CONTEXT_QUEUE_OFFSET(i) + sizeof (uint32_t),
2314 2313 (SCD_FRAME_LIMIT & 0x7f) << 16);
2315 2314 }
2316 2315 /* interrupt enable on each queue0-7 */
2317 2316 iwk_reg_write(sc, SCD_INTERRUPT_MASK,
2318 2317 (1 << IWK_NUM_QUEUES) - 1);
2319 2318 /* enable each channel 0-7 */
2320 2319 iwk_reg_write(sc, SCD_TXFACT,
2321 2320 SCD_TXFACT_REG_TXFIFO_MASK(0, 7));
2322 2321 /*
2323 2322 * queue 0-7 maps to FIFO 0-7 and
2324 2323 * all queues work under FIFO mode (none-scheduler-ack)
2325 2324 */
2326 2325 for (i = 0; i < 7; i++) {
2327 2326 iwk_reg_write(sc,
2328 2327 SCD_QUEUE_STATUS_BITS(i),
2329 2328 (1 << SCD_QUEUE_STTS_REG_POS_ACTIVE)|
2330 2329 (i << SCD_QUEUE_STTS_REG_POS_TXF)|
2331 2330 SCD_QUEUE_STTS_REG_MSK);
2332 2331 }
2333 2332 iwk_mac_access_exit(sc);
2334 2333
2335 2334 sc->sc_flags |= IWK_F_FW_INIT;
2336 2335 cv_signal(&sc->sc_fw_cv);
2337 2336 }
2338 2337
2339 2338 }
2340 2339
2341 2340 static uint_t
2342 2341 /* LINTED: argument unused in function: unused */
2343 2342 iwk_rx_softintr(caddr_t arg, caddr_t unused)
2344 2343 {
2345 2344 iwk_sc_t *sc = (iwk_sc_t *)arg;
2346 2345 ieee80211com_t *ic = &sc->sc_ic;
2347 2346 iwk_rx_desc_t *desc;
2348 2347 iwk_rx_data_t *data;
2349 2348 uint32_t index;
2350 2349
2351 2350 mutex_enter(&sc->sc_glock);
2352 2351 if (sc->sc_rx_softint_pending != 1) {
2353 2352 mutex_exit(&sc->sc_glock);
2354 2353 return (DDI_INTR_UNCLAIMED);
2355 2354 }
2356 2355 /* disable interrupts */
2357 2356 IWK_WRITE(sc, CSR_INT_MASK, 0);
2358 2357 mutex_exit(&sc->sc_glock);
2359 2358
2360 2359 /*
2361 2360 * firmware has moved the index of the rx queue, driver get it,
2362 2361 * and deal with it.
2363 2362 */
2364 2363 index = sc->sc_shared->val0 & 0xfff;
2365 2364
2366 2365 while (sc->sc_rxq.cur != index) {
2367 2366 data = &sc->sc_rxq.data[sc->sc_rxq.cur];
2368 2367 desc = (iwk_rx_desc_t *)data->dma_data.mem_va;
2369 2368
2370 2369 IWK_DBG((IWK_DEBUG_INTR, "rx notification index = %d"
2371 2370 " cur = %d qid=%x idx=%d flags=%x type=%x len=%d\n",
2372 2371 index, sc->sc_rxq.cur, desc->hdr.qid, desc->hdr.idx,
2373 2372 desc->hdr.flags, desc->hdr.type, LE_32(desc->len)));
2374 2373
2375 2374 /* a command other than a tx need to be replied */
2376 2375 if (!(desc->hdr.qid & 0x80) &&
2377 2376 (desc->hdr.type != REPLY_RX_PHY_CMD) &&
2378 2377 (desc->hdr.type != REPLY_TX) &&
2379 2378 (desc->hdr.type != REPLY_TX_PWR_TABLE_CMD) &&
2380 2379 (desc->hdr.type != REPLY_PHY_CALIBRATION_CMD) &&
2381 2380 (desc->hdr.type != SENSITIVITY_CMD))
2382 2381 iwk_cmd_intr(sc, desc);
2383 2382
2384 2383 switch (desc->hdr.type) {
2385 2384 case REPLY_4965_RX:
2386 2385 iwk_rx_intr(sc, desc, data);
2387 2386 break;
2388 2387
2389 2388 case REPLY_TX:
2390 2389 iwk_tx_intr(sc, desc, data);
2391 2390 break;
2392 2391
2393 2392 case REPLY_ALIVE:
2394 2393 iwk_ucode_alive(sc, desc);
2395 2394 break;
2396 2395
2397 2396 case CARD_STATE_NOTIFICATION:
2398 2397 {
2399 2398 uint32_t *status = (uint32_t *)(desc + 1);
2400 2399
2401 2400 IWK_DBG((IWK_DEBUG_RADIO, "state changed to %x\n",
2402 2401 LE_32(*status)));
2403 2402
2404 2403 if (LE_32(*status) & 1) {
2405 2404 /*
2406 2405 * the radio button has to be pushed(OFF). It
2407 2406 * is considered as a hw error, the
2408 2407 * iwk_thread() tries to recover it after the
2409 2408 * button is pushed again(ON)
2410 2409 */
2411 2410 cmn_err(CE_NOTE,
2412 2411 "iwk_rx_softintr(): "
2413 2412 "Radio transmitter is off\n");
2414 2413 sc->sc_ostate = sc->sc_ic.ic_state;
2415 2414 ieee80211_new_state(&sc->sc_ic,
2416 2415 IEEE80211_S_INIT, -1);
2417 2416 sc->sc_flags |=
2418 2417 (IWK_F_HW_ERR_RECOVER | IWK_F_RADIO_OFF);
2419 2418 }
2420 2419 break;
2421 2420 }
2422 2421 case SCAN_START_NOTIFICATION:
2423 2422 {
2424 2423 iwk_start_scan_t *scan =
2425 2424 (iwk_start_scan_t *)(desc + 1);
2426 2425
2427 2426 IWK_DBG((IWK_DEBUG_SCAN,
2428 2427 "scanning channel %d status %x\n",
2429 2428 scan->chan, LE_32(scan->status)));
2430 2429
2431 2430 ic->ic_curchan = &ic->ic_sup_channels[scan->chan];
2432 2431 break;
2433 2432 }
2434 2433 case SCAN_COMPLETE_NOTIFICATION:
2435 2434 {
2436 2435 iwk_stop_scan_t *scan =
2437 2436 (iwk_stop_scan_t *)(desc + 1);
2438 2437
2439 2438 IWK_DBG((IWK_DEBUG_SCAN,
2440 2439 "completed channel %d (burst of %d) status %02x\n",
2441 2440 scan->chan, scan->nchan, scan->status));
2442 2441
2443 2442 sc->sc_scan_pending++;
2444 2443 break;
2445 2444 }
2446 2445 case STATISTICS_NOTIFICATION:
2447 2446 /* handle statistics notification */
2448 2447 iwk_statistics_notify(sc, desc);
2449 2448 break;
2450 2449 }
2451 2450
2452 2451 sc->sc_rxq.cur = (sc->sc_rxq.cur + 1) % RX_QUEUE_SIZE;
2453 2452 }
2454 2453
2455 2454 /*
2456 2455 * driver dealt with what reveived in rx queue and tell the information
2457 2456 * to the firmware.
2458 2457 */
2459 2458 index = (index == 0) ? RX_QUEUE_SIZE - 1 : index - 1;
2460 2459 IWK_WRITE(sc, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, index & (~7));
2461 2460
2462 2461 mutex_enter(&sc->sc_glock);
2463 2462 /* re-enable interrupts */
2464 2463 IWK_WRITE(sc, CSR_INT_MASK, CSR_INI_SET_MASK);
2465 2464 sc->sc_rx_softint_pending = 0;
2466 2465 mutex_exit(&sc->sc_glock);
2467 2466
2468 2467 return (DDI_INTR_CLAIMED);
2469 2468 }
2470 2469
2471 2470 static uint_t
2472 2471 /* LINTED: argument unused in function: unused */
2473 2472 iwk_intr(caddr_t arg, caddr_t unused)
2474 2473 {
2475 2474 iwk_sc_t *sc = (iwk_sc_t *)arg;
2476 2475 uint32_t r, rfh;
2477 2476
2478 2477 mutex_enter(&sc->sc_glock);
2479 2478
2480 2479 if (sc->sc_flags & IWK_F_SUSPEND) {
2481 2480 mutex_exit(&sc->sc_glock);
2482 2481 return (DDI_INTR_UNCLAIMED);
2483 2482 }
2484 2483
2485 2484 r = IWK_READ(sc, CSR_INT);
2486 2485 if (r == 0 || r == 0xffffffff) {
2487 2486 mutex_exit(&sc->sc_glock);
2488 2487 return (DDI_INTR_UNCLAIMED);
2489 2488 }
2490 2489
2491 2490 IWK_DBG((IWK_DEBUG_INTR, "interrupt reg %x\n", r));
2492 2491
2493 2492 rfh = IWK_READ(sc, CSR_FH_INT_STATUS);
2494 2493 IWK_DBG((IWK_DEBUG_INTR, "FH interrupt reg %x\n", rfh));
2495 2494 /* disable interrupts */
2496 2495 IWK_WRITE(sc, CSR_INT_MASK, 0);
2497 2496 /* ack interrupts */
2498 2497 IWK_WRITE(sc, CSR_INT, r);
2499 2498 IWK_WRITE(sc, CSR_FH_INT_STATUS, rfh);
2500 2499
2501 2500 if (sc->sc_soft_hdl == NULL) {
2502 2501 mutex_exit(&sc->sc_glock);
2503 2502 return (DDI_INTR_CLAIMED);
2504 2503 }
2505 2504 if (r & (BIT_INT_SWERROR | BIT_INT_ERR)) {
2506 2505 cmn_err(CE_WARN, "fatal firmware error\n");
2507 2506 mutex_exit(&sc->sc_glock);
2508 2507 #ifdef DEBUG
2509 2508 /* dump event and error logs to dmesg */
2510 2509 iwk_write_error_log(sc);
2511 2510 iwk_write_event_log(sc);
2512 2511 #endif /* DEBUG */
2513 2512 iwk_stop(sc);
2514 2513 sc->sc_ostate = sc->sc_ic.ic_state;
2515 2514
2516 2515 /* not capable of fast recovery */
2517 2516 if (!IWK_CHK_FAST_RECOVER(sc))
2518 2517 ieee80211_new_state(&sc->sc_ic, IEEE80211_S_INIT, -1);
2519 2518
2520 2519 sc->sc_flags |= IWK_F_HW_ERR_RECOVER;
2521 2520 return (DDI_INTR_CLAIMED);
2522 2521 }
2523 2522
2524 2523 if (r & BIT_INT_RF_KILL) {
2525 2524 uint32_t tmp = IWK_READ(sc, CSR_GP_CNTRL);
2526 2525 if (tmp & (1 << 27))
2527 2526 cmn_err(CE_NOTE, "RF switch: radio on\n");
2528 2527 }
2529 2528
2530 2529 if ((r & (BIT_INT_FH_RX | BIT_INT_SW_RX)) ||
2531 2530 (rfh & FH_INT_RX_MASK)) {
2532 2531 sc->sc_rx_softint_pending = 1;
2533 2532 (void) ddi_intr_trigger_softint(sc->sc_soft_hdl, NULL);
2534 2533 }
2535 2534
2536 2535 if (r & BIT_INT_ALIVE) {
2537 2536 IWK_DBG((IWK_DEBUG_FW, "firmware initialized.\n"));
2538 2537 }
2539 2538
2540 2539 /* re-enable interrupts */
2541 2540 IWK_WRITE(sc, CSR_INT_MASK, CSR_INI_SET_MASK);
2542 2541 mutex_exit(&sc->sc_glock);
2543 2542
2544 2543 return (DDI_INTR_CLAIMED);
2545 2544 }
2546 2545
2547 2546 static uint8_t
2548 2547 iwk_rate_to_plcp(int rate)
2549 2548 {
2550 2549 uint8_t ret;
2551 2550
2552 2551 switch (rate) {
2553 2552 /* CCK rates */
2554 2553 case 2:
2555 2554 ret = 0xa;
2556 2555 break;
2557 2556 case 4:
2558 2557 ret = 0x14;
2559 2558 break;
2560 2559 case 11:
2561 2560 ret = 0x37;
2562 2561 break;
2563 2562 case 22:
2564 2563 ret = 0x6e;
2565 2564 break;
2566 2565 /* OFDM rates */
2567 2566 case 12:
2568 2567 ret = 0xd;
2569 2568 break;
2570 2569 case 18:
2571 2570 ret = 0xf;
2572 2571 break;
2573 2572 case 24:
2574 2573 ret = 0x5;
2575 2574 break;
2576 2575 case 36:
2577 2576 ret = 0x7;
2578 2577 break;
2579 2578 case 48:
2580 2579 ret = 0x9;
2581 2580 break;
2582 2581 case 72:
2583 2582 ret = 0xb;
2584 2583 break;
2585 2584 case 96:
2586 2585 ret = 0x1;
2587 2586 break;
2588 2587 case 108:
2589 2588 ret = 0x3;
2590 2589 break;
2591 2590 default:
2592 2591 ret = 0;
2593 2592 break;
2594 2593 }
2595 2594 return (ret);
2596 2595 }
2597 2596
2598 2597 static mblk_t *
2599 2598 iwk_m_tx(void *arg, mblk_t *mp)
2600 2599 {
2601 2600 iwk_sc_t *sc = (iwk_sc_t *)arg;
2602 2601 ieee80211com_t *ic = &sc->sc_ic;
2603 2602 mblk_t *next;
2604 2603
2605 2604 if (sc->sc_flags & IWK_F_SUSPEND) {
2606 2605 freemsgchain(mp);
2607 2606 return (NULL);
2608 2607 }
2609 2608
2610 2609 if (ic->ic_state != IEEE80211_S_RUN) {
2611 2610 freemsgchain(mp);
2612 2611 return (NULL);
2613 2612 }
2614 2613
2615 2614 if ((sc->sc_flags & IWK_F_HW_ERR_RECOVER) &&
2616 2615 IWK_CHK_FAST_RECOVER(sc)) {
2617 2616 IWK_DBG((IWK_DEBUG_FW, "iwk_m_tx(): hold queue\n"));
2618 2617 return (mp);
2619 2618 }
2620 2619
2621 2620 while (mp != NULL) {
2622 2621 next = mp->b_next;
2623 2622 mp->b_next = NULL;
2624 2623 if (iwk_send(ic, mp, IEEE80211_FC0_TYPE_DATA) != 0) {
2625 2624 mp->b_next = next;
2626 2625 break;
2627 2626 }
2628 2627 mp = next;
2629 2628 }
2630 2629 return (mp);
2631 2630 }
2632 2631
2633 2632 /* ARGSUSED */
2634 2633 static int
2635 2634 iwk_send(ieee80211com_t *ic, mblk_t *mp, uint8_t type)
2636 2635 {
2637 2636 iwk_sc_t *sc = (iwk_sc_t *)ic;
2638 2637 iwk_tx_ring_t *ring;
2639 2638 iwk_tx_desc_t *desc;
2640 2639 iwk_tx_data_t *data;
2641 2640 iwk_cmd_t *cmd;
2642 2641 iwk_tx_cmd_t *tx;
2643 2642 ieee80211_node_t *in;
2644 2643 struct ieee80211_frame *wh;
2645 2644 struct ieee80211_key *k = NULL;
2646 2645 mblk_t *m, *m0;
2647 2646 int rate, hdrlen, len, len0, mblen, off, err = IWK_SUCCESS;
2648 2647 uint16_t masks = 0;
2649 2648 uint8_t index, index1, index2;
2650 2649
2651 2650 ring = &sc->sc_txq[0];
2652 2651 data = &ring->data[ring->cur];
2653 2652 desc = data->desc;
2654 2653 cmd = data->cmd;
2655 2654 bzero(desc, sizeof (*desc));
2656 2655 bzero(cmd, sizeof (*cmd));
2657 2656
2658 2657 mutex_enter(&sc->sc_tx_lock);
2659 2658 if (sc->sc_flags & IWK_F_SUSPEND) {
2660 2659 mutex_exit(&sc->sc_tx_lock);
2661 2660 if ((type & IEEE80211_FC0_TYPE_MASK) !=
2662 2661 IEEE80211_FC0_TYPE_DATA) {
2663 2662 freemsg(mp);
2664 2663 }
2665 2664 err = IWK_FAIL;
2666 2665 goto exit;
2667 2666 }
2668 2667
2669 2668 if (ring->queued > ring->count - 64) {
2670 2669 IWK_DBG((IWK_DEBUG_TX, "iwk_send(): no txbuf\n"));
2671 2670 sc->sc_need_reschedule = 1;
2672 2671 mutex_exit(&sc->sc_tx_lock);
2673 2672 if ((type & IEEE80211_FC0_TYPE_MASK) !=
2674 2673 IEEE80211_FC0_TYPE_DATA) {
2675 2674 freemsg(mp);
2676 2675 }
2677 2676 sc->sc_tx_nobuf++;
2678 2677 err = IWK_FAIL;
2679 2678 goto exit;
2680 2679 }
2681 2680 mutex_exit(&sc->sc_tx_lock);
2682 2681
2683 2682 hdrlen = sizeof (struct ieee80211_frame);
2684 2683
2685 2684 m = allocb(msgdsize(mp) + 32, BPRI_MED);
2686 2685 if (m == NULL) { /* can not alloc buf, drop this package */
2687 2686 cmn_err(CE_WARN,
2688 2687 "iwk_send(): failed to allocate msgbuf\n");
2689 2688 freemsg(mp);
2690 2689 err = IWK_SUCCESS;
2691 2690 goto exit;
2692 2691 }
2693 2692 for (off = 0, m0 = mp; m0 != NULL; m0 = m0->b_cont) {
2694 2693 mblen = MBLKL(m0);
2695 2694 (void) memcpy(m->b_rptr + off, m0->b_rptr, mblen);
2696 2695 off += mblen;
2697 2696 }
2698 2697 m->b_wptr += off;
2699 2698 freemsg(mp);
2700 2699
2701 2700 wh = (struct ieee80211_frame *)m->b_rptr;
2702 2701
2703 2702 if (ic->ic_opmode == IEEE80211_M_IBSS &&
2704 2703 (!(IEEE80211_IS_MULTICAST(wh->i_addr1)))) {
2705 2704 mutex_enter(&sc->sc_glock);
2706 2705 mutex_enter(&sc->sc_ibss.node_tb_lock);
2707 2706
2708 2707 /*
2709 2708 * search for node in ibss node table
2710 2709 */
2711 2710 for (index1 = IWK_STA_ID;
2712 2711 index1 < IWK_STATION_COUNT; index1++) {
2713 2712 if (sc->sc_ibss.ibss_node_tb[index1].used &&
2714 2713 IEEE80211_ADDR_EQ(sc->sc_ibss.
2715 2714 ibss_node_tb[index1].node.bssid,
2716 2715 wh->i_addr1)) {
2717 2716 break;
2718 2717 }
2719 2718 }
2720 2719
2721 2720 /*
2722 2721 * if don't find in ibss node table
2723 2722 */
2724 2723 if (index1 >= IWK_BROADCAST_ID) {
2725 2724 err = iwk_clean_add_node_ibss(ic,
2726 2725 wh->i_addr1, &index2);
2727 2726 if (err != IWK_SUCCESS) {
2728 2727 cmn_err(CE_WARN, "iwk_send(): "
2729 2728 "failed to clean all nodes "
2730 2729 "and add one node\n");
2731 2730 mutex_exit(&sc->sc_ibss.node_tb_lock);
2732 2731 mutex_exit(&sc->sc_glock);
2733 2732 freemsg(m);
2734 2733 sc->sc_tx_err++;
2735 2734 err = IWK_SUCCESS;
2736 2735 goto exit;
2737 2736 }
2738 2737 index = index2;
2739 2738 } else {
2740 2739 index = index1;
2741 2740 }
2742 2741 mutex_exit(&sc->sc_ibss.node_tb_lock);
2743 2742 mutex_exit(&sc->sc_glock);
2744 2743 }
2745 2744
2746 2745 in = ieee80211_find_txnode(ic, wh->i_addr1);
2747 2746 if (in == NULL) {
2748 2747 cmn_err(CE_WARN, "iwk_send(): failed to find tx node\n");
2749 2748 freemsg(m);
2750 2749 sc->sc_tx_err++;
2751 2750 err = IWK_SUCCESS;
2752 2751 goto exit;
2753 2752 }
2754 2753 (void) ieee80211_encap(ic, m, in);
2755 2754
2756 2755 cmd->hdr.type = REPLY_TX;
2757 2756 cmd->hdr.flags = 0;
2758 2757 cmd->hdr.qid = ring->qid;
2759 2758 cmd->hdr.idx = ring->cur;
2760 2759
2761 2760 tx = (iwk_tx_cmd_t *)cmd->data;
2762 2761 tx->tx_flags = 0;
2763 2762
2764 2763 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) {
2765 2764 tx->tx_flags &= ~(LE_32(TX_CMD_FLG_ACK_MSK));
2766 2765 } else {
2767 2766 tx->tx_flags |= LE_32(TX_CMD_FLG_ACK_MSK);
2768 2767 }
2769 2768
2770 2769 if (wh->i_fc[1] & IEEE80211_FC1_WEP) {
2771 2770 k = ieee80211_crypto_encap(ic, m);
2772 2771 if (k == NULL) {
2773 2772 freemsg(m);
2774 2773 sc->sc_tx_err++;
2775 2774 err = IWK_SUCCESS;
2776 2775 goto exit;
2777 2776 }
2778 2777
2779 2778 if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_AES_CCM) {
2780 2779 tx->sec_ctl = 2; /* for CCMP */
2781 2780 tx->tx_flags |= LE_32(TX_CMD_FLG_ACK_MSK);
2782 2781 (void) memcpy(&tx->key, k->wk_key, k->wk_keylen);
2783 2782 }
2784 2783
2785 2784 /* packet header may have moved, reset our local pointer */
2786 2785 wh = (struct ieee80211_frame *)m->b_rptr;
2787 2786 }
2788 2787
2789 2788 len = msgdsize(m);
2790 2789
2791 2790 #ifdef DEBUG
2792 2791 if (iwk_dbg_flags & IWK_DEBUG_TX)
2793 2792 ieee80211_dump_pkt((uint8_t *)wh, hdrlen, 0, 0);
2794 2793 #endif
2795 2794
2796 2795 /* pickup a rate */
2797 2796 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) ==
2798 2797 IEEE80211_FC0_TYPE_MGT) {
2799 2798 /* mgmt frames are sent at 1M */
2800 2799 rate = in->in_rates.ir_rates[0];
2801 2800 } else {
2802 2801 /*
2803 2802 * do it here for the software way rate control.
2804 2803 * later for rate scaling in hardware.
2805 2804 * maybe like the following, for management frame:
2806 2805 * tx->initial_rate_index = LINK_QUAL_MAX_RETRY_NUM - 1;
2807 2806 * for data frame:
2808 2807 * tx->tx_flags |= (LE_32(TX_CMD_FLG_STA_RATE_MSK));
2809 2808 * rate = in->in_rates.ir_rates[in->in_txrate];
2810 2809 * tx->initial_rate_index = 1;
2811 2810 *
2812 2811 * now the txrate is determined in tx cmd flags, set to the
2813 2812 * max value 54M for 11g and 11M for 11b.
2814 2813 */
2815 2814
2816 2815 if (ic->ic_fixed_rate != IEEE80211_FIXED_RATE_NONE) {
2817 2816 rate = ic->ic_fixed_rate;
2818 2817 } else {
2819 2818 rate = in->in_rates.ir_rates[in->in_txrate];
2820 2819 }
2821 2820 }
2822 2821 rate &= IEEE80211_RATE_VAL;
2823 2822 IWK_DBG((IWK_DEBUG_TX, "tx rate[%d of %d] = %x",
2824 2823 in->in_txrate, in->in_rates.ir_nrates, rate));
2825 2824
2826 2825 tx->tx_flags |= (LE_32(TX_CMD_FLG_SEQ_CTL_MSK));
2827 2826
2828 2827 len0 = roundup(4 + sizeof (iwk_tx_cmd_t) + hdrlen, 4);
2829 2828 if (len0 != (4 + sizeof (iwk_tx_cmd_t) + hdrlen))
2830 2829 tx->tx_flags |= LE_32(TX_CMD_FLG_MH_PAD_MSK);
2831 2830
2832 2831 /* retrieve destination node's id */
2833 2832 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) {
2834 2833 tx->sta_id = IWK_BROADCAST_ID;
2835 2834 } else {
2836 2835 if (ic->ic_opmode == IEEE80211_M_IBSS)
2837 2836 tx->sta_id = index;
2838 2837 else
2839 2838 tx->sta_id = IWK_AP_ID;
2840 2839 }
2841 2840
2842 2841 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) ==
2843 2842 IEEE80211_FC0_TYPE_MGT) {
2844 2843 /* tell h/w to set timestamp in probe responses */
2845 2844 if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) ==
2846 2845 IEEE80211_FC0_SUBTYPE_PROBE_RESP)
2847 2846 tx->tx_flags |= LE_32(TX_CMD_FLG_TSF_MSK);
2848 2847
2849 2848 if (((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) ==
2850 2849 IEEE80211_FC0_SUBTYPE_ASSOC_REQ) ||
2851 2850 ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) ==
2852 2851 IEEE80211_FC0_SUBTYPE_REASSOC_REQ))
2853 2852 tx->timeout.pm_frame_timeout = LE_16(3);
2854 2853 else
2855 2854 tx->timeout.pm_frame_timeout = LE_16(2);
2856 2855 } else
2857 2856 tx->timeout.pm_frame_timeout = 0;
2858 2857 if (rate == 2 || rate == 4 || rate == 11 || rate == 22)
2859 2858 masks |= RATE_MCS_CCK_MSK;
2860 2859
2861 2860 masks |= RATE_MCS_ANT_B_MSK;
2862 2861 tx->rate.r.rate_n_flags = LE_32(iwk_rate_to_plcp(rate) | masks);
2863 2862
2864 2863 IWK_DBG((IWK_DEBUG_TX, "tx flag = %x",
2865 2864 LE_32(tx->tx_flags)));
2866 2865
2867 2866 tx->rts_retry_limit = 60;
2868 2867 tx->data_retry_limit = 15;
2869 2868
2870 2869 tx->stop_time.life_time = LE_32(0xffffffff);
2871 2870
2872 2871 tx->len = LE_16(len);
2873 2872
2874 2873 tx->dram_lsb_ptr =
2875 2874 LE_32(data->paddr_cmd + 4 + offsetof(iwk_tx_cmd_t, scratch));
2876 2875 tx->dram_msb_ptr = 0;
2877 2876 tx->driver_txop = 0;
2878 2877 tx->next_frame_len = 0;
2879 2878
2880 2879 (void) memcpy(tx + 1, m->b_rptr, hdrlen);
2881 2880 m->b_rptr += hdrlen;
2882 2881 (void) memcpy(data->dma_data.mem_va, m->b_rptr, len - hdrlen);
2883 2882
2884 2883 IWK_DBG((IWK_DEBUG_TX, "sending data: qid=%d idx=%d len=%d",
2885 2884 ring->qid, ring->cur, len));
2886 2885
2887 2886 /*
2888 2887 * first segment includes the tx cmd plus the 802.11 header,
2889 2888 * the second includes the remaining of the 802.11 frame.
2890 2889 */
2891 2890 desc->val0 = 2 << 24;
2892 2891 desc->pa[0].tb1_addr = data->paddr_cmd;
2893 2892 desc->pa[0].val1 = ((len0 << 4) & 0xfff0) |
2894 2893 ((data->dma_data.cookie.dmac_address & 0xffff) << 16);
2895 2894 desc->pa[0].val2 =
2896 2895 ((data->dma_data.cookie.dmac_address & 0xffff0000) >> 16) |
2897 2896 ((len - hdrlen) << 20);
2898 2897 IWK_DBG((IWK_DEBUG_TX, "phy addr1 = 0x%x phy addr2 = 0x%x "
2899 2898 "len1 = 0x%x, len2 = 0x%x val1 = 0x%x val2 = 0x%x",
2900 2899 data->paddr_cmd, data->dma_data.cookie.dmac_address,
2901 2900 len0, len - hdrlen, LE_32(desc->pa[0].val1),
2902 2901 LE_32(desc->pa[0].val2)));
2903 2902
2904 2903 mutex_enter(&sc->sc_tx_lock);
2905 2904 ring->queued++;
2906 2905 mutex_exit(&sc->sc_tx_lock);
2907 2906
2908 2907 /* kick ring */
2909 2908 sc->sc_shared->queues_byte_cnt_tbls[ring->qid].
2910 2909 tfd_offset[ring->cur].val = 8 + len;
2911 2910 if (ring->cur < IWK_MAX_WIN_SIZE) {
2912 2911 sc->sc_shared->queues_byte_cnt_tbls[ring->qid].
2913 2912 tfd_offset[IWK_QUEUE_SIZE + ring->cur].val = 8 + len;
2914 2913 }
2915 2914
2916 2915 IWK_DMA_SYNC(data->dma_data, DDI_DMA_SYNC_FORDEV);
2917 2916 IWK_DMA_SYNC(ring->dma_desc, DDI_DMA_SYNC_FORDEV);
2918 2917
2919 2918 ring->cur = (ring->cur + 1) % ring->count;
2920 2919 IWK_WRITE(sc, HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur);
2921 2920 freemsg(m);
2922 2921 /* release node reference */
2923 2922 ieee80211_free_node(in);
2924 2923
2925 2924 ic->ic_stats.is_tx_bytes += len;
2926 2925 ic->ic_stats.is_tx_frags++;
2927 2926
2928 2927 if (sc->sc_tx_timer == 0)
2929 2928 sc->sc_tx_timer = 4;
2930 2929
2931 2930 exit:
2932 2931 return (err);
2933 2932 }
2934 2933
2935 2934 static void
2936 2935 iwk_m_ioctl(void* arg, queue_t *wq, mblk_t *mp)
2937 2936 {
2938 2937 iwk_sc_t *sc = (iwk_sc_t *)arg;
2939 2938 ieee80211com_t *ic = &sc->sc_ic;
2940 2939
2941 2940 enum ieee80211_opmode oldmod;
2942 2941 iwk_tx_power_table_cmd_t txpower;
2943 2942 iwk_add_sta_t node;
2944 2943 iwk_link_quality_cmd_t link_quality;
2945 2944 uint16_t masks = 0;
2946 2945 int i, err, err1;
2947 2946
2948 2947 oldmod = ic->ic_opmode;
2949 2948
2950 2949 err = ieee80211_ioctl(ic, wq, mp);
2951 2950
2952 2951 /*
2953 2952 * return to STA mode
2954 2953 */
2955 2954 if ((0 == err || ENETRESET == err) && (oldmod != ic->ic_opmode) &&
2956 2955 (ic->ic_opmode == IEEE80211_M_STA)) {
2957 2956 /* configure rxon */
2958 2957 (void) memset(&sc->sc_config, 0, sizeof (iwk_rxon_cmd_t));
2959 2958 IEEE80211_ADDR_COPY(sc->sc_config.node_addr, ic->ic_macaddr);
2960 2959 IEEE80211_ADDR_COPY(sc->sc_config.wlap_bssid, ic->ic_macaddr);
2961 2960 sc->sc_config.chan =
2962 2961 LE_16(ieee80211_chan2ieee(ic, ic->ic_curchan));
2963 2962 sc->sc_config.flags = LE_32(RXON_FLG_TSF2HOST_MSK |
2964 2963 RXON_FLG_AUTO_DETECT_MSK |
2965 2964 RXON_FLG_BAND_24G_MSK);
2966 2965 sc->sc_config.flags &= LE_32(~RXON_FLG_CCK_MSK);
2967 2966 switch (ic->ic_opmode) {
2968 2967 case IEEE80211_M_STA:
2969 2968 sc->sc_config.dev_type = RXON_DEV_TYPE_ESS;
2970 2969 sc->sc_config.filter_flags |=
2971 2970 LE_32(RXON_FILTER_ACCEPT_GRP_MSK |
2972 2971 RXON_FILTER_DIS_DECRYPT_MSK |
2973 2972 RXON_FILTER_DIS_GRP_DECRYPT_MSK);
2974 2973 break;
2975 2974 case IEEE80211_M_IBSS:
2976 2975 case IEEE80211_M_AHDEMO:
2977 2976 sc->sc_config.dev_type = RXON_DEV_TYPE_IBSS;
2978 2977 sc->sc_config.flags |=
2979 2978 LE_32(RXON_FLG_SHORT_PREAMBLE_MSK);
2980 2979 sc->sc_config.filter_flags =
2981 2980 LE_32(RXON_FILTER_ACCEPT_GRP_MSK |
2982 2981 RXON_FILTER_DIS_DECRYPT_MSK |
2983 2982 RXON_FILTER_DIS_GRP_DECRYPT_MSK);
2984 2983 break;
2985 2984 case IEEE80211_M_HOSTAP:
2986 2985 sc->sc_config.dev_type = RXON_DEV_TYPE_AP;
2987 2986 break;
2988 2987 case IEEE80211_M_MONITOR:
2989 2988 sc->sc_config.dev_type = RXON_DEV_TYPE_SNIFFER;
2990 2989 sc->sc_config.filter_flags |=
2991 2990 LE_32(RXON_FILTER_ACCEPT_GRP_MSK |
2992 2991 RXON_FILTER_CTL2HOST_MSK |
2993 2992 RXON_FILTER_PROMISC_MSK);
2994 2993 break;
2995 2994 }
2996 2995 sc->sc_config.cck_basic_rates = 0x0f;
2997 2996 sc->sc_config.ofdm_basic_rates = 0xff;
2998 2997 sc->sc_config.ofdm_ht_single_stream_basic_rates = 0xff;
2999 2998 sc->sc_config.ofdm_ht_dual_stream_basic_rates = 0xff;
3000 2999 /* set antenna */
3001 3000 mutex_enter(&sc->sc_glock);
3002 3001 sc->sc_config.rx_chain = LE_16(RXON_RX_CHAIN_DRIVER_FORCE_MSK |
3003 3002 (0x7 << RXON_RX_CHAIN_VALID_POS) |
3004 3003 (0x6 << RXON_RX_CHAIN_FORCE_SEL_POS) |
3005 3004 (0x7 << RXON_RX_CHAIN_FORCE_MIMO_SEL_POS));
3006 3005 err1 = iwk_cmd(sc, REPLY_RXON, &sc->sc_config,
3007 3006 sizeof (iwk_rxon_cmd_t), 1);
3008 3007 if (err1 != IWK_SUCCESS) {
3009 3008 cmn_err(CE_WARN, "iwk_m_ioctl(): "
3010 3009 "failed to set configure command"
3011 3010 " please run (ifconfig unplumb and"
3012 3011 " ifconfig plumb)\n");
3013 3012 }
3014 3013 /*
3015 3014 * set Tx power for 2.4GHz channels
3016 3015 * (need further investigation. fix tx power at present)
3017 3016 */
3018 3017 (void) memset(&txpower, 0, sizeof (txpower));
3019 3018 txpower.band = 1; /* for 2.4G */
3020 3019 txpower.channel = sc->sc_config.chan;
3021 3020 txpower.channel_normal_width = 0;
3022 3021 for (i = 0; i < POWER_TABLE_NUM_HT_OFDM_ENTRIES; i++) {
3023 3022 txpower.tx_power.ht_ofdm_power[i].
3024 3023 s.ramon_tx_gain = LE_16(0x3f3f);
3025 3024 txpower.tx_power.ht_ofdm_power[i].
3026 3025 s.dsp_predis_atten = LE_16(110 | (110 << 8));
3027 3026 }
3028 3027 txpower.tx_power.legacy_cck_power.s.
3029 3028 ramon_tx_gain = LE_16(0x3f3f);
3030 3029 txpower.tx_power.legacy_cck_power.s.
3031 3030 dsp_predis_atten = LE_16(110 | (110 << 8));
3032 3031 err1 = iwk_cmd(sc, REPLY_TX_PWR_TABLE_CMD, &txpower,
3033 3032 sizeof (txpower), 1);
3034 3033 if (err1 != IWK_SUCCESS) {
3035 3034 cmn_err(CE_WARN, "iwk_m_ioctl(): failed to set txpower"
3036 3035 " please run (ifconfig unplumb "
3037 3036 "and ifconfig plumb)\n");
3038 3037 }
3039 3038 /* add broadcast node so that we can send broadcast frame */
3040 3039 (void) memset(&node, 0, sizeof (node));
3041 3040 (void) memset(node.bssid, 0xff, 6);
3042 3041 node.id = IWK_BROADCAST_ID;
3043 3042 err1 = iwk_cmd(sc, REPLY_ADD_STA, &node, sizeof (node), 1);
3044 3043 if (err1 != IWK_SUCCESS) {
3045 3044 cmn_err(CE_WARN, "iwk_m_ioctl(): "
3046 3045 "failed to add broadcast node\n");
3047 3046 }
3048 3047
3049 3048 /* TX_LINK_QUALITY cmd */
3050 3049 (void) memset(&link_quality, 0, sizeof (link_quality));
3051 3050 for (i = 0; i < LINK_QUAL_MAX_RETRY_NUM; i++) {
3052 3051 masks |= RATE_MCS_CCK_MSK;
3053 3052 masks |= RATE_MCS_ANT_B_MSK;
3054 3053 masks &= ~RATE_MCS_ANT_A_MSK;
3055 3054 link_quality.rate_n_flags[i] =
3056 3055 LE_32(iwk_rate_to_plcp(2) | masks);
3057 3056 }
3058 3057 link_quality.general_params.single_stream_ant_msk = 2;
3059 3058 link_quality.general_params.dual_stream_ant_msk = 3;
3060 3059 link_quality.agg_params.agg_dis_start_th = 3;
3061 3060 link_quality.agg_params.agg_time_limit = LE_16(4000);
3062 3061 link_quality.sta_id = IWK_BROADCAST_ID;
3063 3062 err1 = iwk_cmd(sc, REPLY_TX_LINK_QUALITY_CMD, &link_quality,
3064 3063 sizeof (link_quality), 1);
3065 3064 if (err1 != IWK_SUCCESS) {
3066 3065 cmn_err(CE_WARN, "iwk_m_ioctl(): "
3067 3066 "failed to config link quality table\n");
3068 3067 }
3069 3068 mutex_exit(&sc->sc_glock);
3070 3069 ieee80211_new_state(ic, IEEE80211_S_INIT, -1);
3071 3070 }
3072 3071
3073 3072 if (err == ENETRESET) {
3074 3073 /*
3075 3074 * This is special for the hidden AP connection.
3076 3075 * In any case, we should make sure only one 'scan'
3077 3076 * in the driver for a 'connect' CLI command. So
3078 3077 * when connecting to a hidden AP, the scan is just
3079 3078 * sent out to the air when we know the desired
3080 3079 * essid of the AP we want to connect.
3081 3080 */
3082 3081 if (ic->ic_des_esslen) {
3083 3082 if (sc->sc_flags & IWK_F_RUNNING) {
3084 3083 iwk_m_stop(sc);
3085 3084 (void) iwk_m_start(sc);
3086 3085 (void) ieee80211_new_state(ic,
3087 3086 IEEE80211_S_SCAN, -1);
3088 3087 }
3089 3088 }
3090 3089 }
3091 3090 }
3092 3091
3093 3092 /*
3094 3093 * callback functions for set/get properties
3095 3094 */
3096 3095
3097 3096 static int
3098 3097 iwk_m_getprop(void *arg, const char *pr_name, mac_prop_id_t wldp_pr_num,
3099 3098 uint_t wldp_length, void *wldp_buf)
3100 3099 {
3101 3100 int err = 0;
3102 3101 iwk_sc_t *sc = (iwk_sc_t *)arg;
3103 3102
3104 3103 err = ieee80211_getprop(&sc->sc_ic, pr_name, wldp_pr_num,
3105 3104 wldp_length, wldp_buf);
3106 3105
3107 3106 return (err);
3108 3107 }
3109 3108
3110 3109 static int
3111 3110 iwk_m_setprop(void *arg, const char *pr_name, mac_prop_id_t wldp_pr_num,
3112 3111 uint_t wldp_length, const void *wldp_buf)
3113 3112 {
3114 3113 int err;
3115 3114 iwk_sc_t *sc = (iwk_sc_t *)arg;
3116 3115 ieee80211com_t *ic = &sc->sc_ic;
3117 3116
3118 3117 err = ieee80211_setprop(ic, pr_name, wldp_pr_num, wldp_length,
3119 3118 wldp_buf);
3120 3119
3121 3120 if (err == ENETRESET) {
3122 3121 if (ic->ic_des_esslen) {
3123 3122 if (sc->sc_flags & IWK_F_RUNNING) {
3124 3123 iwk_m_stop(sc);
3125 3124 (void) iwk_m_start(sc);
3126 3125 (void) ieee80211_new_state(ic,
3127 3126 IEEE80211_S_SCAN, -1);
3128 3127 }
3129 3128 }
3130 3129 err = 0;
3131 3130 }
3132 3131
3133 3132 return (err);
3134 3133 }
3135 3134
3136 3135 static void
3137 3136 iwk_m_propinfo(void *arg, const char *pr_name, mac_prop_id_t wldp_pr_num,
3138 3137 mac_prop_info_handle_t mph)
3139 3138 {
3140 3139 iwk_sc_t *sc = (iwk_sc_t *)arg;
3141 3140 ieee80211com_t *ic = &sc->sc_ic;
3142 3141
3143 3142 ieee80211_propinfo(ic, pr_name, wldp_pr_num, mph);
3144 3143 }
3145 3144
3146 3145 /*ARGSUSED*/
3147 3146 static int
3148 3147 iwk_m_stat(void *arg, uint_t stat, uint64_t *val)
3149 3148 {
3150 3149 iwk_sc_t *sc = (iwk_sc_t *)arg;
3151 3150 ieee80211com_t *ic = &sc->sc_ic;
3152 3151 ieee80211_node_t *in;
3153 3152
3154 3153 mutex_enter(&sc->sc_glock);
3155 3154 switch (stat) {
3156 3155 case MAC_STAT_IFSPEED:
3157 3156 in = ic->ic_bss;
3158 3157 *val = ((ic->ic_fixed_rate == IEEE80211_FIXED_RATE_NONE) ?
3159 3158 IEEE80211_RATE(in->in_txrate) :
3160 3159 ic->ic_fixed_rate) / 2 * 1000000;
3161 3160 break;
3162 3161 case MAC_STAT_NOXMTBUF:
3163 3162 *val = sc->sc_tx_nobuf;
3164 3163 break;
3165 3164 case MAC_STAT_NORCVBUF:
3166 3165 *val = sc->sc_rx_nobuf;
3167 3166 break;
3168 3167 case MAC_STAT_IERRORS:
3169 3168 *val = sc->sc_rx_err;
3170 3169 break;
3171 3170 case MAC_STAT_RBYTES:
3172 3171 *val = ic->ic_stats.is_rx_bytes;
3173 3172 break;
3174 3173 case MAC_STAT_IPACKETS:
3175 3174 *val = ic->ic_stats.is_rx_frags;
3176 3175 break;
3177 3176 case MAC_STAT_OBYTES:
3178 3177 *val = ic->ic_stats.is_tx_bytes;
3179 3178 break;
3180 3179 case MAC_STAT_OPACKETS:
3181 3180 *val = ic->ic_stats.is_tx_frags;
3182 3181 break;
3183 3182 case MAC_STAT_OERRORS:
3184 3183 case WIFI_STAT_TX_FAILED:
3185 3184 *val = sc->sc_tx_err;
3186 3185 break;
3187 3186 case WIFI_STAT_TX_RETRANS:
3188 3187 *val = sc->sc_tx_retries;
3189 3188 break;
3190 3189 case WIFI_STAT_FCS_ERRORS:
3191 3190 case WIFI_STAT_WEP_ERRORS:
3192 3191 case WIFI_STAT_TX_FRAGS:
3193 3192 case WIFI_STAT_MCAST_TX:
3194 3193 case WIFI_STAT_RTS_SUCCESS:
3195 3194 case WIFI_STAT_RTS_FAILURE:
3196 3195 case WIFI_STAT_ACK_FAILURE:
3197 3196 case WIFI_STAT_RX_FRAGS:
3198 3197 case WIFI_STAT_MCAST_RX:
3199 3198 case WIFI_STAT_RX_DUPS:
3200 3199 mutex_exit(&sc->sc_glock);
3201 3200 return (ieee80211_stat(ic, stat, val));
3202 3201 default:
3203 3202 mutex_exit(&sc->sc_glock);
3204 3203 return (ENOTSUP);
3205 3204 }
3206 3205 mutex_exit(&sc->sc_glock);
3207 3206
3208 3207 return (IWK_SUCCESS);
3209 3208
3210 3209 }
3211 3210
3212 3211 static int
3213 3212 iwk_m_start(void *arg)
3214 3213 {
3215 3214 iwk_sc_t *sc = (iwk_sc_t *)arg;
3216 3215 ieee80211com_t *ic = &sc->sc_ic;
3217 3216 int err;
3218 3217
3219 3218 err = iwk_init(sc);
3220 3219
3221 3220 if (err != IWK_SUCCESS) {
3222 3221 /*
3223 3222 * The hw init err(eg. RF is OFF). Return Success to make
3224 3223 * the 'plumb' succeed. The iwk_thread() tries to re-init
3225 3224 * background.
3226 3225 */
3227 3226 mutex_enter(&sc->sc_glock);
3228 3227 sc->sc_flags |= IWK_F_HW_ERR_RECOVER;
3229 3228 mutex_exit(&sc->sc_glock);
3230 3229 return (IWK_SUCCESS);
3231 3230 }
3232 3231
3233 3232 ieee80211_new_state(ic, IEEE80211_S_INIT, -1);
3234 3233
3235 3234 mutex_enter(&sc->sc_glock);
3236 3235 sc->sc_flags |= IWK_F_RUNNING;
3237 3236 mutex_exit(&sc->sc_glock);
3238 3237
3239 3238 return (IWK_SUCCESS);
3240 3239 }
3241 3240
3242 3241 static void
3243 3242 iwk_m_stop(void *arg)
3244 3243 {
3245 3244 iwk_sc_t *sc = (iwk_sc_t *)arg;
3246 3245 ieee80211com_t *ic = &sc->sc_ic;
3247 3246
3248 3247 iwk_stop(sc);
3249 3248 ieee80211_new_state(ic, IEEE80211_S_INIT, -1);
3250 3249 ieee80211_stop_watchdog(ic);
3251 3250 mutex_enter(&sc->sc_mt_lock);
3252 3251 sc->sc_flags &= ~IWK_F_HW_ERR_RECOVER;
3253 3252 sc->sc_flags &= ~IWK_F_RATE_AUTO_CTL;
3254 3253 mutex_exit(&sc->sc_mt_lock);
3255 3254 mutex_enter(&sc->sc_glock);
3256 3255 sc->sc_flags &= ~IWK_F_RUNNING;
3257 3256 mutex_exit(&sc->sc_glock);
3258 3257 }
3259 3258
3260 3259 /*ARGSUSED*/
3261 3260 static int
3262 3261 iwk_m_unicst(void *arg, const uint8_t *macaddr)
3263 3262 {
3264 3263 iwk_sc_t *sc = (iwk_sc_t *)arg;
3265 3264 ieee80211com_t *ic = &sc->sc_ic;
3266 3265 int err;
3267 3266
3268 3267 if (!IEEE80211_ADDR_EQ(ic->ic_macaddr, macaddr)) {
3269 3268 IEEE80211_ADDR_COPY(ic->ic_macaddr, macaddr);
3270 3269 mutex_enter(&sc->sc_glock);
3271 3270 err = iwk_config(sc);
3272 3271 mutex_exit(&sc->sc_glock);
3273 3272 if (err != IWK_SUCCESS) {
3274 3273 cmn_err(CE_WARN,
3275 3274 "iwk_m_unicst(): "
3276 3275 "failed to configure device\n");
3277 3276 goto fail;
3278 3277 }
3279 3278 }
3280 3279 return (IWK_SUCCESS);
3281 3280 fail:
3282 3281 return (err);
3283 3282 }
3284 3283
3285 3284 /*ARGSUSED*/
3286 3285 static int
3287 3286 iwk_m_multicst(void *arg, boolean_t add, const uint8_t *m)
3288 3287 {
3289 3288 return (IWK_SUCCESS);
3290 3289 }
3291 3290
3292 3291 /*ARGSUSED*/
3293 3292 static int
3294 3293 iwk_m_promisc(void *arg, boolean_t on)
3295 3294 {
3296 3295 return (IWK_SUCCESS);
3297 3296 }
3298 3297
3299 3298 static void
3300 3299 iwk_thread(iwk_sc_t *sc)
3301 3300 {
3302 3301 ieee80211com_t *ic = &sc->sc_ic;
3303 3302 clock_t clk;
3304 3303 int times = 0, err, n = 0, timeout = 0;
3305 3304 uint32_t tmp;
3306 3305
3307 3306 mutex_enter(&sc->sc_mt_lock);
3308 3307 while (sc->sc_mf_thread_switch) {
3309 3308 tmp = IWK_READ(sc, CSR_GP_CNTRL);
3310 3309 if (tmp & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW) {
3311 3310 sc->sc_flags &= ~IWK_F_RADIO_OFF;
3312 3311 } else {
3313 3312 sc->sc_flags |= IWK_F_RADIO_OFF;
3314 3313 }
3315 3314 /*
3316 3315 * If in SUSPEND or the RF is OFF, do nothing
3317 3316 */
3318 3317 if ((sc->sc_flags & IWK_F_SUSPEND) ||
3319 3318 (sc->sc_flags & IWK_F_RADIO_OFF)) {
3320 3319 mutex_exit(&sc->sc_mt_lock);
3321 3320 delay(drv_usectohz(100000));
3322 3321 mutex_enter(&sc->sc_mt_lock);
3323 3322 continue;
3324 3323 }
3325 3324
3326 3325 /*
3327 3326 * recovery fatal error
3328 3327 */
3329 3328 if (ic->ic_mach &&
3330 3329 (sc->sc_flags & IWK_F_HW_ERR_RECOVER)) {
3331 3330
3332 3331 IWK_DBG((IWK_DEBUG_FW,
3333 3332 "iwk_thread(): "
3334 3333 "try to recover fatal hw error: %d\n", times++));
3335 3334
3336 3335 iwk_stop(sc);
3337 3336
3338 3337 if (IWK_CHK_FAST_RECOVER(sc)) {
3339 3338 /* save runtime configuration */
3340 3339 bcopy(&sc->sc_config, &sc->sc_config_save,
3341 3340 sizeof (sc->sc_config));
3342 3341 } else {
3343 3342 mutex_exit(&sc->sc_mt_lock);
3344 3343 ieee80211_new_state(ic, IEEE80211_S_INIT, -1);
3345 3344 delay(drv_usectohz(2000000 + n*500000));
3346 3345 mutex_enter(&sc->sc_mt_lock);
3347 3346 }
3348 3347
3349 3348 err = iwk_init(sc);
3350 3349 if (err != IWK_SUCCESS) {
3351 3350 n++;
3352 3351 if (n < 20)
3353 3352 continue;
3354 3353 }
3355 3354 n = 0;
3356 3355 if (!err)
3357 3356 sc->sc_flags |= IWK_F_RUNNING;
3358 3357
3359 3358 if (!IWK_CHK_FAST_RECOVER(sc) ||
3360 3359 iwk_fast_recover(sc) != IWK_SUCCESS) {
3361 3360 sc->sc_flags &= ~IWK_F_HW_ERR_RECOVER;
3362 3361
3363 3362 mutex_exit(&sc->sc_mt_lock);
3364 3363 delay(drv_usectohz(2000000));
3365 3364 if (sc->sc_ostate != IEEE80211_S_INIT)
3366 3365 ieee80211_new_state(ic,
3367 3366 IEEE80211_S_SCAN, 0);
3368 3367 mutex_enter(&sc->sc_mt_lock);
3369 3368 }
3370 3369 }
3371 3370
3372 3371 if (ic->ic_mach && (sc->sc_flags & IWK_F_LAZY_RESUME)) {
3373 3372 IWK_DBG((IWK_DEBUG_RESUME,
3374 3373 "iwk_thread(): lazy resume\n"));
3375 3374
3376 3375 sc->sc_flags &= ~IWK_F_LAZY_RESUME;
3377 3376 mutex_exit(&sc->sc_mt_lock);
3378 3377 /*
3379 3378 * NB: under WPA mode, this call hangs (door problem?)
3380 3379 * when called in iwk_attach() and iwk_detach() while
3381 3380 * system is in the procedure of CPR. To be safe, let
3382 3381 * the thread do this.
3383 3382 */
3384 3383 ieee80211_new_state(&sc->sc_ic, IEEE80211_S_INIT, -1);
3385 3384 mutex_enter(&sc->sc_mt_lock);
3386 3385 }
3387 3386
3388 3387 if (ic->ic_mach &&
3389 3388 (sc->sc_flags & IWK_F_SCANNING) && sc->sc_scan_pending) {
3390 3389 IWK_DBG((IWK_DEBUG_SCAN,
3391 3390 "iwk_thread(): "
3392 3391 "wait for probe response\n"));
3393 3392 sc->sc_scan_pending--;
3394 3393 mutex_exit(&sc->sc_mt_lock);
3395 3394 delay(drv_usectohz(200000));
3396 3395 if (sc->sc_flags & IWK_F_SCANNING)
3397 3396 ieee80211_next_scan(ic);
3398 3397 mutex_enter(&sc->sc_mt_lock);
3399 3398 }
3400 3399
3401 3400 /*
3402 3401 * rate ctl
3403 3402 */
3404 3403 if (ic->ic_mach &&
3405 3404 (sc->sc_flags & IWK_F_RATE_AUTO_CTL)) {
3406 3405 clk = ddi_get_lbolt();
3407 3406 if (clk > sc->sc_clk + drv_usectohz(500000)) {
3408 3407 iwk_amrr_timeout(sc);
3409 3408 }
3410 3409 }
3411 3410
3412 3411 if ((ic->ic_state == IEEE80211_S_RUN) &&
3413 3412 (ic->ic_beaconmiss++ > 50)) { /* 5 seconds */
3414 3413 cmn_err(CE_WARN, "iwk: beacon missed for 5 seconds\n");
3415 3414 (void) ieee80211_new_state(ic,
3416 3415 IEEE80211_S_INIT, -1);
3417 3416 }
3418 3417
3419 3418 mutex_exit(&sc->sc_mt_lock);
3420 3419 delay(drv_usectohz(100000));
3421 3420 mutex_enter(&sc->sc_mt_lock);
3422 3421
3423 3422 if (sc->sc_tx_timer) {
3424 3423 timeout++;
3425 3424 if (timeout == 10) {
3426 3425 sc->sc_tx_timer--;
3427 3426 if (sc->sc_tx_timer == 0) {
3428 3427 sc->sc_flags |= IWK_F_HW_ERR_RECOVER;
3429 3428 sc->sc_ostate = IEEE80211_S_RUN;
3430 3429 IWK_DBG((IWK_DEBUG_FW,
3431 3430 "iwk_thread(): try to recover from"
3432 3431 " 'send fail\n"));
3433 3432 }
3434 3433 timeout = 0;
3435 3434 }
3436 3435 }
3437 3436
3438 3437 }
3439 3438 sc->sc_mf_thread = NULL;
3440 3439 cv_signal(&sc->sc_mt_cv);
3441 3440 mutex_exit(&sc->sc_mt_lock);
3442 3441 }
3443 3442
3444 3443
3445 3444 /*
3446 3445 * Send a command to the firmware.
3447 3446 */
3448 3447 static int
3449 3448 iwk_cmd(iwk_sc_t *sc, int code, const void *buf, int size, int async)
3450 3449 {
3451 3450 iwk_tx_ring_t *ring = &sc->sc_txq[IWK_CMD_QUEUE_NUM];
3452 3451 iwk_tx_desc_t *desc;
3453 3452 iwk_cmd_t *cmd;
3454 3453 clock_t clk;
3455 3454
3456 3455 ASSERT(size <= sizeof (cmd->data));
3457 3456 ASSERT(mutex_owned(&sc->sc_glock));
3458 3457
3459 3458 IWK_DBG((IWK_DEBUG_CMD, "iwk_cmd() code[%d]", code));
3460 3459 desc = ring->data[ring->cur].desc;
3461 3460 cmd = ring->data[ring->cur].cmd;
3462 3461
3463 3462 cmd->hdr.type = (uint8_t)code;
3464 3463 cmd->hdr.flags = 0;
3465 3464 cmd->hdr.qid = ring->qid;
3466 3465 cmd->hdr.idx = ring->cur;
3467 3466 (void) memcpy(cmd->data, buf, size);
3468 3467 (void) memset(desc, 0, sizeof (*desc));
3469 3468
3470 3469 desc->val0 = 1 << 24;
3471 3470 desc->pa[0].tb1_addr =
3472 3471 (uint32_t)(ring->data[ring->cur].paddr_cmd & 0xffffffff);
3473 3472 desc->pa[0].val1 = ((4 + size) << 4) & 0xfff0;
3474 3473
3475 3474 /* kick cmd ring XXX */
3476 3475 sc->sc_shared->queues_byte_cnt_tbls[ring->qid].
3477 3476 tfd_offset[ring->cur].val = 8;
3478 3477 if (ring->cur < IWK_MAX_WIN_SIZE) {
3479 3478 sc->sc_shared->queues_byte_cnt_tbls[ring->qid].
3480 3479 tfd_offset[IWK_QUEUE_SIZE + ring->cur].val = 8;
3481 3480 }
3482 3481 ring->cur = (ring->cur + 1) % ring->count;
3483 3482 IWK_WRITE(sc, HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur);
3484 3483
3485 3484 if (async)
3486 3485 return (IWK_SUCCESS);
3487 3486 else {
3488 3487 sc->sc_flags &= ~IWK_F_CMD_DONE;
3489 3488 clk = ddi_get_lbolt() + drv_usectohz(2000000);
3490 3489 while (!(sc->sc_flags & IWK_F_CMD_DONE)) {
3491 3490 if (cv_timedwait(&sc->sc_cmd_cv, &sc->sc_glock, clk) <
3492 3491 0)
3493 3492 break;
3494 3493 }
3495 3494 if (sc->sc_flags & IWK_F_CMD_DONE)
3496 3495 return (IWK_SUCCESS);
3497 3496 else
3498 3497 return (IWK_FAIL);
3499 3498 }
3500 3499 }
3501 3500
3502 3501 static void
3503 3502 iwk_set_led(iwk_sc_t *sc, uint8_t id, uint8_t off, uint8_t on)
3504 3503 {
3505 3504 iwk_led_cmd_t led;
3506 3505
3507 3506 led.interval = LE_32(100000); /* unit: 100ms */
3508 3507 led.id = id;
3509 3508 led.off = off;
3510 3509 led.on = on;
3511 3510
3512 3511 (void) iwk_cmd(sc, REPLY_LEDS_CMD, &led, sizeof (led), 1);
3513 3512 }
3514 3513
3515 3514 static int
3516 3515 iwk_hw_set_before_auth(iwk_sc_t *sc)
3517 3516 {
3518 3517 ieee80211com_t *ic = &sc->sc_ic;
3519 3518 ieee80211_node_t *in = ic->ic_bss;
3520 3519 iwk_add_sta_t node;
3521 3520 iwk_link_quality_cmd_t link_quality;
3522 3521 struct ieee80211_rateset rs;
3523 3522 uint16_t masks = 0, rate;
3524 3523 int i, err;
3525 3524
3526 3525 if (in->in_chan == IEEE80211_CHAN_ANYC) {
3527 3526 cmn_err(CE_WARN, "iwk_hw_set_before_auth():"
3528 3527 "channel (%d) isn't in proper range\n",
3529 3528 LE_16(ieee80211_chan2ieee(ic, in->in_chan)));
3530 3529 return (IWK_FAIL);
3531 3530 }
3532 3531
3533 3532 /* update adapter's configuration according the info of target AP */
3534 3533 IEEE80211_ADDR_COPY(sc->sc_config.bssid, in->in_bssid);
3535 3534 sc->sc_config.chan = LE_16(ieee80211_chan2ieee(ic, in->in_chan));
3536 3535 if (ic->ic_curmode == IEEE80211_MODE_11B) {
3537 3536 sc->sc_config.cck_basic_rates = 0x03;
3538 3537 sc->sc_config.ofdm_basic_rates = 0;
3539 3538 } else if ((in->in_chan != IEEE80211_CHAN_ANYC) &&
3540 3539 (IEEE80211_IS_CHAN_5GHZ(in->in_chan))) {
3541 3540 sc->sc_config.cck_basic_rates = 0;
3542 3541 sc->sc_config.ofdm_basic_rates = 0x15;
3543 3542 } else { /* assume 802.11b/g */
3544 3543 sc->sc_config.cck_basic_rates = 0x0f;
3545 3544 sc->sc_config.ofdm_basic_rates = 0xff;
3546 3545 }
3547 3546
3548 3547 sc->sc_config.flags &= ~LE_32(RXON_FLG_SHORT_PREAMBLE_MSK |
3549 3548 RXON_FLG_SHORT_SLOT_MSK);
3550 3549
3551 3550 if (ic->ic_flags & IEEE80211_F_SHSLOT)
3552 3551 sc->sc_config.flags |= LE_32(RXON_FLG_SHORT_SLOT_MSK);
3553 3552 else
3554 3553 sc->sc_config.flags &= LE_32(~RXON_FLG_SHORT_SLOT_MSK);
3555 3554
3556 3555 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE)
3557 3556 sc->sc_config.flags |= LE_32(RXON_FLG_SHORT_PREAMBLE_MSK);
3558 3557 else
3559 3558 sc->sc_config.flags &= LE_32(~RXON_FLG_SHORT_PREAMBLE_MSK);
3560 3559
3561 3560 IWK_DBG((IWK_DEBUG_80211, "config chan %d flags %x "
3562 3561 "filter_flags %x cck %x ofdm %x"
3563 3562 " bssid:%02x:%02x:%02x:%02x:%02x:%2x\n",
3564 3563 LE_16(sc->sc_config.chan), LE_32(sc->sc_config.flags),
3565 3564 LE_32(sc->sc_config.filter_flags),
3566 3565 sc->sc_config.cck_basic_rates, sc->sc_config.ofdm_basic_rates,
3567 3566 sc->sc_config.bssid[0], sc->sc_config.bssid[1],
3568 3567 sc->sc_config.bssid[2], sc->sc_config.bssid[3],
3569 3568 sc->sc_config.bssid[4], sc->sc_config.bssid[5]));
3570 3569 err = iwk_cmd(sc, REPLY_RXON, &sc->sc_config,
3571 3570 sizeof (iwk_rxon_cmd_t), 1);
3572 3571 if (err != IWK_SUCCESS) {
3573 3572 cmn_err(CE_WARN, "iwk_hw_set_before_auth():"
3574 3573 " failed to config chan%d\n",
3575 3574 sc->sc_config.chan);
3576 3575 return (err);
3577 3576 }
3578 3577
3579 3578 /* obtain current temperature of chipset */
3580 3579 sc->sc_tempera = iwk_curr_tempera(sc);
3581 3580
3582 3581 /* make Tx power calibration to determine the gains of DSP and radio */
3583 3582 err = iwk_tx_power_calibration(sc);
3584 3583 if (err) {
3585 3584 cmn_err(CE_WARN, "iwk_hw_set_before_auth():"
3586 3585 "failed to set tx power table\n");
3587 3586 return (err);
3588 3587 }
3589 3588
3590 3589 /* add default AP node */
3591 3590 (void) memset(&node, 0, sizeof (node));
3592 3591 IEEE80211_ADDR_COPY(node.bssid, in->in_bssid);
3593 3592 node.id = IWK_AP_ID;
3594 3593 err = iwk_cmd(sc, REPLY_ADD_STA, &node, sizeof (node), 1);
3595 3594 if (err != IWK_SUCCESS) {
3596 3595 cmn_err(CE_WARN, "iwk_hw_set_before_auth(): "
3597 3596 "failed to add BSS node\n");
3598 3597 return (err);
3599 3598 }
3600 3599
3601 3600 /* TX_LINK_QUALITY cmd */
3602 3601 (void) memset(&link_quality, 0, sizeof (link_quality));
3603 3602 rs = ic->ic_sup_rates[ieee80211_chan2mode(ic, ic->ic_curchan)];
3604 3603 for (i = 0; i < LINK_QUAL_MAX_RETRY_NUM; i++) {
3605 3604 if (i < rs.ir_nrates)
3606 3605 rate = rs.ir_rates[rs.ir_nrates - i];
3607 3606 else
3608 3607 rate = 2;
3609 3608 if (rate == 2 || rate == 4 || rate == 11 || rate == 22)
3610 3609 masks |= RATE_MCS_CCK_MSK;
3611 3610 masks |= RATE_MCS_ANT_B_MSK;
3612 3611 masks &= ~RATE_MCS_ANT_A_MSK;
3613 3612 link_quality.rate_n_flags[i] =
3614 3613 LE_32(iwk_rate_to_plcp(rate) | masks);
3615 3614 }
3616 3615
3617 3616 link_quality.general_params.single_stream_ant_msk = 2;
3618 3617 link_quality.general_params.dual_stream_ant_msk = 3;
3619 3618 link_quality.agg_params.agg_dis_start_th = 3;
3620 3619 link_quality.agg_params.agg_time_limit = LE_16(4000);
3621 3620 link_quality.sta_id = IWK_AP_ID;
3622 3621 err = iwk_cmd(sc, REPLY_TX_LINK_QUALITY_CMD, &link_quality,
3623 3622 sizeof (link_quality), 1);
3624 3623 if (err != IWK_SUCCESS) {
3625 3624 cmn_err(CE_WARN, "iwk_hw_set_before_auth(): "
3626 3625 "failed to config link quality table\n");
3627 3626 return (err);
3628 3627 }
3629 3628
3630 3629 return (IWK_SUCCESS);
3631 3630 }
3632 3631
3633 3632 /*
3634 3633 * Send a scan request(assembly scan cmd) to the firmware.
3635 3634 */
3636 3635 static int
3637 3636 iwk_scan(iwk_sc_t *sc)
3638 3637 {
3639 3638 ieee80211com_t *ic = &sc->sc_ic;
3640 3639 iwk_tx_ring_t *ring = &sc->sc_txq[IWK_CMD_QUEUE_NUM];
3641 3640 iwk_tx_desc_t *desc;
3642 3641 iwk_tx_data_t *data;
3643 3642 iwk_cmd_t *cmd;
3644 3643 iwk_scan_hdr_t *hdr;
3645 3644 iwk_scan_chan_t *chan;
3646 3645 struct ieee80211_frame *wh;
3647 3646 ieee80211_node_t *in = ic->ic_bss;
3648 3647 uint8_t essid[IEEE80211_NWID_LEN+1];
3649 3648 struct ieee80211_rateset *rs;
3650 3649 enum ieee80211_phymode mode;
3651 3650 uint8_t *frm;
3652 3651 int i, pktlen, nrates;
3653 3652
3654 3653 data = &ring->data[ring->cur];
3655 3654 desc = data->desc;
3656 3655 cmd = (iwk_cmd_t *)data->dma_data.mem_va;
3657 3656
3658 3657 cmd->hdr.type = REPLY_SCAN_CMD;
3659 3658 cmd->hdr.flags = 0;
3660 3659 cmd->hdr.qid = ring->qid;
3661 3660 cmd->hdr.idx = ring->cur | 0x40;
3662 3661
3663 3662 hdr = (iwk_scan_hdr_t *)cmd->data;
3664 3663 (void) memset(hdr, 0, sizeof (iwk_scan_hdr_t));
3665 3664 hdr->nchan = 1;
3666 3665 hdr->quiet_time = LE_16(50);
3667 3666 hdr->quiet_plcp_th = LE_16(1);
3668 3667
3669 3668 hdr->flags = LE_32(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK);
3670 3669 hdr->rx_chain = LE_16(RXON_RX_CHAIN_DRIVER_FORCE_MSK |
3671 3670 (0x7 << RXON_RX_CHAIN_VALID_POS) |
3672 3671 (0x6 << RXON_RX_CHAIN_FORCE_SEL_POS) |
3673 3672 (0x7 << RXON_RX_CHAIN_FORCE_MIMO_SEL_POS));
3674 3673
3675 3674 hdr->tx_cmd.tx_flags = LE_32(TX_CMD_FLG_SEQ_CTL_MSK);
3676 3675 hdr->tx_cmd.sta_id = IWK_BROADCAST_ID;
3677 3676 hdr->tx_cmd.stop_time.life_time = LE_32(0xffffffff);
3678 3677 hdr->tx_cmd.tx_flags |= LE_32(0x200);
3679 3678 hdr->tx_cmd.rate.r.rate_n_flags = LE_32(iwk_rate_to_plcp(2));
3680 3679 hdr->tx_cmd.rate.r.rate_n_flags |=
3681 3680 LE_32(RATE_MCS_ANT_B_MSK|RATE_MCS_CCK_MSK);
3682 3681 hdr->direct_scan[0].len = ic->ic_des_esslen;
3683 3682 hdr->direct_scan[0].id = IEEE80211_ELEMID_SSID;
3684 3683
3685 3684 if (ic->ic_des_esslen) {
3686 3685 bcopy(ic->ic_des_essid, essid, ic->ic_des_esslen);
3687 3686 essid[ic->ic_des_esslen] = '\0';
3688 3687 IWK_DBG((IWK_DEBUG_SCAN, "directed scan %s\n", essid));
3689 3688
3690 3689 bcopy(ic->ic_des_essid, hdr->direct_scan[0].ssid,
3691 3690 ic->ic_des_esslen);
3692 3691 } else {
3693 3692 bzero(hdr->direct_scan[0].ssid,
3694 3693 sizeof (hdr->direct_scan[0].ssid));
3695 3694 }
3696 3695 /*
3697 3696 * a probe request frame is required after the REPLY_SCAN_CMD
3698 3697 */
3699 3698 wh = (struct ieee80211_frame *)(hdr + 1);
3700 3699 wh->i_fc[0] = IEEE80211_FC0_VERSION_0 | IEEE80211_FC0_TYPE_MGT |
3701 3700 IEEE80211_FC0_SUBTYPE_PROBE_REQ;
3702 3701 wh->i_fc[1] = IEEE80211_FC1_DIR_NODS;
3703 3702 (void) memset(wh->i_addr1, 0xff, 6);
3704 3703 IEEE80211_ADDR_COPY(wh->i_addr2, ic->ic_macaddr);
3705 3704 (void) memset(wh->i_addr3, 0xff, 6);
3706 3705 *(uint16_t *)&wh->i_dur[0] = 0;
3707 3706 *(uint16_t *)&wh->i_seq[0] = 0;
3708 3707
3709 3708 frm = (uint8_t *)(wh + 1);
3710 3709
3711 3710 /* essid IE */
3712 3711 if (in->in_esslen) {
3713 3712 bcopy(in->in_essid, essid, in->in_esslen);
3714 3713 essid[in->in_esslen] = '\0';
3715 3714 IWK_DBG((IWK_DEBUG_SCAN, "probe with ESSID %s\n",
3716 3715 essid));
3717 3716 }
3718 3717 *frm++ = IEEE80211_ELEMID_SSID;
3719 3718 *frm++ = in->in_esslen;
3720 3719 (void) memcpy(frm, in->in_essid, in->in_esslen);
3721 3720 frm += in->in_esslen;
3722 3721
3723 3722 mode = ieee80211_chan2mode(ic, ic->ic_curchan);
3724 3723 rs = &ic->ic_sup_rates[mode];
3725 3724
3726 3725 /* supported rates IE */
3727 3726 *frm++ = IEEE80211_ELEMID_RATES;
3728 3727 nrates = rs->ir_nrates;
3729 3728 if (nrates > IEEE80211_RATE_SIZE)
3730 3729 nrates = IEEE80211_RATE_SIZE;
3731 3730 *frm++ = (uint8_t)nrates;
3732 3731 (void) memcpy(frm, rs->ir_rates, nrates);
3733 3732 frm += nrates;
3734 3733
3735 3734 /* supported xrates IE */
3736 3735 if (rs->ir_nrates > IEEE80211_RATE_SIZE) {
3737 3736 nrates = rs->ir_nrates - IEEE80211_RATE_SIZE;
3738 3737 *frm++ = IEEE80211_ELEMID_XRATES;
3739 3738 *frm++ = (uint8_t)nrates;
3740 3739 (void) memcpy(frm, rs->ir_rates + IEEE80211_RATE_SIZE, nrates);
3741 3740 frm += nrates;
3742 3741 }
3743 3742
3744 3743 /* optionnal IE (usually for wpa) */
3745 3744 if (ic->ic_opt_ie != NULL) {
3746 3745 (void) memcpy(frm, ic->ic_opt_ie, ic->ic_opt_ie_len);
3747 3746 frm += ic->ic_opt_ie_len;
3748 3747 }
3749 3748
3750 3749 /* setup length of probe request */
3751 3750 hdr->tx_cmd.len = LE_16(_PTRDIFF(frm, wh));
3752 3751 hdr->len = LE_16(hdr->nchan * sizeof (iwk_scan_chan_t) +
3753 3752 LE_16(hdr->tx_cmd.len) + sizeof (iwk_scan_hdr_t));
3754 3753
3755 3754 /*
3756 3755 * the attribute of the scan channels are required after the probe
3757 3756 * request frame.
3758 3757 */
3759 3758 chan = (iwk_scan_chan_t *)frm;
3760 3759 for (i = 1; i <= hdr->nchan; i++, chan++) {
3761 3760 if (ic->ic_des_esslen) {
3762 3761 chan->type = 3;
3763 3762 } else {
3764 3763 chan->type = 1;
3765 3764 }
3766 3765
3767 3766 chan->chan = ieee80211_chan2ieee(ic, ic->ic_curchan);
3768 3767 chan->tpc.tx_gain = 0x3f;
3769 3768 chan->tpc.dsp_atten = 110;
3770 3769 chan->active_dwell = LE_16(50);
3771 3770 chan->passive_dwell = LE_16(120);
3772 3771
3773 3772 frm += sizeof (iwk_scan_chan_t);
3774 3773 }
3775 3774
3776 3775 pktlen = _PTRDIFF(frm, cmd);
3777 3776
3778 3777 (void) memset(desc, 0, sizeof (*desc));
3779 3778 desc->val0 = 1 << 24;
3780 3779 desc->pa[0].tb1_addr =
3781 3780 (uint32_t)(data->dma_data.cookie.dmac_address & 0xffffffff);
3782 3781 desc->pa[0].val1 = (pktlen << 4) & 0xfff0;
3783 3782
3784 3783 /*
3785 3784 * maybe for cmd, filling the byte cnt table is not necessary.
3786 3785 * anyway, we fill it here.
3787 3786 */
3788 3787 sc->sc_shared->queues_byte_cnt_tbls[ring->qid].
3789 3788 tfd_offset[ring->cur].val = 8;
3790 3789 if (ring->cur < IWK_MAX_WIN_SIZE) {
3791 3790 sc->sc_shared->queues_byte_cnt_tbls[ring->qid].
3792 3791 tfd_offset[IWK_QUEUE_SIZE + ring->cur].val = 8;
3793 3792 }
3794 3793
3795 3794 /* kick cmd ring */
3796 3795 ring->cur = (ring->cur + 1) % ring->count;
3797 3796 IWK_WRITE(sc, HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur);
3798 3797
3799 3798 return (IWK_SUCCESS);
3800 3799 }
3801 3800
3802 3801 static int
3803 3802 iwk_config(iwk_sc_t *sc)
3804 3803 {
3805 3804 ieee80211com_t *ic = &sc->sc_ic;
3806 3805 iwk_powertable_cmd_t powertable;
3807 3806 iwk_bt_cmd_t bt;
3808 3807 iwk_add_sta_t node;
3809 3808 iwk_link_quality_cmd_t link_quality;
3810 3809 int i, err;
3811 3810 uint16_t masks = 0;
3812 3811
3813 3812 /*
3814 3813 * set power mode. Disable power management at present, do it later
3815 3814 */
3816 3815 (void) memset(&powertable, 0, sizeof (powertable));
3817 3816 powertable.flags = LE_16(0x8);
3818 3817 err = iwk_cmd(sc, POWER_TABLE_CMD, &powertable,
3819 3818 sizeof (powertable), 0);
3820 3819 if (err != IWK_SUCCESS) {
3821 3820 cmn_err(CE_WARN, "iwk_config(): failed to set power mode\n");
3822 3821 return (err);
3823 3822 }
3824 3823
3825 3824 /* configure bt coexistence */
3826 3825 (void) memset(&bt, 0, sizeof (bt));
3827 3826 bt.flags = 3;
3828 3827 bt.lead_time = 0xaa;
3829 3828 bt.max_kill = 1;
3830 3829 err = iwk_cmd(sc, REPLY_BT_CONFIG, &bt,
3831 3830 sizeof (bt), 0);
3832 3831 if (err != IWK_SUCCESS) {
3833 3832 cmn_err(CE_WARN,
3834 3833 "iwk_config(): "
3835 3834 "failed to configurate bt coexistence\n");
3836 3835 return (err);
3837 3836 }
3838 3837
3839 3838 /* configure rxon */
3840 3839 (void) memset(&sc->sc_config, 0, sizeof (iwk_rxon_cmd_t));
3841 3840 IEEE80211_ADDR_COPY(sc->sc_config.node_addr, ic->ic_macaddr);
3842 3841 IEEE80211_ADDR_COPY(sc->sc_config.wlap_bssid, ic->ic_macaddr);
3843 3842 sc->sc_config.chan = LE_16(ieee80211_chan2ieee(ic, ic->ic_curchan));
3844 3843 sc->sc_config.flags = LE_32(RXON_FLG_TSF2HOST_MSK |
3845 3844 RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_BAND_24G_MSK);
3846 3845 sc->sc_config.flags &= LE_32(~RXON_FLG_CCK_MSK);
3847 3846 switch (ic->ic_opmode) {
3848 3847 case IEEE80211_M_STA:
3849 3848 sc->sc_config.dev_type = RXON_DEV_TYPE_ESS;
3850 3849 sc->sc_config.filter_flags |= LE_32(RXON_FILTER_ACCEPT_GRP_MSK |
3851 3850 RXON_FILTER_DIS_DECRYPT_MSK |
3852 3851 RXON_FILTER_DIS_GRP_DECRYPT_MSK);
3853 3852 break;
3854 3853 case IEEE80211_M_IBSS:
3855 3854 case IEEE80211_M_AHDEMO:
3856 3855 sc->sc_config.dev_type = RXON_DEV_TYPE_IBSS;
3857 3856 sc->sc_config.flags |= LE_32(RXON_FLG_SHORT_PREAMBLE_MSK);
3858 3857 sc->sc_config.filter_flags = LE_32(RXON_FILTER_ACCEPT_GRP_MSK |
3859 3858 RXON_FILTER_DIS_DECRYPT_MSK |
3860 3859 RXON_FILTER_DIS_GRP_DECRYPT_MSK);
3861 3860 break;
3862 3861 case IEEE80211_M_HOSTAP:
3863 3862 sc->sc_config.dev_type = RXON_DEV_TYPE_AP;
3864 3863 break;
3865 3864 case IEEE80211_M_MONITOR:
3866 3865 sc->sc_config.dev_type = RXON_DEV_TYPE_SNIFFER;
3867 3866 sc->sc_config.filter_flags |= LE_32(RXON_FILTER_ACCEPT_GRP_MSK |
3868 3867 RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_PROMISC_MSK);
3869 3868 break;
3870 3869 }
3871 3870 sc->sc_config.cck_basic_rates = 0x0f;
3872 3871 sc->sc_config.ofdm_basic_rates = 0xff;
3873 3872
3874 3873 sc->sc_config.ofdm_ht_single_stream_basic_rates = 0xff;
3875 3874 sc->sc_config.ofdm_ht_dual_stream_basic_rates = 0xff;
3876 3875
3877 3876 /* set antenna */
3878 3877
3879 3878 sc->sc_config.rx_chain = LE_16(RXON_RX_CHAIN_DRIVER_FORCE_MSK |
3880 3879 (0x7 << RXON_RX_CHAIN_VALID_POS) |
3881 3880 (0x6 << RXON_RX_CHAIN_FORCE_SEL_POS) |
3882 3881 (0x7 << RXON_RX_CHAIN_FORCE_MIMO_SEL_POS));
3883 3882
3884 3883 err = iwk_cmd(sc, REPLY_RXON, &sc->sc_config,
3885 3884 sizeof (iwk_rxon_cmd_t), 0);
3886 3885 if (err != IWK_SUCCESS) {
3887 3886 cmn_err(CE_WARN, "iwk_config(): "
3888 3887 "failed to set configure command\n");
3889 3888 return (err);
3890 3889 }
3891 3890 /* obtain current temperature of chipset */
3892 3891 sc->sc_tempera = iwk_curr_tempera(sc);
3893 3892
3894 3893 /* make Tx power calibration to determine the gains of DSP and radio */
3895 3894 err = iwk_tx_power_calibration(sc);
3896 3895 if (err) {
3897 3896 cmn_err(CE_WARN, "iwk_config(): "
3898 3897 "failed to set tx power table\n");
3899 3898 return (err);
3900 3899 }
3901 3900
3902 3901 /* add broadcast node so that we can send broadcast frame */
3903 3902 (void) memset(&node, 0, sizeof (node));
3904 3903 (void) memset(node.bssid, 0xff, 6);
3905 3904 node.id = IWK_BROADCAST_ID;
3906 3905 err = iwk_cmd(sc, REPLY_ADD_STA, &node, sizeof (node), 0);
3907 3906 if (err != IWK_SUCCESS) {
3908 3907 cmn_err(CE_WARN, "iwk_config(): "
3909 3908 "failed to add broadcast node\n");
3910 3909 return (err);
3911 3910 }
3912 3911
3913 3912 /* TX_LINK_QUALITY cmd ? */
3914 3913 (void) memset(&link_quality, 0, sizeof (link_quality));
3915 3914 for (i = 0; i < LINK_QUAL_MAX_RETRY_NUM; i++) {
3916 3915 masks |= RATE_MCS_CCK_MSK;
3917 3916 masks |= RATE_MCS_ANT_B_MSK;
3918 3917 masks &= ~RATE_MCS_ANT_A_MSK;
3919 3918 link_quality.rate_n_flags[i] =
3920 3919 LE_32(iwk_rate_to_plcp(2) | masks);
3921 3920 }
3922 3921
3923 3922 link_quality.general_params.single_stream_ant_msk = 2;
3924 3923 link_quality.general_params.dual_stream_ant_msk = 3;
3925 3924 link_quality.agg_params.agg_dis_start_th = 3;
3926 3925 link_quality.agg_params.agg_time_limit = LE_16(4000);
3927 3926 link_quality.sta_id = IWK_BROADCAST_ID;
3928 3927 err = iwk_cmd(sc, REPLY_TX_LINK_QUALITY_CMD, &link_quality,
3929 3928 sizeof (link_quality), 0);
3930 3929 if (err != IWK_SUCCESS) {
3931 3930 cmn_err(CE_WARN, "iwk_config(): "
3932 3931 "failed to config link quality table\n");
3933 3932 return (err);
3934 3933 }
3935 3934
3936 3935 return (IWK_SUCCESS);
3937 3936 }
3938 3937
3939 3938 static void
3940 3939 iwk_stop_master(iwk_sc_t *sc)
3941 3940 {
3942 3941 uint32_t tmp;
3943 3942 int n;
3944 3943
3945 3944 tmp = IWK_READ(sc, CSR_RESET);
3946 3945 IWK_WRITE(sc, CSR_RESET, tmp | CSR_RESET_REG_FLAG_STOP_MASTER);
3947 3946
3948 3947 tmp = IWK_READ(sc, CSR_GP_CNTRL);
3949 3948 if ((tmp & CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE) ==
3950 3949 CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE)
3951 3950 return;
3952 3951
3953 3952 for (n = 0; n < 2000; n++) {
3954 3953 if (IWK_READ(sc, CSR_RESET) &
3955 3954 CSR_RESET_REG_FLAG_MASTER_DISABLED)
3956 3955 break;
3957 3956 DELAY(1000);
3958 3957 }
3959 3958 if (n == 2000)
3960 3959 IWK_DBG((IWK_DEBUG_HW,
3961 3960 "timeout waiting for master stop\n"));
3962 3961 }
3963 3962
3964 3963 static int
3965 3964 iwk_power_up(iwk_sc_t *sc)
3966 3965 {
3967 3966 uint32_t tmp;
3968 3967
3969 3968 iwk_mac_access_enter(sc);
3970 3969 tmp = iwk_reg_read(sc, ALM_APMG_PS_CTL);
3971 3970 tmp &= ~APMG_PS_CTRL_REG_MSK_POWER_SRC;
3972 3971 tmp |= APMG_PS_CTRL_REG_VAL_POWER_SRC_VMAIN;
3973 3972 iwk_reg_write(sc, ALM_APMG_PS_CTL, tmp);
3974 3973 iwk_mac_access_exit(sc);
3975 3974
3976 3975 DELAY(5000);
3977 3976 return (IWK_SUCCESS);
3978 3977 }
3979 3978
3980 3979 static int
3981 3980 iwk_preinit(iwk_sc_t *sc)
3982 3981 {
3983 3982 uint32_t tmp;
3984 3983 int n;
3985 3984 uint8_t vlink;
3986 3985
3987 3986 /* clear any pending interrupts */
3988 3987 IWK_WRITE(sc, CSR_INT, 0xffffffff);
3989 3988
3990 3989 tmp = IWK_READ(sc, CSR_GIO_CHICKEN_BITS);
3991 3990 IWK_WRITE(sc, CSR_GIO_CHICKEN_BITS,
3992 3991 tmp | CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
3993 3992
3994 3993 tmp = IWK_READ(sc, CSR_GP_CNTRL);
3995 3994 IWK_WRITE(sc, CSR_GP_CNTRL, tmp | CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
3996 3995
3997 3996 /* wait for clock ready */
3998 3997 for (n = 0; n < 1000; n++) {
3999 3998 if (IWK_READ(sc, CSR_GP_CNTRL) &
4000 3999 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY)
4001 4000 break;
4002 4001 DELAY(10);
4003 4002 }
4004 4003 if (n == 1000) {
4005 4004 cmn_err(CE_WARN,
4006 4005 "iwk_preinit(): timeout waiting for clock ready\n");
4007 4006 return (ETIMEDOUT);
4008 4007 }
4009 4008 iwk_mac_access_enter(sc);
4010 4009 tmp = iwk_reg_read(sc, APMG_CLK_CTRL_REG);
4011 4010 iwk_reg_write(sc, APMG_CLK_CTRL_REG, tmp |
4012 4011 APMG_CLK_REG_VAL_DMA_CLK_RQT | APMG_CLK_REG_VAL_BSM_CLK_RQT);
4013 4012
4014 4013 DELAY(20);
4015 4014 tmp = iwk_reg_read(sc, ALM_APMG_PCIDEV_STT);
4016 4015 iwk_reg_write(sc, ALM_APMG_PCIDEV_STT, tmp |
4017 4016 APMG_DEV_STATE_REG_VAL_L1_ACTIVE_DISABLE);
4018 4017 iwk_mac_access_exit(sc);
4019 4018
4020 4019 IWK_WRITE(sc, CSR_INT_COALESCING, 512 / 32); /* ??? */
4021 4020
4022 4021 (void) iwk_power_up(sc);
4023 4022
4024 4023 if ((sc->sc_rev & 0x80) == 0x80 && (sc->sc_rev & 0x7f) < 8) {
4025 4024 tmp = ddi_get32(sc->sc_cfg_handle,
4026 4025 (uint32_t *)(sc->sc_cfg_base + 0xe8));
4027 4026 ddi_put32(sc->sc_cfg_handle,
4028 4027 (uint32_t *)(sc->sc_cfg_base + 0xe8),
4029 4028 tmp & ~(1 << 11));
4030 4029 }
4031 4030
4032 4031
4033 4032 vlink = ddi_get8(sc->sc_cfg_handle,
4034 4033 (uint8_t *)(sc->sc_cfg_base + 0xf0));
4035 4034 ddi_put8(sc->sc_cfg_handle, (uint8_t *)(sc->sc_cfg_base + 0xf0),
4036 4035 vlink & ~2);
4037 4036
4038 4037 tmp = IWK_READ(sc, CSR_SW_VER);
4039 4038 tmp |= CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
4040 4039 CSR_HW_IF_CONFIG_REG_BIT_MAC_SI |
4041 4040 CSR_HW_IF_CONFIG_REG_BIT_KEDRON_R;
4042 4041 IWK_WRITE(sc, CSR_SW_VER, tmp);
4043 4042
4044 4043 /* make sure power supply on each part of the hardware */
4045 4044 iwk_mac_access_enter(sc);
4046 4045 tmp = iwk_reg_read(sc, ALM_APMG_PS_CTL);
4047 4046 tmp |= APMG_PS_CTRL_REG_VAL_ALM_R_RESET_REQ;
4048 4047 iwk_reg_write(sc, ALM_APMG_PS_CTL, tmp);
4049 4048 DELAY(5);
4050 4049 tmp = iwk_reg_read(sc, ALM_APMG_PS_CTL);
4051 4050 tmp &= ~APMG_PS_CTRL_REG_VAL_ALM_R_RESET_REQ;
4052 4051 iwk_reg_write(sc, ALM_APMG_PS_CTL, tmp);
4053 4052 iwk_mac_access_exit(sc);
4054 4053 return (IWK_SUCCESS);
4055 4054 }
4056 4055
4057 4056 /*
4058 4057 * set up semphore flag to own EEPROM
4059 4058 */
4060 4059 static int iwk_eep_sem_down(iwk_sc_t *sc)
4061 4060 {
4062 4061 int count1, count2;
4063 4062 uint32_t tmp;
4064 4063
4065 4064 for (count1 = 0; count1 < 1000; count1++) {
4066 4065 tmp = IWK_READ(sc, CSR_HW_IF_CONFIG_REG);
4067 4066 IWK_WRITE(sc, CSR_HW_IF_CONFIG_REG,
4068 4067 tmp | CSR_HW_IF_CONFIG_REG_EEP_SEM);
4069 4068
4070 4069 for (count2 = 0; count2 < 2; count2++) {
4071 4070 if (IWK_READ(sc, CSR_HW_IF_CONFIG_REG) &
4072 4071 CSR_HW_IF_CONFIG_REG_EEP_SEM)
4073 4072 return (IWK_SUCCESS);
4074 4073 DELAY(10000);
4075 4074 }
4076 4075 }
4077 4076 return (IWK_FAIL);
4078 4077 }
4079 4078
4080 4079 /*
4081 4080 * reset semphore flag to release EEPROM
4082 4081 */
4083 4082 static void iwk_eep_sem_up(iwk_sc_t *sc)
4084 4083 {
4085 4084 uint32_t tmp;
4086 4085
4087 4086 tmp = IWK_READ(sc, CSR_HW_IF_CONFIG_REG);
4088 4087 IWK_WRITE(sc, CSR_HW_IF_CONFIG_REG,
4089 4088 tmp & (~CSR_HW_IF_CONFIG_REG_EEP_SEM));
4090 4089 }
4091 4090
4092 4091 /*
4093 4092 * This function load all infomation in eeprom into iwk_eep
4094 4093 * structure in iwk_sc_t structure
4095 4094 */
4096 4095 static int iwk_eep_load(iwk_sc_t *sc)
4097 4096 {
4098 4097 int i, rr;
4099 4098 uint32_t rv, tmp, eep_gp;
4100 4099 uint16_t addr, eep_sz = sizeof (sc->sc_eep_map);
4101 4100 uint16_t *eep_p = (uint16_t *)&sc->sc_eep_map;
4102 4101
4103 4102 /* read eeprom gp register in CSR */
4104 4103 eep_gp = IWK_READ(sc, CSR_EEPROM_GP);
4105 4104 if ((eep_gp & CSR_EEPROM_GP_VALID_MSK) ==
4106 4105 CSR_EEPROM_GP_BAD_SIGNATURE) {
4107 4106 cmn_err(CE_WARN, "EEPROM not found\n");
4108 4107 return (IWK_FAIL);
4109 4108 }
4110 4109
4111 4110 rr = iwk_eep_sem_down(sc);
4112 4111 if (rr != 0) {
4113 4112 cmn_err(CE_WARN, "failed to own EEPROM\n");
4114 4113 return (IWK_FAIL);
4115 4114 }
4116 4115
4117 4116 for (addr = 0; addr < eep_sz; addr += 2) {
4118 4117 IWK_WRITE(sc, CSR_EEPROM_REG, addr<<1);
4119 4118 tmp = IWK_READ(sc, CSR_EEPROM_REG);
4120 4119 IWK_WRITE(sc, CSR_EEPROM_REG, tmp & ~(0x2));
4121 4120
4122 4121 for (i = 0; i < 10; i++) {
4123 4122 rv = IWK_READ(sc, CSR_EEPROM_REG);
4124 4123 if (rv & 1)
4125 4124 break;
4126 4125 DELAY(10);
4127 4126 }
4128 4127
4129 4128 if (!(rv & 1)) {
4130 4129 cmn_err(CE_WARN, "time out when read EEPROM\n");
4131 4130 iwk_eep_sem_up(sc);
4132 4131 return (IWK_FAIL);
4133 4132 }
4134 4133
4135 4134 eep_p[addr/2] = LE_16(rv >> 16);
4136 4135 }
4137 4136
4138 4137 iwk_eep_sem_up(sc);
4139 4138 return (IWK_SUCCESS);
4140 4139 }
4141 4140
4142 4141 /*
4143 4142 * init mac address in ieee80211com_t struct
4144 4143 */
4145 4144 static void iwk_get_mac_from_eep(iwk_sc_t *sc)
4146 4145 {
4147 4146 ieee80211com_t *ic = &sc->sc_ic;
4148 4147 struct iwk_eep *ep = &sc->sc_eep_map;
4149 4148
4150 4149 IEEE80211_ADDR_COPY(ic->ic_macaddr, ep->mac_address);
4151 4150
4152 4151 IWK_DBG((IWK_DEBUG_EEPROM, "mac:%2x:%2x:%2x:%2x:%2x:%2x\n",
4153 4152 ic->ic_macaddr[0], ic->ic_macaddr[1], ic->ic_macaddr[2],
4154 4153 ic->ic_macaddr[3], ic->ic_macaddr[4], ic->ic_macaddr[5]));
4155 4154 }
4156 4155
4157 4156 static int
4158 4157 iwk_init(iwk_sc_t *sc)
4159 4158 {
4160 4159 int qid, n, err;
4161 4160 clock_t clk;
4162 4161 uint32_t tmp;
4163 4162
4164 4163 mutex_enter(&sc->sc_glock);
4165 4164 sc->sc_flags &= ~IWK_F_FW_INIT;
4166 4165
4167 4166 (void) iwk_preinit(sc);
4168 4167
4169 4168 tmp = IWK_READ(sc, CSR_GP_CNTRL);
4170 4169 if (!(tmp & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)) {
4171 4170 cmn_err(CE_NOTE, "iwk_init(): Radio transmitter is off\n");
4172 4171 goto fail1;
4173 4172 }
4174 4173
4175 4174 /* init Rx ring */
4176 4175 iwk_mac_access_enter(sc);
4177 4176 IWK_WRITE(sc, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
4178 4177
4179 4178 IWK_WRITE(sc, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
4180 4179 IWK_WRITE(sc, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
4181 4180 sc->sc_rxq.dma_desc.cookie.dmac_address >> 8);
4182 4181
4183 4182 IWK_WRITE(sc, FH_RSCSR_CHNL0_STTS_WPTR_REG,
4184 4183 ((uint32_t)(sc->sc_dma_sh.cookie.dmac_address +
4185 4184 offsetof(struct iwk_shared, val0)) >> 4));
4186 4185
4187 4186 IWK_WRITE(sc, FH_MEM_RCSR_CHNL0_CONFIG_REG,
4188 4187 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
4189 4188 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
4190 4189 IWK_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K |
4191 4190 (RX_QUEUE_SIZE_LOG <<
4192 4191 FH_RCSR_RX_CONFIG_RBDCB_SIZE_BITSHIFT));
4193 4192 iwk_mac_access_exit(sc);
4194 4193 IWK_WRITE(sc, FH_RSCSR_CHNL0_RBDCB_WPTR_REG,
4195 4194 (RX_QUEUE_SIZE - 1) & ~0x7);
4196 4195
4197 4196 /* init Tx rings */
4198 4197 iwk_mac_access_enter(sc);
4199 4198 iwk_reg_write(sc, SCD_TXFACT, 0);
4200 4199
4201 4200 /* keep warm page */
4202 4201 iwk_reg_write(sc, IWK_FH_KW_MEM_ADDR_REG,
4203 4202 sc->sc_dma_kw.cookie.dmac_address >> 4);
4204 4203
4205 4204 for (qid = 0; qid < IWK_NUM_QUEUES; qid++) {
4206 4205 IWK_WRITE(sc, FH_MEM_CBBC_QUEUE(qid),
4207 4206 sc->sc_txq[qid].dma_desc.cookie.dmac_address >> 8);
4208 4207 IWK_WRITE(sc, IWK_FH_TCSR_CHNL_TX_CONFIG_REG(qid),
4209 4208 IWK_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
4210 4209 IWK_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL);
4211 4210 }
4212 4211 iwk_mac_access_exit(sc);
4213 4212
4214 4213 /* clear "radio off" and "disable command" bits */
4215 4214 IWK_WRITE(sc, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
4216 4215 IWK_WRITE(sc, CSR_UCODE_DRV_GP1_CLR,
4217 4216 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
4218 4217
4219 4218 /* clear any pending interrupts */
4220 4219 IWK_WRITE(sc, CSR_INT, 0xffffffff);
4221 4220
4222 4221 /* enable interrupts */
4223 4222 IWK_WRITE(sc, CSR_INT_MASK, CSR_INI_SET_MASK);
4224 4223
4225 4224 IWK_WRITE(sc, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
4226 4225 IWK_WRITE(sc, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
4227 4226
4228 4227 /*
4229 4228 * backup ucode data part for future use.
4230 4229 */
4231 4230 (void) memcpy(sc->sc_dma_fw_data_bak.mem_va,
4232 4231 sc->sc_dma_fw_data.mem_va,
4233 4232 sc->sc_dma_fw_data.alength);
4234 4233
4235 4234 for (n = 0; n < 2; n++) {
4236 4235 /* load firmware init segment into NIC */
4237 4236 err = iwk_load_firmware(sc);
4238 4237 if (err != IWK_SUCCESS) {
4239 4238 cmn_err(CE_WARN, "iwk_init(): "
4240 4239 "failed to setup boot firmware\n");
4241 4240 continue;
4242 4241 }
4243 4242
4244 4243 /* now press "execute" start running */
4245 4244 IWK_WRITE(sc, CSR_RESET, 0);
4246 4245 break;
4247 4246 }
4248 4247 if (n == 2) {
4249 4248 cmn_err(CE_WARN, "iwk_init(): failed to load firmware\n");
4250 4249 goto fail1;
4251 4250 }
4252 4251 /* ..and wait at most one second for adapter to initialize */
4253 4252 clk = ddi_get_lbolt() + drv_usectohz(2000000);
4254 4253 while (!(sc->sc_flags & IWK_F_FW_INIT)) {
4255 4254 if (cv_timedwait(&sc->sc_fw_cv, &sc->sc_glock, clk) < 0)
4256 4255 break;
4257 4256 }
4258 4257 if (!(sc->sc_flags & IWK_F_FW_INIT)) {
4259 4258 cmn_err(CE_WARN,
4260 4259 "iwk_init(): timeout waiting for firmware init\n");
4261 4260 goto fail1;
4262 4261 }
4263 4262
4264 4263 /*
4265 4264 * at this point, the firmware is loaded OK, then config the hardware
4266 4265 * with the ucode API, including rxon, txpower, etc.
4267 4266 */
4268 4267 err = iwk_config(sc);
4269 4268 if (err) {
4270 4269 cmn_err(CE_WARN, "iwk_init(): failed to configure device\n");
4271 4270 goto fail1;
4272 4271 }
4273 4272
4274 4273 /* at this point, hardware may receive beacons :) */
4275 4274 mutex_exit(&sc->sc_glock);
4276 4275 return (IWK_SUCCESS);
4277 4276
4278 4277 fail1:
4279 4278 err = IWK_FAIL;
4280 4279 mutex_exit(&sc->sc_glock);
4281 4280 return (err);
4282 4281 }
4283 4282
4284 4283 static void
4285 4284 iwk_stop(iwk_sc_t *sc)
4286 4285 {
4287 4286 uint32_t tmp;
4288 4287 int i;
4289 4288
4290 4289 if (!(sc->sc_flags & IWK_F_QUIESCED))
4291 4290 mutex_enter(&sc->sc_glock);
4292 4291
4293 4292 IWK_WRITE(sc, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
4294 4293 /* disable interrupts */
4295 4294 IWK_WRITE(sc, CSR_INT_MASK, 0);
4296 4295 IWK_WRITE(sc, CSR_INT, CSR_INI_SET_MASK);
4297 4296 IWK_WRITE(sc, CSR_FH_INT_STATUS, 0xffffffff);
4298 4297
4299 4298 /* reset all Tx rings */
4300 4299 for (i = 0; i < IWK_NUM_QUEUES; i++)
4301 4300 iwk_reset_tx_ring(sc, &sc->sc_txq[i]);
4302 4301
4303 4302 /* reset Rx ring */
4304 4303 iwk_reset_rx_ring(sc);
4305 4304
4306 4305 iwk_mac_access_enter(sc);
4307 4306 iwk_reg_write(sc, ALM_APMG_CLK_DIS, APMG_CLK_REG_VAL_DMA_CLK_RQT);
4308 4307 iwk_mac_access_exit(sc);
4309 4308
4310 4309 DELAY(5);
4311 4310
4312 4311 iwk_stop_master(sc);
4313 4312
4314 4313 sc->sc_tx_timer = 0;
4315 4314 sc->sc_flags &= ~IWK_F_SCANNING;
4316 4315 sc->sc_scan_pending = 0;
4317 4316
4318 4317 tmp = IWK_READ(sc, CSR_RESET);
4319 4318 IWK_WRITE(sc, CSR_RESET, tmp | CSR_RESET_REG_FLAG_SW_RESET);
4320 4319
4321 4320 if (!(sc->sc_flags & IWK_F_QUIESCED))
4322 4321 mutex_exit(&sc->sc_glock);
4323 4322 }
4324 4323
4325 4324 /*
4326 4325 * Naive implementation of the Adaptive Multi Rate Retry algorithm:
4327 4326 * "IEEE 802.11 Rate Adaptation: A Practical Approach"
4328 4327 * Mathieu Lacage, Hossein Manshaei, Thierry Turletti
4329 4328 * INRIA Sophia - Projet Planete
4330 4329 * http://www-sop.inria.fr/rapports/sophia/RR-5208.html
4331 4330 */
4332 4331 #define is_success(amrr) \
4333 4332 ((amrr)->retrycnt < (amrr)->txcnt / 10)
4334 4333 #define is_failure(amrr) \
4335 4334 ((amrr)->retrycnt > (amrr)->txcnt / 3)
4336 4335 #define is_enough(amrr) \
4337 4336 ((amrr)->txcnt > 100)
4338 4337 #define is_min_rate(in) \
4339 4338 ((in)->in_txrate == 0)
4340 4339 #define is_max_rate(in) \
4341 4340 ((in)->in_txrate == (in)->in_rates.ir_nrates - 1)
4342 4341 #define increase_rate(in) \
4343 4342 ((in)->in_txrate++)
4344 4343 #define decrease_rate(in) \
4345 4344 ((in)->in_txrate--)
4346 4345 #define reset_cnt(amrr) \
4347 4346 { (amrr)->txcnt = (amrr)->retrycnt = 0; }
4348 4347
4349 4348 #define IWK_AMRR_MIN_SUCCESS_THRESHOLD 1
4350 4349 #define IWK_AMRR_MAX_SUCCESS_THRESHOLD 15
4351 4350
4352 4351 static void
4353 4352 iwk_amrr_init(iwk_amrr_t *amrr)
4354 4353 {
4355 4354 amrr->success = 0;
4356 4355 amrr->recovery = 0;
4357 4356 amrr->txcnt = amrr->retrycnt = 0;
4358 4357 amrr->success_threshold = IWK_AMRR_MIN_SUCCESS_THRESHOLD;
4359 4358 }
4360 4359
4361 4360 static void
4362 4361 iwk_amrr_timeout(iwk_sc_t *sc)
4363 4362 {
4364 4363 ieee80211com_t *ic = &sc->sc_ic;
4365 4364
4366 4365 IWK_DBG((IWK_DEBUG_RATECTL, "iwk_amrr_timeout() enter\n"));
4367 4366 if (ic->ic_opmode == IEEE80211_M_STA)
4368 4367 iwk_amrr_ratectl(NULL, ic->ic_bss);
4369 4368 else
4370 4369 ieee80211_iterate_nodes(&ic->ic_sta, iwk_amrr_ratectl, NULL);
4371 4370 sc->sc_clk = ddi_get_lbolt();
4372 4371 }
4373 4372
4374 4373 /* ARGSUSED */
4375 4374 static void
4376 4375 iwk_amrr_ratectl(void *arg, ieee80211_node_t *in)
4377 4376 {
4378 4377 iwk_amrr_t *amrr = (iwk_amrr_t *)in;
4379 4378 int need_change = 0;
4380 4379
4381 4380 if (is_success(amrr) && is_enough(amrr)) {
4382 4381 amrr->success++;
4383 4382 if (amrr->success >= amrr->success_threshold &&
4384 4383 !is_max_rate(in)) {
4385 4384 amrr->recovery = 1;
4386 4385 amrr->success = 0;
4387 4386 increase_rate(in);
4388 4387 IWK_DBG((IWK_DEBUG_RATECTL,
4389 4388 "AMRR increasing rate %d (txcnt=%d retrycnt=%d)\n",
4390 4389 in->in_txrate, amrr->txcnt, amrr->retrycnt));
4391 4390 need_change = 1;
4392 4391 } else {
4393 4392 amrr->recovery = 0;
4394 4393 }
4395 4394 } else if (is_failure(amrr)) {
4396 4395 amrr->success = 0;
4397 4396 if (!is_min_rate(in)) {
4398 4397 if (amrr->recovery) {
4399 4398 amrr->success_threshold++;
4400 4399 if (amrr->success_threshold >
4401 4400 IWK_AMRR_MAX_SUCCESS_THRESHOLD)
4402 4401 amrr->success_threshold =
4403 4402 IWK_AMRR_MAX_SUCCESS_THRESHOLD;
4404 4403 } else {
4405 4404 amrr->success_threshold =
4406 4405 IWK_AMRR_MIN_SUCCESS_THRESHOLD;
4407 4406 }
4408 4407 decrease_rate(in);
4409 4408 IWK_DBG((IWK_DEBUG_RATECTL,
4410 4409 "AMRR decreasing rate %d (txcnt=%d retrycnt=%d)\n",
4411 4410 in->in_txrate, amrr->txcnt, amrr->retrycnt));
4412 4411 need_change = 1;
4413 4412 }
4414 4413 amrr->recovery = 0; /* paper is incorrect */
4415 4414 }
4416 4415
4417 4416 if (is_enough(amrr) || need_change)
4418 4417 reset_cnt(amrr);
4419 4418 }
4420 4419
4421 4420 /*
4422 4421 * calculate 4965 chipset's kelvin temperature according to
4423 4422 * the data of init alive and satistics notification.
4424 4423 * The details is described in iwk_calibration.h file
4425 4424 */
4426 4425 static int32_t iwk_curr_tempera(iwk_sc_t *sc)
4427 4426 {
4428 4427 int32_t tempera;
4429 4428 int32_t r1, r2, r3;
4430 4429 uint32_t r4_u;
4431 4430 int32_t r4_s;
4432 4431
4433 4432 if (iwk_is_fat_channel(sc)) {
4434 4433 r1 = (int32_t)LE_32(sc->sc_card_alive_init.therm_r1[1]);
4435 4434 r2 = (int32_t)LE_32(sc->sc_card_alive_init.therm_r2[1]);
4436 4435 r3 = (int32_t)LE_32(sc->sc_card_alive_init.therm_r3[1]);
4437 4436 r4_u = LE_32(sc->sc_card_alive_init.therm_r4[1]);
4438 4437 } else {
4439 4438 r1 = (int32_t)LE_32(sc->sc_card_alive_init.therm_r1[0]);
4440 4439 r2 = (int32_t)LE_32(sc->sc_card_alive_init.therm_r2[0]);
4441 4440 r3 = (int32_t)LE_32(sc->sc_card_alive_init.therm_r3[0]);
4442 4441 r4_u = LE_32(sc->sc_card_alive_init.therm_r4[0]);
4443 4442 }
4444 4443
4445 4444 if (sc->sc_flags & IWK_F_STATISTICS) {
4446 4445 r4_s = (int32_t)(LE_32(sc->sc_statistics.general.temperature) <<
4447 4446 (31-23)) >> (31-23);
4448 4447 } else {
4449 4448 r4_s = (int32_t)(r4_u << (31-23)) >> (31-23);
4450 4449 }
4451 4450
4452 4451 IWK_DBG((IWK_DEBUG_CALIBRATION, "temperature R[1-4]: %d %d %d %d\n",
4453 4452 r1, r2, r3, r4_s));
4454 4453
4455 4454 if (r3 == r1) {
4456 4455 cmn_err(CE_WARN, "iwk_curr_tempera(): "
4457 4456 "failed to calculate temperature"
4458 4457 "because r3 = r1\n");
4459 4458 return (DDI_FAILURE);
4460 4459 }
4461 4460
4462 4461 tempera = TEMPERATURE_CALIB_A_VAL * (r4_s - r2);
4463 4462 tempera /= (r3 - r1);
4464 4463 tempera = (tempera*97) / 100 + TEMPERATURE_CALIB_KELVIN_OFFSET;
4465 4464
4466 4465 IWK_DBG((IWK_DEBUG_CALIBRATION, "calculated temperature: %dK, %dC\n",
4467 4466 tempera, KELVIN_TO_CELSIUS(tempera)));
4468 4467
4469 4468 return (tempera);
4470 4469 }
4471 4470
4472 4471 /* Determine whether 4965 is using 2.4 GHz band */
4473 4472 static inline int iwk_is_24G_band(iwk_sc_t *sc)
4474 4473 {
4475 4474 return (LE_32(sc->sc_config.flags) & RXON_FLG_BAND_24G_MSK);
4476 4475 }
4477 4476
4478 4477 /* Determine whether 4965 is using fat channel */
4479 4478 static inline int iwk_is_fat_channel(iwk_sc_t *sc)
4480 4479 {
4481 4480 return ((LE_32(sc->sc_config.flags) &
4482 4481 RXON_FLG_CHANNEL_MODE_PURE_40_MSK) ||
4483 4482 (LE_32(sc->sc_config.flags) & RXON_FLG_CHANNEL_MODE_MIXED_MSK));
4484 4483 }
4485 4484
4486 4485 /*
4487 4486 * In MIMO mode, determine which group 4965's current channel belong to.
4488 4487 * For more infomation about "channel group",
4489 4488 * please refer to iwk_calibration.h file
4490 4489 */
4491 4490 static int iwk_txpower_grp(uint16_t channel)
4492 4491 {
4493 4492 if (channel >= CALIB_IWK_TX_ATTEN_GR5_FCH &&
4494 4493 channel <= CALIB_IWK_TX_ATTEN_GR5_LCH) {
4495 4494 return (CALIB_CH_GROUP_5);
4496 4495 }
4497 4496
4498 4497 if (channel >= CALIB_IWK_TX_ATTEN_GR1_FCH &&
4499 4498 channel <= CALIB_IWK_TX_ATTEN_GR1_LCH) {
4500 4499 return (CALIB_CH_GROUP_1);
4501 4500 }
4502 4501
4503 4502 if (channel >= CALIB_IWK_TX_ATTEN_GR2_FCH &&
4504 4503 channel <= CALIB_IWK_TX_ATTEN_GR2_LCH) {
4505 4504 return (CALIB_CH_GROUP_2);
4506 4505 }
4507 4506
4508 4507 if (channel >= CALIB_IWK_TX_ATTEN_GR3_FCH &&
4509 4508 channel <= CALIB_IWK_TX_ATTEN_GR3_LCH) {
4510 4509 return (CALIB_CH_GROUP_3);
4511 4510 }
4512 4511
4513 4512 if (channel >= CALIB_IWK_TX_ATTEN_GR4_FCH &&
4514 4513 channel <= CALIB_IWK_TX_ATTEN_GR4_LCH) {
4515 4514 return (CALIB_CH_GROUP_4);
4516 4515 }
4517 4516
4518 4517 cmn_err(CE_WARN, "iwk_txpower_grp(): "
4519 4518 "can't find txpower group for channel %d.\n", channel);
4520 4519
4521 4520 return (DDI_FAILURE);
4522 4521 }
4523 4522
4524 4523 /* 2.4 GHz */
4525 4524 static uint16_t iwk_eep_band_1[14] = {
4526 4525 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
4527 4526 };
4528 4527
4529 4528 /* 5.2 GHz bands */
4530 4529 static uint16_t iwk_eep_band_2[13] = {
4531 4530 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16
4532 4531 };
4533 4532
4534 4533 static uint16_t iwk_eep_band_3[12] = {
4535 4534 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
4536 4535 };
4537 4536
4538 4537 static uint16_t iwk_eep_band_4[11] = {
4539 4538 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
4540 4539 };
4541 4540
4542 4541 static uint16_t iwk_eep_band_5[6] = {
4543 4542 145, 149, 153, 157, 161, 165
4544 4543 };
4545 4544
4546 4545 static uint16_t iwk_eep_band_6[7] = {
4547 4546 1, 2, 3, 4, 5, 6, 7
4548 4547 };
4549 4548
4550 4549 static uint16_t iwk_eep_band_7[11] = {
4551 4550 36, 44, 52, 60, 100, 108, 116, 124, 132, 149, 157
4552 4551 };
4553 4552
4554 4553 /* Get regulatory data from eeprom for a given channel */
4555 4554 static struct iwk_eep_channel *iwk_get_eep_channel(iwk_sc_t *sc,
4556 4555 uint16_t channel,
4557 4556 int is_24G, int is_fat, int is_hi_chan)
4558 4557 {
4559 4558 int32_t i;
4560 4559 uint16_t chan;
4561 4560
4562 4561 if (is_fat) { /* 11n mode */
4563 4562
4564 4563 if (is_hi_chan) {
4565 4564 chan = channel - 4;
4566 4565 } else {
4567 4566 chan = channel;
4568 4567 }
4569 4568
4570 4569 for (i = 0; i < 7; i++) {
4571 4570 if (iwk_eep_band_6[i] == chan) {
4572 4571 return (&sc->sc_eep_map.band_24_channels[i]);
4573 4572 }
4574 4573 }
4575 4574 for (i = 0; i < 11; i++) {
4576 4575 if (iwk_eep_band_7[i] == chan) {
4577 4576 return (&sc->sc_eep_map.band_52_channels[i]);
4578 4577 }
4579 4578 }
4580 4579 } else if (is_24G) { /* 2.4 GHz band */
4581 4580 for (i = 0; i < 14; i++) {
4582 4581 if (iwk_eep_band_1[i] == channel) {
4583 4582 return (&sc->sc_eep_map.band_1_channels[i]);
4584 4583 }
4585 4584 }
4586 4585 } else { /* 5 GHz band */
4587 4586 for (i = 0; i < 13; i++) {
4588 4587 if (iwk_eep_band_2[i] == channel) {
4589 4588 return (&sc->sc_eep_map.band_2_channels[i]);
4590 4589 }
4591 4590 }
4592 4591 for (i = 0; i < 12; i++) {
4593 4592 if (iwk_eep_band_3[i] == channel) {
4594 4593 return (&sc->sc_eep_map.band_3_channels[i]);
4595 4594 }
4596 4595 }
4597 4596 for (i = 0; i < 11; i++) {
4598 4597 if (iwk_eep_band_4[i] == channel) {
4599 4598 return (&sc->sc_eep_map.band_4_channels[i]);
4600 4599 }
4601 4600 }
4602 4601 for (i = 0; i < 6; i++) {
4603 4602 if (iwk_eep_band_5[i] == channel) {
4604 4603 return (&sc->sc_eep_map.band_5_channels[i]);
4605 4604 }
4606 4605 }
4607 4606 }
4608 4607
4609 4608 return (NULL);
4610 4609 }
4611 4610
4612 4611 /*
4613 4612 * Determine which subband a given channel belongs
4614 4613 * to in 2.4 GHz or 5 GHz band
4615 4614 */
4616 4615 static int32_t iwk_band_number(iwk_sc_t *sc, uint16_t channel)
4617 4616 {
4618 4617 int32_t b_n = -1;
4619 4618
4620 4619 for (b_n = 0; b_n < EEP_TX_POWER_BANDS; b_n++) {
4621 4620 if (0 == sc->sc_eep_map.calib_info.band_info_tbl[b_n].ch_from) {
4622 4621 continue;
4623 4622 }
4624 4623
4625 4624 if ((channel >=
4626 4625 (uint16_t)sc->sc_eep_map.calib_info.
4627 4626 band_info_tbl[b_n].ch_from) &&
4628 4627 (channel <=
4629 4628 (uint16_t)sc->sc_eep_map.calib_info.
4630 4629 band_info_tbl[b_n].ch_to)) {
4631 4630 break;
4632 4631 }
4633 4632 }
4634 4633
4635 4634 return (b_n);
4636 4635 }
4637 4636
4638 4637 /* Make a special division for interpolation operation */
4639 4638 static int iwk_division(int32_t num, int32_t denom, int32_t *res)
4640 4639 {
4641 4640 int32_t sign = 1;
4642 4641
4643 4642 if (num < 0) {
4644 4643 sign = -sign;
4645 4644 num = -num;
4646 4645 }
4647 4646
4648 4647 if (denom < 0) {
4649 4648 sign = -sign;
4650 4649 denom = -denom;
4651 4650 }
4652 4651
4653 4652 *res = ((num*2 + denom) / (denom*2)) * sign;
4654 4653
4655 4654 return (IWK_SUCCESS);
4656 4655 }
4657 4656
4658 4657 /* Make interpolation operation */
4659 4658 static int32_t iwk_interpolate_value(int32_t x, int32_t x1, int32_t y1,
4660 4659 int32_t x2, int32_t y2)
4661 4660 {
4662 4661 int32_t val;
4663 4662
4664 4663 if (x2 == x1) {
4665 4664 return (y1);
4666 4665 } else {
4667 4666 (void) iwk_division((x2-x)*(y1-y2), (x2-x1), &val);
4668 4667 return (val + y2);
4669 4668 }
4670 4669 }
4671 4670
4672 4671 /* Get interpolation measurement data of a given channel for all chains. */
4673 4672 static int iwk_channel_interpolate(iwk_sc_t *sc, uint16_t channel,
4674 4673 struct iwk_eep_calib_channel_info *chan_info)
4675 4674 {
4676 4675 int32_t ban_n;
4677 4676 uint32_t ch1_n, ch2_n;
4678 4677 int32_t c, m;
4679 4678 struct iwk_eep_calib_measure *m1_p, *m2_p, *m_p;
4680 4679
4681 4680 /* determine subband number */
4682 4681 ban_n = iwk_band_number(sc, channel);
4683 4682 if (ban_n >= EEP_TX_POWER_BANDS) {
4684 4683 return (DDI_FAILURE);
4685 4684 }
4686 4685
4687 4686 ch1_n =
4688 4687 (uint32_t)sc->sc_eep_map.calib_info.band_info_tbl[ban_n].ch1.ch_num;
4689 4688 ch2_n =
4690 4689 (uint32_t)sc->sc_eep_map.calib_info.band_info_tbl[ban_n].ch2.ch_num;
4691 4690
4692 4691 chan_info->ch_num = (uint8_t)channel; /* given channel number */
4693 4692
4694 4693 /*
4695 4694 * go through all chains on chipset
4696 4695 */
4697 4696 for (c = 0; c < EEP_TX_POWER_TX_CHAINS; c++) {
4698 4697 /*
4699 4698 * go through all factory measurements
4700 4699 */
4701 4700 for (m = 0; m < EEP_TX_POWER_MEASUREMENTS; m++) {
4702 4701 m1_p =
4703 4702 &(sc->sc_eep_map.calib_info.
4704 4703 band_info_tbl[ban_n].ch1.measure[c][m]);
4705 4704 m2_p =
4706 4705 &(sc->sc_eep_map.calib_info.band_info_tbl[ban_n].
4707 4706 ch2.measure[c][m]);
4708 4707 m_p = &(chan_info->measure[c][m]);
4709 4708
4710 4709 /*
4711 4710 * make interpolation to get actual
4712 4711 * Tx power for given channel
4713 4712 */
4714 4713 m_p->actual_pow = iwk_interpolate_value(channel,
4715 4714 ch1_n, m1_p->actual_pow,
4716 4715 ch2_n, m2_p->actual_pow);
4717 4716
4718 4717 /* make interpolation to get index into gain table */
4719 4718 m_p->gain_idx = iwk_interpolate_value(channel,
4720 4719 ch1_n, m1_p->gain_idx,
4721 4720 ch2_n, m2_p->gain_idx);
4722 4721
4723 4722 /* make interpolation to get chipset temperature */
4724 4723 m_p->temperature = iwk_interpolate_value(channel,
4725 4724 ch1_n, m1_p->temperature,
4726 4725 ch2_n, m2_p->temperature);
4727 4726
4728 4727 /*
4729 4728 * make interpolation to get power
4730 4729 * amp detector level
4731 4730 */
4732 4731 m_p->pa_det = iwk_interpolate_value(channel, ch1_n,
4733 4732 m1_p->pa_det,
4734 4733 ch2_n, m2_p->pa_det);
4735 4734 }
4736 4735 }
4737 4736
4738 4737 return (IWK_SUCCESS);
4739 4738 }
4740 4739
4741 4740 /*
4742 4741 * Calculate voltage compensation for Tx power. For more infomation,
4743 4742 * please refer to iwk_calibration.h file
4744 4743 */
4745 4744 static int32_t iwk_voltage_compensation(int32_t eep_voltage,
4746 4745 int32_t curr_voltage)
4747 4746 {
4748 4747 int32_t vol_comp = 0;
4749 4748
4750 4749 if ((TX_POWER_IWK_ILLEGAL_VOLTAGE == eep_voltage) ||
4751 4750 (TX_POWER_IWK_ILLEGAL_VOLTAGE == curr_voltage)) {
4752 4751 return (vol_comp);
4753 4752 }
4754 4753
4755 4754 (void) iwk_division(curr_voltage-eep_voltage,
4756 4755 TX_POWER_IWK_VOLTAGE_CODES_PER_03V, &vol_comp);
4757 4756
4758 4757 if (curr_voltage > eep_voltage) {
4759 4758 vol_comp *= 2;
4760 4759 }
4761 4760 if ((vol_comp < -2) || (vol_comp > 2)) {
4762 4761 vol_comp = 0;
4763 4762 }
4764 4763
4765 4764 return (vol_comp);
4766 4765 }
4767 4766
4768 4767 /*
4769 4768 * Thermal compensation values for txpower for various frequency ranges ...
4770 4769 * ratios from 3:1 to 4.5:1 of degrees (Celsius) per half-dB gain adjust
4771 4770 */
4772 4771 static struct iwk_txpower_tempera_comp {
4773 4772 int32_t degrees_per_05db_a;
4774 4773 int32_t degrees_per_05db_a_denom;
4775 4774 } txpower_tempera_comp_table[CALIB_CH_GROUP_MAX] = {
4776 4775 {9, 2}, /* group 0 5.2, ch 34-43 */
4777 4776 {4, 1}, /* group 1 5.2, ch 44-70 */
4778 4777 {4, 1}, /* group 2 5.2, ch 71-124 */
4779 4778 {4, 1}, /* group 3 5.2, ch 125-200 */
4780 4779 {3, 1} /* group 4 2.4, ch all */
4781 4780 };
4782 4781
4783 4782 /*
4784 4783 * bit-rate-dependent table to prevent Tx distortion, in half-dB units,
4785 4784 * for OFDM 6, 12, 18, 24, 36, 48, 54, 60 MBit, and CCK all rates.
4786 4785 */
4787 4786 static int32_t back_off_table[] = {
4788 4787 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 20 MHz */
4789 4788 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 20 MHz */
4790 4789 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 40 MHz */
4791 4790 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 40 MHz */
4792 4791 10 /* CCK */
4793 4792 };
4794 4793
4795 4794 /* determine minimum Tx power index in gain table */
4796 4795 static int32_t iwk_min_power_index(int32_t rate_pow_idx, int32_t is_24G)
4797 4796 {
4798 4797 if ((!is_24G) && ((rate_pow_idx & 7) <= 4)) {
4799 4798 return (MIN_TX_GAIN_INDEX_52GHZ_EXT);
4800 4799 }
4801 4800
4802 4801 return (MIN_TX_GAIN_INDEX);
4803 4802 }
4804 4803
4805 4804 /*
4806 4805 * Determine DSP and radio gain according to temperature and other factors.
4807 4806 * This function is the majority of Tx power calibration
4808 4807 */
4809 4808 static int iwk_txpower_table_cmd_init(iwk_sc_t *sc,
4810 4809 struct iwk_tx_power_db *tp_db)
4811 4810 {
4812 4811 int is_24G, is_fat, is_high_chan, is_mimo;
4813 4812 int c, r;
4814 4813 int32_t target_power;
4815 4814 int32_t tx_grp = CALIB_CH_GROUP_MAX;
4816 4815 uint16_t channel;
4817 4816 uint8_t saturation_power;
4818 4817 int32_t regu_power;
4819 4818 int32_t curr_regu_power;
4820 4819 struct iwk_eep_channel *eep_chan_p;
4821 4820 struct iwk_eep_calib_channel_info eep_chan_calib;
4822 4821 int32_t eep_voltage, init_voltage;
4823 4822 int32_t voltage_compensation;
4824 4823 int32_t temperature;
4825 4824 int32_t degrees_per_05db_num;
4826 4825 int32_t degrees_per_05db_denom;
4827 4826 struct iwk_eep_calib_measure *measure_p;
4828 4827 int32_t interpo_temp;
4829 4828 int32_t power_limit;
4830 4829 int32_t atten_value;
4831 4830 int32_t tempera_comp[2];
4832 4831 int32_t interpo_gain_idx[2];
4833 4832 int32_t interpo_actual_pow[2];
4834 4833 union iwk_tx_power_dual_stream txpower_gains;
4835 4834 int32_t txpower_gains_idx;
4836 4835
4837 4836 channel = LE_16(sc->sc_config.chan);
4838 4837
4839 4838 /* 2.4 GHz or 5 GHz band */
4840 4839 is_24G = iwk_is_24G_band(sc);
4841 4840
4842 4841 /* fat channel or not */
4843 4842 is_fat = iwk_is_fat_channel(sc);
4844 4843
4845 4844 /*
4846 4845 * using low half channel number or high half channel number
4847 4846 * identify fat channel
4848 4847 */
4849 4848 if (is_fat && (LE_32(sc->sc_config.flags) &
4850 4849 RXON_FLG_CONTROL_CHANNEL_LOC_HIGH_MSK)) {
4851 4850 is_high_chan = 1;
4852 4851 }
4853 4852
4854 4853 if ((channel > 0) && (channel < 200)) {
4855 4854 /* get regulatory channel data from eeprom */
4856 4855 eep_chan_p = iwk_get_eep_channel(sc, channel, is_24G,
4857 4856 is_fat, is_high_chan);
4858 4857 if (NULL == eep_chan_p) {
4859 4858 cmn_err(CE_WARN,
4860 4859 "iwk_txpower_table_cmd_init(): "
4861 4860 "can't get channel infomation\n");
4862 4861 return (DDI_FAILURE);
4863 4862 }
4864 4863 } else {
4865 4864 cmn_err(CE_WARN, "iwk_txpower_table_cmd_init(): "
4866 4865 "channel(%d) isn't in proper range\n",
4867 4866 channel);
4868 4867 return (DDI_FAILURE);
4869 4868 }
4870 4869
4871 4870 /* initial value of Tx power */
4872 4871 sc->sc_user_txpower = (int32_t)eep_chan_p->max_power_avg;
4873 4872 if (sc->sc_user_txpower < IWK_TX_POWER_TARGET_POWER_MIN) {
4874 4873 cmn_err(CE_WARN, "iwk_txpower_table_cmd_init(): "
4875 4874 "user TX power is too weak\n");
4876 4875 return (DDI_FAILURE);
4877 4876 } else if (sc->sc_user_txpower > IWK_TX_POWER_TARGET_POWER_MAX) {
4878 4877 cmn_err(CE_WARN, "iwk_txpower_table_cmd_init(): "
4879 4878 "user TX power is too strong\n");
4880 4879 return (DDI_FAILURE);
4881 4880 }
4882 4881
4883 4882 target_power = 2 * sc->sc_user_txpower;
4884 4883
4885 4884 /* determine which group current channel belongs to */
4886 4885 tx_grp = iwk_txpower_grp(channel);
4887 4886 if (tx_grp < 0) {
4888 4887 return (tx_grp);
4889 4888 }
4890 4889
4891 4890
4892 4891 if (is_fat) {
4893 4892 if (is_high_chan) {
4894 4893 channel -= 2;
4895 4894 } else {
4896 4895 channel += 2;
4897 4896 }
4898 4897 }
4899 4898
4900 4899 /* determine saturation power */
4901 4900 if (is_24G) {
4902 4901 saturation_power =
4903 4902 sc->sc_eep_map.calib_info.saturation_power24;
4904 4903 } else {
4905 4904 saturation_power =
4906 4905 sc->sc_eep_map.calib_info.saturation_power52;
4907 4906 }
4908 4907
4909 4908 if (saturation_power < IWK_TX_POWER_SATURATION_MIN ||
4910 4909 saturation_power > IWK_TX_POWER_SATURATION_MAX) {
4911 4910 if (is_24G) {
4912 4911 saturation_power = IWK_TX_POWER_DEFAULT_SATURATION_24;
4913 4912 } else {
4914 4913 saturation_power = IWK_TX_POWER_DEFAULT_SATURATION_52;
4915 4914 }
4916 4915 }
4917 4916
4918 4917 /* determine regulatory power */
4919 4918 regu_power = (int32_t)eep_chan_p->max_power_avg * 2;
4920 4919 if ((regu_power < IWK_TX_POWER_REGULATORY_MIN) ||
4921 4920 (regu_power > IWK_TX_POWER_REGULATORY_MAX)) {
4922 4921 if (is_24G) {
4923 4922 regu_power = IWK_TX_POWER_DEFAULT_REGULATORY_24;
4924 4923 } else {
4925 4924 regu_power = IWK_TX_POWER_DEFAULT_REGULATORY_52;
4926 4925 }
4927 4926 }
4928 4927
4929 4928 /*
4930 4929 * get measurement data for current channel
4931 4930 * suach as temperature,index to gain table,actual Tx power
4932 4931 */
4933 4932 (void) iwk_channel_interpolate(sc, channel, &eep_chan_calib);
4934 4933
4935 4934 eep_voltage = (int32_t)LE_16(sc->sc_eep_map.calib_info.voltage);
4936 4935 init_voltage = (int32_t)LE_32(sc->sc_card_alive_init.voltage);
4937 4936
4938 4937 /* calculate voltage compensation to Tx power */
4939 4938 voltage_compensation =
4940 4939 iwk_voltage_compensation(eep_voltage, init_voltage);
4941 4940
4942 4941 if (sc->sc_tempera >= IWK_TX_POWER_TEMPERATURE_MIN) {
4943 4942 temperature = sc->sc_tempera;
4944 4943 } else {
4945 4944 temperature = IWK_TX_POWER_TEMPERATURE_MIN;
4946 4945 }
4947 4946 if (sc->sc_tempera <= IWK_TX_POWER_TEMPERATURE_MAX) {
4948 4947 temperature = sc->sc_tempera;
4949 4948 } else {
4950 4949 temperature = IWK_TX_POWER_TEMPERATURE_MAX;
4951 4950 }
4952 4951 temperature = KELVIN_TO_CELSIUS(temperature);
4953 4952
4954 4953 degrees_per_05db_num =
4955 4954 txpower_tempera_comp_table[tx_grp].degrees_per_05db_a;
4956 4955 degrees_per_05db_denom =
4957 4956 txpower_tempera_comp_table[tx_grp].degrees_per_05db_a_denom;
4958 4957
4959 4958 for (c = 0; c < 2; c++) { /* go through all chains */
4960 4959 measure_p = &eep_chan_calib.measure[c][1];
4961 4960 interpo_temp = measure_p->temperature;
4962 4961
4963 4962 /* determine temperature compensation to Tx power */
4964 4963 (void) iwk_division(
4965 4964 (temperature-interpo_temp)*degrees_per_05db_denom,
4966 4965 degrees_per_05db_num, &tempera_comp[c]);
4967 4966
4968 4967 interpo_gain_idx[c] = measure_p->gain_idx;
4969 4968 interpo_actual_pow[c] = measure_p->actual_pow;
4970 4969 }
4971 4970
4972 4971 /*
4973 4972 * go through all rate entries in Tx power table
4974 4973 */
4975 4974 for (r = 0; r < POWER_TABLE_NUM_ENTRIES; r++) {
4976 4975 if (r & 0x8) {
4977 4976 /* need to lower regulatory power for MIMO mode */
4978 4977 curr_regu_power = regu_power -
4979 4978 IWK_TX_POWER_MIMO_REGULATORY_COMPENSATION;
4980 4979 is_mimo = 1;
4981 4980 } else {
4982 4981 curr_regu_power = regu_power;
4983 4982 is_mimo = 0;
4984 4983 }
4985 4984
4986 4985 power_limit = saturation_power - back_off_table[r];
4987 4986 if (power_limit > curr_regu_power) {
4988 4987 /* final Tx power limit */
4989 4988 power_limit = curr_regu_power;
4990 4989 }
4991 4990
4992 4991 if (target_power > power_limit) {
4993 4992 target_power = power_limit; /* final target Tx power */
4994 4993 }
4995 4994
4996 4995 for (c = 0; c < 2; c++) { /* go through all Tx chains */
4997 4996 if (is_mimo) {
4998 4997 atten_value =
4999 4998 LE_32(sc->sc_card_alive_init.
5000 4999 tx_atten[tx_grp][c]);
5001 5000 } else {
5002 5001 atten_value = 0;
5003 5002 }
5004 5003
5005 5004 /*
5006 5005 * calculate index in gain table
5007 5006 * this step is very important
5008 5007 */
5009 5008 txpower_gains_idx = interpo_gain_idx[c] -
5010 5009 (target_power - interpo_actual_pow[c]) -
5011 5010 tempera_comp[c] - voltage_compensation +
5012 5011 atten_value;
5013 5012
5014 5013 if (txpower_gains_idx <
5015 5014 iwk_min_power_index(r, is_24G)) {
5016 5015 txpower_gains_idx =
5017 5016 iwk_min_power_index(r, is_24G);
5018 5017 }
5019 5018
5020 5019 if (!is_24G) {
5021 5020 /*
5022 5021 * support negative index for 5 GHz
5023 5022 * band
5024 5023 */
5025 5024 txpower_gains_idx += 9;
5026 5025 }
5027 5026
5028 5027 if (POWER_TABLE_CCK_ENTRY == r) {
5029 5028 /* for CCK mode, make necessary attenuaton */
5030 5029 txpower_gains_idx +=
5031 5030 IWK_TX_POWER_CCK_COMPENSATION_C_STEP;
5032 5031 }
5033 5032
5034 5033 if (txpower_gains_idx > 107) {
5035 5034 txpower_gains_idx = 107;
5036 5035 } else if (txpower_gains_idx < 0) {
5037 5036 txpower_gains_idx = 0;
5038 5037 }
5039 5038
5040 5039 /* search DSP and radio gains in gain table */
5041 5040 txpower_gains.s.radio_tx_gain[c] =
5042 5041 gains_table[is_24G][txpower_gains_idx].radio;
5043 5042 txpower_gains.s.dsp_predis_atten[c] =
5044 5043 gains_table[is_24G][txpower_gains_idx].dsp;
5045 5044
5046 5045 IWK_DBG((IWK_DEBUG_CALIBRATION,
5047 5046 "rate_index: %d, "
5048 5047 "gain_index %d, c: %d,is_mimo: %d\n",
5049 5048 r, txpower_gains_idx, c, is_mimo));
5050 5049 }
5051 5050
5052 5051 /* initialize Tx power table */
5053 5052 if (r < POWER_TABLE_NUM_HT_OFDM_ENTRIES) {
5054 5053 tp_db->ht_ofdm_power[r].dw = LE_32(txpower_gains.dw);
5055 5054 } else {
5056 5055 tp_db->legacy_cck_power.dw = LE_32(txpower_gains.dw);
5057 5056 }
5058 5057 }
5059 5058
5060 5059 return (IWK_SUCCESS);
5061 5060 }
5062 5061
5063 5062 /*
5064 5063 * make Tx power calibration to adjust Tx power.
5065 5064 * This is completed by sending out Tx power table command.
5066 5065 */
5067 5066 static int iwk_tx_power_calibration(iwk_sc_t *sc)
5068 5067 {
5069 5068 iwk_tx_power_table_cmd_t cmd;
5070 5069 int rv;
5071 5070
5072 5071 if (sc->sc_flags & IWK_F_SCANNING) {
5073 5072 return (IWK_SUCCESS);
5074 5073 }
5075 5074
5076 5075 /* necessary initialization to Tx power table command */
5077 5076 cmd.band = (uint8_t)iwk_is_24G_band(sc);
5078 5077 cmd.channel = sc->sc_config.chan;
5079 5078 cmd.channel_normal_width = 0;
5080 5079
5081 5080 /* initialize Tx power table */
5082 5081 rv = iwk_txpower_table_cmd_init(sc, &cmd.tx_power);
5083 5082 if (rv) {
5084 5083 cmn_err(CE_NOTE, "rv= %d\n", rv);
5085 5084 return (rv);
5086 5085 }
5087 5086
5088 5087 /* send out Tx power table command */
5089 5088 rv = iwk_cmd(sc, REPLY_TX_PWR_TABLE_CMD, &cmd, sizeof (cmd), 1);
5090 5089 if (rv) {
5091 5090 return (rv);
5092 5091 }
5093 5092
5094 5093 /* record current temperature */
5095 5094 sc->sc_last_tempera = sc->sc_tempera;
5096 5095
5097 5096 return (IWK_SUCCESS);
5098 5097 }
5099 5098
5100 5099 /* This function is the handler of statistics notification from uCode */
5101 5100 static void iwk_statistics_notify(iwk_sc_t *sc, iwk_rx_desc_t *desc)
5102 5101 {
5103 5102 int is_diff;
5104 5103 struct iwk_notif_statistics *statistics_p =
5105 5104 (struct iwk_notif_statistics *)(desc + 1);
5106 5105
5107 5106 mutex_enter(&sc->sc_glock);
5108 5107
5109 5108 is_diff = (sc->sc_statistics.general.temperature !=
5110 5109 statistics_p->general.temperature) ||
5111 5110 (LE_32(sc->sc_statistics.flag) &
5112 5111 STATISTICS_REPLY_FLG_FAT_MODE_MSK) !=
5113 5112 (LE_32(statistics_p->flag) & STATISTICS_REPLY_FLG_FAT_MODE_MSK);
5114 5113
5115 5114 /* update statistics data */
5116 5115 (void) memcpy(&sc->sc_statistics, statistics_p,
5117 5116 sizeof (struct iwk_notif_statistics));
5118 5117
5119 5118 sc->sc_flags |= IWK_F_STATISTICS;
5120 5119
5121 5120 if (!(sc->sc_flags & IWK_F_SCANNING)) {
5122 5121 /* make Receiver gain balance calibration */
5123 5122 (void) iwk_rxgain_diff(sc);
5124 5123
5125 5124 /* make Receiver sensitivity calibration */
5126 5125 (void) iwk_rx_sens(sc);
5127 5126 }
5128 5127
5129 5128
5130 5129 if (!is_diff) {
5131 5130 mutex_exit(&sc->sc_glock);
5132 5131 return;
5133 5132 }
5134 5133
5135 5134 /* calibration current temperature of 4965 chipset */
5136 5135 sc->sc_tempera = iwk_curr_tempera(sc);
5137 5136
5138 5137 /* distinct temperature change will trigger Tx power calibration */
5139 5138 if (((sc->sc_tempera - sc->sc_last_tempera) >= 3) ||
5140 5139 ((sc->sc_last_tempera - sc->sc_tempera) >= 3)) {
5141 5140 /* make Tx power calibration */
5142 5141 (void) iwk_tx_power_calibration(sc);
5143 5142 }
5144 5143
5145 5144 mutex_exit(&sc->sc_glock);
5146 5145 }
5147 5146
5148 5147 /* Determine this station is in associated state or not */
5149 5148 static int iwk_is_associated(iwk_sc_t *sc)
5150 5149 {
5151 5150 return (LE_32(sc->sc_config.filter_flags) & RXON_FILTER_ASSOC_MSK);
5152 5151 }
5153 5152
5154 5153 /* Make necessary preparation for Receiver gain balance calibration */
5155 5154 static int iwk_rxgain_diff_init(iwk_sc_t *sc)
5156 5155 {
5157 5156 int i, rv;
5158 5157 struct iwk_calibration_cmd cmd;
5159 5158 struct iwk_rx_gain_diff *gain_diff_p;
5160 5159
5161 5160 gain_diff_p = &sc->sc_rxgain_diff;
5162 5161
5163 5162 (void) memset(gain_diff_p, 0, sizeof (struct iwk_rx_gain_diff));
5164 5163 (void) memset(&cmd, 0, sizeof (struct iwk_calibration_cmd));
5165 5164
5166 5165 for (i = 0; i < RX_CHAINS_NUM; i++) {
5167 5166 gain_diff_p->gain_diff_chain[i] = CHAIN_GAIN_DIFF_INIT_VAL;
5168 5167 }
5169 5168
5170 5169 if (iwk_is_associated(sc)) {
5171 5170 cmd.opCode = PHY_CALIBRATE_DIFF_GAIN_CMD;
5172 5171 cmd.diff_gain_a = 0;
5173 5172 cmd.diff_gain_b = 0;
5174 5173 cmd.diff_gain_c = 0;
5175 5174
5176 5175 /* assume the gains of every Rx chains is balanceable */
5177 5176 rv = iwk_cmd(sc, REPLY_PHY_CALIBRATION_CMD, &cmd,
5178 5177 sizeof (cmd), 1);
5179 5178 if (rv) {
5180 5179 return (rv);
5181 5180 }
5182 5181
5183 5182 gain_diff_p->state = IWK_GAIN_DIFF_ACCUMULATE;
5184 5183 }
5185 5184
5186 5185 return (IWK_SUCCESS);
5187 5186 }
5188 5187
5189 5188 /*
5190 5189 * make Receiver gain balance to balance Rx gain between Rx chains
5191 5190 * and determine which chain is disconnected
5192 5191 */
5193 5192 static int iwk_rxgain_diff(iwk_sc_t *sc)
5194 5193 {
5195 5194 int i, is_24G, rv;
5196 5195 int max_beacon_chain_n;
5197 5196 int min_noise_chain_n;
5198 5197 uint16_t channel_n;
5199 5198 int32_t beacon_diff;
5200 5199 int32_t noise_diff;
5201 5200 uint32_t noise_chain_a, noise_chain_b, noise_chain_c;
5202 5201 uint32_t beacon_chain_a, beacon_chain_b, beacon_chain_c;
5203 5202 struct iwk_calibration_cmd cmd;
5204 5203 uint32_t beacon_aver[RX_CHAINS_NUM] = {0xFFFFFFFF};
5205 5204 uint32_t noise_aver[RX_CHAINS_NUM] = {0xFFFFFFFF};
5206 5205 struct statistics_rx_non_phy *rx_general_p =
5207 5206 &sc->sc_statistics.rx.general;
5208 5207 struct iwk_rx_gain_diff *gain_diff_p = &sc->sc_rxgain_diff;
5209 5208
5210 5209 if (INTERFERENCE_DATA_AVAILABLE !=
5211 5210 LE_32(rx_general_p->interference_data_flag)) {
5212 5211 return (IWK_SUCCESS);
5213 5212 }
5214 5213
5215 5214 if (IWK_GAIN_DIFF_ACCUMULATE != gain_diff_p->state) {
5216 5215 return (IWK_SUCCESS);
5217 5216 }
5218 5217
5219 5218 is_24G = iwk_is_24G_band(sc);
5220 5219 channel_n = sc->sc_config.chan; /* channel number */
5221 5220
5222 5221 if ((channel_n != (LE_32(sc->sc_statistics.flag) >> 16)) ||
5223 5222 ((STATISTICS_REPLY_FLG_BAND_24G_MSK ==
5224 5223 (LE_32(sc->sc_statistics.flag) &
5225 5224 STATISTICS_REPLY_FLG_BAND_24G_MSK)) &&
5226 5225 !is_24G)) {
5227 5226 return (IWK_SUCCESS);
5228 5227 }
5229 5228
5230 5229 /* Rx chain's noise strength from statistics notification */
5231 5230 noise_chain_a = LE_32(rx_general_p->beacon_silence_rssi_a) & 0xFF;
5232 5231 noise_chain_b = LE_32(rx_general_p->beacon_silence_rssi_b) & 0xFF;
5233 5232 noise_chain_c = LE_32(rx_general_p->beacon_silence_rssi_c) & 0xFF;
5234 5233
5235 5234 /* Rx chain's beacon strength from statistics notification */
5236 5235 beacon_chain_a = LE_32(rx_general_p->beacon_rssi_a) & 0xFF;
5237 5236 beacon_chain_b = LE_32(rx_general_p->beacon_rssi_b) & 0xFF;
5238 5237 beacon_chain_c = LE_32(rx_general_p->beacon_rssi_c) & 0xFF;
5239 5238
5240 5239 gain_diff_p->beacon_count++;
5241 5240
5242 5241 /* accumulate chain's noise strength */
5243 5242 gain_diff_p->noise_stren_a += noise_chain_a;
5244 5243 gain_diff_p->noise_stren_b += noise_chain_b;
5245 5244 gain_diff_p->noise_stren_c += noise_chain_c;
5246 5245
5247 5246 /* accumulate chain's beacon strength */
5248 5247 gain_diff_p->beacon_stren_a += beacon_chain_a;
5249 5248 gain_diff_p->beacon_stren_b += beacon_chain_b;
5250 5249 gain_diff_p->beacon_stren_c += beacon_chain_c;
5251 5250
5252 5251 if (BEACON_NUM_20 == gain_diff_p->beacon_count) {
5253 5252 /* calculate average beacon strength */
5254 5253 beacon_aver[0] = (gain_diff_p->beacon_stren_a) / BEACON_NUM_20;
5255 5254 beacon_aver[1] = (gain_diff_p->beacon_stren_b) / BEACON_NUM_20;
5256 5255 beacon_aver[2] = (gain_diff_p->beacon_stren_c) / BEACON_NUM_20;
5257 5256
5258 5257 /* calculate average noise strength */
5259 5258 noise_aver[0] = (gain_diff_p->noise_stren_a) / BEACON_NUM_20;
5260 5259 noise_aver[1] = (gain_diff_p->noise_stren_b) / BEACON_NUM_20;
5261 5260 noise_aver[2] = (gain_diff_p->noise_stren_b) / BEACON_NUM_20;
5262 5261
5263 5262 /* determine maximum beacon strength among 3 chains */
5264 5263 if ((beacon_aver[0] >= beacon_aver[1]) &&
5265 5264 (beacon_aver[0] >= beacon_aver[2])) {
5266 5265 max_beacon_chain_n = 0;
5267 5266 gain_diff_p->connected_chains = 1 << 0;
5268 5267 } else if (beacon_aver[1] >= beacon_aver[2]) {
5269 5268 max_beacon_chain_n = 1;
5270 5269 gain_diff_p->connected_chains = 1 << 1;
5271 5270 } else {
5272 5271 max_beacon_chain_n = 2;
5273 5272 gain_diff_p->connected_chains = 1 << 2;
5274 5273 }
5275 5274
5276 5275 /* determine which chain is disconnected */
5277 5276 for (i = 0; i < RX_CHAINS_NUM; i++) {
5278 5277 if (i != max_beacon_chain_n) {
5279 5278 beacon_diff = beacon_aver[max_beacon_chain_n] -
5280 5279 beacon_aver[i];
5281 5280 if (beacon_diff > MAX_ALLOWED_DIFF) {
5282 5281 gain_diff_p->disconnect_chain[i] = 1;
5283 5282 } else {
5284 5283 gain_diff_p->connected_chains |=
5285 5284 (1 << i);
5286 5285 }
5287 5286 }
5288 5287 }
5289 5288
5290 5289 /*
5291 5290 * if chain A and B are both disconnected,
5292 5291 * assume the stronger in beacon strength is connected
5293 5292 */
5294 5293 if (gain_diff_p->disconnect_chain[0] &&
5295 5294 gain_diff_p->disconnect_chain[1]) {
5296 5295 if (beacon_aver[0] >= beacon_aver[1]) {
5297 5296 gain_diff_p->disconnect_chain[0] = 0;
5298 5297 gain_diff_p->connected_chains |= (1 << 0);
5299 5298 } else {
5300 5299 gain_diff_p->disconnect_chain[1] = 0;
5301 5300 gain_diff_p->connected_chains |= (1 << 1);
5302 5301 }
5303 5302 }
5304 5303
5305 5304 /* determine minimum noise strength among 3 chains */
5306 5305 if (!gain_diff_p->disconnect_chain[0]) {
5307 5306 min_noise_chain_n = 0;
5308 5307
5309 5308 for (i = 0; i < RX_CHAINS_NUM; i++) {
5310 5309 if (!gain_diff_p->disconnect_chain[i] &&
5311 5310 (noise_aver[i] <=
5312 5311 noise_aver[min_noise_chain_n])) {
5313 5312 min_noise_chain_n = i;
5314 5313 }
5315 5314
5316 5315 }
5317 5316 } else {
5318 5317 min_noise_chain_n = 1;
5319 5318
5320 5319 for (i = 0; i < RX_CHAINS_NUM; i++) {
5321 5320 if (!gain_diff_p->disconnect_chain[i] &&
5322 5321 (noise_aver[i] <=
5323 5322 noise_aver[min_noise_chain_n])) {
5324 5323 min_noise_chain_n = i;
5325 5324 }
5326 5325 }
5327 5326 }
5328 5327
5329 5328 gain_diff_p->gain_diff_chain[min_noise_chain_n] = 0;
5330 5329
5331 5330 /* determine gain difference between chains */
5332 5331 for (i = 0; i < RX_CHAINS_NUM; i++) {
5333 5332 if (!gain_diff_p->disconnect_chain[i] &&
5334 5333 (CHAIN_GAIN_DIFF_INIT_VAL ==
5335 5334 gain_diff_p->gain_diff_chain[i])) {
5336 5335
5337 5336 noise_diff = noise_aver[i] -
5338 5337 noise_aver[min_noise_chain_n];
5339 5338 gain_diff_p->gain_diff_chain[i] =
5340 5339 (uint8_t)((noise_diff * 10) / 15);
5341 5340
5342 5341 if (gain_diff_p->gain_diff_chain[i] > 3) {
5343 5342 gain_diff_p->gain_diff_chain[i] = 3;
5344 5343 }
5345 5344
5346 5345 gain_diff_p->gain_diff_chain[i] |= (1 << 2);
5347 5346 } else {
5348 5347 gain_diff_p->gain_diff_chain[i] = 0;
5349 5348 }
5350 5349 }
5351 5350
5352 5351 if (!gain_diff_p->gain_diff_send) {
5353 5352 gain_diff_p->gain_diff_send = 1;
5354 5353
5355 5354 (void) memset(&cmd, 0, sizeof (cmd));
5356 5355
5357 5356 cmd.opCode = PHY_CALIBRATE_DIFF_GAIN_CMD;
5358 5357 cmd.diff_gain_a = gain_diff_p->gain_diff_chain[0];
5359 5358 cmd.diff_gain_b = gain_diff_p->gain_diff_chain[1];
5360 5359 cmd.diff_gain_c = gain_diff_p->gain_diff_chain[2];
5361 5360
5362 5361 /*
5363 5362 * send out PHY calibration command to
5364 5363 * adjust every chain's Rx gain
5365 5364 */
5366 5365 rv = iwk_cmd(sc, REPLY_PHY_CALIBRATION_CMD,
5367 5366 &cmd, sizeof (cmd), 1);
5368 5367 if (rv) {
5369 5368 return (rv);
5370 5369 }
5371 5370
5372 5371 gain_diff_p->state = IWK_GAIN_DIFF_CALIBRATED;
5373 5372 }
5374 5373
5375 5374 gain_diff_p->beacon_stren_a = 0;
5376 5375 gain_diff_p->beacon_stren_b = 0;
5377 5376 gain_diff_p->beacon_stren_c = 0;
5378 5377
5379 5378 gain_diff_p->noise_stren_a = 0;
5380 5379 gain_diff_p->noise_stren_b = 0;
5381 5380 gain_diff_p->noise_stren_c = 0;
5382 5381 }
5383 5382
5384 5383 return (IWK_SUCCESS);
5385 5384 }
5386 5385
5387 5386 /* Make necessary preparation for Receiver sensitivity calibration */
5388 5387 static int iwk_rx_sens_init(iwk_sc_t *sc)
5389 5388 {
5390 5389 int i, rv;
5391 5390 struct iwk_rx_sensitivity_cmd cmd;
5392 5391 struct iwk_rx_sensitivity *rx_sens_p = &sc->sc_rx_sens;
5393 5392
5394 5393 (void) memset(&cmd, 0, sizeof (struct iwk_rx_sensitivity_cmd));
5395 5394 (void) memset(rx_sens_p, 0, sizeof (struct iwk_rx_sensitivity));
5396 5395
5397 5396 rx_sens_p->auto_corr_ofdm_x4 = 90;
5398 5397 rx_sens_p->auto_corr_mrc_ofdm_x4 = 170;
5399 5398 rx_sens_p->auto_corr_ofdm_x1 = 105;
5400 5399 rx_sens_p->auto_corr_mrc_ofdm_x1 = 220;
5401 5400
5402 5401 rx_sens_p->auto_corr_cck_x4 = 125;
5403 5402 rx_sens_p->auto_corr_mrc_cck_x4 = 200;
5404 5403 rx_sens_p->min_energy_det_cck = 100;
5405 5404
5406 5405 rx_sens_p->flags &= (~IWK_SENSITIVITY_CALIB_ALLOW_MSK);
5407 5406 rx_sens_p->flags &= (~IWK_SENSITIVITY_OFDM_UPDATE_MSK);
5408 5407 rx_sens_p->flags &= (~IWK_SENSITIVITY_CCK_UPDATE_MSK);
5409 5408
5410 5409 rx_sens_p->last_bad_plcp_cnt_ofdm = 0;
5411 5410 rx_sens_p->last_false_alarm_cnt_ofdm = 0;
5412 5411 rx_sens_p->last_bad_plcp_cnt_cck = 0;
5413 5412 rx_sens_p->last_false_alarm_cnt_cck = 0;
5414 5413
5415 5414 rx_sens_p->cck_curr_state = IWK_TOO_MANY_FALSE_ALARM;
5416 5415 rx_sens_p->cck_prev_state = IWK_TOO_MANY_FALSE_ALARM;
5417 5416 rx_sens_p->cck_no_false_alarm_num = 0;
5418 5417 rx_sens_p->cck_beacon_idx = 0;
5419 5418
5420 5419 for (i = 0; i < 10; i++) {
5421 5420 rx_sens_p->cck_beacon_min[i] = 0;
5422 5421 }
5423 5422
5424 5423 rx_sens_p->cck_noise_idx = 0;
5425 5424 rx_sens_p->cck_noise_ref = 0;
5426 5425
5427 5426 for (i = 0; i < 20; i++) {
5428 5427 rx_sens_p->cck_noise_max[i] = 0;
5429 5428 }
5430 5429
5431 5430 rx_sens_p->cck_noise_diff = 0;
5432 5431 rx_sens_p->cck_no_false_alarm_num = 0;
5433 5432
5434 5433 cmd.control = LE_16(IWK_SENSITIVITY_CONTROL_WORK_TABLE);
5435 5434
5436 5435 cmd.table[AUTO_CORR32_X4_TH_ADD_MIN_IDX] =
5437 5436 LE_16(rx_sens_p->auto_corr_ofdm_x4);
5438 5437 cmd.table[AUTO_CORR32_X4_TH_ADD_MIN_MRC_IDX] =
5439 5438 LE_16(rx_sens_p->auto_corr_mrc_ofdm_x4);
5440 5439 cmd.table[AUTO_CORR32_X1_TH_ADD_MIN_IDX] =
5441 5440 LE_16(rx_sens_p->auto_corr_ofdm_x1);
5442 5441 cmd.table[AUTO_CORR32_X1_TH_ADD_MIN_MRC_IDX] =
5443 5442 LE_16(rx_sens_p->auto_corr_mrc_ofdm_x1);
5444 5443
5445 5444 cmd.table[AUTO_CORR40_X4_TH_ADD_MIN_IDX] =
5446 5445 LE_16(rx_sens_p->auto_corr_cck_x4);
5447 5446 cmd.table[AUTO_CORR40_X4_TH_ADD_MIN_MRC_IDX] =
5448 5447 LE_16(rx_sens_p->auto_corr_mrc_cck_x4);
5449 5448 cmd.table[MIN_ENERGY_CCK_DET_IDX] =
5450 5449 LE_16(rx_sens_p->min_energy_det_cck);
5451 5450
5452 5451 cmd.table[MIN_ENERGY_OFDM_DET_IDX] = LE_16(100);
5453 5452 cmd.table[BARKER_CORR_TH_ADD_MIN_IDX] = LE_16(190);
5454 5453 cmd.table[BARKER_CORR_TH_ADD_MIN_MRC_IDX] = LE_16(390);
5455 5454 cmd.table[PTAM_ENERGY_TH_IDX] = LE_16(62);
5456 5455
5457 5456 /* at first, set up Rx to maximum sensitivity */
5458 5457 rv = iwk_cmd(sc, SENSITIVITY_CMD, &cmd, sizeof (cmd), 1);
5459 5458 if (rv) {
5460 5459 cmn_err(CE_WARN, "iwk_rx_sens_init(): "
5461 5460 "in the process of initialization, "
5462 5461 "failed to send rx sensitivity command\n");
5463 5462 return (rv);
5464 5463 }
5465 5464
5466 5465 rx_sens_p->flags |= IWK_SENSITIVITY_CALIB_ALLOW_MSK;
5467 5466
5468 5467 return (IWK_SUCCESS);
5469 5468 }
5470 5469
5471 5470 /*
5472 5471 * make Receiver sensitivity calibration to adjust every chain's Rx sensitivity.
5473 5472 * for more infomation, please refer to iwk_calibration.h file
5474 5473 */
5475 5474 static int iwk_rx_sens(iwk_sc_t *sc)
5476 5475 {
5477 5476 int rv;
5478 5477 uint32_t actual_rx_time;
5479 5478 struct statistics_rx_non_phy *rx_general_p =
5480 5479 &sc->sc_statistics.rx.general;
5481 5480 struct iwk_rx_sensitivity *rx_sens_p = &sc->sc_rx_sens;
5482 5481 struct iwk_rx_sensitivity_cmd cmd;
5483 5482
5484 5483 if (!(rx_sens_p->flags & IWK_SENSITIVITY_CALIB_ALLOW_MSK)) {
5485 5484 cmn_err(CE_WARN, "iwk_rx_sens(): "
5486 5485 "sensitivity initialization has not finished.\n");
5487 5486 return (DDI_FAILURE);
5488 5487 }
5489 5488
5490 5489 if (INTERFERENCE_DATA_AVAILABLE !=
5491 5490 LE_32(rx_general_p->interference_data_flag)) {
5492 5491 cmn_err(CE_WARN, "iwk_rx_sens(): "
5493 5492 "can't make rx sensitivity calibration,"
5494 5493 "because of invalid statistics\n");
5495 5494 return (DDI_FAILURE);
5496 5495 }
5497 5496
5498 5497 actual_rx_time = LE_32(rx_general_p->channel_load);
5499 5498 if (!actual_rx_time) {
5500 5499 IWK_DBG((IWK_DEBUG_CALIBRATION, "iwk_rx_sens(): "
5501 5500 "can't make rx sensitivity calibration,"
5502 5501 "because has not enough rx time\n"));
5503 5502 return (DDI_FAILURE);
5504 5503 }
5505 5504
5506 5505 /* make Rx sensitivity calibration for OFDM mode */
5507 5506 rv = iwk_ofdm_sens(sc, actual_rx_time);
5508 5507 if (rv) {
5509 5508 return (rv);
5510 5509 }
5511 5510
5512 5511 /* make Rx sensitivity calibration for CCK mode */
5513 5512 rv = iwk_cck_sens(sc, actual_rx_time);
5514 5513 if (rv) {
5515 5514 return (rv);
5516 5515 }
5517 5516
5518 5517 /*
5519 5518 * if the sum of false alarm had not changed, nothing will be done
5520 5519 */
5521 5520 if ((!(rx_sens_p->flags & IWK_SENSITIVITY_OFDM_UPDATE_MSK)) &&
5522 5521 (!(rx_sens_p->flags & IWK_SENSITIVITY_CCK_UPDATE_MSK))) {
5523 5522 return (IWK_SUCCESS);
5524 5523 }
5525 5524
5526 5525 cmd.control = IWK_SENSITIVITY_CONTROL_WORK_TABLE;
5527 5526
5528 5527 cmd.table[AUTO_CORR32_X4_TH_ADD_MIN_IDX] =
5529 5528 rx_sens_p->auto_corr_ofdm_x4;
5530 5529 cmd.table[AUTO_CORR32_X4_TH_ADD_MIN_MRC_IDX] =
5531 5530 rx_sens_p->auto_corr_mrc_ofdm_x4;
5532 5531 cmd.table[AUTO_CORR32_X1_TH_ADD_MIN_IDX] =
5533 5532 rx_sens_p->auto_corr_ofdm_x1;
5534 5533 cmd.table[AUTO_CORR32_X1_TH_ADD_MIN_MRC_IDX] =
5535 5534 rx_sens_p->auto_corr_mrc_ofdm_x1;
5536 5535
5537 5536 cmd.table[AUTO_CORR40_X4_TH_ADD_MIN_IDX] =
5538 5537 rx_sens_p->auto_corr_cck_x4;
5539 5538 cmd.table[AUTO_CORR40_X4_TH_ADD_MIN_MRC_IDX] =
5540 5539 rx_sens_p->auto_corr_mrc_cck_x4;
5541 5540 cmd.table[MIN_ENERGY_CCK_DET_IDX] =
5542 5541 rx_sens_p->min_energy_det_cck;
5543 5542
5544 5543 cmd.table[MIN_ENERGY_OFDM_DET_IDX] = 100;
5545 5544 cmd.table[BARKER_CORR_TH_ADD_MIN_IDX] = 190;
5546 5545 cmd.table[BARKER_CORR_TH_ADD_MIN_MRC_IDX] = 390;
5547 5546 cmd.table[PTAM_ENERGY_TH_IDX] = 62;
5548 5547
5549 5548 /*
5550 5549 * send sensitivity command to complete actual sensitivity calibration
5551 5550 */
5552 5551 rv = iwk_cmd(sc, SENSITIVITY_CMD, &cmd, sizeof (cmd), 1);
5553 5552 if (rv) {
5554 5553 cmn_err(CE_WARN, "iwk_rx_sens(): "
5555 5554 "fail to send rx sensitivity command\n");
5556 5555 return (rv);
5557 5556 }
5558 5557
5559 5558 return (IWK_SUCCESS);
5560 5559
5561 5560 }
5562 5561
5563 5562 /*
5564 5563 * make Rx sensitivity calibration for CCK mode.
5565 5564 * This is preparing parameters for Sensitivity command
5566 5565 */
5567 5566 static int iwk_cck_sens(iwk_sc_t *sc, uint32_t actual_rx_time)
5568 5567 {
5569 5568 int i;
5570 5569 uint8_t noise_a, noise_b, noise_c;
5571 5570 uint8_t max_noise_abc, max_noise_20;
5572 5571 uint32_t beacon_a, beacon_b, beacon_c;
5573 5572 uint32_t min_beacon_abc, max_beacon_10;
5574 5573 uint32_t cck_fa, cck_bp;
5575 5574 uint32_t cck_sum_fa_bp;
5576 5575 uint32_t temp;
5577 5576 struct statistics_rx_non_phy *rx_general_p =
5578 5577 &sc->sc_statistics.rx.general;
5579 5578 struct iwk_rx_sensitivity *rx_sens_p = &sc->sc_rx_sens;
5580 5579
5581 5580 cck_fa = LE_32(sc->sc_statistics.rx.cck.false_alarm_cnt);
5582 5581 cck_bp = LE_32(sc->sc_statistics.rx.cck.plcp_err);
5583 5582
5584 5583 /* accumulate false alarm */
5585 5584 if (rx_sens_p->last_false_alarm_cnt_cck > cck_fa) {
5586 5585 temp = rx_sens_p->last_false_alarm_cnt_cck;
5587 5586 rx_sens_p->last_false_alarm_cnt_cck = cck_fa;
5588 5587 cck_fa += (0xFFFFFFFF - temp);
5589 5588 } else {
5590 5589 cck_fa -= rx_sens_p->last_false_alarm_cnt_cck;
5591 5590 rx_sens_p->last_false_alarm_cnt_cck += cck_fa;
5592 5591 }
5593 5592
5594 5593 /* accumulate bad plcp */
5595 5594 if (rx_sens_p->last_bad_plcp_cnt_cck > cck_bp) {
5596 5595 temp = rx_sens_p->last_bad_plcp_cnt_cck;
5597 5596 rx_sens_p->last_bad_plcp_cnt_cck = cck_bp;
5598 5597 cck_bp += (0xFFFFFFFF - temp);
5599 5598 } else {
5600 5599 cck_bp -= rx_sens_p->last_bad_plcp_cnt_cck;
5601 5600 rx_sens_p->last_bad_plcp_cnt_cck += cck_bp;
5602 5601 }
5603 5602
5604 5603 /*
5605 5604 * calculate relative value
5606 5605 */
5607 5606 cck_sum_fa_bp = (cck_fa + cck_bp) * 200 * 1024;
5608 5607 rx_sens_p->cck_noise_diff = 0;
5609 5608
5610 5609 noise_a =
5611 5610 (uint8_t)((LE_32(rx_general_p->beacon_silence_rssi_a) & 0xFF00) >>
5612 5611 8);
5613 5612 noise_b =
5614 5613 (uint8_t)((LE_32(rx_general_p->beacon_silence_rssi_b) & 0xFF00) >>
5615 5614 8);
5616 5615 noise_c =
5617 5616 (uint8_t)((LE_32(rx_general_p->beacon_silence_rssi_c) & 0xFF00) >>
5618 5617 8);
5619 5618
5620 5619 beacon_a = LE_32(rx_general_p->beacon_energy_a);
5621 5620 beacon_b = LE_32(rx_general_p->beacon_energy_b);
5622 5621 beacon_c = LE_32(rx_general_p->beacon_energy_c);
5623 5622
5624 5623 /* determine maximum noise among 3 chains */
5625 5624 if ((noise_a >= noise_b) && (noise_a >= noise_c)) {
5626 5625 max_noise_abc = noise_a;
5627 5626 } else if (noise_b >= noise_c) {
5628 5627 max_noise_abc = noise_b;
5629 5628 } else {
5630 5629 max_noise_abc = noise_c;
5631 5630 }
5632 5631
5633 5632 /* record maximum noise among 3 chains */
5634 5633 rx_sens_p->cck_noise_max[rx_sens_p->cck_noise_idx] = max_noise_abc;
5635 5634 rx_sens_p->cck_noise_idx++;
5636 5635 if (rx_sens_p->cck_noise_idx >= 20) {
5637 5636 rx_sens_p->cck_noise_idx = 0;
5638 5637 }
5639 5638
5640 5639 /* determine maximum noise among 20 max noise */
5641 5640 max_noise_20 = rx_sens_p->cck_noise_max[0];
5642 5641 for (i = 0; i < 20; i++) {
5643 5642 if (rx_sens_p->cck_noise_max[i] >= max_noise_20) {
5644 5643 max_noise_20 = rx_sens_p->cck_noise_max[i];
5645 5644 }
5646 5645 }
5647 5646
5648 5647 /* determine minimum beacon among 3 chains */
5649 5648 if ((beacon_a <= beacon_b) && (beacon_a <= beacon_c)) {
5650 5649 min_beacon_abc = beacon_a;
5651 5650 } else if (beacon_b <= beacon_c) {
5652 5651 min_beacon_abc = beacon_b;
5653 5652 } else {
5654 5653 min_beacon_abc = beacon_c;
5655 5654 }
5656 5655
5657 5656 /* record miminum beacon among 3 chains */
5658 5657 rx_sens_p->cck_beacon_min[rx_sens_p->cck_beacon_idx] = min_beacon_abc;
5659 5658 rx_sens_p->cck_beacon_idx++;
5660 5659 if (rx_sens_p->cck_beacon_idx >= 10) {
5661 5660 rx_sens_p->cck_beacon_idx = 0;
5662 5661 }
5663 5662
5664 5663 /* determine maximum beacon among 10 miminum beacon among 3 chains */
5665 5664 max_beacon_10 = rx_sens_p->cck_beacon_min[0];
5666 5665 for (i = 0; i < 10; i++) {
5667 5666 if (rx_sens_p->cck_beacon_min[i] >= max_beacon_10) {
5668 5667 max_beacon_10 = rx_sens_p->cck_beacon_min[i];
5669 5668 }
5670 5669 }
5671 5670
5672 5671 /* add a little margin */
5673 5672 max_beacon_10 += 6;
5674 5673
5675 5674 /* record the count of having no false alarms */
5676 5675 if (cck_sum_fa_bp < (5 * actual_rx_time)) {
5677 5676 rx_sens_p->cck_no_false_alarm_num++;
5678 5677 } else {
5679 5678 rx_sens_p->cck_no_false_alarm_num = 0;
5680 5679 }
5681 5680
5682 5681 /*
5683 5682 * adjust parameters in sensitivity command
5684 5683 * according to different status.
5685 5684 * for more infomation, please refer to iwk_calibration.h file
5686 5685 */
5687 5686 if (cck_sum_fa_bp > (50 * actual_rx_time)) {
5688 5687 rx_sens_p->cck_curr_state = IWK_TOO_MANY_FALSE_ALARM;
5689 5688
5690 5689 if (rx_sens_p->auto_corr_cck_x4 > 160) {
5691 5690 rx_sens_p->cck_noise_ref = max_noise_20;
5692 5691
5693 5692 if (rx_sens_p->min_energy_det_cck > 2) {
5694 5693 rx_sens_p->min_energy_det_cck -= 2;
5695 5694 }
5696 5695 }
5697 5696
5698 5697 if (rx_sens_p->auto_corr_cck_x4 < 160) {
5699 5698 rx_sens_p->auto_corr_cck_x4 = 160 + 1;
5700 5699 } else {
5701 5700 if ((rx_sens_p->auto_corr_cck_x4 + 3) < 200) {
5702 5701 rx_sens_p->auto_corr_cck_x4 += 3;
5703 5702 } else {
5704 5703 rx_sens_p->auto_corr_cck_x4 = 200;
5705 5704 }
5706 5705 }
5707 5706
5708 5707 if ((rx_sens_p->auto_corr_mrc_cck_x4 + 3) < 400) {
5709 5708 rx_sens_p->auto_corr_mrc_cck_x4 += 3;
5710 5709 } else {
5711 5710 rx_sens_p->auto_corr_mrc_cck_x4 = 400;
5712 5711 }
5713 5712
5714 5713 rx_sens_p->flags |= IWK_SENSITIVITY_CCK_UPDATE_MSK;
5715 5714
5716 5715 } else if (cck_sum_fa_bp < (5 * actual_rx_time)) {
5717 5716 rx_sens_p->cck_curr_state = IWK_TOO_FEW_FALSE_ALARM;
5718 5717
5719 5718 rx_sens_p->cck_noise_diff = (int32_t)rx_sens_p->cck_noise_ref -
5720 5719 (int32_t)max_noise_20;
5721 5720
5722 5721 if ((rx_sens_p->cck_prev_state != IWK_TOO_MANY_FALSE_ALARM) &&
5723 5722 ((rx_sens_p->cck_noise_diff > 2) ||
5724 5723 (rx_sens_p->cck_no_false_alarm_num > 100))) {
5725 5724 if ((rx_sens_p->min_energy_det_cck + 2) < 97) {
5726 5725 rx_sens_p->min_energy_det_cck += 2;
5727 5726 } else {
5728 5727 rx_sens_p->min_energy_det_cck = 97;
5729 5728 }
5730 5729
5731 5730 if ((rx_sens_p->auto_corr_cck_x4 - 3) > 125) {
5732 5731 rx_sens_p->auto_corr_cck_x4 -= 3;
5733 5732 } else {
5734 5733 rx_sens_p->auto_corr_cck_x4 = 125;
5735 5734 }
5736 5735
5737 5736 if ((rx_sens_p->auto_corr_mrc_cck_x4 -3) > 200) {
5738 5737 rx_sens_p->auto_corr_mrc_cck_x4 -= 3;
5739 5738 } else {
5740 5739 rx_sens_p->auto_corr_mrc_cck_x4 = 200;
5741 5740 }
5742 5741
5743 5742 rx_sens_p->flags |= IWK_SENSITIVITY_CCK_UPDATE_MSK;
5744 5743 } else {
5745 5744 rx_sens_p->flags &= (~IWK_SENSITIVITY_CCK_UPDATE_MSK);
5746 5745 }
5747 5746 } else {
5748 5747 rx_sens_p->cck_curr_state = IWK_GOOD_RANGE_FALSE_ALARM;
5749 5748
5750 5749 rx_sens_p->cck_noise_ref = max_noise_20;
5751 5750
5752 5751 if (IWK_TOO_MANY_FALSE_ALARM == rx_sens_p->cck_prev_state) {
5753 5752 rx_sens_p->min_energy_det_cck -= 8;
5754 5753 }
5755 5754
5756 5755 rx_sens_p->flags &= (~IWK_SENSITIVITY_CCK_UPDATE_MSK);
5757 5756 }
5758 5757
5759 5758 if (rx_sens_p->min_energy_det_cck < max_beacon_10) {
5760 5759 rx_sens_p->min_energy_det_cck = (uint16_t)max_beacon_10;
5761 5760 }
5762 5761
5763 5762 rx_sens_p->cck_prev_state = rx_sens_p->cck_curr_state;
5764 5763
5765 5764 return (IWK_SUCCESS);
5766 5765 }
5767 5766
5768 5767 /*
5769 5768 * make Rx sensitivity calibration for OFDM mode.
5770 5769 * This is preparing parameters for Sensitivity command
5771 5770 */
5772 5771 static int iwk_ofdm_sens(iwk_sc_t *sc, uint32_t actual_rx_time)
5773 5772 {
5774 5773 uint32_t temp;
5775 5774 uint16_t temp1;
5776 5775 uint32_t ofdm_fa, ofdm_bp;
5777 5776 uint32_t ofdm_sum_fa_bp;
5778 5777 struct iwk_rx_sensitivity *rx_sens_p = &sc->sc_rx_sens;
5779 5778
5780 5779 ofdm_fa = LE_32(sc->sc_statistics.rx.ofdm.false_alarm_cnt);
5781 5780 ofdm_bp = LE_32(sc->sc_statistics.rx.ofdm.plcp_err);
5782 5781
5783 5782 /* accumulate false alarm */
5784 5783 if (rx_sens_p->last_false_alarm_cnt_ofdm > ofdm_fa) {
5785 5784 temp = rx_sens_p->last_false_alarm_cnt_ofdm;
5786 5785 rx_sens_p->last_false_alarm_cnt_ofdm = ofdm_fa;
5787 5786 ofdm_fa += (0xFFFFFFFF - temp);
5788 5787 } else {
5789 5788 ofdm_fa -= rx_sens_p->last_false_alarm_cnt_ofdm;
5790 5789 rx_sens_p->last_false_alarm_cnt_ofdm += ofdm_fa;
5791 5790 }
5792 5791
5793 5792 /* accumulate bad plcp */
5794 5793 if (rx_sens_p->last_bad_plcp_cnt_ofdm > ofdm_bp) {
5795 5794 temp = rx_sens_p->last_bad_plcp_cnt_ofdm;
5796 5795 rx_sens_p->last_bad_plcp_cnt_ofdm = ofdm_bp;
5797 5796 ofdm_bp += (0xFFFFFFFF - temp);
5798 5797 } else {
5799 5798 ofdm_bp -= rx_sens_p->last_bad_plcp_cnt_ofdm;
5800 5799 rx_sens_p->last_bad_plcp_cnt_ofdm += ofdm_bp;
5801 5800 }
5802 5801
5803 5802 ofdm_sum_fa_bp = (ofdm_fa + ofdm_bp) * 200 * 1024; /* relative value */
5804 5803
5805 5804 /*
5806 5805 * adjust parameter in sensitivity command according to different status
5807 5806 */
5808 5807 if (ofdm_sum_fa_bp > (50 * actual_rx_time)) {
5809 5808 temp1 = rx_sens_p->auto_corr_ofdm_x4 + 1;
5810 5809 rx_sens_p->auto_corr_ofdm_x4 = (temp1 <= 120) ? temp1 : 120;
5811 5810
5812 5811 temp1 = rx_sens_p->auto_corr_mrc_ofdm_x4 + 1;
5813 5812 rx_sens_p->auto_corr_mrc_ofdm_x4 =
5814 5813 (temp1 <= 210) ? temp1 : 210;
5815 5814
5816 5815 temp1 = rx_sens_p->auto_corr_ofdm_x1 + 1;
5817 5816 rx_sens_p->auto_corr_ofdm_x1 = (temp1 <= 140) ? temp1 : 140;
5818 5817
5819 5818 temp1 = rx_sens_p->auto_corr_mrc_ofdm_x1 + 1;
5820 5819 rx_sens_p->auto_corr_mrc_ofdm_x1 =
5821 5820 (temp1 <= 270) ? temp1 : 270;
5822 5821
5823 5822 rx_sens_p->flags |= IWK_SENSITIVITY_OFDM_UPDATE_MSK;
5824 5823
5825 5824 } else if (ofdm_sum_fa_bp < (5 * actual_rx_time)) {
5826 5825 temp1 = rx_sens_p->auto_corr_ofdm_x4 - 1;
5827 5826 rx_sens_p->auto_corr_ofdm_x4 = (temp1 >= 85) ? temp1 : 85;
5828 5827
5829 5828 temp1 = rx_sens_p->auto_corr_mrc_ofdm_x4 - 1;
5830 5829 rx_sens_p->auto_corr_mrc_ofdm_x4 =
5831 5830 (temp1 >= 170) ? temp1 : 170;
5832 5831
5833 5832 temp1 = rx_sens_p->auto_corr_ofdm_x1 - 1;
5834 5833 rx_sens_p->auto_corr_ofdm_x1 = (temp1 >= 105) ? temp1 : 105;
5835 5834
5836 5835 temp1 = rx_sens_p->auto_corr_mrc_ofdm_x1 - 1;
5837 5836 rx_sens_p->auto_corr_mrc_ofdm_x1 =
5838 5837 (temp1 >= 220) ? temp1 : 220;
5839 5838
5840 5839 rx_sens_p->flags |= IWK_SENSITIVITY_OFDM_UPDATE_MSK;
5841 5840
5842 5841 } else {
5843 5842 rx_sens_p->flags &= (~IWK_SENSITIVITY_OFDM_UPDATE_MSK);
5844 5843 }
5845 5844
5846 5845 return (IWK_SUCCESS);
5847 5846 }
5848 5847
5849 5848 /*
5850 5849 * additional process to management frames
5851 5850 */
5852 5851 static void iwk_recv_mgmt(struct ieee80211com *ic, mblk_t *mp,
5853 5852 struct ieee80211_node *in,
5854 5853 int subtype, int rssi, uint32_t rstamp)
5855 5854 {
5856 5855 iwk_sc_t *sc = (iwk_sc_t *)ic;
5857 5856 struct ieee80211_frame *wh;
5858 5857 uint8_t index1, index2;
5859 5858 int err;
5860 5859
5861 5860 sc->sc_recv_mgmt(ic, mp, in, subtype, rssi, rstamp);
5862 5861
5863 5862 mutex_enter(&sc->sc_glock);
5864 5863 switch (subtype) {
5865 5864 case IEEE80211_FC0_SUBTYPE_BEACON:
5866 5865 if (sc->sc_ibss.ibss_beacon.syncbeacon && in == ic->ic_bss &&
5867 5866 ic->ic_state == IEEE80211_S_RUN) {
5868 5867 if (ieee80211_beacon_update(ic, in,
5869 5868 &sc->sc_ibss.ibss_beacon.iwk_boff,
5870 5869 sc->sc_ibss.ibss_beacon.mp, 0)) {
5871 5870 bcopy(sc->sc_ibss.ibss_beacon.mp->b_rptr,
5872 5871 sc->sc_ibss.ibss_beacon.beacon_cmd.
5873 5872 bcon_frame,
5874 5873 MBLKL(sc->sc_ibss.ibss_beacon.mp));
5875 5874 }
5876 5875 err = iwk_cmd(sc, REPLY_TX_BEACON,
5877 5876 &sc->sc_ibss.ibss_beacon.beacon_cmd,
5878 5877 sc->sc_ibss.ibss_beacon.beacon_cmd_len, 1);
5879 5878 if (err != IWK_SUCCESS) {
5880 5879 cmn_err(CE_WARN, "iwk_recv_mgmt(): "
5881 5880 "failed to TX beacon.\n");
5882 5881 }
5883 5882 sc->sc_ibss.ibss_beacon.syncbeacon = 0;
5884 5883 }
5885 5884 if (ic->ic_opmode == IEEE80211_M_IBSS &&
5886 5885 ic->ic_state == IEEE80211_S_RUN) {
5887 5886 wh = (struct ieee80211_frame *)mp->b_rptr;
5888 5887 mutex_enter(&sc->sc_ibss.node_tb_lock);
5889 5888 /*
5890 5889 * search for node in ibss node table
5891 5890 */
5892 5891 for (index1 = IWK_STA_ID; index1 < IWK_STATION_COUNT;
5893 5892 index1++) {
5894 5893 if (sc->sc_ibss.ibss_node_tb[index1].used &&
5895 5894 IEEE80211_ADDR_EQ(sc->sc_ibss.
5896 5895 ibss_node_tb[index1].node.bssid,
5897 5896 wh->i_addr2)) {
5898 5897 break;
5899 5898 }
5900 5899 }
5901 5900 /*
5902 5901 * if don't find in ibss node table
5903 5902 */
5904 5903 if (index1 >= IWK_BROADCAST_ID) {
5905 5904 err = iwk_clean_add_node_ibss(ic,
5906 5905 wh->i_addr2, &index2);
5907 5906 if (err != IWK_SUCCESS) {
5908 5907 cmn_err(CE_WARN, "iwk_recv_mgmt(): "
5909 5908 "failed to clean all nodes "
5910 5909 "and add one node\n");
5911 5910 }
5912 5911 }
5913 5912 mutex_exit(&sc->sc_ibss.node_tb_lock);
5914 5913 }
5915 5914 break;
5916 5915 case IEEE80211_FC0_SUBTYPE_PROBE_RESP:
5917 5916 break;
5918 5917 }
5919 5918 mutex_exit(&sc->sc_glock);
5920 5919 }
5921 5920
5922 5921 /*
5923 5922 * 1) log_event_table_ptr indicates base of the event log. This traces
5924 5923 * a 256-entry history of uCode execution within a circular buffer.
5925 5924 * Its header format is:
5926 5925 *
5927 5926 * uint32_t log_size; log capacity (in number of entries)
5928 5927 * uint32_t type; (1) timestamp with each entry, (0) no timestamp
5929 5928 * uint32_t wraps; # times uCode has wrapped to top of circular buffer
5930 5929 * uint32_t write_index; next circular buffer entry that uCode would fill
5931 5930 *
5932 5931 * The header is followed by the circular buffer of log entries. Entries
5933 5932 * with timestamps have the following format:
5934 5933 *
5935 5934 * uint32_t event_id; range 0 - 1500
5936 5935 * uint32_t timestamp; low 32 bits of TSF (of network, if associated)
5937 5936 * uint32_t data; event_id-specific data value
5938 5937 *
5939 5938 * Entries without timestamps contain only event_id and data.
5940 5939 */
5941 5940
5942 5941 /*
5943 5942 * iwk_write_event_log - Write event log to dmesg
5944 5943 */
5945 5944 static void iwk_write_event_log(iwk_sc_t *sc)
5946 5945 {
5947 5946 uint32_t log_event_table_ptr; /* Start address of event table */
5948 5947 uint32_t startptr; /* Start address of log data */
5949 5948 uint32_t logptr; /* address of log data entry */
5950 5949 uint32_t i, n, num_events;
5951 5950 uint32_t event_id, data1, data2; /* log data */
5952 5951
5953 5952 uint32_t log_size; /* log capacity (in number of entries) */
5954 5953 uint32_t type; /* (1)timestamp with each entry,(0) no timestamp */
5955 5954 uint32_t wraps; /* # times uCode has wrapped to */
5956 5955 /* the top of circular buffer */
5957 5956 uint32_t idx; /* index of entry to be filled in next */
5958 5957
5959 5958 log_event_table_ptr = LE_32(sc->sc_card_alive_run.log_event_table_ptr);
5960 5959 if (!(log_event_table_ptr)) {
5961 5960 IWK_DBG((IWK_DEBUG_EEPROM, "NULL event table pointer\n"));
5962 5961 return;
5963 5962 }
5964 5963
5965 5964 iwk_mac_access_enter(sc);
5966 5965
5967 5966 /* Read log header */
5968 5967 log_size = iwk_mem_read(sc, log_event_table_ptr);
5969 5968 log_event_table_ptr += sizeof (uint32_t); /* addr of "type" */
5970 5969 type = iwk_mem_read(sc, log_event_table_ptr);
5971 5970 log_event_table_ptr += sizeof (uint32_t); /* addr of "wraps" */
5972 5971 wraps = iwk_mem_read(sc, log_event_table_ptr);
5973 5972 log_event_table_ptr += sizeof (uint32_t); /* addr of "idx" */
5974 5973 idx = iwk_mem_read(sc, log_event_table_ptr);
5975 5974 startptr = log_event_table_ptr +
5976 5975 sizeof (uint32_t); /* addr of start of log data */
5977 5976 if (!log_size & !wraps) {
5978 5977 IWK_DBG((IWK_DEBUG_EEPROM, "Empty log\n"));
5979 5978 iwk_mac_access_exit(sc);
5980 5979 return;
5981 5980 }
5982 5981
5983 5982 if (!wraps) {
5984 5983 num_events = idx;
5985 5984 logptr = startptr;
5986 5985 } else {
5987 5986 num_events = log_size - idx;
5988 5987 n = type ? 2 : 3;
5989 5988 logptr = startptr + (idx * n * sizeof (uint32_t));
5990 5989 }
5991 5990
5992 5991 for (i = 0; i < num_events; i++) {
5993 5992 event_id = iwk_mem_read(sc, logptr);
5994 5993 logptr += sizeof (uint32_t);
5995 5994 data1 = iwk_mem_read(sc, logptr);
5996 5995 logptr += sizeof (uint32_t);
5997 5996 if (type == 0) { /* no timestamp */
5998 5997 IWK_DBG((IWK_DEBUG_EEPROM, "Event ID=%d, Data=%x0x",
5999 5998 event_id, data1));
6000 5999 } else { /* timestamp */
6001 6000 data2 = iwk_mem_read(sc, logptr);
6002 6001 IWK_DBG((IWK_DEBUG_EEPROM,
6003 6002 "Time=%d, Event ID=%d, Data=0x%x\n",
6004 6003 data1, event_id, data2));
6005 6004 logptr += sizeof (uint32_t);
6006 6005 }
6007 6006 }
6008 6007
6009 6008 /*
6010 6009 * Print the wrapped around entries, if any
6011 6010 */
6012 6011 if (wraps) {
6013 6012 logptr = startptr;
6014 6013 for (i = 0; i < idx; i++) {
6015 6014 event_id = iwk_mem_read(sc, logptr);
6016 6015 logptr += sizeof (uint32_t);
6017 6016 data1 = iwk_mem_read(sc, logptr);
6018 6017 logptr += sizeof (uint32_t);
6019 6018 if (type == 0) { /* no timestamp */
6020 6019 IWK_DBG((IWK_DEBUG_EEPROM,
6021 6020 "Event ID=%d, Data=%x0x", event_id, data1));
6022 6021 } else { /* timestamp */
6023 6022 data2 = iwk_mem_read(sc, logptr);
6024 6023 IWK_DBG((IWK_DEBUG_EEPROM,
6025 6024 "Time = %d, Event ID=%d, Data=0x%x\n",
6026 6025 data1, event_id, data2));
6027 6026 logptr += sizeof (uint32_t);
6028 6027 }
6029 6028 }
6030 6029 }
6031 6030
6032 6031 iwk_mac_access_exit(sc);
6033 6032 }
6034 6033
6035 6034 /*
6036 6035 * error_event_table_ptr indicates base of the error log. This contains
6037 6036 * information about any uCode error that occurs. For 4965, the format is:
6038 6037 *
6039 6038 * uint32_t valid; (nonzero) valid, (0) log is empty
6040 6039 * uint32_t error_id; type of error
6041 6040 * uint32_t pc; program counter
6042 6041 * uint32_t blink1; branch link
6043 6042 * uint32_t blink2; branch link
6044 6043 * uint32_t ilink1; interrupt link
6045 6044 * uint32_t ilink2; interrupt link
6046 6045 * uint32_t data1; error-specific data
6047 6046 * uint32_t data2; error-specific data
6048 6047 * uint32_t line; source code line of error
6049 6048 * uint32_t bcon_time; beacon timer
6050 6049 * uint32_t tsf_low; network timestamp function timer
6051 6050 * uint32_t tsf_hi; network timestamp function timer
6052 6051 */
6053 6052 /*
6054 6053 * iwk_write_error_log - Write error log to dmesg
6055 6054 */
6056 6055 static void iwk_write_error_log(iwk_sc_t *sc)
6057 6056 {
6058 6057 uint32_t err_ptr; /* Start address of error log */
6059 6058 uint32_t valid; /* is error log valid */
6060 6059
6061 6060 err_ptr = LE_32(sc->sc_card_alive_run.error_event_table_ptr);
6062 6061 if (!(err_ptr)) {
6063 6062 IWK_DBG((IWK_DEBUG_EEPROM, "NULL error table pointer\n"));
6064 6063 return;
6065 6064 }
6066 6065
6067 6066 iwk_mac_access_enter(sc);
6068 6067
6069 6068 valid = iwk_mem_read(sc, err_ptr);
6070 6069 if (!(valid)) {
6071 6070 IWK_DBG((IWK_DEBUG_EEPROM, "Error data not valid\n"));
6072 6071 iwk_mac_access_exit(sc);
6073 6072 return;
6074 6073 }
6075 6074 err_ptr += sizeof (uint32_t);
6076 6075 IWK_DBG((IWK_DEBUG_EEPROM, "err=%d ", iwk_mem_read(sc, err_ptr)));
6077 6076 err_ptr += sizeof (uint32_t);
6078 6077 IWK_DBG((IWK_DEBUG_EEPROM, "pc=0x%X ", iwk_mem_read(sc, err_ptr)));
6079 6078 err_ptr += sizeof (uint32_t);
6080 6079 IWK_DBG((IWK_DEBUG_EEPROM,
6081 6080 "branch link1=0x%X ", iwk_mem_read(sc, err_ptr)));
6082 6081 err_ptr += sizeof (uint32_t);
6083 6082 IWK_DBG((IWK_DEBUG_EEPROM,
6084 6083 "branch link2=0x%X ", iwk_mem_read(sc, err_ptr)));
6085 6084 err_ptr += sizeof (uint32_t);
6086 6085 IWK_DBG((IWK_DEBUG_EEPROM,
6087 6086 "interrupt link1=0x%X ", iwk_mem_read(sc, err_ptr)));
6088 6087 err_ptr += sizeof (uint32_t);
6089 6088 IWK_DBG((IWK_DEBUG_EEPROM,
6090 6089 "interrupt link2=0x%X ", iwk_mem_read(sc, err_ptr)));
6091 6090 err_ptr += sizeof (uint32_t);
6092 6091 IWK_DBG((IWK_DEBUG_EEPROM, "data1=0x%X ", iwk_mem_read(sc, err_ptr)));
6093 6092 err_ptr += sizeof (uint32_t);
6094 6093 IWK_DBG((IWK_DEBUG_EEPROM, "data2=0x%X ", iwk_mem_read(sc, err_ptr)));
6095 6094 err_ptr += sizeof (uint32_t);
6096 6095 IWK_DBG((IWK_DEBUG_EEPROM, "line=%d ", iwk_mem_read(sc, err_ptr)));
6097 6096 err_ptr += sizeof (uint32_t);
6098 6097 IWK_DBG((IWK_DEBUG_EEPROM, "bcon_time=%d ", iwk_mem_read(sc, err_ptr)));
6099 6098 err_ptr += sizeof (uint32_t);
6100 6099 IWK_DBG((IWK_DEBUG_EEPROM, "tsf_low=%d ", iwk_mem_read(sc, err_ptr)));
6101 6100 err_ptr += sizeof (uint32_t);
6102 6101 IWK_DBG((IWK_DEBUG_EEPROM, "tsf_hi=%d\n", iwk_mem_read(sc, err_ptr)));
6103 6102
6104 6103 iwk_mac_access_exit(sc);
6105 6104 }
6106 6105
6107 6106 static int
6108 6107 iwk_run_state_config_ibss(ieee80211com_t *ic)
6109 6108 {
6110 6109 iwk_sc_t *sc = (iwk_sc_t *)ic;
6111 6110 ieee80211_node_t *in = ic->ic_bss;
6112 6111 int i, err = IWK_SUCCESS;
6113 6112
6114 6113 mutex_enter(&sc->sc_ibss.node_tb_lock);
6115 6114
6116 6115 /*
6117 6116 * clean all nodes in ibss node table assure be
6118 6117 * consistent with hardware
6119 6118 */
6120 6119 for (i = IWK_STA_ID; i < IWK_STATION_COUNT; i++) {
6121 6120 sc->sc_ibss.ibss_node_tb[i].used = 0;
6122 6121 (void) memset(&sc->sc_ibss.ibss_node_tb[i].node,
6123 6122 0,
6124 6123 sizeof (iwk_add_sta_t));
6125 6124 }
6126 6125
6127 6126 sc->sc_ibss.node_number = 0;
6128 6127
6129 6128 mutex_exit(&sc->sc_ibss.node_tb_lock);
6130 6129
6131 6130 /*
6132 6131 * configure RX and TX
6133 6132 */
6134 6133 sc->sc_config.dev_type = RXON_DEV_TYPE_IBSS;
6135 6134
6136 6135 sc->sc_config.flags |= LE_32(RXON_FLG_SHORT_PREAMBLE_MSK);
6137 6136 sc->sc_config.filter_flags =
6138 6137 LE_32(RXON_FILTER_ACCEPT_GRP_MSK |
6139 6138 RXON_FILTER_DIS_DECRYPT_MSK |
6140 6139 RXON_FILTER_DIS_GRP_DECRYPT_MSK);
6141 6140
6142 6141 sc->sc_config.assoc_id = 0;
6143 6142
6144 6143 IEEE80211_ADDR_COPY(sc->sc_config.bssid, in->in_bssid);
6145 6144 sc->sc_config.chan = LE_16(ieee80211_chan2ieee(ic,
6146 6145 in->in_chan));
6147 6146
6148 6147 if (ic->ic_curmode == IEEE80211_MODE_11B) {
6149 6148 sc->sc_config.cck_basic_rates = 0x03;
6150 6149 sc->sc_config.ofdm_basic_rates = 0;
6151 6150 } else if ((in->in_chan != IEEE80211_CHAN_ANYC) &&
6152 6151 (IEEE80211_IS_CHAN_5GHZ(in->in_chan))) {
6153 6152 sc->sc_config.cck_basic_rates = 0;
6154 6153 sc->sc_config.ofdm_basic_rates = 0x15;
6155 6154
6156 6155 } else {
6157 6156 sc->sc_config.cck_basic_rates = 0x0f;
6158 6157 sc->sc_config.ofdm_basic_rates = 0xff;
6159 6158 }
6160 6159
6161 6160 sc->sc_config.flags &=
6162 6161 ~LE_32(RXON_FLG_SHORT_PREAMBLE_MSK |
6163 6162 RXON_FLG_SHORT_SLOT_MSK);
6164 6163
6165 6164 if (ic->ic_flags & IEEE80211_F_SHSLOT) {
6166 6165 sc->sc_config.flags |=
6167 6166 LE_32(RXON_FLG_SHORT_SLOT_MSK);
6168 6167 }
6169 6168
6170 6169 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) {
6171 6170 sc->sc_config.flags |=
6172 6171 LE_32(RXON_FLG_SHORT_PREAMBLE_MSK);
6173 6172 }
6174 6173
6175 6174 sc->sc_config.filter_flags |=
6176 6175 LE_32(RXON_FILTER_ASSOC_MSK);
6177 6176
6178 6177 err = iwk_cmd(sc, REPLY_RXON, &sc->sc_config,
6179 6178 sizeof (iwk_rxon_cmd_t), 1);
6180 6179 if (err != IWK_SUCCESS) {
6181 6180 cmn_err(CE_WARN, "iwk_run_state_config_ibss(): "
6182 6181 "failed to update configuration.\n");
6183 6182 return (err);
6184 6183 }
6185 6184
6186 6185 return (err);
6187 6186
6188 6187 }
6189 6188
6190 6189 static int
6191 6190 iwk_run_state_config_sta(ieee80211com_t *ic)
6192 6191 {
6193 6192 iwk_sc_t *sc = (iwk_sc_t *)ic;
6194 6193 ieee80211_node_t *in = ic->ic_bss;
6195 6194 int err = IWK_SUCCESS;
6196 6195
6197 6196 /* update adapter's configuration */
6198 6197 if (sc->sc_assoc_id != in->in_associd) {
6199 6198 cmn_err(CE_WARN, "iwk_run_state_config_sta(): "
6200 6199 "associate ID mismatch: expected %d, "
6201 6200 "got %d\n",
6202 6201 in->in_associd, sc->sc_assoc_id);
6203 6202 }
6204 6203 sc->sc_config.assoc_id = LE_16(in->in_associd & 0x3fff);
6205 6204
6206 6205 /*
6207 6206 * short preamble/slot time are
6208 6207 * negotiated when associating
6209 6208 */
6210 6209 sc->sc_config.flags &=
6211 6210 ~LE_32(RXON_FLG_SHORT_PREAMBLE_MSK |
6212 6211 RXON_FLG_SHORT_SLOT_MSK);
6213 6212
6214 6213 if (ic->ic_flags & IEEE80211_F_SHSLOT)
6215 6214 sc->sc_config.flags |=
6216 6215 LE_32(RXON_FLG_SHORT_SLOT_MSK);
6217 6216
6218 6217 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE)
6219 6218 sc->sc_config.flags |=
6220 6219 LE_32(RXON_FLG_SHORT_PREAMBLE_MSK);
6221 6220
6222 6221 sc->sc_config.filter_flags |=
6223 6222 LE_32(RXON_FILTER_ASSOC_MSK);
6224 6223
6225 6224 if (ic->ic_opmode != IEEE80211_M_STA)
6226 6225 sc->sc_config.filter_flags |=
6227 6226 LE_32(RXON_FILTER_BCON_AWARE_MSK);
6228 6227
6229 6228 IWK_DBG((IWK_DEBUG_80211, "config chan %d flags %x"
6230 6229 " filter_flags %x\n",
6231 6230 sc->sc_config.chan, sc->sc_config.flags,
6232 6231 sc->sc_config.filter_flags));
6233 6232
6234 6233 err = iwk_cmd(sc, REPLY_RXON, &sc->sc_config,
6235 6234 sizeof (iwk_rxon_cmd_t), 1);
6236 6235 if (err != IWK_SUCCESS) {
6237 6236 cmn_err(CE_WARN, "iwk_run_state_config_sta(): "
6238 6237 "failed to update configuration\n");
6239 6238 return (err);
6240 6239 }
6241 6240
6242 6241 return (err);
6243 6242 }
6244 6243
6245 6244 static int
6246 6245 iwk_fast_recover(iwk_sc_t *sc)
6247 6246 {
6248 6247 ieee80211com_t *ic = &sc->sc_ic;
6249 6248 int err;
6250 6249
6251 6250 mutex_enter(&sc->sc_glock);
6252 6251
6253 6252 /* restore runtime configuration */
6254 6253 bcopy(&sc->sc_config_save, &sc->sc_config,
6255 6254 sizeof (sc->sc_config));
6256 6255
6257 6256 /* reset state to handle reassociations correctly */
6258 6257 sc->sc_config.assoc_id = 0;
6259 6258 sc->sc_config.filter_flags &=
6260 6259 ~LE_32(RXON_FILTER_ASSOC_MSK);
6261 6260
6262 6261 if ((err = iwk_hw_set_before_auth(sc)) != 0) {
6263 6262 cmn_err(CE_WARN, "iwk_fast_recover(): "
6264 6263 "failed to setup authentication\n");
6265 6264 mutex_exit(&sc->sc_glock);
6266 6265 return (err);
6267 6266 }
6268 6267
6269 6268 bcopy(&sc->sc_config_save, &sc->sc_config,
6270 6269 sizeof (sc->sc_config));
6271 6270
6272 6271 /* update adapter's configuration */
6273 6272 err = iwk_run_state_config_sta(ic);
6274 6273 if (err != IWK_SUCCESS) {
6275 6274 cmn_err(CE_WARN, "iwk_fast_recover(): "
6276 6275 "failed to setup association\n");
6277 6276 mutex_exit(&sc->sc_glock);
6278 6277 return (err);
6279 6278 }
6280 6279
6281 6280 /* obtain current temperature of chipset */
6282 6281 sc->sc_tempera = iwk_curr_tempera(sc);
6283 6282
6284 6283 /*
6285 6284 * make Tx power calibration to determine
6286 6285 * the gains of DSP and radio
6287 6286 */
6288 6287 err = iwk_tx_power_calibration(sc);
6289 6288 if (err) {
6290 6289 cmn_err(CE_WARN, "iwk_fast_recover(): "
6291 6290 "failed to set tx power table\n");
6292 6291 mutex_exit(&sc->sc_glock);
6293 6292 return (err);
6294 6293 }
6295 6294
6296 6295 /*
6297 6296 * make initialization for Receiver
6298 6297 * sensitivity calibration
6299 6298 */
6300 6299 err = iwk_rx_sens_init(sc);
6301 6300 if (err) {
6302 6301 cmn_err(CE_WARN, "iwk_fast_recover(): "
6303 6302 "failed to init RX sensitivity\n");
6304 6303 mutex_exit(&sc->sc_glock);
6305 6304 return (err);
6306 6305 }
6307 6306
6308 6307 /* make initialization for Receiver gain balance */
6309 6308 err = iwk_rxgain_diff_init(sc);
6310 6309 if (err) {
6311 6310 cmn_err(CE_WARN, "iwk_fast_recover(): "
6312 6311 "failed to init phy calibration\n");
6313 6312 mutex_exit(&sc->sc_glock);
6314 6313 return (err);
6315 6314
6316 6315 }
6317 6316 /* set LED on */
6318 6317 iwk_set_led(sc, 2, 0, 1);
6319 6318
6320 6319 mutex_exit(&sc->sc_glock);
6321 6320
6322 6321 /* update keys */
6323 6322 if (ic->ic_flags & IEEE80211_F_PRIVACY) {
6324 6323 for (int i = 0; i < IEEE80211_KEY_MAX; i++) {
6325 6324 if (ic->ic_nw_keys[i].wk_keyix == IEEE80211_KEYIX_NONE)
6326 6325 continue;
6327 6326 err = iwk_key_set(ic, &ic->ic_nw_keys[i],
6328 6327 ic->ic_bss->in_macaddr);
6329 6328 /* failure */
6330 6329 if (err == 0) {
6331 6330 cmn_err(CE_WARN, "iwk_fast_recover(): "
6332 6331 "failed to setup hardware keys\n");
6333 6332 return (IWK_FAIL);
6334 6333 }
6335 6334 }
6336 6335 }
6337 6336
6338 6337 sc->sc_flags &= ~IWK_F_HW_ERR_RECOVER;
6339 6338
6340 6339 /* start queue */
6341 6340 IWK_DBG((IWK_DEBUG_FW, "iwk_fast_recover(): resume xmit\n"));
6342 6341 mac_tx_update(ic->ic_mach);
6343 6342
6344 6343
6345 6344 return (IWK_SUCCESS);
6346 6345 }
6347 6346
6348 6347 static int
6349 6348 iwk_start_tx_beacon(ieee80211com_t *ic)
6350 6349 {
6351 6350 iwk_sc_t *sc = (iwk_sc_t *)ic;
6352 6351 ieee80211_node_t *in = ic->ic_bss;
6353 6352 int err = IWK_SUCCESS;
6354 6353 iwk_tx_beacon_cmd_t *tx_beacon_p;
6355 6354 uint16_t masks = 0;
6356 6355 mblk_t *mp;
6357 6356 int rate;
6358 6357
6359 6358 /*
6360 6359 * allocate and transmit beacon frames
6361 6360 */
6362 6361 tx_beacon_p = &sc->sc_ibss.ibss_beacon.beacon_cmd;
6363 6362
6364 6363 (void) memset(tx_beacon_p, 0,
6365 6364 sizeof (iwk_tx_beacon_cmd_t));
6366 6365 rate = 0;
6367 6366 masks = 0;
6368 6367
6369 6368 tx_beacon_p->config.sta_id = IWK_BROADCAST_ID;
6370 6369 tx_beacon_p->config.stop_time.life_time =
6371 6370 LE_32(0xffffffff);
6372 6371
6373 6372 if (sc->sc_ibss.ibss_beacon.mp != NULL) {
6374 6373 freemsg(sc->sc_ibss.ibss_beacon.mp);
6375 6374 sc->sc_ibss.ibss_beacon.mp = NULL;
6376 6375 }
6377 6376
6378 6377 sc->sc_ibss.ibss_beacon.mp =
6379 6378 ieee80211_beacon_alloc(ic, in,
6380 6379 &sc->sc_ibss.ibss_beacon.iwk_boff);
6381 6380 if (sc->sc_ibss.ibss_beacon.mp == NULL) {
6382 6381 cmn_err(CE_WARN, "iwk_start_tx_beacon(): "
6383 6382 "failed to get beacon frame.\n");
6384 6383 return (IWK_FAIL);
6385 6384 }
6386 6385
6387 6386 mp = sc->sc_ibss.ibss_beacon.mp;
6388 6387
6389 6388 ASSERT(mp->b_cont == NULL);
6390 6389
6391 6390 bcopy(mp->b_rptr, tx_beacon_p->bcon_frame, MBLKL(mp));
6392 6391
6393 6392 tx_beacon_p->config.len = LE_16((uint16_t)(MBLKL(mp)));
6394 6393 sc->sc_ibss.ibss_beacon.beacon_cmd_len =
6395 6394 sizeof (iwk_tx_cmd_t) +
6396 6395 4 + LE_16(tx_beacon_p->config.len);
6397 6396
6398 6397 /*
6399 6398 * beacons are sent at 1M
6400 6399 */
6401 6400 rate = in->in_rates.ir_rates[0];
6402 6401 rate &= IEEE80211_RATE_VAL;
6403 6402
6404 6403 if (2 == rate || 4 == rate || 11 == rate ||
6405 6404 22 == rate) {
6406 6405 masks |= RATE_MCS_CCK_MSK;
6407 6406 }
6408 6407
6409 6408 masks |= RATE_MCS_ANT_B_MSK;
6410 6409
6411 6410 tx_beacon_p->config.rate.r.rate_n_flags =
6412 6411 LE_32(iwk_rate_to_plcp(rate) | masks);
6413 6412
6414 6413
6415 6414 tx_beacon_p->config.tx_flags =
6416 6415 LE_32(TX_CMD_FLG_SEQ_CTL_MSK | TX_CMD_FLG_TSF_MSK);
6417 6416
6418 6417 if (ic->ic_bss->in_tstamp.tsf != 0) {
6419 6418 sc->sc_ibss.ibss_beacon.syncbeacon = 1;
6420 6419 } else {
6421 6420 if (ieee80211_beacon_update(ic, in,
6422 6421 &sc->sc_ibss.ibss_beacon.iwk_boff,
6423 6422 mp, 0)) {
6424 6423 bcopy(mp->b_rptr,
6425 6424 tx_beacon_p->bcon_frame,
6426 6425 MBLKL(mp));
6427 6426 }
6428 6427
6429 6428 err = iwk_cmd(sc, REPLY_TX_BEACON,
6430 6429 tx_beacon_p,
6431 6430 sc->sc_ibss.ibss_beacon.beacon_cmd_len,
6432 6431 1);
6433 6432 if (err != IWK_SUCCESS) {
6434 6433 cmn_err(CE_WARN, "iwk_start_tx_beacon(): "
6435 6434 "failed to TX beacon.\n");
6436 6435 return (err);
6437 6436 }
6438 6437
6439 6438 sc->sc_ibss.ibss_beacon.syncbeacon = 0;
6440 6439 }
6441 6440
6442 6441 return (err);
6443 6442 }
6444 6443
6445 6444 static int
6446 6445 iwk_clean_add_node_ibss(struct ieee80211com *ic,
6447 6446 uint8_t addr[IEEE80211_ADDR_LEN], uint8_t *index2)
6448 6447 {
6449 6448 iwk_sc_t *sc = (iwk_sc_t *)ic;
6450 6449 uint8_t index;
6451 6450 iwk_add_sta_t bc_node;
6452 6451 iwk_link_quality_cmd_t bc_link_quality;
6453 6452 iwk_link_quality_cmd_t link_quality;
6454 6453 uint16_t bc_masks = 0;
6455 6454 uint16_t masks = 0;
6456 6455 int i, rate;
6457 6456 struct ieee80211_rateset rs;
6458 6457 iwk_ibss_node_t *ibss_node_p;
6459 6458 int err = IWK_SUCCESS;
6460 6459
6461 6460 /*
6462 6461 * find a location that is not
6463 6462 * used in ibss node table
6464 6463 */
6465 6464 for (index = IWK_STA_ID;
6466 6465 index < IWK_STATION_COUNT; index++) {
6467 6466 if (!sc->sc_ibss.ibss_node_tb[index].used) {
6468 6467 break;
6469 6468 }
6470 6469 }
6471 6470
6472 6471 /*
6473 6472 * if have too many nodes in hardware, clean up
6474 6473 */
6475 6474 if (index < IWK_BROADCAST_ID &&
6476 6475 sc->sc_ibss.node_number >= 25) {
6477 6476 if (iwk_cmd(sc, REPLY_REMOVE_ALL_STA,
6478 6477 NULL, 0, 1) != IWK_SUCCESS) {
6479 6478 cmn_err(CE_WARN, "iwk_clean_add_node_ibss(): "
6480 6479 "failed to remove all nodes in hardware\n");
6481 6480 return (IWK_FAIL);
6482 6481 }
6483 6482
6484 6483 for (i = IWK_STA_ID; i < IWK_STATION_COUNT; i++) {
6485 6484 sc->sc_ibss.ibss_node_tb[i].used = 0;
6486 6485 (void) memset(&sc->sc_ibss.ibss_node_tb[i].node,
6487 6486 0, sizeof (iwk_add_sta_t));
6488 6487 }
6489 6488
6490 6489 sc->sc_ibss.node_number = 0;
6491 6490
6492 6491 /*
6493 6492 * add broadcast node so that we
6494 6493 * can send broadcast frame
6495 6494 */
6496 6495 (void) memset(&bc_node, 0, sizeof (bc_node));
6497 6496 (void) memset(bc_node.bssid, 0xff, 6);
6498 6497 bc_node.id = IWK_BROADCAST_ID;
6499 6498
6500 6499 err = iwk_cmd(sc, REPLY_ADD_STA, &bc_node, sizeof (bc_node), 1);
6501 6500 if (err != IWK_SUCCESS) {
6502 6501 cmn_err(CE_WARN, "iwk_clean_add_node_ibss(): "
6503 6502 "failed to add broadcast node\n");
6504 6503 return (err);
6505 6504 }
6506 6505
6507 6506 /* TX_LINK_QUALITY cmd */
6508 6507 (void) memset(&bc_link_quality, 0, sizeof (bc_link_quality));
6509 6508 for (i = 0; i < LINK_QUAL_MAX_RETRY_NUM; i++) {
6510 6509 bc_masks |= RATE_MCS_CCK_MSK;
6511 6510 bc_masks |= RATE_MCS_ANT_B_MSK;
6512 6511 bc_masks &= ~RATE_MCS_ANT_A_MSK;
6513 6512 bc_link_quality.rate_n_flags[i] =
6514 6513 LE_32(iwk_rate_to_plcp(2) | bc_masks);
6515 6514 }
6516 6515
6517 6516 bc_link_quality.general_params.single_stream_ant_msk = 2;
6518 6517 bc_link_quality.general_params.dual_stream_ant_msk = 3;
6519 6518 bc_link_quality.agg_params.agg_dis_start_th = 3;
6520 6519 bc_link_quality.agg_params.agg_time_limit = LE_16(4000);
6521 6520 bc_link_quality.sta_id = IWK_BROADCAST_ID;
6522 6521
6523 6522 err = iwk_cmd(sc, REPLY_TX_LINK_QUALITY_CMD,
6524 6523 &bc_link_quality, sizeof (bc_link_quality), 1);
6525 6524 if (err != IWK_SUCCESS) {
6526 6525 cmn_err(CE_WARN, "iwk_clean_add_node_ibss(): "
6527 6526 "failed to config link quality table\n");
6528 6527 return (err);
6529 6528 }
6530 6529 }
6531 6530
6532 6531 if (index >= IWK_BROADCAST_ID) {
6533 6532 cmn_err(CE_WARN, "iwk_clean_add_node_ibss(): "
6534 6533 "the count of node in hardware is too much\n");
6535 6534 return (IWK_FAIL);
6536 6535 }
6537 6536
6538 6537 /*
6539 6538 * add a node into hardware
6540 6539 */
6541 6540 ibss_node_p = &sc->sc_ibss.ibss_node_tb[index];
6542 6541
6543 6542 ibss_node_p->used = 1;
6544 6543
6545 6544 (void) memset(&ibss_node_p->node, 0,
6546 6545 sizeof (iwk_add_sta_t));
6547 6546
6548 6547 IEEE80211_ADDR_COPY(ibss_node_p->node.bssid, addr);
6549 6548 ibss_node_p->node.id = index;
6550 6549 ibss_node_p->node.control = 0;
6551 6550 ibss_node_p->node.flags = 0;
6552 6551
6553 6552 err = iwk_cmd(sc, REPLY_ADD_STA, &ibss_node_p->node,
6554 6553 sizeof (iwk_add_sta_t), 1);
6555 6554 if (err != IWK_SUCCESS) {
6556 6555 cmn_err(CE_WARN, "iwk_clean_add_node_ibss(): "
6557 6556 "failed to add IBSS node\n");
6558 6557 ibss_node_p->used = 0;
6559 6558 (void) memset(&ibss_node_p->node, 0,
6560 6559 sizeof (iwk_add_sta_t));
6561 6560 return (err);
6562 6561 }
6563 6562
6564 6563 sc->sc_ibss.node_number++;
6565 6564
6566 6565 (void) memset(&link_quality, 0, sizeof (link_quality));
6567 6566
6568 6567 rs = ic->ic_sup_rates[ieee80211_chan2mode(ic,
6569 6568 ic->ic_curchan)];
6570 6569
6571 6570 for (i = 0; i < LINK_QUAL_MAX_RETRY_NUM; i++) {
6572 6571 if (i < rs.ir_nrates) {
6573 6572 rate = rs.
6574 6573 ir_rates[rs.ir_nrates - i];
6575 6574 } else {
6576 6575 rate = 2;
6577 6576 }
6578 6577
6579 6578 if (2 == rate || 4 == rate ||
6580 6579 11 == rate || 22 == rate) {
6581 6580 masks |= RATE_MCS_CCK_MSK;
6582 6581 }
6583 6582
6584 6583 masks |= RATE_MCS_ANT_B_MSK;
6585 6584 masks &= ~RATE_MCS_ANT_A_MSK;
6586 6585
6587 6586 link_quality.rate_n_flags[i] =
6588 6587 LE_32(iwk_rate_to_plcp(rate) | masks);
6589 6588 }
6590 6589
6591 6590 link_quality.general_params.single_stream_ant_msk = 2;
6592 6591 link_quality.general_params.dual_stream_ant_msk = 3;
6593 6592 link_quality.agg_params.agg_dis_start_th = 3;
6594 6593 link_quality.agg_params.agg_time_limit = LE_16(4000);
6595 6594 link_quality.sta_id = ibss_node_p->node.id;
6596 6595
6597 6596 err = iwk_cmd(sc, REPLY_TX_LINK_QUALITY_CMD,
6598 6597 &link_quality, sizeof (link_quality), 1);
6599 6598 if (err != IWK_SUCCESS) {
6600 6599 cmn_err(CE_WARN, "iwk_clean_add_node_ibss(): "
6601 6600 "failed to set up TX link quality\n");
6602 6601 ibss_node_p->used = 0;
6603 6602 (void) memset(ibss_node_p->node.bssid, 0, 6);
6604 6603 return (err);
6605 6604 }
6606 6605
6607 6606 *index2 = index;
6608 6607
6609 6608 return (err);
6610 6609 }
|
↓ open down ↓ |
6211 lines elided |
↑ open up ↑ |
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX