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7127 remove -Wno-missing-braces from Makefile.uts
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--- old/usr/src/uts/common/io/ecpp.c
+++ new/usr/src/uts/common/io/ecpp.c
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21 /*
22 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
23 23 * Use is subject to license terms.
24 24 */
25 25
26 26
27 27 /*
28 28 *
29 29 * IEEE 1284 Parallel Port Device Driver
30 30 *
31 31 */
32 32
33 33 #include <sys/param.h>
34 34 #include <sys/errno.h>
35 35 #include <sys/file.h>
36 36 #include <sys/cmn_err.h>
37 37 #include <sys/stropts.h>
38 38 #include <sys/debug.h>
39 39 #include <sys/stream.h>
40 40 #include <sys/strsun.h>
41 41 #include <sys/kmem.h>
42 42 #include <sys/ddi.h>
43 43 #include <sys/sunddi.h>
44 44 #include <sys/conf.h> /* req. by dev_ops flags MTSAFE etc. */
45 45 #include <sys/modctl.h> /* for modldrv */
46 46 #include <sys/stat.h> /* ddi_create_minor_node S_IFCHR */
47 47 #include <sys/open.h>
48 48 #include <sys/ddi_impldefs.h>
49 49 #include <sys/kstat.h>
50 50
51 51 #include <sys/prnio.h>
52 52 #include <sys/ecppreg.h> /* hw description */
53 53 #include <sys/ecppio.h> /* ioctl description */
54 54 #include <sys/ecppvar.h> /* driver description */
55 55 #include <sys/dma_engine.h>
56 56 #include <sys/dma_i8237A.h>
57 57
58 58 /*
59 59 * Background
60 60 * ==========
61 61 * IEEE 1284-1994 standard defines "a signalling method for asynchronous,
62 62 * fully interlocked, bidirectional parallel communications between hosts
63 63 * and printers or other peripherals." (1.1) The standard defines 5 modes
64 64 * of operation - Compatibility, Nibble, Byte, ECP and EPP - which differ
65 65 * in direction, bandwidth, pins assignment, DMA capability, etc.
66 66 *
67 67 * Negotiation is a mechanism for moving between modes. Compatibility mode
68 68 * is a default mode, from which negotiations to other modes occur and
69 69 * to which both host and peripheral break in case of interface errors.
70 70 * Compatibility mode provides a unidirectional (forward) channel for
71 71 * communicating with old pre-1284 peripherals.
72 72 *
73 73 * Each mode has a number of phases. [Mode, phase] pair represents the
74 74 * interface state. Host initiates all transfers, though peripheral can
75 75 * request backchannel transfer by asserting nErr pin.
76 76 *
77 77 * Ecpp driver implements an IEEE 1284-compliant host using a combination
78 78 * of hardware and software. Hardware part is represented by a controller,
79 79 * which is a part of the SuperIO chip. Ecpp supports the following SuperIOs:
80 80 * PC82332/PC82336 (U5/U10/U60), PC97317 (U100), M1553 (Grover).
81 81 * Struct ecpp_hw describes each SuperIO and is determined in ecpp_attach().
82 82 *
83 83 * Negotiation is performed in software. Transfer may be performed either
84 84 * in software by driving output pins for each byte (PIO method), or with
85 85 * hardware assistance - SuperIO has a 16-byte FIFO, which is filled by
86 86 * the driver (normally using DMA), while the chip performs the actual xfer.
87 87 * PIO is used for Nibble and Compat, DMA is used for ECP and Compat modes.
88 88 *
89 89 * Driver currently supports the following modes:
90 90 *
91 91 * - Compatibility mode: byte-wide forward channel ~50KB/sec;
92 92 * pp->io_mode defines PIO or DMA method of transfer;
93 93 * - Nibble mode: nibble-wide (4-bit) reverse channel ~30KB/sec;
94 94 * - ECP mode: byte-wide bidirectional channel (~1MB/sec);
95 95 *
96 96 * Theory of operation
97 97 * ===================
98 98 * The manner in which ecpp drives 1284 interface is that of a state machine.
99 99 * State is a combination of 1284 mode {ECPP_*_MODE}, 1284 phase {ECPP_PHASE_*}
100 100 * and transfer method {PIO, DMA}. State is a function of application actions
101 101 * {write(2), ioctl(2)} and peripheral reaction.
102 102 *
103 103 * 1284 interface state is described by the following variables:
104 104 * pp->current_mode -- 1284 mode used for forward transfers;
105 105 * pp->backchannel -- 1284 mode used for backward transfers;
106 106 * pp->curent_phase -- 1284 phase;
107 107 *
108 108 * Bidirectional operation in Compatibility mode is provided by a combination:
109 109 * pp->current_mode == ECPP_COMPAT_MODE && pp->backchannel == ECPP_NIBBLE_MODE
110 110 * ECPP_CENTRONICS means no backchannel
111 111 *
112 112 * Driver internal state is defined by pp->e_busy as follows:
113 113 * ECPP_IDLE -- idle, no active transfers;
114 114 * ECPP_BUSY -- transfer is in progress;
115 115 * ECPP_ERR -- have data to transfer, but peripheral can`t receive data;
116 116 * ECPP_FLUSH -- flushing the queues;
117 117 *
118 118 * When opened, driver is in ECPP_IDLE state, current mode is ECPP_CENTRONICS
119 119 * Default negotiation tries to negotiate to the best mode supported by printer,
120 120 * sets pp->current_mode and pp->backchannel accordingly.
121 121 *
122 122 * When output data arrives in M_DATA mblks ecpp_wput() puts them on the queue
123 123 * to let ecpp_wsrv() concatenate small blocks into one big transfer
124 124 * by copying them into pp->ioblock. If first the mblk data is bigger than
125 125 * pp->ioblock, then it is used instead of i/o block (pointed by pp->msg)
126 126 *
127 127 * Before starting the transfer the driver will check if peripheral is ready
128 128 * by calling ecpp_check_status() and if it is not, driver goes ECPP_ERR state
129 129 * and schedules ecpp_wsrv_timer() which would qenable() the wq, effectively
130 130 * rechecking the peripheral readiness and restarting itself until it is ready.
131 131 * The transfer is then started by calling ecpp_start(), driver goes ECPP_BUSY
132 132 *
133 133 * While transfer is in progress all arriving messages will be queued up.
134 134 * Transfer can end up in either of two ways:
135 135 * - interrupt occurs, ecpp_isr() checks if all the data was transferred, if so
136 136 * cleanup and go ECPP_IDLE, otherwise putback untransferred and qenable();
137 137 * - ecpp_xfer_timeout() cancels the transfer and puts back untransferred data;
138 138 *
139 139 * PIO transfer method is very CPU intensive: for each sent byte the peripheral
140 140 * state is checked, then the byte is transfered and driver waits for an nAck
141 141 * interrupt; ecpp_isr() will then look if there is more data and if so
142 142 * triggers the soft interrupt, which transfers the next byte. PIO method
143 143 * is needed only for legacy printers which are sensitive to strobe problem
144 144 * (Bugid 4192788).
145 145 *
146 146 * ecpp_wsrv() is responsible for both starting transfers (ecpp_start()) and
147 147 * going idle (ecpp_idle_phase()). Many routines qenable() the write queue,
148 148 * meaning "check if there are pending requests, process them and go idle".
149 149 *
150 150 * In it`s idle state the driver will always try to listen to the backchannel
151 151 * (as advised by 1284).
152 152 *
153 153 * The mechanism for handling backchannel requests is as follows:
154 154 * - when the peripheral has data to send it asserts nErr pin
155 155 * (and also nAck in Nibble Mode) which results in an interrupt on the host;
156 156 * - ISR creates M_CTL message containing an ECPP_BACKCHANNEL byte and
157 157 * puts it back on the write queue;
158 158 * - ecpp_wsrv() gets M_CTL and calls ecpp_peripheral2host(), which kicks off
159 159 * the transfer;
160 160 *
161 161 * This way Nibble and ECP mode backchannel are implemented.
162 162 * If the read queue gets full, backchannel request is rejected.
163 163 * As the application reads data and queue size falls below the low watermark,
164 164 * ecpp_rsrv() gets called and enables the backchannel again.
165 165 *
166 166 * Future enhancements
167 167 * ===================
168 168 *
169 169 * Support new modes: Byte and EPP.
170 170 */
171 171
172 172 #ifndef ECPP_DEBUG
173 173 #define ECPP_DEBUG 0
174 174 #endif /* ECPP_DEBUG */
175 175 int ecpp_debug = ECPP_DEBUG;
176 176
177 177 int noecp = 0; /* flag not to use ECP mode */
178 178
179 179 /* driver entry point fn definitions */
180 180 static int ecpp_open(queue_t *, dev_t *, int, int, cred_t *);
181 181 static int ecpp_close(queue_t *, int, cred_t *);
182 182 static uint_t ecpp_isr(caddr_t);
183 183 static uint_t ecpp_softintr(caddr_t);
184 184
185 185 /* configuration entry point fn definitions */
186 186 static int ecpp_getinfo(dev_info_t *, ddi_info_cmd_t, void *, void **);
187 187 static int ecpp_attach(dev_info_t *, ddi_attach_cmd_t);
188 188 static int ecpp_detach(dev_info_t *, ddi_detach_cmd_t);
189 189 static struct ecpp_hw_bind *ecpp_determine_sio_type(struct ecppunit *);
190 190
191 191 /* isr support routines */
192 192 static uint_t ecpp_nErr_ihdlr(struct ecppunit *);
193 193 static uint_t ecpp_pio_ihdlr(struct ecppunit *);
194 194 static uint_t ecpp_dma_ihdlr(struct ecppunit *);
195 195 static uint_t ecpp_M1553_intr(struct ecppunit *);
196 196
197 197 /* configuration support routines */
198 198 static void ecpp_get_props(struct ecppunit *);
199 199
200 200 /* Streams Routines */
201 201 static int ecpp_wput(queue_t *, mblk_t *);
202 202 static int ecpp_wsrv(queue_t *);
203 203 static int ecpp_rsrv(queue_t *);
204 204 static void ecpp_flush(struct ecppunit *, int);
205 205 static void ecpp_start(struct ecppunit *, caddr_t, size_t);
206 206
207 207 /* ioctl handling */
208 208 static void ecpp_putioc(queue_t *, mblk_t *);
209 209 static void ecpp_srvioc(queue_t *, mblk_t *);
210 210 static void ecpp_wput_iocdata_devid(queue_t *, mblk_t *, uintptr_t);
211 211 static void ecpp_putioc_copyout(queue_t *, mblk_t *, void *, int);
212 212 static void ecpp_putioc_stateful_copyin(queue_t *, mblk_t *, size_t);
213 213 static void ecpp_srvioc_devid(queue_t *, mblk_t *,
214 214 struct ecpp_device_id *, int *);
215 215 static void ecpp_srvioc_prnif(queue_t *, mblk_t *);
216 216 static void ecpp_ack_ioctl(queue_t *, mblk_t *);
217 217 static void ecpp_nack_ioctl(queue_t *, mblk_t *, int);
218 218
219 219 /* kstat routines */
220 220 static void ecpp_kstat_init(struct ecppunit *);
221 221 static int ecpp_kstat_update(kstat_t *, int);
222 222 static int ecpp_kstatintr_update(kstat_t *, int);
223 223
224 224 /* dma routines */
225 225 static void ecpp_putback_untransfered(struct ecppunit *, void *, uint_t);
226 226 static uint8_t ecpp_setup_dma_resources(struct ecppunit *, caddr_t, size_t);
227 227 static uint8_t ecpp_init_dma_xfer(struct ecppunit *, caddr_t, size_t);
228 228
229 229 /* pio routines */
230 230 static void ecpp_pio_writeb(struct ecppunit *);
231 231 static void ecpp_xfer_cleanup(struct ecppunit *);
232 232 static uint8_t ecpp_prep_pio_xfer(struct ecppunit *, caddr_t, size_t);
233 233
234 234 /* misc */
235 235 static uchar_t ecpp_reset_port_regs(struct ecppunit *);
236 236 static void ecpp_xfer_timeout(void *);
237 237 static void ecpp_fifo_timer(void *);
238 238 static void ecpp_wsrv_timer(void *);
239 239 static uchar_t dcr_write(struct ecppunit *, uint8_t);
240 240 static uchar_t ecr_write(struct ecppunit *, uint8_t);
241 241 static uchar_t ecpp_check_status(struct ecppunit *);
242 242 static int ecpp_backchan_req(struct ecppunit *);
243 243 static void ecpp_untimeout_unblock(struct ecppunit *, timeout_id_t *);
244 244 static uint_t ecpp_get_prn_ifcap(struct ecppunit *);
245 245
246 246 /* stubs */
247 247 static void empty_config_mode(struct ecppunit *);
248 248 static void empty_mask_intr(struct ecppunit *);
249 249
250 250 /* PC87332 support */
251 251 static int pc87332_map_regs(struct ecppunit *);
252 252 static void pc87332_unmap_regs(struct ecppunit *);
253 253 static int pc87332_config_chip(struct ecppunit *);
254 254 static void pc87332_config_mode(struct ecppunit *);
255 255 static uint8_t pc87332_read_config_reg(struct ecppunit *, uint8_t);
256 256 static void pc87332_write_config_reg(struct ecppunit *, uint8_t, uint8_t);
257 257 static void cheerio_mask_intr(struct ecppunit *);
258 258 static void cheerio_unmask_intr(struct ecppunit *);
259 259 static int cheerio_dma_start(struct ecppunit *);
260 260 static int cheerio_dma_stop(struct ecppunit *, size_t *);
261 261 static size_t cheerio_getcnt(struct ecppunit *);
262 262 static void cheerio_reset_dcsr(struct ecppunit *);
263 263
264 264 /* PC97317 support */
265 265 static int pc97317_map_regs(struct ecppunit *);
266 266 static void pc97317_unmap_regs(struct ecppunit *);
267 267 static int pc97317_config_chip(struct ecppunit *);
268 268 static void pc97317_config_mode(struct ecppunit *);
269 269
270 270 /* M1553 Southbridge support */
271 271 static int m1553_map_regs(struct ecppunit *pp);
272 272 static void m1553_unmap_regs(struct ecppunit *pp);
273 273 static int m1553_config_chip(struct ecppunit *);
274 274 static uint8_t m1553_read_config_reg(struct ecppunit *, uint8_t);
275 275 static void m1553_write_config_reg(struct ecppunit *, uint8_t, uint8_t);
276 276
277 277 /* M1553 Southbridge DMAC 8237 support routines */
278 278 static int dma8237_dma_start(struct ecppunit *);
279 279 static int dma8237_dma_stop(struct ecppunit *, size_t *);
280 280 static size_t dma8237_getcnt(struct ecppunit *);
281 281 static void dma8237_write_addr(struct ecppunit *, uint32_t);
282 282 static void dma8237_write_count(struct ecppunit *, uint32_t);
283 283 static uint32_t dma8237_read_count(struct ecppunit *);
284 284 static void dma8237_write(struct ecppunit *, int, uint8_t);
285 285 static uint8_t dma8237_read(struct ecppunit *, int);
286 286 #ifdef INCLUDE_DMA8237_READ_ADDR
287 287 static uint32_t dma8237_read_addr(struct ecppunit *);
288 288 #endif
289 289
290 290 /* i86 PC support rountines */
291 291
292 292 #if defined(__x86)
293 293 static int x86_dma_start(struct ecppunit *);
294 294 static int x86_dma_stop(struct ecppunit *, size_t *);
295 295 static int x86_map_regs(struct ecppunit *);
296 296 static void x86_unmap_regs(struct ecppunit *);
297 297 static int x86_config_chip(struct ecppunit *);
298 298 static size_t x86_getcnt(struct ecppunit *);
299 299 #endif
300 300
301 301 /* IEEE 1284 phase transitions */
302 302 static void ecpp_1284_init_interface(struct ecppunit *);
303 303 static int ecpp_1284_termination(struct ecppunit *);
304 304 static uchar_t ecpp_idle_phase(struct ecppunit *);
305 305 static int ecp_forward2reverse(struct ecppunit *);
306 306 static int ecp_reverse2forward(struct ecppunit *);
307 307 static int read_nibble_backchan(struct ecppunit *);
308 308
309 309 /* reverse transfers */
310 310 static uint_t ecpp_peripheral2host(struct ecppunit *);
311 311 static uchar_t ecp_peripheral2host(struct ecppunit *);
312 312 static uchar_t nibble_peripheral2host(struct ecppunit *pp, uint8_t *);
313 313 static int ecpp_getdevid(struct ecppunit *, uint8_t *, int *, int);
314 314 static void ecpp_ecp_read_timeout(void *);
315 315 static void ecpp_ecp_read_completion(struct ecppunit *);
316 316
317 317 /* IEEE 1284 mode transitions */
318 318 static void ecpp_default_negotiation(struct ecppunit *);
319 319 static int ecpp_mode_negotiation(struct ecppunit *, uchar_t);
320 320 static int ecpp_1284_negotiation(struct ecppunit *, uint8_t, uint8_t *);
321 321 static int ecp_negotiation(struct ecppunit *);
322 322 static int nibble_negotiation(struct ecppunit *);
323 323 static int devidnib_negotiation(struct ecppunit *);
324 324
325 325 /* IEEE 1284 utility routines */
326 326 static int wait_dsr(struct ecppunit *, uint8_t, uint8_t, int);
327 327
328 328 /* debugging functions */
329 329 static void ecpp_error(dev_info_t *, char *, ...);
330 330 static uchar_t ecpp_get_error_status(uchar_t);
331 331
332 332 /*
333 333 * Chip-dependent structures
334 334 */
335 335 static ddi_dma_attr_t cheerio_dma_attr = {
336 336 DMA_ATTR_VERSION, /* version */
337 337 0x00000000ull, /* dlim_addr_lo */
338 338 0xfffffffeull, /* dlim_addr_hi */
339 339 0xffffff, /* DMA counter register */
340 340 1, /* DMA address alignment */
341 341 0x74, /* burst sizes */
342 342 0x0001, /* min effective DMA size */
343 343 0xffff, /* maximum transfer size */
344 344 0xffff, /* segment boundary */
345 345 1, /* s/g list length */
346 346 1, /* granularity of device */
347 347 0 /* DMA flags */
348 348 };
349 349
350 350 static struct ecpp_hw pc87332 = {
351 351 pc87332_map_regs,
352 352 pc87332_unmap_regs,
353 353 pc87332_config_chip,
354 354 pc87332_config_mode,
355 355 cheerio_mask_intr,
356 356 cheerio_unmask_intr,
357 357 cheerio_dma_start,
358 358 cheerio_dma_stop,
359 359 cheerio_getcnt,
360 360 &cheerio_dma_attr
361 361 };
362 362
363 363 static struct ecpp_hw pc97317 = {
364 364 pc97317_map_regs,
365 365 pc97317_unmap_regs,
366 366 pc97317_config_chip,
367 367 pc97317_config_mode,
368 368 cheerio_mask_intr,
369 369 cheerio_unmask_intr,
370 370 cheerio_dma_start,
371 371 cheerio_dma_stop,
372 372 cheerio_getcnt,
373 373 &cheerio_dma_attr
374 374 };
375 375
376 376 static ddi_dma_attr_t i8237_dma_attr = {
377 377 DMA_ATTR_VERSION, /* version */
378 378 0x00000000ull, /* dlim_addr_lo */
379 379 0xfffffffeull, /* dlim_addr_hi */
380 380 0xffff, /* DMA counter register */
381 381 1, /* DMA address alignment */
382 382 0x01, /* burst sizes */
383 383 0x0001, /* min effective DMA size */
384 384 0xffff, /* maximum transfer size */
385 385 0x7fff, /* segment boundary */
386 386 1, /* s/g list length */
387 387 1, /* granularity of device */
388 388 0 /* DMA flags */
389 389 };
390 390
391 391 static struct ecpp_hw m1553 = {
392 392 m1553_map_regs,
393 393 m1553_unmap_regs,
394 394 m1553_config_chip,
395 395 empty_config_mode, /* no config_mode */
396 396 empty_mask_intr, /* no mask_intr */
397 397 empty_mask_intr, /* no unmask_intr */
398 398 dma8237_dma_start,
399 399 dma8237_dma_stop,
400 400 dma8237_getcnt,
401 401 &i8237_dma_attr
402 402 };
403 403
404 404 #if defined(__x86)
405 405 static ddi_dma_attr_t sb_dma_attr = {
406 406 DMA_ATTR_VERSION, /* version */
407 407 0x00000000ull, /* dlim_addr_lo */
408 408 0xffffff, /* dlim_addr_hi */
409 409 0xffff, /* DMA counter register */
410 410 1, /* DMA address alignment */
411 411 0x01, /* burst sizes */
412 412 0x0001, /* min effective DMA size */
413 413 0xffffffff, /* maximum transfer size */
414 414 0xffff, /* segment boundary */
415 415 1, /* s/g list length */
416 416 1, /* granularity of device */
417 417 0 /* DMA flags */
418 418 };
419 419
420 420 static struct ecpp_hw x86 = {
421 421 x86_map_regs,
422 422 x86_unmap_regs,
423 423 x86_config_chip,
424 424 empty_config_mode, /* no config_mode */
425 425 empty_mask_intr, /* no mask_intr */
426 426 empty_mask_intr, /* no unmask_intr */
427 427 x86_dma_start,
428 428 x86_dma_stop,
429 429 x86_getcnt,
430 430 &sb_dma_attr
431 431 };
432 432 #endif
433 433
434 434 /*
435 435 * list of supported devices
436 436 */
437 437 struct ecpp_hw_bind ecpp_hw_bind[] = {
438 438 { "ns87317-ecpp", &pc97317, "PC97317" },
439 439 { "pnpALI,1533,3", &m1553, "M1553" },
440 440 { "ecpp", &pc87332, "PC87332" },
441 441 #if defined(__x86)
442 442 { "lp", &x86, "i86pc"},
443 443 #endif
444 444 };
445 445
446 446 static ddi_device_acc_attr_t acc_attr = {
447 447 DDI_DEVICE_ATTR_V0,
448 448 DDI_STRUCTURE_LE_ACC,
449 449 DDI_STRICTORDER_ACC
450 450 };
451 451
452 452 static struct ecpp_transfer_parms default_xfer_parms = {
453 453 FWD_TIMEOUT_DEFAULT, /* write timeout in seconds */
454 454 ECPP_CENTRONICS /* supported mode */
455 455 };
456 456
457 457 /* prnio interface info string */
458 458 static const char prn_ifinfo[] = PRN_PARALLEL;
459 459
460 460 /* prnio timeouts */
461 461 static const struct prn_timeouts prn_timeouts_default = {
462 462 FWD_TIMEOUT_DEFAULT, /* forward timeout */
463 463 REV_TIMEOUT_DEFAULT /* reverse timeout */
464 464 };
465 465
466 466 static int ecpp_isr_max_delay = ECPP_ISR_MAX_DELAY;
467 467 static int ecpp_def_timeout = 90; /* left in for 2.7 compatibility */
468 468
469 469 static void *ecppsoft_statep;
470 470
471 471 /*
472 472 * STREAMS framework manages locks for these structures
473 473 */
474 474 _NOTE(SCHEME_PROTECTS_DATA("unique per call", iocblk))
475 475 _NOTE(SCHEME_PROTECTS_DATA("unique per call", datab))
476 476 _NOTE(SCHEME_PROTECTS_DATA("unique per call", msgb))
477 477 _NOTE(SCHEME_PROTECTS_DATA("unique per call", queue))
478 478 _NOTE(SCHEME_PROTECTS_DATA("unique per call", copyreq))
479 479 _NOTE(SCHEME_PROTECTS_DATA("unique per call", stroptions))
480 480
481 481 struct module_info ecppinfo = {
482 482 /* id, name, min pkt siz, max pkt siz, hi water, low water */
483 483 42, "ecpp", 0, IO_BLOCK_SZ, ECPPHIWAT, ECPPLOWAT
484 484 };
485 485
486 486 static struct qinit ecpp_rinit = {
487 487 putq, ecpp_rsrv, ecpp_open, ecpp_close, NULL, &ecppinfo, NULL
488 488 };
489 489
490 490 static struct qinit ecpp_wint = {
491 491 ecpp_wput, ecpp_wsrv, ecpp_open, ecpp_close, NULL, &ecppinfo, NULL
492 492 };
493 493
494 494 struct streamtab ecpp_str_info = {
495 495 &ecpp_rinit, &ecpp_wint, NULL, NULL
496 496 };
497 497
498 498 static struct cb_ops ecpp_cb_ops = {
499 499 nodev, /* cb_open */
500 500 nodev, /* cb_close */
501 501 nodev, /* cb_strategy */
502 502 nodev, /* cb_print */
503 503 nodev, /* cb_dump */
504 504 nodev, /* cb_read */
505 505 nodev, /* cb_write */
506 506 nodev, /* cb_ioctl */
507 507 nodev, /* cb_devmap */
508 508 nodev, /* cb_mmap */
509 509 nodev, /* cb_segmap */
510 510 nochpoll, /* cb_chpoll */
511 511 ddi_prop_op, /* cb_prop_op */
512 512 &ecpp_str_info, /* cb_stream */
513 513 (D_NEW | D_MP | D_MTPERQ) /* cb_flag */
514 514 };
515 515
516 516 /*
517 517 * Declare ops vectors for auto configuration.
518 518 */
519 519 struct dev_ops ecpp_ops = {
520 520 DEVO_REV, /* devo_rev */
521 521 0, /* devo_refcnt */
522 522 ecpp_getinfo, /* devo_getinfo */
523 523 nulldev, /* devo_identify */
524 524 nulldev, /* devo_probe */
525 525 ecpp_attach, /* devo_attach */
526 526 ecpp_detach, /* devo_detach */
527 527 nodev, /* devo_reset */
528 528 &ecpp_cb_ops, /* devo_cb_ops */
529 529 (struct bus_ops *)NULL, /* devo_bus_ops */
530 530 nulldev, /* devo_power */
531 531 ddi_quiesce_not_needed, /* devo_quiesce */
532 532 };
533 533
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534 534 extern struct mod_ops mod_driverops;
535 535
536 536 static struct modldrv ecppmodldrv = {
537 537 &mod_driverops, /* type of module - driver */
538 538 "parallel port driver",
539 539 &ecpp_ops,
540 540 };
541 541
542 542 static struct modlinkage ecppmodlinkage = {
543 543 MODREV_1,
544 - &ecppmodldrv,
545 - 0
544 + { &ecppmodldrv, NULL }
546 545 };
547 546
548 547
549 548 /*
550 549 *
551 550 * DDI/DKI entry points and supplementary routines
552 551 *
553 552 */
554 553
555 554
556 555 int
557 556 _init(void)
558 557 {
559 558 int error;
560 559
561 560 if ((error = mod_install(&ecppmodlinkage)) == 0) {
562 561 (void) ddi_soft_state_init(&ecppsoft_statep,
563 562 sizeof (struct ecppunit), 1);
564 563 }
565 564
566 565 return (error);
567 566 }
568 567
569 568 int
570 569 _fini(void)
571 570 {
572 571 int error;
573 572
574 573 if ((error = mod_remove(&ecppmodlinkage)) == 0) {
575 574 ddi_soft_state_fini(&ecppsoft_statep);
576 575 }
577 576
578 577 return (error);
579 578 }
580 579
581 580 int
582 581 _info(struct modinfo *modinfop)
583 582 {
584 583 return (mod_info(&ecppmodlinkage, modinfop));
585 584 }
586 585
587 586 static int
588 587 ecpp_attach(dev_info_t *dip, ddi_attach_cmd_t cmd)
589 588 {
590 589 int instance;
591 590 char name[16];
592 591 struct ecppunit *pp;
593 592 struct ecpp_hw_bind *hw_bind;
594 593
595 594 instance = ddi_get_instance(dip);
596 595
597 596 switch (cmd) {
598 597 case DDI_ATTACH:
599 598 break;
600 599
601 600 case DDI_RESUME:
602 601 if (!(pp = ddi_get_soft_state(ecppsoft_statep, instance))) {
603 602 return (DDI_FAILURE);
604 603 }
605 604
606 605 mutex_enter(&pp->umutex);
607 606
608 607 pp->suspended = FALSE;
609 608
610 609 /*
611 610 * Initialize the chip and restore current mode if needed
612 611 */
613 612 (void) ECPP_CONFIG_CHIP(pp);
614 613 (void) ecpp_reset_port_regs(pp);
615 614
616 615 if (pp->oflag == TRUE) {
617 616 int current_mode = pp->current_mode;
618 617
619 618 (void) ecpp_1284_termination(pp);
620 619 (void) ecpp_mode_negotiation(pp, current_mode);
621 620 }
622 621
623 622 mutex_exit(&pp->umutex);
624 623
625 624 return (DDI_SUCCESS);
626 625
627 626 default:
628 627 return (DDI_FAILURE);
629 628 }
630 629
631 630 if (ddi_soft_state_zalloc(ecppsoft_statep, instance) != 0) {
632 631 ecpp_error(dip, "ddi_soft_state_zalloc failed\n");
633 632 goto fail;
634 633 }
635 634
636 635 pp = ddi_get_soft_state(ecppsoft_statep, instance);
637 636
638 637 pp->dip = dip;
639 638 pp->suspended = FALSE;
640 639
641 640 /*
642 641 * Determine SuperIO type and set chip-dependent variables
643 642 */
644 643 hw_bind = ecpp_determine_sio_type(pp);
645 644
646 645 if (hw_bind == NULL) {
647 646 cmn_err(CE_NOTE, "parallel port controller not supported");
648 647 goto fail_sio;
649 648 } else {
650 649 pp->hw = hw_bind->hw;
651 650 ecpp_error(pp->dip, "SuperIO type: %s\n", hw_bind->info);
652 651 }
653 652
654 653 /*
655 654 * Map registers
656 655 */
657 656 if (ECPP_MAP_REGS(pp) != SUCCESS) {
658 657 goto fail_map;
659 658 }
660 659
661 660 if (ddi_dma_alloc_handle(dip, pp->hw->attr, DDI_DMA_DONTWAIT,
662 661 NULL, &pp->dma_handle) != DDI_SUCCESS) {
663 662 ecpp_error(dip, "ecpp_attach: failed ddi_dma_alloc_handle\n");
664 663 goto fail_dma;
665 664 }
666 665
667 666 if (ddi_get_iblock_cookie(dip, 0,
668 667 &pp->ecpp_trap_cookie) != DDI_SUCCESS) {
669 668 ecpp_error(dip, "ecpp_attach: failed ddi_get_iblock_cookie\n");
670 669 goto fail_ibc;
671 670 }
672 671
673 672 mutex_init(&pp->umutex, NULL, MUTEX_DRIVER,
674 673 (void *)pp->ecpp_trap_cookie);
675 674
676 675 cv_init(&pp->pport_cv, NULL, CV_DRIVER, NULL);
677 676
678 677 if (ddi_add_intr(dip, 0, &pp->ecpp_trap_cookie, NULL, ecpp_isr,
679 678 (caddr_t)pp) != DDI_SUCCESS) {
680 679 ecpp_error(dip, "ecpp_attach: failed to add hard intr\n");
681 680 goto fail_intr;
682 681 }
683 682
684 683 if (ddi_add_softintr(dip, DDI_SOFTINT_LOW,
685 684 &pp->softintr_id, 0, 0, ecpp_softintr,
686 685 (caddr_t)pp) != DDI_SUCCESS) {
687 686 ecpp_error(dip, "ecpp_attach: failed to add soft intr\n");
688 687 goto fail_softintr;
689 688 }
690 689
691 690 (void) sprintf(name, "ecpp%d", instance);
692 691
693 692 if (ddi_create_minor_node(dip, name, S_IFCHR, instance,
694 693 DDI_NT_PRINTER, NULL) == DDI_FAILURE) {
695 694 ecpp_error(dip, "ecpp_attach: create_minor_node failed\n");
696 695 goto fail_minor;
697 696 }
698 697
699 698 pp->ioblock = (caddr_t)kmem_alloc(IO_BLOCK_SZ, KM_SLEEP);
700 699 if (pp->ioblock == NULL) {
701 700 ecpp_error(dip, "ecpp_attach: kmem_alloc failed\n");
702 701 goto fail_iob;
703 702 } else {
704 703 ecpp_error(pp->dip, "ecpp_attach: ioblock=0x%x\n", pp->ioblock);
705 704 }
706 705
707 706 ecpp_get_props(pp);
708 707 #if defined(__x86)
709 708 if (pp->hw == &x86 && pp->uh.x86.chn != 0xff) {
710 709 if (ddi_dmae_alloc(dip, pp->uh.x86.chn,
711 710 DDI_DMA_DONTWAIT, NULL) == DDI_SUCCESS)
712 711 ecpp_error(pp->dip, "dmae_alloc success!\n");
713 712 }
714 713 #endif
715 714 if (ECPP_CONFIG_CHIP(pp) == FAILURE) {
716 715 ecpp_error(pp->dip, "config_chip failed.\n");
717 716 goto fail_config;
718 717 }
719 718
720 719 ecpp_kstat_init(pp);
721 720
722 721 ddi_report_dev(dip);
723 722
724 723 return (DDI_SUCCESS);
725 724
726 725 fail_config:
727 726 ddi_prop_remove_all(dip);
728 727 kmem_free(pp->ioblock, IO_BLOCK_SZ);
729 728 fail_iob:
730 729 ddi_remove_minor_node(dip, NULL);
731 730 fail_minor:
732 731 ddi_remove_softintr(pp->softintr_id);
733 732 fail_softintr:
734 733 ddi_remove_intr(dip, (uint_t)0, pp->ecpp_trap_cookie);
735 734 fail_intr:
736 735 mutex_destroy(&pp->umutex);
737 736 cv_destroy(&pp->pport_cv);
738 737 fail_ibc:
739 738 ddi_dma_free_handle(&pp->dma_handle);
740 739 fail_dma:
741 740 ECPP_UNMAP_REGS(pp);
742 741 fail_map:
743 742 fail_sio:
744 743 ddi_soft_state_free(ecppsoft_statep, instance);
745 744 fail:
746 745 ecpp_error(dip, "ecpp_attach: failed.\n");
747 746
748 747 return (DDI_FAILURE);
749 748 }
750 749
751 750 static int
752 751 ecpp_detach(dev_info_t *dip, ddi_detach_cmd_t cmd)
753 752 {
754 753 int instance;
755 754 struct ecppunit *pp;
756 755
757 756 instance = ddi_get_instance(dip);
758 757
759 758 switch (cmd) {
760 759 case DDI_DETACH:
761 760 break;
762 761
763 762 case DDI_SUSPEND:
764 763 if (!(pp = ddi_get_soft_state(ecppsoft_statep, instance))) {
765 764 return (DDI_FAILURE);
766 765 }
767 766
768 767 mutex_enter(&pp->umutex);
769 768 ASSERT(pp->suspended == FALSE);
770 769
771 770 pp->suspended = TRUE; /* prevent new transfers */
772 771
773 772 /*
774 773 * Wait if there's any activity on the port
775 774 */
776 775 if ((pp->e_busy == ECPP_BUSY) || (pp->e_busy == ECPP_FLUSH)) {
777 776 (void) cv_reltimedwait(&pp->pport_cv, &pp->umutex,
778 777 SUSPEND_TOUT * drv_usectohz(1000000),
779 778 TR_CLOCK_TICK);
780 779 if ((pp->e_busy == ECPP_BUSY) ||
781 780 (pp->e_busy == ECPP_FLUSH)) {
782 781 pp->suspended = FALSE;
783 782 mutex_exit(&pp->umutex);
784 783 ecpp_error(pp->dip,
785 784 "ecpp_detach: suspend timeout\n");
786 785 return (DDI_FAILURE);
787 786 }
788 787 }
789 788
790 789 mutex_exit(&pp->umutex);
791 790 return (DDI_SUCCESS);
792 791
793 792 default:
794 793 return (DDI_FAILURE);
795 794 }
796 795
797 796 pp = ddi_get_soft_state(ecppsoft_statep, instance);
798 797 #if defined(__x86)
799 798 if (pp->hw == &x86 && pp->uh.x86.chn != 0xff)
800 799 (void) ddi_dmae_release(pp->dip, pp->uh.x86.chn);
801 800 #endif
802 801 if (pp->dma_handle != NULL)
803 802 ddi_dma_free_handle(&pp->dma_handle);
804 803
805 804 ddi_remove_minor_node(dip, NULL);
806 805
807 806 ddi_remove_softintr(pp->softintr_id);
808 807
809 808 ddi_remove_intr(dip, (uint_t)0, pp->ecpp_trap_cookie);
810 809
811 810 if (pp->ksp) {
812 811 kstat_delete(pp->ksp);
813 812 }
814 813 if (pp->intrstats) {
815 814 kstat_delete(pp->intrstats);
816 815 }
817 816
818 817 cv_destroy(&pp->pport_cv);
819 818
820 819 mutex_destroy(&pp->umutex);
821 820
822 821 ECPP_UNMAP_REGS(pp);
823 822
824 823 kmem_free(pp->ioblock, IO_BLOCK_SZ);
825 824
826 825 ddi_prop_remove_all(dip);
827 826
828 827 ddi_soft_state_free(ecppsoft_statep, instance);
829 828
830 829 return (DDI_SUCCESS);
831 830
832 831 }
833 832
834 833 /*
835 834 * ecpp_get_props() reads ecpp.conf for user defineable tuneables.
836 835 * If the file or a particular variable is not there, a default value
837 836 * is assigned.
838 837 */
839 838
840 839 static void
841 840 ecpp_get_props(struct ecppunit *pp)
842 841 {
843 842 char *prop;
844 843 #if defined(__x86)
845 844 int len;
846 845 int value;
847 846 #endif
848 847 /*
849 848 * If fast_centronics is TRUE, non-compliant IEEE 1284
850 849 * peripherals ( Centronics peripherals) will operate in DMA mode.
851 850 * Transfers betwee main memory and the device will be via DMA;
852 851 * peripheral handshaking will be conducted by superio logic.
853 852 * If ecpp can not read the variable correctly fast_centronics will
854 853 * be set to FALSE. In this case, transfers and handshaking
855 854 * will be conducted by PIO for Centronics devices.
856 855 */
857 856 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, pp->dip, 0,
858 857 "fast-centronics", &prop) == DDI_PROP_SUCCESS) {
859 858 pp->fast_centronics =
860 859 (strcmp(prop, "true") == 0) ? TRUE : FALSE;
861 860 ddi_prop_free(prop);
862 861 } else {
863 862 pp->fast_centronics = FALSE;
864 863 }
865 864
866 865 /*
867 866 * If fast-1284-compatible is set to TRUE, when ecpp communicates
868 867 * with IEEE 1284 compliant peripherals, data transfers between
869 868 * main memory and the parallel port will be conducted by DMA.
870 869 * Handshaking between the port and peripheral will be conducted
871 870 * by superio logic. This is the default characteristic. If
872 871 * fast-1284-compatible is set to FALSE, transfers and handshaking
873 872 * will be conducted by PIO.
874 873 */
875 874
876 875 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, pp->dip, 0,
877 876 "fast-1284-compatible", &prop) == DDI_PROP_SUCCESS) {
878 877 pp->fast_compat = (strcmp(prop, "true") == 0) ? TRUE : FALSE;
879 878 ddi_prop_free(prop);
880 879 } else {
881 880 pp->fast_compat = TRUE;
882 881 }
883 882
884 883 /*
885 884 * Some centronics peripherals require the nInit signal to be
886 885 * toggled to reset the device. If centronics_init_seq is set
887 886 * to TRUE, ecpp will toggle the nInit signal upon every ecpp_open().
888 887 * Applications have the opportunity to toggle the nInit signal
889 888 * with ioctl(2) calls as well. The default is to set it to FALSE.
890 889 */
891 890 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, pp->dip, 0,
892 891 "centronics-init-seq", &prop) == DDI_PROP_SUCCESS) {
893 892 pp->init_seq = (strcmp(prop, "true") == 0) ? TRUE : FALSE;
894 893 ddi_prop_free(prop);
895 894 } else {
896 895 pp->init_seq = FALSE;
897 896 }
898 897
899 898 /*
900 899 * If one of the centronics status signals are in an erroneous
901 900 * state, ecpp_wsrv() will be reinvoked centronics-retry ms to
902 901 * check if the status is ok to transfer. If the property is not
903 902 * found, wsrv_retry will be set to CENTRONICS_RETRY ms.
904 903 */
905 904 pp->wsrv_retry = ddi_prop_get_int(DDI_DEV_T_ANY, pp->dip, 0,
906 905 "centronics-retry", CENTRONICS_RETRY);
907 906
908 907 /*
909 908 * In PIO mode, ecpp_isr() will loop for wait for the busy signal
910 909 * to be deasserted before transferring the next byte. wait_for_busy
911 910 * is specificied in microseconds. If the property is not found
912 911 * ecpp_isr() will wait for a maximum of WAIT_FOR_BUSY us.
913 912 */
914 913 pp->wait_for_busy = ddi_prop_get_int(DDI_DEV_T_ANY, pp->dip, 0,
915 914 "centronics-wait-for-busy", WAIT_FOR_BUSY);
916 915
917 916 /*
918 917 * In PIO mode, centronics transfers must hold the data signals
919 918 * for a data_setup_time milliseconds before the strobe is asserted.
920 919 */
921 920 pp->data_setup_time = ddi_prop_get_int(DDI_DEV_T_ANY, pp->dip, 0,
922 921 "centronics-data-setup-time", DATA_SETUP_TIME);
923 922
924 923 /*
925 924 * In PIO mode, centronics transfers asserts the strobe signal
926 925 * for a period of strobe_pulse_width milliseconds.
927 926 */
928 927 pp->strobe_pulse_width = ddi_prop_get_int(DDI_DEV_T_ANY, pp->dip, 0,
929 928 "centronics-strobe-pulse-width", STROBE_PULSE_WIDTH);
930 929
931 930 /*
932 931 * Upon a transfer the peripheral, ecpp waits write_timeout seconds
933 932 * for the transmission to complete.
934 933 */
935 934 default_xfer_parms.write_timeout = ddi_prop_get_int(DDI_DEV_T_ANY,
936 935 pp->dip, 0, "ecpp-transfer-timeout", ecpp_def_timeout);
937 936
938 937 pp->xfer_parms = default_xfer_parms;
939 938
940 939 /*
941 940 * Get dma channel for M1553
942 941 */
943 942 if (pp->hw == &m1553) {
944 943 pp->uh.m1553.chn = ddi_prop_get_int(DDI_DEV_T_ANY,
945 944 pp->dip, 0, "dma-channel", 0x1);
946 945 ecpp_error(pp->dip, "ecpp_get_prop:chn=%x\n", pp->uh.m1553.chn);
947 946 }
948 947 #if defined(__x86)
949 948 len = sizeof (value);
950 949 /* Get dma channel for i86 pc */
951 950 if (pp->hw == &x86) {
952 951 if (ddi_prop_op(DDI_DEV_T_ANY, pp->dip, PROP_LEN_AND_VAL_BUF,
953 952 DDI_PROP_DONTPASS, "dma-channels", (caddr_t)&value, &len)
954 953 != DDI_PROP_SUCCESS) {
955 954 ecpp_error(pp->dip, "No dma channel found\n");
956 955 pp->uh.x86.chn = 0xff;
957 956 pp->fast_compat = FALSE;
958 957 pp->noecpregs = TRUE;
959 958 } else
960 959 pp->uh.x86.chn = (uint8_t)value;
961 960 }
962 961 #endif
963 962 /*
964 963 * these properties are not yet public
965 964 */
966 965 pp->ecp_rev_speed = ddi_prop_get_int(DDI_DEV_T_ANY, pp->dip, 0,
967 966 "ecp-rev-speed", ECP_REV_SPEED);
968 967
969 968 pp->rev_watchdog = ddi_prop_get_int(DDI_DEV_T_ANY, pp->dip, 0,
970 969 "rev-watchdog", REV_WATCHDOG);
971 970
972 971 ecpp_error(pp->dip,
973 972 "ecpp_get_prop: fast_centronics=%x, fast-1284=%x\n"
974 973 "ecpp_get_prop: wsrv_retry=%d, wait_for_busy=%d\n"
975 974 "ecpp_get_prop: data_setup=%d, strobe_pulse=%d\n"
976 975 "ecpp_get_prop: transfer-timeout=%d\n",
977 976 pp->fast_centronics, pp->fast_compat,
978 977 pp->wsrv_retry, pp->wait_for_busy,
979 978 pp->data_setup_time, pp->strobe_pulse_width,
980 979 pp->xfer_parms.write_timeout);
981 980 }
982 981
983 982 /*ARGSUSED*/
984 983 int
985 984 ecpp_getinfo(dev_info_t *dip, ddi_info_cmd_t infocmd, void *arg, void **result)
986 985 {
987 986 dev_t dev = (dev_t)arg;
988 987 struct ecppunit *pp;
989 988 int instance, ret;
990 989
991 990 instance = getminor(dev);
992 991
993 992 switch (infocmd) {
994 993 case DDI_INFO_DEVT2DEVINFO:
995 994 pp = ddi_get_soft_state(ecppsoft_statep, instance);
996 995 if (pp != NULL) {
997 996 *result = pp->dip;
998 997 ret = DDI_SUCCESS;
999 998 } else {
1000 999 ret = DDI_FAILURE;
1001 1000 }
1002 1001 break;
1003 1002
1004 1003 case DDI_INFO_DEVT2INSTANCE:
1005 1004 *result = (void *)(uintptr_t)instance;
1006 1005 ret = DDI_SUCCESS;
1007 1006 break;
1008 1007
1009 1008 default:
1010 1009 ret = DDI_FAILURE;
1011 1010 break;
1012 1011 }
1013 1012
1014 1013 return (ret);
1015 1014 }
1016 1015
1017 1016 /*ARGSUSED2*/
1018 1017 static int
1019 1018 ecpp_open(queue_t *q, dev_t *dev, int flag, int sflag, cred_t *credp)
1020 1019 {
1021 1020 struct ecppunit *pp;
1022 1021 int instance;
1023 1022 struct stroptions *sop;
1024 1023 mblk_t *mop;
1025 1024
1026 1025 instance = getminor(*dev);
1027 1026
1028 1027 if (instance < 0) {
1029 1028 return (ENXIO);
1030 1029 }
1031 1030
1032 1031 pp = (struct ecppunit *)ddi_get_soft_state(ecppsoft_statep, instance);
1033 1032
1034 1033 if (pp == NULL) {
1035 1034 return (ENXIO);
1036 1035 }
1037 1036
1038 1037 mutex_enter(&pp->umutex);
1039 1038
1040 1039 /*
1041 1040 * Parallel port is an exclusive-use device
1042 1041 * thus providing print job integrity
1043 1042 */
1044 1043 if (pp->oflag == TRUE) {
1045 1044 ecpp_error(pp->dip, "ecpp open failed");
1046 1045 mutex_exit(&pp->umutex);
1047 1046 return (EBUSY);
1048 1047 }
1049 1048
1050 1049 pp->oflag = TRUE;
1051 1050
1052 1051 /* initialize state variables */
1053 1052 pp->prn_timeouts = prn_timeouts_default;
1054 1053 pp->xfer_parms = default_xfer_parms;
1055 1054 pp->current_mode = ECPP_CENTRONICS;
1056 1055 pp->backchannel = ECPP_CENTRONICS;
1057 1056 pp->current_phase = ECPP_PHASE_PO;
1058 1057 pp->port = ECPP_PORT_DMA;
1059 1058 pp->instance = instance;
1060 1059 pp->timeout_error = 0;
1061 1060 pp->saved_dsr = DSR_READ(pp);
1062 1061 pp->ecpp_drain_counter = 0;
1063 1062 pp->dma_cancelled = FALSE;
1064 1063 pp->io_mode = ECPP_DMA;
1065 1064 pp->joblen = 0;
1066 1065 pp->tfifo_intr = 0;
1067 1066 pp->softintr_pending = 0;
1068 1067 pp->nread = 0;
1069 1068
1070 1069 /* clear the state flag */
1071 1070 pp->e_busy = ECPP_IDLE;
1072 1071
1073 1072 pp->readq = RD(q);
1074 1073 pp->writeq = WR(q);
1075 1074 pp->msg = NULL;
1076 1075
1077 1076 RD(q)->q_ptr = WR(q)->q_ptr = (caddr_t)pp;
1078 1077
1079 1078 /*
1080 1079 * Get ready: check host/peripheral, negotiate into default mode
1081 1080 */
1082 1081 if (ecpp_reset_port_regs(pp) == FAILURE) {
1083 1082 mutex_exit(&pp->umutex);
1084 1083 return (EIO);
1085 1084 }
1086 1085
1087 1086 mutex_exit(&pp->umutex);
1088 1087
1089 1088 /*
1090 1089 * Configure the Stream head and enable the Stream
1091 1090 */
1092 1091 if (!(mop = allocb(sizeof (struct stroptions), BPRI_MED))) {
1093 1092 return (EAGAIN);
1094 1093 }
1095 1094
1096 1095 mop->b_datap->db_type = M_SETOPTS;
1097 1096 mop->b_wptr += sizeof (struct stroptions);
1098 1097
1099 1098 /*
1100 1099 * if device is open with O_NONBLOCK flag set, let read(2) return 0
1101 1100 * if no data waiting to be read. Writes will block on flow control.
1102 1101 */
1103 1102 sop = (struct stroptions *)mop->b_rptr;
1104 1103 sop->so_flags = SO_HIWAT | SO_LOWAT | SO_NDELON | SO_MREADON;
1105 1104 sop->so_hiwat = ECPPHIWAT;
1106 1105 sop->so_lowat = ECPPLOWAT;
1107 1106
1108 1107 /* enable the stream */
1109 1108 qprocson(q);
1110 1109
1111 1110 putnext(q, mop);
1112 1111
1113 1112 mutex_enter(&pp->umutex);
1114 1113
1115 1114 ecpp_default_negotiation(pp);
1116 1115
1117 1116 /* go revidle */
1118 1117 (void) ecpp_idle_phase(pp);
1119 1118
1120 1119 ecpp_error(pp->dip,
1121 1120 "ecpp_open: mode=%x, phase=%x ecr=%x, dsr=%x, dcr=%x\n",
1122 1121 pp->current_mode, pp->current_phase,
1123 1122 ECR_READ(pp), DSR_READ(pp), DCR_READ(pp));
1124 1123
1125 1124 mutex_exit(&pp->umutex);
1126 1125
1127 1126 return (0);
1128 1127 }
1129 1128
1130 1129 /*ARGSUSED1*/
1131 1130 static int
1132 1131 ecpp_close(queue_t *q, int flag, cred_t *cred_p)
1133 1132 {
1134 1133 struct ecppunit *pp;
1135 1134 timeout_id_t timeout_id, fifo_timer_id, wsrv_timer_id;
1136 1135
1137 1136 pp = (struct ecppunit *)q->q_ptr;
1138 1137
1139 1138 ecpp_error(pp->dip, "ecpp_close: entering ...\n");
1140 1139
1141 1140 mutex_enter(&pp->umutex);
1142 1141
1143 1142 /*
1144 1143 * ecpp_close() will continue to loop until the
1145 1144 * queue has been drained or if the thread
1146 1145 * has received a SIG. Typically, when the queue
1147 1146 * has data, the port will be ECPP_BUSY. However,
1148 1147 * after a dma completes and before the wsrv
1149 1148 * starts the next transfer, the port may be IDLE.
1150 1149 * In this case, ecpp_close() will loop within this
1151 1150 * while(qsize) segment. Since, ecpp_wsrv() runs
1152 1151 * at software interupt level, this shouldn't loop
1153 1152 * very long.
1154 1153 */
1155 1154 while (pp->e_busy != ECPP_IDLE || qsize(WR(q))) {
1156 1155 if (!cv_wait_sig(&pp->pport_cv, &pp->umutex)) {
1157 1156 ecpp_error(pp->dip, "ecpp_close:B: received SIG\n");
1158 1157 /*
1159 1158 * Returning from a signal such as
1160 1159 * SIGTERM or SIGKILL
1161 1160 */
1162 1161 ecpp_flush(pp, FWRITE);
1163 1162 break;
1164 1163 } else {
1165 1164 ecpp_error(pp->dip, "ecpp_close:rcvd cv-sig\n");
1166 1165 }
1167 1166 }
1168 1167
1169 1168 ecpp_error(pp->dip, "ecpp_close: joblen=%d, ctx_cf=%d, "
1170 1169 "qsize(WR(q))=%d, qsize(RD(q))=%d\n",
1171 1170 pp->joblen, pp->ctx_cf, qsize(pp->writeq), qsize(q));
1172 1171
1173 1172 /*
1174 1173 * Cancel all timeouts, disable interrupts
1175 1174 *
1176 1175 * Note that we can`t call untimeout(9F) with mutex held:
1177 1176 * callout may be blocked on the same mutex, and untimeout() will
1178 1177 * cv_wait() while callout is executing, thus creating a deadlock
1179 1178 * So we zero the timeout id's inside mutex and call untimeout later
1180 1179 */
1181 1180 timeout_id = pp->timeout_id;
1182 1181 fifo_timer_id = pp->fifo_timer_id;
1183 1182 wsrv_timer_id = pp->wsrv_timer_id;
1184 1183
1185 1184 pp->timeout_id = pp->fifo_timer_id = pp->wsrv_timer_id = 0;
1186 1185
1187 1186 pp->softintr_pending = 0;
1188 1187 pp->dma_cancelled = TRUE;
1189 1188 ECPP_MASK_INTR(pp);
1190 1189
1191 1190 mutex_exit(&pp->umutex);
1192 1191
1193 1192 qprocsoff(q);
1194 1193
1195 1194 if (timeout_id) {
1196 1195 (void) untimeout(timeout_id);
1197 1196 }
1198 1197 if (fifo_timer_id) {
1199 1198 (void) untimeout(fifo_timer_id);
1200 1199 }
1201 1200 if (wsrv_timer_id) {
1202 1201 (void) untimeout(wsrv_timer_id);
1203 1202 }
1204 1203
1205 1204 mutex_enter(&pp->umutex);
1206 1205
1207 1206 /* set link to Compatible mode */
1208 1207 if ((pp->current_mode == ECPP_ECP_MODE) &&
1209 1208 (pp->current_phase != ECPP_PHASE_ECP_FWD_IDLE)) {
1210 1209 (void) ecp_reverse2forward(pp);
1211 1210 }
1212 1211
1213 1212 (void) ecpp_1284_termination(pp);
1214 1213
1215 1214 pp->oflag = FALSE;
1216 1215 q->q_ptr = WR(q)->q_ptr = NULL;
1217 1216 pp->readq = pp->writeq = NULL;
1218 1217 pp->msg = NULL;
1219 1218
1220 1219 ecpp_error(pp->dip, "ecpp_close: ecr=%x, dsr=%x, dcr=%x\n",
1221 1220 ECR_READ(pp), DSR_READ(pp), DCR_READ(pp));
1222 1221
1223 1222 mutex_exit(&pp->umutex);
1224 1223
1225 1224 return (0);
1226 1225 }
1227 1226
1228 1227 /*
1229 1228 * standard put procedure for ecpp
1230 1229 */
1231 1230 static int
1232 1231 ecpp_wput(queue_t *q, mblk_t *mp)
1233 1232 {
1234 1233 struct msgb *nmp;
1235 1234 struct ecppunit *pp;
1236 1235
1237 1236 pp = (struct ecppunit *)q->q_ptr;
1238 1237
1239 1238 if (!mp) {
1240 1239 return (0);
1241 1240 }
1242 1241
1243 1242 if ((mp->b_wptr - mp->b_rptr) <= 0) {
1244 1243 ecpp_error(pp->dip,
1245 1244 "ecpp_wput:bogus packet recieved mp=%x\n", mp);
1246 1245 freemsg(mp);
1247 1246 return (0);
1248 1247 }
1249 1248
1250 1249 switch (DB_TYPE(mp)) {
1251 1250 case M_DATA:
1252 1251 /*
1253 1252 * This is a quick fix for multiple message block problem,
1254 1253 * it will be changed later with better performance code.
1255 1254 */
1256 1255 if (mp->b_cont) {
1257 1256 /*
1258 1257 * mblk has scattered data ... do msgpullup
1259 1258 * if it fails, continue with the current mblk
1260 1259 */
1261 1260 if ((nmp = msgpullup(mp, -1)) != NULL) {
1262 1261 freemsg(mp);
1263 1262 mp = nmp;
1264 1263 ecpp_error(pp->dip,
1265 1264 "ecpp_wput:msgpullup: mp=%p len=%d\n",
1266 1265 mp, mp->b_wptr - mp->b_rptr);
1267 1266 }
1268 1267 }
1269 1268
1270 1269 /* let ecpp_wsrv() concatenate small blocks */
1271 1270 (void) putq(q, mp);
1272 1271
1273 1272 break;
1274 1273
1275 1274 case M_CTL:
1276 1275 (void) putq(q, mp);
1277 1276
1278 1277 break;
1279 1278
1280 1279 case M_IOCTL: {
1281 1280 struct iocblk *iocbp;
1282 1281
1283 1282 iocbp = (struct iocblk *)mp->b_rptr;
1284 1283
1285 1284 ecpp_error(pp->dip, "ecpp_wput:M_IOCTL %x\n", iocbp->ioc_cmd);
1286 1285
1287 1286 mutex_enter(&pp->umutex);
1288 1287
1289 1288 /* TESTIO and GET_STATUS can be used during transfer */
1290 1289 if ((pp->e_busy == ECPP_BUSY) &&
1291 1290 (iocbp->ioc_cmd != BPPIOC_TESTIO) &&
1292 1291 (iocbp->ioc_cmd != PRNIOC_GET_STATUS)) {
1293 1292 mutex_exit(&pp->umutex);
1294 1293 (void) putq(q, mp);
1295 1294 } else {
1296 1295 mutex_exit(&pp->umutex);
1297 1296 ecpp_putioc(q, mp);
1298 1297 }
1299 1298
1300 1299 break;
1301 1300 }
1302 1301
1303 1302 case M_IOCDATA: {
1304 1303 struct copyresp *csp;
1305 1304
1306 1305 ecpp_error(pp->dip, "ecpp_wput:M_IOCDATA\n");
1307 1306
1308 1307 csp = (struct copyresp *)mp->b_rptr;
1309 1308
1310 1309 /*
1311 1310 * If copy request failed, quit now
1312 1311 */
1313 1312 if (csp->cp_rval != 0) {
1314 1313 freemsg(mp);
1315 1314 return (0);
1316 1315 }
1317 1316
1318 1317 switch (csp->cp_cmd) {
1319 1318 case ECPPIOC_SETPARMS:
1320 1319 case ECPPIOC_SETREGS:
1321 1320 case ECPPIOC_SETPORT:
1322 1321 case ECPPIOC_SETDATA:
1323 1322 case PRNIOC_SET_IFCAP:
1324 1323 case PRNIOC_SET_TIMEOUTS:
1325 1324 /*
1326 1325 * need to retrieve and use the data, but if the
1327 1326 * device is busy, wait.
1328 1327 */
1329 1328 (void) putq(q, mp);
1330 1329 break;
1331 1330
1332 1331 case ECPPIOC_GETPARMS:
1333 1332 case ECPPIOC_GETREGS:
1334 1333 case ECPPIOC_GETPORT:
1335 1334 case ECPPIOC_GETDATA:
1336 1335 case BPPIOC_GETERR:
1337 1336 case BPPIOC_TESTIO:
1338 1337 case PRNIOC_GET_IFCAP:
1339 1338 case PRNIOC_GET_STATUS:
1340 1339 case PRNIOC_GET_1284_STATUS:
1341 1340 case PRNIOC_GET_TIMEOUTS:
1342 1341 /* data transfered to user space okay */
1343 1342 ecpp_ack_ioctl(q, mp);
1344 1343 break;
1345 1344
1346 1345 case ECPPIOC_GETDEVID:
1347 1346 ecpp_wput_iocdata_devid(q, mp,
1348 1347 offsetof(struct ecpp_device_id, rlen));
1349 1348 break;
1350 1349
1351 1350 case PRNIOC_GET_1284_DEVID:
1352 1351 ecpp_wput_iocdata_devid(q, mp,
1353 1352 offsetof(struct prn_1284_device_id, id_rlen));
1354 1353 break;
1355 1354
1356 1355 case PRNIOC_GET_IFINFO:
1357 1356 ecpp_wput_iocdata_devid(q, mp,
1358 1357 offsetof(struct prn_interface_info, if_rlen));
1359 1358 break;
1360 1359
1361 1360 default:
1362 1361 ecpp_nack_ioctl(q, mp, EINVAL);
1363 1362 break;
1364 1363 }
1365 1364
1366 1365 break;
1367 1366 }
1368 1367
1369 1368 case M_FLUSH:
1370 1369 ecpp_error(pp->dip, "ecpp_wput:M_FLUSH\n");
1371 1370
1372 1371 if (*mp->b_rptr & FLUSHW) {
1373 1372 mutex_enter(&pp->umutex);
1374 1373 ecpp_flush(pp, FWRITE);
1375 1374 mutex_exit(&pp->umutex);
1376 1375 }
1377 1376
1378 1377 if (*mp->b_rptr & FLUSHR) {
1379 1378 mutex_enter(&pp->umutex);
1380 1379 ecpp_flush(pp, FREAD);
1381 1380 mutex_exit(&pp->umutex);
1382 1381 qreply(q, mp);
1383 1382 } else {
1384 1383 freemsg(mp);
1385 1384 }
1386 1385
1387 1386 break;
1388 1387
1389 1388 case M_READ:
1390 1389 /*
1391 1390 * When the user calls read(2), M_READ message is sent to us,
1392 1391 * first byte of which is the number of requested bytes
1393 1392 * We add up user requests and use resulting number
1394 1393 * to calculate the reverse transfer block size
1395 1394 */
1396 1395 mutex_enter(&pp->umutex);
1397 1396 if (pp->e_busy == ECPP_IDLE) {
1398 1397 pp->nread += *(size_t *)mp->b_rptr;
1399 1398 ecpp_error(pp->dip, "ecpp_wput: M_READ %d", pp->nread);
1400 1399 freemsg(mp);
1401 1400 } else {
1402 1401 ecpp_error(pp->dip, "ecpp_wput: M_READ queueing");
1403 1402 (void) putq(q, mp);
1404 1403 }
1405 1404 mutex_exit(&pp->umutex);
1406 1405 break;
1407 1406
1408 1407 default:
1409 1408 ecpp_error(pp->dip, "ecpp_wput: bad messagetype 0x%x\n",
1410 1409 DB_TYPE(mp));
1411 1410 freemsg(mp);
1412 1411 break;
1413 1412 }
1414 1413
1415 1414 return (0);
1416 1415 }
1417 1416
1418 1417 /*
1419 1418 * Process ECPPIOC_GETDEVID-like ioctls
1420 1419 */
1421 1420 static void
1422 1421 ecpp_wput_iocdata_devid(queue_t *q, mblk_t *mp, uintptr_t rlen_offset)
1423 1422 {
1424 1423 struct copyresp *csp;
1425 1424 struct ecpp_copystate *stp;
1426 1425 mblk_t *datamp;
1427 1426
1428 1427 csp = (struct copyresp *)mp->b_rptr;
1429 1428 stp = (struct ecpp_copystate *)csp->cp_private->b_rptr;
1430 1429
1431 1430 /* determine the state of copyin/copyout process */
1432 1431 switch (stp->state) {
1433 1432 case ECPP_STRUCTIN:
1434 1433 /* user structure has arrived */
1435 1434 (void) putq(q, mp);
1436 1435 break;
1437 1436
1438 1437 case ECPP_ADDROUT:
1439 1438 /*
1440 1439 * data transfered to user space okay
1441 1440 * now update user structure
1442 1441 */
1443 1442 datamp = allocb(sizeof (int), BPRI_MED);
1444 1443 if (datamp == NULL) {
1445 1444 ecpp_nack_ioctl(q, mp, ENOSR);
1446 1445 break;
1447 1446 }
1448 1447
1449 1448 *(int *)datamp->b_rptr =
1450 1449 *(int *)((char *)&stp->un + rlen_offset);
1451 1450 stp->state = ECPP_STRUCTOUT;
1452 1451
1453 1452 mcopyout(mp, csp->cp_private, sizeof (int),
1454 1453 (char *)stp->uaddr + rlen_offset, datamp);
1455 1454 qreply(q, mp);
1456 1455 break;
1457 1456
1458 1457 case ECPP_STRUCTOUT:
1459 1458 /* user structure was updated okay */
1460 1459 freemsg(csp->cp_private);
1461 1460 ecpp_ack_ioctl(q, mp);
1462 1461 break;
1463 1462
1464 1463 default:
1465 1464 ecpp_nack_ioctl(q, mp, EINVAL);
1466 1465 break;
1467 1466 }
1468 1467 }
1469 1468
1470 1469 static uchar_t
1471 1470 ecpp_get_error_status(uchar_t status)
1472 1471 {
1473 1472 uchar_t pin_status = 0;
1474 1473
1475 1474 if (!(status & ECPP_nERR)) {
1476 1475 pin_status |= BPP_ERR_ERR;
1477 1476 }
1478 1477
1479 1478 if (status & ECPP_PE) {
1480 1479 pin_status |= BPP_PE_ERR;
1481 1480 }
1482 1481
1483 1482 if (!(status & ECPP_SLCT)) {
1484 1483 pin_status |= BPP_SLCT_ERR;
1485 1484 }
1486 1485
1487 1486 if (!(status & ECPP_nBUSY)) {
1488 1487 pin_status |= BPP_SLCT_ERR;
1489 1488 }
1490 1489
1491 1490 return (pin_status);
1492 1491 }
1493 1492
1494 1493 /*
1495 1494 * ioctl handler for output PUT procedure.
1496 1495 */
1497 1496 static void
1498 1497 ecpp_putioc(queue_t *q, mblk_t *mp)
1499 1498 {
1500 1499 struct iocblk *iocbp;
1501 1500 struct ecppunit *pp;
1502 1501
1503 1502 pp = (struct ecppunit *)q->q_ptr;
1504 1503
1505 1504 iocbp = (struct iocblk *)mp->b_rptr;
1506 1505
1507 1506 /* I_STR ioctls are invalid */
1508 1507 if (iocbp->ioc_count != TRANSPARENT) {
1509 1508 ecpp_nack_ioctl(q, mp, EINVAL);
1510 1509 return;
1511 1510 }
1512 1511
1513 1512 switch (iocbp->ioc_cmd) {
1514 1513 case ECPPIOC_SETPARMS: {
1515 1514 mcopyin(mp, NULL, sizeof (struct ecpp_transfer_parms), NULL);
1516 1515 qreply(q, mp);
1517 1516 break;
1518 1517 }
1519 1518
1520 1519 case ECPPIOC_GETPARMS: {
1521 1520 struct ecpp_transfer_parms xfer_parms;
1522 1521
1523 1522 mutex_enter(&pp->umutex);
1524 1523
1525 1524 pp->xfer_parms.mode = pp->current_mode;
1526 1525 xfer_parms = pp->xfer_parms;
1527 1526
1528 1527 mutex_exit(&pp->umutex);
1529 1528
1530 1529 ecpp_putioc_copyout(q, mp, &xfer_parms, sizeof (xfer_parms));
1531 1530 break;
1532 1531 }
1533 1532
1534 1533 case ECPPIOC_SETREGS: {
1535 1534 mutex_enter(&pp->umutex);
1536 1535 if (pp->current_mode != ECPP_DIAG_MODE) {
1537 1536 mutex_exit(&pp->umutex);
1538 1537 ecpp_nack_ioctl(q, mp, EINVAL);
1539 1538 break;
1540 1539 }
1541 1540 mutex_exit(&pp->umutex);
1542 1541
1543 1542 mcopyin(mp, NULL, sizeof (struct ecpp_regs), NULL);
1544 1543 qreply(q, mp);
1545 1544 break;
1546 1545 }
1547 1546
1548 1547 case ECPPIOC_GETREGS: {
1549 1548 struct ecpp_regs rg;
1550 1549
1551 1550 mutex_enter(&pp->umutex);
1552 1551
1553 1552 if (pp->current_mode != ECPP_DIAG_MODE) {
1554 1553 mutex_exit(&pp->umutex);
1555 1554 ecpp_nack_ioctl(q, mp, EINVAL);
1556 1555 break;
1557 1556 }
1558 1557
1559 1558 rg.dsr = DSR_READ(pp);
1560 1559 rg.dcr = DCR_READ(pp);
1561 1560
1562 1561 mutex_exit(&pp->umutex);
1563 1562
1564 1563 ecpp_error(pp->dip, "ECPPIOC_GETREGS: dsr=%x,dcr=%x\n",
1565 1564 rg.dsr, rg.dcr);
1566 1565
1567 1566 /* these bits must be 1 */
1568 1567 rg.dsr |= ECPP_SETREGS_DSR_MASK;
1569 1568 rg.dcr |= ECPP_SETREGS_DCR_MASK;
1570 1569
1571 1570 ecpp_putioc_copyout(q, mp, &rg, sizeof (rg));
1572 1571 break;
1573 1572 }
1574 1573
1575 1574 case ECPPIOC_SETPORT:
1576 1575 case ECPPIOC_SETDATA: {
1577 1576 mutex_enter(&pp->umutex);
1578 1577 if (pp->current_mode != ECPP_DIAG_MODE) {
1579 1578 mutex_exit(&pp->umutex);
1580 1579 ecpp_nack_ioctl(q, mp, EINVAL);
1581 1580 break;
1582 1581 }
1583 1582 mutex_exit(&pp->umutex);
1584 1583
1585 1584 /*
1586 1585 * each of the commands fetches a byte quantity.
1587 1586 */
1588 1587 mcopyin(mp, NULL, sizeof (uchar_t), NULL);
1589 1588 qreply(q, mp);
1590 1589 break;
1591 1590 }
1592 1591
1593 1592 case ECPPIOC_GETDATA:
1594 1593 case ECPPIOC_GETPORT: {
1595 1594 uchar_t byte;
1596 1595
1597 1596 mutex_enter(&pp->umutex);
1598 1597
1599 1598 /* must be in diagnostic mode for these commands to work */
1600 1599 if (pp->current_mode != ECPP_DIAG_MODE) {
1601 1600 mutex_exit(&pp->umutex);
1602 1601 ecpp_nack_ioctl(q, mp, EINVAL);
1603 1602 break;
1604 1603 }
1605 1604
1606 1605 if (iocbp->ioc_cmd == ECPPIOC_GETPORT) {
1607 1606 byte = pp->port;
1608 1607 } else if (iocbp->ioc_cmd == ECPPIOC_GETDATA) {
1609 1608 switch (pp->port) {
1610 1609 case ECPP_PORT_PIO:
1611 1610 byte = DATAR_READ(pp);
1612 1611 break;
1613 1612 case ECPP_PORT_TDMA:
1614 1613 byte = TFIFO_READ(pp);
1615 1614 ecpp_error(pp->dip, "GETDATA=0x%x\n", byte);
1616 1615 break;
1617 1616 default:
1618 1617 ecpp_nack_ioctl(q, mp, EINVAL);
1619 1618 break;
1620 1619 }
1621 1620 } else {
1622 1621 mutex_exit(&pp->umutex);
1623 1622 ecpp_error(pp->dip, "weird command");
1624 1623 ecpp_nack_ioctl(q, mp, EINVAL);
1625 1624 break;
1626 1625 }
1627 1626
1628 1627 mutex_exit(&pp->umutex);
1629 1628
1630 1629 ecpp_putioc_copyout(q, mp, &byte, sizeof (byte));
1631 1630
1632 1631 break;
1633 1632 }
1634 1633
1635 1634 case BPPIOC_GETERR: {
1636 1635 struct bpp_error_status bpp_status;
1637 1636
1638 1637 mutex_enter(&pp->umutex);
1639 1638
1640 1639 bpp_status.timeout_occurred = pp->timeout_error;
1641 1640 bpp_status.bus_error = 0; /* not used */
1642 1641 bpp_status.pin_status = ecpp_get_error_status(pp->saved_dsr);
1643 1642
1644 1643 mutex_exit(&pp->umutex);
1645 1644
1646 1645 ecpp_putioc_copyout(q, mp, &bpp_status, sizeof (bpp_status));
1647 1646
1648 1647 break;
1649 1648 }
1650 1649
1651 1650 case BPPIOC_TESTIO: {
1652 1651 mutex_enter(&pp->umutex);
1653 1652
1654 1653 if (!((pp->current_mode == ECPP_CENTRONICS) ||
1655 1654 (pp->current_mode == ECPP_COMPAT_MODE))) {
1656 1655 ecpp_nack_ioctl(q, mp, EINVAL);
1657 1656 } else {
1658 1657 pp->saved_dsr = DSR_READ(pp);
1659 1658
1660 1659 if ((pp->saved_dsr & ECPP_PE) ||
1661 1660 !(pp->saved_dsr & ECPP_SLCT) ||
1662 1661 !(pp->saved_dsr & ECPP_nERR)) {
1663 1662 ecpp_nack_ioctl(q, mp, EIO);
1664 1663 } else {
1665 1664 ecpp_ack_ioctl(q, mp);
1666 1665 }
1667 1666 }
1668 1667
1669 1668 mutex_exit(&pp->umutex);
1670 1669
1671 1670 break;
1672 1671 }
1673 1672
1674 1673 case PRNIOC_RESET:
1675 1674 /*
1676 1675 * Initialize interface only if no transfer is in progress
1677 1676 */
1678 1677 mutex_enter(&pp->umutex);
1679 1678 if (pp->e_busy == ECPP_BUSY) {
1680 1679 mutex_exit(&pp->umutex);
1681 1680 ecpp_nack_ioctl(q, mp, EIO);
1682 1681 } else {
1683 1682 (void) ecpp_mode_negotiation(pp, ECPP_CENTRONICS);
1684 1683
1685 1684 DCR_WRITE(pp, ECPP_SLCTIN);
1686 1685 drv_usecwait(2);
1687 1686 DCR_WRITE(pp, ECPP_SLCTIN | ECPP_nINIT);
1688 1687
1689 1688 ecpp_default_negotiation(pp);
1690 1689
1691 1690 mutex_exit(&pp->umutex);
1692 1691 ecpp_ack_ioctl(q, mp);
1693 1692 }
1694 1693 break;
1695 1694
1696 1695 case PRNIOC_GET_IFCAP: {
1697 1696 uint_t ifcap;
1698 1697
1699 1698 mutex_enter(&pp->umutex);
1700 1699
1701 1700 ifcap = ecpp_get_prn_ifcap(pp);
1702 1701
1703 1702 mutex_exit(&pp->umutex);
1704 1703
1705 1704 ecpp_putioc_copyout(q, mp, &ifcap, sizeof (ifcap));
1706 1705 break;
1707 1706 }
1708 1707
1709 1708 case PRNIOC_SET_IFCAP: {
1710 1709 mcopyin(mp, NULL, sizeof (uint_t), NULL);
1711 1710 qreply(q, mp);
1712 1711 break;
1713 1712 }
1714 1713
1715 1714 case PRNIOC_GET_TIMEOUTS: {
1716 1715 struct prn_timeouts timeouts;
1717 1716
1718 1717 mutex_enter(&pp->umutex);
1719 1718 timeouts = pp->prn_timeouts;
1720 1719 mutex_exit(&pp->umutex);
1721 1720
1722 1721 ecpp_putioc_copyout(q, mp, &timeouts, sizeof (timeouts));
1723 1722
1724 1723 break;
1725 1724 }
1726 1725
1727 1726 case PRNIOC_SET_TIMEOUTS:
1728 1727 mcopyin(mp, NULL, sizeof (struct prn_timeouts),
1729 1728 *(caddr_t *)(void *)mp->b_cont->b_rptr);
1730 1729 qreply(q, mp);
1731 1730 break;
1732 1731
1733 1732 case PRNIOC_GET_STATUS: {
1734 1733 uint8_t dsr;
1735 1734 uint_t status;
1736 1735
1737 1736 mutex_enter(&pp->umutex);
1738 1737
1739 1738 /* DSR only makes sense in Centronics & Compat mode */
1740 1739 if (pp->current_mode == ECPP_CENTRONICS ||
1741 1740 pp->current_mode == ECPP_COMPAT_MODE) {
1742 1741 dsr = DSR_READ(pp);
1743 1742 if ((dsr & ECPP_PE) ||
1744 1743 !(dsr & ECPP_SLCT) || !(dsr & ECPP_nERR)) {
1745 1744 status = PRN_ONLINE;
1746 1745 } else {
1747 1746 status = PRN_ONLINE | PRN_READY;
1748 1747 }
1749 1748 } else {
1750 1749 status = PRN_ONLINE | PRN_READY;
1751 1750 }
1752 1751
1753 1752 mutex_exit(&pp->umutex);
1754 1753
1755 1754 ecpp_putioc_copyout(q, mp, &status, sizeof (status));
1756 1755 break;
1757 1756 }
1758 1757
1759 1758 case PRNIOC_GET_1284_STATUS: {
1760 1759 uint8_t dsr;
1761 1760 uchar_t status;
1762 1761
1763 1762 mutex_enter(&pp->umutex);
1764 1763
1765 1764 /* status only makes sense in Centronics & Compat mode */
1766 1765 if (pp->current_mode != ECPP_COMPAT_MODE &&
1767 1766 pp->current_mode != ECPP_CENTRONICS) {
1768 1767 mutex_exit(&pp->umutex);
1769 1768 ecpp_nack_ioctl(q, mp, EINVAL);
1770 1769 break;
1771 1770 }
1772 1771
1773 1772 dsr = DSR_READ(pp); /* read status */
1774 1773
1775 1774 mutex_exit(&pp->umutex);
1776 1775
1777 1776 ecpp_error(pp->dip, "PRNIOC_GET_STATUS: %x\n", dsr);
1778 1777
1779 1778 status = (dsr & (ECPP_SLCT | ECPP_PE | ECPP_nERR)) |
1780 1779 (~dsr & ECPP_nBUSY);
1781 1780
1782 1781 ecpp_putioc_copyout(q, mp, &status, sizeof (status));
1783 1782 break;
1784 1783 }
1785 1784
1786 1785 case ECPPIOC_GETDEVID:
1787 1786 ecpp_putioc_stateful_copyin(q, mp,
1788 1787 sizeof (struct ecpp_device_id));
1789 1788 break;
1790 1789
1791 1790 case PRNIOC_GET_1284_DEVID:
1792 1791 ecpp_putioc_stateful_copyin(q, mp,
1793 1792 sizeof (struct prn_1284_device_id));
1794 1793 break;
1795 1794
1796 1795 case PRNIOC_GET_IFINFO:
1797 1796 ecpp_putioc_stateful_copyin(q, mp,
1798 1797 sizeof (struct prn_interface_info));
1799 1798 break;
1800 1799
1801 1800 default:
1802 1801 ecpp_error(pp->dip, "putioc: unknown IOCTL: %x\n",
1803 1802 iocbp->ioc_cmd);
1804 1803 ecpp_nack_ioctl(q, mp, EINVAL);
1805 1804 break;
1806 1805 }
1807 1806 }
1808 1807
1809 1808 /*
1810 1809 * allocate mblk and copyout the requested number of bytes
1811 1810 */
1812 1811 static void
1813 1812 ecpp_putioc_copyout(queue_t *q, mblk_t *mp, void *buf, int len)
1814 1813 {
1815 1814 mblk_t *tmp;
1816 1815
1817 1816 if ((tmp = allocb(len, BPRI_MED)) == NULL) {
1818 1817 ecpp_nack_ioctl(q, mp, ENOSR);
1819 1818 return;
1820 1819 }
1821 1820
1822 1821 bcopy(buf, tmp->b_wptr, len);
1823 1822
1824 1823 mcopyout(mp, NULL, len, NULL, tmp);
1825 1824 qreply(q, mp);
1826 1825 }
1827 1826
1828 1827 /*
1829 1828 * copyin the structure using struct ecpp_copystate
1830 1829 */
1831 1830 static void
1832 1831 ecpp_putioc_stateful_copyin(queue_t *q, mblk_t *mp, size_t size)
1833 1832 {
1834 1833 mblk_t *tmp;
1835 1834 struct ecpp_copystate *stp;
1836 1835
1837 1836 if ((tmp = allocb(sizeof (struct ecpp_copystate), BPRI_MED)) == NULL) {
1838 1837 ecpp_nack_ioctl(q, mp, EAGAIN);
1839 1838 return;
1840 1839 }
1841 1840
1842 1841 stp = (struct ecpp_copystate *)tmp->b_rptr;
1843 1842 stp->state = ECPP_STRUCTIN;
1844 1843 stp->uaddr = *(caddr_t *)mp->b_cont->b_rptr;
1845 1844
1846 1845 tmp->b_wptr += sizeof (struct ecpp_copystate);
1847 1846
1848 1847 mcopyin(mp, tmp, size, stp->uaddr);
1849 1848 qreply(q, mp);
1850 1849 }
1851 1850
1852 1851 /*
1853 1852 * read queue is only used when the peripheral sends data faster,
1854 1853 * then the application consumes it;
1855 1854 * once the low water mark is reached, this routine will be scheduled
1856 1855 */
1857 1856 static int
1858 1857 ecpp_rsrv(queue_t *q)
1859 1858 {
1860 1859 struct msgb *mp;
1861 1860
1862 1861 /*
1863 1862 * send data upstream until next queue is full or the queue is empty
1864 1863 */
1865 1864 while (canputnext(q) && (mp = getq(q))) {
1866 1865 putnext(q, mp);
1867 1866 }
1868 1867
1869 1868 /*
1870 1869 * if there is still space on the queue, enable backchannel
1871 1870 */
1872 1871 if (canputnext(q)) {
1873 1872 struct ecppunit *pp = (struct ecppunit *)q->q_ptr;
1874 1873
1875 1874 mutex_enter(&pp->umutex);
1876 1875
1877 1876 if (pp->e_busy == ECPP_IDLE) {
1878 1877 (void) ecpp_idle_phase(pp);
1879 1878 cv_signal(&pp->pport_cv); /* signal ecpp_close() */
1880 1879 }
1881 1880
1882 1881 mutex_exit(&pp->umutex);
1883 1882 }
1884 1883
1885 1884 return (0);
1886 1885 }
1887 1886
1888 1887 static int
1889 1888 ecpp_wsrv(queue_t *q)
1890 1889 {
1891 1890 struct ecppunit *pp = (struct ecppunit *)q->q_ptr;
1892 1891 struct msgb *mp;
1893 1892 size_t len, total_len;
1894 1893 size_t my_ioblock_sz;
1895 1894 caddr_t my_ioblock;
1896 1895 caddr_t start_addr;
1897 1896
1898 1897 mutex_enter(&pp->umutex);
1899 1898
1900 1899 ecpp_error(pp->dip, "ecpp_wsrv: e_busy=%x\n", pp->e_busy);
1901 1900
1902 1901 /* if channel is actively doing work, wait till completed */
1903 1902 if (pp->e_busy == ECPP_BUSY || pp->e_busy == ECPP_FLUSH) {
1904 1903 mutex_exit(&pp->umutex);
1905 1904 return (0);
1906 1905 } else if (pp->suspended == TRUE) {
1907 1906 /*
1908 1907 * if the system is about to suspend and ecpp_detach()
1909 1908 * is blocked due to active transfers, wake it up and exit
1910 1909 */
1911 1910 cv_signal(&pp->pport_cv);
1912 1911 mutex_exit(&pp->umutex);
1913 1912 return (0);
1914 1913 }
1915 1914
1916 1915 /* peripheral status should be okay before starting transfer */
1917 1916 if (pp->e_busy == ECPP_ERR) {
1918 1917 if (ecpp_check_status(pp) == FAILURE) {
1919 1918 if (pp->wsrv_timer_id == 0) {
1920 1919 ecpp_error(pp->dip, "wsrv: start wrsv_timer\n");
1921 1920 pp->wsrv_timer_id = timeout(ecpp_wsrv_timer,
1922 1921 (caddr_t)pp,
1923 1922 drv_usectohz(pp->wsrv_retry * 1000));
1924 1923 } else {
1925 1924 ecpp_error(pp->dip,
1926 1925 "ecpp_wsrv: wrsv_timer is active\n");
1927 1926 }
1928 1927
1929 1928 mutex_exit(&pp->umutex);
1930 1929 return (0);
1931 1930 } else {
1932 1931 pp->e_busy = ECPP_IDLE;
1933 1932 }
1934 1933 }
1935 1934
1936 1935 my_ioblock = pp->ioblock;
1937 1936 my_ioblock_sz = IO_BLOCK_SZ;
1938 1937
1939 1938 /*
1940 1939 * it`s important to null pp->msg here,
1941 1940 * cleaning up from the previous transfer attempts
1942 1941 */
1943 1942 pp->msg = NULL;
1944 1943
1945 1944 start_addr = NULL;
1946 1945 len = total_len = 0;
1947 1946 /*
1948 1947 * The following loop is implemented to gather the
1949 1948 * many small writes that the lp subsystem makes and
1950 1949 * compile them into one large dma transfer. The len and
1951 1950 * total_len variables are a running count of the number of
1952 1951 * bytes that have been gathered. They are bcopied to the
1953 1952 * ioblock buffer. The pp->e_busy is set to E_BUSY as soon as
1954 1953 * we start gathering packets to indicate the following transfer.
1955 1954 */
1956 1955 while (mp = getq(q)) {
1957 1956 switch (DB_TYPE(mp)) {
1958 1957 case M_DATA:
1959 1958 pp->e_busy = ECPP_BUSY;
1960 1959 len = mp->b_wptr - mp->b_rptr;
1961 1960
1962 1961 if ((total_len == 0) && (len >= my_ioblock_sz)) {
1963 1962 /*
1964 1963 * if the first M_DATA is bigger than ioblock,
1965 1964 * just use this mblk and start the transfer
1966 1965 */
1967 1966 total_len = len;
1968 1967 start_addr = (caddr_t)mp->b_rptr;
1969 1968 pp->msg = mp;
1970 1969 goto breakout;
1971 1970 } else if (total_len + len > my_ioblock_sz) {
1972 1971 /*
1973 1972 * current M_DATA does not fit in ioblock,
1974 1973 * put it back and start the transfer
1975 1974 */
1976 1975 (void) putbq(q, mp);
1977 1976 goto breakout;
1978 1977 } else {
1979 1978 /*
1980 1979 * otherwise add data to ioblock and free mblk
1981 1980 */
1982 1981 bcopy(mp->b_rptr, my_ioblock, len);
1983 1982 my_ioblock += len;
1984 1983 total_len += len;
1985 1984 start_addr = (caddr_t)pp->ioblock;
1986 1985 freemsg(mp);
1987 1986 }
1988 1987 break;
1989 1988
1990 1989 case M_IOCTL:
1991 1990 /*
1992 1991 * Assume a simple loopback test: an application
1993 1992 * writes data into the TFIFO, reads it using
1994 1993 * ECPPIOC_GETDATA and compares. If the transfer
1995 1994 * times out (which is only possible on Grover),
1996 1995 * the ioctl might be processed before the data
1997 1996 * got to the TFIFO, which leads to miscompare.
1998 1997 * So if we met ioctl, postpone it until after xfer.
1999 1998 */
2000 1999 if (total_len > 0) {
2001 2000 (void) putbq(q, mp);
2002 2001 goto breakout;
2003 2002 }
2004 2003
2005 2004 ecpp_error(pp->dip, "M_IOCTL.\n");
2006 2005
2007 2006 mutex_exit(&pp->umutex);
2008 2007
2009 2008 ecpp_putioc(q, mp);
2010 2009
2011 2010 mutex_enter(&pp->umutex);
2012 2011
2013 2012 break;
2014 2013
2015 2014 case M_IOCDATA: {
2016 2015 struct copyresp *csp = (struct copyresp *)mp->b_rptr;
2017 2016
2018 2017 ecpp_error(pp->dip, "M_IOCDATA\n");
2019 2018
2020 2019 /*
2021 2020 * If copy request failed, quit now
2022 2021 */
2023 2022 if (csp->cp_rval != 0) {
2024 2023 freemsg(mp);
2025 2024 break;
2026 2025 }
2027 2026
2028 2027 switch (csp->cp_cmd) {
2029 2028 case ECPPIOC_SETPARMS:
2030 2029 case ECPPIOC_SETREGS:
2031 2030 case ECPPIOC_SETPORT:
2032 2031 case ECPPIOC_SETDATA:
2033 2032 case ECPPIOC_GETDEVID:
2034 2033 case PRNIOC_SET_IFCAP:
2035 2034 case PRNIOC_GET_1284_DEVID:
2036 2035 case PRNIOC_SET_TIMEOUTS:
2037 2036 case PRNIOC_GET_IFINFO:
2038 2037 ecpp_srvioc(q, mp);
2039 2038 break;
2040 2039
2041 2040 default:
2042 2041 ecpp_nack_ioctl(q, mp, EINVAL);
2043 2042 break;
2044 2043 }
2045 2044
2046 2045 break;
2047 2046 }
2048 2047
2049 2048 case M_CTL:
2050 2049 if (pp->e_busy != ECPP_IDLE) {
2051 2050 ecpp_error(pp->dip, "wsrv: M_CTL postponed\n");
2052 2051 (void) putbq(q, mp);
2053 2052 goto breakout;
2054 2053 } else {
2055 2054 ecpp_error(pp->dip, "wsrv: M_CTL\n");
2056 2055 }
2057 2056
2058 2057 /* sanity check */
2059 2058 if ((mp->b_wptr - mp->b_rptr != sizeof (int)) ||
2060 2059 (*(int *)mp->b_rptr != ECPP_BACKCHANNEL)) {
2061 2060 ecpp_error(pp->dip, "wsrv: bogus M_CTL");
2062 2061 freemsg(mp);
2063 2062 break;
2064 2063 } else {
2065 2064 freemsg(mp);
2066 2065 }
2067 2066
2068 2067 /* This was a backchannel request */
2069 2068 (void) ecpp_peripheral2host(pp);
2070 2069
2071 2070 /* exit if transfer have been initiated */
2072 2071 if (pp->e_busy == ECPP_BUSY) {
2073 2072 goto breakout;
2074 2073 }
2075 2074 break;
2076 2075
2077 2076 case M_READ:
2078 2077 pp->nread += *(size_t *)mp->b_rptr;
2079 2078 freemsg(mp);
2080 2079 ecpp_error(pp->dip, "wsrv: M_READ %d", pp->nread);
2081 2080 break;
2082 2081
2083 2082 default:
2084 2083 ecpp_error(pp->dip, "wsrv: should never get here\n");
2085 2084 freemsg(mp);
2086 2085 break;
2087 2086 }
2088 2087 }
2089 2088 breakout:
2090 2089 /*
2091 2090 * If total_len > 0 then start the transfer, otherwise goto idle state
2092 2091 */
2093 2092 if (total_len > 0) {
2094 2093 ecpp_error(pp->dip, "wsrv:starting: total_len=%d\n", total_len);
2095 2094 pp->e_busy = ECPP_BUSY;
2096 2095 ecpp_start(pp, start_addr, total_len);
2097 2096 } else {
2098 2097 ecpp_error(pp->dip, "wsrv:finishing: ebusy=%x\n", pp->e_busy);
2099 2098
2100 2099 /* IDLE if xfer_timeout, or FIFO_EMPTY */
2101 2100 if (pp->e_busy == ECPP_IDLE) {
2102 2101 (void) ecpp_idle_phase(pp);
2103 2102 cv_signal(&pp->pport_cv); /* signal ecpp_close() */
2104 2103 }
2105 2104 }
2106 2105
2107 2106 mutex_exit(&pp->umutex);
2108 2107 return (1);
2109 2108 }
2110 2109
2111 2110 /*
2112 2111 * Ioctl processor for queued ioctl data transfer messages.
2113 2112 */
2114 2113 static void
2115 2114 ecpp_srvioc(queue_t *q, mblk_t *mp)
2116 2115 {
2117 2116 struct iocblk *iocbp;
2118 2117 struct ecppunit *pp;
2119 2118
2120 2119 iocbp = (struct iocblk *)mp->b_rptr;
2121 2120 pp = (struct ecppunit *)q->q_ptr;
2122 2121
2123 2122 switch (iocbp->ioc_cmd) {
2124 2123 case ECPPIOC_SETPARMS: {
2125 2124 struct ecpp_transfer_parms *xferp;
2126 2125
2127 2126 xferp = (struct ecpp_transfer_parms *)mp->b_cont->b_rptr;
2128 2127
2129 2128 if (xferp->write_timeout <= 0 ||
2130 2129 xferp->write_timeout >= ECPP_MAX_TIMEOUT) {
2131 2130 ecpp_nack_ioctl(q, mp, EINVAL);
2132 2131 break;
2133 2132 }
2134 2133
2135 2134 if (!((xferp->mode == ECPP_CENTRONICS) ||
2136 2135 (xferp->mode == ECPP_COMPAT_MODE) ||
2137 2136 (xferp->mode == ECPP_NIBBLE_MODE) ||
2138 2137 (xferp->mode == ECPP_ECP_MODE) ||
2139 2138 (xferp->mode == ECPP_DIAG_MODE))) {
2140 2139 ecpp_nack_ioctl(q, mp, EINVAL);
2141 2140 break;
2142 2141 }
2143 2142
2144 2143 pp->xfer_parms = *xferp;
2145 2144 pp->prn_timeouts.tmo_forward = pp->xfer_parms.write_timeout;
2146 2145
2147 2146 ecpp_error(pp->dip, "srvioc: current_mode =%x new mode=%x\n",
2148 2147 pp->current_mode, pp->xfer_parms.mode);
2149 2148
2150 2149 if (ecpp_mode_negotiation(pp, pp->xfer_parms.mode) == FAILURE) {
2151 2150 ecpp_nack_ioctl(q, mp, EPROTONOSUPPORT);
2152 2151 } else {
2153 2152 /*
2154 2153 * mode nego was a success. If nibble mode check
2155 2154 * back channel and set into REVIDLE.
2156 2155 */
2157 2156 if ((pp->current_mode == ECPP_NIBBLE_MODE) &&
2158 2157 (read_nibble_backchan(pp) == FAILURE)) {
2159 2158 /*
2160 2159 * problems reading the backchannel
2161 2160 * returned to centronics;
2162 2161 * ioctl fails.
2163 2162 */
2164 2163 ecpp_nack_ioctl(q, mp, EPROTONOSUPPORT);
2165 2164 break;
2166 2165 }
2167 2166
2168 2167 ecpp_ack_ioctl(q, mp);
2169 2168 }
2170 2169 if (pp->current_mode != ECPP_DIAG_MODE) {
2171 2170 pp->port = ECPP_PORT_DMA;
2172 2171 } else {
2173 2172 pp->port = ECPP_PORT_PIO;
2174 2173 }
2175 2174
2176 2175 pp->xfer_parms.mode = pp->current_mode;
2177 2176
2178 2177 break;
2179 2178 }
2180 2179
2181 2180 case ECPPIOC_SETREGS: {
2182 2181 struct ecpp_regs *rg;
2183 2182 uint8_t dcr;
2184 2183
2185 2184 rg = (struct ecpp_regs *)mp->b_cont->b_rptr;
2186 2185
2187 2186 /* must be in diagnostic mode for these commands to work */
2188 2187 if (pp->current_mode != ECPP_DIAG_MODE) {
2189 2188 ecpp_nack_ioctl(q, mp, EINVAL);
2190 2189 break;
2191 2190 }
2192 2191
2193 2192 /* bits 4-7 must be 1 or return EINVAL */
2194 2193 if ((rg->dcr & ECPP_SETREGS_DCR_MASK) !=
2195 2194 ECPP_SETREGS_DCR_MASK) {
2196 2195 ecpp_nack_ioctl(q, mp, EINVAL);
2197 2196 break;
2198 2197 }
2199 2198
2200 2199 /* get the old dcr */
2201 2200 dcr = DCR_READ(pp) & ~ECPP_REV_DIR;
2202 2201 /* get the new dcr */
2203 2202 dcr = (dcr & ECPP_SETREGS_DCR_MASK) |
2204 2203 (rg->dcr & ~ECPP_SETREGS_DCR_MASK);
2205 2204 DCR_WRITE(pp, dcr);
2206 2205 ecpp_error(pp->dip, "ECPPIOC_SETREGS:dcr=%x\n", dcr);
2207 2206 ecpp_ack_ioctl(q, mp);
2208 2207 break;
2209 2208 }
2210 2209
2211 2210 case ECPPIOC_SETPORT: {
2212 2211 uchar_t *port;
2213 2212
2214 2213 port = (uchar_t *)mp->b_cont->b_rptr;
2215 2214
2216 2215 /* must be in diagnostic mode for these commands to work */
2217 2216 if (pp->current_mode != ECPP_DIAG_MODE) {
2218 2217 ecpp_nack_ioctl(q, mp, EINVAL);
2219 2218 break;
2220 2219 }
2221 2220
2222 2221 switch (*port) {
2223 2222 case ECPP_PORT_PIO:
2224 2223 /* put superio into PIO mode */
2225 2224 ECR_WRITE(pp,
2226 2225 ECR_mode_001 | ECPP_INTR_MASK | ECPP_INTR_SRV);
2227 2226 pp->port = *port;
2228 2227 ecpp_ack_ioctl(q, mp);
2229 2228 break;
2230 2229
2231 2230 case ECPP_PORT_TDMA:
2232 2231 ecpp_error(pp->dip, "SETPORT: to TDMA\n");
2233 2232 pp->tfifo_intr = 1;
2234 2233 /* change to mode 110 */
2235 2234 ECR_WRITE(pp,
2236 2235 ECR_mode_110 | ECPP_INTR_MASK | ECPP_INTR_SRV);
2237 2236 pp->port = *port;
2238 2237 ecpp_ack_ioctl(q, mp);
2239 2238 break;
2240 2239
2241 2240 default:
2242 2241 ecpp_nack_ioctl(q, mp, EINVAL);
2243 2242 }
2244 2243
2245 2244 break;
2246 2245 }
2247 2246
2248 2247 case ECPPIOC_SETDATA: {
2249 2248 uchar_t *data;
2250 2249
2251 2250 data = (uchar_t *)mp->b_cont->b_rptr;
2252 2251
2253 2252 /* must be in diagnostic mode for these commands to work */
2254 2253 if (pp->current_mode != ECPP_DIAG_MODE) {
2255 2254 ecpp_nack_ioctl(q, mp, EINVAL);
2256 2255 break;
2257 2256 }
2258 2257
2259 2258 switch (pp->port) {
2260 2259 case ECPP_PORT_PIO:
2261 2260 DATAR_WRITE(pp, *data);
2262 2261 ecpp_ack_ioctl(q, mp);
2263 2262 break;
2264 2263
2265 2264 case ECPP_PORT_TDMA:
2266 2265 TFIFO_WRITE(pp, *data);
2267 2266 ecpp_ack_ioctl(q, mp);
2268 2267 break;
2269 2268
2270 2269 default:
2271 2270 ecpp_nack_ioctl(q, mp, EINVAL);
2272 2271 }
2273 2272
2274 2273 break;
2275 2274 }
2276 2275
2277 2276 case ECPPIOC_GETDEVID: {
2278 2277 struct copyresp *csp;
2279 2278 struct ecpp_copystate *stp;
2280 2279 struct ecpp_device_id *dp;
2281 2280 struct ecpp_device_id id;
2282 2281
2283 2282 csp = (struct copyresp *)mp->b_rptr;
2284 2283 stp = (struct ecpp_copystate *)csp->cp_private->b_rptr;
2285 2284 dp = (struct ecpp_device_id *)mp->b_cont->b_rptr;
2286 2285
2287 2286 #ifdef _MULTI_DATAMODEL
2288 2287 if (IOC_CONVERT_FROM(iocbp) == IOC_ILP32) {
2289 2288 struct ecpp_device_id32 *dp32;
2290 2289
2291 2290 dp32 = (struct ecpp_device_id32 *)dp;
2292 2291 id.mode = dp32->mode;
2293 2292 id.len = dp32->len;
2294 2293 id.addr = (char *)(uintptr_t)dp32->addr;
2295 2294 } else {
2296 2295 #endif /* _MULTI_DATAMODEL */
2297 2296 id = *dp;
2298 2297 #ifdef _MULTI_DATAMODEL
2299 2298 }
2300 2299 #endif /* _MULTI_DATAMODEL */
2301 2300
2302 2301 ecpp_srvioc_devid(q, mp, &id, &stp->un.devid.rlen);
2303 2302 break;
2304 2303 }
2305 2304
2306 2305 case PRNIOC_GET_1284_DEVID: {
2307 2306 struct copyresp *csp;
2308 2307 struct ecpp_copystate *stp;
2309 2308 struct prn_1284_device_id *dp;
2310 2309 struct ecpp_device_id id;
2311 2310
2312 2311 csp = (struct copyresp *)mp->b_rptr;
2313 2312 stp = (struct ecpp_copystate *)csp->cp_private->b_rptr;
2314 2313 dp = (struct prn_1284_device_id *)mp->b_cont->b_rptr;
2315 2314
2316 2315 /* imitate struct ecpp_device_id */
2317 2316 id.mode = ECPP_NIBBLE_MODE;
2318 2317
2319 2318 #ifdef _MULTI_DATAMODEL
2320 2319 if (IOC_CONVERT_FROM(iocbp) == IOC_ILP32) {
2321 2320 struct prn_1284_device_id32 *dp32;
2322 2321
2323 2322 dp32 = (struct prn_1284_device_id32 *)dp;
2324 2323 id.len = dp32->id_len;
2325 2324 id.addr = (char *)(uintptr_t)dp32->id_data;
2326 2325 } else {
2327 2326 #endif /* _MULTI_DATAMODEL */
2328 2327 id.len = dp->id_len;
2329 2328 id.addr = (char *)dp->id_data;
2330 2329 #ifdef _MULTI_DATAMODEL
2331 2330 }
2332 2331 #endif /* _MULTI_DATAMODEL */
2333 2332
2334 2333 ecpp_srvioc_devid(q, mp, &id,
2335 2334 (int *)&stp->un.prn_devid.id_rlen);
2336 2335 break;
2337 2336 }
2338 2337
2339 2338 case PRNIOC_SET_IFCAP: {
2340 2339 uint_t ifcap, new_ifcap;
2341 2340
2342 2341 ifcap = ecpp_get_prn_ifcap(pp);
2343 2342 new_ifcap = *(uint_t *)mp->b_cont->b_rptr;
2344 2343
2345 2344 if (ifcap == new_ifcap) {
2346 2345 ecpp_ack_ioctl(q, mp);
2347 2346 break;
2348 2347 }
2349 2348
2350 2349 /* only changing PRN_BIDI is supported */
2351 2350 if ((ifcap ^ new_ifcap) & ~PRN_BIDI) {
2352 2351 ecpp_nack_ioctl(q, mp, EINVAL);
2353 2352 break;
2354 2353 }
2355 2354
2356 2355 if (new_ifcap & PRN_BIDI) { /* go bidirectional */
2357 2356 ecpp_default_negotiation(pp);
2358 2357 } else { /* go unidirectional */
2359 2358 (void) ecpp_mode_negotiation(pp, ECPP_CENTRONICS);
2360 2359 }
2361 2360
2362 2361 ecpp_ack_ioctl(q, mp);
2363 2362 break;
2364 2363 }
2365 2364
2366 2365 case PRNIOC_SET_TIMEOUTS: {
2367 2366 struct prn_timeouts *prn_timeouts;
2368 2367
2369 2368 prn_timeouts = (struct prn_timeouts *)mp->b_cont->b_rptr;
2370 2369
2371 2370 if (prn_timeouts->tmo_forward > ECPP_MAX_TIMEOUT) {
2372 2371 ecpp_nack_ioctl(q, mp, EINVAL);
2373 2372 break;
2374 2373 }
2375 2374
2376 2375 pp->prn_timeouts = *prn_timeouts;
2377 2376 pp->xfer_parms.write_timeout = (int)prn_timeouts->tmo_forward;
2378 2377
2379 2378 ecpp_ack_ioctl(q, mp);
2380 2379 break;
2381 2380 }
2382 2381
2383 2382 case PRNIOC_GET_IFINFO:
2384 2383 ecpp_srvioc_prnif(q, mp);
2385 2384 break;
2386 2385
2387 2386 default: /* unexpected ioctl type */
2388 2387 ecpp_nack_ioctl(q, mp, EINVAL);
2389 2388 break;
2390 2389 }
2391 2390 }
2392 2391
2393 2392 static void
2394 2393 ecpp_srvioc_devid(queue_t *q, mblk_t *mp, struct ecpp_device_id *id, int *rlen)
2395 2394 {
2396 2395 struct ecppunit *pp;
2397 2396 struct copyresp *csp;
2398 2397 struct ecpp_copystate *stp;
2399 2398 int error;
2400 2399 int len;
2401 2400 int mode;
2402 2401 mblk_t *datamp;
2403 2402
2404 2403 pp = (struct ecppunit *)q->q_ptr;
2405 2404 csp = (struct copyresp *)mp->b_rptr;
2406 2405 stp = (struct ecpp_copystate *)csp->cp_private->b_rptr;
2407 2406 mode = id->mode;
2408 2407
2409 2408 /* check arguments */
2410 2409 if ((mode < ECPP_CENTRONICS) || (mode > ECPP_ECP_MODE)) {
2411 2410 ecpp_error(pp->dip, "ecpp_srvioc_devid: mode=%x, len=%x\n",
2412 2411 mode, id->len);
2413 2412 ecpp_nack_ioctl(q, mp, EINVAL);
2414 2413 return;
2415 2414 }
2416 2415
2417 2416 /* Currently only Nibble mode is supported */
2418 2417 if (mode != ECPP_NIBBLE_MODE) {
2419 2418 ecpp_nack_ioctl(q, mp, EPROTONOSUPPORT);
2420 2419 return;
2421 2420 }
2422 2421
2423 2422 if ((id->addr == NULL) && (id->len != 0)) {
2424 2423 ecpp_nack_ioctl(q, mp, EFAULT);
2425 2424 return;
2426 2425 }
2427 2426
2428 2427 /* read device ID length */
2429 2428 if (error = ecpp_getdevid(pp, NULL, &len, mode)) {
2430 2429 ecpp_nack_ioctl(q, mp, error);
2431 2430 goto breakout;
2432 2431 }
2433 2432
2434 2433 /* don't take into account two length bytes */
2435 2434 len -= 2;
2436 2435 *rlen = len;
2437 2436
2438 2437 /* limit transfer to user buffer length */
2439 2438 if (id->len < len) {
2440 2439 len = id->len;
2441 2440 }
2442 2441
2443 2442 if (len == 0) {
2444 2443 /* just return rlen */
2445 2444 stp->state = ECPP_ADDROUT;
2446 2445 ecpp_wput_iocdata_devid(q, mp,
2447 2446 (uintptr_t)rlen - (uintptr_t)&stp->un);
2448 2447 goto breakout;
2449 2448 }
2450 2449
2451 2450 if ((datamp = allocb(len, BPRI_MED)) == NULL) {
2452 2451 ecpp_nack_ioctl(q, mp, ENOSR);
2453 2452 goto breakout;
2454 2453 }
2455 2454
2456 2455 /* read ID string */
2457 2456 error = ecpp_getdevid(pp, datamp->b_rptr, &len, mode);
2458 2457 if (error) {
2459 2458 freemsg(datamp);
2460 2459 ecpp_nack_ioctl(q, mp, error);
2461 2460 goto breakout;
2462 2461 } else {
2463 2462 datamp->b_wptr += len;
2464 2463
2465 2464 stp->state = ECPP_ADDROUT;
2466 2465 mcopyout(mp, csp->cp_private, len, id->addr, datamp);
2467 2466 qreply(q, mp);
2468 2467 }
2469 2468
2470 2469 return;
2471 2470
2472 2471 breakout:
2473 2472 (void) ecpp_1284_termination(pp);
2474 2473 }
2475 2474
2476 2475 /*
2477 2476 * PRNIOC_GET_IFINFO: return prnio interface info string
2478 2477 */
2479 2478 static void
2480 2479 ecpp_srvioc_prnif(queue_t *q, mblk_t *mp)
2481 2480 {
2482 2481 struct copyresp *csp;
2483 2482 struct ecpp_copystate *stp;
2484 2483 uint_t len;
2485 2484 struct prn_interface_info *ip;
2486 2485 struct prn_interface_info info;
2487 2486 mblk_t *datamp;
2488 2487 #ifdef _MULTI_DATAMODEL
2489 2488 struct iocblk *iocbp = (struct iocblk *)mp->b_rptr;
2490 2489 #endif
2491 2490
2492 2491 csp = (struct copyresp *)mp->b_rptr;
2493 2492 stp = (struct ecpp_copystate *)csp->cp_private->b_rptr;
2494 2493 ip = (struct prn_interface_info *)mp->b_cont->b_rptr;
2495 2494
2496 2495 #ifdef _MULTI_DATAMODEL
2497 2496 if (IOC_CONVERT_FROM(iocbp) == IOC_ILP32) {
2498 2497 struct prn_interface_info32 *ip32;
2499 2498
2500 2499 ip32 = (struct prn_interface_info32 *)ip;
2501 2500 info.if_len = ip32->if_len;
2502 2501 info.if_data = (char *)(uintptr_t)ip32->if_data;
2503 2502 } else {
2504 2503 #endif /* _MULTI_DATAMODEL */
2505 2504 info = *ip;
2506 2505 #ifdef _MULTI_DATAMODEL
2507 2506 }
2508 2507 #endif /* _MULTI_DATAMODEL */
2509 2508
2510 2509 len = strlen(prn_ifinfo);
2511 2510 stp->un.prn_if.if_rlen = len;
2512 2511 stp->state = ECPP_ADDROUT;
2513 2512
2514 2513 /* check arguments */
2515 2514 if ((info.if_data == NULL) && (info.if_len != 0)) {
2516 2515 ecpp_nack_ioctl(q, mp, EFAULT);
2517 2516 return;
2518 2517 }
2519 2518
2520 2519 if (info.if_len == 0) {
2521 2520 /* just copyout rlen */
2522 2521 ecpp_wput_iocdata_devid(q, mp,
2523 2522 offsetof(struct prn_interface_info, if_rlen));
2524 2523 return;
2525 2524 }
2526 2525
2527 2526 /* if needed, trim to the buffer size */
2528 2527 if (len > info.if_len) {
2529 2528 len = info.if_len;
2530 2529 }
2531 2530
2532 2531 if ((datamp = allocb(len, BPRI_MED)) == NULL) {
2533 2532 ecpp_nack_ioctl(q, mp, ENOSR);
2534 2533 return;
2535 2534 }
2536 2535
2537 2536 bcopy(&prn_ifinfo[0], datamp->b_wptr, len);
2538 2537 datamp->b_wptr += len;
2539 2538
2540 2539 mcopyout(mp, csp->cp_private, len, info.if_data, datamp);
2541 2540 qreply(q, mp);
2542 2541 }
2543 2542
2544 2543 static void
2545 2544 ecpp_flush(struct ecppunit *pp, int cmd)
2546 2545 {
2547 2546 queue_t *q;
2548 2547 uint8_t ecr, dcr;
2549 2548 timeout_id_t timeout_id, fifo_timer_id, wsrv_timer_id;
2550 2549
2551 2550 ASSERT(mutex_owned(&pp->umutex));
2552 2551
2553 2552 if (!(cmd & FWRITE)) {
2554 2553 return;
2555 2554 }
2556 2555
2557 2556 q = pp->writeq;
2558 2557 timeout_id = fifo_timer_id = wsrv_timer_id = 0;
2559 2558
2560 2559 ecpp_error(pp->dip, "ecpp_flush e_busy=%x\n", pp->e_busy);
2561 2560
2562 2561 /* if there is an ongoing DMA, it needs to be turned off. */
2563 2562 switch (pp->e_busy) {
2564 2563 case ECPP_BUSY:
2565 2564 /*
2566 2565 * Change the port status to ECPP_FLUSH to
2567 2566 * indicate to ecpp_wsrv that the wq is being flushed.
2568 2567 */
2569 2568 pp->e_busy = ECPP_FLUSH;
2570 2569
2571 2570 /*
2572 2571 * dma_cancelled indicates to ecpp_isr() that we have
2573 2572 * turned off the DMA. Since the mutex is held, ecpp_isr()
2574 2573 * may be blocked. Once ecpp_flush() finishes and ecpp_isr()
2575 2574 * gains the mutex, ecpp_isr() will have a _reset_ DMAC. Most
2576 2575 * significantly, the DMAC will be reset after ecpp_isr() was
2577 2576 * invoked. Therefore we need to have a flag "dma_cancelled"
2578 2577 * to signify when the described condition has occured. If
2579 2578 * ecpp_isr() notes a dma_cancelled, it will ignore the DMAC csr
2580 2579 * and simply claim the interupt.
2581 2580 */
2582 2581
2583 2582 pp->dma_cancelled = TRUE;
2584 2583
2585 2584 /* either DMA or PIO transfer */
2586 2585 if (COMPAT_DMA(pp) ||
2587 2586 (pp->current_mode == ECPP_ECP_MODE) ||
2588 2587 (pp->current_mode == ECPP_DIAG_MODE)) {
2589 2588 /*
2590 2589 * if the bcr is zero, then DMA is complete and
2591 2590 * we are waiting for the fifo to drain. Therefore,
2592 2591 * turn off dma.
2593 2592 */
2594 2593 if (ECPP_DMA_STOP(pp, NULL) == FAILURE) {
2595 2594 ecpp_error(pp->dip,
2596 2595 "ecpp_flush: dma_stop failed.\n");
2597 2596 }
2598 2597
2599 2598 /*
2600 2599 * If the status of the port is ECPP_BUSY,
2601 2600 * the DMA is stopped by either explicitly above, or by
2602 2601 * ecpp_isr() but the FIFO hasn't drained yet. In either
2603 2602 * case, we need to unbind the dma mappings.
2604 2603 */
2605 2604 if (ddi_dma_unbind_handle(
2606 2605 pp->dma_handle) != DDI_SUCCESS)
2607 2606 ecpp_error(pp->dip,
2608 2607 "ecpp_flush: unbind failed.\n");
2609 2608
2610 2609 if (pp->msg != NULL) {
2611 2610 freemsg(pp->msg);
2612 2611 pp->msg = NULL;
2613 2612 }
2614 2613 } else {
2615 2614 /*
2616 2615 * PIO transfer: disable nAck interrups
2617 2616 */
2618 2617 dcr = DCR_READ(pp);
2619 2618 dcr &= ~(ECPP_REV_DIR | ECPP_INTR_EN);
2620 2619 DCR_WRITE(pp, dcr);
2621 2620 ECPP_MASK_INTR(pp);
2622 2621 }
2623 2622
2624 2623 /*
2625 2624 * The transfer is cleaned up. There may or may not be data
2626 2625 * in the fifo. We don't care at this point. Ie. SuperIO may
2627 2626 * transfer the remaining bytes in the fifo or not. it doesn't
2628 2627 * matter. All that is important at this stage is that no more
2629 2628 * fifo timers are started.
2630 2629 */
2631 2630
2632 2631 timeout_id = pp->timeout_id;
2633 2632 fifo_timer_id = pp->fifo_timer_id;
2634 2633 pp->timeout_id = pp->fifo_timer_id = 0;
2635 2634 pp->softintr_pending = 0;
2636 2635
2637 2636 break;
2638 2637
2639 2638 case ECPP_ERR:
2640 2639 /*
2641 2640 * Change the port status to ECPP_FLUSH to
2642 2641 * indicate to ecpp_wsrv that the wq is being flushed.
2643 2642 */
2644 2643 pp->e_busy = ECPP_FLUSH;
2645 2644
2646 2645 /*
2647 2646 * Most likely there are mblks in the queue,
2648 2647 * but the driver can not transmit because
2649 2648 * of the bad port status. In this case,
2650 2649 * ecpp_flush() should make sure ecpp_wsrv_timer()
2651 2650 * is turned off.
2652 2651 */
2653 2652 wsrv_timer_id = pp->wsrv_timer_id;
2654 2653 pp->wsrv_timer_id = 0;
2655 2654
2656 2655 break;
2657 2656
2658 2657 case ECPP_IDLE:
2659 2658 /* No work to do. Ready to flush */
2660 2659 break;
2661 2660
2662 2661 default:
2663 2662 ecpp_error(pp->dip,
2664 2663 "ecpp_flush: illegal state %x\n", pp->e_busy);
2665 2664 }
2666 2665
2667 2666 /* in DIAG mode clear TFIFO if needed */
2668 2667 if (pp->current_mode == ECPP_DIAG_MODE) {
2669 2668 ecr = ECR_READ(pp);
2670 2669 if (!(ecr & ECPP_FIFO_EMPTY)) {
2671 2670 ECR_WRITE(pp,
2672 2671 ECPP_INTR_SRV | ECPP_INTR_MASK | ECR_mode_001);
2673 2672 ECR_WRITE(pp, ecr);
2674 2673 }
2675 2674 }
2676 2675
2677 2676 /* Discard all messages on the output queue. */
2678 2677 flushq(q, FLUSHDATA);
2679 2678
2680 2679 /* The port is no longer flushing or dma'ing for that matter. */
2681 2680 pp->e_busy = ECPP_IDLE;
2682 2681
2683 2682 /* Set the right phase */
2684 2683 if (pp->current_mode == ECPP_ECP_MODE) {
2685 2684 if (pp->current_phase == ECPP_PHASE_ECP_REV_XFER) {
2686 2685 pp->current_phase = ECPP_PHASE_ECP_REV_IDLE;
2687 2686 } else {
2688 2687 pp->current_phase = ECPP_PHASE_ECP_FWD_IDLE;
2689 2688 }
2690 2689 }
2691 2690
2692 2691 /* cancel timeouts if any */
2693 2692 mutex_exit(&pp->umutex);
2694 2693
2695 2694 if (timeout_id) {
2696 2695 (void) untimeout(timeout_id);
2697 2696 }
2698 2697 if (fifo_timer_id) {
2699 2698 (void) untimeout(fifo_timer_id);
2700 2699 }
2701 2700 if (wsrv_timer_id) {
2702 2701 (void) untimeout(wsrv_timer_id);
2703 2702 }
2704 2703
2705 2704 mutex_enter(&pp->umutex);
2706 2705
2707 2706 cv_signal(&pp->pport_cv); /* wake up ecpp_close() */
2708 2707 }
2709 2708
2710 2709 static void
2711 2710 ecpp_start(struct ecppunit *pp, caddr_t addr, size_t len)
2712 2711 {
2713 2712 ASSERT(mutex_owned(&pp->umutex));
2714 2713 ASSERT(pp->e_busy == ECPP_BUSY);
2715 2714
2716 2715 ecpp_error(pp->dip,
2717 2716 "ecpp_start:current_mode=%x,current_phase=%x,ecr=%x,len=%d\n",
2718 2717 pp->current_mode, pp->current_phase, ECR_READ(pp), len);
2719 2718
2720 2719 pp->dma_dir = DDI_DMA_WRITE; /* this is a forward transfer */
2721 2720
2722 2721 switch (pp->current_mode) {
2723 2722 case ECPP_NIBBLE_MODE:
2724 2723 (void) ecpp_1284_termination(pp);
2725 2724
2726 2725 /* After termination we are either Compatible or Centronics */
2727 2726
2728 2727 /* FALLTHRU */
2729 2728
2730 2729 case ECPP_CENTRONICS:
2731 2730 case ECPP_COMPAT_MODE:
2732 2731 if (pp->io_mode == ECPP_DMA) {
2733 2732 if (ecpp_init_dma_xfer(pp, addr, len) == FAILURE) {
2734 2733 return;
2735 2734 }
2736 2735 } else {
2737 2736 /* PIO mode */
2738 2737 if (ecpp_prep_pio_xfer(pp, addr, len) == FAILURE) {
2739 2738 return;
2740 2739 }
2741 2740 (void) ecpp_pio_writeb(pp);
2742 2741 }
2743 2742 break;
2744 2743
2745 2744 case ECPP_DIAG_MODE: {
2746 2745 int oldlen;
2747 2746
2748 2747 /* put superio into TFIFO mode, if not already */
2749 2748 ECR_WRITE(pp, ECPP_INTR_SRV | ECPP_INTR_MASK | ECR_mode_110);
2750 2749 /*
2751 2750 * DMA would block if the TFIFO is not empty
2752 2751 * if by this moment nobody read these bytes, they`re gone
2753 2752 */
2754 2753 drv_usecwait(1);
2755 2754 if (!(ECR_READ(pp) & ECPP_FIFO_EMPTY)) {
2756 2755 ecpp_error(pp->dip,
2757 2756 "ecpp_start: TFIFO not empty, clearing\n");
2758 2757 ECR_WRITE(pp,
2759 2758 ECPP_INTR_SRV | ECPP_INTR_MASK | ECR_mode_001);
2760 2759 ECR_WRITE(pp,
2761 2760 ECPP_INTR_SRV | ECPP_INTR_MASK | ECR_mode_110);
2762 2761 }
2763 2762
2764 2763 /* we can DMA at most 16 bytes into TFIFO */
2765 2764 oldlen = len;
2766 2765 if (len > ECPP_FIFO_SZ) {
2767 2766 len = ECPP_FIFO_SZ;
2768 2767 }
2769 2768
2770 2769 if (ecpp_init_dma_xfer(pp, addr, len) == FAILURE) {
2771 2770 return;
2772 2771 }
2773 2772
2774 2773 /* put the rest of data back on the queue */
2775 2774 if (oldlen > len) {
2776 2775 ecpp_putback_untransfered(pp, addr + len, oldlen - len);
2777 2776 }
2778 2777
2779 2778 break;
2780 2779 }
2781 2780
2782 2781 case ECPP_ECP_MODE:
2783 2782 ASSERT(pp->current_phase == ECPP_PHASE_ECP_FWD_IDLE ||
2784 2783 pp->current_phase == ECPP_PHASE_ECP_REV_IDLE);
2785 2784
2786 2785 /* if in Reverse Phase negotiate to Forward */
2787 2786 if (pp->current_phase == ECPP_PHASE_ECP_REV_IDLE) {
2788 2787 if (ecp_reverse2forward(pp) == FAILURE) {
2789 2788 if (pp->msg) {
2790 2789 (void) putbq(pp->writeq, pp->msg);
2791 2790 } else {
2792 2791 ecpp_putback_untransfered(pp,
2793 2792 addr, len);
2794 2793 }
2795 2794 }
2796 2795 }
2797 2796
2798 2797 if (ecpp_init_dma_xfer(pp, addr, len) == FAILURE) {
2799 2798 return;
2800 2799 }
2801 2800
2802 2801 break;
2803 2802 }
2804 2803
2805 2804 /* schedule transfer timeout */
2806 2805 pp->timeout_id = timeout(ecpp_xfer_timeout, (caddr_t)pp,
2807 2806 pp->xfer_parms.write_timeout * drv_usectohz(1000000));
2808 2807 }
2809 2808
2810 2809 /*
2811 2810 * Transfer a PIO "block" a byte at a time.
2812 2811 * The block is starts at addr and ends at pp->last_byte
2813 2812 */
2814 2813 static uint8_t
2815 2814 ecpp_prep_pio_xfer(struct ecppunit *pp, caddr_t addr, size_t len)
2816 2815 {
2817 2816 pp->next_byte = addr;
2818 2817 pp->last_byte = (caddr_t)((ulong_t)addr + len);
2819 2818
2820 2819 if (ecpp_check_status(pp) == FAILURE) {
2821 2820 /*
2822 2821 * if status signals are bad, do not start PIO,
2823 2822 * put everything back on the queue.
2824 2823 */
2825 2824 ecpp_error(pp->dip,
2826 2825 "ecpp_prep_pio_xfer:suspend PIO len=%d\n", len);
2827 2826
2828 2827 if (pp->msg != NULL) {
2829 2828 /*
2830 2829 * this circumstance we want to copy the
2831 2830 * untransfered section of msg to a new mblk,
2832 2831 * then free the orignal one.
2833 2832 */
2834 2833 ecpp_putback_untransfered(pp,
2835 2834 (void *)pp->msg->b_rptr, len);
2836 2835 ecpp_error(pp->dip,
2837 2836 "ecpp_prep_pio_xfer: len1=%d\n", len);
2838 2837
2839 2838 freemsg(pp->msg);
2840 2839 pp->msg = NULL;
2841 2840 } else {
2842 2841 ecpp_putback_untransfered(pp, pp->ioblock, len);
2843 2842 ecpp_error(pp->dip,
2844 2843 "ecpp_prep_pio_xfer: len2=%d\n", len);
2845 2844 }
2846 2845 qenable(pp->writeq);
2847 2846
2848 2847 return (FAILURE);
2849 2848 }
2850 2849
2851 2850 pp->dma_cancelled = FALSE;
2852 2851
2853 2852 /* pport must be in PIO mode */
2854 2853 if (ecr_write(pp, ECR_mode_001 |
2855 2854 ECPP_INTR_MASK | ECPP_INTR_SRV) != SUCCESS) {
2856 2855 ecpp_error(pp->dip, "ecpp_prep_pio_xfer: failed w/ECR.\n");
2857 2856 }
2858 2857
2859 2858 ecpp_error(pp->dip, "ecpp_prep_pio_xfer: dcr=%x ecr=%x\n",
2860 2859 DCR_READ(pp), ECR_READ(pp));
2861 2860
2862 2861 return (SUCCESS);
2863 2862 }
2864 2863
2865 2864 static uint8_t
2866 2865 ecpp_init_dma_xfer(struct ecppunit *pp, caddr_t addr, size_t len)
2867 2866 {
2868 2867 uint8_t ecr_mode[] = {
2869 2868 0,
2870 2869 ECR_mode_010, /* Centronix */
2871 2870 ECR_mode_010, /* Compat */
2872 2871 0, /* Byte */
2873 2872 0, /* Nibble */
2874 2873 ECR_mode_011, /* ECP */
2875 2874 0, /* Failure */
2876 2875 ECR_mode_110, /* Diag */
2877 2876 };
2878 2877 uint8_t ecr;
2879 2878
2880 2879 ASSERT((pp->current_mode <= ECPP_DIAG_MODE) &&
2881 2880 (ecr_mode[pp->current_mode] != 0));
2882 2881
2883 2882 if (ecpp_setup_dma_resources(pp, addr, len) == FAILURE) {
2884 2883 qenable(pp->writeq);
2885 2884 return (FAILURE);
2886 2885 }
2887 2886
2888 2887 if (ecpp_check_status(pp) == FAILURE) {
2889 2888 /*
2890 2889 * if status signals are bad, do not start DMA, but
2891 2890 * rather put everything back on the queue.
2892 2891 */
2893 2892 ecpp_error(pp->dip,
2894 2893 "ecpp_init_dma_xfer: suspending DMA len=%d\n",
2895 2894 pp->dma_cookie.dmac_size);
2896 2895
2897 2896 if (pp->msg != NULL) {
2898 2897 /*
2899 2898 * this circumstance we want to copy the
2900 2899 * untransfered section of msg to a new mblk,
2901 2900 * then free the orignal one.
2902 2901 */
2903 2902 ecpp_putback_untransfered(pp,
2904 2903 (void *)pp->msg->b_rptr, len);
2905 2904 ecpp_error(pp->dip,
2906 2905 "ecpp_init_dma_xfer:a:len=%d\n", len);
2907 2906
2908 2907 freemsg(pp->msg);
2909 2908 pp->msg = NULL;
2910 2909 } else {
2911 2910 ecpp_putback_untransfered(pp, pp->ioblock, len);
2912 2911 ecpp_error(pp->dip,
2913 2912 "ecpp_init_dma_xfer:b:len=%d\n", len);
2914 2913 }
2915 2914
2916 2915 if (ddi_dma_unbind_handle(pp->dma_handle) != DDI_SUCCESS) {
2917 2916 ecpp_error(pp->dip,
2918 2917 "ecpp_init_dma_xfer: unbind FAILURE.\n");
2919 2918 }
2920 2919 qenable(pp->writeq);
2921 2920 return (FAILURE);
2922 2921 }
2923 2922
2924 2923 pp->xfercnt = pp->resid = len;
2925 2924 pp->dma_cancelled = FALSE;
2926 2925 pp->tfifo_intr = 0;
2927 2926
2928 2927 /* set the right ECR mode and disable DMA */
2929 2928 ecr = ecr_mode[pp->current_mode];
2930 2929 (void) ecr_write(pp, ecr | ECPP_INTR_SRV | ECPP_INTR_MASK);
2931 2930
2932 2931 /* prepare DMAC for a transfer */
2933 2932 if (ECPP_DMA_START(pp) == FAILURE) {
2934 2933 ecpp_error(pp->dip, "ecpp_init_dma_xfer: dma_start FAILED.\n");
2935 2934 return (FAILURE);
2936 2935 }
2937 2936
2938 2937 /* GO! */
2939 2938 (void) ecr_write(pp, ecr | ECPP_DMA_ENABLE | ECPP_INTR_MASK);
2940 2939
2941 2940 return (SUCCESS);
2942 2941 }
2943 2942
2944 2943 static uint8_t
2945 2944 ecpp_setup_dma_resources(struct ecppunit *pp, caddr_t addr, size_t len)
2946 2945 {
2947 2946 int err;
2948 2947 off_t woff;
2949 2948 size_t wlen;
2950 2949
2951 2950 ASSERT(pp->dma_dir == DDI_DMA_READ || pp->dma_dir == DDI_DMA_WRITE);
2952 2951
2953 2952 err = ddi_dma_addr_bind_handle(pp->dma_handle, NULL,
2954 2953 addr, len, pp->dma_dir | DDI_DMA_PARTIAL,
2955 2954 DDI_DMA_DONTWAIT, NULL,
2956 2955 &pp->dma_cookie, &pp->dma_cookie_count);
2957 2956
2958 2957 switch (err) {
2959 2958 case DDI_DMA_MAPPED:
2960 2959 ecpp_error(pp->dip, "ecpp_setup_dma: DMA_MAPPED\n");
2961 2960
2962 2961 pp->dma_nwin = 1;
2963 2962 pp->dma_curwin = 1;
2964 2963 break;
2965 2964
2966 2965 case DDI_DMA_PARTIAL_MAP: {
2967 2966 ecpp_error(pp->dip, "ecpp_setup_dma: DMA_PARTIAL_MAP\n");
2968 2967
2969 2968 if (ddi_dma_numwin(pp->dma_handle,
2970 2969 &pp->dma_nwin) != DDI_SUCCESS) {
2971 2970 (void) ddi_dma_unbind_handle(pp->dma_handle);
2972 2971 return (FAILURE);
2973 2972 }
2974 2973 pp->dma_curwin = 1;
2975 2974
2976 2975 /*
2977 2976 * The very first window is returned by bind_handle,
2978 2977 * but we must do this explicitly here, otherwise
2979 2978 * next getwin would return wrong cookie dmac_size
2980 2979 */
2981 2980 if (ddi_dma_getwin(pp->dma_handle, 0, &woff, &wlen,
2982 2981 &pp->dma_cookie, &pp->dma_cookie_count) != DDI_SUCCESS) {
2983 2982 ecpp_error(pp->dip,
2984 2983 "ecpp_setup_dma: ddi_dma_getwin failed!");
2985 2984 (void) ddi_dma_unbind_handle(pp->dma_handle);
2986 2985 return (FAILURE);
2987 2986 }
2988 2987
2989 2988 ecpp_error(pp->dip,
2990 2989 "ecpp_setup_dma: cookies=%d, windows=%d"
2991 2990 " addr=%lx len=%d\n",
2992 2991 pp->dma_cookie_count, pp->dma_nwin,
2993 2992 pp->dma_cookie.dmac_address, pp->dma_cookie.dmac_size);
2994 2993
2995 2994 break;
2996 2995 }
2997 2996
2998 2997 default:
2999 2998 ecpp_error(pp->dip, "ecpp_setup_dma: err=%x\n", err);
3000 2999 return (FAILURE);
3001 3000 }
3002 3001
3003 3002 return (SUCCESS);
3004 3003 }
3005 3004
3006 3005 static void
3007 3006 ecpp_ack_ioctl(queue_t *q, mblk_t *mp)
3008 3007 {
3009 3008 struct iocblk *iocbp;
3010 3009
3011 3010 mp->b_datap->db_type = M_IOCACK;
3012 3011 mp->b_wptr = mp->b_rptr + sizeof (struct iocblk);
3013 3012
3014 3013 if (mp->b_cont) {
3015 3014 freemsg(mp->b_cont);
3016 3015 mp->b_cont = NULL;
3017 3016 }
3018 3017
3019 3018 iocbp = (struct iocblk *)mp->b_rptr;
3020 3019 iocbp->ioc_error = 0;
3021 3020 iocbp->ioc_count = 0;
3022 3021 iocbp->ioc_rval = 0;
3023 3022
3024 3023 qreply(q, mp);
3025 3024 }
3026 3025
3027 3026 static void
3028 3027 ecpp_nack_ioctl(queue_t *q, mblk_t *mp, int err)
3029 3028 {
3030 3029 struct iocblk *iocbp;
3031 3030
3032 3031 mp->b_datap->db_type = M_IOCNAK;
3033 3032 mp->b_wptr = mp->b_rptr + sizeof (struct iocblk);
3034 3033 iocbp = (struct iocblk *)mp->b_rptr;
3035 3034 iocbp->ioc_error = err;
3036 3035
3037 3036 if (mp->b_cont) {
3038 3037 freemsg(mp->b_cont);
3039 3038 mp->b_cont = NULL;
3040 3039 }
3041 3040
3042 3041 qreply(q, mp);
3043 3042 }
3044 3043
3045 3044 uint_t
3046 3045 ecpp_isr(caddr_t arg)
3047 3046 {
3048 3047 struct ecppunit *pp = (struct ecppunit *)(void *)arg;
3049 3048 uint32_t dcsr;
3050 3049 uint8_t dsr;
3051 3050 int cheerio_pend_counter;
3052 3051 int retval = DDI_INTR_UNCLAIMED;
3053 3052 hrtime_t now;
3054 3053
3055 3054 mutex_enter(&pp->umutex);
3056 3055 /*
3057 3056 * interrupt may occur while other thread is holding the lock
3058 3057 * and cancels DMA transfer (e.g. ecpp_flush())
3059 3058 * since it cannot cancel the interrupt thread,
3060 3059 * it just sets dma_cancelled to TRUE,
3061 3060 * telling interrupt handler to exit immediately
3062 3061 */
3063 3062 if (pp->dma_cancelled == TRUE) {
3064 3063 ecpp_error(pp->dip, "dma-cancel isr\n");
3065 3064
3066 3065 pp->intr_hard++;
3067 3066 pp->dma_cancelled = FALSE;
3068 3067
3069 3068 mutex_exit(&pp->umutex);
3070 3069 return (DDI_INTR_CLAIMED);
3071 3070 }
3072 3071
3073 3072 /* Southbridge interrupts are handled separately */
3074 3073 #if defined(__x86)
3075 3074 if (pp->hw == &x86)
3076 3075 #else
3077 3076 if (pp->hw == &m1553)
3078 3077 #endif
3079 3078 {
3080 3079 retval = ecpp_M1553_intr(pp);
3081 3080 if (retval == DDI_INTR_UNCLAIMED) {
3082 3081 goto unexpected;
3083 3082 }
3084 3083 mutex_exit(&pp->umutex);
3085 3084 return (DDI_INTR_CLAIMED);
3086 3085 }
3087 3086
3088 3087 /*
3089 3088 * the intr is through the motherboard. it is faster than PCI route.
3090 3089 * sometimes ecpp_isr() is invoked before cheerio csr is updated.
3091 3090 */
3092 3091 cheerio_pend_counter = ecpp_isr_max_delay;
3093 3092 dcsr = GET_DMAC_CSR(pp);
3094 3093
3095 3094 while (!(dcsr & DCSR_INT_PEND) && cheerio_pend_counter-- > 0) {
3096 3095 drv_usecwait(1);
3097 3096 dcsr = GET_DMAC_CSR(pp);
3098 3097 }
3099 3098
3100 3099 /*
3101 3100 * This is a workaround for what seems to be a timing problem
3102 3101 * with the delivery of interrupts and CSR updating with the
3103 3102 * ebus2 csr, superio and the n_ERR pin from the peripheral.
3104 3103 *
3105 3104 * delay is not needed for PIO mode
3106 3105 */
3107 3106 if (!COMPAT_PIO(pp)) {
3108 3107 drv_usecwait(100);
3109 3108 dcsr = GET_DMAC_CSR(pp);
3110 3109 }
3111 3110
3112 3111 /* on 97317 in Extended mode IRQ_ST of DSR is deasserted when read */
3113 3112 dsr = DSR_READ(pp);
3114 3113
3115 3114 /*
3116 3115 * check if interrupt is for this device:
3117 3116 * it should be reflected either in cheerio DCSR register
3118 3117 * or in IRQ_ST bit of DSR on 97317
3119 3118 */
3120 3119 if ((dcsr & DCSR_INT_PEND) == 0) {
3121 3120 if (pp->hw != &pc97317) {
3122 3121 goto unclaimed;
3123 3122 }
3124 3123 /*
3125 3124 * on Excalibur, reading DSR will deassert SuperIO IRQx line
3126 3125 * RIO's DCSR_INT_PEND seems to follow IRQx transitions,
3127 3126 * so if DSR is read after interrupt occured, but before
3128 3127 * we get here, IRQx and hence INT_PEND will be deasserted
3129 3128 * as a result, we can miss a service interrupt in PIO mode
3130 3129 *
3131 3130 * malicious DSR reader is BPPIOC_TESTIO, which is called
3132 3131 * by LP in between data blocks to check printer status
3133 3132 * this workaround lets us not to miss an interrupt
3134 3133 *
3135 3134 * also, nErr interrupt (ECP mode) not always reflected in DCSR
3136 3135 */
3137 3136 if (((dsr & ECPP_IRQ_ST) == 0) ||
3138 3137 ((COMPAT_PIO(pp)) && (pp->e_busy == ECPP_BUSY)) ||
3139 3138 (((dsr & ECPP_nERR) == 0) &&
3140 3139 (pp->current_mode == ECPP_ECP_MODE))) {
3141 3140 dcsr = 0;
3142 3141 } else {
3143 3142 goto unclaimed;
3144 3143 }
3145 3144 }
3146 3145
3147 3146 pp->intr_hard++;
3148 3147
3149 3148 /* the intr is for us - check all possible interrupt sources */
3150 3149 if (dcsr & DCSR_ERR_PEND) {
3151 3150 size_t bcr;
3152 3151
3153 3152 /* we are expecting a data transfer interrupt */
3154 3153 ASSERT(pp->e_busy == ECPP_BUSY);
3155 3154
3156 3155 /*
3157 3156 * some kind of DMA error
3158 3157 */
3159 3158 if (ECPP_DMA_STOP(pp, &bcr) == FAILURE) {
3160 3159 ecpp_error(pp->dip, "ecpp_isr: dma_stop failed\n");
3161 3160 }
3162 3161
3163 3162 ecpp_error(pp->dip, "ecpp_isr: DMAC ERROR bcr=%d\n", bcr);
3164 3163
3165 3164 ecpp_xfer_cleanup(pp);
3166 3165
3167 3166 if (ddi_dma_unbind_handle(pp->dma_handle) != DDI_SUCCESS) {
3168 3167 ecpp_error(pp->dip, "ecpp_isr(e): unbind failed\n");
3169 3168 }
3170 3169
3171 3170 mutex_exit(&pp->umutex);
3172 3171 return (DDI_INTR_CLAIMED);
3173 3172 }
3174 3173
3175 3174 if (dcsr & DCSR_TC) {
3176 3175 retval = ecpp_dma_ihdlr(pp);
3177 3176 mutex_exit(&pp->umutex);
3178 3177 return (DDI_INTR_CLAIMED);
3179 3178 }
3180 3179
3181 3180 if (COMPAT_PIO(pp)) {
3182 3181 retval = ecpp_pio_ihdlr(pp);
3183 3182 mutex_exit(&pp->umutex);
3184 3183 return (DDI_INTR_CLAIMED);
3185 3184 }
3186 3185
3187 3186 /* does peripheral need attention? */
3188 3187 if ((dsr & ECPP_nERR) == 0) {
3189 3188 retval = ecpp_nErr_ihdlr(pp);
3190 3189 mutex_exit(&pp->umutex);
3191 3190 return (DDI_INTR_CLAIMED);
3192 3191 }
3193 3192
3194 3193 pp->intr_hard--;
3195 3194
3196 3195 unexpected:
3197 3196
3198 3197 pp->intr_spurious++;
3199 3198
3200 3199 /*
3201 3200 * The following procedure tries to prevent soft hangs
3202 3201 * in event of peripheral/superio misbehaviour:
3203 3202 * if number of unexpected interrupts in the last SPUR_PERIOD ns
3204 3203 * exceeded SPUR_CRITICAL, then shut up interrupts
3205 3204 */
3206 3205 now = gethrtime();
3207 3206 if (pp->lastspur == 0 || now - pp->lastspur > SPUR_PERIOD) {
3208 3207 /* last unexpected interrupt was long ago */
3209 3208 pp->lastspur = now;
3210 3209 pp->nspur = 1;
3211 3210 } else {
3212 3211 /* last unexpected interrupt was recently */
3213 3212 pp->nspur++;
3214 3213 }
3215 3214
3216 3215 if (pp->nspur >= SPUR_CRITICAL) {
3217 3216 ECPP_MASK_INTR(pp);
3218 3217 ECR_WRITE(pp, ECR_READ(pp) | ECPP_INTR_MASK | ECPP_INTR_SRV);
3219 3218 pp->nspur = 0;
3220 3219 cmn_err(CE_NOTE, "%s%d: too many interrupt requests",
3221 3220 ddi_get_name(pp->dip), ddi_get_instance(pp->dip));
3222 3221 } else {
3223 3222 ECR_WRITE(pp, ECR_READ(pp) | ECPP_INTR_SRV | ECPP_INTR_MASK);
3224 3223 }
3225 3224
3226 3225 ecpp_error(pp->dip,
3227 3226 "isr:unknown: dcsr=%x ecr=%x dsr=%x dcr=%x\nmode=%x phase=%x\n",
3228 3227 dcsr, ECR_READ(pp), dsr, DCR_READ(pp),
3229 3228 pp->current_mode, pp->current_phase);
3230 3229
3231 3230 mutex_exit(&pp->umutex);
3232 3231 return (DDI_INTR_CLAIMED);
3233 3232
3234 3233 unclaimed:
3235 3234
3236 3235 pp->intr_spurious++;
3237 3236
3238 3237 ecpp_error(pp->dip,
3239 3238 "isr:UNCL: dcsr=%x ecr=%x dsr=%x dcr=%x\nmode=%x phase=%x\n",
3240 3239 dcsr, ECR_READ(pp), DSR_READ(pp), DCR_READ(pp),
3241 3240 pp->current_mode, pp->current_phase);
3242 3241
3243 3242 mutex_exit(&pp->umutex);
3244 3243 return (DDI_INTR_UNCLAIMED);
3245 3244 }
3246 3245
3247 3246 /*
3248 3247 * M1553 intr handler
3249 3248 */
3250 3249 static uint_t
3251 3250 ecpp_M1553_intr(struct ecppunit *pp)
3252 3251 {
3253 3252 int retval = DDI_INTR_UNCLAIMED;
3254 3253
3255 3254 pp->intr_hard++;
3256 3255
3257 3256 if (pp->e_busy == ECPP_BUSY) {
3258 3257 /* Centronics or Compat PIO transfer */
3259 3258 if (COMPAT_PIO(pp)) {
3260 3259 return (ecpp_pio_ihdlr(pp));
3261 3260 }
3262 3261
3263 3262 /* Centronics or Compat DMA transfer */
3264 3263 if (COMPAT_DMA(pp) ||
3265 3264 (pp->current_mode == ECPP_ECP_MODE) ||
3266 3265 (pp->current_mode == ECPP_DIAG_MODE)) {
3267 3266 return (ecpp_dma_ihdlr(pp));
3268 3267 }
3269 3268 }
3270 3269
3271 3270 /* Nibble or ECP backchannel request? */
3272 3271 if ((DSR_READ(pp) & ECPP_nERR) == 0) {
3273 3272 return (ecpp_nErr_ihdlr(pp));
3274 3273 }
3275 3274
3276 3275 return (retval);
3277 3276 }
3278 3277
3279 3278 /*
3280 3279 * DMA completion interrupt handler
3281 3280 */
3282 3281 static uint_t
3283 3282 ecpp_dma_ihdlr(struct ecppunit *pp)
3284 3283 {
3285 3284 clock_t tm;
3286 3285
3287 3286 ecpp_error(pp->dip, "ecpp_dma_ihdlr(%x): ecr=%x, dsr=%x, dcr=%x\n",
3288 3287 pp->current_mode, ECR_READ(pp), DSR_READ(pp), DCR_READ(pp));
3289 3288
3290 3289 /* we are expecting a data transfer interrupt */
3291 3290 ASSERT(pp->e_busy == ECPP_BUSY);
3292 3291
3293 3292 /* Intr generated while invoking TFIFO mode. Exit */
3294 3293 if (pp->tfifo_intr == 1) {
3295 3294 pp->tfifo_intr = 0;
3296 3295 ecpp_error(pp->dip, "ecpp_dma_ihdlr: tfifo_intr is 1\n");
3297 3296 return (DDI_INTR_CLAIMED);
3298 3297 }
3299 3298
3300 3299 if (ECPP_DMA_STOP(pp, NULL) == FAILURE) {
3301 3300 ecpp_error(pp->dip, "ecpp_dma_ihdlr: dma_stop failed\n");
3302 3301 }
3303 3302
3304 3303 if (pp->current_mode == ECPP_ECP_MODE &&
3305 3304 pp->current_phase == ECPP_PHASE_ECP_REV_XFER) {
3306 3305 ecpp_ecp_read_completion(pp);
3307 3306 } else {
3308 3307 /*
3309 3308 * fifo_timer() will do the cleanup when the FIFO drains
3310 3309 */
3311 3310 if ((ECR_READ(pp) & ECPP_FIFO_EMPTY) ||
3312 3311 (pp->current_mode == ECPP_DIAG_MODE)) {
3313 3312 tm = 0; /* no use in waiting if FIFO is already empty */
3314 3313 } else {
3315 3314 tm = drv_usectohz(FIFO_DRAIN_PERIOD);
3316 3315 }
3317 3316 pp->fifo_timer_id = timeout(ecpp_fifo_timer, (caddr_t)pp, tm);
3318 3317 }
3319 3318
3320 3319 /*
3321 3320 * Stop the DMA transfer timeout timer
3322 3321 * this operation will temporarily give up the mutex,
3323 3322 * so we do it in the end of the handler to avoid races
3324 3323 */
3325 3324 ecpp_untimeout_unblock(pp, &pp->timeout_id);
3326 3325
3327 3326 return (DDI_INTR_CLAIMED);
3328 3327 }
3329 3328
3330 3329 /*
3331 3330 * ecpp_pio_ihdlr() is a PIO interrupt processing routine
3332 3331 * It masks interrupts, updates statistics and initiates next byte transfer
3333 3332 */
3334 3333 static uint_t
3335 3334 ecpp_pio_ihdlr(struct ecppunit *pp)
3336 3335 {
3337 3336 ASSERT(mutex_owned(&pp->umutex));
3338 3337 ASSERT(pp->e_busy == ECPP_BUSY);
3339 3338
3340 3339 /* update statistics */
3341 3340 pp->joblen++;
3342 3341 pp->ctxpio_obytes++;
3343 3342
3344 3343 /* disable nAck interrups */
3345 3344 ECPP_MASK_INTR(pp);
3346 3345 DCR_WRITE(pp, DCR_READ(pp) & ~(ECPP_REV_DIR | ECPP_INTR_EN));
3347 3346
3348 3347 /*
3349 3348 * If it was the last byte of the data block cleanup,
3350 3349 * otherwise trigger a soft interrupt to send the next byte
3351 3350 */
3352 3351 if (pp->next_byte >= pp->last_byte) {
3353 3352 ecpp_xfer_cleanup(pp);
3354 3353 ecpp_error(pp->dip,
3355 3354 "ecpp_pio_ihdlr: pp->joblen=%d,pp->ctx_cf=%d,\n",
3356 3355 pp->joblen, pp->ctx_cf);
3357 3356 } else {
3358 3357 if (pp->softintr_pending) {
3359 3358 ecpp_error(pp->dip,
3360 3359 "ecpp_pio_ihdlr:E: next byte in progress\n");
3361 3360 } else {
3362 3361 pp->softintr_flags = ECPP_SOFTINTR_PIONEXT;
3363 3362 pp->softintr_pending = 1;
3364 3363 ddi_trigger_softintr(pp->softintr_id);
3365 3364 }
3366 3365 }
3367 3366
3368 3367 return (DDI_INTR_CLAIMED);
3369 3368 }
3370 3369
3371 3370 /*
3372 3371 * ecpp_pio_writeb() sends a byte using Centronics handshake
3373 3372 */
3374 3373 static void
3375 3374 ecpp_pio_writeb(struct ecppunit *pp)
3376 3375 {
3377 3376 uint8_t dcr;
3378 3377
3379 3378 dcr = DCR_READ(pp) & ~ECPP_REV_DIR;
3380 3379 dcr |= ECPP_INTR_EN;
3381 3380
3382 3381 /* send the next byte */
3383 3382 DATAR_WRITE(pp, *(pp->next_byte++));
3384 3383
3385 3384 drv_usecwait(pp->data_setup_time);
3386 3385
3387 3386 /* Now Assert (neg logic) nStrobe */
3388 3387 if (dcr_write(pp, dcr | ECPP_STB) == FAILURE) {
3389 3388 ecpp_error(pp->dip, "ecpp_pio_writeb:1: failed w/DCR\n");
3390 3389 }
3391 3390
3392 3391 /* Enable nAck interrupts */
3393 3392 (void) DSR_READ(pp); /* ensure IRQ_ST is armed */
3394 3393 ECPP_UNMASK_INTR(pp);
3395 3394
3396 3395 drv_usecwait(pp->strobe_pulse_width);
3397 3396
3398 3397 if (dcr_write(pp, dcr & ~ECPP_STB) == FAILURE) {
3399 3398 ecpp_error(pp->dip, "ecpp_pio_writeb:2: failed w/DCR\n");
3400 3399 }
3401 3400 }
3402 3401
3403 3402 /*
3404 3403 * Backchannel request interrupt handler
3405 3404 */
3406 3405 static uint_t
3407 3406 ecpp_nErr_ihdlr(struct ecppunit *pp)
3408 3407 {
3409 3408 ecpp_error(pp->dip, "ecpp_nErr_ihdlr: mode=%x, phase=%x\n",
3410 3409 pp->current_mode, pp->current_phase);
3411 3410
3412 3411 if (pp->oflag != TRUE) {
3413 3412 ecpp_error(pp->dip, "ecpp_nErr_ihdlr: not open!\n");
3414 3413 return (DDI_INTR_UNCLAIMED);
3415 3414 }
3416 3415
3417 3416 if (pp->e_busy == ECPP_BUSY) {
3418 3417 ecpp_error(pp->dip, "ecpp_nErr_ihdlr: busy\n");
3419 3418 ECR_WRITE(pp, ECR_READ(pp) | ECPP_INTR_MASK);
3420 3419 return (DDI_INTR_CLAIMED);
3421 3420 }
3422 3421
3423 3422 /* mask nErr & nAck interrupts */
3424 3423 ECPP_MASK_INTR(pp);
3425 3424 DCR_WRITE(pp, DCR_READ(pp) & ~(ECPP_INTR_EN | ECPP_REV_DIR));
3426 3425 ECR_WRITE(pp, ECR_READ(pp) | ECPP_INTR_MASK);
3427 3426
3428 3427 /* going reverse */
3429 3428 switch (pp->current_mode) {
3430 3429 case ECPP_ECP_MODE:
3431 3430 /*
3432 3431 * Peripheral asserts nPeriphRequest (nFault)
3433 3432 */
3434 3433 break;
3435 3434 case ECPP_NIBBLE_MODE:
3436 3435 /*
3437 3436 * Event 18: Periph asserts nErr to indicate data avail
3438 3437 * Event 19: After waiting minimum pulse width,
3439 3438 * periph sets nAck high to generate an interrupt
3440 3439 *
3441 3440 * Interface is in Interrupt Phase
3442 3441 */
3443 3442 pp->current_phase = ECPP_PHASE_NIBT_REVINTR;
3444 3443
3445 3444 break;
3446 3445 default:
3447 3446 ecpp_error(pp->dip, "ecpp_nErr_ihdlr: wrong mode!\n");
3448 3447 return (DDI_INTR_UNCLAIMED);
3449 3448 }
3450 3449
3451 3450 (void) ecpp_backchan_req(pp); /* put backchannel request on the wq */
3452 3451
3453 3452 return (DDI_INTR_CLAIMED);
3454 3453 }
3455 3454
3456 3455 /*
3457 3456 * Softintr handler does work according to softintr_flags:
3458 3457 * in case of ECPP_SOFTINTR_PIONEXT it sends next byte of PIO transfer
3459 3458 */
3460 3459 static uint_t
3461 3460 ecpp_softintr(caddr_t arg)
3462 3461 {
3463 3462 struct ecppunit *pp = (struct ecppunit *)arg;
3464 3463 uint32_t unx_len, ecpp_reattempts = 0;
3465 3464
3466 3465 mutex_enter(&pp->umutex);
3467 3466
3468 3467 pp->intr_soft++;
3469 3468
3470 3469 if (!pp->softintr_pending) {
3471 3470 mutex_exit(&pp->umutex);
3472 3471 return (DDI_INTR_CLAIMED);
3473 3472 } else {
3474 3473 pp->softintr_pending = 0;
3475 3474 }
3476 3475
3477 3476 if (pp->softintr_flags & ECPP_SOFTINTR_PIONEXT) {
3478 3477 pp->softintr_flags &= ~ECPP_SOFTINTR_PIONEXT;
3479 3478 /*
3480 3479 * Sent next byte in PIO mode
3481 3480 */
3482 3481 ecpp_reattempts = 0;
3483 3482 do {
3484 3483 if (ecpp_check_status(pp) == SUCCESS) {
3485 3484 pp->e_busy = ECPP_BUSY;
3486 3485 break;
3487 3486 }
3488 3487 drv_usecwait(1);
3489 3488 if (pp->isr_reattempt_high < ecpp_reattempts) {
3490 3489 pp->isr_reattempt_high = ecpp_reattempts;
3491 3490 }
3492 3491 } while (++ecpp_reattempts < pp->wait_for_busy);
3493 3492
3494 3493 /* if the peripheral still not recovered suspend the transfer */
3495 3494 if (pp->e_busy == ECPP_ERR) {
3496 3495 ++pp->ctx_cf; /* check status fail */
3497 3496 ecpp_error(pp->dip, "ecpp_softintr:check_status:F: "
3498 3497 "dsr=%x jl=%d cf_isr=%d\n",
3499 3498 DSR_READ(pp), pp->joblen, pp->ctx_cf);
3500 3499
3501 3500 /*
3502 3501 * if status signals are bad,
3503 3502 * put everything back on the wq.
3504 3503 */
3505 3504 unx_len = pp->last_byte - pp->next_byte;
3506 3505 if (pp->msg != NULL) {
3507 3506 ecpp_putback_untransfered(pp,
3508 3507 (void *)pp->msg->b_rptr, unx_len);
3509 3508 ecpp_error(pp->dip,
3510 3509 "ecpp_softintr:e1:unx_len=%d\n", unx_len);
3511 3510
3512 3511 freemsg(pp->msg);
3513 3512 pp->msg = NULL;
3514 3513 } else {
3515 3514 ecpp_putback_untransfered(pp,
3516 3515 pp->next_byte, unx_len);
3517 3516 ecpp_error(pp->dip,
3518 3517 "ecpp_softintr:e2:unx_len=%d\n", unx_len);
3519 3518 }
3520 3519
3521 3520 ecpp_xfer_cleanup(pp);
3522 3521 pp->e_busy = ECPP_ERR;
3523 3522 qenable(pp->writeq);
3524 3523 } else {
3525 3524 /* send the next one */
3526 3525 pp->e_busy = ECPP_BUSY;
3527 3526 (void) ecpp_pio_writeb(pp);
3528 3527 }
3529 3528 }
3530 3529
3531 3530 mutex_exit(&pp->umutex);
3532 3531 return (DDI_INTR_CLAIMED);
3533 3532 }
3534 3533
3535 3534
3536 3535 /*
3537 3536 * Transfer clean-up:
3538 3537 * shut down the DMAC
3539 3538 * stop the transfer timer
3540 3539 * enable write queue
3541 3540 */
3542 3541 static void
3543 3542 ecpp_xfer_cleanup(struct ecppunit *pp)
3544 3543 {
3545 3544 ASSERT(mutex_owned(&pp->umutex));
3546 3545
3547 3546 /*
3548 3547 * if we did not use the ioblock, the mblk that
3549 3548 * was used should be freed.
3550 3549 */
3551 3550 if (pp->msg != NULL) {
3552 3551 freemsg(pp->msg);
3553 3552 pp->msg = NULL;
3554 3553 }
3555 3554
3556 3555 /* The port is no longer active */
3557 3556 pp->e_busy = ECPP_IDLE;
3558 3557
3559 3558 /* Stop the transfer timeout timer */
3560 3559 ecpp_untimeout_unblock(pp, &pp->timeout_id);
3561 3560
3562 3561 qenable(pp->writeq);
3563 3562 }
3564 3563
3565 3564 /*VARARGS*/
3566 3565 static void
3567 3566 ecpp_error(dev_info_t *dip, char *fmt, ...)
3568 3567 {
3569 3568 static long last;
3570 3569 static char *lastfmt;
3571 3570 char msg_buffer[255];
3572 3571 va_list ap;
3573 3572 time_t now;
3574 3573
3575 3574 if (!ecpp_debug) {
3576 3575 return;
3577 3576 }
3578 3577
3579 3578 /*
3580 3579 * This function is supposed to be a quick non-blockable
3581 3580 * wrapper for cmn_err(9F), which provides a sensible degree
3582 3581 * of debug message throttling. Not using any type of lock
3583 3582 * is a requirement, but this also leaves two static variables
3584 3583 * - last and lastfmt - unprotected. However, this will not do
3585 3584 * any harm to driver functionality, it can only weaken throttling.
3586 3585 * The following directive asks warlock to not worry about these
3587 3586 * variables.
3588 3587 */
3589 3588 _NOTE(NOW_INVISIBLE_TO_OTHER_THREADS(last, lastfmt))
3590 3589
3591 3590 /*
3592 3591 * Don't print same error message too often.
3593 3592 */
3594 3593 now = gethrestime_sec();
3595 3594 if ((last == (now & ~1)) && (lastfmt == fmt))
3596 3595 return;
3597 3596
3598 3597 last = now & ~1;
3599 3598 lastfmt = fmt;
3600 3599
3601 3600 va_start(ap, fmt);
3602 3601 (void) vsprintf(msg_buffer, fmt, ap);
3603 3602 cmn_err(CE_CONT, "%s%d: %s", ddi_get_name(dip),
3604 3603 ddi_get_instance(dip), msg_buffer);
3605 3604 va_end(ap);
3606 3605 }
3607 3606
3608 3607 /*
3609 3608 * Forward transfer timeout
3610 3609 */
3611 3610 static void
3612 3611 ecpp_xfer_timeout(void *arg)
3613 3612 {
3614 3613 struct ecppunit *pp = arg;
3615 3614 void *unx_addr;
3616 3615 size_t unx_len, xferd;
3617 3616 uint8_t dcr;
3618 3617 timeout_id_t fifo_timer_id;
3619 3618
3620 3619 mutex_enter(&pp->umutex);
3621 3620
3622 3621 if (pp->timeout_id == 0) {
3623 3622 mutex_exit(&pp->umutex);
3624 3623 return;
3625 3624 } else {
3626 3625 pp->timeout_id = 0;
3627 3626 }
3628 3627
3629 3628 pp->xfer_tout++;
3630 3629
3631 3630 pp->dma_cancelled = TRUE; /* prevent race with isr() */
3632 3631
3633 3632 if (COMPAT_PIO(pp)) {
3634 3633 /*
3635 3634 * PIO mode timeout
3636 3635 */
3637 3636
3638 3637 /* turn off nAck interrupts */
3639 3638 dcr = DCR_READ(pp);
3640 3639 (void) dcr_write(pp, dcr & ~(ECPP_REV_DIR | ECPP_INTR_EN));
3641 3640 ECPP_MASK_INTR(pp);
3642 3641
3643 3642 pp->softintr_pending = 0;
3644 3643 unx_len = pp->last_byte - pp->next_byte;
3645 3644 ecpp_error(pp->dip, "xfer_timeout: unx_len=%d\n", unx_len);
3646 3645
3647 3646 if (unx_len > 0) {
3648 3647 unx_addr = pp->next_byte;
3649 3648 } else {
3650 3649 ecpp_xfer_cleanup(pp);
3651 3650 qenable(pp->writeq);
3652 3651 mutex_exit(&pp->umutex);
3653 3652 return;
3654 3653 }
3655 3654 } else {
3656 3655 /*
3657 3656 * DMA mode timeout
3658 3657 *
3659 3658 * If DMAC fails to shut off, continue anyways and attempt
3660 3659 * to put untransfered data back on queue.
3661 3660 */
3662 3661 if (ECPP_DMA_STOP(pp, &unx_len) == FAILURE) {
3663 3662 ecpp_error(pp->dip,
3664 3663 "ecpp_xfer_timeout: failed dma_stop\n");
3665 3664 }
3666 3665
3667 3666 ecpp_error(pp->dip, "xfer_timeout: unx_len=%d\n", unx_len);
3668 3667
3669 3668 if (ddi_dma_unbind_handle(pp->dma_handle) == DDI_FAILURE) {
3670 3669 ecpp_error(pp->dip,
3671 3670 "ecpp_xfer_timeout: failed unbind\n");
3672 3671 }
3673 3672
3674 3673 /*
3675 3674 * if the bcr is zero, then DMA is complete and
3676 3675 * we are waiting for the fifo to drain. So let
3677 3676 * ecpp_fifo_timer() look after the clean up.
3678 3677 */
3679 3678 if (unx_len == 0) {
3680 3679 qenable(pp->writeq);
3681 3680 mutex_exit(&pp->umutex);
3682 3681 return;
3683 3682 } else {
3684 3683 xferd = pp->dma_cookie.dmac_size - unx_len;
3685 3684 pp->resid -= xferd;
3686 3685 unx_len = pp->resid;
3687 3686
3688 3687 /* update statistics */
3689 3688 pp->obytes[pp->current_mode] += xferd;
3690 3689 pp->joblen += xferd;
3691 3690
3692 3691 if (pp->msg != NULL) {
3693 3692 unx_addr = (caddr_t)pp->msg->b_wptr - unx_len;
3694 3693 } else {
3695 3694 unx_addr = pp->ioblock +
3696 3695 (pp->xfercnt - unx_len);
3697 3696 }
3698 3697 }
3699 3698 }
3700 3699
3701 3700 /* Following code is common for PIO and DMA modes */
3702 3701
3703 3702 ecpp_putback_untransfered(pp, (caddr_t)unx_addr, unx_len);
3704 3703
3705 3704 if (pp->msg != NULL) {
3706 3705 freemsg(pp->msg);
3707 3706 pp->msg = NULL;
3708 3707 }
3709 3708
3710 3709 /* mark the error status structure */
3711 3710 pp->timeout_error = 1;
3712 3711 pp->e_busy = ECPP_ERR;
3713 3712 fifo_timer_id = pp->fifo_timer_id;
3714 3713 pp->fifo_timer_id = 0;
3715 3714
3716 3715 qenable(pp->writeq);
3717 3716
3718 3717 mutex_exit(&pp->umutex);
3719 3718
3720 3719 if (fifo_timer_id) {
3721 3720 (void) untimeout(fifo_timer_id);
3722 3721 }
3723 3722 }
3724 3723
3725 3724 static void
3726 3725 ecpp_putback_untransfered(struct ecppunit *pp, void *startp, uint_t len)
3727 3726 {
3728 3727 mblk_t *new_mp;
3729 3728
3730 3729 ecpp_error(pp->dip, "ecpp_putback_untrans=%d\n", len);
3731 3730
3732 3731 if (len == 0) {
3733 3732 return;
3734 3733 }
3735 3734
3736 3735 new_mp = allocb(len, BPRI_MED);
3737 3736 if (new_mp == NULL) {
3738 3737 ecpp_error(pp->dip,
3739 3738 "ecpp_putback_untransfered: allocb FAILURE.\n");
3740 3739 return;
3741 3740 }
3742 3741
3743 3742 bcopy(startp, new_mp->b_rptr, len);
3744 3743 new_mp->b_wptr = new_mp->b_rptr + len;
3745 3744
3746 3745 if (!putbq(pp->writeq, new_mp)) {
3747 3746 freemsg(new_mp);
3748 3747 }
3749 3748 }
3750 3749
3751 3750 static uchar_t
3752 3751 ecr_write(struct ecppunit *pp, uint8_t ecr_byte)
3753 3752 {
3754 3753 int i, current_ecr;
3755 3754
3756 3755 for (i = ECPP_REG_WRITE_MAX_LOOP; i > 0; i--) {
3757 3756 ECR_WRITE(pp, ecr_byte);
3758 3757
3759 3758 current_ecr = ECR_READ(pp);
3760 3759
3761 3760 /* mask off the lower two read-only bits */
3762 3761 if ((ecr_byte & 0xFC) == (current_ecr & 0xFC))
3763 3762 return (SUCCESS);
3764 3763 }
3765 3764 return (FAILURE);
3766 3765 }
3767 3766
3768 3767 static uchar_t
3769 3768 dcr_write(struct ecppunit *pp, uint8_t dcr_byte)
3770 3769 {
3771 3770 uint8_t current_dcr;
3772 3771 int i;
3773 3772
3774 3773 for (i = ECPP_REG_WRITE_MAX_LOOP; i > 0; i--) {
3775 3774 DCR_WRITE(pp, dcr_byte);
3776 3775
3777 3776 current_dcr = DCR_READ(pp);
3778 3777
3779 3778 /* compare only bits 0-4 (direction bit return 1) */
3780 3779 if ((dcr_byte & 0x1F) == (current_dcr & 0x1F))
3781 3780 return (SUCCESS);
3782 3781 }
3783 3782 ecpp_error(pp->dip,
3784 3783 "(%d)dcr_write: dcr written =%x, dcr readback =%x\n",
3785 3784 i, dcr_byte, current_dcr);
3786 3785
3787 3786 return (FAILURE);
3788 3787 }
3789 3788
3790 3789 static uchar_t
3791 3790 ecpp_reset_port_regs(struct ecppunit *pp)
3792 3791 {
3793 3792 DCR_WRITE(pp, ECPP_SLCTIN | ECPP_nINIT);
3794 3793 ECR_WRITE(pp, ECR_mode_001 | ECPP_INTR_MASK | ECPP_INTR_SRV);
3795 3794 return (SUCCESS);
3796 3795 }
3797 3796
3798 3797 /*
3799 3798 * The data transferred by the DMA engine goes through the FIFO,
3800 3799 * so that when the DMA counter reaches zero (and an interrupt occurs)
3801 3800 * the FIFO can still contain data. If this is the case, the ISR will
3802 3801 * schedule this callback to wait until the FIFO drains or a timeout occurs.
3803 3802 */
3804 3803 static void
3805 3804 ecpp_fifo_timer(void *arg)
3806 3805 {
3807 3806 struct ecppunit *pp = arg;
3808 3807 uint8_t ecr;
3809 3808 timeout_id_t timeout_id;
3810 3809
3811 3810 mutex_enter(&pp->umutex);
3812 3811
3813 3812 /*
3814 3813 * If the FIFO timer has been turned off, exit.
3815 3814 */
3816 3815 if (pp->fifo_timer_id == 0) {
3817 3816 ecpp_error(pp->dip, "ecpp_fifo_timer: untimedout\n");
3818 3817 mutex_exit(&pp->umutex);
3819 3818 return;
3820 3819 } else {
3821 3820 pp->fifo_timer_id = 0;
3822 3821 }
3823 3822
3824 3823 /*
3825 3824 * If the FIFO is not empty restart timer. Wait FIFO_DRAIN_PERIOD
3826 3825 * (250 ms) and check FIFO_EMPTY bit again. Repeat until FIFO is
3827 3826 * empty or until 10 * FIFO_DRAIN_PERIOD expires.
3828 3827 */
3829 3828 ecr = ECR_READ(pp);
3830 3829
3831 3830 if ((pp->current_mode != ECPP_DIAG_MODE) &&
3832 3831 (((ecr & ECPP_FIFO_EMPTY) == 0) &&
3833 3832 (pp->ecpp_drain_counter < 10))) {
3834 3833
3835 3834 ecpp_error(pp->dip,
3836 3835 "ecpp_fifo_timer(%d):FIFO not empty:ecr=%x\n",
3837 3836 pp->ecpp_drain_counter, ecr);
3838 3837
3839 3838 pp->fifo_timer_id = timeout(ecpp_fifo_timer,
3840 3839 (caddr_t)pp, drv_usectohz(FIFO_DRAIN_PERIOD));
3841 3840 ++pp->ecpp_drain_counter;
3842 3841
3843 3842 mutex_exit(&pp->umutex);
3844 3843 return;
3845 3844 }
3846 3845
3847 3846 if (pp->current_mode != ECPP_DIAG_MODE) {
3848 3847 /*
3849 3848 * If the FIFO won't drain after 10 FIFO_DRAIN_PERIODs
3850 3849 * then don't wait any longer. Simply clean up the transfer.
3851 3850 */
3852 3851 if (pp->ecpp_drain_counter >= 10) {
3853 3852 ecpp_error(pp->dip, "ecpp_fifo_timer(%d):"
3854 3853 " clearing FIFO,can't wait:ecr=%x\n",
3855 3854 pp->ecpp_drain_counter, ecr);
3856 3855 } else {
3857 3856 ecpp_error(pp->dip,
3858 3857 "ecpp_fifo_timer(%d):FIFO empty:ecr=%x\n",
3859 3858 pp->ecpp_drain_counter, ecr);
3860 3859 }
3861 3860
3862 3861 pp->ecpp_drain_counter = 0;
3863 3862 }
3864 3863
3865 3864 /*
3866 3865 * Main section of routine:
3867 3866 * - stop the DMA transfer timer
3868 3867 * - program DMA with next cookie/window or unbind the DMA mapping
3869 3868 * - update stats
3870 3869 * - if last mblk in queue, signal to close() & return to idle state
3871 3870 */
3872 3871
3873 3872 /* Stop the DMA transfer timeout timer */
3874 3873 timeout_id = pp->timeout_id;
3875 3874 pp->timeout_id = 0;
3876 3875
3877 3876 /* data has drained from fifo, it is ok to free dma resource */
3878 3877 if (pp->current_mode == ECPP_ECP_MODE ||
3879 3878 pp->current_mode == ECPP_DIAG_MODE ||
3880 3879 COMPAT_DMA(pp)) {
3881 3880 off_t off;
3882 3881 size_t len;
3883 3882
3884 3883 /* update residual */
3885 3884 pp->resid -= pp->dma_cookie.dmac_size;
3886 3885
3887 3886 /* update statistics */
3888 3887 pp->joblen += pp->dma_cookie.dmac_size;
3889 3888 if (pp->dma_dir == DDI_DMA_WRITE) {
3890 3889 pp->obytes[pp->current_mode] +=
3891 3890 pp->dma_cookie.dmac_size;
3892 3891 } else {
3893 3892 pp->ibytes[pp->current_mode] +=
3894 3893 pp->dma_cookie.dmac_size;
3895 3894 }
3896 3895
3897 3896 /*
3898 3897 * Look if any cookies/windows left
3899 3898 */
3900 3899 if (--pp->dma_cookie_count > 0) {
3901 3900 /* process the next cookie */
3902 3901 ddi_dma_nextcookie(pp->dma_handle,
3903 3902 &pp->dma_cookie);
3904 3903 } else if (pp->dma_curwin < pp->dma_nwin) {
3905 3904 /* process the next window */
3906 3905 if (ddi_dma_getwin(pp->dma_handle,
3907 3906 pp->dma_curwin, &off, &len,
3908 3907 &pp->dma_cookie,
3909 3908 &pp->dma_cookie_count) != DDI_SUCCESS) {
3910 3909 ecpp_error(pp->dip,
3911 3910 "ecpp_fifo_timer: ddi_dma_getwin failed\n");
3912 3911 goto dma_done;
3913 3912 }
3914 3913
3915 3914 pp->dma_curwin++;
3916 3915 } else {
3917 3916 goto dma_done;
3918 3917 }
3919 3918
3920 3919 ecpp_error(pp->dip, "ecpp_fifo_timer: next addr=%llx len=%d\n",
3921 3920 pp->dma_cookie.dmac_address,
3922 3921 pp->dma_cookie.dmac_size);
3923 3922
3924 3923 /* kick off new transfer */
3925 3924 if (ECPP_DMA_START(pp) != SUCCESS) {
3926 3925 ecpp_error(pp->dip,
3927 3926 "ecpp_fifo_timer: dma_start failed\n");
3928 3927 goto dma_done;
3929 3928 }
3930 3929
3931 3930 (void) ecr_write(pp, (ecr & 0xe0) |
3932 3931 ECPP_DMA_ENABLE | ECPP_INTR_MASK);
3933 3932
3934 3933 mutex_exit(&pp->umutex);
3935 3934
3936 3935 if (timeout_id) {
3937 3936 (void) untimeout(timeout_id);
3938 3937 }
3939 3938 return;
3940 3939
3941 3940 dma_done:
3942 3941 if (ddi_dma_unbind_handle(pp->dma_handle) != DDI_SUCCESS) {
3943 3942 ecpp_error(pp->dip, "ecpp_fifo_timer: unbind failed\n");
3944 3943 } else {
3945 3944 ecpp_error(pp->dip, "ecpp_fifo_timer: unbind ok\n");
3946 3945 }
3947 3946 }
3948 3947
3949 3948 /*
3950 3949 * if we did not use the dmablock, the mblk that
3951 3950 * was used should be freed.
3952 3951 */
3953 3952 if (pp->msg != NULL) {
3954 3953 freemsg(pp->msg);
3955 3954 pp->msg = NULL;
3956 3955 }
3957 3956
3958 3957 /* The port is no longer active */
3959 3958 pp->e_busy = ECPP_IDLE;
3960 3959
3961 3960 qenable(pp->writeq);
3962 3961
3963 3962 mutex_exit(&pp->umutex);
3964 3963
3965 3964 if (timeout_id) {
3966 3965 (void) untimeout(timeout_id);
3967 3966 }
3968 3967 }
3969 3968
3970 3969 /*
3971 3970 * In Compatibility mode, check if the peripheral is ready to accept data
3972 3971 */
3973 3972 static uint8_t
3974 3973 ecpp_check_status(struct ecppunit *pp)
3975 3974 {
3976 3975 uint8_t dsr;
3977 3976 uint8_t statmask;
3978 3977
3979 3978 if (pp->current_mode == ECPP_ECP_MODE ||
3980 3979 pp->current_mode == ECPP_DIAG_MODE)
3981 3980 return (SUCCESS);
3982 3981
3983 3982 statmask = ECPP_nERR | ECPP_SLCT | ECPP_nBUSY | ECPP_nACK;
3984 3983
3985 3984 dsr = DSR_READ(pp);
3986 3985 if ((dsr & ECPP_PE) || ((dsr & statmask) != statmask)) {
3987 3986 pp->e_busy = ECPP_ERR;
3988 3987 return (FAILURE);
3989 3988 } else {
3990 3989 return (SUCCESS);
3991 3990 }
3992 3991 }
3993 3992
3994 3993 /*
3995 3994 * if the peripheral is not ready to accept data, write service routine
3996 3995 * periodically reschedules itself to recheck peripheral status
3997 3996 * and start data transfer as soon as possible
3998 3997 */
3999 3998 static void
4000 3999 ecpp_wsrv_timer(void *arg)
4001 4000 {
4002 4001 struct ecppunit *pp = arg;
4003 4002
4004 4003 ecpp_error(pp->dip, "ecpp_wsrv_timer: starting\n");
4005 4004
4006 4005 mutex_enter(&pp->umutex);
4007 4006
4008 4007 if (pp->wsrv_timer_id == 0) {
4009 4008 mutex_exit(&pp->umutex);
4010 4009 return;
4011 4010 } else {
4012 4011 pp->wsrv_timer_id = 0;
4013 4012 }
4014 4013
4015 4014 ecpp_error(pp->dip, "ecpp_wsrv_timer: qenabling...\n");
4016 4015
4017 4016 qenable(pp->writeq);
4018 4017
4019 4018 mutex_exit(&pp->umutex);
4020 4019 }
4021 4020
4022 4021 /*
4023 4022 * Allocate a message indicating a backchannel request
4024 4023 * and put it on the write queue
4025 4024 */
4026 4025 static int
4027 4026 ecpp_backchan_req(struct ecppunit *pp)
4028 4027 {
4029 4028 mblk_t *mp;
4030 4029
4031 4030 if ((mp = allocb(sizeof (int), BPRI_MED)) == NULL) {
4032 4031 ecpp_error(pp->dip, "ecpp_backchan_req: allocb failed\n");
4033 4032 return (FAILURE);
4034 4033 } else {
4035 4034 mp->b_datap->db_type = M_CTL;
4036 4035 *(int *)mp->b_rptr = ECPP_BACKCHANNEL;
4037 4036 mp->b_wptr = mp->b_rptr + sizeof (int);
4038 4037 if (!putbq(pp->writeq, mp)) {
4039 4038 ecpp_error(pp->dip, "ecpp_backchan_req:putbq failed\n");
4040 4039 freemsg(mp);
4041 4040 return (FAILURE);
4042 4041 }
4043 4042 return (SUCCESS);
4044 4043 }
4045 4044 }
4046 4045
4047 4046 /*
4048 4047 * Cancel the function scheduled with timeout(9F)
4049 4048 * This function is to be called with the mutex held
4050 4049 */
4051 4050 static void
4052 4051 ecpp_untimeout_unblock(struct ecppunit *pp, timeout_id_t *id)
4053 4052 {
4054 4053 timeout_id_t saved_id;
4055 4054
4056 4055 ASSERT(mutex_owned(&pp->umutex));
4057 4056
4058 4057 if (*id) {
4059 4058 saved_id = *id;
4060 4059 *id = 0;
4061 4060 mutex_exit(&pp->umutex);
4062 4061 (void) untimeout(saved_id);
4063 4062 mutex_enter(&pp->umutex);
4064 4063 }
4065 4064 }
4066 4065
4067 4066 /*
4068 4067 * get prnio interface capabilities
4069 4068 */
4070 4069 static uint_t
4071 4070 ecpp_get_prn_ifcap(struct ecppunit *pp)
4072 4071 {
4073 4072 uint_t ifcap;
4074 4073
4075 4074 ifcap = PRN_1284_DEVID | PRN_TIMEOUTS | PRN_STREAMS;
4076 4075
4077 4076 /* status (DSR) only makes sense in Centronics & Compat modes */
4078 4077 if (pp->current_mode == ECPP_CENTRONICS ||
4079 4078 pp->current_mode == ECPP_COMPAT_MODE) {
4080 4079 ifcap |= PRN_1284_STATUS;
4081 4080 } else if (pp->current_mode == ECPP_NIBBLE_MODE ||
4082 4081 pp->current_mode == ECPP_ECP_MODE) {
4083 4082 ifcap |= PRN_BIDI;
4084 4083 }
4085 4084
4086 4085 return (ifcap);
4087 4086 }
4088 4087
4089 4088 /*
4090 4089 * Determine SuperI/O type
4091 4090 */
4092 4091 static struct ecpp_hw_bind *
4093 4092 ecpp_determine_sio_type(struct ecppunit *pp)
4094 4093 {
4095 4094 struct ecpp_hw_bind *hw_bind;
4096 4095 char *name;
4097 4096 int i;
4098 4097
4099 4098 name = ddi_binding_name(pp->dip);
4100 4099
4101 4100 for (hw_bind = NULL, i = 0; i < NELEM(ecpp_hw_bind); i++) {
4102 4101 if (strcmp(name, ecpp_hw_bind[i].name) == 0) {
4103 4102 hw_bind = &ecpp_hw_bind[i];
4104 4103 break;
4105 4104 }
4106 4105 }
4107 4106
4108 4107 return (hw_bind);
4109 4108 }
4110 4109
4111 4110
4112 4111 /*
4113 4112 *
4114 4113 * IEEE 1284 support routines:
4115 4114 * negotiation and termination;
4116 4115 * phase transitions;
4117 4116 * device ID;
4118 4117 *
4119 4118 */
4120 4119
4121 4120 /*
4122 4121 * Interface initialization, abnormal termination into Compatibility mode
4123 4122 *
4124 4123 * Peripheral may be non-1284, so we set current mode to ECPP_CENTRONICS
4125 4124 */
4126 4125 static void
4127 4126 ecpp_1284_init_interface(struct ecppunit *pp)
4128 4127 {
4129 4128 ECR_WRITE(pp, ECPP_INTR_SRV | ECPP_INTR_MASK | ECR_mode_001);
4130 4129
4131 4130 /*
4132 4131 * Toggle the nInit signal if configured in ecpp.conf
4133 4132 * for most peripherals it is not needed
4134 4133 */
4135 4134 if (pp->init_seq == TRUE) {
4136 4135 DCR_WRITE(pp, ECPP_SLCTIN);
4137 4136 drv_usecwait(50); /* T(ER) = 50us */
4138 4137 }
4139 4138
4140 4139 DCR_WRITE(pp, ECPP_nINIT | ECPP_SLCTIN);
4141 4140
4142 4141 pp->current_mode = pp->backchannel = ECPP_CENTRONICS;
4143 4142 pp->current_phase = ECPP_PHASE_C_IDLE;
4144 4143 ECPP_CONFIG_MODE(pp);
4145 4144 pp->to_mode[pp->current_mode]++;
4146 4145
4147 4146 ecpp_error(pp->dip, "ecpp_1284_init_interface: ok\n");
4148 4147 }
4149 4148
4150 4149 /*
4151 4150 * ECP mode negotiation
4152 4151 */
4153 4152 static int
4154 4153 ecp_negotiation(struct ecppunit *pp)
4155 4154 {
4156 4155 uint8_t dsr;
4157 4156
4158 4157 /* ECP mode negotiation */
4159 4158
4160 4159 if (ecpp_1284_negotiation(pp, ECPP_XREQ_ECP, &dsr) == FAILURE)
4161 4160 return (FAILURE);
4162 4161
4163 4162 /* Event 5: peripheral deasserts PError and Busy, asserts Select */
4164 4163 if ((dsr & (ECPP_PE | ECPP_nBUSY | ECPP_SLCT)) !=
4165 4164 (ECPP_nBUSY | ECPP_SLCT)) {
4166 4165 ecpp_error(pp->dip,
4167 4166 "ecp_negotiation: failed event 5 %x\n", DSR_READ(pp));
4168 4167 (void) ecpp_1284_termination(pp);
4169 4168 return (FAILURE);
4170 4169 }
4171 4170
4172 4171 /* entered Setup Phase */
4173 4172 pp->current_phase = ECPP_PHASE_ECP_SETUP;
4174 4173
4175 4174 /* Event 30: host asserts nAutoFd */
4176 4175 DCR_WRITE(pp, ECPP_nINIT | ECPP_AFX);
4177 4176
4178 4177 /* Event 31: peripheral asserts PError */
4179 4178 if (wait_dsr(pp, ECPP_PE, ECPP_PE, 35000) < 0) {
4180 4179 ecpp_error(pp->dip,
4181 4180 "ecp_negotiation: failed event 31 %x\n", DSR_READ(pp));
4182 4181 (void) ecpp_1284_termination(pp);
4183 4182 return (FAILURE);
4184 4183 }
4185 4184
4186 4185 /* entered Forward Idle Phase */
4187 4186 pp->current_phase = ECPP_PHASE_ECP_FWD_IDLE;
4188 4187
4189 4188 /* successful negotiation into ECP mode */
4190 4189 pp->current_mode = ECPP_ECP_MODE;
4191 4190 pp->backchannel = ECPP_ECP_MODE;
4192 4191
4193 4192 ecpp_error(pp->dip, "ecp_negotiation: ok\n");
4194 4193
4195 4194 return (SUCCESS);
4196 4195 }
4197 4196
4198 4197 /*
4199 4198 * Nibble mode negotiation
4200 4199 */
4201 4200 static int
4202 4201 nibble_negotiation(struct ecppunit *pp)
4203 4202 {
4204 4203 uint8_t dsr;
4205 4204
4206 4205 if (ecpp_1284_negotiation(pp, ECPP_XREQ_NIBBLE, &dsr) == FAILURE) {
4207 4206 return (FAILURE);
4208 4207 }
4209 4208
4210 4209 /*
4211 4210 * If peripheral has data available, PE and nErr will
4212 4211 * be set low at Event 5 & 6.
4213 4212 */
4214 4213 if ((dsr & (ECPP_PE | ECPP_nERR)) == 0) {
4215 4214 pp->current_phase = ECPP_PHASE_NIBT_AVAIL;
4216 4215 } else {
4217 4216 pp->current_phase = ECPP_PHASE_NIBT_NAVAIL;
4218 4217 }
4219 4218
4220 4219 /* successful negotiation into Nibble mode */
4221 4220 pp->current_mode = ECPP_NIBBLE_MODE;
4222 4221 pp->backchannel = ECPP_NIBBLE_MODE;
4223 4222
4224 4223 ecpp_error(pp->dip, "nibble_negotiation: ok (phase=%x)\n",
4225 4224 pp->current_phase);
4226 4225
4227 4226 return (SUCCESS);
4228 4227
4229 4228 }
4230 4229
4231 4230 /*
4232 4231 * Wait ptimeout usec for periph to set 'mask' bits to 'val' state
4233 4232 *
4234 4233 * return value < 0 indicates timeout
4235 4234 */
4236 4235 static int
4237 4236 wait_dsr(struct ecppunit *pp, uint8_t mask, uint8_t val, int ptimeout)
4238 4237 {
4239 4238 while (((DSR_READ(pp) & mask) != val) && ptimeout--) {
4240 4239 drv_usecwait(1);
4241 4240 }
4242 4241
4243 4242 return (ptimeout);
4244 4243 }
4245 4244
4246 4245 /*
4247 4246 * 1284 negotiation Events 0..6
4248 4247 * required mode is indicated by extensibility request value
4249 4248 *
4250 4249 * After successful negotiation SUCCESS is returned and
4251 4250 * current mode is set according to xreq,
4252 4251 * otherwise FAILURE is returned and current mode is set to
4253 4252 * either COMPAT (1284 periph) or CENTRONICS (non-1284 periph)
4254 4253 *
4255 4254 * Current phase must be set by the caller (mode-specific negotiation)
4256 4255 *
4257 4256 * If rdsr is not NULL, DSR value after Event 6 is stored here
4258 4257 */
4259 4258 static int
4260 4259 ecpp_1284_negotiation(struct ecppunit *pp, uint8_t xreq, uint8_t *rdsr)
4261 4260 {
4262 4261 int xflag;
4263 4262
4264 4263 ecpp_error(pp->dip, "nego(%x): entering...\n", xreq);
4265 4264
4266 4265 /* negotiation should start in Compatibility mode */
4267 4266 (void) ecpp_1284_termination(pp);
4268 4267
4269 4268 /* Set host into Compat mode */
4270 4269 ECR_WRITE(pp, ECPP_INTR_SRV | ECPP_INTR_MASK | ECR_mode_001);
4271 4270
4272 4271 pp->current_phase = ECPP_PHASE_NEGO;
4273 4272
4274 4273 /* Event 0: host sets extensibility request on data lines */
4275 4274 DATAR_WRITE(pp, xreq);
4276 4275
4277 4276 /* Event 1: host deassert nSelectin and assert nAutoFd */
4278 4277 DCR_WRITE(pp, ECPP_nINIT | ECPP_AFX);
4279 4278
4280 4279 drv_usecwait(1); /* Tp(ecp) == 0.5us */
4281 4280
4282 4281 /*
4283 4282 * Event 2: peripheral asserts nAck, deasserts nFault,
4284 4283 * asserts Select, asserts PError
4285 4284 */
4286 4285 if (wait_dsr(pp, ECPP_nERR | ECPP_SLCT | ECPP_PE | ECPP_nACK,
4287 4286 ECPP_nERR | ECPP_SLCT | ECPP_PE, 35000) < 0) {
4288 4287 /* peripheral is not 1284-compliant */
4289 4288 ecpp_error(pp->dip,
4290 4289 "nego(%x): failed event 2 %x\n", xreq, DSR_READ(pp));
4291 4290 (void) ecpp_1284_termination(pp);
4292 4291 return (FAILURE);
4293 4292 }
4294 4293
4295 4294 /*
4296 4295 * Event 3: host asserts nStrobe, latching extensibility value into
4297 4296 * peripherals input latch.
4298 4297 */
4299 4298 DCR_WRITE(pp, ECPP_nINIT | ECPP_AFX | ECPP_STB);
4300 4299
4301 4300 drv_usecwait(2); /* Tp(ecp) = 0.5us */
4302 4301
4303 4302 /*
4304 4303 * Event 4: hosts deasserts nStrobe and nAutoFD to acknowledge that
4305 4304 * it has recognized an 1284 compatible peripheral
4306 4305 */
4307 4306 DCR_WRITE(pp, ECPP_nINIT);
4308 4307
4309 4308 /*
4310 4309 * Event 5: Peripheral confirms it supports requested extension
4311 4310 * For Nibble mode Xflag must be low, otherwise it must be high
4312 4311 */
4313 4312 xflag = (xreq == ECPP_XREQ_NIBBLE) ? 0 : ECPP_SLCT;
4314 4313
4315 4314 /*
4316 4315 * Event 6: Peripheral sets nAck high
4317 4316 * indicating that status lines are valid
4318 4317 */
4319 4318 if (wait_dsr(pp, ECPP_nACK, ECPP_nACK, 35000) < 0) {
4320 4319 /* Something wrong with peripheral */
4321 4320 ecpp_error(pp->dip,
4322 4321 "nego(%x): failed event 6 %x\n", xreq, DSR_READ(pp));
4323 4322 (void) ecpp_1284_termination(pp);
4324 4323 return (FAILURE);
4325 4324 }
4326 4325
4327 4326 if ((DSR_READ(pp) & ECPP_SLCT) != xflag) {
4328 4327 /* Extensibility value is not supported */
4329 4328 ecpp_error(pp->dip,
4330 4329 "nego(%x): failed event 5 %x\n", xreq, DSR_READ(pp));
4331 4330 (void) ecpp_1284_termination(pp);
4332 4331 return (FAILURE);
4333 4332 }
4334 4333
4335 4334 if (rdsr) {
4336 4335 *rdsr = DSR_READ(pp);
4337 4336 }
4338 4337
4339 4338 return (SUCCESS);
4340 4339 }
4341 4340
4342 4341 /*
4343 4342 * 1284 Termination: Events 22..28 - set link to Compatibility mode
4344 4343 *
4345 4344 * This routine is not designed for Immediate termination,
4346 4345 * caller must take care of waiting for a valid state,
4347 4346 * (in particular, in ECP mode current phase must be Forward Idle)
4348 4347 * otherwise interface will be reinitialized
4349 4348 *
4350 4349 * In case of Valid state termination SUCCESS is returned and
4351 4350 * current_mode is ECPP_COMPAT_MODE, current phase is ECPP_PHASE_C_IDLE
4352 4351 * Otherwise interface is reinitialized, FAILURE is returned and
4353 4352 * current mode is ECPP_CENTRONICS, current phase is ECPP_PHASE_C_IDLE
4354 4353 */
4355 4354 static int
4356 4355 ecpp_1284_termination(struct ecppunit *pp)
4357 4356 {
4358 4357 int previous_mode = pp->current_mode;
4359 4358
4360 4359 if (((pp->current_mode == ECPP_COMPAT_MODE ||
4361 4360 pp->current_mode == ECPP_CENTRONICS) &&
4362 4361 pp->current_phase == ECPP_PHASE_C_IDLE) ||
4363 4362 pp->current_mode == ECPP_DIAG_MODE) {
4364 4363 ecpp_error(pp->dip, "termination: not needed\n");
4365 4364 return (SUCCESS);
4366 4365 }
4367 4366
4368 4367 /* Set host into Compat mode, interrupts disabled */
4369 4368 ECPP_MASK_INTR(pp);
4370 4369 ECR_WRITE(pp, ECPP_INTR_SRV | ECPP_INTR_MASK | ECR_mode_001);
4371 4370
4372 4371 pp->current_mode = ECPP_COMPAT_MODE; /* needed by next function */
4373 4372
4374 4373 ECPP_CONFIG_MODE(pp);
4375 4374
4376 4375 /*
4377 4376 * EPP mode uses simple nInit pulse for termination
4378 4377 */
4379 4378 if (previous_mode == ECPP_EPP_MODE) {
4380 4379 /* Event 68: host sets nInit low */
4381 4380 DCR_WRITE(pp, 0);
4382 4381
4383 4382 drv_usecwait(55); /* T(ER) = 50us */
4384 4383
4385 4384 /* Event 69: host sets nInit high */
4386 4385 DCR_WRITE(pp, ECPP_nINIT | ECPP_SLCTIN);
4387 4386
4388 4387 goto endterm;
4389 4388 }
4390 4389
4391 4390 /* terminate peripheral to Compat mode */
4392 4391 pp->current_phase = ECPP_PHASE_TERM;
4393 4392
4394 4393 /* Event 22: hosts sets nSelectIn low and nAutoFd high */
4395 4394 DCR_WRITE(pp, ECPP_nINIT | ECPP_SLCTIN);
4396 4395
4397 4396 /* Event 23: peripheral deasserts nFault and nBusy */
4398 4397 /* Event 24: peripheral asserts nAck */
4399 4398 if (wait_dsr(pp, ECPP_nERR | ECPP_nBUSY | ECPP_nACK,
4400 4399 ECPP_nERR, 35000) < 0) {
4401 4400 ecpp_error(pp->dip,
4402 4401 "termination: failed events 23,24 %x\n", DSR_READ(pp));
4403 4402 ecpp_1284_init_interface(pp);
4404 4403 return (FAILURE);
4405 4404 }
4406 4405
4407 4406 drv_usecwait(1); /* Tp = 0.5us */
4408 4407
4409 4408 /* Event 25: hosts sets nAutoFd low */
4410 4409 DCR_WRITE(pp, ECPP_nINIT | ECPP_SLCTIN | ECPP_AFX);
4411 4410
4412 4411 /* Event 26: the peripheral puts itself in Compatible mode */
4413 4412
4414 4413 /* Event 27: peripheral deasserts nAck */
4415 4414 if (wait_dsr(pp, ECPP_nACK, ECPP_nACK, 35000) < 0) {
4416 4415 ecpp_error(pp->dip,
4417 4416 "termination: failed event 27 %x\n", DSR_READ(pp));
4418 4417 ecpp_1284_init_interface(pp);
4419 4418 return (FAILURE);
4420 4419 }
4421 4420
4422 4421 drv_usecwait(1); /* Tp = 0.5us */
4423 4422
4424 4423 /* Event 28: hosts deasserts nAutoFd */
4425 4424 DCR_WRITE(pp, ECPP_nINIT | ECPP_SLCTIN);
4426 4425
4427 4426 drv_usecwait(1); /* Tp = 0.5us */
4428 4427
4429 4428 endterm:
4430 4429 /* Compatible mode Idle Phase */
4431 4430 pp->current_phase = ECPP_PHASE_C_IDLE;
4432 4431
4433 4432 ecpp_error(pp->dip, "termination: completed %x %x\n",
4434 4433 DSR_READ(pp), DCR_READ(pp));
4435 4434
4436 4435 return (SUCCESS);
4437 4436 }
4438 4437
4439 4438 /*
4440 4439 * Initiate ECP backchannel DMA transfer
4441 4440 */
4442 4441 static uchar_t
4443 4442 ecp_peripheral2host(struct ecppunit *pp)
4444 4443 {
4445 4444 mblk_t *mp = NULL;
4446 4445 size_t len;
4447 4446 uint32_t xfer_time;
4448 4447
4449 4448 ASSERT(pp->current_mode == ECPP_ECP_MODE &&
4450 4449 pp->current_phase == ECPP_PHASE_ECP_REV_IDLE);
4451 4450
4452 4451 /*
4453 4452 * hardware generates cycles to receive data from the peripheral
4454 4453 * we only need to read from FIFO
4455 4454 */
4456 4455
4457 4456 /*
4458 4457 * If user issued read(2) of rev_resid bytes, xfer exactly this amount
4459 4458 * unless it exceeds ECP_REV_BLKSZ_MAX; otherwise try to read
4460 4459 * ECP_REV_BLKSZ_MAX or at least ECP_REV_BLKSZ bytes
4461 4460 */
4462 4461 if (pp->nread > 0) {
4463 4462 len = min(pp->nread, ECP_REV_BLKSZ_MAX);
4464 4463 } else {
4465 4464 len = ECP_REV_BLKSZ_MAX;
4466 4465 }
4467 4466
4468 4467 pp->nread = 0; /* clear after use */
4469 4468
4470 4469 /*
4471 4470 * Allocate mblk for data, make max 2 attepmts:
4472 4471 * if len bytes block fails, try our block size
4473 4472 */
4474 4473 while ((mp = allocb(len, BPRI_MED)) == NULL) {
4475 4474 ecpp_error(pp->dip,
4476 4475 "ecp_periph2host: failed allocb(%d)\n", len);
4477 4476 if (len > ECP_REV_BLKSZ) {
4478 4477 len = ECP_REV_BLKSZ;
4479 4478 } else {
4480 4479 break;
4481 4480 }
4482 4481 }
4483 4482
4484 4483 if (mp == NULL) {
4485 4484 goto fail;
4486 4485 }
4487 4486
4488 4487 pp->msg = mp;
4489 4488 pp->e_busy = ECPP_BUSY;
4490 4489 pp->dma_dir = DDI_DMA_READ;
4491 4490 pp->current_phase = ECPP_PHASE_ECP_REV_XFER;
4492 4491
4493 4492 if (ecpp_init_dma_xfer(pp, (caddr_t)mp->b_rptr, len) == FAILURE) {
4494 4493 goto fail;
4495 4494 }
4496 4495
4497 4496 /*
4498 4497 * there are two problems with defining ECP backchannel xfer timeout
4499 4498 *
4500 4499 * a) IEEE 1284 allows infinite time between backchannel bytes,
4501 4500 * but we must stop at some point to send the data upstream,
4502 4501 * look if any forward transfer requests are pending, etc;
4503 4502 * all that done, we can continue with backchannel data;
4504 4503 *
4505 4504 * b) we don`t know how much data peripheral has;
4506 4505 * DMA counter is set to our buffer size, which can be bigger
4507 4506 * than needed - in this case a timeout must detect this;
4508 4507 *
4509 4508 * The timeout we schedule here serves as both the transfer timeout
4510 4509 * and a means of detecting backchannel stalls; in fact, there are
4511 4510 * two timeouts in one:
4512 4511 *
4513 4512 * - transfer timeout is based on the ECP bandwidth of ~1MB/sec and
4514 4513 * equals the time needed to transfer the whole buffer
4515 4514 * (but not less than ECP_REV_MINTOUT ms); if it occurs,
4516 4515 * DMA is stopped and the data is sent upstream;
4517 4516 *
4518 4517 * - backchannel watchdog, which would look at DMA counter
4519 4518 * every rev_watchdog ms and stop the transfer only
4520 4519 * if the counter hasn`t changed since the last time;
4521 4520 * otherwise it would save DMA counter value and restart itself;
4522 4521 *
4523 4522 * transfer timeout is a multiple of rev_watchdog
4524 4523 * and implemented as a downward counter
4525 4524 *
4526 4525 * on Grover, we can`t access DMAC registers while DMA is in flight,
4527 4526 * so we can`t have watchdog on Grover, only timeout
4528 4527 */
4529 4528
4530 4529 /* calculate number of watchdog invocations equal to the xfer timeout */
4531 4530 xfer_time = max((1000 * len) / pp->ecp_rev_speed, ECP_REV_MINTOUT);
4532 4531 #if defined(__x86)
4533 4532 pp->rev_timeout_cnt = (pp->hw == &x86) ? 1 :
4534 4533 max(xfer_time / pp->rev_watchdog, 1);
4535 4534 #else
4536 4535 pp->rev_timeout_cnt = (pp->hw == &m1553) ? 1 :
4537 4536 max(xfer_time / pp->rev_watchdog, 1);
4538 4537 #endif
4539 4538
4540 4539 pp->last_dmacnt = len; /* nothing xferred yet */
4541 4540
4542 4541 pp->timeout_id = timeout(ecpp_ecp_read_timeout, (caddr_t)pp,
4543 4542 drv_usectohz(pp->rev_watchdog * 1000));
4544 4543
4545 4544 ecpp_error(pp->dip, "ecp_periph2host: DMA started len=%d\n"
4546 4545 "xfer_time=%d wdog=%d cnt=%d\n",
4547 4546 len, xfer_time, pp->rev_watchdog, pp->rev_timeout_cnt);
4548 4547
4549 4548 return (SUCCESS);
4550 4549
4551 4550 fail:
4552 4551 if (mp) {
4553 4552 freemsg(mp);
4554 4553 }
4555 4554 pp->e_busy = ECPP_IDLE;
4556 4555 pp->current_phase = ECPP_PHASE_ECP_REV_IDLE;
4557 4556
4558 4557 return (FAILURE);
4559 4558 }
4560 4559
4561 4560 /*
4562 4561 * ECP backchannel read timeout
4563 4562 * implements both backchannel watchdog and transfer timeout in ECP mode
4564 4563 * if the transfer is still in progress, reschedule itself,
4565 4564 * otherwise call completion routine
4566 4565 */
4567 4566 static void
4568 4567 ecpp_ecp_read_timeout(void *arg)
4569 4568 {
4570 4569 struct ecppunit *pp = arg;
4571 4570 size_t dmacnt;
4572 4571
4573 4572 mutex_enter(&pp->umutex);
4574 4573
4575 4574 if (pp->timeout_id == 0) {
4576 4575 mutex_exit(&pp->umutex);
4577 4576 return;
4578 4577 } else {
4579 4578 pp->timeout_id = 0;
4580 4579 }
4581 4580
4582 4581 if (--pp->rev_timeout_cnt == 0) {
4583 4582 /*
4584 4583 * Transfer timed out
4585 4584 */
4586 4585 ecpp_error(pp->dip, "ecp_read_timeout: timeout\n");
4587 4586 pp->xfer_tout++;
4588 4587 ecpp_ecp_read_completion(pp);
4589 4588 } else {
4590 4589 /*
4591 4590 * Backchannel watchdog:
4592 4591 * look if DMA made any progress from the last time
4593 4592 */
4594 4593 dmacnt = ECPP_DMA_GETCNT(pp);
4595 4594 if (dmacnt - pp->last_dmacnt == 0) {
4596 4595 /*
4597 4596 * No progress - stop the transfer and send
4598 4597 * whatever has been read so far up the stream
4599 4598 */
4600 4599 ecpp_error(pp->dip, "ecp_read_timeout: no progress\n");
4601 4600 pp->xfer_tout++;
4602 4601 ecpp_ecp_read_completion(pp);
4603 4602 } else {
4604 4603 /*
4605 4604 * Something was transferred - restart ourselves
4606 4605 */
4607 4606 ecpp_error(pp->dip, "ecp_read_timeout: restarting\n");
4608 4607 pp->last_dmacnt = dmacnt;
4609 4608 pp->timeout_id = timeout(ecpp_ecp_read_timeout,
4610 4609 (caddr_t)pp,
4611 4610 drv_usectohz(pp->rev_watchdog * 1000));
4612 4611 }
4613 4612 }
4614 4613
4615 4614 mutex_exit(&pp->umutex);
4616 4615 }
4617 4616
4618 4617 /*
4619 4618 * ECP backchannel read completion:
4620 4619 * stop the DMA, free DMA resources and send read data upstream
4621 4620 */
4622 4621 static void
4623 4622 ecpp_ecp_read_completion(struct ecppunit *pp)
4624 4623 {
4625 4624 size_t xfer_len, unx_len;
4626 4625 mblk_t *mp;
4627 4626
4628 4627 ASSERT(mutex_owned(&pp->umutex));
4629 4628 ASSERT(pp->current_mode == ECPP_ECP_MODE &&
4630 4629 pp->current_phase == ECPP_PHASE_ECP_REV_XFER);
4631 4630 ASSERT(pp->msg != NULL);
4632 4631
4633 4632 /*
4634 4633 * Stop the transfer and unbind DMA handle
4635 4634 */
4636 4635 if (ECPP_DMA_STOP(pp, &unx_len) == FAILURE) {
4637 4636 unx_len = pp->resid;
4638 4637 ecpp_error(pp->dip, "ecp_read_completion: failed dma_stop\n");
4639 4638 }
4640 4639
4641 4640 mp = pp->msg;
4642 4641 xfer_len = pp->resid - unx_len; /* how much data was transferred */
4643 4642
4644 4643 if (ddi_dma_unbind_handle(pp->dma_handle) != DDI_SUCCESS) {
4645 4644 ecpp_error(pp->dip, "ecp_read_completion: unbind failed.\n");
4646 4645 }
4647 4646
4648 4647 ecpp_error(pp->dip, "ecp_read_completion: xfered %d bytes of %d\n",
4649 4648 xfer_len, pp->resid);
4650 4649
4651 4650 /* clean up and update statistics */
4652 4651 pp->msg = NULL;
4653 4652 pp->resid -= xfer_len;
4654 4653 pp->ibytes[pp->current_mode] += xfer_len;
4655 4654 pp->e_busy = ECPP_IDLE;
4656 4655 pp->current_phase = ECPP_PHASE_ECP_REV_IDLE;
4657 4656
4658 4657 /*
4659 4658 * Send the read data up the stream
4660 4659 */
4661 4660 mp->b_wptr += xfer_len;
4662 4661 if (canputnext(pp->readq)) {
4663 4662 mutex_exit(&pp->umutex);
4664 4663 putnext(pp->readq, mp);
4665 4664 mutex_enter(&pp->umutex);
4666 4665 } else {
4667 4666 ecpp_error(pp->dip, "ecp_read_completion: fail canputnext\n");
4668 4667 if (!putq(pp->readq, mp)) {
4669 4668 freemsg(mp);
4670 4669 }
4671 4670 }
4672 4671
4673 4672 /* if bytes left in the FIFO another transfer is needed */
4674 4673 if (!(ECR_READ(pp) & ECPP_FIFO_EMPTY)) {
4675 4674 (void) ecpp_backchan_req(pp);
4676 4675 }
4677 4676
4678 4677 qenable(pp->writeq);
4679 4678 }
4680 4679
4681 4680 /*
4682 4681 * Read one byte in the Nibble mode
4683 4682 */
4684 4683 static uchar_t
4685 4684 nibble_peripheral2host(struct ecppunit *pp, uint8_t *byte)
4686 4685 {
4687 4686 uint8_t n[2]; /* two nibbles */
4688 4687 int i;
4689 4688
4690 4689 /*
4691 4690 * One byte is made of two nibbles
4692 4691 */
4693 4692 for (i = 0; i < 2; i++) {
4694 4693 /* Event 7, 12: host asserts nAutoFd to move to read a nibble */
4695 4694 DCR_WRITE(pp, ECPP_nINIT | ECPP_AFX);
4696 4695
4697 4696 /* Event 8: peripheral puts data on the status lines */
4698 4697
4699 4698 /* Event 9: peripheral asserts nAck, data available */
4700 4699 if (wait_dsr(pp, ECPP_nACK, 0, 35000) < 0) {
4701 4700 ecpp_error(pp->dip,
4702 4701 "nibble_periph2host(%d): failed event 9 %x\n",
4703 4702 i + 1, DSR_READ(pp));
4704 4703 (void) ecpp_1284_termination(pp);
4705 4704 return (FAILURE);
4706 4705 }
4707 4706
4708 4707 n[i] = DSR_READ(pp); /* get a nibble */
4709 4708
4710 4709 /* Event 10: host deasserts nAutoFd to say it grabbed data */
4711 4710 DCR_WRITE(pp, ECPP_nINIT);
4712 4711
4713 4712 /* (2) Event 13: peripheral asserts PE - end of data phase */
4714 4713
4715 4714 /* Event 11: peripheral deasserts nAck to finish handshake */
4716 4715 if (wait_dsr(pp, ECPP_nACK, ECPP_nACK, 35000) < 0) {
4717 4716 ecpp_error(pp->dip,
4718 4717 "nibble_periph2host(%d): failed event 11 %x\n",
4719 4718 i + 1, DSR_READ(pp));
4720 4719 (void) ecpp_1284_termination(pp);
4721 4720 return (FAILURE);
4722 4721 }
4723 4722 }
4724 4723
4725 4724 /* extract data byte from two nibbles - optimized formula */
4726 4725 *byte = ((((n[1] & ~ECPP_nACK) << 1) | (~n[1] & ECPP_nBUSY)) & 0xf0) |
4727 4726 ((((n[0] & ~ECPP_nACK) >> 3) | ((~n[0] & ECPP_nBUSY) >> 4)) & 0x0f);
4728 4727
4729 4728 pp->ibytes[ECPP_NIBBLE_MODE]++;
4730 4729 return (SUCCESS);
4731 4730 }
4732 4731
4733 4732 /*
4734 4733 * process data transfers requested by the peripheral
4735 4734 */
4736 4735 static uint_t
4737 4736 ecpp_peripheral2host(struct ecppunit *pp)
4738 4737 {
4739 4738 if (!canputnext(pp->readq)) {
4740 4739 ecpp_error(pp->dip, "ecpp_peripheral2host: readq full\n");
4741 4740 return (SUCCESS);
4742 4741 }
4743 4742
4744 4743 switch (pp->backchannel) {
4745 4744 case ECPP_CENTRONICS:
4746 4745 /* no backchannel */
4747 4746 return (SUCCESS);
4748 4747
4749 4748 case ECPP_NIBBLE_MODE:
4750 4749 ASSERT(pp->current_mode == ECPP_NIBBLE_MODE);
4751 4750
4752 4751 /*
4753 4752 * Event 20: Host sets nAutoFd high to ack request
4754 4753 */
4755 4754 DCR_WRITE(pp, ECPP_nINIT);
4756 4755
4757 4756 /* Event 21: Periph sets PError low to ack host */
4758 4757 if (wait_dsr(pp, ECPP_PE, 0, 35000) < 0) {
4759 4758 ecpp_error(pp->dip,
4760 4759 "ecpp_periph2host: failed event 21 %x\n",
4761 4760 DSR_READ(pp));
4762 4761 (void) ecpp_1284_termination(pp);
4763 4762 return (FAILURE);
4764 4763 }
4765 4764
4766 4765 pp->current_phase = ECPP_PHASE_NIBT_AVAIL;
4767 4766
4768 4767 /* this routine will read the data in Nibble mode */
4769 4768 return (ecpp_idle_phase(pp));
4770 4769
4771 4770 case ECPP_ECP_MODE:
4772 4771 if ((pp->current_phase == ECPP_PHASE_ECP_FWD_IDLE) &&
4773 4772 (ecp_forward2reverse(pp) == FAILURE)) {
4774 4773 return (FAILURE);
4775 4774 }
4776 4775
4777 4776 return (ecp_peripheral2host(pp)); /* start the transfer */
4778 4777
4779 4778 case ECPP_DIAG_MODE: {
4780 4779 mblk_t *mp;
4781 4780 int i;
4782 4781
4783 4782 if (ECR_READ(pp) & ECPP_FIFO_EMPTY) {
4784 4783 ecpp_error(pp->dip, "ecpp_periph2host: fifo empty\n");
4785 4784 return (SUCCESS);
4786 4785 }
4787 4786
4788 4787 /* allocate the FIFO size */
4789 4788 if ((mp = allocb(ECPP_FIFO_SZ, BPRI_MED)) == NULL) {
4790 4789 ecpp_error(pp->dip,
4791 4790 "ecpp_periph2host: allocb FAILURE.\n");
4792 4791 return (FAILURE);
4793 4792 }
4794 4793
4795 4794 /*
4796 4795 * For the time being just read it byte by byte
4797 4796 */
4798 4797 i = ECPP_FIFO_SZ;
4799 4798 while (i-- && (!(ECR_READ(pp) & ECPP_FIFO_EMPTY))) {
4800 4799 *mp->b_wptr++ = TFIFO_READ(pp);
4801 4800 drv_usecwait(1); /* ECR is sometimes slow to update */
4802 4801 }
4803 4802
4804 4803 if (canputnext(pp->readq)) {
4805 4804 mutex_exit(&pp->umutex);
4806 4805 mp->b_datap->db_type = M_DATA;
4807 4806 ecpp_error(pp->dip,
4808 4807 "ecpp_periph2host: sending %d bytes\n",
4809 4808 mp->b_wptr - mp->b_rptr);
4810 4809 putnext(pp->readq, mp);
4811 4810 mutex_enter(&pp->umutex);
4812 4811 return (SUCCESS);
4813 4812 } else {
4814 4813 ecpp_error(pp->dip,
4815 4814 "ecpp_periph2host: !canputnext data lost\n");
4816 4815 freemsg(mp);
4817 4816 return (FAILURE);
4818 4817 }
4819 4818 }
4820 4819
4821 4820 default:
4822 4821 ecpp_error(pp->dip, "ecpp_peripheraltohost: illegal back");
4823 4822 return (FAILURE);
4824 4823 }
4825 4824 }
4826 4825
4827 4826 /*
4828 4827 * Negotiate from ECP Forward Idle to Reverse Idle Phase
4829 4828 *
4830 4829 * (manipulations with dcr/ecr are according to ECP Specification)
4831 4830 */
4832 4831 static int
4833 4832 ecp_forward2reverse(struct ecppunit *pp)
4834 4833 {
4835 4834 ASSERT(pp->current_mode == ECPP_ECP_MODE &&
4836 4835 pp->current_phase == ECPP_PHASE_ECP_FWD_IDLE);
4837 4836
4838 4837 /* place port into PS2 mode */
4839 4838 ECR_WRITE(pp, ECR_mode_001 | ECPP_INTR_SRV | ECPP_INTR_MASK);
4840 4839
4841 4840 /* set direction bit (DCR3-0 must be 0100 - National) */
4842 4841 DCR_WRITE(pp, ECPP_REV_DIR | ECPP_nINIT);
4843 4842
4844 4843 /* enable hardware assist */
4845 4844 ECR_WRITE(pp, ECR_mode_011 | ECPP_INTR_SRV | ECPP_INTR_MASK);
4846 4845
4847 4846 drv_usecwait(1); /* Tp(ecp) = 0.5us */
4848 4847
4849 4848 /* Event 39: host sets nInit low */
4850 4849 DCR_WRITE(pp, ECPP_REV_DIR);
4851 4850
4852 4851 /* Event 40: peripheral sets PError low */
4853 4852
4854 4853 pp->current_phase = ECPP_PHASE_ECP_REV_IDLE;
4855 4854
4856 4855 ecpp_error(pp->dip, "ecp_forward2reverse ok\n");
4857 4856
4858 4857 return (SUCCESS);
4859 4858 }
4860 4859
4861 4860 /*
4862 4861 * Negotiate from ECP Reverse Idle to Forward Idle Phase
4863 4862 *
4864 4863 * (manipulations with dcr/ecr are according to ECP Specification)
4865 4864 */
4866 4865 static int
4867 4866 ecp_reverse2forward(struct ecppunit *pp)
4868 4867 {
4869 4868 ASSERT(pp->current_mode == ECPP_ECP_MODE &&
4870 4869 pp->current_phase == ECPP_PHASE_ECP_REV_IDLE);
4871 4870
4872 4871 /* Event 47: host deasserts nInit */
4873 4872 DCR_WRITE(pp, ECPP_REV_DIR | ECPP_nINIT);
4874 4873
4875 4874 /*
4876 4875 * Event 48: peripheral deasserts nAck
4877 4876 * Event 49: peripheral asserts PError
4878 4877 */
4879 4878 if (wait_dsr(pp, ECPP_PE, ECPP_PE, 35000) < 0) {
4880 4879 ecpp_error(pp->dip,
4881 4880 "ecp_reverse2forward: failed event 49 %x\n", DSR_READ(pp));
4882 4881 (void) ecpp_1284_termination(pp);
4883 4882 return (FAILURE);
4884 4883 }
4885 4884
4886 4885 /* place port into PS2 mode */
4887 4886 ECR_WRITE(pp, ECR_mode_001 | ECPP_INTR_SRV | ECPP_INTR_MASK);
4888 4887
4889 4888 /* clear direction bit */
4890 4889 DCR_WRITE(pp, ECPP_nINIT);
4891 4890
4892 4891 /* reenable hardware assist */
4893 4892 ECR_WRITE(pp, ECR_mode_011 | ECPP_INTR_SRV | ECPP_INTR_MASK);
4894 4893
4895 4894 pp->current_phase = ECPP_PHASE_ECP_FWD_IDLE;
4896 4895
4897 4896 ecpp_error(pp->dip, "ecp_reverse2forward ok\n");
4898 4897
4899 4898 return (SUCCESS);
4900 4899 }
4901 4900
4902 4901 /*
4903 4902 * Default negotiation chooses the best mode supported by peripheral
4904 4903 * Note that backchannel mode may be different from forward mode
4905 4904 */
4906 4905 static void
4907 4906 ecpp_default_negotiation(struct ecppunit *pp)
4908 4907 {
4909 4908 if (!noecp && (ecpp_mode_negotiation(pp, ECPP_ECP_MODE) == SUCCESS)) {
4910 4909 /* 1284 compatible device */
4911 4910 pp->io_mode = (pp->fast_compat == TRUE) ? ECPP_DMA : ECPP_PIO;
4912 4911 return;
4913 4912 } else if (ecpp_mode_negotiation(pp, ECPP_NIBBLE_MODE) == SUCCESS) {
4914 4913 /* 1284 compatible device */
4915 4914 pp->io_mode = (pp->fast_compat == TRUE) ? ECPP_DMA : ECPP_PIO;
4916 4915 } else {
4917 4916 /* Centronics device */
4918 4917 pp->io_mode =
4919 4918 (pp->fast_centronics == TRUE) ? ECPP_DMA : ECPP_PIO;
4920 4919 }
4921 4920 ECPP_CONFIG_MODE(pp);
4922 4921 }
4923 4922
4924 4923 /*
4925 4924 * Negotiate to the mode indicated by newmode
4926 4925 */
4927 4926 static int
4928 4927 ecpp_mode_negotiation(struct ecppunit *pp, uchar_t newmode)
4929 4928 {
4930 4929 /* any other mode is impossible */
4931 4930 ASSERT(pp->current_mode == ECPP_CENTRONICS ||
4932 4931 pp->current_mode == ECPP_COMPAT_MODE ||
4933 4932 pp->current_mode == ECPP_NIBBLE_MODE ||
4934 4933 pp->current_mode == ECPP_ECP_MODE ||
4935 4934 pp->current_mode == ECPP_DIAG_MODE);
4936 4935
4937 4936 if (pp->current_mode == newmode) {
4938 4937 return (SUCCESS);
4939 4938 }
4940 4939
4941 4940 /* termination from ECP is only allowed from the Forward Idle Phase */
4942 4941 if ((pp->current_mode == ECPP_ECP_MODE) &&
4943 4942 (pp->current_phase != ECPP_PHASE_ECP_FWD_IDLE)) {
4944 4943 /* this may break into Centronics */
4945 4944 (void) ecp_reverse2forward(pp);
4946 4945 }
4947 4946
4948 4947 switch (newmode) {
4949 4948 case ECPP_CENTRONICS:
4950 4949 (void) ecpp_1284_termination(pp);
4951 4950
4952 4951 /* put superio into PIO mode */
4953 4952 ECR_WRITE(pp, ECR_mode_001 | ECPP_INTR_MASK | ECPP_INTR_SRV);
4954 4953
4955 4954 pp->current_mode = ECPP_CENTRONICS;
4956 4955 pp->backchannel = ECPP_CENTRONICS;
4957 4956 ECPP_CONFIG_MODE(pp);
4958 4957
4959 4958 pp->to_mode[pp->current_mode]++;
4960 4959 return (SUCCESS);
4961 4960
4962 4961 case ECPP_COMPAT_MODE:
4963 4962 /* ECPP_COMPAT_MODE should support Nibble as a backchannel */
4964 4963 if (pp->current_mode == ECPP_NIBBLE_MODE) {
4965 4964 if (ecpp_1284_termination(pp) == SUCCESS) {
4966 4965 pp->current_mode = ECPP_COMPAT_MODE;
4967 4966 pp->backchannel = ECPP_NIBBLE_MODE;
4968 4967 ECPP_CONFIG_MODE(pp);
4969 4968 pp->to_mode[pp->current_mode]++;
4970 4969 return (SUCCESS);
4971 4970 } else {
4972 4971 return (FAILURE);
4973 4972 }
4974 4973 }
4975 4974
4976 4975 if ((nibble_negotiation(pp) == SUCCESS) &&
4977 4976 (ecpp_1284_termination(pp) == SUCCESS)) {
4978 4977 pp->backchannel = ECPP_NIBBLE_MODE;
4979 4978 pp->current_mode = ECPP_COMPAT_MODE;
4980 4979 ECPP_CONFIG_MODE(pp);
4981 4980 pp->to_mode[pp->current_mode]++;
4982 4981 return (SUCCESS);
4983 4982 } else {
4984 4983 return (FAILURE);
4985 4984 }
4986 4985
4987 4986 case ECPP_NIBBLE_MODE:
4988 4987 if (nibble_negotiation(pp) == FAILURE) {
4989 4988 return (FAILURE);
4990 4989 }
4991 4990
4992 4991 pp->backchannel = ECPP_NIBBLE_MODE;
4993 4992 ECPP_CONFIG_MODE(pp);
4994 4993 pp->to_mode[pp->current_mode]++;
4995 4994
4996 4995 return (SUCCESS);
4997 4996
4998 4997 case ECPP_ECP_MODE:
4999 4998 if (pp->noecpregs)
5000 4999 return (FAILURE);
5001 5000 if (ecp_negotiation(pp) == FAILURE) {
5002 5001 return (FAILURE);
5003 5002 }
5004 5003
5005 5004 /*
5006 5005 * National says CTR[3:0] should be 0100b before moving to 011
5007 5006 */
5008 5007 DCR_WRITE(pp, ECPP_nINIT);
5009 5008
5010 5009 if (ecr_write(pp, ECR_mode_011 |
5011 5010 ECPP_INTR_MASK | ECPP_INTR_SRV) == FAILURE) {
5012 5011 ecpp_error(pp->dip, "mode_nego:ECP: failed w/ecr\n");
5013 5012 return (FAILURE);
5014 5013 }
5015 5014
5016 5015 ECPP_CONFIG_MODE(pp);
5017 5016 pp->to_mode[pp->current_mode]++;
5018 5017
5019 5018 return (SUCCESS);
5020 5019
5021 5020 case ECPP_DIAG_MODE:
5022 5021 /*
5023 5022 * In DIAG mode application can do nasty things(e.g drive pins)
5024 5023 * To keep peripheral sane, terminate to Compatibility mode
5025 5024 */
5026 5025 (void) ecpp_1284_termination(pp);
5027 5026
5028 5027 /* put superio into TFIFO mode */
5029 5028 if (ecr_write(pp, ECR_mode_001 |
5030 5029 ECPP_INTR_MASK | ECPP_INTR_SRV) == FAILURE) {
5031 5030 ecpp_error(pp->dip, "put to TFIFO: failed w/ecr\n");
5032 5031 return (FAILURE);
5033 5032 }
5034 5033
5035 5034 pp->current_mode = ECPP_DIAG_MODE;
5036 5035 pp->backchannel = ECPP_DIAG_MODE;
5037 5036 ECPP_CONFIG_MODE(pp);
5038 5037 pp->to_mode[pp->current_mode]++;
5039 5038
5040 5039 return (SUCCESS);
5041 5040
5042 5041 default:
5043 5042 ecpp_error(pp->dip,
5044 5043 "ecpp_mode_negotiation: mode %d not supported\n", newmode);
5045 5044 return (FAILURE);
5046 5045 }
5047 5046 }
5048 5047
5049 5048 /*
5050 5049 * Standard (9.1): Peripheral data is available only when the host places
5051 5050 * the interface in a mode capable of peripheral-to-host data transfer.
5052 5051 * This requires the host periodically to place the interface in such a mode.
5053 5052 * Polling can be eliminated by leaving the interface in an 1284 idle phase.
5054 5053 */
5055 5054 static uchar_t
5056 5055 ecpp_idle_phase(struct ecppunit *pp)
5057 5056 {
5058 5057 uchar_t rval = FAILURE;
5059 5058
5060 5059 /*
5061 5060 * If there is no space on the read queue, do not reverse channel
5062 5061 */
5063 5062 if (!canputnext(pp->readq)) {
5064 5063 ecpp_error(pp->dip, "ecpp_idle_phase: readq full\n");
5065 5064 return (SUCCESS);
5066 5065 }
5067 5066
5068 5067 switch (pp->backchannel) {
5069 5068 case ECPP_CENTRONICS:
5070 5069 case ECPP_COMPAT_MODE:
5071 5070 case ECPP_DIAG_MODE:
5072 5071 /* nothing */
5073 5072 ecpp_error(pp->dip, "ecpp_idle_phase: compat idle\n");
5074 5073 return (SUCCESS);
5075 5074
5076 5075 case ECPP_NIBBLE_MODE:
5077 5076 /*
5078 5077 * read as much data as possible, ending up in either
5079 5078 * Reverse Idle or Host Busy Data Available phase
5080 5079 */
5081 5080 ecpp_error(pp->dip, "ecpp_idle_phase: nibble backchannel\n");
5082 5081 if ((pp->current_mode != ECPP_NIBBLE_MODE) &&
5083 5082 (ecpp_mode_negotiation(pp, ECPP_NIBBLE_MODE) == FAILURE)) {
5084 5083 break;
5085 5084 }
5086 5085
5087 5086 rval = read_nibble_backchan(pp);
5088 5087
5089 5088 /* put interface into Reverse Idle phase */
5090 5089 if (pp->current_phase == ECPP_PHASE_NIBT_NAVAIL &&
5091 5090 canputnext(pp->readq)) {
5092 5091 ecpp_error(pp->dip, "ecpp_idle_phase: going revidle\n");
5093 5092
5094 5093 /*
5095 5094 * Event 7: host asserts nAutoFd
5096 5095 * enable nAck interrupt to get a backchannel request
5097 5096 */
5098 5097 DCR_WRITE(pp, ECPP_nINIT | ECPP_AFX | ECPP_INTR_EN);
5099 5098
5100 5099 ECPP_UNMASK_INTR(pp);
5101 5100 }
5102 5101
5103 5102 break;
5104 5103
5105 5104 case ECPP_ECP_MODE:
5106 5105 /*
5107 5106 * if data is already available, request the backchannel xfer
5108 5107 * otherwise stay in Forward Idle and enable nErr interrupts
5109 5108 */
5110 5109 ecpp_error(pp->dip, "ecpp_idle_phase: ECP forward\n");
5111 5110
5112 5111 ASSERT(pp->current_phase == ECPP_PHASE_ECP_FWD_IDLE ||
5113 5112 pp->current_phase == ECPP_PHASE_ECP_REV_IDLE);
5114 5113
5115 5114 /* put interface into Forward Idle phase */
5116 5115 if ((pp->current_phase == ECPP_PHASE_ECP_REV_IDLE) &&
5117 5116 (ecp_reverse2forward(pp) == FAILURE)) {
5118 5117 return (FAILURE);
5119 5118 }
5120 5119
5121 5120 /*
5122 5121 * if data already available, put backchannel request on the wq
5123 5122 * otherwise enable nErr interrupts
5124 5123 */
5125 5124 if ((DSR_READ(pp) & ECPP_nERR) == 0) {
5126 5125 (void) ecpp_backchan_req(pp);
5127 5126 } else {
5128 5127 ECR_WRITE(pp,
5129 5128 ECR_READ(pp) & ~ECPP_INTR_MASK | ECPP_INTR_SRV);
5130 5129
5131 5130 ECPP_UNMASK_INTR(pp);
5132 5131 }
5133 5132
5134 5133 return (SUCCESS);
5135 5134
5136 5135 default:
5137 5136 ecpp_error(pp->dip, "ecpp_idle_phase: illegal backchannel");
5138 5137 }
5139 5138
5140 5139 return (rval);
5141 5140 }
5142 5141
5143 5142 /*
5144 5143 * This routine will leave the port in ECPP_PHASE_NIBT_REVIDLE
5145 5144 * Due to flow control, though, it may stop at ECPP_PHASE_NIBT_AVAIL,
5146 5145 * and continue later as the user consumes data from the read queue
5147 5146 *
5148 5147 * The current phase should be NIBT_AVAIL or NIBT_NAVAIL
5149 5148 * If some events fail during transfer, termination puts link
5150 5149 * to Compatibility mode and FAILURE is returned
5151 5150 */
5152 5151 static int
5153 5152 read_nibble_backchan(struct ecppunit *pp)
5154 5153 {
5155 5154 mblk_t *mp;
5156 5155 int i;
5157 5156 int rval = SUCCESS;
5158 5157
5159 5158 ASSERT(pp->current_mode == ECPP_NIBBLE_MODE);
5160 5159
5161 5160 pp->current_phase = (DSR_READ(pp) & (ECPP_nERR | ECPP_PE))
5162 5161 ? ECPP_PHASE_NIBT_NAVAIL : ECPP_PHASE_NIBT_AVAIL;
5163 5162
5164 5163 ecpp_error(pp->dip, "read_nibble_backchan: %x\n", DSR_READ(pp));
5165 5164
5166 5165 /*
5167 5166 * While data is available, read it in NIBBLE_REV_BLKSZ byte chunks
5168 5167 * and send up the stream
5169 5168 */
5170 5169 while (pp->current_phase == ECPP_PHASE_NIBT_AVAIL && rval == SUCCESS) {
5171 5170 /* see if there's space on the queue */
5172 5171 if (!canputnext(pp->readq)) {
5173 5172 ecpp_error(pp->dip,
5174 5173 "read_nibble_backchan: canputnext failed\n");
5175 5174 return (SUCCESS);
5176 5175 }
5177 5176
5178 5177 if ((mp = allocb(NIBBLE_REV_BLKSZ, BPRI_MED)) == NULL) {
5179 5178 ecpp_error(pp->dip,
5180 5179 "read_nibble_backchan: allocb failed\n");
5181 5180 return (SUCCESS);
5182 5181 }
5183 5182
5184 5183 /* read a chunk of data from the peripheral byte by byte */
5185 5184 i = NIBBLE_REV_BLKSZ;
5186 5185 while (i-- && !(DSR_READ(pp) & ECPP_nERR)) {
5187 5186 if (nibble_peripheral2host(pp, mp->b_wptr) != SUCCESS) {
5188 5187 rval = FAILURE;
5189 5188 break;
5190 5189 }
5191 5190 mp->b_wptr++;
5192 5191 }
5193 5192
5194 5193 pp->current_phase = (DSR_READ(pp) & (ECPP_nERR | ECPP_PE))
5195 5194 ? ECPP_PHASE_NIBT_NAVAIL
5196 5195 : ECPP_PHASE_NIBT_AVAIL;
5197 5196
5198 5197 if (mp->b_wptr - mp->b_rptr > 0) {
5199 5198 ecpp_error(pp->dip,
5200 5199 "read_nibble_backchan: sending %d bytes\n",
5201 5200 mp->b_wptr - mp->b_rptr);
5202 5201 pp->nread = 0;
5203 5202 mutex_exit(&pp->umutex);
5204 5203 putnext(pp->readq, mp);
5205 5204 mutex_enter(&pp->umutex);
5206 5205 } else {
5207 5206 freemsg(mp);
5208 5207 }
5209 5208 }
5210 5209
5211 5210 return (rval);
5212 5211 }
5213 5212
5214 5213 /*
5215 5214 * 'Request Device ID using nibble mode' negotiation
5216 5215 */
5217 5216 static int
5218 5217 devidnib_negotiation(struct ecppunit *pp)
5219 5218 {
5220 5219 uint8_t dsr;
5221 5220
5222 5221 if (ecpp_1284_negotiation(pp,
5223 5222 ECPP_XREQ_NIBBLE | ECPP_XREQ_ID, &dsr) == FAILURE) {
5224 5223 return (FAILURE);
5225 5224 }
5226 5225
5227 5226 /*
5228 5227 * If peripheral has data available, PE and nErr will
5229 5228 * be set low at Event 5 & 6.
5230 5229 */
5231 5230 if ((dsr & (ECPP_PE | ECPP_nERR)) == 0) {
5232 5231 pp->current_phase = ECPP_PHASE_NIBT_AVAIL;
5233 5232 } else {
5234 5233 pp->current_phase = ECPP_PHASE_NIBT_NAVAIL;
5235 5234 }
5236 5235
5237 5236 ecpp_error(pp->dip, "ecpp_devidnib_nego: current_phase=%x\n",
5238 5237 pp->current_phase);
5239 5238
5240 5239 /* successful negotiation into Nibble mode */
5241 5240 pp->current_mode = ECPP_NIBBLE_MODE;
5242 5241 pp->backchannel = ECPP_NIBBLE_MODE;
5243 5242
5244 5243 ecpp_error(pp->dip, "ecpp_devidnib_nego: ok\n");
5245 5244
5246 5245 return (SUCCESS);
5247 5246 }
5248 5247
5249 5248 /*
5250 5249 * Read 1284 device ID sequence
5251 5250 *
5252 5251 * This function should be called two times:
5253 5252 * 1) ecpp_getdevid(pp, NULL, &len) - to retrieve ID length;
5254 5253 * 2) ecpp_getdevid(pp, buffer, &len) - to read len bytes into buffer
5255 5254 *
5256 5255 * After 2) port is in Compatible mode
5257 5256 * If the caller fails to make second call, it must reset port to Centronics
5258 5257 *
5259 5258 */
5260 5259 static int
5261 5260 ecpp_getdevid(struct ecppunit *pp, uint8_t *id, int *lenp, int mode)
5262 5261 {
5263 5262 uint8_t lenhi, lenlo;
5264 5263 uint8_t dsr;
5265 5264 int i;
5266 5265
5267 5266 switch (mode) {
5268 5267 case ECPP_NIBBLE_MODE:
5269 5268 /* negotiate only if neccessary */
5270 5269 if ((pp->current_mode != mode) || (id == NULL)) {
5271 5270 if (devidnib_negotiation(pp) == FAILURE) {
5272 5271 return (EIO);
5273 5272 }
5274 5273 }
5275 5274
5276 5275 if (pp->current_phase != ECPP_PHASE_NIBT_AVAIL) {
5277 5276 return (EIO);
5278 5277 }
5279 5278
5280 5279 /*
5281 5280 * Event 14: Host tristates data bus, peripheral
5282 5281 * asserts nERR if data available, usually the
5283 5282 * status bits (7-0) and requires two reads since
5284 5283 * only nibbles are transfered.
5285 5284 */
5286 5285 dsr = DSR_READ(pp);
5287 5286
5288 5287 if (id == NULL) {
5289 5288 /*
5290 5289 * first two bytes are the length of the sequence
5291 5290 * (incl. these bytes)
5292 5291 * first byte is MSB
5293 5292 */
5294 5293 if ((dsr & ECPP_nERR) ||
5295 5294 (nibble_peripheral2host(pp, &lenhi) == FAILURE) ||
5296 5295 (dsr & ECPP_nERR) ||
5297 5296 (nibble_peripheral2host(pp, &lenlo) == FAILURE)) {
5298 5297 ecpp_error(pp->dip,
5299 5298 "ecpp_getdevid: id length read error\n");
5300 5299 return (EIO);
5301 5300 }
5302 5301
5303 5302 *lenp = (lenhi << 8) | (lenlo);
5304 5303
5305 5304 ecpp_error(pp->dip,
5306 5305 "ecpp_getdevid: id length = %d\n", *lenp);
5307 5306
5308 5307 if (*lenp < 2) {
5309 5308 return (EIO);
5310 5309 }
5311 5310 } else {
5312 5311 /*
5313 5312 * read the rest of the data
5314 5313 */
5315 5314 i = *lenp;
5316 5315 while (i && ((dsr & ECPP_nERR) == 0)) {
5317 5316 if (nibble_peripheral2host(pp, id++) == FAILURE)
5318 5317 break;
5319 5318
5320 5319 i--;
5321 5320 dsr = DSR_READ(pp);
5322 5321 }
5323 5322 ecpp_error(pp->dip,
5324 5323 "ecpp_getdevid: read %d bytes\n", *lenp - i);
5325 5324
5326 5325 /*
5327 5326 * 1284: After receiving the sequence, the host is
5328 5327 * required to return the link to the Compatibility mode
5329 5328 */
5330 5329 (void) ecpp_1284_termination(pp);
5331 5330 }
5332 5331
5333 5332 break;
5334 5333
5335 5334 /* Other modes are not yet supported */
5336 5335 default:
5337 5336 return (EINVAL);
5338 5337 }
5339 5338
5340 5339 return (0);
5341 5340 }
5342 5341
5343 5342 /*
5344 5343 * Various hardware support
5345 5344 *
5346 5345 * First define some stubs for functions that do nothing
5347 5346 */
5348 5347
5349 5348 /*ARGSUSED*/
5350 5349 static void
5351 5350 empty_config_mode(struct ecppunit *pp)
5352 5351 {
5353 5352 }
5354 5353
5355 5354 /*ARGSUSED*/
5356 5355 static void
5357 5356 empty_mask_intr(struct ecppunit *pp)
5358 5357 {
5359 5358 }
5360 5359
5361 5360 #if defined(__x86)
5362 5361 static size_t
5363 5362 x86_getcnt(struct ecppunit *pp)
5364 5363 {
5365 5364 int count;
5366 5365
5367 5366 (void) ddi_dmae_getcnt(pp->dip, pp->uh.x86.chn, &count);
5368 5367 return (count);
5369 5368 }
5370 5369 #endif
5371 5370
5372 5371 /*
5373 5372 *
5374 5373 * National PC87332 and PC97317 SuperIOs support routines
5375 5374 * These chips are used in PCI-based Darwin, Quark, Quasar, Excalibur
5376 5375 * and use EBus DMA facilities (Cheerio or RIO)
5377 5376 *
5378 5377 */
5379 5378
5380 5379 static int
5381 5380 pc87332_map_regs(struct ecppunit *pp)
5382 5381 {
5383 5382 if (ddi_regs_map_setup(pp->dip, 1, (caddr_t *)&pp->uh.ebus.c_reg, 0,
5384 5383 sizeof (struct config_reg), &acc_attr,
5385 5384 &pp->uh.ebus.c_handle) != DDI_SUCCESS) {
5386 5385 ecpp_error(pp->dip, "pc87332_map_regs: failed c_reg\n");
5387 5386 goto fail;
5388 5387 }
5389 5388
5390 5389 if (ddi_regs_map_setup(pp->dip, 0, (caddr_t *)&pp->i_reg, 0,
5391 5390 sizeof (struct info_reg), &acc_attr, &pp->i_handle)
5392 5391 != DDI_SUCCESS) {
5393 5392 ecpp_error(pp->dip, "pc87332_map_regs: failed i_reg\n");
5394 5393 goto fail;
5395 5394 }
5396 5395
5397 5396 if (ddi_regs_map_setup(pp->dip, 0, (caddr_t *)&pp->f_reg, 0x400,
5398 5397 sizeof (struct fifo_reg), &acc_attr, &pp->f_handle)
5399 5398 != DDI_SUCCESS) {
5400 5399 ecpp_error(pp->dip, "pc87332_map_regs: failed f_reg\n");
5401 5400 goto fail;
5402 5401 }
5403 5402
5404 5403 if (ddi_regs_map_setup(pp->dip, 2, (caddr_t *)&pp->uh.ebus.dmac, 0,
5405 5404 sizeof (struct cheerio_dma_reg), &acc_attr,
5406 5405 &pp->uh.ebus.d_handle) != DDI_SUCCESS) {
5407 5406 ecpp_error(pp->dip, "pc87332_map_regs: failed dmac\n");
5408 5407 goto fail;
5409 5408 }
5410 5409
5411 5410 return (SUCCESS);
5412 5411
5413 5412 fail:
5414 5413 pc87332_unmap_regs(pp);
5415 5414 return (FAILURE);
5416 5415 }
5417 5416
5418 5417 static void
5419 5418 pc87332_unmap_regs(struct ecppunit *pp)
5420 5419 {
5421 5420 if (pp->uh.ebus.c_handle) {
5422 5421 ddi_regs_map_free(&pp->uh.ebus.c_handle);
5423 5422 }
5424 5423 if (pp->uh.ebus.d_handle) {
5425 5424 ddi_regs_map_free(&pp->uh.ebus.d_handle);
5426 5425 }
5427 5426 if (pp->i_handle) {
5428 5427 ddi_regs_map_free(&pp->i_handle);
5429 5428 }
5430 5429 if (pp->f_handle) {
5431 5430 ddi_regs_map_free(&pp->f_handle);
5432 5431 }
5433 5432 }
5434 5433
5435 5434 static uint8_t
5436 5435 pc87332_read_config_reg(struct ecppunit *pp, uint8_t reg_num)
5437 5436 {
5438 5437 uint8_t retval;
5439 5438
5440 5439 PP_PUTB(pp->uh.ebus.c_handle, &pp->uh.ebus.c_reg->index, reg_num);
5441 5440 retval = PP_GETB(pp->uh.ebus.c_handle, &pp->uh.ebus.c_reg->data);
5442 5441
5443 5442 return (retval);
5444 5443 }
5445 5444
5446 5445 static void
5447 5446 pc87332_write_config_reg(struct ecppunit *pp, uint8_t reg_num, uint8_t val)
5448 5447 {
5449 5448 PP_PUTB(pp->uh.ebus.c_handle, &pp->uh.ebus.c_reg->index, reg_num);
5450 5449 PP_PUTB(pp->uh.ebus.c_handle, &pp->uh.ebus.c_reg->data, val);
5451 5450
5452 5451 /*
5453 5452 * second write to this register is needed. the register behaves as
5454 5453 * a fifo. the first value written goes to the data register. the
5455 5454 * second write pushes the initial value to the register indexed.
5456 5455 */
5457 5456
5458 5457 PP_PUTB(pp->uh.ebus.c_handle, &pp->uh.ebus.c_reg->data, val);
5459 5458 }
5460 5459
5461 5460 static int
5462 5461 pc87332_config_chip(struct ecppunit *pp)
5463 5462 {
5464 5463 uint8_t pmc, fcr;
5465 5464
5466 5465 pp->current_phase = ECPP_PHASE_INIT;
5467 5466
5468 5467 /* ECP DMA configuration bit (PMC4) must be set */
5469 5468 pmc = pc87332_read_config_reg(pp, PMC);
5470 5469 if (!(pmc & PC87332_PMC_ECP_DMA_CONFIG)) {
5471 5470 pc87332_write_config_reg(pp, PMC,
5472 5471 pmc | PC87332_PMC_ECP_DMA_CONFIG);
5473 5472 }
5474 5473
5475 5474 /*
5476 5475 * The Parallel Port Multiplexor pins must be driven.
5477 5476 * Check to see if FCR3 is zero, if not clear FCR3.
5478 5477 */
5479 5478 fcr = pc87332_read_config_reg(pp, FCR);
5480 5479 if (fcr & PC87332_FCR_PPM_FLOAT_CTL) {
5481 5480 pc87332_write_config_reg(pp, FCR,
5482 5481 fcr & ~PC87332_FCR_PPM_FLOAT_CTL);
5483 5482 }
5484 5483
5485 5484 /*
5486 5485 * clear bits 3-0 in CTR (aka DCR) prior to enabling ECP mode
5487 5486 * CTR5 can not be cleared in SPP mode, CTR5 will return 1.
5488 5487 * "FAILURE" in this case is ok. Better to use dcr_write()
5489 5488 * to ensure reliable writing to DCR.
5490 5489 */
5491 5490 if (dcr_write(pp, ECPP_DCR_SET | ECPP_nINIT) == FAILURE) {
5492 5491 ecpp_error(pp->dip, "ecpp_config_87332: DCR config\n");
5493 5492 }
5494 5493
5495 5494 /* enable ECP mode, level intr (note that DCR bits 3-0 == 0x0) */
5496 5495 pc87332_write_config_reg(pp, PCR,
5497 5496 PC87332_PCR_INTR_LEVL | PC87332_PCR_ECP_EN);
5498 5497
5499 5498 /* put SuperIO in initial state */
5500 5499 if (ecr_write(pp, ECR_mode_001 |
5501 5500 ECPP_INTR_MASK | ECPP_INTR_SRV) == FAILURE) {
5502 5501 ecpp_error(pp->dip, "ecpp_config_87332: ECR\n");
5503 5502 }
5504 5503
5505 5504 if (dcr_write(pp, ECPP_DCR_SET | ECPP_SLCTIN | ECPP_nINIT) == FAILURE) {
5506 5505 ecpp_error(pp->dip, "ecpp_config_87332: w/DCR failed2.\n");
5507 5506 return (FAILURE);
5508 5507
5509 5508 }
5510 5509 /* we are in centronic mode */
5511 5510 pp->current_mode = ECPP_CENTRONICS;
5512 5511
5513 5512 /* in compatible mode with no data transfer in progress */
5514 5513 pp->current_phase = ECPP_PHASE_C_IDLE;
5515 5514
5516 5515 return (SUCCESS);
5517 5516 }
5518 5517
5519 5518 /*
5520 5519 * A new mode was set, do some mode specific reconfiguration
5521 5520 * in this case - set interrupt characteristic
5522 5521 */
5523 5522 static void
5524 5523 pc87332_config_mode(struct ecppunit *pp)
5525 5524 {
5526 5525 if (COMPAT_PIO(pp)) {
5527 5526 pc87332_write_config_reg(pp, PCR, 0x04);
5528 5527 } else {
5529 5528 pc87332_write_config_reg(pp, PCR, 0x14);
5530 5529 }
5531 5530 }
5532 5531
5533 5532 static int
5534 5533 pc97317_map_regs(struct ecppunit *pp)
5535 5534 {
5536 5535 if (pc87332_map_regs(pp) != SUCCESS) {
5537 5536 return (FAILURE);
5538 5537 }
5539 5538
5540 5539 if (ddi_regs_map_setup(pp->dip, 0, (caddr_t *)&pp->uh.ebus.c2_reg,
5541 5540 0x403, sizeof (struct config2_reg), &acc_attr,
5542 5541 &pp->uh.ebus.c2_handle) != DDI_SUCCESS) {
5543 5542 ecpp_error(pp->dip, "pc97317_map_regs: failed c2_reg\n");
5544 5543 pc87332_unmap_regs(pp);
5545 5544 return (FAILURE);
5546 5545 } else {
5547 5546 return (SUCCESS);
5548 5547 }
5549 5548 }
5550 5549
5551 5550 static void
5552 5551 pc97317_unmap_regs(struct ecppunit *pp)
5553 5552 {
5554 5553 if (pp->uh.ebus.c2_handle) {
5555 5554 ddi_regs_map_free(&pp->uh.ebus.c2_handle);
5556 5555 }
5557 5556
5558 5557 pc87332_unmap_regs(pp);
5559 5558 }
5560 5559
5561 5560 /*
5562 5561 * OBP should configure the PC97317 such that it does not need further
5563 5562 * configuration. Upon sustaining, it may be necessary to examine
5564 5563 * or change the configuration registers. This routine is left in
5565 5564 * the file for that purpose.
5566 5565 */
5567 5566 static int
5568 5567 pc97317_config_chip(struct ecppunit *pp)
5569 5568 {
5570 5569 uint8_t conreg;
5571 5570
5572 5571 /* set the logical device name */
5573 5572 pc87332_write_config_reg(pp, PC97317_CONFIG_DEV_NO, 0x4);
5574 5573
5575 5574 /* SPP Compatibility */
5576 5575 PP_PUTB(pp->uh.ebus.c2_handle,
5577 5576 &pp->uh.ebus.c2_reg->eir, PC97317_CONFIG2_CONTROL2);
5578 5577 PP_PUTB(pp->uh.ebus.c2_handle, &pp->uh.ebus.c2_reg->edr, 0x80);
5579 5578
5580 5579 /* low interrupt polarity */
5581 5580 pc87332_write_config_reg(pp, PC97317_CONFIG_INTR_TYPE, 0x00);
5582 5581
5583 5582 /* ECP mode */
5584 5583 pc87332_write_config_reg(pp, PC97317_CONFIG_PP_CONFIG, 0xf2);
5585 5584
5586 5585 if (dcr_write(pp, ECPP_SLCTIN | ECPP_nINIT) == FAILURE) {
5587 5586 ecpp_error(pp->dip, "pc97317_config_chip: failed w/DCR\n");
5588 5587 }
5589 5588
5590 5589 if (ecr_write(pp, ECR_mode_001 |
5591 5590 ECPP_INTR_MASK | ECPP_INTR_SRV) == FAILURE) {
5592 5591 ecpp_error(pp->dip, "pc97317_config_chip: failed w/ECR\n");
5593 5592 }
5594 5593
5595 5594 #ifdef DEBUG
5596 5595 conreg = pc87332_read_config_reg(pp, PC97317_CONFIG_DEV_NO);
5597 5596 ecpp_error(pp->dip, "97317:conreg7(logical dev)=%x\n", conreg);
5598 5597
5599 5598 conreg = pc87332_read_config_reg(pp, PC97317_CONFIG_BASE_ADDR_MSB);
5600 5599 ecpp_error(pp->dip, "97317:conreg60(addrHi)=%x\n", conreg);
5601 5600
5602 5601 conreg = pc87332_read_config_reg(pp, PC97317_CONFIG_BASE_ADDR_LSB);
5603 5602 ecpp_error(pp->dip, "97317:conreg61(addrLo)=%x\n", conreg);
5604 5603
5605 5604 conreg = pc87332_read_config_reg(pp, PC97317_CONFIG_INTR_SEL);
5606 5605 ecpp_error(pp->dip, "97317:conreg70(IRQL)=%x\n", conreg);
5607 5606
5608 5607 conreg = pc87332_read_config_reg(pp, PC97317_CONFIG_INTR_TYPE);
5609 5608 ecpp_error(pp->dip, "97317:conreg71(intr type)=%x\n", conreg);
5610 5609
5611 5610 conreg = pc87332_read_config_reg(pp, PC97317_CONFIG_ACTIVATE);
5612 5611 ecpp_error(pp->dip, "97317:conreg30(Active)=%x\n", conreg);
5613 5612
5614 5613 conreg = pc87332_read_config_reg(pp, PC97317_CONFIG_IO_RANGE);
5615 5614 ecpp_error(pp->dip, "97317:conreg31(IO Range Check)=%x\n", conreg);
5616 5615
5617 5616 conreg = pc87332_read_config_reg(pp, PC97317_CONFIG_DMA0_CHAN);
5618 5617 ecpp_error(pp->dip, "97317:conreg74(DMA0 Chan)=%x\n", conreg);
5619 5618 conreg = pc87332_read_config_reg(pp, PC97317_CONFIG_DMA1_CHAN);
5620 5619 ecpp_error(pp->dip, "97317:conreg75(DMA1 Chan)=%x\n", conreg);
5621 5620
5622 5621 conreg = pc87332_read_config_reg(pp, PC97317_CONFIG_PP_CONFIG);
5623 5622 ecpp_error(pp->dip, "97317:conregFO(pport conf)=%x\n", conreg);
5624 5623
5625 5624 conreg = pc87332_read_config_reg(pp, PC97317_CONFIG_PP_CONFIG);
5626 5625 ecpp_error(pp->dip, "97317:conregFO(pport conf)=%x\n", conreg);
5627 5626 #endif /* DEBUG */
5628 5627
5629 5628 return (SUCCESS);
5630 5629 }
5631 5630
5632 5631 /*
5633 5632 * A new mode was set, do some mode specific reconfiguration
5634 5633 * in this case - set interrupt polarity
5635 5634 */
5636 5635 static void
5637 5636 pc97317_config_mode(struct ecppunit *pp)
5638 5637 {
5639 5638 /* set the logical device name */
5640 5639 pc87332_write_config_reg(pp, PC97317_CONFIG_DEV_NO, 0x4);
5641 5640
5642 5641 if (COMPAT_PIO(pp) || pp->current_mode == ECPP_NIBBLE_MODE) {
5643 5642 pc87332_write_config_reg(pp, PC97317_CONFIG_INTR_TYPE, 0x02);
5644 5643 } else {
5645 5644 pc87332_write_config_reg(pp, PC97317_CONFIG_INTR_TYPE, 0x00);
5646 5645 }
5647 5646 }
5648 5647
5649 5648 static void
5650 5649 cheerio_mask_intr(struct ecppunit *pp)
5651 5650 {
5652 5651 /* mask Cheerio interrupts */
5653 5652 AND_SET_LONG_R(pp->uh.ebus.d_handle,
5654 5653 &pp->uh.ebus.dmac->csr, ~DCSR_INT_EN);
5655 5654 }
5656 5655
5657 5656 static void
5658 5657 cheerio_unmask_intr(struct ecppunit *pp)
5659 5658 {
5660 5659 /* unmask Cheerio interrupts */
5661 5660 OR_SET_LONG_R(pp->uh.ebus.d_handle,
5662 5661 &pp->uh.ebus.dmac->csr, DCSR_INT_EN | DCSR_TCI_DIS);
5663 5662 }
5664 5663
5665 5664 static int
5666 5665 cheerio_dma_start(struct ecppunit *pp)
5667 5666 {
5668 5667 cheerio_reset_dcsr(pp);
5669 5668 SET_DMAC_BCR(pp, pp->dma_cookie.dmac_size);
5670 5669 SET_DMAC_ACR(pp, pp->dma_cookie.dmac_address);
5671 5670
5672 5671 if (pp->dma_dir == DDI_DMA_READ) {
5673 5672 SET_DMAC_CSR(pp, DCSR_INT_EN | DCSR_EN_CNT | DCSR_EN_DMA |
5674 5673 DCSR_CSR_DRAIN | DCSR_BURST_1 | DCSR_BURST_0 | DCSR_WRITE);
5675 5674 } else {
5676 5675 SET_DMAC_CSR(pp, DCSR_INT_EN | DCSR_EN_CNT | DCSR_EN_DMA |
5677 5676 DCSR_CSR_DRAIN | DCSR_BURST_1 | DCSR_BURST_0);
5678 5677 }
5679 5678
5680 5679 return (SUCCESS);
5681 5680 }
5682 5681
5683 5682 /*
5684 5683 * Note: BCR is reset to 0, so counter should always be read before dma_stop
5685 5684 */
5686 5685 static int
5687 5686 cheerio_dma_stop(struct ecppunit *pp, size_t *countp)
5688 5687 {
5689 5688 uint8_t ecr;
5690 5689
5691 5690 /* disable DMA and byte counter */
5692 5691 AND_SET_LONG_R(pp->uh.ebus.d_handle, &pp->uh.ebus.dmac->csr,
5693 5692 ~(DCSR_EN_DMA | DCSR_EN_CNT| DCSR_INT_EN));
5694 5693
5695 5694 /* ACK and disable the TC interrupt */
5696 5695 OR_SET_LONG_R(pp->uh.ebus.d_handle, &pp->uh.ebus.dmac->csr,
5697 5696 DCSR_TC | DCSR_TCI_DIS);
5698 5697
5699 5698 /* read DMA count if requested */
5700 5699 if (countp) {
5701 5700 *countp = cheerio_getcnt(pp);
5702 5701 }
5703 5702
5704 5703 cheerio_reset_dcsr(pp);
5705 5704 SET_DMAC_BCR(pp, 0);
5706 5705
5707 5706 /* turn off SuperIO's DMA */
5708 5707 ecr = ECR_READ(pp);
5709 5708 if (ecr_write(pp, ecr & ~ECPP_DMA_ENABLE) == FAILURE) {
5710 5709 return (FAILURE);
5711 5710 }
5712 5711
5713 5712 /* Disable SuperIO interrupts and DMA */
5714 5713 ecr = ECR_READ(pp);
5715 5714
5716 5715 return (ecr_write(pp, ecr | ECPP_INTR_SRV));
5717 5716 }
5718 5717
5719 5718 static size_t
5720 5719 cheerio_getcnt(struct ecppunit *pp)
5721 5720 {
5722 5721 return (GET_DMAC_BCR(pp));
5723 5722 }
5724 5723
5725 5724 /*
5726 5725 * Reset the DCSR by first setting the RESET bit to 1. Poll the
5727 5726 * DCSR_CYC_PEND bit to make sure there are no more pending DMA cycles.
5728 5727 * If there are no more pending cycles, clear the RESET bit.
5729 5728 */
5730 5729 static void
5731 5730 cheerio_reset_dcsr(struct ecppunit *pp)
5732 5731 {
5733 5732 int timeout = DMAC_RESET_TIMEOUT;
5734 5733
5735 5734 SET_DMAC_CSR(pp, DCSR_RESET);
5736 5735
5737 5736 while (GET_DMAC_CSR(pp) & DCSR_CYC_PEND) {
5738 5737 if (timeout == 0) {
5739 5738 ecpp_error(pp->dip, "cheerio_reset_dcsr: timeout\n");
5740 5739 break;
5741 5740 } else {
5742 5741 drv_usecwait(1);
5743 5742 timeout--;
5744 5743 }
5745 5744 }
5746 5745
5747 5746 SET_DMAC_CSR(pp, 0);
5748 5747 }
5749 5748
5750 5749 /*
5751 5750 *
5752 5751 * Grover Southbridge (M1553) support routines
5753 5752 * Southbridge contains an Intel 8237 DMAC onboard which is used
5754 5753 * to transport data to/from PCI space to superio parallel port
5755 5754 *
5756 5755 */
5757 5756
5758 5757
5759 5758 static int
5760 5759 m1553_map_regs(struct ecppunit *pp)
5761 5760 {
5762 5761 if (ddi_regs_map_setup(pp->dip, 1, (caddr_t *)&pp->uh.m1553.isa_space,
5763 5762 0, sizeof (struct isaspace), &acc_attr,
5764 5763 &pp->uh.m1553.d_handle) != DDI_SUCCESS) {
5765 5764 ecpp_error(pp->dip, "m1553_map_regs: failed isa space\n");
5766 5765 goto fail;
5767 5766 }
5768 5767
5769 5768 if (ddi_regs_map_setup(pp->dip, 0, (caddr_t *)&pp->i_reg, 0,
5770 5769 sizeof (struct info_reg), &acc_attr, &pp->i_handle)
5771 5770 != DDI_SUCCESS) {
5772 5771 ecpp_error(pp->dip, "m1553_map_regs: failed i_reg\n");
5773 5772 goto fail;
5774 5773 }
5775 5774
5776 5775 if (ddi_regs_map_setup(pp->dip, 0, (caddr_t *)&pp->f_reg, 0x400,
5777 5776 sizeof (struct fifo_reg), &acc_attr, &pp->f_handle)
5778 5777 != DDI_SUCCESS) {
5779 5778 ecpp_error(pp->dip, "m1553_map_regs: failed f_reg\n");
5780 5779 goto fail;
5781 5780 }
5782 5781
5783 5782 return (SUCCESS);
5784 5783
5785 5784 fail:
5786 5785 m1553_unmap_regs(pp);
5787 5786 return (FAILURE);
5788 5787 }
5789 5788
5790 5789 static void
5791 5790 m1553_unmap_regs(struct ecppunit *pp)
5792 5791 {
5793 5792 if (pp->uh.m1553.d_handle) {
5794 5793 ddi_regs_map_free(&pp->uh.m1553.d_handle);
5795 5794 }
5796 5795 if (pp->i_handle) {
5797 5796 ddi_regs_map_free(&pp->i_handle);
5798 5797 }
5799 5798 if (pp->f_handle) {
5800 5799 ddi_regs_map_free(&pp->f_handle);
5801 5800 }
5802 5801 }
5803 5802
5804 5803 #if defined(__x86)
5805 5804 static int
5806 5805 x86_map_regs(struct ecppunit *pp)
5807 5806 {
5808 5807 int nregs = 0;
5809 5808
5810 5809 if (ddi_regs_map_setup(pp->dip, 0, (caddr_t *)&pp->i_reg, 0,
5811 5810 sizeof (struct info_reg), &acc_attr, &pp->i_handle)
5812 5811 != DDI_SUCCESS) {
5813 5812 ecpp_error(pp->dip, "x86_map_regs: failed i_reg\n");
5814 5813 goto fail;
5815 5814 }
5816 5815 if (ddi_dev_nregs(pp->dip, &nregs) == DDI_SUCCESS && nregs == 2) {
5817 5816 if (ddi_regs_map_setup(pp->dip, 1, (caddr_t *)&pp->f_reg, 0,
5818 5817 sizeof (struct fifo_reg), &acc_attr, &pp->f_handle)
5819 5818 != DDI_SUCCESS) {
5820 5819 ecpp_error(pp->dip, "x86_map_regs: failed f_reg\n");
5821 5820 goto fail;
5822 5821 } else
5823 5822 pp->noecpregs = FALSE;
5824 5823 } else {
5825 5824 pp->noecpregs = TRUE;
5826 5825 }
5827 5826 return (SUCCESS);
5828 5827 fail:
5829 5828 x86_unmap_regs(pp);
5830 5829 return (FAILURE);
5831 5830 }
5832 5831
5833 5832 static void
5834 5833 x86_unmap_regs(struct ecppunit *pp)
5835 5834 {
5836 5835 if (pp->i_handle) {
5837 5836 ddi_regs_map_free(&pp->i_handle);
5838 5837 }
5839 5838 if (pp->f_handle) {
5840 5839 ddi_regs_map_free(&pp->f_handle);
5841 5840 }
5842 5841 }
5843 5842 #endif
5844 5843
5845 5844 static uint8_t
5846 5845 m1553_read_config_reg(struct ecppunit *pp, uint8_t reg_num)
5847 5846 {
5848 5847 uint8_t retval;
5849 5848
5850 5849 dma8237_write(pp, 0x3F0, reg_num);
5851 5850 retval = dma8237_read(pp, 0x3F1);
5852 5851
5853 5852 return (retval);
5854 5853 }
5855 5854
5856 5855 static void
5857 5856 m1553_write_config_reg(struct ecppunit *pp, uint8_t reg_num, uint8_t val)
5858 5857 {
5859 5858 dma8237_write(pp, 0x3F0, reg_num);
5860 5859 dma8237_write(pp, 0x3F1, val);
5861 5860 }
5862 5861
5863 5862 static int
5864 5863 m1553_config_chip(struct ecppunit *pp)
5865 5864 {
5866 5865 uint8_t conreg;
5867 5866
5868 5867 /* Unlock configuration regs with "key sequence" */
5869 5868 dma8237_write(pp, 0x3F0, 0x51);
5870 5869 dma8237_write(pp, 0x3F0, 0x23);
5871 5870
5872 5871 m1553_write_config_reg(pp, PnP_CONFIG_DEV_NO, 0x3);
5873 5872 conreg = m1553_read_config_reg(pp, PnP_CONFIG_DEV_NO);
5874 5873 ecpp_error(pp->dip, "M1553:conreg7(logical dev)=%x\n", conreg);
5875 5874
5876 5875 conreg = m1553_read_config_reg(pp, PnP_CONFIG_ACTIVATE);
5877 5876 ecpp_error(pp->dip, "M1553:conreg30(Active)=%x\n", conreg);
5878 5877
5879 5878 conreg = m1553_read_config_reg(pp, PnP_CONFIG_BASE_ADDR_MSB);
5880 5879 ecpp_error(pp->dip, "M1553:conreg60(addrHi)=%x\n", conreg);
5881 5880 conreg = m1553_read_config_reg(pp, PnP_CONFIG_BASE_ADDR_LSB);
5882 5881 ecpp_error(pp->dip, "M1553:conreg61(addrLo)=%x\n", conreg);
5883 5882
5884 5883 conreg = m1553_read_config_reg(pp, PnP_CONFIG_INTR_SEL);
5885 5884 ecpp_error(pp->dip, "M1553:conreg70(IRQL)=%x\n", conreg);
5886 5885
5887 5886 conreg = m1553_read_config_reg(pp, PnP_CONFIG_DMA0_CHAN);
5888 5887 ecpp_error(pp->dip, "M1553:conreg74(DMA0 Chan)=%x\n", conreg);
5889 5888
5890 5889 /* set FIFO threshold 1 and ECP mode, preserve bit 7 (IRQ polarity) */
5891 5890 conreg = m1553_read_config_reg(pp, PnP_CONFIG_PP_CONFIG0);
5892 5891 conreg = (conreg & ~0x7F) | 0x0A;
5893 5892 m1553_write_config_reg(pp, PnP_CONFIG_PP_CONFIG0, conreg);
5894 5893 conreg = m1553_read_config_reg(pp, PnP_CONFIG_PP_CONFIG0);
5895 5894 ecpp_error(pp->dip, "M1553:conregFO(pport conf)=%x\n", conreg);
5896 5895
5897 5896 m1553_write_config_reg(pp, PnP_CONFIG_PP_CONFIG1, 0x04);
5898 5897 conreg = m1553_read_config_reg(pp, PnP_CONFIG_PP_CONFIG1);
5899 5898 ecpp_error(pp->dip, "M1553:conregF1(outconf)=%x\n", conreg);
5900 5899
5901 5900 /* lock configuration regs with key */
5902 5901 dma8237_write(pp, 0x3F0, 0xBB);
5903 5902
5904 5903 /* Set ECR, DCR in known state */
5905 5904 ECR_WRITE(pp, ECR_mode_001 | ECPP_INTR_MASK | ECPP_INTR_SRV);
5906 5905 DCR_WRITE(pp, ECPP_SLCTIN | ECPP_nINIT);
5907 5906
5908 5907 ecpp_error(pp->dip, "m1553_config_chip: ecr=%x, dsr=%x, dcr=%x\n",
5909 5908 ECR_READ(pp), DSR_READ(pp), DCR_READ(pp));
5910 5909
5911 5910 return (SUCCESS);
5912 5911 }
5913 5912
5914 5913 #if defined(__x86)
5915 5914 static int
5916 5915 x86_config_chip(struct ecppunit *pp)
5917 5916 {
5918 5917 if (ecr_write(pp, ECR_mode_001 |
5919 5918 ECPP_INTR_MASK | ECPP_INTR_SRV) == FAILURE) {
5920 5919 ecpp_error(pp->dip, "config chip: failed w/ecr\n");
5921 5920 pp->noecpregs = TRUE;
5922 5921 }
5923 5922 if (pp->noecpregs)
5924 5923 pp->fast_compat = FALSE;
5925 5924 DCR_WRITE(pp, ECPP_SLCTIN | ECPP_nINIT);
5926 5925 ecpp_error(pp->dip, "x86_config_chip: ecr=%x, dsr=%x, dcr=%x\n",
5927 5926 ECR_READ(pp), DSR_READ(pp), DCR_READ(pp));
5928 5927 return (SUCCESS);
5929 5928 }
5930 5929 #endif
5931 5930
5932 5931 /*
5933 5932 * dma8237_dma_start() programs the selected 8 bit channel
5934 5933 * of DMAC1 with the dma cookie. pp->dma_cookie must
5935 5934 * be set before this routine is called.
5936 5935 */
5937 5936 static int
5938 5937 dma8237_dma_start(struct ecppunit *pp)
5939 5938 {
5940 5939 uint8_t chn;
5941 5940
5942 5941 chn = pp->uh.m1553.chn;
5943 5942
5944 5943 ASSERT(chn <= DMAE_CH3 &&
5945 5944 pp->dma_cookie.dmac_size != 0 &&
5946 5945 pp->dma_cookie.dmac_address != NULL);
5947 5946
5948 5947 /* At this point Southbridge has not yet asserted DREQ */
5949 5948
5950 5949 /* set mode to read-from-memory. */
5951 5950 dma8237_write(pp, DMAC2_MODE, DMAMODE_CASC);
5952 5951 if (pp->dma_dir == DDI_DMA_READ) {
5953 5952 dma8237_write(pp, DMAC1_MODE, DMAMODE_SINGLE |
5954 5953 DMAMODE_READ | chn);
5955 5954 } else {
5956 5955 dma8237_write(pp, DMAC1_MODE, DMAMODE_SINGLE |
5957 5956 DMAMODE_WRITE | chn);
5958 5957 }
5959 5958
5960 5959 dma8237_write_addr(pp, pp->dma_cookie.dmac_address);
5961 5960 dma8237_write_count(pp, pp->dma_cookie.dmac_size - 1);
5962 5961
5963 5962 /*
5964 5963 * M1553 chip does not permit to access DMA register banks
5965 5964 * while DMA is in flight. As a result, ecpp and floppy drivers
5966 5965 * can potentially corrupt each other's DMA. The interlocking mechanism
5967 5966 * is provided by a parent nexus driver (isadma), which is enabled
5968 5967 * indirectly through a DMAC1_ALLMASK register access:
5969 5968 *
5970 5969 * writing a non-zero value to this register enters a lock,
5971 5970 * writing zero releases the lock.
5972 5971 *
5973 5972 * DMA transfer must only occur after entering a lock.
5974 5973 * If the lock is already owned by other driver, we will block.
5975 5974 *
5976 5975 * The following operation unmasks our channel and masks all others
5977 5976 */
5978 5977 dma8237_write(pp, DMAC1_ALLMASK, ~(1 << chn));
5979 5978 pp->uh.m1553.isadma_entered = 1;
5980 5979
5981 5980 return (SUCCESS);
5982 5981 }
5983 5982
5984 5983 static int
5985 5984 dma8237_dma_stop(struct ecppunit *pp, size_t *countp)
5986 5985 {
5987 5986 uint8_t ecr;
5988 5987
5989 5988 /* stop DMA */
5990 5989 ecr = (ECR_READ(pp) & 0xe0) | ECPP_INTR_MASK | ECPP_INTR_SRV;
5991 5990 (void) ecr_write(pp, ecr);
5992 5991
5993 5992 if (pp->uh.m1553.isadma_entered) {
5994 5993 /* reset the channel mask so we can issue PIO's to our device */
5995 5994 dma8237_write(pp, DMAC1_ALLMASK, 0);
5996 5995 pp->uh.m1553.isadma_entered = 0;
5997 5996
5998 5997 }
5999 5998
6000 5999 /* read DMA count if requested */
6001 6000 if (countp) {
6002 6001 *countp = dma8237_getcnt(pp);
6003 6002 if (pp->dma_dir == DDI_DMA_READ && *countp > 0) {
6004 6003 (*countp)++; /* need correction for reverse xfers */
6005 6004 }
6006 6005 }
6007 6006 return (SUCCESS);
6008 6007 }
6009 6008 #if defined(__x86)
6010 6009 static int
6011 6010 x86_dma_start(struct ecppunit *pp)
6012 6011 {
6013 6012 uint8_t chn;
6014 6013 struct ddi_dmae_req dmaereq;
6015 6014
6016 6015 chn = pp->uh.x86.chn;
6017 6016 ASSERT(chn <= DMAE_CH3 &&
6018 6017 pp->dma_cookie.dmac_size != 0 &&
6019 6018 pp->dma_cookie.dmac_address != NULL);
6020 6019 bzero(&dmaereq, sizeof (struct ddi_dmae_req));
6021 6020 dmaereq.der_command =
6022 6021 (pp->dma_dir & DDI_DMA_READ) ? DMAE_CMD_READ : DMAE_CMD_WRITE;
6023 6022 if (ddi_dmae_prog(pp->dip, &dmaereq, &pp->dma_cookie, chn)
6024 6023 != DDI_SUCCESS)
6025 6024 ecpp_error(pp->dip, "prog failed !!!\n");
6026 6025 ecpp_error(pp->dip, "dma_started..\n");
6027 6026 return (SUCCESS);
6028 6027 }
6029 6028
6030 6029 static int
6031 6030 x86_dma_stop(struct ecppunit *pp, size_t *countp)
6032 6031 {
6033 6032 uint8_t ecr;
6034 6033
6035 6034 /* stop DMA */
6036 6035 if (pp->uh.x86.chn == 0xff)
6037 6036 return (FAILURE);
6038 6037 ecr = (ECR_READ(pp) & 0xe0) | ECPP_INTR_MASK | ECPP_INTR_SRV;
6039 6038 (void) ecr_write(pp, ecr);
6040 6039 ecpp_error(pp->dip, "dma_stop\n");
6041 6040
6042 6041 /* read DMA count if requested */
6043 6042 if (countp) {
6044 6043 *countp = x86_getcnt(pp);
6045 6044 }
6046 6045 ecpp_error(pp->dip, "dma_stoped..\n");
6047 6046 return (SUCCESS);
6048 6047 }
6049 6048 #endif
6050 6049
6051 6050 /* channel must be masked */
6052 6051 static void
6053 6052 dma8237_write_addr(struct ecppunit *pp, uint32_t addr)
6054 6053 {
6055 6054 uint8_t c_addr, c_lpage;
6056 6055 uint16_t c_hpage, *p;
6057 6056
6058 6057 switch (pp->uh.m1553.chn) {
6059 6058 case DMAE_CH0:
6060 6059 c_addr = DMA_0ADR;
6061 6060 c_lpage = DMA_0PAGE;
6062 6061 c_hpage = DMA_0HPG;
6063 6062 break;
6064 6063
6065 6064 case DMAE_CH1:
6066 6065 c_addr = DMA_1ADR;
6067 6066 c_lpage = DMA_1PAGE;
6068 6067 c_hpage = DMA_1HPG;
6069 6068 break;
6070 6069
6071 6070 case DMAE_CH2:
6072 6071 c_addr = DMA_2ADR;
6073 6072 c_lpage = DMA_2PAGE;
6074 6073 c_hpage = DMA_2HPG;
6075 6074 break;
6076 6075
6077 6076 case DMAE_CH3:
6078 6077 c_addr = DMA_3ADR;
6079 6078 c_lpage = DMA_3PAGE;
6080 6079 c_hpage = DMA_3HPG;
6081 6080 break;
6082 6081
6083 6082 default:
6084 6083 return;
6085 6084 }
6086 6085
6087 6086 p = (uint16_t *)&pp->uh.m1553.isa_space->isa_reg[c_addr];
6088 6087 ddi_put16(pp->uh.m1553.d_handle, p, addr & 0xFFFF);
6089 6088
6090 6089 dma8237_write(pp, c_lpage, (addr & 0xFF0000) >> 16);
6091 6090 dma8237_write(pp, c_hpage, (addr & 0xFF000000) >> 24);
6092 6091
6093 6092 }
6094 6093
6095 6094 /*
6096 6095 * This function may be useful during debugging,
6097 6096 * so we leave it in, but do not include in the binary
6098 6097 */
6099 6098 #ifdef INCLUDE_DMA8237_READ_ADDR
6100 6099 static uint32_t
6101 6100 dma8237_read_addr(struct ecppunit *pp)
6102 6101 {
6103 6102 uint8_t rval3, rval4;
6104 6103 uint16_t rval16;
6105 6104 uint32_t rval;
6106 6105 uint8_t c_addr, c_lpage;
6107 6106 uint16_t c_hpage, *p;
6108 6107
6109 6108 switch (pp->uh.m1553.chn) {
6110 6109 case DMAE_CH0:
6111 6110 c_addr = DMA_0ADR;
6112 6111 c_lpage = DMA_0PAGE;
6113 6112 c_hpage = DMA_0HPG;
6114 6113 break;
6115 6114
6116 6115 case DMAE_CH1:
6117 6116 c_addr = DMA_1ADR;
6118 6117 c_lpage = DMA_1PAGE;
6119 6118 c_hpage = DMA_1HPG;
6120 6119 break;
6121 6120
6122 6121 case DMAE_CH2:
6123 6122 c_addr = DMA_2ADR;
6124 6123 c_lpage = DMA_2PAGE;
6125 6124 c_hpage = DMA_2HPG;
6126 6125 break;
6127 6126
6128 6127 case DMAE_CH3:
6129 6128 c_addr = DMA_3ADR;
6130 6129 c_lpage = DMA_3PAGE;
6131 6130 c_hpage = DMA_3HPG;
6132 6131 break;
6133 6132
6134 6133 default:
6135 6134 return (NULL);
6136 6135 }
6137 6136
6138 6137 p = (uint16_t *)&pp->uh.m1553.isa_space->isa_reg[c_addr];
6139 6138 rval16 = ddi_get16(pp->uh.m1553.d_handle, p);
6140 6139
6141 6140 rval3 = dma8237_read(pp, c_lpage);
6142 6141 rval4 = dma8237_read(pp, c_hpage);
6143 6142
6144 6143 rval = rval16 | (rval3 << 16) | (rval4 <<24);
6145 6144
6146 6145 return (rval);
6147 6146 }
6148 6147 #endif
6149 6148
6150 6149 static void
6151 6150 dma8237_write_count(struct ecppunit *pp, uint32_t count)
6152 6151 {
6153 6152 uint8_t c_wcnt;
6154 6153 uint16_t *p;
6155 6154
6156 6155 switch (pp->uh.m1553.chn) {
6157 6156 case DMAE_CH0:
6158 6157 c_wcnt = DMA_0WCNT;
6159 6158 break;
6160 6159
6161 6160 case DMAE_CH1:
6162 6161 c_wcnt = DMA_1WCNT;
6163 6162 break;
6164 6163
6165 6164 case DMAE_CH2:
6166 6165 c_wcnt = DMA_2WCNT;
6167 6166 break;
6168 6167
6169 6168 case DMAE_CH3:
6170 6169 c_wcnt = DMA_3WCNT;
6171 6170 break;
6172 6171
6173 6172 default:
6174 6173 return;
6175 6174 }
6176 6175
6177 6176 p = (uint16_t *)&pp->uh.m1553.isa_space->isa_reg[c_wcnt];
6178 6177 ddi_put16(pp->uh.m1553.d_handle, p, count & 0xFFFF);
6179 6178
6180 6179 }
6181 6180
6182 6181 static uint32_t
6183 6182 dma8237_read_count(struct ecppunit *pp)
6184 6183 {
6185 6184 uint8_t c_wcnt;
6186 6185 uint16_t *p;
6187 6186
6188 6187 switch (pp->uh.m1553.chn) {
6189 6188 case DMAE_CH0:
6190 6189 c_wcnt = DMA_0WCNT;
6191 6190 break;
6192 6191
6193 6192 case DMAE_CH1:
6194 6193 c_wcnt = DMA_1WCNT;
6195 6194 break;
6196 6195
6197 6196 case DMAE_CH2:
6198 6197 c_wcnt = DMA_2WCNT;
6199 6198 break;
6200 6199
6201 6200 case DMAE_CH3:
6202 6201 c_wcnt = DMA_3WCNT;
6203 6202 break;
6204 6203
6205 6204 default:
6206 6205 return (NULL);
6207 6206 }
6208 6207
6209 6208 p = (uint16_t *)&pp->uh.m1553.isa_space->isa_reg[c_wcnt];
6210 6209 return (ddi_get16(pp->uh.m1553.d_handle, p));
6211 6210
6212 6211 }
6213 6212
6214 6213 static void
6215 6214 dma8237_write(struct ecppunit *pp, int reg_num, uint8_t val)
6216 6215 {
6217 6216 ddi_put8(pp->uh.m1553.d_handle,
6218 6217 &pp->uh.m1553.isa_space->isa_reg[reg_num], val);
6219 6218 }
6220 6219
6221 6220 static uint8_t
6222 6221 dma8237_read(struct ecppunit *pp, int reg_num)
6223 6222 {
6224 6223 return (ddi_get8(pp->uh.m1553.d_handle,
6225 6224 &pp->uh.m1553.isa_space->isa_reg[reg_num]));
6226 6225 }
6227 6226
6228 6227 static size_t
6229 6228 dma8237_getcnt(struct ecppunit *pp)
6230 6229 {
6231 6230 uint32_t cnt;
6232 6231
6233 6232 if ((cnt = dma8237_read_count(pp)) == 0xffff)
6234 6233 cnt = 0;
6235 6234 else
6236 6235 cnt++;
6237 6236 return (cnt);
6238 6237 }
6239 6238
6240 6239
6241 6240 /*
6242 6241 *
6243 6242 * Kstat support routines
6244 6243 *
6245 6244 */
6246 6245 static void
6247 6246 ecpp_kstat_init(struct ecppunit *pp)
6248 6247 {
6249 6248 struct ecppkstat *ekp;
6250 6249 char buf[16];
6251 6250
6252 6251 /*
6253 6252 * Allocate, initialize and install interrupt counter kstat
6254 6253 */
6255 6254 (void) sprintf(buf, "ecppc%d", pp->instance);
6256 6255 pp->intrstats = kstat_create("ecpp", pp->instance, buf, "controller",
6257 6256 KSTAT_TYPE_INTR, 1, KSTAT_FLAG_PERSISTENT);
6258 6257 if (pp->intrstats == NULL) {
6259 6258 ecpp_error(pp->dip, "ecpp_kstat_init:1: kstat_create failed");
6260 6259 } else {
6261 6260 pp->intrstats->ks_update = ecpp_kstatintr_update;
6262 6261 pp->intrstats->ks_private = (void *) pp;
6263 6262 kstat_install(pp->intrstats);
6264 6263 }
6265 6264
6266 6265 /*
6267 6266 * Allocate, initialize and install misc stats kstat
6268 6267 */
6269 6268 pp->ksp = kstat_create("ecpp", pp->instance, NULL, "misc",
6270 6269 KSTAT_TYPE_NAMED,
6271 6270 sizeof (struct ecppkstat) / sizeof (kstat_named_t),
6272 6271 KSTAT_FLAG_PERSISTENT);
6273 6272 if (pp->ksp == NULL) {
6274 6273 ecpp_error(pp->dip, "ecpp_kstat_init:2: kstat_create failed");
6275 6274 return;
6276 6275 }
6277 6276
6278 6277 ekp = (struct ecppkstat *)pp->ksp->ks_data;
6279 6278
6280 6279 #define EK_NAMED_INIT(name) \
6281 6280 kstat_named_init(&ekp->ek_##name, #name, KSTAT_DATA_UINT32)
6282 6281
6283 6282 EK_NAMED_INIT(ctx_obytes);
6284 6283 EK_NAMED_INIT(ctxpio_obytes);
6285 6284 EK_NAMED_INIT(nib_ibytes);
6286 6285 EK_NAMED_INIT(ecp_obytes);
6287 6286 EK_NAMED_INIT(ecp_ibytes);
6288 6287 EK_NAMED_INIT(epp_obytes);
6289 6288 EK_NAMED_INIT(epp_ibytes);
6290 6289 EK_NAMED_INIT(diag_obytes);
6291 6290 EK_NAMED_INIT(to_ctx);
6292 6291 EK_NAMED_INIT(to_nib);
6293 6292 EK_NAMED_INIT(to_ecp);
6294 6293 EK_NAMED_INIT(to_epp);
6295 6294 EK_NAMED_INIT(to_diag);
6296 6295 EK_NAMED_INIT(xfer_tout);
6297 6296 EK_NAMED_INIT(ctx_cf);
6298 6297 EK_NAMED_INIT(joblen);
6299 6298 EK_NAMED_INIT(isr_reattempt_high);
6300 6299 EK_NAMED_INIT(mode);
6301 6300 EK_NAMED_INIT(phase);
6302 6301 EK_NAMED_INIT(backchan);
6303 6302 EK_NAMED_INIT(iomode);
6304 6303 EK_NAMED_INIT(state);
6305 6304
6306 6305 pp->ksp->ks_update = ecpp_kstat_update;
6307 6306 pp->ksp->ks_private = (void *) pp;
6308 6307 kstat_install(pp->ksp);
6309 6308 }
6310 6309
6311 6310 static int
6312 6311 ecpp_kstat_update(kstat_t *ksp, int rw)
6313 6312 {
6314 6313 struct ecppunit *pp;
6315 6314 struct ecppkstat *ekp;
6316 6315
6317 6316 /*
6318 6317 * For the time being there is no point
6319 6318 * in supporting writable kstats
6320 6319 */
6321 6320 if (rw == KSTAT_WRITE) {
6322 6321 return (EACCES);
6323 6322 }
6324 6323
6325 6324 pp = (struct ecppunit *)ksp->ks_private;
6326 6325 ekp = (struct ecppkstat *)ksp->ks_data;
6327 6326
6328 6327 mutex_enter(&pp->umutex);
6329 6328
6330 6329 ekp->ek_ctx_obytes.value.ui32 = pp->obytes[ECPP_CENTRONICS] +
6331 6330 pp->obytes[ECPP_COMPAT_MODE];
6332 6331 ekp->ek_ctxpio_obytes.value.ui32 = pp->ctxpio_obytes;
6333 6332 ekp->ek_nib_ibytes.value.ui32 = pp->ibytes[ECPP_NIBBLE_MODE];
6334 6333 ekp->ek_ecp_obytes.value.ui32 = pp->obytes[ECPP_ECP_MODE];
6335 6334 ekp->ek_ecp_ibytes.value.ui32 = pp->ibytes[ECPP_ECP_MODE];
6336 6335 ekp->ek_epp_obytes.value.ui32 = pp->obytes[ECPP_EPP_MODE];
6337 6336 ekp->ek_epp_ibytes.value.ui32 = pp->ibytes[ECPP_EPP_MODE];
6338 6337 ekp->ek_diag_obytes.value.ui32 = pp->obytes[ECPP_DIAG_MODE];
6339 6338 ekp->ek_to_ctx.value.ui32 = pp->to_mode[ECPP_CENTRONICS] +
6340 6339 pp->to_mode[ECPP_COMPAT_MODE];
6341 6340 ekp->ek_to_nib.value.ui32 = pp->to_mode[ECPP_NIBBLE_MODE];
6342 6341 ekp->ek_to_ecp.value.ui32 = pp->to_mode[ECPP_ECP_MODE];
6343 6342 ekp->ek_to_epp.value.ui32 = pp->to_mode[ECPP_EPP_MODE];
6344 6343 ekp->ek_to_diag.value.ui32 = pp->to_mode[ECPP_DIAG_MODE];
6345 6344 ekp->ek_xfer_tout.value.ui32 = pp->xfer_tout;
6346 6345 ekp->ek_ctx_cf.value.ui32 = pp->ctx_cf;
6347 6346 ekp->ek_joblen.value.ui32 = pp->joblen;
6348 6347 ekp->ek_isr_reattempt_high.value.ui32 = pp->isr_reattempt_high;
6349 6348 ekp->ek_mode.value.ui32 = pp->current_mode;
6350 6349 ekp->ek_phase.value.ui32 = pp->current_phase;
6351 6350 ekp->ek_backchan.value.ui32 = pp->backchannel;
6352 6351 ekp->ek_iomode.value.ui32 = pp->io_mode;
6353 6352 ekp->ek_state.value.ui32 = pp->e_busy;
6354 6353
6355 6354 mutex_exit(&pp->umutex);
6356 6355
6357 6356 return (0);
6358 6357 }
6359 6358
6360 6359 static int
6361 6360 ecpp_kstatintr_update(kstat_t *ksp, int rw)
6362 6361 {
6363 6362 struct ecppunit *pp;
6364 6363
6365 6364 /*
6366 6365 * For the time being there is no point
6367 6366 * in supporting writable kstats
6368 6367 */
6369 6368 if (rw == KSTAT_WRITE) {
6370 6369 return (EACCES);
6371 6370 }
6372 6371
6373 6372 pp = (struct ecppunit *)ksp->ks_private;
6374 6373
6375 6374 mutex_enter(&pp->umutex);
6376 6375
6377 6376 KSTAT_INTR_PTR(ksp)->intrs[KSTAT_INTR_HARD] = pp->intr_hard;
6378 6377 KSTAT_INTR_PTR(ksp)->intrs[KSTAT_INTR_SPURIOUS] = pp->intr_spurious;
6379 6378 KSTAT_INTR_PTR(ksp)->intrs[KSTAT_INTR_SOFT] = pp->intr_soft;
6380 6379
6381 6380 mutex_exit(&pp->umutex);
6382 6381
6383 6382 return (0);
6384 6383 }
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