1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21 /*
22 * Copyright 2010 Sun Microsystems, Inc. All rights reserved.
23 * Use is subject to license terms.
24 */
25
26
27 /*
28 * audio810 Audio Driver
29 *
30 * The driver is primarily targeted at providing audio support for the
31 * Intel ICHx family of AC'97 controllers and compatible parts (such
32 * as those from nVidia and AMD.)
33 *
34 * These audio parts have independent channels for PCM in, PCM out,
35 * mic in, and sometimes modem in, and modem out. The AC'97
36 * controller is a PCI bus master with scatter/gather support. Each
37 * channel has a DMA engine. Currently, we use only the PCM in and PCM
38 * out channels. Each DMA engine uses one buffer descriptor list. And
39 * the buffer descriptor list is an array of up to 32 entries, each of
40 * which describes a data buffer. Each entry contains a pointer to a
41 * data buffer, control bits, and the length of the buffer being
42 * pointed to, where the length is expressed as the number of
43 * samples. This, combined with the 16-bit sample size, gives the
44 * actual physical length of the buffer.
45 *
46 * A workaround for the AD1980 and AD1985 codec:
47 * Most vendors connect the surr-out of the codecs to the line-out jack.
48 * So far we haven't found which vendors don't do that. So we assume that
49 * all vendors swap the surr-out and the line-out outputs. So we need swap
50 * the two outputs. But we still internally process the
51 * "ad198x-swap-output" property. If someday some vendors do not swap the
52 * outputs, we would set "ad198x-swap-output = 0" in the
53 * /kernel/drv/audio810.conf file, and unload and reload the audio810
54 * driver (or reboot).
55 *
56 * NOTE:
57 * This driver depends on the drv/audio and misc/ac97
58 * modules being loaded first.
59 *
60 * The audio framework guarantees that our entry points are exclusive
61 * with suspend and resume. This includes data flow and control entry
62 * points alike.
63 *
64 * The audio framework guarantees that only one control is being
65 * accessed on any given audio device at a time.
66 *
67 * The audio framework guarantees that entry points are themselves
68 * serialized for a given engine.
69 *
70 * We have no interrupt routine or other internal asynchronous routines.
71 *
72 * Our device uses completely separate registers for each engine,
73 * except for the start/stop registers, which are implemented in a
74 * manner that allows for them to be accessed concurrently safely from
75 * different threads.
76 *
77 * Hence, it turns out that we simply don't need any locking in this
78 * driver.
79 */
80 #include <sys/types.h>
81 #include <sys/modctl.h>
82 #include <sys/kmem.h>
83 #include <sys/conf.h>
84 #include <sys/ddi.h>
85 #include <sys/sunddi.h>
86 #include <sys/pci.h>
87 #include <sys/note.h>
88 #include <sys/audio/audio_driver.h>
89 #include <sys/audio/ac97.h>
90 #include "audio810.h"
91
92 /*
93 * Module linkage routines for the kernel
94 */
95 static int audio810_ddi_attach(dev_info_t *, ddi_attach_cmd_t);
96 static int audio810_ddi_detach(dev_info_t *, ddi_detach_cmd_t);
97 static int audio810_ddi_quiesce(dev_info_t *);
98
99 /*
100 * Entry point routine prototypes
101 */
102 static int audio810_open(void *, int, unsigned *, caddr_t *);
103 static void audio810_close(void *);
104 static int audio810_start(void *);
105 static void audio810_stop(void *);
106 static int audio810_format(void *);
107 static int audio810_channels(void *);
108 static int audio810_rate(void *);
109 static uint64_t audio810_count(void *);
110 static void audio810_sync(void *, unsigned);
111 static unsigned audio810_playahead(void *);
112
113 static audio_engine_ops_t audio810_engine_ops = {
114 AUDIO_ENGINE_VERSION,
115 audio810_open,
116 audio810_close,
117 audio810_start,
118 audio810_stop,
119 audio810_count,
120 audio810_format,
121 audio810_channels,
122 audio810_rate,
123 audio810_sync,
124 NULL,
125 NULL,
126 audio810_playahead
127 };
128
129 /*
130 * Local Routine Prototypes
131 */
132 static int audio810_attach(dev_info_t *);
133 static int audio810_resume(dev_info_t *);
134 static int audio810_detach(dev_info_t *);
135 static int audio810_suspend(dev_info_t *);
136
137 static int audio810_alloc_port(audio810_state_t *, int, uint8_t);
138 static int audio810_codec_sync(audio810_state_t *);
139 static void audio810_write_ac97(void *, uint8_t, uint16_t);
140 static uint16_t audio810_read_ac97(void *, uint8_t);
141 static int audio810_map_regs(dev_info_t *, audio810_state_t *);
142 static void audio810_unmap_regs(audio810_state_t *);
143 static void audio810_stop_dma(audio810_state_t *);
144 static int audio810_chip_init(audio810_state_t *);
145 static void audio810_set_channels(audio810_state_t *);
146 static void audio810_destroy(audio810_state_t *);
147
148 /*
149 * Global variables, but used only by this file.
150 */
151
152 /*
153 * DDI Structures
154 */
155
156 /* Device operations structure */
157 static struct dev_ops audio810_dev_ops = {
158 DEVO_REV, /* devo_rev */
159 0, /* devo_refcnt */
160 NULL, /* devo_getinfo */
161 nulldev, /* devo_identify - obsolete */
162 nulldev, /* devo_probe */
163 audio810_ddi_attach, /* devo_attach */
164 audio810_ddi_detach, /* devo_detach */
165 nodev, /* devo_reset */
166 NULL, /* devi_cb_ops */
167 NULL, /* devo_bus_ops */
168 NULL, /* devo_power */
169 audio810_ddi_quiesce, /* devo_quiesce */
170 };
171
172 /* Linkage structure for loadable drivers */
173 static struct modldrv audio810_modldrv = {
174 &mod_driverops, /* drv_modops */
175 I810_MOD_NAME, /* drv_linkinfo */
176 &audio810_dev_ops, /* drv_dev_ops */
177 };
178
179 /* Module linkage structure */
180 static struct modlinkage audio810_modlinkage = {
181 MODREV_1, /* ml_rev */
182 { (void *)&audio810_modldrv, NULL } /* ml_linkage */
183 };
184
185 /*
186 * device access attributes for register mapping
187 */
188 static struct ddi_device_acc_attr dev_attr = {
189 DDI_DEVICE_ATTR_V0,
190 DDI_STRUCTURE_LE_ACC,
191 DDI_STRICTORDER_ACC
192 };
193
194 static struct ddi_device_acc_attr buf_attr = {
195 DDI_DEVICE_ATTR_V0,
196 DDI_STRUCTURE_LE_ACC,
197 DDI_STRICTORDER_ACC
198 };
199
200 /*
201 * DMA attributes of buffer descriptor list
202 */
203 static ddi_dma_attr_t bdlist_dma_attr = {
204 DMA_ATTR_V0, /* version */
205 0, /* addr_lo */
206 0xffffffff, /* addr_hi */
207 0x0000ffff, /* count_max */
208 8, /* align, BDL must be aligned on a 8-byte boundary */
209 0x3c, /* burstsize */
210 8, /* minxfer, set to the size of a BDlist entry */
211 0x0000ffff, /* maxxfer */
212 0x00000fff, /* seg, set to the RAM pagesize of intel platform */
213 1, /* sgllen, there's no scatter-gather list */
214 8, /* granular, set to the value of minxfer */
215 0 /* flags, use virtual address */
216 };
217
218 /*
219 * DMA attributes of buffers to be used to receive/send audio data
220 */
221 static ddi_dma_attr_t sample_buf_dma_attr = {
222 DMA_ATTR_V0,
223 0, /* addr_lo */
224 0xffffffff, /* addr_hi */
225 0x0001ffff, /* count_max */
226 4, /* align, data buffer is aligned on a 4-byte boundary */
227 0x3c, /* burstsize */
228 4, /* minxfer, set to the size of a sample data */
229 0x0001ffff, /* maxxfer */
230 0x0001ffff, /* seg */
231 1, /* sgllen, no scatter-gather */
232 4, /* granular, set to the value of minxfer */
233 0, /* flags, use virtual address */
234 };
235
236 /*
237 * _init()
238 *
239 * Description:
240 * Driver initialization, called when driver is first loaded.
241 * This is how access is initially given to all the static structures.
242 *
243 * Arguments:
244 * None
245 *
246 * Returns:
247 * mod_install() status, see mod_install(9f)
248 */
249 int
250 _init(void)
251 {
252 int error;
253
254 audio_init_ops(&audio810_dev_ops, I810_NAME);
255
256 if ((error = mod_install(&audio810_modlinkage)) != 0) {
257 audio_fini_ops(&audio810_dev_ops);
258 }
259
260 return (error);
261 }
262
263 /*
264 * _fini()
265 *
266 * Description:
267 * Module de-initialization, called when the driver is to be unloaded.
268 *
269 * Arguments:
270 * None
271 *
272 * Returns:
273 * mod_remove() status, see mod_remove(9f)
274 */
275 int
276 _fini(void)
277 {
278 int error;
279
280 if ((error = mod_remove(&audio810_modlinkage)) != 0) {
281 return (error);
282 }
283
284 /* clean up ops */
285 audio_fini_ops(&audio810_dev_ops);
286
287 return (0);
288 }
289
290 /*
291 * _info()
292 *
293 * Description:
294 * Module information, returns information about the driver.
295 *
296 * Arguments:
297 * modinfo *modinfop Pointer to the opaque modinfo structure
298 *
299 * Returns:
300 * mod_info() status, see mod_info(9f)
301 */
302 int
303 _info(struct modinfo *modinfop)
304 {
305 return (mod_info(&audio810_modlinkage, modinfop));
306 }
307
308
309 /* ******************* Driver Entry Points ********************************* */
310
311 /*
312 * audio810_ddi_attach()
313 *
314 * Description:
315 * Implements the DDI attach(9e) entry point.
316 *
317 * Arguments:
318 * dev_info_t *dip Pointer to the device's dev_info struct
319 * ddi_attach_cmd_t cmd Attach command
320 *
321 * Returns:
322 * DDI_SUCCESS The driver was initialized properly
323 * DDI_FAILURE The driver couldn't be initialized properly
324 */
325 static int
326 audio810_ddi_attach(dev_info_t *dip, ddi_attach_cmd_t cmd)
327 {
328 switch (cmd) {
329 case DDI_ATTACH:
330 return (audio810_attach(dip));
331
332 case DDI_RESUME:
333 return (audio810_resume(dip));
334 }
335 return (DDI_FAILURE);
336 }
337
338 /*
339 * audio810_ddi_detach()
340 *
341 * Description:
342 * Implements the detach(9e) entry point.
343 *
344 * Arguments:
345 * dev_info_t *dip Pointer to the device's dev_info struct
346 * ddi_detach_cmd_t cmd Detach command
347 *
348 * Returns:
349 * DDI_SUCCESS The driver was detached
350 * DDI_FAILURE The driver couldn't be detached
351 */
352 static int
353 audio810_ddi_detach(dev_info_t *dip, ddi_detach_cmd_t cmd)
354 {
355 switch (cmd) {
356 case DDI_DETACH:
357 return (audio810_detach(dip));
358
359 case DDI_SUSPEND:
360 return (audio810_suspend(dip));
361 }
362 return (DDI_FAILURE);
363 }
364
365 /*
366 * audio810_ddi_quiesce()
367 *
368 * Description:
369 * Implements the quiesce(9e) entry point.
370 *
371 * Arguments:
372 * dev_info_t *dip Pointer to the device's dev_info struct
373 *
374 * Returns:
375 * DDI_SUCCESS The driver was quiesced
376 * DDI_FAILURE The driver couldn't be quiesced
377 */
378 static int
379 audio810_ddi_quiesce(dev_info_t *dip)
380 {
381 audio810_state_t *statep;
382
383 if ((statep = ddi_get_driver_private(dip)) == NULL)
384 return (DDI_FAILURE);
385
386 audio810_stop_dma(statep);
387 return (DDI_SUCCESS);
388 }
389
390 /*
391 * audio810_open()
392 *
393 * Description:
394 * Opens a DMA engine for use.
395 *
396 * Arguments:
397 * void *arg The DMA engine to set up
398 * int flag Open flags
399 * unsigned *nframes Receives total number of frames
400 * caddr_t *bufp Receives kernel data buffer
401 *
402 * Returns:
403 * 0 on success
404 * errno on failure
405 */
406 static int
407 audio810_open(void *arg, int flag, unsigned *nframes, caddr_t *bufp)
408 {
409 audio810_port_t *port = arg;
410
411 _NOTE(ARGUNUSED(flag));
412
413 port->count = 0;
414 *nframes = port->samp_frames;
415 *bufp = port->samp_kaddr;
416
417 return (0);
418 }
419
420 /*
421 * audio810_close()
422 *
423 * Description:
424 * Closes an audio DMA engine that was previously opened. Since
425 * nobody is using it, we take this opportunity to possibly power
426 * down the entire device.
427 *
428 * Arguments:
429 * void *arg The DMA engine to shut down
430 */
431 static void
432 audio810_close(void *arg)
433 {
434 _NOTE(ARGUNUSED(arg));
435 }
436
437 /*
438 * audio810_stop()
439 *
440 * Description:
441 * This is called by the framework to stop a port that is
442 * transferring data.
443 *
444 * Arguments:
445 * void *arg The DMA engine to stop
446 */
447 static void
448 audio810_stop(void *arg)
449 {
450 audio810_port_t *port = arg;
451 audio810_state_t *statep = port->statep;
452 uint8_t cr;
453
454 cr = I810_BM_GET8(port->regoff + I810_OFFSET_CR);
455 cr &= ~I810_BM_CR_RUN;
456 I810_BM_PUT8(port->regoff + I810_OFFSET_CR, cr);
457 }
458
459 /*
460 * audio810_start()
461 *
462 * Description:
463 * This is called by the framework to start a port transferring data.
464 *
465 * Arguments:
466 * void *arg The DMA engine to start
467 *
468 * Returns:
469 * 0 on success (never fails, errno if it did)
470 */
471 static int
472 audio810_start(void *arg)
473 {
474 audio810_port_t *port = arg;
475 audio810_state_t *statep = port->statep;
476 uint8_t regoff, cr;
477
478 regoff = port->regoff;
479 port->offset = 0;
480
481 /* program multiple channel settings */
482 if (port->num == I810_PCM_OUT) {
483 audio810_set_channels(statep);
484
485 if (statep->quirk == QUIRK_SIS7012) {
486 /*
487 * SiS 7012 has special unmute bit.
488 */
489 I810_BM_PUT8(I810_REG_SISCTL, I810_SISCTL_UNMUTE);
490 }
491 }
492
493 /*
494 * Perform full reset of the engine, but leave it turned off.
495 */
496 I810_BM_PUT8(regoff + I810_OFFSET_CR, 0);
497 I810_BM_PUT8(regoff + I810_OFFSET_CR, I810_BM_CR_RST);
498
499 /* program the offset of the BD list */
500 I810_BM_PUT32(regoff + I810_OFFSET_BD_BASE, port->bdl_paddr);
501
502 /* we set the last index to the full count -- all buffers are valid */
503 I810_BM_PUT8(regoff + I810_OFFSET_LVI, I810_BD_NUMS - 1);
504
505 cr = I810_BM_GET8(regoff + I810_OFFSET_CR);
506 cr |= I810_BM_CR_RUN;
507 I810_BM_PUT8(regoff + I810_OFFSET_CR, cr);
508
509 (void) I810_BM_GET8(regoff + I810_OFFSET_CR);
510
511 return (0);
512 }
513
514 /*
515 * audio810_format()
516 *
517 * Description:
518 * This is called by the framework to query the format of the device.
519 *
520 * Arguments:
521 * void *arg The DMA engine to query
522 *
523 * Returns:
524 * Format of the device (fixed at AUDIO_FORMAT_S16_LE)
525 */
526 static int
527 audio810_format(void *arg)
528 {
529 _NOTE(ARGUNUSED(arg));
530
531 return (AUDIO_FORMAT_S16_LE);
532 }
533
534 /*
535 * audio810_channels()
536 *
537 * Description:
538 * This is called by the framework to query the num channels of
539 * the device.
540 *
541 * Arguments:
542 * void *arg The DMA engine to query
543 *
544 * Returns:
545 * 0 number of channels for device
546 */
547 static int
548 audio810_channels(void *arg)
549 {
550 audio810_port_t *port = arg;
551
552 return (port->nchan);
553 }
554
555 /*
556 * audio810_rate()
557 *
558 * Description:
559 * This is called by the framework to query the rate of the device.
560 *
561 * Arguments:
562 * void *arg The DMA engine to query
563 *
564 * Returns:
565 * Rate of device (fixed at 48000 Hz)
566 */
567 static int
568 audio810_rate(void *arg)
569 {
570 _NOTE(ARGUNUSED(arg));
571
572 return (48000);
573 }
574
575 /*
576 * audio810_count()
577 *
578 * Description:
579 * This is called by the framework to get the engine's frame counter
580 *
581 * Arguments:
582 * void *arg The DMA engine to query
583 *
584 * Returns:
585 * frame count for current engine
586 */
587 static uint64_t
588 audio810_count(void *arg)
589 {
590 audio810_port_t *port = arg;
591 audio810_state_t *statep = port->statep;
592 uint8_t regoff = port->regoff;
593 uint64_t val;
594 uint32_t offset;
595 uint8_t civ;
596
597 /*
598 * Read the position counters. We also take this opportunity
599 * to update the last valid index to the one just previous to
600 * the one we're working on (so we'll fully loop.)
601 */
602 offset = I810_BM_GET16(port->picboff);
603 civ = I810_BM_GET8(regoff + I810_OFFSET_CIV);
604 I810_BM_PUT8(port->regoff + I810_OFFSET_LVI, (civ - 1) % I810_BD_NUMS);
605
606 /* SiS counts in bytes, all others in words. */
607 if (statep->quirk != QUIRK_SIS7012)
608 offset *= 2;
609
610 /* counter is reversed */
611 offset = port->samp_size - offset;
612
613 if (offset < port->offset) {
614 val = (port->samp_size - port->offset) + offset;
615 } else {
616 val = offset - port->offset;
617 }
618 port->offset = offset;
619 port->count += (val / (port->nchan * 2));
620 val = port->count;
621
622 return (val);
623 }
624
625 /*
626 * audio810_sync()
627 *
628 * Description:
629 * This is called by the framework to synchronize DMA caches.
630 *
631 * Arguments:
632 * void *arg The DMA engine to sync
633 */
634 static void
635 audio810_sync(void *arg, unsigned nframes)
636 {
637 audio810_port_t *port = arg;
638 _NOTE(ARGUNUSED(nframes));
639
640 (void) ddi_dma_sync(port->samp_dmah, 0, 0, port->sync_dir);
641 }
642
643 /*
644 * audio810_playahead()
645 *
646 * Description:
647 * This is called by the framework to determine how much data it
648 * should queue up. We desire a deeper playahead than most to
649 * allow for virtualized devices which have less "regular"
650 * interrupt scheduling.
651 *
652 * Arguments:
653 * void *arg The DMA engine to query
654 *
655 * Returns:
656 * Play ahead in frames.
657 */
658 static unsigned
659 audio810_playahead(void *arg)
660 {
661 audio810_port_t *port = arg;
662 audio810_state_t *statep = port->statep;
663
664 /* Older ICH is likely to be emulated, deeper (40 ms) playahead */
665 return (statep->quirk == QUIRK_OLDICH ? 1920 : 0);
666 }
667
668
669
670 /* *********************** Local Routines *************************** */
671
672 /*
673 * audio810_attach()
674 *
675 * Description:
676 * Attach an instance of the audio810 driver. This routine does the
677 * device dependent attach tasks, and registers with the audio framework.
678 *
679 * Arguments:
680 * dev_info_t *dip Pointer to the device's dev_info struct
681 * ddi_attach_cmd_t cmd Attach command
682 *
683 * Returns:
684 * DDI_SUCCESS The driver was initialized properly
685 * DDI_FAILURE The driver couldn't be initialized properly
686 */
687 static int
688 audio810_attach(dev_info_t *dip)
689 {
690 uint16_t cmdreg;
691 audio810_state_t *statep;
692 audio_dev_t *adev;
693 ddi_acc_handle_t pcih;
694 uint32_t devid;
695 uint32_t gsr;
696 const char *name;
697 const char *vers;
698 uint8_t nch;
699 int maxch;
700
701 /* allocate the soft state structure */
702 statep = kmem_zalloc(sizeof (*statep), KM_SLEEP);
703 ddi_set_driver_private(dip, statep);
704
705 if ((adev = audio_dev_alloc(dip, 0)) == NULL) {
706 cmn_err(CE_WARN, "!%s%d: unable to allocate audio dev",
707 ddi_driver_name(dip), ddi_get_instance(dip));
708 goto error;
709 }
710 statep->adev = adev;
711 statep->dip = dip;
712
713 /* map in the registers, allocate DMA buffers, etc. */
714 if (audio810_map_regs(dip, statep) != DDI_SUCCESS) {
715 audio_dev_warn(adev, "couldn't map registers");
716 goto error;
717 }
718
719 /* set PCI command register */
720 if (pci_config_setup(dip, &pcih) != DDI_SUCCESS) {
721 audio_dev_warn(adev, "pci conf mapping failed");
722 goto error;
723 }
724 cmdreg = pci_config_get16(pcih, PCI_CONF_COMM);
725 pci_config_put16(pcih, PCI_CONF_COMM,
726 cmdreg | PCI_COMM_IO | PCI_COMM_MAE | PCI_COMM_ME);
727 devid = pci_config_get16(pcih, PCI_CONF_VENID);
728 devid <<= 16;
729 devid |= pci_config_get16(pcih, PCI_CONF_DEVID);
730 pci_config_teardown(&pcih);
731
732 name = "Unknown AC'97";
733 vers = "";
734
735 statep->quirk = QUIRK_NONE;
736 switch (devid) {
737 case 0x80862415:
738 name = "Intel AC'97";
739 vers = "ICH";
740 statep->quirk = QUIRK_OLDICH;
741 break;
742 case 0x80862425:
743 name = "Intel AC'97";
744 vers = "ICH0";
745 break;
746 case 0x80867195:
747 name = "Intel AC'97";
748 vers = "440MX";
749 break;
750 case 0x80862445:
751 name = "Intel AC'97";
752 vers = "ICH2";
753 break;
754 case 0x80862485:
755 name = "Intel AC'97";
756 vers = "ICH3";
757 break;
758 case 0x808624C5:
759 name = "Intel AC'97";
760 vers = "ICH4";
761 break;
762 case 0x808624D5:
763 name = "Intel AC'97";
764 vers = "ICH5";
765 break;
766 case 0x8086266E:
767 name = "Intel AC'97";
768 vers = "ICH6";
769 break;
770 case 0x808627DE:
771 name = "Intel AC'97";
772 vers = "ICH7";
773 break;
774 case 0x808625A6:
775 name = "Intel AC'97";
776 vers = "6300ESB";
777 break;
778 case 0x80862698:
779 name = "Intel AC'97";
780 vers = "ESB2";
781 break;
782 case 0x10397012:
783 name = "SiS AC'97";
784 vers = "7012";
785 statep->quirk = QUIRK_SIS7012;
786 break;
787 case 0x10de01b1: /* nForce */
788 name = "NVIDIA AC'97";
789 vers = "MCP1";
790 break;
791 case 0x10de006a: /* nForce 2 */
792 name = "NVIDIA AC'97";
793 vers = "MCP2";
794 break;
795 case 0x10de00da: /* nForce 3 */
796 name = "NVIDIA AC'97";
797 vers = "MCP3";
798 break;
799 case 0x10de00ea:
800 name = "NVIDIA AC'97";
801 vers = "CK8S";
802 break;
803 case 0x10de0059:
804 name = "NVIDIA AC'97";
805 vers = "CK804";
806 break;
807 case 0x10de008a:
808 name = "NVIDIA AC'97";
809 vers = "CK8";
810 break;
811 case 0x10de003a: /* nForce 4 */
812 name = "NVIDIA AC'97";
813 vers = "MCP4";
814 break;
815 case 0x10de026b:
816 name = "NVIDIA AC'97";
817 vers = "MCP51";
818 break;
819 case 0x1022746d:
820 name = "AMD AC'97";
821 vers = "8111";
822 break;
823 case 0x10227445:
824 name = "AMD AC'97";
825 vers = "AMD768";
826 break;
827 }
828 /* set device information */
829 audio_dev_set_description(adev, name);
830 audio_dev_set_version(adev, vers);
831
832 /* initialize audio controller and AC97 codec */
833 if (audio810_chip_init(statep) != DDI_SUCCESS) {
834 audio_dev_warn(adev, "failed to init chip");
835 goto error;
836 }
837
838 /* allocate ac97 handle */
839 statep->ac97 = ac97_alloc(dip, audio810_read_ac97, audio810_write_ac97,
840 statep);
841 if (statep->ac97 == NULL) {
842 audio_dev_warn(adev, "failed to allocate ac97 handle");
843 goto error;
844 }
845
846 /* initialize the AC'97 part */
847 if (ac97_init(statep->ac97, adev) != DDI_SUCCESS) {
848 audio_dev_warn(adev, "ac'97 initialization failed");
849 goto error;
850 }
851
852 /*
853 * Override "max-channels" property to prevent configuration
854 * of 4 or 6 (or possibly even 8!) channel audio. The default
855 * is to support as many channels as the hardware can do.
856 *
857 * (Hmmm... perhaps this should be driven in the common
858 * framework. The framework could even offer simplistic upmix
859 * and downmix for various standard configs.)
860 */
861 maxch = ddi_prop_get_int(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS,
862 "max-channels", ac97_num_channels(statep->ac97));
863 if (maxch < 2) {
864 maxch = 2;
865 }
866
867 gsr = I810_BM_GET32(I810_REG_GSR);
868 if (gsr & I810_GSR_CAP6CH) {
869 nch = 6;
870 } else if (gsr & I810_GSR_CAP4CH) {
871 nch = 4;
872 } else {
873 nch = 2;
874 }
875
876 statep->maxch = (uint8_t)min(nch, maxch);
877 statep->maxch &= ~1;
878
879 /* allocate port structures */
880 if ((audio810_alloc_port(statep, I810_PCM_OUT, statep->maxch) !=
881 DDI_SUCCESS) ||
882 (audio810_alloc_port(statep, I810_PCM_IN, 2) != DDI_SUCCESS)) {
883 goto error;
884 }
885
886 if (audio_dev_register(adev) != DDI_SUCCESS) {
887 audio_dev_warn(adev, "unable to register with framework");
888 goto error;
889 }
890
891 ddi_report_dev(dip);
892
893 return (DDI_SUCCESS);
894
895 error:
896 audio810_destroy(statep);
897
898 return (DDI_FAILURE);
899 }
900
901
902 /*
903 * audio810_resume()
904 *
905 * Description:
906 * Resume operation of the device after sleeping or hibernating.
907 * Note that this should never fail, even if hardware goes wonky,
908 * because the current PM framework will panic if it does.
909 *
910 * Arguments:
911 * dev_info_t *dip Pointer to the device's dev_info struct
912 *
913 * Returns:
914 * DDI_SUCCESS The driver was resumed.
915 */
916 static int
917 audio810_resume(dev_info_t *dip)
918 {
919 audio810_state_t *statep;
920 audio_dev_t *adev;
921
922 /* this should always be valid */
923 statep = ddi_get_driver_private(dip);
924 adev = statep->adev;
925
926 ASSERT(statep != NULL);
927 ASSERT(dip == statep->dip);
928
929 /* Restore the audio810 chip's state */
930 if (audio810_chip_init(statep) != DDI_SUCCESS) {
931 /*
932 * Note that PM gurus say we should return success
933 * here. Failure of audio shouldn't be considered
934 * FATAL to the system.
935 *
936 * It turns out that the only way that the
937 * audio810_chip_init fails is that the codec won't
938 * re-initialize. Audio streams may or may not make
939 * progress; setting changes may or may not have the
940 * desired effect. What we'd really to do at this
941 * point is use FMA to offline the part. In the
942 * meantime, we just muddle on logging the error.
943 *
944 * Note that returning from this routine without
945 * allowing the audio_dev_resume() to take place can
946 * have bad effects, as the framework does not know
947 * what to do in the event of a failure of this
948 * nature. (It may be unsafe to call ENG_CLOSE(), for
949 * example.)
950 */
951 audio_dev_warn(adev, "failure to resume codec");
952 }
953
954 /* Reset the AC'97 codec. */
955 ac97_reset(statep->ac97);
956
957 /* And let the framework know we're ready for business again. */
958 audio_dev_resume(statep->adev);
959
960 return (DDI_SUCCESS);
961 }
962
963 /*
964 * audio810_detach()
965 *
966 * Description:
967 * Detach an instance of the audio810 driver.
968 *
969 * Arguments:
970 * dev_info_t *dip Pointer to the device's dev_info struct
971 *
972 * Returns:
973 * DDI_SUCCESS The driver was detached
974 * DDI_FAILURE The driver couldn't be detached
975 */
976 static int
977 audio810_detach(dev_info_t *dip)
978 {
979 audio810_state_t *statep;
980
981 statep = ddi_get_driver_private(dip);
982 ASSERT(statep != NULL);
983
984 /* don't detach us if we are still in use */
985 if (audio_dev_unregister(statep->adev) != DDI_SUCCESS) {
986 return (DDI_FAILURE);
987 }
988
989 audio810_destroy(statep);
990 return (DDI_SUCCESS);
991 }
992
993 /*
994 * audio810_suspend()
995 *
996 * Description:
997 * Suspend an instance of the audio810 driver, in preparation for
998 * sleep or hibernation.
999 *
1000 * Arguments:
1001 * dev_info_t *dip Pointer to the device's dev_info struct
1002 *
1003 * Returns:
1004 * DDI_SUCCESS The driver was suspended
1005 */
1006 static int
1007 audio810_suspend(dev_info_t *dip)
1008 {
1009 audio810_state_t *statep;
1010
1011 statep = ddi_get_driver_private(dip);
1012 ASSERT(statep != NULL);
1013
1014 audio_dev_suspend(statep->adev);
1015
1016 /* stop DMA engines - should be redundant (paranoia) */
1017 audio810_stop_dma(statep);
1018
1019 return (DDI_SUCCESS);
1020 }
1021
1022 /*
1023 * audio810_alloc_port()
1024 *
1025 * Description:
1026 * This routine allocates the DMA handles and the memory for the
1027 * DMA engines to use. It also configures the BDL lists properly
1028 * for use.
1029 *
1030 * Arguments:
1031 * dev_info_t *dip Pointer to the device's devinfo
1032 *
1033 * Returns:
1034 * DDI_SUCCESS Registers successfully mapped
1035 * DDI_FAILURE Registers not successfully mapped
1036 */
1037 static int
1038 audio810_alloc_port(audio810_state_t *statep, int num, uint8_t nchan)
1039 {
1040 ddi_dma_cookie_t cookie;
1041 uint_t count;
1042 int dir;
1043 unsigned caps;
1044 audio_dev_t *adev;
1045 audio810_port_t *port;
1046 int rc;
1047 dev_info_t *dip;
1048 i810_bd_entry_t *bdentry;
1049
1050 adev = statep->adev;
1051 dip = statep->dip;
1052
1053 port = kmem_zalloc(sizeof (*port), KM_SLEEP);
1054 statep->ports[num] = port;
1055 port->statep = statep;
1056 port->nchan = nchan;
1057 port->num = num;
1058
1059 switch (num) {
1060 case I810_PCM_IN:
1061 dir = DDI_DMA_READ;
1062 caps = ENGINE_INPUT_CAP;
1063 port->sync_dir = DDI_DMA_SYNC_FORKERNEL;
1064 port->regoff = I810_BASE_PCM_IN;
1065 break;
1066 case I810_PCM_OUT:
1067 dir = DDI_DMA_WRITE;
1068 caps = ENGINE_OUTPUT_CAP;
1069 port->sync_dir = DDI_DMA_SYNC_FORDEV;
1070 port->regoff = I810_BASE_PCM_OUT;
1071 break;
1072 default:
1073 audio_dev_warn(adev, "bad port number (%d)!", num);
1074 return (DDI_FAILURE);
1075 }
1076
1077 /*
1078 * SiS 7012 swaps status and picb registers.
1079 */
1080 if (statep->quirk == QUIRK_SIS7012) {
1081 port->stsoff = port->regoff + I810_OFFSET_PICB;
1082 port->picboff = port->regoff + I810_OFFSET_SR;
1083 } else {
1084 port->stsoff = port->regoff + I810_OFFSET_SR;
1085 port->picboff = port->regoff + I810_OFFSET_PICB;
1086 }
1087
1088 /*
1089 * We use one big sample area. The sample area must be larger
1090 * than about 1.5 framework fragment sizes. (Currently 480 *
1091 * 1.5 = 720 frames.) This is necessary to ensure that we
1092 * don't have to involve an interrupt service routine on our
1093 * own, to keep the last valid index updated reasonably.
1094 */
1095 port->samp_frames = 4096;
1096 port->samp_size = port->samp_frames * port->nchan * sizeof (int16_t);
1097
1098 /* allocate dma handle */
1099 rc = ddi_dma_alloc_handle(dip, &sample_buf_dma_attr, DDI_DMA_SLEEP,
1100 NULL, &port->samp_dmah);
1101 if (rc != DDI_SUCCESS) {
1102 audio_dev_warn(adev, "ddi_dma_alloc_handle failed: %d", rc);
1103 return (DDI_FAILURE);
1104 }
1105 /* allocate DMA buffer */
1106 rc = ddi_dma_mem_alloc(port->samp_dmah, port->samp_size, &buf_attr,
1107 DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, NULL, &port->samp_kaddr,
1108 &port->samp_size, &port->samp_acch);
1109 if (rc == DDI_FAILURE) {
1110 audio_dev_warn(adev, "dma_mem_alloc (%d) failed: %d",
1111 port->samp_size, rc);
1112 return (DDI_FAILURE);
1113 }
1114
1115 /* bind DMA buffer */
1116 rc = ddi_dma_addr_bind_handle(port->samp_dmah, NULL,
1117 port->samp_kaddr, port->samp_size, dir|DDI_DMA_CONSISTENT,
1118 DDI_DMA_SLEEP, NULL, &cookie, &count);
1119 if ((rc != DDI_DMA_MAPPED) || (count != 1)) {
1120 audio_dev_warn(adev,
1121 "ddi_dma_addr_bind_handle failed: %d", rc);
1122 return (DDI_FAILURE);
1123 }
1124 port->samp_paddr = cookie.dmac_address;
1125
1126 /*
1127 * now, from here we allocate DMA memory for buffer descriptor list.
1128 * we allocate adjacent DMA memory for all DMA engines.
1129 */
1130 rc = ddi_dma_alloc_handle(dip, &bdlist_dma_attr, DDI_DMA_SLEEP,
1131 NULL, &port->bdl_dmah);
1132 if (rc != DDI_SUCCESS) {
1133 audio_dev_warn(adev, "ddi_dma_alloc_handle(bdlist) failed");
1134 return (DDI_FAILURE);
1135 }
1136
1137 /*
1138 * we allocate all buffer descriptors lists in continuous dma memory.
1139 */
1140 port->bdl_size = sizeof (i810_bd_entry_t) * I810_BD_NUMS;
1141 rc = ddi_dma_mem_alloc(port->bdl_dmah, port->bdl_size,
1142 &dev_attr, DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, NULL,
1143 &port->bdl_kaddr, &port->bdl_size, &port->bdl_acch);
1144 if (rc != DDI_SUCCESS) {
1145 audio_dev_warn(adev, "ddi_dma_mem_alloc(bdlist) failed");
1146 return (DDI_FAILURE);
1147 }
1148
1149 rc = ddi_dma_addr_bind_handle(port->bdl_dmah, NULL, port->bdl_kaddr,
1150 port->bdl_size, DDI_DMA_WRITE|DDI_DMA_CONSISTENT, DDI_DMA_SLEEP,
1151 NULL, &cookie, &count);
1152 if ((rc != DDI_DMA_MAPPED) || (count != 1)) {
1153 audio_dev_warn(adev, "addr_bind_handle failed");
1154 return (DDI_FAILURE);
1155 }
1156 port->bdl_paddr = cookie.dmac_address;
1157
1158 /*
1159 * Wire up the BD list.
1160 */
1161 bdentry = (void *)port->bdl_kaddr;
1162 for (int i = 0; i < I810_BD_NUMS; i++) {
1163
1164 /* set base address of buffer */
1165 ddi_put32(port->bdl_acch, &bdentry->buf_base,
1166 port->samp_paddr);
1167 /* SiS 7012 counts in bytes, all others in words */
1168 ddi_put16(port->bdl_acch, &bdentry->buf_len,
1169 statep->quirk == QUIRK_SIS7012 ? port->samp_size :
1170 port->samp_size / 2);
1171 ddi_put16(port->bdl_acch, &bdentry->buf_cmd, BUF_CMD_BUP);
1172
1173 bdentry++;
1174 }
1175 (void) ddi_dma_sync(port->bdl_dmah, 0, 0, DDI_DMA_SYNC_FORDEV);
1176
1177 port->engine = audio_engine_alloc(&audio810_engine_ops, caps);
1178 if (port->engine == NULL) {
1179 audio_dev_warn(adev, "audio_engine_alloc failed");
1180 return (DDI_FAILURE);
1181 }
1182
1183 audio_engine_set_private(port->engine, port);
1184 audio_dev_add_engine(adev, port->engine);
1185
1186 return (DDI_SUCCESS);
1187 }
1188
1189 /*
1190 * audio810_free_port()
1191 *
1192 * Description:
1193 * This routine unbinds the DMA cookies, frees the DMA buffers,
1194 * deallocates the DMA handles.
1195 *
1196 * Arguments:
1197 * audio810_port_t *port The port structure for a DMA engine.
1198 */
1199 static void
1200 audio810_free_port(audio810_port_t *port)
1201 {
1202 if (port == NULL)
1203 return;
1204
1205 if (port->engine) {
1206 audio_dev_remove_engine(port->statep->adev, port->engine);
1207 audio_engine_free(port->engine);
1208 }
1209 if (port->bdl_paddr) {
1210 (void) ddi_dma_unbind_handle(port->bdl_dmah);
1211 }
1212 if (port->bdl_acch) {
1213 ddi_dma_mem_free(&port->bdl_acch);
1214 }
1215 if (port->bdl_dmah) {
1216 ddi_dma_free_handle(&port->bdl_dmah);
1217 }
1218 if (port->samp_paddr) {
1219 (void) ddi_dma_unbind_handle(port->samp_dmah);
1220 }
1221 if (port->samp_acch) {
1222 ddi_dma_mem_free(&port->samp_acch);
1223 }
1224 if (port->samp_dmah) {
1225 ddi_dma_free_handle(&port->samp_dmah);
1226 }
1227 kmem_free(port, sizeof (*port));
1228 }
1229
1230 /*
1231 * audio810_map_regs()
1232 *
1233 * Description:
1234 * The registers are mapped in.
1235 *
1236 * Arguments:
1237 * dev_info_t *dip Pointer to the device's devinfo
1238 *
1239 * Returns:
1240 * DDI_SUCCESS Registers successfully mapped
1241 * DDI_FAILURE Registers not successfully mapped
1242 */
1243 static int
1244 audio810_map_regs(dev_info_t *dip, audio810_state_t *statep)
1245 {
1246 uint_t nregs = 0;
1247 int *regs_list;
1248 int i;
1249 int pciBar1 = 0;
1250 int pciBar2 = 0;
1251 int pciBar3 = 0;
1252 int pciBar4 = 0;
1253
1254 /* check the "reg" property to get the length of memory-mapped I/O */
1255 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS,
1256 "reg", (int **)®s_list, &nregs) != DDI_PROP_SUCCESS) {
1257 audio_dev_warn(statep->adev, "inquire regs property failed");
1258 goto error;
1259 }
1260 /*
1261 * Some hardwares, such as Intel ICH0/ICH and AMD 8111, use PCI 0x10
1262 * and 0x14 BAR separately for native audio mixer BAR and native bus
1263 * mastering BAR. More advanced hardwares, such as Intel ICH4 and ICH5,
1264 * support PCI memory BAR, via PCI 0x18 and 0x1C BAR, that allows for
1265 * higher performance access to the controller register. All features
1266 * can be accessed via this BAR making the I/O BAR (PCI 0x10 and 0x14
1267 * BAR) capabilities obsolete. However, these controller maintain the
1268 * I/O BAR capability to allow for the reuse of legacy code maintaining
1269 * backward compatibility. The I/O BAR is disabled unless system BIOS
1270 * enables the simultaneous backward compatible capability on the 0x41
1271 * register.
1272 *
1273 * When I/O BAR is enabled, the value of "reg" property should be like
1274 * this,
1275 * phys_hi phys_mid phys_lo size_hi size_lo
1276 * --------------------------------------------------------
1277 * 0000fd00 00000000 00000000 00000000 00000000
1278 * 0100fd10 00000000 00000000 00000000 00000100
1279 * 0100fd14 00000000 00000000 00000000 00000040
1280 * 0200fd18 00000000 00000000 00000000 00000200
1281 * 0200fd1c 00000000 00000000 00000000 00000100
1282 *
1283 * When I/O BAR is disabled, the "reg" property of the device node does
1284 * not consist of the description for the I/O BAR. The following example
1285 * illustrates the vaule of "reg" property,
1286 *
1287 * phys_hi phys_mid phys_lo size_hi size_lo
1288 * --------------------------------------------------------
1289 * 0000fd00 00000000 00000000 00000000 00000000
1290 * 0200fd18 00000000 00000000 00000000 00000200
1291 * 0200fd1c 00000000 00000000 00000000 00000100
1292 *
1293 * If the hardware has memory-mapped I/O access, first try to use
1294 * this facility, otherwise we will try I/O access.
1295 */
1296 for (i = 1; i < nregs/I810_INTS_PER_REG_PROP; i++) {
1297 switch (regs_list[I810_INTS_PER_REG_PROP * i] & 0x000000ff) {
1298 case 0x10:
1299 pciBar1 = i;
1300 break;
1301 case 0x14:
1302 pciBar2 = i;
1303 break;
1304 case 0x18:
1305 pciBar3 = i;
1306 break;
1307 case 0x1c:
1308 pciBar4 = i;
1309 break;
1310 default: /* we don't care others */
1311 break;
1312 }
1313 }
1314
1315 if ((pciBar3 != 0) && (pciBar4 != 0)) {
1316 /* map audio mixer registers */
1317 if ((ddi_regs_map_setup(dip, pciBar3, &statep->am_regs_base, 0,
1318 0, &dev_attr, &statep->am_regs_handle)) != DDI_SUCCESS) {
1319 audio_dev_warn(statep->adev,
1320 "memory am mapping failed");
1321 goto error;
1322 }
1323
1324 /* map bus master register */
1325 if ((ddi_regs_map_setup(dip, pciBar4, &statep->bm_regs_base, 0,
1326 0, &dev_attr, &statep->bm_regs_handle)) != DDI_SUCCESS) {
1327 audio_dev_warn(statep->adev,
1328 "memory bm mapping failed");
1329 goto error;
1330 }
1331
1332 } else if ((pciBar1 != 0) && (pciBar2 != 0)) {
1333 /* map audio mixer registers */
1334 if ((ddi_regs_map_setup(dip, pciBar1, &statep->am_regs_base, 0,
1335 0, &dev_attr, &statep->am_regs_handle)) != DDI_SUCCESS) {
1336 audio_dev_warn(statep->adev, "I/O am mapping failed");
1337 goto error;
1338 }
1339
1340 /* map bus master register */
1341 if ((ddi_regs_map_setup(dip, pciBar2, &statep->bm_regs_base, 0,
1342 0, &dev_attr, &statep->bm_regs_handle)) != DDI_SUCCESS) {
1343 audio_dev_warn(statep->adev, "I/O bm mapping failed");
1344 goto error;
1345 }
1346 } else {
1347 audio_dev_warn(statep->adev, "map_regs() pci BAR error");
1348 goto error;
1349 }
1350
1351 ddi_prop_free(regs_list);
1352
1353 return (DDI_SUCCESS);
1354
1355 error:
1356 if (nregs > 0) {
1357 ddi_prop_free(regs_list);
1358 }
1359 audio810_unmap_regs(statep);
1360
1361 return (DDI_FAILURE);
1362 }
1363
1364 /*
1365 * audio810_unmap_regs()
1366 *
1367 * Description:
1368 * This routine unmaps control registers.
1369 *
1370 * Arguments:
1371 * audio810_state_t *state The device's state structure
1372 */
1373 static void
1374 audio810_unmap_regs(audio810_state_t *statep)
1375 {
1376 if (statep->bm_regs_handle) {
1377 ddi_regs_map_free(&statep->bm_regs_handle);
1378 }
1379
1380 if (statep->am_regs_handle) {
1381 ddi_regs_map_free(&statep->am_regs_handle);
1382 }
1383 }
1384
1385 /*
1386 * audio810_chip_init()
1387 *
1388 * Description:
1389 * This routine initializes the audio controller.
1390 *
1391 * Arguments:
1392 * audio810_state_t *state The device's state structure
1393 *
1394 * Returns:
1395 * DDI_SUCCESS The hardware was initialized properly
1396 * DDI_FAILURE The hardware couldn't be initialized properly
1397 */
1398 static int
1399 audio810_chip_init(audio810_state_t *statep)
1400 {
1401 uint32_t gcr;
1402 uint32_t gsr;
1403 uint32_t codec_ready;
1404 int loop;
1405 clock_t ticks;
1406
1407 gcr = I810_BM_GET32(I810_REG_GCR);
1408 ticks = drv_usectohz(100);
1409
1410 /*
1411 * Clear the channels bits for now. We'll set them later in
1412 * reset port.
1413 */
1414 if (statep->quirk == QUIRK_SIS7012) {
1415 gcr &= ~(I810_GCR_ACLINK_OFF | I810_GCR_SIS_CHANNELS_MASK);
1416 } else {
1417 gcr &= ~(I810_GCR_ACLINK_OFF | I810_GCR_CHANNELS_MASK);
1418 }
1419
1420 /*
1421 * Datasheet(ICH5, document number of Intel: 252751-001):
1422 * 3.6.5.5(page 37)
1423 * if reset bit(bit1) is "0", driver must set it
1424 * to "1" to de-assert the AC_RESET# signal in AC
1425 * link, thus completing a cold reset. But if the
1426 * bit is "1", then a warm reset is required.
1427 */
1428 gcr |= (gcr & I810_GCR_COLD_RST) == 0 ?
1429 I810_GCR_COLD_RST:I810_GCR_WARM_RST;
1430 I810_BM_PUT32(I810_REG_GCR, gcr);
1431
1432 /* according AC'97 spec, wait for codec reset */
1433 for (loop = 6000; --loop >= 0; ) {
1434 delay(ticks);
1435 gcr = I810_BM_GET32(I810_REG_GCR);
1436 if ((gcr & I810_GCR_WARM_RST) == 0) {
1437 break;
1438 }
1439 }
1440
1441 /* codec reset failed */
1442 if (loop < 0) {
1443 audio_dev_warn(statep->adev, "Failed to reset codec");
1444 return (DDI_FAILURE);
1445 }
1446
1447 /*
1448 * Wait for codec ready. The hardware can provide the state of
1449 * codec ready bit on SDATA_IN[0], SDATA_IN[1] or SDATA_IN[2]
1450 */
1451 codec_ready =
1452 I810_GSR_PRI_READY | I810_GSR_SEC_READY | I810_GSR_TRI_READY;
1453 for (loop = 7000; --loop >= 0; ) {
1454 delay(ticks);
1455 gsr = I810_BM_GET32(I810_REG_GSR);
1456 if ((gsr & codec_ready) != 0) {
1457 break;
1458 }
1459 }
1460 if (loop < 0) {
1461 audio_dev_warn(statep->adev, "No codec ready signal received");
1462 return (DDI_FAILURE);
1463 }
1464
1465 /*
1466 * put the audio controller into quiet state, everything off
1467 */
1468 audio810_stop_dma(statep);
1469
1470 return (DDI_SUCCESS);
1471 }
1472
1473 /*
1474 * audio810_set_channels()
1475 *
1476 * Description:
1477 * This routine initializes the multichannel configuration.
1478 *
1479 * Arguments:
1480 * audio810_state_t *state The device's state structure
1481 */
1482 static void
1483 audio810_set_channels(audio810_state_t *statep)
1484 {
1485 uint32_t gcr;
1486
1487 /*
1488 * Configure multi-channel.
1489 */
1490 if (statep->quirk == QUIRK_SIS7012) {
1491 /*
1492 * SiS 7012 needs its own special multichannel config.
1493 */
1494 gcr = I810_BM_GET32(I810_REG_GCR);
1495 gcr &= ~I810_GCR_SIS_CHANNELS_MASK;
1496 I810_BM_PUT32(I810_REG_GCR, gcr);
1497 delay(drv_usectohz(50000)); /* 50 msec */
1498
1499 switch (statep->maxch) {
1500 case 2:
1501 gcr |= I810_GCR_SIS_2_CHANNELS;
1502 break;
1503 case 4:
1504 gcr |= I810_GCR_SIS_4_CHANNELS;
1505 break;
1506 case 6:
1507 gcr |= I810_GCR_SIS_6_CHANNELS;
1508 break;
1509 }
1510 I810_BM_PUT32(I810_REG_GCR, gcr);
1511 delay(drv_usectohz(50000)); /* 50 msec */
1512 } else {
1513
1514 /*
1515 * All other devices work the same.
1516 */
1517 gcr = I810_BM_GET32(I810_REG_GCR);
1518 gcr &= ~I810_GCR_CHANNELS_MASK;
1519
1520 I810_BM_PUT32(I810_REG_GCR, gcr);
1521 delay(drv_usectohz(50000)); /* 50 msec */
1522
1523 switch (statep->maxch) {
1524 case 2:
1525 gcr |= I810_GCR_2_CHANNELS;
1526 break;
1527 case 4:
1528 gcr |= I810_GCR_4_CHANNELS;
1529 break;
1530 case 6:
1531 gcr |= I810_GCR_6_CHANNELS;
1532 break;
1533 }
1534 I810_BM_PUT32(I810_REG_GCR, gcr);
1535 delay(drv_usectohz(50000)); /* 50 msec */
1536 }
1537 }
1538
1539 /*
1540 * audio810_stop_dma()
1541 *
1542 * Description:
1543 * This routine is used to put each DMA engine into the quiet state.
1544 *
1545 * Arguments:
1546 * audio810_state_t *state The device's state structure
1547 */
1548 static void
1549 audio810_stop_dma(audio810_state_t *statep)
1550 {
1551 if (statep->bm_regs_handle == NULL) {
1552 return;
1553 }
1554 /* pause bus master (needed for the following reset register) */
1555 I810_BM_PUT8(I810_BASE_PCM_IN + I810_OFFSET_CR, 0x0);
1556 I810_BM_PUT8(I810_BASE_PCM_OUT + I810_OFFSET_CR, 0x0);
1557 I810_BM_PUT8(I810_BASE_MIC + I810_OFFSET_CR, 0x0);
1558
1559 /* and then reset the bus master registers for a three DMA engines */
1560 I810_BM_PUT8(I810_BASE_PCM_IN + I810_OFFSET_CR, I810_BM_CR_RST);
1561 I810_BM_PUT8(I810_BASE_PCM_OUT + I810_OFFSET_CR, I810_BM_CR_RST);
1562 I810_BM_PUT8(I810_BASE_MIC + I810_OFFSET_CR, I810_BM_CR_RST);
1563 }
1564
1565
1566 /*
1567 * audio810_codec_sync()
1568 *
1569 * Description:
1570 * Serialize access to the AC97 audio mixer registers.
1571 *
1572 * Arguments:
1573 * audio810_state_t *state The device's state structure
1574 *
1575 * Returns:
1576 * DDI_SUCCESS Ready for an I/O access to the codec
1577 * DDI_FAILURE An I/O access is currently in progress, can't
1578 * perform another I/O access.
1579 */
1580 static int
1581 audio810_codec_sync(audio810_state_t *statep)
1582 {
1583 int i;
1584 uint16_t casr;
1585
1586 for (i = 0; i < 300; i++) {
1587 casr = I810_BM_GET8(I810_REG_CASR);
1588 if ((casr & 1) == 0) {
1589 return (DDI_SUCCESS);
1590 }
1591 drv_usecwait(10);
1592 }
1593
1594 return (DDI_FAILURE);
1595 }
1596
1597 /*
1598 * audio810_write_ac97()
1599 *
1600 * Description:
1601 * Set the specific AC97 Codec register.
1602 *
1603 * Arguments:
1604 * void *arg The device's state structure
1605 * uint8_t reg AC97 register number
1606 * uint16_t data The data want to be set
1607 */
1608 static void
1609 audio810_write_ac97(void *arg, uint8_t reg, uint16_t data)
1610 {
1611 audio810_state_t *statep = arg;
1612
1613 if (audio810_codec_sync(statep) == DDI_SUCCESS) {
1614 I810_AM_PUT16(reg, data);
1615 }
1616
1617 (void) audio810_read_ac97(statep, reg);
1618 }
1619
1620 /*
1621 * audio810_read_ac97()
1622 *
1623 * Description:
1624 * Get the specific AC97 Codec register.
1625 *
1626 * Arguments:
1627 * void *arg The device's state structure
1628 * uint8_t reg AC97 register number
1629 *
1630 * Returns:
1631 * The register value.
1632 */
1633 static uint16_t
1634 audio810_read_ac97(void *arg, uint8_t reg)
1635 {
1636 audio810_state_t *statep = arg;
1637 uint16_t val = 0xffff;
1638
1639 if (audio810_codec_sync(statep) == DDI_SUCCESS) {
1640 val = I810_AM_GET16(reg);
1641 }
1642 return (val);
1643 }
1644
1645 /*
1646 * audio810_destroy()
1647 *
1648 * Description:
1649 * This routine releases all resources held by the device instance,
1650 * as part of either detach or a failure in attach.
1651 *
1652 * Arguments:
1653 * audio810_state_t *state The device soft state.
1654 */
1655 void
1656 audio810_destroy(audio810_state_t *statep)
1657 {
1658 /* stop DMA engines */
1659 audio810_stop_dma(statep);
1660
1661 for (int i = 0; i < I810_NUM_PORTS; i++) {
1662 audio810_free_port(statep->ports[i]);
1663 }
1664
1665 audio810_unmap_regs(statep);
1666
1667 if (statep->ac97)
1668 ac97_free(statep->ac97);
1669
1670 if (statep->adev)
1671 audio_dev_free(statep->adev);
1672
1673 kmem_free(statep, sizeof (*statep));
1674 }