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5218 posix definition of NULL
correct unistd.h and iso/stddef_iso.h
update gate source affected
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--- old/usr/src/cmd/fm/modules/common/fabric-xlate/fx_fabric.c
+++ new/usr/src/cmd/fm/modules/common/fabric-xlate/fx_fabric.c
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21
22 22 /*
23 23 * Copyright 2010 Sun Microsystems, Inc. All rights reserved.
24 24 * Use is subject to license terms.
25 25 */
26 26 #include <stddef.h>
27 27 #include <strings.h>
28 28 #include <sys/fm/util.h>
29 29
30 30 #include "fabric-xlate.h"
31 31
32 32 #define FAB_LOOKUP(sz, name, field) \
33 33 (void) nvlist_lookup_uint ## sz(nvl, name, field)
34 34
35 35 static boolean_t fab_xlate_fake_rp = B_TRUE;
36 36 static fab_err_tbl_t *fab_master_err_tbl;
37 37
38 38 /*
39 39 * Translation tables for converting "fabric" error bits into "pci" ereports.
40 40 * <Ereport Class Name>, <Error Bit Mask>, <Preparation Function>
41 41 */
42 42
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43 43 /* MACRO for table entries with no TGT ereports */
44 44 #define NT(class, bit, prep) class, bit, prep, NULL
45 45 /* Translate Fabric ereports to ereport.io.pci.* */
46 46 fab_erpt_tbl_t fab_pci_erpt_tbl[] = {
47 47 PCI_DET_PERR, PCI_STAT_PERROR, NULL,
48 48 PCI_MDPE, PCI_STAT_S_PERROR, NULL,
49 49 PCI_SIG_SERR, PCI_STAT_S_SYSERR, NULL,
50 50 PCI_MA, PCI_STAT_R_MAST_AB, NULL,
51 51 PCI_REC_TA, PCI_STAT_R_TARG_AB, NULL,
52 52 PCI_SIG_TA, PCI_STAT_S_TARG_AB, NULL,
53 - NULL, NULL, NULL
53 + NULL, 0 , NULL
54 54 };
55 55
56 56 /* Translate Fabric ereports to ereport.io.pci.sec-* */
57 57 static fab_erpt_tbl_t fab_pci_bdg_erpt_tbl[] = {
58 58 PCI_DET_PERR, PCI_STAT_PERROR, NULL,
59 59 PCI_MDPE, PCI_STAT_S_PERROR, NULL,
60 60 PCI_REC_SERR, PCI_STAT_S_SYSERR, NULL,
61 61 #ifdef sparc
62 62 PCI_MA, PCI_STAT_R_MAST_AB, NULL,
63 63 #endif
64 64 PCI_REC_TA, PCI_STAT_R_TARG_AB, NULL,
65 65 PCI_SIG_TA, PCI_STAT_S_TARG_AB, NULL,
66 - NULL, NULL, NULL, NULL,
66 + NULL, 0 , NULL
67 67 };
68 68
69 69
70 70 /* Translate Fabric ereports to ereport.io.pci.dto */
71 71 static fab_erpt_tbl_t fab_pci_bdg_ctl_erpt_tbl[] = {
72 72 PCI_DTO, PCI_BCNF_BCNTRL_DTO_STAT, NULL,
73 - NULL, NULL, NULL
73 + NULL, 0, NULL
74 74 };
75 75
76 76 /* Translate Fabric ereports to ereport.io.pciex.* */
77 77 static fab_erpt_tbl_t fab_pcie_ce_erpt_tbl[] = {
78 78 PCIEX_RE, PCIE_AER_CE_RECEIVER_ERR, NULL,
79 79 PCIEX_RNR, PCIE_AER_CE_REPLAY_ROLLOVER, NULL,
80 80 PCIEX_RTO, PCIE_AER_CE_REPLAY_TO, NULL,
81 81 PCIEX_BDP, PCIE_AER_CE_BAD_DLLP, NULL,
82 82 PCIEX_BTP, PCIE_AER_CE_BAD_TLP, NULL,
83 83 PCIEX_ANFE, PCIE_AER_CE_AD_NFE, NULL,
84 - NULL, NULL, NULL
84 + NULL, 0, NULL
85 85 };
86 86
87 87 /*
88 88 * Translate Fabric ereports to ereport.io.pciex.*
89 89 * The Target Ereports for this section is only used on leaf devices, with the
90 90 * exception of TO
91 91 */
92 92 static fab_erpt_tbl_t fab_pcie_ue_erpt_tbl[] = {
93 93 PCIEX_TE, PCIE_AER_UCE_TRAINING, NULL,
94 94 PCIEX_DLP, PCIE_AER_UCE_DLP, NULL,
95 95 PCIEX_SD, PCIE_AER_UCE_SD, NULL,
96 96 PCIEX_ROF, PCIE_AER_UCE_RO, NULL,
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97 97 PCIEX_FCP, PCIE_AER_UCE_FCP, NULL,
98 98 PCIEX_MFP, PCIE_AER_UCE_MTLP, NULL,
99 99 PCIEX_CTO, PCIE_AER_UCE_TO, PCI_TARG_MA,
100 100 PCIEX_UC, PCIE_AER_UCE_UC, NULL,
101 101 PCIEX_ECRC, PCIE_AER_UCE_ECRC, NULL,
102 102 PCIEX_CA, PCIE_AER_UCE_CA, PCI_TARG_REC_TA,
103 103 #ifdef sparc
104 104 PCIEX_UR, PCIE_AER_UCE_UR, PCI_TARG_MA,
105 105 #endif
106 106 PCIEX_POIS, PCIE_AER_UCE_PTLP, PCI_TARG_MDPE,
107 - NULL, NULL, NULL
107 + NULL, 0, NULL
108 108 };
109 109
110 110 /* Translate Fabric ereports to ereport.io.pciex.* */
111 111 static fab_erpt_tbl_t fab_pcie_sue_erpt_tbl[] = {
112 112 PCIEX_S_TA_SC, PCIE_AER_SUCE_TA_ON_SC, PCI_TARG_REC_TA,
113 113 PCIEX_S_MA_SC, PCIE_AER_SUCE_MA_ON_SC, PCI_TARG_MA,
114 114 PCIEX_S_RTA, PCIE_AER_SUCE_RCVD_TA, PCI_TARG_REC_TA,
115 115 #ifdef sparc
116 116 PCIEX_S_RMA, PCIE_AER_SUCE_RCVD_MA, PCI_TARG_MA,
117 117 #endif
118 118 PCIEX_S_USC, PCIE_AER_SUCE_USC_ERR, NULL,
119 119 PCIEX_S_USCMD, PCIE_AER_SUCE_USC_MSG_DATA_ERR, PCI_TARG_REC_TA,
120 120 PCIEX_S_UDE, PCIE_AER_SUCE_UC_DATA_ERR, PCI_TARG_MDPE,
121 121 PCIEX_S_UAT, PCIE_AER_SUCE_UC_ATTR_ERR, PCI_TARG_MDPE,
122 122 PCIEX_S_UADR, PCIE_AER_SUCE_UC_ADDR_ERR, PCI_TARG_MDPE,
123 123 PCIEX_S_TEX, PCIE_AER_SUCE_TIMER_EXPIRED, NULL,
124 124 PCIEX_S_PERR, PCIE_AER_SUCE_PERR_ASSERT, PCI_TARG_MDPE,
125 125 PCIEX_S_SERR, PCIE_AER_SUCE_SERR_ASSERT, NULL,
126 126 PCIEX_INTERR, PCIE_AER_SUCE_INTERNAL_ERR, NULL,
127 - NULL, NULL, NULL
127 + NULL, 0, NULL
128 128 };
129 129
130 130 /* Translate Fabric ereports to ereport.io.pcix.* */
131 131 static fab_erpt_tbl_t fab_pcix_erpt_tbl[] = {
132 132 PCIX_SPL_DIS, PCI_PCIX_SPL_DSCD, NULL,
133 133 PCIX_UNEX_SPL, PCI_PCIX_UNEX_SPL, NULL,
134 134 PCIX_RX_SPL_MSG, PCI_PCIX_RX_SPL_MSG, NULL,
135 - NULL, NULL, NULL
135 + NULL, 0, NULL
136 136 };
137 137 static fab_erpt_tbl_t *fab_pcix_bdg_erpt_tbl = fab_pcix_erpt_tbl;
138 138
139 139 /* Translate Fabric ereports to ereport.io.pcix.sec-* */
140 140 static fab_erpt_tbl_t fab_pcix_bdg_sec_erpt_tbl[] = {
141 141 PCIX_SPL_DIS, PCI_PCIX_BSS_SPL_DSCD, NULL,
142 142 PCIX_UNEX_SPL, PCI_PCIX_BSS_UNEX_SPL, NULL,
143 143 PCIX_BSS_SPL_OR, PCI_PCIX_BSS_SPL_OR, NULL,
144 144 PCIX_BSS_SPL_DLY, PCI_PCIX_BSS_SPL_DLY, NULL,
145 - NULL, NULL, NULL
145 + NULL, 0, NULL
146 146 };
147 147
148 148 /* Translate Fabric ereports to ereport.io.pciex.* */
149 149 static fab_erpt_tbl_t fab_pcie_nadv_erpt_tbl[] = {
150 150 #ifdef sparc
151 151 PCIEX_UR, PCIE_DEVSTS_UR_DETECTED, NULL,
152 152 #endif
153 153 PCIEX_FAT, PCIE_DEVSTS_FE_DETECTED, NULL,
154 154 PCIEX_NONFAT, PCIE_DEVSTS_NFE_DETECTED, NULL,
155 155 PCIEX_CORR, PCIE_DEVSTS_CE_DETECTED, NULL,
156 - NULL, NULL, NULL
156 + NULL, 0, NULL
157 157 };
158 158
159 159 /* Translate Fabric ereports to ereport.io.pciex.* */
160 160 static fab_erpt_tbl_t fab_pcie_rc_erpt_tbl[] = {
161 161 PCIEX_RC_FE_MSG, PCIE_AER_RE_STS_FE_MSGS_RCVD, NULL,
162 162 PCIEX_RC_NFE_MSG, PCIE_AER_RE_STS_NFE_MSGS_RCVD, NULL,
163 163 PCIEX_RC_CE_MSG, PCIE_AER_RE_STS_CE_RCVD, NULL,
164 164 PCIEX_RC_MCE_MSG, PCIE_AER_RE_STS_MUL_CE_RCVD, NULL,
165 165 PCIEX_RC_MUE_MSG, PCIE_AER_RE_STS_MUL_FE_NFE_RCVD, NULL,
166 - NULL, NULL, NULL
166 + NULL, 0, NULL
167 167 };
168 168
169 169 /*
170 170 * Translate Fabric ereports to pseudo ereport.io.pciex.* RC Fabric Messages.
171 171 * If the RP is not a PCIe compliant RP or does not support AER, rely on the
172 172 * leaf fabric ereport to help create a xxx_MSG ereport coming from the RC.
173 173 */
174 174 static fab_erpt_tbl_t fab_pcie_fake_rc_erpt_tbl[] = {
175 175 PCIEX_RC_FE_MSG, PCIE_DEVSTS_FE_DETECTED, NULL,
176 176 PCIEX_RC_NFE_MSG, PCIE_DEVSTS_NFE_DETECTED, NULL,
177 177 PCIEX_RC_CE_MSG, PCIE_DEVSTS_CE_DETECTED, NULL,
178 - NULL, NULL, NULL,
178 + NULL, 0, NULL
179 179 };
180 180
181 181 /* ARGSUSED */
182 182 void
183 183 fab_pci_fabric_to_data(fmd_hdl_t *hdl, nvlist_t *nvl, fab_data_t *data)
184 184 {
185 185 data->nvl = nvl;
186 186
187 187 /* Generic PCI device information */
188 188 FAB_LOOKUP(16, "bdf", &data->bdf);
189 189 FAB_LOOKUP(16, "device_id", &data->device_id);
190 190 FAB_LOOKUP(16, "vendor_id", &data->vendor_id);
191 191 FAB_LOOKUP(8, "rev_id", &data->rev_id);
192 192 FAB_LOOKUP(16, "dev_type", &data->dev_type);
193 193 FAB_LOOKUP(16, "pcie_off", &data->pcie_off);
194 194 FAB_LOOKUP(16, "pcix_off", &data->pcix_off);
195 195 FAB_LOOKUP(16, "aer_off", &data->aer_off);
196 196 FAB_LOOKUP(16, "ecc_ver", &data->ecc_ver);
197 197
198 198 /* Misc ereport information */
199 199 FAB_LOOKUP(32, "remainder", &data->remainder);
200 200 FAB_LOOKUP(32, "severity", &data->severity);
201 201
202 202 /* PCI registers */
203 203 FAB_LOOKUP(16, "pci_status", &data->pci_err_status);
204 204 FAB_LOOKUP(16, "pci_command", &data->pci_cfg_comm);
205 205
206 206 /* PCI bridge registers */
207 207 FAB_LOOKUP(16, "pci_bdg_sec_status", &data->pci_bdg_sec_stat);
208 208 FAB_LOOKUP(16, "pci_bdg_ctrl", &data->pci_bdg_ctrl);
209 209
210 210 /* PCIx registers */
211 211 FAB_LOOKUP(32, "pcix_status", &data->pcix_status);
212 212 FAB_LOOKUP(16, "pcix_command", &data->pcix_command);
213 213
214 214 /* PCIx ECC Registers */
215 215 FAB_LOOKUP(16, "pcix_ecc_control_0", &data->pcix_ecc_control_0);
216 216 FAB_LOOKUP(16, "pcix_ecc_status_0", &data->pcix_ecc_status_0);
217 217 FAB_LOOKUP(32, "pcix_ecc_fst_addr_0", &data->pcix_ecc_fst_addr_0);
218 218 FAB_LOOKUP(32, "pcix_ecc_sec_addr_0", &data->pcix_ecc_sec_addr_0);
219 219 FAB_LOOKUP(32, "pcix_ecc_attr_0", &data->pcix_ecc_attr_0);
220 220
221 221 /* PCIx ECC Bridge Registers */
222 222 FAB_LOOKUP(16, "pcix_ecc_control_1", &data->pcix_ecc_control_1);
223 223 FAB_LOOKUP(16, "pcix_ecc_status_1", &data->pcix_ecc_status_1);
224 224 FAB_LOOKUP(32, "pcix_ecc_fst_addr_1", &data->pcix_ecc_fst_addr_1);
225 225 FAB_LOOKUP(32, "pcix_ecc_sec_addr_1", &data->pcix_ecc_sec_addr_1);
226 226 FAB_LOOKUP(32, "pcix_ecc_attr_1", &data->pcix_ecc_attr_1);
227 227
228 228 /* PCIx Bridge */
229 229 FAB_LOOKUP(32, "pcix_bdg_status", &data->pcix_bdg_stat);
230 230 FAB_LOOKUP(16, "pcix_bdg_sec_status", &data->pcix_bdg_sec_stat);
231 231
232 232 /* PCIe registers */
233 233 FAB_LOOKUP(16, "pcie_status", &data->pcie_err_status);
234 234 FAB_LOOKUP(16, "pcie_command", &data->pcie_err_ctl);
235 235 FAB_LOOKUP(32, "pcie_dev_cap", &data->pcie_dev_cap);
236 236
237 237 /* PCIe AER registers */
238 238 FAB_LOOKUP(32, "pcie_adv_ctl", &data->pcie_adv_ctl);
239 239 FAB_LOOKUP(32, "pcie_ue_status", &data->pcie_ue_status);
240 240 FAB_LOOKUP(32, "pcie_ue_mask", &data->pcie_ue_mask);
241 241 FAB_LOOKUP(32, "pcie_ue_sev", &data->pcie_ue_sev);
242 242 FAB_LOOKUP(32, "pcie_ue_hdr0", &data->pcie_ue_hdr[0]);
243 243 FAB_LOOKUP(32, "pcie_ue_hdr1", &data->pcie_ue_hdr[1]);
244 244 FAB_LOOKUP(32, "pcie_ue_hdr2", &data->pcie_ue_hdr[2]);
245 245 FAB_LOOKUP(32, "pcie_ue_hdr3", &data->pcie_ue_hdr[3]);
246 246 FAB_LOOKUP(32, "pcie_ce_status", &data->pcie_ce_status);
247 247 FAB_LOOKUP(32, "pcie_ce_mask", &data->pcie_ce_mask);
248 248 FAB_LOOKUP(32, "pcie_ue_tgt_trans", &data->pcie_ue_tgt_trans);
249 249 FAB_LOOKUP(64, "pcie_ue_tgt_addr", &data->pcie_ue_tgt_addr);
250 250 FAB_LOOKUP(16, "pcie_ue_tgt_bdf", &data->pcie_ue_tgt_bdf);
251 251
252 252 /* PCIe BDG AER registers */
253 253 FAB_LOOKUP(32, "pcie_sue_adv_ctl", &data->pcie_sue_ctl);
254 254 FAB_LOOKUP(32, "pcie_sue_status", &data->pcie_sue_status);
255 255 FAB_LOOKUP(32, "pcie_sue_mask", &data->pcie_sue_mask);
256 256 FAB_LOOKUP(32, "pcie_sue_sev", &data->pcie_sue_sev);
257 257 FAB_LOOKUP(32, "pcie_sue_hdr0", &data->pcie_sue_hdr[0]);
258 258 FAB_LOOKUP(32, "pcie_sue_hdr1", &data->pcie_sue_hdr[1]);
259 259 FAB_LOOKUP(32, "pcie_sue_hdr2", &data->pcie_sue_hdr[2]);
260 260 FAB_LOOKUP(32, "pcie_sue_hdr3", &data->pcie_sue_hdr[3]);
261 261 FAB_LOOKUP(32, "pcie_sue_tgt_trans", &data->pcie_sue_tgt_trans);
262 262 FAB_LOOKUP(64, "pcie_sue_tgt_addr", &data->pcie_sue_tgt_addr);
263 263 FAB_LOOKUP(16, "pcie_sue_tgt_bdf", &data->pcie_sue_tgt_bdf);
264 264
265 265 /* PCIe RP registers */
266 266 FAB_LOOKUP(32, "pcie_rp_status", &data->pcie_rp_status);
267 267 FAB_LOOKUP(16, "pcie_rp_control", &data->pcie_rp_ctl);
268 268
269 269 /* PCIe RP AER registers */
270 270 FAB_LOOKUP(32, "pcie_adv_rp_status", &data->pcie_rp_err_status);
271 271 FAB_LOOKUP(32, "pcie_adv_rp_command", &data->pcie_rp_err_cmd);
272 272 FAB_LOOKUP(16, "pcie_adv_rp_ce_src_id", &data->pcie_rp_ce_src_id);
273 273 FAB_LOOKUP(16, "pcie_adv_rp_ue_src_id", &data->pcie_rp_ue_src_id);
274 274 }
275 275
276 276 static int
277 277 fab_prep_pci_erpt(fmd_hdl_t *hdl, fab_data_t *data, nvlist_t *erpt,
278 278 fab_erpt_tbl_t *tbl)
279 279 {
280 280 const char *class = tbl->err_class;
281 281 int err = fab_prep_basic_erpt(hdl, data->nvl, erpt, B_FALSE);
282 282
283 283 /* Generate an ereport for this error bit. */
284 284 (void) snprintf(fab_buf, FM_MAX_CLASS, "ereport.io.%s.%s",
285 285 PCI_ERROR_SUBCLASS, class);
286 286 (void) nvlist_add_string(erpt, FM_CLASS, fab_buf);
287 287
288 288 (void) nvlist_add_uint16(erpt, PCI_CONFIG_STATUS, data->pci_err_status);
289 289 (void) nvlist_add_uint16(erpt, PCI_CONFIG_COMMAND, data->pci_cfg_comm);
290 290
291 291 return (err);
292 292 }
293 293
294 294 static int
295 295 fab_prep_pci_bdg_erpt(fmd_hdl_t *hdl, fab_data_t *data, nvlist_t *erpt,
296 296 fab_erpt_tbl_t *tbl)
297 297 {
298 298 const char *class = tbl->err_class;
299 299 int err = fab_prep_basic_erpt(hdl, data->nvl, erpt, B_FALSE);
300 300
301 301 /* Generate an ereport for this error bit. */
302 302 (void) snprintf(fab_buf, FM_MAX_CLASS, "ereport.io.%s.%s-%s",
303 303 PCI_ERROR_SUBCLASS, PCI_SEC_ERROR_SUBCLASS, class);
304 304 (void) nvlist_add_string(erpt, FM_CLASS, fab_buf);
305 305
306 306 (void) nvlist_add_uint16(erpt, PCI_SEC_CONFIG_STATUS,
307 307 data->pci_bdg_sec_stat);
308 308 (void) nvlist_add_uint16(erpt, PCI_BCNTRL, data->pci_bdg_ctrl);
309 309
310 310 return (err);
311 311 }
312 312
313 313 static int
314 314 fab_prep_pci_bdg_ctl_erpt(fmd_hdl_t *hdl, fab_data_t *data, nvlist_t *erpt,
315 315 fab_erpt_tbl_t *tbl)
316 316 {
317 317 const char *class = tbl->err_class;
318 318 int err = fab_prep_basic_erpt(hdl, data->nvl, erpt, B_FALSE);
319 319
320 320 /* Generate an ereport for this error bit. */
321 321 (void) snprintf(fab_buf, FM_MAX_CLASS, "ereport.io.%s.%s",
322 322 PCI_ERROR_SUBCLASS, class);
323 323 (void) nvlist_add_string(erpt, FM_CLASS, fab_buf);
324 324
325 325 (void) nvlist_add_uint16(erpt, PCI_SEC_CONFIG_STATUS,
326 326 data->pci_bdg_sec_stat);
327 327 (void) nvlist_add_uint16(erpt, PCI_BCNTRL, data->pci_bdg_ctrl);
328 328
329 329 return (err);
330 330 }
331 331
332 332
333 333 static int
334 334 fab_prep_pcie_ce_erpt(fmd_hdl_t *hdl, fab_data_t *data, nvlist_t *erpt,
335 335 fab_erpt_tbl_t *tbl)
336 336 {
337 337 const char *class = tbl->err_class;
338 338 int err = fab_prep_basic_erpt(hdl, data->nvl, erpt, B_FALSE);
339 339
340 340 /* Generate an ereport for this error bit. */
341 341 (void) snprintf(fab_buf, FM_MAX_CLASS, "ereport.io.%s.%s",
342 342 PCIEX_ERROR_SUBCLASS, class);
343 343 (void) nvlist_add_string(erpt, FM_CLASS, fab_buf);
344 344
345 345 (void) nvlist_add_uint16(erpt, PCIEX_DEVSTS_REG, data->pcie_err_status);
346 346 (void) nvlist_add_uint32(erpt, PCIEX_CE_STATUS_REG,
347 347 data->pcie_ce_status);
348 348
349 349 return (err);
350 350 }
351 351
352 352 static int
353 353 fab_prep_pcie_ue_erpt(fmd_hdl_t *hdl, fab_data_t *data, nvlist_t *erpt,
354 354 fab_erpt_tbl_t *tbl)
355 355 {
356 356 const char *class = tbl->err_class;
357 357 uint32_t first_err = 1 << (data->pcie_adv_ctl &
358 358 PCIE_AER_CTL_FST_ERR_PTR_MASK);
359 359 int err = fab_prep_basic_erpt(hdl, data->nvl, erpt, B_FALSE);
360 360
361 361 /* Generate an ereport for this error bit. */
362 362 (void) snprintf(fab_buf, FM_MAX_CLASS, "ereport.io.%s.%s",
363 363 PCIEX_ERROR_SUBCLASS, class);
364 364 (void) nvlist_add_string(erpt, FM_CLASS, fab_buf);
365 365
366 366 (void) nvlist_add_uint16(erpt, PCIEX_DEVSTS_REG, data->pcie_err_status);
367 367 (void) nvlist_add_uint32(erpt, PCIEX_UE_STATUS_REG,
368 368 data->pcie_ue_status);
369 369 (void) nvlist_add_uint32(erpt, PCIEX_UE_SEV_REG, data->pcie_ue_sev);
370 370 (void) nvlist_add_uint32(erpt, PCIEX_ADV_CTL, data->pcie_adv_ctl);
371 371
372 372 fmd_hdl_debug(hdl, "Bit 0x%x First Err 0x%x", tbl->reg_bit, first_err);
373 373
374 374 if ((tbl->reg_bit == first_err) && data->pcie_ue_tgt_bdf) {
375 375 (void) nvlist_add_uint16(erpt, PCIEX_SRC_ID,
376 376 data->pcie_ue_tgt_bdf);
377 377 (void) nvlist_add_boolean_value(erpt, PCIEX_SRC_VALID, B_TRUE);
378 378 } else {
379 379 (void) nvlist_add_uint16(erpt, PCIEX_SRC_ID, 0);
380 380 (void) nvlist_add_boolean_value(erpt, PCIEX_SRC_VALID, B_FALSE);
381 381 }
382 382
383 383 if ((tbl->reg_bit == first_err) && !data->pcie_ue_no_tgt_erpt &&
384 384 data->pcie_ue_tgt_trans) {
385 385 if (tbl->tgt_class)
386 386 fab_send_tgt_erpt(hdl, data, tbl->tgt_class, B_TRUE);
387 387 }
388 388
389 389 return (err);
390 390 }
391 391
392 392 static int
393 393 fab_prep_pcie_sue_erpt(fmd_hdl_t *hdl, fab_data_t *data, nvlist_t *erpt,
394 394 fab_erpt_tbl_t *tbl)
395 395 {
396 396 const char *class = tbl->err_class;
397 397 uint32_t first_err = 1 << (data->pcie_sue_ctl &
398 398 PCIE_AER_SCTL_FST_ERR_PTR_MASK);
399 399 int err = fab_prep_basic_erpt(hdl, data->nvl, erpt, B_FALSE);
400 400
401 401 /* Generate an ereport for this error bit. */
402 402 (void) snprintf(fab_buf, FM_MAX_CLASS, "ereport.io.%s.%s",
403 403 PCIEX_ERROR_SUBCLASS, class);
404 404 (void) nvlist_add_string(erpt, FM_CLASS, fab_buf);
405 405
406 406 (void) nvlist_add_uint32(erpt, PCIEX_SEC_UE_STATUS,
407 407 data->pcie_sue_status);
408 408
409 409 fmd_hdl_debug(hdl, "Bit 0x%x First Err 0x%x", tbl->reg_bit, first_err);
410 410
411 411 if ((tbl->reg_bit == first_err) && data->pcie_sue_tgt_bdf) {
412 412 (void) nvlist_add_uint16(erpt, PCIEX_SRC_ID,
413 413 data->pcie_sue_tgt_bdf);
414 414 (void) nvlist_add_boolean_value(erpt, PCIEX_SRC_VALID, B_TRUE);
415 415 } else {
416 416 (void) nvlist_add_uint16(erpt, PCIEX_SRC_ID, 0);
417 417 (void) nvlist_add_boolean_value(erpt, PCIEX_SRC_VALID, B_FALSE);
418 418 }
419 419
420 420 if ((tbl->reg_bit == first_err) && !data->pcie_ue_no_tgt_erpt &&
421 421 data->pcie_sue_tgt_trans) {
422 422 if (tbl->tgt_class)
423 423 fab_send_tgt_erpt(hdl, data, tbl->tgt_class, B_FALSE);
424 424 }
425 425
426 426 return (err);
427 427 }
428 428
429 429 static int
430 430 fab_prep_pcix_erpt(fmd_hdl_t *hdl, fab_data_t *data, nvlist_t *erpt,
431 431 fab_erpt_tbl_t *tbl)
432 432 {
433 433 const char *class = tbl->err_class;
434 434 int err = 0;
435 435
436 436 /* Only send if this is not a bridge */
437 437 if (!data->pcix_status || data->pcix_bdg_sec_stat)
438 438 return (1);
439 439
440 440 err = fab_prep_basic_erpt(hdl, data->nvl, erpt, B_FALSE);
441 441
442 442 /* Generate an ereport for this error bit. */
443 443 (void) snprintf(fab_buf, FM_MAX_CLASS, "ereport.io.%s.%s",
444 444 PCIX_ERROR_SUBCLASS, class);
445 445 (void) nvlist_add_string(erpt, FM_CLASS, fab_buf);
446 446
447 447 (void) nvlist_add_uint8(erpt, PCIX_COMMAND, data->pcix_command);
448 448 (void) nvlist_add_uint32(erpt, PCIX_STATUS, data->pcix_status);
449 449
450 450 return (err);
451 451 }
452 452
453 453 static void
454 454 fab_send_pcix_ecc_erpt(fmd_hdl_t *hdl, fab_data_t *data)
455 455 {
456 456 nvlist_t *erpt;
457 457 int ecc_phase = (data->pcix_ecc_status_0 & PCI_PCIX_ECC_PHASE) >> 0x4;
458 458 int ecc_corr = data->pcix_ecc_status_0 & PCI_PCIX_ECC_CORR;
459 459 int sec_ue = data->pcix_ecc_status_0 & PCI_PCIX_ECC_S_UE;
460 460 int sec_ce = data->pcix_ecc_status_0 & PCI_PCIX_ECC_S_CE;
461 461 uint32_t ctlstat = (data->pcix_ecc_control_0 << 16) |
462 462 data->pcix_ecc_status_0;
463 463
464 464 switch (ecc_phase) {
465 465 case PCI_PCIX_ECC_PHASE_NOERR:
466 466 break;
467 467 case PCI_PCIX_ECC_PHASE_FADDR:
468 468 case PCI_PCIX_ECC_PHASE_SADDR:
469 469 (void) snprintf(fab_buf, FM_MAX_CLASS,
470 470 "%s.%s", PCIX_ERROR_SUBCLASS,
471 471 ecc_corr ? PCIX_ECC_CE_ADDR : PCIX_ECC_UE_ADDR);
472 472 break;
473 473 case PCI_PCIX_ECC_PHASE_ATTR:
474 474 (void) snprintf(fab_buf, FM_MAX_CLASS,
475 475 "%s.%s", PCIX_ERROR_SUBCLASS,
476 476 ecc_corr ? PCIX_ECC_CE_ATTR : PCIX_ECC_UE_ATTR);
477 477 break;
478 478 case PCI_PCIX_ECC_PHASE_DATA32:
479 479 case PCI_PCIX_ECC_PHASE_DATA64:
480 480 (void) snprintf(fab_buf, FM_MAX_CLASS,
481 481 "%s.%s", PCIX_ERROR_SUBCLASS,
482 482 ecc_corr ? PCIX_ECC_CE_DATA : PCIX_ECC_UE_DATA);
483 483 break;
484 484 }
485 485
486 486 if (ecc_phase) {
487 487 if (nvlist_alloc(&erpt, NV_UNIQUE_NAME, 0) != 0)
488 488 goto done;
489 489 (void) fab_prep_basic_erpt(hdl, data->nvl, erpt, B_FALSE);
490 490 (void) nvlist_add_string(erpt, FM_CLASS, fab_buf);
491 491 (void) nvlist_add_uint16(erpt, PCIX_COMMAND,
492 492 data->pcix_command);
493 493 (void) nvlist_add_uint32(erpt, PCIX_STATUS, data->pcix_status);
494 494 (void) nvlist_add_uint32(erpt, PCIX_ECC_CTLSTAT, ctlstat);
495 495 (void) nvlist_add_uint32(erpt, PCIX_ECC_ATTR,
496 496 data->pcix_ecc_attr_0);
497 497 fmd_hdl_debug(hdl, "Sending ecc ereport: %s\n", fab_buf);
498 498 fmd_xprt_post(hdl, fab_fmd_xprt, erpt, 0);
499 499 if (fmd_xprt_error(hdl, fab_fmd_xprt))
500 500 fmd_hdl_debug(hdl, "Failed to send ECC ereport\n");
501 501 }
502 502
503 503 if (sec_ce || sec_ue) {
504 504 (void) snprintf(fab_buf, FM_MAX_CLASS,
505 505 "%s.%s", PCIX_ERROR_SUBCLASS,
506 506 sec_ce ? PCIX_ECC_S_CE : PCIX_ECC_S_UE);
507 507 if (nvlist_alloc(&erpt, NV_UNIQUE_NAME, 0) != 0)
508 508 goto done;
509 509 (void) fab_prep_basic_erpt(hdl, data->nvl, erpt, B_FALSE);
510 510 (void) nvlist_add_string(erpt, FM_CLASS, fab_buf);
511 511 (void) nvlist_add_uint16(erpt, PCIX_COMMAND,
512 512 data->pcix_command);
513 513 (void) nvlist_add_uint32(erpt, PCIX_STATUS, data->pcix_status);
514 514 (void) nvlist_add_uint32(erpt, PCIX_ECC_CTLSTAT, ctlstat);
515 515 (void) nvlist_add_uint32(erpt, PCIX_ECC_ATTR,
516 516 data->pcix_ecc_attr_0);
517 517 fmd_hdl_debug(hdl, "Sending ecc ereport: %s\n", fab_buf);
518 518 fmd_xprt_post(hdl, fab_fmd_xprt, erpt, 0);
519 519 if (fmd_xprt_error(hdl, fab_fmd_xprt))
520 520 fmd_hdl_debug(hdl, "Failed to send ECC ereport\n");
521 521 }
522 522
523 523 return;
524 524 done:
525 525 fmd_hdl_debug(hdl, "Failed to send ECC ereport\n");
526 526 }
527 527
528 528 static int
529 529 fab_prep_pcix_bdg_sec_erpt(fmd_hdl_t *hdl, fab_data_t *data, nvlist_t *erpt,
530 530 fab_erpt_tbl_t *tbl)
531 531 {
532 532 const char *class = tbl->err_class;
533 533 int err = fab_prep_basic_erpt(hdl, data->nvl, erpt, B_FALSE);
534 534
535 535 /* Generate an ereport for this error bit. */
536 536 (void) snprintf(fab_buf, FM_MAX_CLASS, "ereport.io.%s.%s%s",
537 537 PCIX_ERROR_SUBCLASS, PCIX_SEC_ERROR_SUBCLASS, class);
538 538 (void) nvlist_add_string(erpt, FM_CLASS, fab_buf);
539 539
540 540 (void) nvlist_add_uint16(erpt, PCIX_SEC_STATUS,
541 541 data->pcix_bdg_sec_stat);
542 542 (void) nvlist_add_uint32(erpt, PCIX_BDG_STAT, data->pcix_bdg_stat);
543 543
544 544 return (err);
545 545 }
546 546
547 547 static int
548 548 fab_prep_pcix_bdg_erpt(fmd_hdl_t *hdl, fab_data_t *data, nvlist_t *erpt,
549 549 fab_erpt_tbl_t *tbl)
550 550 {
551 551 const char *class = tbl->err_class;
552 552 int err = fab_prep_basic_erpt(hdl, data->nvl, erpt, B_FALSE);
553 553
554 554 /* Generate an ereport for this error bit. */
555 555 (void) snprintf(fab_buf, FM_MAX_CLASS, "ereport.io.%s.%s",
556 556 PCIX_ERROR_SUBCLASS, class);
557 557 (void) nvlist_add_string(erpt, FM_CLASS, fab_buf);
558 558
559 559 (void) nvlist_add_uint16(erpt, PCIX_SEC_STATUS,
560 560 data->pcix_bdg_sec_stat);
561 561 (void) nvlist_add_uint32(erpt, PCIX_BDG_STAT, data->pcix_bdg_stat);
562 562
563 563 return (err);
564 564 }
565 565
566 566 static void
567 567 fab_send_pcix_bdg_ecc_erpt(fmd_hdl_t *hdl, fab_data_t *data)
568 568 {
569 569 nvlist_t *erpt;
570 570 int ecc_phase = (data->pcix_ecc_status_1 & PCI_PCIX_ECC_PHASE) >> 0x4;
571 571 int ecc_corr = data->pcix_ecc_status_1 & PCI_PCIX_ECC_CORR;
572 572 int sec_ue = data->pcix_ecc_status_1 & PCI_PCIX_ECC_S_UE;
573 573 int sec_ce = data->pcix_ecc_status_1 & PCI_PCIX_ECC_S_CE;
574 574 uint32_t ctlstat = (data->pcix_ecc_control_1 << 16) |
575 575 data->pcix_ecc_status_1;
576 576
577 577 switch (ecc_phase) {
578 578 case PCI_PCIX_ECC_PHASE_NOERR:
579 579 break;
580 580 case PCI_PCIX_ECC_PHASE_FADDR:
581 581 case PCI_PCIX_ECC_PHASE_SADDR:
582 582 (void) snprintf(fab_buf, FM_MAX_CLASS,
583 583 "%s.%s%s", PCIX_ERROR_SUBCLASS, PCIX_SEC_ERROR_SUBCLASS,
584 584 ecc_corr ? PCIX_ECC_CE_ADDR : PCIX_ECC_UE_ADDR);
585 585 break;
586 586 case PCI_PCIX_ECC_PHASE_ATTR:
587 587 (void) snprintf(fab_buf, FM_MAX_CLASS,
588 588 "%s.%s%s", PCIX_ERROR_SUBCLASS, PCIX_SEC_ERROR_SUBCLASS,
589 589 ecc_corr ? PCIX_ECC_CE_ATTR : PCIX_ECC_UE_ATTR);
590 590 break;
591 591 case PCI_PCIX_ECC_PHASE_DATA32:
592 592 case PCI_PCIX_ECC_PHASE_DATA64:
593 593 (void) snprintf(fab_buf, FM_MAX_CLASS,
594 594 "%s.%s%s", PCIX_ERROR_SUBCLASS, PCIX_SEC_ERROR_SUBCLASS,
595 595 ecc_corr ? PCIX_ECC_CE_DATA : PCIX_ECC_UE_DATA);
596 596 break;
597 597 }
598 598 if (ecc_phase) {
599 599 if (nvlist_alloc(&erpt, NV_UNIQUE_NAME, 0) != 0)
600 600 goto done;
601 601 (void) fab_prep_basic_erpt(hdl, data->nvl, erpt, B_FALSE);
602 602 (void) nvlist_add_string(erpt, FM_CLASS, fab_buf);
603 603 (void) nvlist_add_uint16(erpt, PCIX_SEC_STATUS,
604 604 data->pcix_bdg_sec_stat);
605 605 (void) nvlist_add_uint32(erpt, PCIX_BDG_STAT,
606 606 data->pcix_bdg_stat);
607 607 (void) nvlist_add_uint32(erpt, PCIX_ECC_CTLSTAT, ctlstat);
608 608 (void) nvlist_add_uint32(erpt, PCIX_ECC_ATTR,
609 609 data->pcix_ecc_attr_1);
610 610 fmd_hdl_debug(hdl, "Sending ecc ereport: %s\n", fab_buf);
611 611 fmd_xprt_post(hdl, fab_fmd_xprt, erpt, 0);
612 612 if (fmd_xprt_error(hdl, fab_fmd_xprt))
613 613 fmd_hdl_debug(hdl, "Failed to send ECC ereport\n");
614 614 }
615 615
616 616 if (sec_ce || sec_ue) {
617 617 (void) snprintf(fab_buf, FM_MAX_CLASS,
618 618 "%s.%s%s", PCIX_ERROR_SUBCLASS, PCIX_SEC_ERROR_SUBCLASS,
619 619 sec_ce ? PCIX_ECC_S_CE : PCIX_ECC_S_UE);
620 620 if (nvlist_alloc(&erpt, NV_UNIQUE_NAME, 0) != 0)
621 621 goto done;
622 622 (void) fab_prep_basic_erpt(hdl, data->nvl, erpt, B_FALSE);
623 623 (void) nvlist_add_string(erpt, FM_CLASS, fab_buf);
624 624 (void) nvlist_add_uint16(erpt, PCIX_SEC_STATUS,
625 625 data->pcix_bdg_sec_stat);
626 626 (void) nvlist_add_uint32(erpt, PCIX_BDG_STAT,
627 627 data->pcix_bdg_stat);
628 628 (void) nvlist_add_uint32(erpt, PCIX_ECC_CTLSTAT, ctlstat);
629 629 (void) nvlist_add_uint32(erpt, PCIX_ECC_ATTR,
630 630 data->pcix_ecc_attr_1);
631 631 fmd_hdl_debug(hdl, "Sending ecc ereport: %s\n", fab_buf);
632 632 fmd_xprt_post(hdl, fab_fmd_xprt, erpt, 0);
633 633 if (fmd_xprt_error(hdl, fab_fmd_xprt))
634 634 fmd_hdl_debug(hdl, "Failed to send ECC ereport\n");
635 635 }
636 636 return;
637 637 done:
638 638 fmd_hdl_debug(hdl, "Failed to send ECC ereport\n");
639 639 }
640 640
641 641 static int
642 642 fab_prep_pcie_nadv_erpt(fmd_hdl_t *hdl, fab_data_t *data, nvlist_t *erpt,
643 643 fab_erpt_tbl_t *tbl)
644 644 {
645 645 const char *class = tbl->err_class;
646 646 int err = 0;
647 647
648 648 /* Don't send this for PCI device, Root Ports, or PCIe with AER */
649 649 if ((data->dev_type == PCIE_PCIECAP_DEV_TYPE_PCI_DEV) ||
650 650 (data->dev_type == PCIE_PCIECAP_DEV_TYPE_ROOT) ||
651 651 data->aer_off)
652 652 return (1);
653 653
654 654 err = fab_prep_basic_erpt(hdl, data->nvl, erpt, B_FALSE);
655 655
656 656 /* Generate an ereport for this error bit. */
657 657 (void) snprintf(fab_buf, FM_MAX_CLASS, "ereport.io.%s.%s",
658 658 PCIEX_ERROR_SUBCLASS, class);
659 659 (void) nvlist_add_string(erpt, FM_CLASS, fab_buf);
660 660
661 661 (void) nvlist_add_uint16(erpt, PCIEX_DEVSTS_REG, data->pcie_err_status);
662 662
663 663 return (err);
664 664 }
665 665
666 666 static int
667 667 fab_prep_pcie_rc_erpt(fmd_hdl_t *hdl, fab_data_t *data, nvlist_t *erpt,
668 668 fab_erpt_tbl_t *tbl)
669 669 {
670 670 const char *class = tbl->err_class;
671 671 uint32_t status = data->pcie_rp_err_status;
672 672 int err = 0;
673 673 int isFE = 0, isNFE = 0;
674 674
675 675 fmd_hdl_debug(hdl, "XLATE RP Error Class %s", class);
676 676
677 677 if (!data->aer_off)
678 678 return (-1);
679 679
680 680 /* Only send a FE Msg if the 1st UE error is FE */
681 681 if (STRCMP(class, PCIEX_RC_FE_MSG))
682 682 if (!(status & PCIE_AER_RE_STS_FIRST_UC_FATAL))
683 683 return (-1);
684 684 else
685 685 isFE = 1;
686 686
687 687 /* Only send a NFE Msg is the 1st UE error is NFE */
688 688 if (STRCMP(class, PCIEX_RC_NFE_MSG))
689 689 if (status & PCIE_AER_RE_STS_FIRST_UC_FATAL)
690 690 return (-1);
691 691 else
692 692 isNFE = 1;
693 693
694 694 fmd_hdl_debug(hdl, "XLATE RP Error");
695 695
696 696 err |= fab_prep_basic_erpt(hdl, data->nvl, erpt, B_FALSE);
697 697
698 698 /* Generate an ereport for this error bit. */
699 699 (void) snprintf(fab_buf, FM_MAX_CLASS, "ereport.io.%s.%s",
700 700 PCIEX_ERROR_SUBCLASS, class);
701 701 (void) nvlist_add_string(erpt, FM_CLASS, fab_buf);
702 702
703 703 (void) nvlist_add_uint32(erpt, PCIEX_ROOT_ERRSTS_REG, status);
704 704 if ((isFE || isNFE) && data->pcie_rp_ue_src_id) {
705 705 (void) nvlist_add_uint16(erpt, PCIEX_SRC_ID,
706 706 data->pcie_rp_ue_src_id);
707 707 (void) nvlist_add_boolean_value(erpt, PCIEX_SRC_VALID, B_TRUE);
708 708 }
709 709 if (STRCMP(class, PCIEX_RC_CE_MSG) && data->pcie_rp_ce_src_id) {
710 710 (void) nvlist_add_uint16(erpt, PCIEX_SRC_ID,
711 711 data->pcie_rp_ce_src_id);
712 712 (void) nvlist_add_boolean_value(erpt, PCIEX_SRC_VALID, B_TRUE);
713 713 }
714 714
715 715 return (err);
716 716 }
717 717
718 718 static int
719 719 fab_prep_pcie_fake_rc_erpt(fmd_hdl_t *hdl, fab_data_t *data, nvlist_t *erpt,
720 720 fab_erpt_tbl_t *tbl)
721 721 {
722 722 const char *class = tbl->err_class;
723 723 uint32_t rc_err_sts = 0;
724 724 int err = 0;
725 725
726 726 /*
727 727 * Don't send this for PCI device or Root Ports. Only send it on
728 728 * systems with non-compliant RPs.
729 729 */
730 730 if ((data->dev_type == PCIE_PCIECAP_DEV_TYPE_PCI_DEV) ||
731 731 (data->dev_type == PCIE_PCIECAP_DEV_TYPE_ROOT) ||
732 732 (!fab_xlate_fake_rp))
733 733 return (-1);
734 734
735 735 err = fab_prep_basic_erpt(hdl, data->nvl, erpt, B_TRUE);
736 736
737 737 /* Generate an ereport for this error bit. */
738 738 (void) snprintf(fab_buf, FM_MAX_CLASS, "ereport.io.%s.%s",
739 739 PCIEX_ERROR_SUBCLASS, class);
740 740 (void) nvlist_add_string(erpt, FM_CLASS, fab_buf);
741 741
742 742 /* Send PCIe RC Ereports */
743 743 if (data->pcie_err_status & PCIE_DEVSTS_CE_DETECTED) {
744 744 rc_err_sts |= PCIE_AER_RE_STS_CE_RCVD;
745 745 }
746 746
747 747 /* NFE/FE src id takes precedence over CE src id */
748 748 if (data->pcie_err_status & PCIE_DEVSTS_NFE_DETECTED) {
749 749 rc_err_sts |= PCIE_AER_RE_STS_NFE_MSGS_RCVD;
750 750 rc_err_sts |= PCIE_AER_RE_STS_FE_NFE_RCVD;
751 751 }
752 752 if (data->pcie_err_status & PCIE_DEVSTS_FE_DETECTED) {
753 753 rc_err_sts |= PCIE_AER_RE_STS_FE_MSGS_RCVD;
754 754 rc_err_sts |= PCIE_AER_RE_STS_FE_NFE_RCVD;
755 755 }
756 756 if ((data->pcie_err_status & PCIE_DEVSTS_NFE_DETECTED) &&
757 757 (data->pcie_err_status & PCIE_DEVSTS_FE_DETECTED)) {
758 758 rc_err_sts |= PCIE_AER_RE_STS_FIRST_UC_FATAL;
759 759 rc_err_sts |= PCIE_AER_RE_STS_MUL_FE_NFE_RCVD;
760 760 }
761 761
762 762 (void) nvlist_add_uint32(erpt, PCIEX_ROOT_ERRSTS_REG, rc_err_sts);
763 763
764 764 if (!(rc_err_sts & PCIE_AER_RE_STS_MUL_FE_NFE_RCVD)) {
765 765 (void) nvlist_add_uint16(erpt, PCIEX_SRC_ID, data->bdf);
766 766 (void) nvlist_add_boolean_value(erpt, PCIEX_SRC_VALID, B_TRUE);
767 767 }
768 768
769 769 return (err);
770 770 }
771 771
772 772 void
773 773 fab_xlate_pcie_erpts(fmd_hdl_t *hdl, fab_data_t *data)
774 774 {
775 775 fab_err_tbl_t *tbl;
776 776
777 777 fmd_hdl_debug(hdl, "Sending Ereports Now");
778 778
779 779 /* Go through the error logs and send the relavant reports */
780 780 for (tbl = fab_master_err_tbl; tbl->erpt_tbl; tbl++) {
781 781 fab_send_erpt(hdl, data, tbl);
782 782 }
783 783
784 784 /* Send PCI-X ECC Ereports */
785 785 fab_send_pcix_ecc_erpt(hdl, data);
786 786 fab_send_pcix_bdg_ecc_erpt(hdl, data);
787 787 }
788 788
789 789 void
790 790 fab_xlate_fabric_erpts(fmd_hdl_t *hdl, nvlist_t *nvl, const char *class)
791 791 {
792 792 fab_data_t data = {0};
793 793
794 794 fmd_hdl_debug(hdl, "fabric ereport received: %s\n", class);
795 795
796 796 fab_pci_fabric_to_data(hdl, nvl, &data);
797 797 fab_xlate_pcie_erpts(hdl, &data);
798 798 }
799 799
800 800 void
801 801 fab_set_fake_rp(fmd_hdl_t *hdl)
802 802 {
803 803 char *rppath = fab_get_rpdev(hdl), *str = NULL;
804 804 int count = 0;
805 805
806 806 if (!rppath) {
807 807 fmd_hdl_debug(hdl, "Can't find root port dev path");
808 808 return;
809 809 }
810 810
811 811 /*
812 812 * For the path '/pci@xxx' is fake root port,
813 813 * and '/pci@xxx/pci@y' is real root port.
814 814 */
815 815 str = rppath;
816 816 while (*str) {
817 817 if (*str == '/')
818 818 count++;
819 819 str++;
820 820 }
821 821
822 822 if (count == 1)
823 823 fab_xlate_fake_rp = B_TRUE;
824 824 else
825 825 /*
826 826 * If count is 0, then it should still be B_FALSE
827 827 */
828 828 fab_xlate_fake_rp = B_FALSE;
829 829
830 830 fmd_hdl_strfree(hdl, rppath);
831 831 }
832 832
833 833 #define SET_TBL(n, err, reg, sz) \
834 834 fab_master_err_tbl[n].erpt_tbl = fab_ ## err ## _erpt_tbl; \
835 835 fab_master_err_tbl[n].reg_offset = offsetof(fab_data_t, reg); \
836 836 fab_master_err_tbl[n].reg_size = sz; \
837 837 fab_master_err_tbl[n].fab_prep = fab_prep_ ## err ## _erpt;
838 838
839 839 void
840 840 fab_setup_master_table()
841 841 {
842 842 /* Setup the master error table */
843 843 fab_master_err_tbl = (fab_err_tbl_t *)calloc(13,
844 844 sizeof (fab_err_tbl_t));
845 845
846 846 SET_TBL(0, pci, pci_err_status, 16);
847 847 SET_TBL(1, pci_bdg, pci_bdg_sec_stat, 16);
848 848 SET_TBL(2, pci_bdg_ctl, pci_bdg_ctrl, 16);
849 849 SET_TBL(3, pcie_ce, pcie_ce_status, 32);
850 850 SET_TBL(4, pcie_ue, pcie_ue_status, 32);
851 851 SET_TBL(5, pcie_sue, pcie_sue_status, 32);
852 852 SET_TBL(6, pcix, pcix_status, 32);
853 853 SET_TBL(7, pcix_bdg_sec, pcix_bdg_sec_stat, 16);
854 854 SET_TBL(8, pcix_bdg, pcix_bdg_stat, 32);
855 855 SET_TBL(9, pcie_nadv, pcie_err_status, 16);
856 856 SET_TBL(10, pcie_rc, pcie_rp_err_status, 32);
857 857 SET_TBL(11, pcie_fake_rc, pcie_err_status, 16);
858 858 }
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