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--- old/usr/src/uts/i86pc/io/pcplusmp/apic_common.c
+++ new/usr/src/uts/i86pc/io/pcplusmp/apic_common.c
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21
22 22 /*
23 23 * Copyright (c) 2010, Oracle and/or its affiliates. All rights reserved.
24 24 */
25 25 /*
26 26 * Copyright (c) 2013, Joyent, Inc. All rights reserved.
27 27 */
28 28
29 29 /*
30 30 * PSMI 1.1 extensions are supported only in 2.6 and later versions.
31 31 * PSMI 1.2 extensions are supported only in 2.7 and later versions.
32 32 * PSMI 1.3 and 1.4 extensions are supported in Solaris 10.
33 33 * PSMI 1.5 extensions are supported in Solaris Nevada.
|
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33 lines elided |
↑ open up ↑ |
34 34 * PSMI 1.6 extensions are supported in Solaris Nevada.
35 35 * PSMI 1.7 extensions are supported in Solaris Nevada.
36 36 */
37 37 #define PSMI_1_7
38 38
39 39 #include <sys/processor.h>
40 40 #include <sys/time.h>
41 41 #include <sys/psm.h>
42 42 #include <sys/smp_impldefs.h>
43 43 #include <sys/cram.h>
44 -#include <sys/acpi/acpi.h>
44 +#include <acpica/include/acpi.h>
45 45 #include <sys/acpica.h>
46 46 #include <sys/psm_common.h>
47 47 #include <sys/apic.h>
48 48 #include <sys/pit.h>
49 49 #include <sys/ddi.h>
50 50 #include <sys/sunddi.h>
51 51 #include <sys/ddi_impldefs.h>
52 52 #include <sys/pci.h>
53 53 #include <sys/promif.h>
54 54 #include <sys/x86_archext.h>
55 55 #include <sys/cpc_impl.h>
56 56 #include <sys/uadmin.h>
57 57 #include <sys/panic.h>
58 58 #include <sys/debug.h>
59 59 #include <sys/archsystm.h>
60 60 #include <sys/trap.h>
61 61 #include <sys/machsystm.h>
62 62 #include <sys/sysmacros.h>
63 63 #include <sys/cpuvar.h>
64 64 #include <sys/rm_platter.h>
65 65 #include <sys/privregs.h>
66 66 #include <sys/note.h>
67 67 #include <sys/pci_intr_lib.h>
68 68 #include <sys/spl.h>
69 69 #include <sys/clock.h>
70 70 #include <sys/dditypes.h>
71 71 #include <sys/sunddi.h>
72 72 #include <sys/x_call.h>
73 73 #include <sys/reboot.h>
74 74 #include <sys/hpet.h>
75 75 #include <sys/apic_common.h>
76 76 #include <sys/apic_timer.h>
77 77
78 78 static void apic_record_ioapic_rdt(void *intrmap_private,
79 79 ioapic_rdt_t *irdt);
80 80 static void apic_record_msi(void *intrmap_private, msi_regs_t *mregs);
81 81
82 82 /*
83 83 * Common routines between pcplusmp & apix (taken from apic.c).
84 84 */
85 85
86 86 int apic_clkinit(int);
87 87 hrtime_t apic_gethrtime(void);
88 88 void apic_send_ipi(int, int);
89 89 void apic_set_idlecpu(processorid_t);
90 90 void apic_unset_idlecpu(processorid_t);
91 91 void apic_shutdown(int, int);
92 92 void apic_preshutdown(int, int);
93 93 processorid_t apic_get_next_processorid(processorid_t);
94 94
95 95 hrtime_t apic_gettime();
96 96
97 97 enum apic_ioapic_method_type apix_mul_ioapic_method = APIC_MUL_IOAPIC_PCPLUSMP;
98 98
99 99 /* Now the ones for Dynamic Interrupt distribution */
100 100 int apic_enable_dynamic_migration = 0;
101 101
102 102 /* maximum loop count when sending Start IPIs. */
103 103 int apic_sipi_max_loop_count = 0x1000;
104 104
105 105 /*
106 106 * These variables are frequently accessed in apic_intr_enter(),
107 107 * apic_intr_exit and apic_setspl, so group them together
108 108 */
109 109 volatile uint32_t *apicadr = NULL; /* virtual addr of local APIC */
110 110 int apic_setspl_delay = 1; /* apic_setspl - delay enable */
111 111 int apic_clkvect;
112 112
113 113 /* vector at which error interrupts come in */
114 114 int apic_errvect;
115 115 int apic_enable_error_intr = 1;
116 116 int apic_error_display_delay = 100;
117 117
118 118 /* vector at which performance counter overflow interrupts come in */
119 119 int apic_cpcovf_vect;
120 120 int apic_enable_cpcovf_intr = 1;
121 121
122 122 /* vector at which CMCI interrupts come in */
123 123 int apic_cmci_vect;
124 124 extern int cmi_enable_cmci;
125 125 extern void cmi_cmci_trap(void);
126 126
127 127 kmutex_t cmci_cpu_setup_lock; /* protects cmci_cpu_setup_registered */
128 128 int cmci_cpu_setup_registered;
129 129
130 130 /* number of CPUs in power-on transition state */
131 131 static int apic_poweron_cnt = 0;
132 132 lock_t apic_mode_switch_lock;
133 133
134 134 /*
135 135 * Patchable global variables.
136 136 */
137 137 int apic_forceload = 0;
138 138
139 139 int apic_coarse_hrtime = 1; /* 0 - use accurate slow gethrtime() */
140 140
141 141 int apic_flat_model = 0; /* 0 - clustered. 1 - flat */
142 142 int apic_panic_on_nmi = 0;
143 143 int apic_panic_on_apic_error = 0;
144 144
145 145 int apic_verbose = 0; /* 0x1ff */
146 146
147 147 #ifdef DEBUG
148 148 int apic_debug = 0;
149 149 int apic_restrict_vector = 0;
150 150
151 151 int apic_debug_msgbuf[APIC_DEBUG_MSGBUFSIZE];
152 152 int apic_debug_msgbufindex = 0;
153 153
154 154 #endif /* DEBUG */
155 155
156 156 uint_t apic_nticks = 0;
157 157 uint_t apic_skipped_redistribute = 0;
158 158
159 159 uint_t last_count_read = 0;
160 160 lock_t apic_gethrtime_lock;
161 161 volatile int apic_hrtime_stamp = 0;
162 162 volatile hrtime_t apic_nsec_since_boot = 0;
163 163
164 164 static hrtime_t apic_last_hrtime = 0;
165 165 int apic_hrtime_error = 0;
166 166 int apic_remote_hrterr = 0;
167 167 int apic_num_nmis = 0;
168 168 int apic_apic_error = 0;
169 169 int apic_num_apic_errors = 0;
170 170 int apic_num_cksum_errors = 0;
171 171
172 172 int apic_error = 0;
173 173
174 174 static int apic_cmos_ssb_set = 0;
175 175
176 176 /* use to make sure only one cpu handles the nmi */
177 177 lock_t apic_nmi_lock;
178 178 /* use to make sure only one cpu handles the error interrupt */
179 179 lock_t apic_error_lock;
180 180
181 181 static struct {
182 182 uchar_t cntl;
183 183 uchar_t data;
184 184 } aspen_bmc[] = {
185 185 { CC_SMS_WR_START, 0x18 }, /* NetFn/LUN */
186 186 { CC_SMS_WR_NEXT, 0x24 }, /* Cmd SET_WATCHDOG_TIMER */
187 187 { CC_SMS_WR_NEXT, 0x84 }, /* DataByte 1: SMS/OS no log */
188 188 { CC_SMS_WR_NEXT, 0x2 }, /* DataByte 2: Power Down */
189 189 { CC_SMS_WR_NEXT, 0x0 }, /* DataByte 3: no pre-timeout */
190 190 { CC_SMS_WR_NEXT, 0x0 }, /* DataByte 4: timer expir. */
191 191 { CC_SMS_WR_NEXT, 0xa }, /* DataByte 5: init countdown */
192 192 { CC_SMS_WR_END, 0x0 }, /* DataByte 6: init countdown */
193 193
194 194 { CC_SMS_WR_START, 0x18 }, /* NetFn/LUN */
195 195 { CC_SMS_WR_END, 0x22 } /* Cmd RESET_WATCHDOG_TIMER */
196 196 };
197 197
198 198 static struct {
199 199 int port;
200 200 uchar_t data;
201 201 } sitka_bmc[] = {
202 202 { SMS_COMMAND_REGISTER, SMS_WRITE_START },
203 203 { SMS_DATA_REGISTER, 0x18 }, /* NetFn/LUN */
204 204 { SMS_DATA_REGISTER, 0x24 }, /* Cmd SET_WATCHDOG_TIMER */
205 205 { SMS_DATA_REGISTER, 0x84 }, /* DataByte 1: SMS/OS no log */
206 206 { SMS_DATA_REGISTER, 0x2 }, /* DataByte 2: Power Down */
207 207 { SMS_DATA_REGISTER, 0x0 }, /* DataByte 3: no pre-timeout */
208 208 { SMS_DATA_REGISTER, 0x0 }, /* DataByte 4: timer expir. */
209 209 { SMS_DATA_REGISTER, 0xa }, /* DataByte 5: init countdown */
210 210 { SMS_COMMAND_REGISTER, SMS_WRITE_END },
211 211 { SMS_DATA_REGISTER, 0x0 }, /* DataByte 6: init countdown */
212 212
213 213 { SMS_COMMAND_REGISTER, SMS_WRITE_START },
214 214 { SMS_DATA_REGISTER, 0x18 }, /* NetFn/LUN */
215 215 { SMS_COMMAND_REGISTER, SMS_WRITE_END },
216 216 { SMS_DATA_REGISTER, 0x22 } /* Cmd RESET_WATCHDOG_TIMER */
217 217 };
218 218
219 219 /* Patchable global variables. */
220 220 int apic_kmdb_on_nmi = 0; /* 0 - no, 1 - yes enter kmdb */
221 221 uint32_t apic_divide_reg_init = 0; /* 0 - divide by 2 */
222 222
223 223 /* default apic ops without interrupt remapping */
224 224 static apic_intrmap_ops_t apic_nointrmap_ops = {
225 225 (int (*)(int))return_instr,
226 226 (void (*)(int))return_instr,
227 227 (void (*)(void **, dev_info_t *, uint16_t, int, uchar_t))return_instr,
228 228 (void (*)(void *, void *, uint16_t, int))return_instr,
229 229 (void (*)(void **))return_instr,
230 230 apic_record_ioapic_rdt,
231 231 apic_record_msi,
232 232 };
233 233
234 234 apic_intrmap_ops_t *apic_vt_ops = &apic_nointrmap_ops;
235 235 apic_cpus_info_t *apic_cpus = NULL;
236 236 cpuset_t apic_cpumask;
237 237 uint_t apic_picinit_called;
238 238
239 239 /* Flag to indicate that we need to shut down all processors */
240 240 static uint_t apic_shutdown_processors;
241 241
242 242 /*
243 243 * Probe the ioapic method for apix module. Called in apic_probe_common()
244 244 */
245 245 int
246 246 apic_ioapic_method_probe()
247 247 {
248 248 if (apix_enable == 0)
249 249 return (PSM_SUCCESS);
250 250
251 251 /*
252 252 * Set IOAPIC EOI handling method. The priority from low to high is:
253 253 * 1. IOxAPIC: with EOI register
254 254 * 2. IOMMU interrupt mapping
255 255 * 3. Mask-Before-EOI method for systems without boot
256 256 * interrupt routing, such as systems with only one IOAPIC;
257 257 * NVIDIA CK8-04/MCP55 systems; systems with bridge solution
258 258 * which disables the boot interrupt routing already.
259 259 * 4. Directed EOI
260 260 */
261 261 if (apic_io_ver[0] >= 0x20)
262 262 apix_mul_ioapic_method = APIC_MUL_IOAPIC_IOXAPIC;
263 263 if ((apic_io_max == 1) || (apic_nvidia_io_max == apic_io_max))
264 264 apix_mul_ioapic_method = APIC_MUL_IOAPIC_MASK;
265 265 if (apic_directed_EOI_supported())
266 266 apix_mul_ioapic_method = APIC_MUL_IOAPIC_DEOI;
267 267
268 268 /* fall back to pcplusmp */
269 269 if (apix_mul_ioapic_method == APIC_MUL_IOAPIC_PCPLUSMP) {
270 270 /* make sure apix is after pcplusmp in /etc/mach */
271 271 apix_enable = 0; /* go ahead with pcplusmp install next */
272 272 return (PSM_FAILURE);
273 273 }
274 274
275 275 return (PSM_SUCCESS);
276 276 }
277 277
278 278 /*
279 279 * handler for APIC Error interrupt. Just print a warning and continue
280 280 */
281 281 int
282 282 apic_error_intr()
283 283 {
284 284 uint_t error0, error1, error;
285 285 uint_t i;
286 286
287 287 /*
288 288 * We need to write before read as per 7.4.17 of system prog manual.
289 289 * We do both and or the results to be safe
290 290 */
291 291 error0 = apic_reg_ops->apic_read(APIC_ERROR_STATUS);
292 292 apic_reg_ops->apic_write(APIC_ERROR_STATUS, 0);
293 293 error1 = apic_reg_ops->apic_read(APIC_ERROR_STATUS);
294 294 error = error0 | error1;
295 295
296 296 /*
297 297 * Clear the APIC error status (do this on all cpus that enter here)
298 298 * (two writes are required due to the semantics of accessing the
299 299 * error status register.)
300 300 */
301 301 apic_reg_ops->apic_write(APIC_ERROR_STATUS, 0);
302 302 apic_reg_ops->apic_write(APIC_ERROR_STATUS, 0);
303 303
304 304 /*
305 305 * Prevent more than 1 CPU from handling error interrupt causing
306 306 * double printing (interleave of characters from multiple
307 307 * CPU's when using prom_printf)
308 308 */
309 309 if (lock_try(&apic_error_lock) == 0)
310 310 return (error ? DDI_INTR_CLAIMED : DDI_INTR_UNCLAIMED);
311 311 if (error) {
312 312 #if DEBUG
313 313 if (apic_debug)
314 314 debug_enter("pcplusmp: APIC Error interrupt received");
315 315 #endif /* DEBUG */
316 316 if (apic_panic_on_apic_error)
317 317 cmn_err(CE_PANIC,
318 318 "APIC Error interrupt on CPU %d. Status = %x",
319 319 psm_get_cpu_id(), error);
320 320 else {
321 321 if ((error & ~APIC_CS_ERRORS) == 0) {
322 322 /* cksum error only */
323 323 apic_error |= APIC_ERR_APIC_ERROR;
324 324 apic_apic_error |= error;
325 325 apic_num_apic_errors++;
326 326 apic_num_cksum_errors++;
327 327 } else {
328 328 /*
329 329 * prom_printf is the best shot we have of
330 330 * something which is problem free from
331 331 * high level/NMI type of interrupts
332 332 */
333 333 prom_printf("APIC Error interrupt on CPU %d. "
334 334 "Status 0 = %x, Status 1 = %x\n",
335 335 psm_get_cpu_id(), error0, error1);
336 336 apic_error |= APIC_ERR_APIC_ERROR;
337 337 apic_apic_error |= error;
338 338 apic_num_apic_errors++;
339 339 for (i = 0; i < apic_error_display_delay; i++) {
340 340 tenmicrosec();
341 341 }
342 342 /*
343 343 * provide more delay next time limited to
344 344 * roughly 1 clock tick time
345 345 */
346 346 if (apic_error_display_delay < 500)
347 347 apic_error_display_delay *= 2;
348 348 }
349 349 }
350 350 lock_clear(&apic_error_lock);
351 351 return (DDI_INTR_CLAIMED);
352 352 } else {
353 353 lock_clear(&apic_error_lock);
354 354 return (DDI_INTR_UNCLAIMED);
355 355 }
356 356 }
357 357
358 358 /*
359 359 * Turn off the mask bit in the performance counter Local Vector Table entry.
360 360 */
361 361 void
362 362 apic_cpcovf_mask_clear(void)
363 363 {
364 364 apic_reg_ops->apic_write(APIC_PCINT_VECT,
365 365 (apic_reg_ops->apic_read(APIC_PCINT_VECT) & ~APIC_LVT_MASK));
366 366 }
367 367
368 368 /*ARGSUSED*/
369 369 static int
370 370 apic_cmci_enable(xc_arg_t arg1, xc_arg_t arg2, xc_arg_t arg3)
371 371 {
372 372 apic_reg_ops->apic_write(APIC_CMCI_VECT, apic_cmci_vect);
373 373 return (0);
374 374 }
375 375
376 376 /*ARGSUSED*/
377 377 static int
378 378 apic_cmci_disable(xc_arg_t arg1, xc_arg_t arg2, xc_arg_t arg3)
379 379 {
380 380 apic_reg_ops->apic_write(APIC_CMCI_VECT, apic_cmci_vect | AV_MASK);
381 381 return (0);
382 382 }
383 383
384 384 /*ARGSUSED*/
385 385 int
386 386 cmci_cpu_setup(cpu_setup_t what, int cpuid, void *arg)
387 387 {
388 388 cpuset_t cpu_set;
389 389
390 390 CPUSET_ONLY(cpu_set, cpuid);
391 391
392 392 switch (what) {
393 393 case CPU_ON:
394 394 xc_call(NULL, NULL, NULL, CPUSET2BV(cpu_set),
395 395 (xc_func_t)apic_cmci_enable);
396 396 break;
397 397
398 398 case CPU_OFF:
399 399 xc_call(NULL, NULL, NULL, CPUSET2BV(cpu_set),
400 400 (xc_func_t)apic_cmci_disable);
401 401 break;
402 402
403 403 default:
404 404 break;
405 405 }
406 406
407 407 return (0);
408 408 }
409 409
410 410 static void
411 411 apic_disable_local_apic(void)
412 412 {
413 413 apic_reg_ops->apic_write_task_reg(APIC_MASK_ALL);
414 414 apic_reg_ops->apic_write(APIC_LOCAL_TIMER, AV_MASK);
415 415
416 416 /* local intr reg 0 */
417 417 apic_reg_ops->apic_write(APIC_INT_VECT0, AV_MASK);
418 418
419 419 /* disable NMI */
420 420 apic_reg_ops->apic_write(APIC_INT_VECT1, AV_MASK);
421 421
422 422 /* and error interrupt */
423 423 apic_reg_ops->apic_write(APIC_ERR_VECT, AV_MASK);
424 424
425 425 /* and perf counter intr */
426 426 apic_reg_ops->apic_write(APIC_PCINT_VECT, AV_MASK);
427 427
428 428 apic_reg_ops->apic_write(APIC_SPUR_INT_REG, APIC_SPUR_INTR);
429 429 }
430 430
431 431 static void
432 432 apic_cpu_send_SIPI(processorid_t cpun, boolean_t start)
433 433 {
434 434 int loop_count;
435 435 uint32_t vector;
436 436 uint_t apicid;
437 437 ulong_t iflag;
438 438
439 439 apicid = apic_cpus[cpun].aci_local_id;
440 440
441 441 /*
442 442 * Interrupts on current CPU will be disabled during the
443 443 * steps in order to avoid unwanted side effects from
444 444 * executing interrupt handlers on a problematic BIOS.
445 445 */
446 446 iflag = intr_clear();
447 447
448 448 if (start) {
449 449 outb(CMOS_ADDR, SSB);
450 450 outb(CMOS_DATA, BIOS_SHUTDOWN);
451 451 }
452 452
453 453 /*
454 454 * According to X2APIC specification in section '2.3.5.1' of
455 455 * Interrupt Command Register Semantics, the semantics of
456 456 * programming the Interrupt Command Register to dispatch an interrupt
457 457 * is simplified. A single MSR write to the 64-bit ICR is required
458 458 * for dispatching an interrupt. Specifically, with the 64-bit MSR
459 459 * interface to ICR, system software is not required to check the
460 460 * status of the delivery status bit prior to writing to the ICR
461 461 * to send an IPI. With the removal of the Delivery Status bit,
462 462 * system software no longer has a reason to read the ICR. It remains
463 463 * readable only to aid in debugging.
464 464 */
465 465 #ifdef DEBUG
466 466 APIC_AV_PENDING_SET();
467 467 #else
468 468 if (apic_mode == LOCAL_APIC) {
469 469 APIC_AV_PENDING_SET();
470 470 }
471 471 #endif /* DEBUG */
472 472
473 473 /* for integrated - make sure there is one INIT IPI in buffer */
474 474 /* for external - it will wake up the cpu */
475 475 apic_reg_ops->apic_write_int_cmd(apicid, AV_ASSERT | AV_RESET);
476 476
477 477 /* If only 1 CPU is installed, PENDING bit will not go low */
478 478 for (loop_count = apic_sipi_max_loop_count; loop_count; loop_count--) {
479 479 if (apic_mode == LOCAL_APIC &&
480 480 apic_reg_ops->apic_read(APIC_INT_CMD1) & AV_PENDING)
481 481 apic_ret();
482 482 else
483 483 break;
484 484 }
485 485
486 486 apic_reg_ops->apic_write_int_cmd(apicid, AV_DEASSERT | AV_RESET);
487 487 drv_usecwait(20000); /* 20 milli sec */
488 488
489 489 if (apic_cpus[cpun].aci_local_ver >= APIC_INTEGRATED_VERS) {
490 490 /* integrated apic */
491 491
492 492 vector = (rm_platter_pa >> MMU_PAGESHIFT) &
493 493 (APIC_VECTOR_MASK | APIC_IPL_MASK);
494 494
495 495 /* to offset the INIT IPI queue up in the buffer */
496 496 apic_reg_ops->apic_write_int_cmd(apicid, vector | AV_STARTUP);
497 497 drv_usecwait(200); /* 20 micro sec */
498 498
499 499 /*
500 500 * send the second SIPI (Startup IPI) as recommended by Intel
501 501 * software development manual.
502 502 */
503 503 apic_reg_ops->apic_write_int_cmd(apicid, vector | AV_STARTUP);
504 504 drv_usecwait(200); /* 20 micro sec */
505 505 }
506 506
507 507 intr_restore(iflag);
508 508 }
509 509
510 510 /*ARGSUSED1*/
511 511 int
512 512 apic_cpu_start(processorid_t cpun, caddr_t arg)
513 513 {
514 514 ASSERT(MUTEX_HELD(&cpu_lock));
515 515
516 516 if (!apic_cpu_in_range(cpun)) {
517 517 return (EINVAL);
518 518 }
519 519
520 520 /*
521 521 * Switch to apic_common_send_ipi for safety during starting other CPUs.
522 522 */
523 523 if (apic_mode == LOCAL_X2APIC) {
524 524 apic_switch_ipi_callback(B_TRUE);
525 525 }
526 526
527 527 apic_cmos_ssb_set = 1;
528 528 apic_cpu_send_SIPI(cpun, B_TRUE);
529 529
530 530 return (0);
531 531 }
532 532
533 533 /*
534 534 * Put CPU into halted state with interrupts disabled.
535 535 */
536 536 /*ARGSUSED1*/
537 537 int
538 538 apic_cpu_stop(processorid_t cpun, caddr_t arg)
539 539 {
540 540 int rc;
541 541 cpu_t *cp;
542 542 extern cpuset_t cpu_ready_set;
543 543 extern void cpu_idle_intercept_cpu(cpu_t *cp);
544 544
545 545 ASSERT(MUTEX_HELD(&cpu_lock));
546 546
547 547 if (!apic_cpu_in_range(cpun)) {
548 548 return (EINVAL);
549 549 }
550 550 if (apic_cpus[cpun].aci_local_ver < APIC_INTEGRATED_VERS) {
551 551 return (ENOTSUP);
552 552 }
553 553
554 554 cp = cpu_get(cpun);
555 555 ASSERT(cp != NULL);
556 556 ASSERT((cp->cpu_flags & CPU_OFFLINE) != 0);
557 557 ASSERT((cp->cpu_flags & CPU_QUIESCED) != 0);
558 558 ASSERT((cp->cpu_flags & CPU_ENABLE) == 0);
559 559
560 560 /* Clear CPU_READY flag to disable cross calls. */
561 561 cp->cpu_flags &= ~CPU_READY;
562 562 CPUSET_ATOMIC_DEL(cpu_ready_set, cpun);
563 563 rc = xc_flush_cpu(cp);
564 564 if (rc != 0) {
565 565 CPUSET_ATOMIC_ADD(cpu_ready_set, cpun);
566 566 cp->cpu_flags |= CPU_READY;
567 567 return (rc);
568 568 }
569 569
570 570 /* Intercept target CPU at a safe point before powering it off. */
571 571 cpu_idle_intercept_cpu(cp);
572 572
573 573 apic_cpu_send_SIPI(cpun, B_FALSE);
574 574 cp->cpu_flags &= ~CPU_RUNNING;
575 575
576 576 return (0);
577 577 }
578 578
579 579 int
580 580 apic_cpu_ops(psm_cpu_request_t *reqp)
581 581 {
582 582 if (reqp == NULL) {
583 583 return (EINVAL);
584 584 }
585 585
586 586 switch (reqp->pcr_cmd) {
587 587 case PSM_CPU_ADD:
588 588 return (apic_cpu_add(reqp));
589 589
590 590 case PSM_CPU_REMOVE:
591 591 return (apic_cpu_remove(reqp));
592 592
593 593 case PSM_CPU_STOP:
594 594 return (apic_cpu_stop(reqp->req.cpu_stop.cpuid,
595 595 reqp->req.cpu_stop.ctx));
596 596
597 597 default:
598 598 return (ENOTSUP);
599 599 }
600 600 }
601 601
602 602 #ifdef DEBUG
603 603 int apic_break_on_cpu = 9;
604 604 int apic_stretch_interrupts = 0;
605 605 int apic_stretch_ISR = 1 << 3; /* IPL of 3 matches nothing now */
606 606 #endif /* DEBUG */
607 607
608 608 /*
609 609 * generates an interprocessor interrupt to another CPU. Any changes made to
610 610 * this routine must be accompanied by similar changes to
611 611 * apic_common_send_ipi().
612 612 */
613 613 void
614 614 apic_send_ipi(int cpun, int ipl)
615 615 {
616 616 int vector;
617 617 ulong_t flag;
618 618
619 619 vector = apic_resv_vector[ipl];
620 620
621 621 ASSERT((vector >= APIC_BASE_VECT) && (vector <= APIC_SPUR_INTR));
622 622
623 623 flag = intr_clear();
624 624
625 625 APIC_AV_PENDING_SET();
626 626
627 627 apic_reg_ops->apic_write_int_cmd(apic_cpus[cpun].aci_local_id,
628 628 vector);
629 629
630 630 intr_restore(flag);
631 631 }
632 632
633 633
634 634 /*ARGSUSED*/
635 635 void
636 636 apic_set_idlecpu(processorid_t cpun)
637 637 {
638 638 }
639 639
640 640 /*ARGSUSED*/
641 641 void
642 642 apic_unset_idlecpu(processorid_t cpun)
643 643 {
644 644 }
645 645
646 646
647 647 void
648 648 apic_ret()
649 649 {
650 650 }
651 651
652 652 /*
653 653 * If apic_coarse_time == 1, then apic_gettime() is used instead of
654 654 * apic_gethrtime(). This is used for performance instead of accuracy.
655 655 */
656 656
657 657 hrtime_t
658 658 apic_gettime()
659 659 {
660 660 int old_hrtime_stamp;
661 661 hrtime_t temp;
662 662
663 663 /*
664 664 * In one-shot mode, we do not keep time, so if anyone
665 665 * calls psm_gettime() directly, we vector over to
666 666 * gethrtime().
667 667 * one-shot mode MUST NOT be enabled if this psm is the source of
668 668 * hrtime.
669 669 */
670 670
671 671 if (apic_oneshot)
672 672 return (gethrtime());
673 673
674 674
675 675 gettime_again:
676 676 while ((old_hrtime_stamp = apic_hrtime_stamp) & 1)
677 677 apic_ret();
678 678
679 679 temp = apic_nsec_since_boot;
680 680
681 681 if (apic_hrtime_stamp != old_hrtime_stamp) { /* got an interrupt */
682 682 goto gettime_again;
683 683 }
684 684 return (temp);
685 685 }
686 686
687 687 /*
688 688 * Here we return the number of nanoseconds since booting. Note every
689 689 * clock interrupt increments apic_nsec_since_boot by the appropriate
690 690 * amount.
691 691 */
692 692 hrtime_t
693 693 apic_gethrtime(void)
694 694 {
695 695 int curr_timeval, countval, elapsed_ticks;
696 696 int old_hrtime_stamp, status;
697 697 hrtime_t temp;
698 698 uint32_t cpun;
699 699 ulong_t oflags;
700 700
701 701 /*
702 702 * In one-shot mode, we do not keep time, so if anyone
703 703 * calls psm_gethrtime() directly, we vector over to
704 704 * gethrtime().
705 705 * one-shot mode MUST NOT be enabled if this psm is the source of
706 706 * hrtime.
707 707 */
708 708
709 709 if (apic_oneshot)
710 710 return (gethrtime());
711 711
712 712 oflags = intr_clear(); /* prevent migration */
713 713
714 714 cpun = apic_reg_ops->apic_read(APIC_LID_REG);
715 715 if (apic_mode == LOCAL_APIC)
716 716 cpun >>= APIC_ID_BIT_OFFSET;
717 717
718 718 lock_set(&apic_gethrtime_lock);
719 719
720 720 gethrtime_again:
721 721 while ((old_hrtime_stamp = apic_hrtime_stamp) & 1)
722 722 apic_ret();
723 723
724 724 /*
725 725 * Check to see which CPU we are on. Note the time is kept on
726 726 * the local APIC of CPU 0. If on CPU 0, simply read the current
727 727 * counter. If on another CPU, issue a remote read command to CPU 0.
728 728 */
729 729 if (cpun == apic_cpus[0].aci_local_id) {
730 730 countval = apic_reg_ops->apic_read(APIC_CURR_COUNT);
731 731 } else {
732 732 #ifdef DEBUG
733 733 APIC_AV_PENDING_SET();
734 734 #else
735 735 if (apic_mode == LOCAL_APIC)
736 736 APIC_AV_PENDING_SET();
737 737 #endif /* DEBUG */
738 738
739 739 apic_reg_ops->apic_write_int_cmd(
740 740 apic_cpus[0].aci_local_id, APIC_CURR_ADD | AV_REMOTE);
741 741
742 742 while ((status = apic_reg_ops->apic_read(APIC_INT_CMD1))
743 743 & AV_READ_PENDING) {
744 744 apic_ret();
745 745 }
746 746
747 747 if (status & AV_REMOTE_STATUS) /* 1 = valid */
748 748 countval = apic_reg_ops->apic_read(APIC_REMOTE_READ);
749 749 else { /* 0 = invalid */
750 750 apic_remote_hrterr++;
751 751 /*
752 752 * return last hrtime right now, will need more
753 753 * testing if change to retry
754 754 */
755 755 temp = apic_last_hrtime;
756 756
757 757 lock_clear(&apic_gethrtime_lock);
758 758
759 759 intr_restore(oflags);
760 760
761 761 return (temp);
762 762 }
763 763 }
764 764 if (countval > last_count_read)
765 765 countval = 0;
766 766 else
767 767 last_count_read = countval;
768 768
769 769 elapsed_ticks = apic_hertz_count - countval;
770 770
771 771 curr_timeval = APIC_TICKS_TO_NSECS(elapsed_ticks);
772 772 temp = apic_nsec_since_boot + curr_timeval;
773 773
774 774 if (apic_hrtime_stamp != old_hrtime_stamp) { /* got an interrupt */
775 775 /* we might have clobbered last_count_read. Restore it */
776 776 last_count_read = apic_hertz_count;
777 777 goto gethrtime_again;
778 778 }
779 779
780 780 if (temp < apic_last_hrtime) {
781 781 /* return last hrtime if error occurs */
782 782 apic_hrtime_error++;
783 783 temp = apic_last_hrtime;
784 784 }
785 785 else
786 786 apic_last_hrtime = temp;
787 787
788 788 lock_clear(&apic_gethrtime_lock);
789 789 intr_restore(oflags);
790 790
791 791 return (temp);
792 792 }
793 793
794 794 /* apic NMI handler */
795 795 /*ARGSUSED*/
796 796 void
797 797 apic_nmi_intr(caddr_t arg, struct regs *rp)
798 798 {
799 799 if (apic_shutdown_processors) {
800 800 apic_disable_local_apic();
801 801 return;
802 802 }
803 803
804 804 apic_error |= APIC_ERR_NMI;
805 805
806 806 if (!lock_try(&apic_nmi_lock))
807 807 return;
808 808 apic_num_nmis++;
809 809
810 810 if (apic_kmdb_on_nmi && psm_debugger()) {
811 811 debug_enter("NMI received: entering kmdb\n");
812 812 } else if (apic_panic_on_nmi) {
813 813 /* Keep panic from entering kmdb. */
814 814 nopanicdebug = 1;
815 815 panic("NMI received\n");
816 816 } else {
817 817 /*
818 818 * prom_printf is the best shot we have of something which is
819 819 * problem free from high level/NMI type of interrupts
820 820 */
821 821 prom_printf("NMI received\n");
822 822 }
823 823
824 824 lock_clear(&apic_nmi_lock);
825 825 }
826 826
827 827 processorid_t
828 828 apic_get_next_processorid(processorid_t cpu_id)
829 829 {
830 830
831 831 int i;
832 832
833 833 if (cpu_id == -1)
834 834 return ((processorid_t)0);
835 835
836 836 for (i = cpu_id + 1; i < NCPU; i++) {
837 837 if (apic_cpu_in_range(i))
838 838 return (i);
839 839 }
840 840
841 841 return ((processorid_t)-1);
842 842 }
843 843
844 844 int
845 845 apic_cpu_add(psm_cpu_request_t *reqp)
846 846 {
847 847 int i, rv = 0;
848 848 ulong_t iflag;
849 849 boolean_t first = B_TRUE;
850 850 uchar_t localver;
851 851 uint32_t localid, procid;
852 852 processorid_t cpuid = (processorid_t)-1;
853 853 mach_cpu_add_arg_t *ap;
854 854
855 855 ASSERT(reqp != NULL);
856 856 reqp->req.cpu_add.cpuid = (processorid_t)-1;
857 857
858 858 /* Check whether CPU hotplug is supported. */
859 859 if (!plat_dr_support_cpu() || apic_max_nproc == -1) {
860 860 return (ENOTSUP);
861 861 }
862 862
863 863 ap = (mach_cpu_add_arg_t *)reqp->req.cpu_add.argp;
864 864 switch (ap->type) {
865 865 case MACH_CPU_ARG_LOCAL_APIC:
866 866 localid = ap->arg.apic.apic_id;
867 867 procid = ap->arg.apic.proc_id;
868 868 if (localid >= 255 || procid > 255) {
869 869 cmn_err(CE_WARN,
870 870 "!apic: apicid(%u) or procid(%u) is invalid.",
871 871 localid, procid);
872 872 return (EINVAL);
873 873 }
874 874 break;
875 875
876 876 case MACH_CPU_ARG_LOCAL_X2APIC:
877 877 localid = ap->arg.apic.apic_id;
878 878 procid = ap->arg.apic.proc_id;
879 879 if (localid >= UINT32_MAX) {
880 880 cmn_err(CE_WARN,
881 881 "!apic: x2apicid(%u) is invalid.", localid);
882 882 return (EINVAL);
883 883 } else if (localid >= 255 && apic_mode == LOCAL_APIC) {
884 884 cmn_err(CE_WARN, "!apic: system is in APIC mode, "
885 885 "can't support x2APIC processor.");
886 886 return (ENOTSUP);
887 887 }
888 888 break;
889 889
890 890 default:
891 891 cmn_err(CE_WARN,
892 892 "!apic: unknown argument type %d to apic_cpu_add().",
893 893 ap->type);
894 894 return (EINVAL);
895 895 }
896 896
897 897 /* Use apic_ioapic_lock to sync with apic_get_next_bind_cpu. */
898 898 iflag = intr_clear();
899 899 lock_set(&apic_ioapic_lock);
900 900
901 901 /* Check whether local APIC id already exists. */
902 902 for (i = 0; i < apic_nproc; i++) {
903 903 if (!CPU_IN_SET(apic_cpumask, i))
904 904 continue;
905 905 if (apic_cpus[i].aci_local_id == localid) {
906 906 lock_clear(&apic_ioapic_lock);
907 907 intr_restore(iflag);
908 908 cmn_err(CE_WARN,
909 909 "!apic: local apic id %u already exists.",
910 910 localid);
911 911 return (EEXIST);
912 912 } else if (apic_cpus[i].aci_processor_id == procid) {
913 913 lock_clear(&apic_ioapic_lock);
914 914 intr_restore(iflag);
915 915 cmn_err(CE_WARN,
916 916 "!apic: processor id %u already exists.",
917 917 (int)procid);
918 918 return (EEXIST);
919 919 }
920 920
921 921 /*
922 922 * There's no local APIC version number available in MADT table,
923 923 * so assume that all CPUs are homogeneous and use local APIC
924 924 * version number of the first existing CPU.
925 925 */
926 926 if (first) {
927 927 first = B_FALSE;
928 928 localver = apic_cpus[i].aci_local_ver;
929 929 }
930 930 }
931 931 ASSERT(first == B_FALSE);
932 932
933 933 /*
934 934 * Try to assign the same cpuid if APIC id exists in the dirty cache.
935 935 */
936 936 for (i = 0; i < apic_max_nproc; i++) {
937 937 if (CPU_IN_SET(apic_cpumask, i)) {
938 938 ASSERT((apic_cpus[i].aci_status & APIC_CPU_FREE) == 0);
939 939 continue;
940 940 }
941 941 ASSERT(apic_cpus[i].aci_status & APIC_CPU_FREE);
942 942 if ((apic_cpus[i].aci_status & APIC_CPU_DIRTY) &&
943 943 apic_cpus[i].aci_local_id == localid &&
944 944 apic_cpus[i].aci_processor_id == procid) {
945 945 cpuid = i;
946 946 break;
947 947 }
948 948 }
949 949
950 950 /* Avoid the dirty cache and allocate fresh slot if possible. */
951 951 if (cpuid == (processorid_t)-1) {
952 952 for (i = 0; i < apic_max_nproc; i++) {
953 953 if ((apic_cpus[i].aci_status & APIC_CPU_FREE) &&
954 954 (apic_cpus[i].aci_status & APIC_CPU_DIRTY) == 0) {
955 955 cpuid = i;
956 956 break;
957 957 }
958 958 }
959 959 }
960 960
961 961 /* Try to find any free slot as last resort. */
962 962 if (cpuid == (processorid_t)-1) {
963 963 for (i = 0; i < apic_max_nproc; i++) {
964 964 if (apic_cpus[i].aci_status & APIC_CPU_FREE) {
965 965 cpuid = i;
966 966 break;
967 967 }
968 968 }
969 969 }
970 970
971 971 if (cpuid == (processorid_t)-1) {
972 972 lock_clear(&apic_ioapic_lock);
973 973 intr_restore(iflag);
974 974 cmn_err(CE_NOTE,
975 975 "!apic: failed to allocate cpu id for processor %u.",
976 976 procid);
977 977 rv = EAGAIN;
978 978 } else if (ACPI_FAILURE(acpica_map_cpu(cpuid, procid))) {
979 979 lock_clear(&apic_ioapic_lock);
980 980 intr_restore(iflag);
981 981 cmn_err(CE_NOTE,
982 982 "!apic: failed to build mapping for processor %u.",
983 983 procid);
984 984 rv = EBUSY;
985 985 } else {
986 986 ASSERT(cpuid >= 0 && cpuid < NCPU);
987 987 ASSERT(cpuid < apic_max_nproc && cpuid < max_ncpus);
988 988 bzero(&apic_cpus[cpuid], sizeof (apic_cpus[0]));
989 989 apic_cpus[cpuid].aci_processor_id = procid;
990 990 apic_cpus[cpuid].aci_local_id = localid;
991 991 apic_cpus[cpuid].aci_local_ver = localver;
992 992 CPUSET_ATOMIC_ADD(apic_cpumask, cpuid);
993 993 if (cpuid >= apic_nproc) {
994 994 apic_nproc = cpuid + 1;
995 995 }
996 996 lock_clear(&apic_ioapic_lock);
997 997 intr_restore(iflag);
998 998 reqp->req.cpu_add.cpuid = cpuid;
999 999 }
1000 1000
1001 1001 return (rv);
1002 1002 }
1003 1003
1004 1004 int
1005 1005 apic_cpu_remove(psm_cpu_request_t *reqp)
1006 1006 {
1007 1007 int i;
1008 1008 ulong_t iflag;
1009 1009 processorid_t cpuid;
1010 1010
1011 1011 /* Check whether CPU hotplug is supported. */
1012 1012 if (!plat_dr_support_cpu() || apic_max_nproc == -1) {
1013 1013 return (ENOTSUP);
1014 1014 }
1015 1015
1016 1016 cpuid = reqp->req.cpu_remove.cpuid;
1017 1017
1018 1018 /* Use apic_ioapic_lock to sync with apic_get_next_bind_cpu. */
1019 1019 iflag = intr_clear();
1020 1020 lock_set(&apic_ioapic_lock);
1021 1021
1022 1022 if (!apic_cpu_in_range(cpuid)) {
1023 1023 lock_clear(&apic_ioapic_lock);
1024 1024 intr_restore(iflag);
1025 1025 cmn_err(CE_WARN,
1026 1026 "!apic: cpuid %d doesn't exist in apic_cpus array.",
1027 1027 cpuid);
1028 1028 return (ENODEV);
1029 1029 }
1030 1030 ASSERT((apic_cpus[cpuid].aci_status & APIC_CPU_FREE) == 0);
1031 1031
1032 1032 if (ACPI_FAILURE(acpica_unmap_cpu(cpuid))) {
1033 1033 lock_clear(&apic_ioapic_lock);
1034 1034 intr_restore(iflag);
1035 1035 return (ENOENT);
1036 1036 }
1037 1037
1038 1038 if (cpuid == apic_nproc - 1) {
1039 1039 /*
1040 1040 * We are removing the highest numbered cpuid so we need to
1041 1041 * find the next highest cpuid as the new value for apic_nproc.
1042 1042 */
1043 1043 for (i = apic_nproc; i > 0; i--) {
1044 1044 if (CPU_IN_SET(apic_cpumask, i - 1)) {
1045 1045 apic_nproc = i;
1046 1046 break;
1047 1047 }
1048 1048 }
1049 1049 /* at least one CPU left */
1050 1050 ASSERT(i > 0);
1051 1051 }
1052 1052 CPUSET_ATOMIC_DEL(apic_cpumask, cpuid);
1053 1053 /* mark slot as free and keep it in the dirty cache */
1054 1054 apic_cpus[cpuid].aci_status = APIC_CPU_FREE | APIC_CPU_DIRTY;
1055 1055
1056 1056 lock_clear(&apic_ioapic_lock);
1057 1057 intr_restore(iflag);
1058 1058
1059 1059 return (0);
1060 1060 }
1061 1061
1062 1062 /*
1063 1063 * Return the number of APIC clock ticks elapsed for 8245 to decrement
1064 1064 * (APIC_TIME_COUNT + pit_ticks_adj) ticks.
1065 1065 */
1066 1066 uint_t
1067 1067 apic_calibrate(volatile uint32_t *addr, uint16_t *pit_ticks_adj)
1068 1068 {
1069 1069 uint8_t pit_tick_lo;
1070 1070 uint16_t pit_tick, target_pit_tick;
1071 1071 uint32_t start_apic_tick, end_apic_tick;
1072 1072 ulong_t iflag;
1073 1073 uint32_t reg;
1074 1074
1075 1075 reg = addr + APIC_CURR_COUNT - apicadr;
1076 1076
1077 1077 iflag = intr_clear();
1078 1078
1079 1079 do {
1080 1080 pit_tick_lo = inb(PITCTR0_PORT);
1081 1081 pit_tick = (inb(PITCTR0_PORT) << 8) | pit_tick_lo;
1082 1082 } while (pit_tick < APIC_TIME_MIN ||
1083 1083 pit_tick_lo <= APIC_LB_MIN || pit_tick_lo >= APIC_LB_MAX);
1084 1084
1085 1085 /*
1086 1086 * Wait for the 8254 to decrement by 5 ticks to ensure
1087 1087 * we didn't start in the middle of a tick.
1088 1088 * Compare with 0x10 for the wrap around case.
1089 1089 */
1090 1090 target_pit_tick = pit_tick - 5;
1091 1091 do {
1092 1092 pit_tick_lo = inb(PITCTR0_PORT);
1093 1093 pit_tick = (inb(PITCTR0_PORT) << 8) | pit_tick_lo;
1094 1094 } while (pit_tick > target_pit_tick || pit_tick_lo < 0x10);
1095 1095
1096 1096 start_apic_tick = apic_reg_ops->apic_read(reg);
1097 1097
1098 1098 /*
1099 1099 * Wait for the 8254 to decrement by
1100 1100 * (APIC_TIME_COUNT + pit_ticks_adj) ticks
1101 1101 */
1102 1102 target_pit_tick = pit_tick - APIC_TIME_COUNT;
1103 1103 do {
1104 1104 pit_tick_lo = inb(PITCTR0_PORT);
1105 1105 pit_tick = (inb(PITCTR0_PORT) << 8) | pit_tick_lo;
1106 1106 } while (pit_tick > target_pit_tick || pit_tick_lo < 0x10);
1107 1107
1108 1108 end_apic_tick = apic_reg_ops->apic_read(reg);
1109 1109
1110 1110 *pit_ticks_adj = target_pit_tick - pit_tick;
1111 1111
1112 1112 intr_restore(iflag);
1113 1113
1114 1114 return (start_apic_tick - end_apic_tick);
1115 1115 }
1116 1116
1117 1117 /*
1118 1118 * Initialise the APIC timer on the local APIC of CPU 0 to the desired
1119 1119 * frequency. Note at this stage in the boot sequence, the boot processor
1120 1120 * is the only active processor.
1121 1121 * hertz value of 0 indicates a one-shot mode request. In this case
1122 1122 * the function returns the resolution (in nanoseconds) for the hardware
1123 1123 * timer interrupt. If one-shot mode capability is not available,
1124 1124 * the return value will be 0. apic_enable_oneshot is a global switch
1125 1125 * for disabling the functionality.
1126 1126 * A non-zero positive value for hertz indicates a periodic mode request.
1127 1127 * In this case the hardware will be programmed to generate clock interrupts
1128 1128 * at hertz frequency and returns the resolution of interrupts in
1129 1129 * nanosecond.
1130 1130 */
1131 1131
1132 1132 int
1133 1133 apic_clkinit(int hertz)
1134 1134 {
1135 1135 int ret;
1136 1136
1137 1137 apic_int_busy_mark = (apic_int_busy_mark *
1138 1138 apic_sample_factor_redistribution) / 100;
1139 1139 apic_int_free_mark = (apic_int_free_mark *
1140 1140 apic_sample_factor_redistribution) / 100;
1141 1141 apic_diff_for_redistribution = (apic_diff_for_redistribution *
1142 1142 apic_sample_factor_redistribution) / 100;
1143 1143
1144 1144 ret = apic_timer_init(hertz);
1145 1145 return (ret);
1146 1146
1147 1147 }
1148 1148
1149 1149 /*
1150 1150 * apic_preshutdown:
1151 1151 * Called early in shutdown whilst we can still access filesystems to do
1152 1152 * things like loading modules which will be required to complete shutdown
1153 1153 * after filesystems are all unmounted.
1154 1154 */
1155 1155 void
1156 1156 apic_preshutdown(int cmd, int fcn)
1157 1157 {
1158 1158 APIC_VERBOSE_POWEROFF(("apic_preshutdown(%d,%d); m=%d a=%d\n",
1159 1159 cmd, fcn, apic_poweroff_method, apic_enable_acpi));
1160 1160 }
1161 1161
1162 1162 void
1163 1163 apic_shutdown(int cmd, int fcn)
1164 1164 {
1165 1165 int restarts, attempts;
1166 1166 int i;
1167 1167 uchar_t byte;
1168 1168 ulong_t iflag;
1169 1169
1170 1170 hpet_acpi_fini();
1171 1171
1172 1172 /* Send NMI to all CPUs except self to do per processor shutdown */
1173 1173 iflag = intr_clear();
1174 1174 #ifdef DEBUG
1175 1175 APIC_AV_PENDING_SET();
1176 1176 #else
1177 1177 if (apic_mode == LOCAL_APIC)
1178 1178 APIC_AV_PENDING_SET();
1179 1179 #endif /* DEBUG */
1180 1180 apic_shutdown_processors = 1;
1181 1181 apic_reg_ops->apic_write(APIC_INT_CMD1,
1182 1182 AV_NMI | AV_LEVEL | AV_SH_ALL_EXCSELF);
1183 1183
1184 1184 /* restore cmos shutdown byte before reboot */
1185 1185 if (apic_cmos_ssb_set) {
1186 1186 outb(CMOS_ADDR, SSB);
1187 1187 outb(CMOS_DATA, 0);
1188 1188 }
1189 1189
1190 1190 ioapic_disable_redirection();
1191 1191
1192 1192 /* disable apic mode if imcr present */
1193 1193 if (apic_imcrp) {
1194 1194 outb(APIC_IMCR_P1, (uchar_t)APIC_IMCR_SELECT);
1195 1195 outb(APIC_IMCR_P2, (uchar_t)APIC_IMCR_PIC);
1196 1196 }
1197 1197
1198 1198 apic_disable_local_apic();
1199 1199
1200 1200 intr_restore(iflag);
1201 1201
1202 1202 /* remainder of function is for shutdown cases only */
1203 1203 if (cmd != A_SHUTDOWN)
1204 1204 return;
1205 1205
1206 1206 /*
1207 1207 * Switch system back into Legacy-Mode if using ACPI and
1208 1208 * not powering-off. Some BIOSes need to remain in ACPI-mode
1209 1209 * for power-off to succeed (Dell Dimension 4600)
1210 1210 * Do not disable ACPI while doing fastreboot
1211 1211 */
1212 1212 if (apic_enable_acpi && fcn != AD_POWEROFF && fcn != AD_FASTREBOOT)
1213 1213 (void) AcpiDisable();
1214 1214
1215 1215 if (fcn == AD_FASTREBOOT) {
1216 1216 apic_reg_ops->apic_write(APIC_INT_CMD1,
1217 1217 AV_ASSERT | AV_RESET | AV_SH_ALL_EXCSELF);
1218 1218 }
1219 1219
1220 1220 /* remainder of function is for shutdown+poweroff case only */
1221 1221 if (fcn != AD_POWEROFF)
1222 1222 return;
1223 1223
1224 1224 switch (apic_poweroff_method) {
1225 1225 case APIC_POWEROFF_VIA_RTC:
1226 1226
1227 1227 /* select the extended NVRAM bank in the RTC */
1228 1228 outb(CMOS_ADDR, RTC_REGA);
1229 1229 byte = inb(CMOS_DATA);
1230 1230 outb(CMOS_DATA, (byte | EXT_BANK));
1231 1231
1232 1232 outb(CMOS_ADDR, PFR_REG);
1233 1233
1234 1234 /* for Predator must toggle the PAB bit */
1235 1235 byte = inb(CMOS_DATA);
1236 1236
1237 1237 /*
1238 1238 * clear power active bar, wakeup alarm and
1239 1239 * kickstart
1240 1240 */
1241 1241 byte &= ~(PAB_CBIT | WF_FLAG | KS_FLAG);
1242 1242 outb(CMOS_DATA, byte);
1243 1243
1244 1244 /* delay before next write */
1245 1245 drv_usecwait(1000);
1246 1246
1247 1247 /* for S40 the following would suffice */
1248 1248 byte = inb(CMOS_DATA);
1249 1249
1250 1250 /* power active bar control bit */
1251 1251 byte |= PAB_CBIT;
1252 1252 outb(CMOS_DATA, byte);
1253 1253
1254 1254 break;
1255 1255
1256 1256 case APIC_POWEROFF_VIA_ASPEN_BMC:
1257 1257 restarts = 0;
1258 1258 restart_aspen_bmc:
1259 1259 if (++restarts == 3)
1260 1260 break;
1261 1261 attempts = 0;
1262 1262 do {
1263 1263 byte = inb(MISMIC_FLAG_REGISTER);
1264 1264 byte &= MISMIC_BUSY_MASK;
1265 1265 if (byte != 0) {
1266 1266 drv_usecwait(1000);
1267 1267 if (attempts >= 3)
1268 1268 goto restart_aspen_bmc;
1269 1269 ++attempts;
1270 1270 }
1271 1271 } while (byte != 0);
1272 1272 outb(MISMIC_CNTL_REGISTER, CC_SMS_GET_STATUS);
1273 1273 byte = inb(MISMIC_FLAG_REGISTER);
1274 1274 byte |= 0x1;
1275 1275 outb(MISMIC_FLAG_REGISTER, byte);
1276 1276 i = 0;
1277 1277 for (; i < (sizeof (aspen_bmc)/sizeof (aspen_bmc[0]));
1278 1278 i++) {
1279 1279 attempts = 0;
1280 1280 do {
1281 1281 byte = inb(MISMIC_FLAG_REGISTER);
1282 1282 byte &= MISMIC_BUSY_MASK;
1283 1283 if (byte != 0) {
1284 1284 drv_usecwait(1000);
1285 1285 if (attempts >= 3)
1286 1286 goto restart_aspen_bmc;
1287 1287 ++attempts;
1288 1288 }
1289 1289 } while (byte != 0);
1290 1290 outb(MISMIC_CNTL_REGISTER, aspen_bmc[i].cntl);
1291 1291 outb(MISMIC_DATA_REGISTER, aspen_bmc[i].data);
1292 1292 byte = inb(MISMIC_FLAG_REGISTER);
1293 1293 byte |= 0x1;
1294 1294 outb(MISMIC_FLAG_REGISTER, byte);
1295 1295 }
1296 1296 break;
1297 1297
1298 1298 case APIC_POWEROFF_VIA_SITKA_BMC:
1299 1299 restarts = 0;
1300 1300 restart_sitka_bmc:
1301 1301 if (++restarts == 3)
1302 1302 break;
1303 1303 attempts = 0;
1304 1304 do {
1305 1305 byte = inb(SMS_STATUS_REGISTER);
1306 1306 byte &= SMS_STATE_MASK;
1307 1307 if ((byte == SMS_READ_STATE) ||
1308 1308 (byte == SMS_WRITE_STATE)) {
1309 1309 drv_usecwait(1000);
1310 1310 if (attempts >= 3)
1311 1311 goto restart_sitka_bmc;
1312 1312 ++attempts;
1313 1313 }
1314 1314 } while ((byte == SMS_READ_STATE) ||
1315 1315 (byte == SMS_WRITE_STATE));
1316 1316 outb(SMS_COMMAND_REGISTER, SMS_GET_STATUS);
1317 1317 i = 0;
1318 1318 for (; i < (sizeof (sitka_bmc)/sizeof (sitka_bmc[0]));
1319 1319 i++) {
1320 1320 attempts = 0;
1321 1321 do {
1322 1322 byte = inb(SMS_STATUS_REGISTER);
1323 1323 byte &= SMS_IBF_MASK;
1324 1324 if (byte != 0) {
1325 1325 drv_usecwait(1000);
1326 1326 if (attempts >= 3)
1327 1327 goto restart_sitka_bmc;
1328 1328 ++attempts;
1329 1329 }
1330 1330 } while (byte != 0);
1331 1331 outb(sitka_bmc[i].port, sitka_bmc[i].data);
1332 1332 }
1333 1333 break;
1334 1334
1335 1335 case APIC_POWEROFF_NONE:
1336 1336
1337 1337 /* If no APIC direct method, we will try using ACPI */
1338 1338 if (apic_enable_acpi) {
1339 1339 if (acpi_poweroff() == 1)
1340 1340 return;
1341 1341 } else
1342 1342 return;
1343 1343
1344 1344 break;
1345 1345 }
1346 1346 /*
1347 1347 * Wait a limited time here for power to go off.
1348 1348 * If the power does not go off, then there was a
1349 1349 * problem and we should continue to the halt which
1350 1350 * prints a message for the user to press a key to
1351 1351 * reboot.
1352 1352 */
1353 1353 drv_usecwait(7000000); /* wait seven seconds */
1354 1354
1355 1355 }
1356 1356
1357 1357 cyclic_id_t apic_cyclic_id;
1358 1358
1359 1359 /*
1360 1360 * The following functions are in the platform specific file so that they
1361 1361 * can be different functions depending on whether we are running on
1362 1362 * bare metal or a hypervisor.
1363 1363 */
1364 1364
1365 1365 /*
1366 1366 * map an apic for memory-mapped access
1367 1367 */
1368 1368 uint32_t *
1369 1369 mapin_apic(uint32_t addr, size_t len, int flags)
1370 1370 {
1371 1371 return ((void *)psm_map_phys(addr, len, flags));
1372 1372 }
1373 1373
1374 1374 uint32_t *
1375 1375 mapin_ioapic(uint32_t addr, size_t len, int flags)
1376 1376 {
1377 1377 return (mapin_apic(addr, len, flags));
1378 1378 }
1379 1379
1380 1380 /*
1381 1381 * unmap an apic
1382 1382 */
1383 1383 void
1384 1384 mapout_apic(caddr_t addr, size_t len)
1385 1385 {
1386 1386 psm_unmap_phys(addr, len);
1387 1387 }
1388 1388
1389 1389 void
1390 1390 mapout_ioapic(caddr_t addr, size_t len)
1391 1391 {
1392 1392 mapout_apic(addr, len);
1393 1393 }
1394 1394
1395 1395 uint32_t
1396 1396 ioapic_read(int ioapic_ix, uint32_t reg)
1397 1397 {
1398 1398 volatile uint32_t *ioapic;
1399 1399
1400 1400 ioapic = apicioadr[ioapic_ix];
1401 1401 ioapic[APIC_IO_REG] = reg;
1402 1402 return (ioapic[APIC_IO_DATA]);
1403 1403 }
1404 1404
1405 1405 void
1406 1406 ioapic_write(int ioapic_ix, uint32_t reg, uint32_t value)
1407 1407 {
1408 1408 volatile uint32_t *ioapic;
1409 1409
1410 1410 ioapic = apicioadr[ioapic_ix];
1411 1411 ioapic[APIC_IO_REG] = reg;
1412 1412 ioapic[APIC_IO_DATA] = value;
1413 1413 }
1414 1414
1415 1415 void
1416 1416 ioapic_write_eoi(int ioapic_ix, uint32_t value)
1417 1417 {
1418 1418 volatile uint32_t *ioapic;
1419 1419
1420 1420 ioapic = apicioadr[ioapic_ix];
1421 1421 ioapic[APIC_IO_EOI] = value;
1422 1422 }
1423 1423
1424 1424 /*
1425 1425 * Round-robin algorithm to find the next CPU with interrupts enabled.
1426 1426 * It can't share the same static variable apic_next_bind_cpu with
1427 1427 * apic_get_next_bind_cpu(), since that will cause all interrupts to be
1428 1428 * bound to CPU1 at boot time. During boot, only CPU0 is online with
1429 1429 * interrupts enabled when apic_get_next_bind_cpu() and apic_find_cpu()
1430 1430 * are called. However, the pcplusmp driver assumes that there will be
1431 1431 * boot_ncpus CPUs configured eventually so it tries to distribute all
1432 1432 * interrupts among CPU0 - CPU[boot_ncpus - 1]. Thus to prevent all
1433 1433 * interrupts being targetted at CPU1, we need to use a dedicated static
1434 1434 * variable for find_next_cpu() instead of sharing apic_next_bind_cpu.
1435 1435 */
1436 1436
1437 1437 processorid_t
1438 1438 apic_find_cpu(int flag)
1439 1439 {
1440 1440 int i;
1441 1441 static processorid_t acid = 0;
1442 1442
1443 1443 /* Find the first CPU with the passed-in flag set */
1444 1444 for (i = 0; i < apic_nproc; i++) {
1445 1445 if (++acid >= apic_nproc) {
1446 1446 acid = 0;
1447 1447 }
1448 1448 if (apic_cpu_in_range(acid) &&
1449 1449 (apic_cpus[acid].aci_status & flag)) {
1450 1450 break;
1451 1451 }
1452 1452 }
1453 1453
1454 1454 ASSERT((apic_cpus[acid].aci_status & flag) != 0);
1455 1455 return (acid);
1456 1456 }
1457 1457
1458 1458 /*
1459 1459 * Switch between safe and x2APIC IPI sending method.
1460 1460 * CPU may power on in xapic mode or x2apic mode. If CPU needs to send IPI to
1461 1461 * other CPUs before entering x2APIC mode, it still needs to xAPIC method.
1462 1462 * Before sending StartIPI to target CPU, psm_send_ipi will be changed to
1463 1463 * apic_common_send_ipi, which detects current local APIC mode and use right
1464 1464 * method to send IPI. If some CPUs fail to start up, apic_poweron_cnt
1465 1465 * won't return to zero, so apic_common_send_ipi will always be used.
1466 1466 * psm_send_ipi can't be simply changed back to x2apic_send_ipi if some CPUs
1467 1467 * failed to start up because those failed CPUs may recover itself later at
1468 1468 * unpredictable time.
1469 1469 */
1470 1470 void
1471 1471 apic_switch_ipi_callback(boolean_t enter)
1472 1472 {
1473 1473 ulong_t iflag;
1474 1474 struct psm_ops *pops = psmops;
1475 1475
1476 1476 iflag = intr_clear();
1477 1477 lock_set(&apic_mode_switch_lock);
1478 1478 if (enter) {
1479 1479 ASSERT(apic_poweron_cnt >= 0);
1480 1480 if (apic_poweron_cnt == 0) {
1481 1481 pops->psm_send_ipi = apic_common_send_ipi;
1482 1482 send_dirintf = pops->psm_send_ipi;
1483 1483 }
1484 1484 apic_poweron_cnt++;
1485 1485 } else {
1486 1486 ASSERT(apic_poweron_cnt > 0);
1487 1487 apic_poweron_cnt--;
1488 1488 if (apic_poweron_cnt == 0) {
1489 1489 pops->psm_send_ipi = x2apic_send_ipi;
1490 1490 send_dirintf = pops->psm_send_ipi;
1491 1491 }
1492 1492 }
1493 1493 lock_clear(&apic_mode_switch_lock);
1494 1494 intr_restore(iflag);
1495 1495 }
1496 1496
1497 1497 void
1498 1498 apic_intrmap_init(int apic_mode)
1499 1499 {
1500 1500 int suppress_brdcst_eoi = 0;
1501 1501
1502 1502 if (psm_vt_ops != NULL) {
1503 1503 /*
1504 1504 * Since X2APIC requires the use of interrupt remapping
1505 1505 * (though this is not documented explicitly in the Intel
1506 1506 * documentation (yet)), initialize interrupt remapping
1507 1507 * support before initializing the X2APIC unit.
1508 1508 */
1509 1509 if (((apic_intrmap_ops_t *)psm_vt_ops)->
1510 1510 apic_intrmap_init(apic_mode) == DDI_SUCCESS) {
1511 1511
1512 1512 apic_vt_ops = psm_vt_ops;
1513 1513
1514 1514 /*
1515 1515 * We leverage the interrupt remapping engine to
1516 1516 * suppress broadcast EOI; thus we must send the
1517 1517 * directed EOI with the directed-EOI handler.
1518 1518 */
1519 1519 if (apic_directed_EOI_supported() == 0) {
1520 1520 suppress_brdcst_eoi = 1;
1521 1521 }
1522 1522
1523 1523 apic_vt_ops->apic_intrmap_enable(suppress_brdcst_eoi);
1524 1524
1525 1525 if (apic_detect_x2apic()) {
1526 1526 apic_enable_x2apic();
1527 1527 }
1528 1528
1529 1529 if (apic_directed_EOI_supported() == 0) {
1530 1530 apic_set_directed_EOI_handler();
1531 1531 }
1532 1532 }
1533 1533 }
1534 1534 }
1535 1535
1536 1536 /*ARGSUSED*/
1537 1537 static void
1538 1538 apic_record_ioapic_rdt(void *intrmap_private, ioapic_rdt_t *irdt)
1539 1539 {
1540 1540 irdt->ir_hi <<= APIC_ID_BIT_OFFSET;
1541 1541 }
1542 1542
1543 1543 /*ARGSUSED*/
1544 1544 static void
1545 1545 apic_record_msi(void *intrmap_private, msi_regs_t *mregs)
1546 1546 {
1547 1547 mregs->mr_addr = MSI_ADDR_HDR |
1548 1548 (MSI_ADDR_RH_FIXED << MSI_ADDR_RH_SHIFT) |
1549 1549 (MSI_ADDR_DM_PHYSICAL << MSI_ADDR_DM_SHIFT) |
1550 1550 (mregs->mr_addr << MSI_ADDR_DEST_SHIFT);
1551 1551 mregs->mr_data = (MSI_DATA_TM_EDGE << MSI_DATA_TM_SHIFT) |
1552 1552 mregs->mr_data;
1553 1553 }
1554 1554
1555 1555 /*
1556 1556 * Functions from apic_introp.c
1557 1557 *
1558 1558 * Those functions are used by apic_intr_ops().
1559 1559 */
1560 1560
1561 1561 /*
1562 1562 * MSI support flag:
1563 1563 * reflects whether MSI is supported at APIC level
1564 1564 * it can also be patched through /etc/system
1565 1565 *
1566 1566 * 0 = default value - don't know and need to call apic_check_msi_support()
1567 1567 * to find out then set it accordingly
1568 1568 * 1 = supported
1569 1569 * -1 = not supported
1570 1570 */
1571 1571 int apic_support_msi = 0;
1572 1572
1573 1573 /* Multiple vector support for MSI-X */
1574 1574 int apic_msix_enable = 1;
1575 1575
1576 1576 /* Multiple vector support for MSI */
1577 1577 int apic_multi_msi_enable = 1;
1578 1578
1579 1579 /*
1580 1580 * check whether the system supports MSI
1581 1581 *
1582 1582 * If PCI-E capability is found, then this must be a PCI-E system.
1583 1583 * Since MSI is required for PCI-E system, it returns PSM_SUCCESS
1584 1584 * to indicate this system supports MSI.
1585 1585 */
1586 1586 int
1587 1587 apic_check_msi_support()
1588 1588 {
1589 1589 dev_info_t *cdip;
1590 1590 char dev_type[16];
1591 1591 int dev_len;
1592 1592
1593 1593 DDI_INTR_IMPLDBG((CE_CONT, "apic_check_msi_support:\n"));
1594 1594
1595 1595 /*
1596 1596 * check whether the first level children of root_node have
1597 1597 * PCI-E capability
1598 1598 */
1599 1599 for (cdip = ddi_get_child(ddi_root_node()); cdip != NULL;
1600 1600 cdip = ddi_get_next_sibling(cdip)) {
1601 1601
1602 1602 DDI_INTR_IMPLDBG((CE_CONT, "apic_check_msi_support: cdip: 0x%p,"
1603 1603 " driver: %s, binding: %s, nodename: %s\n", (void *)cdip,
1604 1604 ddi_driver_name(cdip), ddi_binding_name(cdip),
1605 1605 ddi_node_name(cdip)));
1606 1606 dev_len = sizeof (dev_type);
1607 1607 if (ddi_getlongprop_buf(DDI_DEV_T_ANY, cdip, DDI_PROP_DONTPASS,
1608 1608 "device_type", (caddr_t)dev_type, &dev_len)
1609 1609 != DDI_PROP_SUCCESS)
1610 1610 continue;
1611 1611 if (strcmp(dev_type, "pciex") == 0)
1612 1612 return (PSM_SUCCESS);
1613 1613 }
1614 1614
1615 1615 /* MSI is not supported on this system */
1616 1616 DDI_INTR_IMPLDBG((CE_CONT, "apic_check_msi_support: no 'pciex' "
1617 1617 "device_type found\n"));
1618 1618 return (PSM_FAILURE);
1619 1619 }
1620 1620
1621 1621 /*
1622 1622 * apic_pci_msi_unconfigure:
1623 1623 *
1624 1624 * This and next two interfaces are copied from pci_intr_lib.c
1625 1625 * Do ensure that these two files stay in sync.
1626 1626 * These needed to be copied over here to avoid a deadlock situation on
1627 1627 * certain mp systems that use MSI interrupts.
1628 1628 *
1629 1629 * IMPORTANT regards next three interfaces:
1630 1630 * i) are called only for MSI/X interrupts.
1631 1631 * ii) called with interrupts disabled, and must not block
1632 1632 */
1633 1633 void
1634 1634 apic_pci_msi_unconfigure(dev_info_t *rdip, int type, int inum)
1635 1635 {
1636 1636 ushort_t msi_ctrl;
1637 1637 int cap_ptr = i_ddi_get_msi_msix_cap_ptr(rdip);
1638 1638 ddi_acc_handle_t handle = i_ddi_get_pci_config_handle(rdip);
1639 1639
1640 1640 ASSERT((handle != NULL) && (cap_ptr != 0));
1641 1641
1642 1642 if (type == DDI_INTR_TYPE_MSI) {
1643 1643 msi_ctrl = pci_config_get16(handle, cap_ptr + PCI_MSI_CTRL);
1644 1644 msi_ctrl &= (~PCI_MSI_MME_MASK);
1645 1645 pci_config_put16(handle, cap_ptr + PCI_MSI_CTRL, msi_ctrl);
1646 1646 pci_config_put32(handle, cap_ptr + PCI_MSI_ADDR_OFFSET, 0);
1647 1647
1648 1648 if (msi_ctrl & PCI_MSI_64BIT_MASK) {
1649 1649 pci_config_put16(handle,
1650 1650 cap_ptr + PCI_MSI_64BIT_DATA, 0);
1651 1651 pci_config_put32(handle,
1652 1652 cap_ptr + PCI_MSI_ADDR_OFFSET + 4, 0);
1653 1653 } else {
1654 1654 pci_config_put16(handle,
1655 1655 cap_ptr + PCI_MSI_32BIT_DATA, 0);
1656 1656 }
1657 1657
1658 1658 } else if (type == DDI_INTR_TYPE_MSIX) {
1659 1659 uintptr_t off;
1660 1660 uint32_t mask;
1661 1661 ddi_intr_msix_t *msix_p = i_ddi_get_msix(rdip);
1662 1662
1663 1663 ASSERT(msix_p != NULL);
1664 1664
1665 1665 /* Offset into "inum"th entry in the MSI-X table & mask it */
1666 1666 off = (uintptr_t)msix_p->msix_tbl_addr + (inum *
1667 1667 PCI_MSIX_VECTOR_SIZE) + PCI_MSIX_VECTOR_CTRL_OFFSET;
1668 1668
1669 1669 mask = ddi_get32(msix_p->msix_tbl_hdl, (uint32_t *)off);
1670 1670
1671 1671 ddi_put32(msix_p->msix_tbl_hdl, (uint32_t *)off, (mask | 1));
1672 1672
1673 1673 /* Offset into the "inum"th entry in the MSI-X table */
1674 1674 off = (uintptr_t)msix_p->msix_tbl_addr +
1675 1675 (inum * PCI_MSIX_VECTOR_SIZE);
1676 1676
1677 1677 /* Reset the "data" and "addr" bits */
1678 1678 ddi_put32(msix_p->msix_tbl_hdl,
1679 1679 (uint32_t *)(off + PCI_MSIX_DATA_OFFSET), 0);
1680 1680 ddi_put64(msix_p->msix_tbl_hdl, (uint64_t *)off, 0);
1681 1681 }
1682 1682 }
1683 1683
1684 1684 /*
1685 1685 * apic_pci_msi_disable_mode:
1686 1686 */
1687 1687 void
1688 1688 apic_pci_msi_disable_mode(dev_info_t *rdip, int type)
1689 1689 {
1690 1690 ushort_t msi_ctrl;
1691 1691 int cap_ptr = i_ddi_get_msi_msix_cap_ptr(rdip);
1692 1692 ddi_acc_handle_t handle = i_ddi_get_pci_config_handle(rdip);
1693 1693
1694 1694 ASSERT((handle != NULL) && (cap_ptr != 0));
1695 1695
1696 1696 if (type == DDI_INTR_TYPE_MSI) {
1697 1697 msi_ctrl = pci_config_get16(handle, cap_ptr + PCI_MSI_CTRL);
1698 1698 if (!(msi_ctrl & PCI_MSI_ENABLE_BIT))
1699 1699 return;
1700 1700
1701 1701 msi_ctrl &= ~PCI_MSI_ENABLE_BIT; /* MSI disable */
1702 1702 pci_config_put16(handle, cap_ptr + PCI_MSI_CTRL, msi_ctrl);
1703 1703
1704 1704 } else if (type == DDI_INTR_TYPE_MSIX) {
1705 1705 msi_ctrl = pci_config_get16(handle, cap_ptr + PCI_MSIX_CTRL);
1706 1706 if (msi_ctrl & PCI_MSIX_ENABLE_BIT) {
1707 1707 msi_ctrl &= ~PCI_MSIX_ENABLE_BIT;
1708 1708 pci_config_put16(handle, cap_ptr + PCI_MSIX_CTRL,
1709 1709 msi_ctrl);
1710 1710 }
1711 1711 }
1712 1712 }
1713 1713
1714 1714 uint32_t
1715 1715 apic_get_localapicid(uint32_t cpuid)
1716 1716 {
1717 1717 ASSERT(cpuid < apic_nproc && apic_cpus != NULL);
1718 1718
1719 1719 return (apic_cpus[cpuid].aci_local_id);
1720 1720 }
1721 1721
1722 1722 uchar_t
1723 1723 apic_get_ioapicid(uchar_t ioapicindex)
1724 1724 {
1725 1725 ASSERT(ioapicindex < MAX_IO_APIC);
1726 1726
1727 1727 return (apic_io_id[ioapicindex]);
1728 1728 }
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