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--- old/usr/src/uts/i86pc/io/pcplusmp/apic.c
+++ new/usr/src/uts/i86pc/io/pcplusmp/apic.c
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21
22 22 /*
23 23 * Copyright (c) 1993, 2010, Oracle and/or its affiliates. All rights reserved.
24 24 */
25 25 /*
26 26 * Copyright (c) 2010, Intel Corporation.
27 27 * All rights reserved.
28 28 */
29 29 /*
30 30 * Copyright (c) 2013, Joyent, Inc. All rights reserved.
31 31 */
32 32
33 33 /*
34 34 * To understand how the pcplusmp module interacts with the interrupt subsystem
35 35 * read the theory statement in uts/i86pc/os/intr.c.
36 36 */
37 37
38 38 /*
39 39 * PSMI 1.1 extensions are supported only in 2.6 and later versions.
40 40 * PSMI 1.2 extensions are supported only in 2.7 and later versions.
41 41 * PSMI 1.3 and 1.4 extensions are supported in Solaris 10.
42 42 * PSMI 1.5 extensions are supported in Solaris Nevada.
|
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42 lines elided |
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43 43 * PSMI 1.6 extensions are supported in Solaris Nevada.
44 44 * PSMI 1.7 extensions are supported in Solaris Nevada.
45 45 */
46 46 #define PSMI_1_7
47 47
48 48 #include <sys/processor.h>
49 49 #include <sys/time.h>
50 50 #include <sys/psm.h>
51 51 #include <sys/smp_impldefs.h>
52 52 #include <sys/cram.h>
53 -#include <sys/acpi/acpi.h>
53 +#include <acpica/include/acpi.h>
54 54 #include <sys/acpica.h>
55 55 #include <sys/psm_common.h>
56 56 #include <sys/apic.h>
57 57 #include <sys/pit.h>
58 58 #include <sys/ddi.h>
59 59 #include <sys/sunddi.h>
60 60 #include <sys/ddi_impldefs.h>
61 61 #include <sys/pci.h>
62 62 #include <sys/promif.h>
63 63 #include <sys/x86_archext.h>
64 64 #include <sys/cpc_impl.h>
65 65 #include <sys/uadmin.h>
66 66 #include <sys/panic.h>
67 67 #include <sys/debug.h>
68 68 #include <sys/archsystm.h>
69 69 #include <sys/trap.h>
70 70 #include <sys/machsystm.h>
71 71 #include <sys/sysmacros.h>
72 72 #include <sys/cpuvar.h>
73 73 #include <sys/rm_platter.h>
74 74 #include <sys/privregs.h>
75 75 #include <sys/note.h>
76 76 #include <sys/pci_intr_lib.h>
77 77 #include <sys/spl.h>
78 78 #include <sys/clock.h>
79 79 #include <sys/cyclic.h>
80 80 #include <sys/dditypes.h>
81 81 #include <sys/sunddi.h>
82 82 #include <sys/x_call.h>
83 83 #include <sys/reboot.h>
84 84 #include <sys/hpet.h>
85 85 #include <sys/apic_common.h>
86 86 #include <sys/apic_timer.h>
87 87
88 88 /*
89 89 * Local Function Prototypes
90 90 */
91 91 static void apic_init_intr(void);
92 92
93 93 /*
94 94 * standard MP entries
95 95 */
96 96 static int apic_probe(void);
97 97 static int apic_getclkirq(int ipl);
98 98 static void apic_init(void);
99 99 static void apic_picinit(void);
100 100 static int apic_post_cpu_start(void);
101 101 static int apic_intr_enter(int ipl, int *vect);
102 102 static void apic_setspl(int ipl);
103 103 static void x2apic_setspl(int ipl);
104 104 static int apic_addspl(int ipl, int vector, int min_ipl, int max_ipl);
105 105 static int apic_delspl(int ipl, int vector, int min_ipl, int max_ipl);
106 106 static int apic_disable_intr(processorid_t cpun);
107 107 static void apic_enable_intr(processorid_t cpun);
108 108 static int apic_get_ipivect(int ipl, int type);
109 109 static void apic_post_cyclic_setup(void *arg);
110 110
111 111 /*
112 112 * The following vector assignments influence the value of ipltopri and
113 113 * vectortoipl. Note that vectors 0 - 0x1f are not used. We can program
114 114 * idle to 0 and IPL 0 to 0xf to differentiate idle in case
115 115 * we care to do so in future. Note some IPLs which are rarely used
116 116 * will share the vector ranges and heavily used IPLs (5 and 6) have
117 117 * a wide range.
118 118 *
119 119 * This array is used to initialize apic_ipls[] (in apic_init()).
120 120 *
121 121 * IPL Vector range. as passed to intr_enter
122 122 * 0 none.
123 123 * 1,2,3 0x20-0x2f 0x0-0xf
124 124 * 4 0x30-0x3f 0x10-0x1f
125 125 * 5 0x40-0x5f 0x20-0x3f
126 126 * 6 0x60-0x7f 0x40-0x5f
127 127 * 7,8,9 0x80-0x8f 0x60-0x6f
128 128 * 10 0x90-0x9f 0x70-0x7f
129 129 * 11 0xa0-0xaf 0x80-0x8f
130 130 * ... ...
131 131 * 15 0xe0-0xef 0xc0-0xcf
132 132 * 15 0xf0-0xff 0xd0-0xdf
133 133 */
134 134 uchar_t apic_vectortoipl[APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL] = {
135 135 3, 4, 5, 5, 6, 6, 9, 10, 11, 12, 13, 14, 15, 15
136 136 };
137 137 /*
138 138 * The ipl of an ISR at vector X is apic_vectortoipl[X>>4]
139 139 * NOTE that this is vector as passed into intr_enter which is
140 140 * programmed vector - 0x20 (APIC_BASE_VECT)
141 141 */
142 142
143 143 uchar_t apic_ipltopri[MAXIPL + 1]; /* unix ipl to apic pri */
144 144 /* The taskpri to be programmed into apic to mask given ipl */
145 145
146 146 #if defined(__amd64)
147 147 uchar_t apic_cr8pri[MAXIPL + 1]; /* unix ipl to cr8 pri */
148 148 #endif
149 149
150 150 /*
151 151 * Correlation of the hardware vector to the IPL in use, initialized
152 152 * from apic_vectortoipl[] in apic_init(). The final IPLs may not correlate
153 153 * to the IPLs in apic_vectortoipl on some systems that share interrupt lines
154 154 * connected to errata-stricken IOAPICs
155 155 */
156 156 uchar_t apic_ipls[APIC_AVAIL_VECTOR];
157 157
158 158 /*
159 159 * Patchable global variables.
160 160 */
161 161 int apic_enable_hwsoftint = 0; /* 0 - disable, 1 - enable */
162 162 int apic_enable_bind_log = 1; /* 1 - display interrupt binding log */
163 163
164 164 /*
165 165 * Local static data
166 166 */
167 167 static struct psm_ops apic_ops = {
168 168 apic_probe,
169 169
170 170 apic_init,
171 171 apic_picinit,
172 172 apic_intr_enter,
173 173 apic_intr_exit,
174 174 apic_setspl,
175 175 apic_addspl,
176 176 apic_delspl,
177 177 apic_disable_intr,
178 178 apic_enable_intr,
179 179 (int (*)(int))NULL, /* psm_softlvl_to_irq */
180 180 (void (*)(int))NULL, /* psm_set_softintr */
181 181
182 182 apic_set_idlecpu,
183 183 apic_unset_idlecpu,
184 184
185 185 apic_clkinit,
186 186 apic_getclkirq,
187 187 (void (*)(void))NULL, /* psm_hrtimeinit */
188 188 apic_gethrtime,
189 189
190 190 apic_get_next_processorid,
191 191 apic_cpu_start,
192 192 apic_post_cpu_start,
193 193 apic_shutdown,
194 194 apic_get_ipivect,
195 195 apic_send_ipi,
196 196
197 197 (int (*)(dev_info_t *, int))NULL, /* psm_translate_irq */
198 198 (void (*)(int, char *))NULL, /* psm_notify_error */
199 199 (void (*)(int))NULL, /* psm_notify_func */
200 200 apic_timer_reprogram,
201 201 apic_timer_enable,
202 202 apic_timer_disable,
203 203 apic_post_cyclic_setup,
204 204 apic_preshutdown,
205 205 apic_intr_ops, /* Advanced DDI Interrupt framework */
206 206 apic_state, /* save, restore apic state for S3 */
207 207 apic_cpu_ops, /* CPU control interface. */
208 208 };
209 209
210 210 struct psm_ops *psmops = &apic_ops;
211 211
212 212 static struct psm_info apic_psm_info = {
213 213 PSM_INFO_VER01_7, /* version */
214 214 PSM_OWN_EXCLUSIVE, /* ownership */
215 215 (struct psm_ops *)&apic_ops, /* operation */
216 216 APIC_PCPLUSMP_NAME, /* machine name */
217 217 "pcplusmp v1.4 compatible",
218 218 };
219 219
220 220 static void *apic_hdlp;
221 221
222 222 /*
223 223 * apic_let_idle_redistribute can have the following values:
224 224 * 0 - If clock decremented it from 1 to 0, clock has to call redistribute.
225 225 * apic_redistribute_lock prevents multiple idle cpus from redistributing
226 226 */
227 227 int apic_num_idle_redistributions = 0;
228 228 static int apic_let_idle_redistribute = 0;
229 229
230 230 /* to gather intr data and redistribute */
231 231 static void apic_redistribute_compute(void);
232 232
233 233 /*
234 234 * This is the loadable module wrapper
235 235 */
236 236
237 237 int
238 238 _init(void)
239 239 {
240 240 if (apic_coarse_hrtime)
241 241 apic_ops.psm_gethrtime = &apic_gettime;
242 242 return (psm_mod_init(&apic_hdlp, &apic_psm_info));
243 243 }
244 244
245 245 int
246 246 _fini(void)
247 247 {
248 248 return (psm_mod_fini(&apic_hdlp, &apic_psm_info));
249 249 }
250 250
251 251 int
252 252 _info(struct modinfo *modinfop)
253 253 {
254 254 return (psm_mod_info(&apic_hdlp, &apic_psm_info, modinfop));
255 255 }
256 256
257 257 static int
258 258 apic_probe(void)
259 259 {
260 260 /* check if apix is initialized */
261 261 if (apix_enable && apix_loaded())
262 262 return (PSM_FAILURE);
263 263 else
264 264 apix_enable = 0; /* continue using pcplusmp PSM */
265 265
266 266 return (apic_probe_common(apic_psm_info.p_mach_idstring));
267 267 }
268 268
269 269 static uchar_t
270 270 apic_xlate_vector_by_irq(uchar_t irq)
271 271 {
272 272 if (apic_irq_table[irq] == NULL)
273 273 return (0);
274 274
275 275 return (apic_irq_table[irq]->airq_vector);
276 276 }
277 277
278 278 void
279 279 apic_init(void)
280 280 {
281 281 int i;
282 282 int j = 1;
283 283
284 284 psm_get_ioapicid = apic_get_ioapicid;
285 285 psm_get_localapicid = apic_get_localapicid;
286 286 psm_xlate_vector_by_irq = apic_xlate_vector_by_irq;
287 287
288 288 apic_ipltopri[0] = APIC_VECTOR_PER_IPL; /* leave 0 for idle */
289 289 for (i = 0; i < (APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL); i++) {
290 290 if ((i < ((APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL) - 1)) &&
291 291 (apic_vectortoipl[i + 1] == apic_vectortoipl[i]))
292 292 /* get to highest vector at the same ipl */
293 293 continue;
294 294 for (; j <= apic_vectortoipl[i]; j++) {
295 295 apic_ipltopri[j] = (i << APIC_IPL_SHIFT) +
296 296 APIC_BASE_VECT;
297 297 }
298 298 }
299 299 for (; j < MAXIPL + 1; j++)
300 300 /* fill up any empty ipltopri slots */
301 301 apic_ipltopri[j] = (i << APIC_IPL_SHIFT) + APIC_BASE_VECT;
302 302 apic_init_common();
303 303 #if defined(__amd64)
304 304 /*
305 305 * Make cpu-specific interrupt info point to cr8pri vector
306 306 */
307 307 for (i = 0; i <= MAXIPL; i++)
308 308 apic_cr8pri[i] = apic_ipltopri[i] >> APIC_IPL_SHIFT;
309 309 CPU->cpu_pri_data = apic_cr8pri;
310 310 #else
311 311 if (cpuid_have_cr8access(CPU))
312 312 apic_have_32bit_cr8 = 1;
313 313 #endif /* __amd64 */
314 314 }
315 315
316 316 static void
317 317 apic_init_intr(void)
318 318 {
319 319 processorid_t cpun = psm_get_cpu_id();
320 320 uint_t nlvt;
321 321 uint32_t svr = AV_UNIT_ENABLE | APIC_SPUR_INTR;
322 322
323 323 apic_reg_ops->apic_write_task_reg(APIC_MASK_ALL);
324 324
325 325 if (apic_mode == LOCAL_APIC) {
326 326 /*
327 327 * We are running APIC in MMIO mode.
328 328 */
329 329 if (apic_flat_model) {
330 330 apic_reg_ops->apic_write(APIC_FORMAT_REG,
331 331 APIC_FLAT_MODEL);
332 332 } else {
333 333 apic_reg_ops->apic_write(APIC_FORMAT_REG,
334 334 APIC_CLUSTER_MODEL);
335 335 }
336 336
337 337 apic_reg_ops->apic_write(APIC_DEST_REG,
338 338 AV_HIGH_ORDER >> cpun);
339 339 }
340 340
341 341 if (apic_directed_EOI_supported()) {
342 342 /*
343 343 * Setting the 12th bit in the Spurious Interrupt Vector
344 344 * Register suppresses broadcast EOIs generated by the local
345 345 * APIC. The suppression of broadcast EOIs happens only when
346 346 * interrupts are level-triggered.
347 347 */
348 348 svr |= APIC_SVR_SUPPRESS_BROADCAST_EOI;
349 349 }
350 350
351 351 /* need to enable APIC before unmasking NMI */
352 352 apic_reg_ops->apic_write(APIC_SPUR_INT_REG, svr);
353 353
354 354 /*
355 355 * Presence of an invalid vector with delivery mode AV_FIXED can
356 356 * cause an error interrupt, even if the entry is masked...so
357 357 * write a valid vector to LVT entries along with the mask bit
358 358 */
359 359
360 360 /* All APICs have timer and LINT0/1 */
361 361 apic_reg_ops->apic_write(APIC_LOCAL_TIMER, AV_MASK|APIC_RESV_IRQ);
362 362 apic_reg_ops->apic_write(APIC_INT_VECT0, AV_MASK|APIC_RESV_IRQ);
363 363 apic_reg_ops->apic_write(APIC_INT_VECT1, AV_NMI); /* enable NMI */
364 364
365 365 /*
366 366 * On integrated APICs, the number of LVT entries is
367 367 * 'Max LVT entry' + 1; on 82489DX's (non-integrated
368 368 * APICs), nlvt is "3" (LINT0, LINT1, and timer)
369 369 */
370 370
371 371 if (apic_cpus[cpun].aci_local_ver < APIC_INTEGRATED_VERS) {
372 372 nlvt = 3;
373 373 } else {
374 374 nlvt = ((apic_reg_ops->apic_read(APIC_VERS_REG) >> 16) &
375 375 0xFF) + 1;
376 376 }
377 377
378 378 if (nlvt >= 5) {
379 379 /* Enable performance counter overflow interrupt */
380 380
381 381 if (!is_x86_feature(x86_featureset, X86FSET_MSR))
382 382 apic_enable_cpcovf_intr = 0;
383 383 if (apic_enable_cpcovf_intr) {
384 384 if (apic_cpcovf_vect == 0) {
385 385 int ipl = APIC_PCINT_IPL;
386 386 int irq = apic_get_ipivect(ipl, -1);
387 387
388 388 ASSERT(irq != -1);
389 389 apic_cpcovf_vect =
390 390 apic_irq_table[irq]->airq_vector;
391 391 ASSERT(apic_cpcovf_vect);
392 392 (void) add_avintr(NULL, ipl,
393 393 (avfunc)kcpc_hw_overflow_intr,
394 394 "apic pcint", irq, NULL, NULL, NULL, NULL);
395 395 kcpc_hw_overflow_intr_installed = 1;
396 396 kcpc_hw_enable_cpc_intr =
397 397 apic_cpcovf_mask_clear;
398 398 }
399 399 apic_reg_ops->apic_write(APIC_PCINT_VECT,
400 400 apic_cpcovf_vect);
401 401 }
402 402 }
403 403
404 404 if (nlvt >= 6) {
405 405 /* Only mask TM intr if the BIOS apparently doesn't use it */
406 406
407 407 uint32_t lvtval;
408 408
409 409 lvtval = apic_reg_ops->apic_read(APIC_THERM_VECT);
410 410 if (((lvtval & AV_MASK) == AV_MASK) ||
411 411 ((lvtval & AV_DELIV_MODE) != AV_SMI)) {
412 412 apic_reg_ops->apic_write(APIC_THERM_VECT,
413 413 AV_MASK|APIC_RESV_IRQ);
414 414 }
415 415 }
416 416
417 417 /* Enable error interrupt */
418 418
419 419 if (nlvt >= 4 && apic_enable_error_intr) {
420 420 if (apic_errvect == 0) {
421 421 int ipl = 0xf; /* get highest priority intr */
422 422 int irq = apic_get_ipivect(ipl, -1);
423 423
424 424 ASSERT(irq != -1);
425 425 apic_errvect = apic_irq_table[irq]->airq_vector;
426 426 ASSERT(apic_errvect);
427 427 /*
428 428 * Not PSMI compliant, but we are going to merge
429 429 * with ON anyway
430 430 */
431 431 (void) add_avintr((void *)NULL, ipl,
432 432 (avfunc)apic_error_intr, "apic error intr",
433 433 irq, NULL, NULL, NULL, NULL);
434 434 }
435 435 apic_reg_ops->apic_write(APIC_ERR_VECT, apic_errvect);
436 436 apic_reg_ops->apic_write(APIC_ERROR_STATUS, 0);
437 437 apic_reg_ops->apic_write(APIC_ERROR_STATUS, 0);
438 438 }
439 439
440 440 /* Enable CMCI interrupt */
441 441 if (cmi_enable_cmci) {
442 442
443 443 mutex_enter(&cmci_cpu_setup_lock);
444 444 if (cmci_cpu_setup_registered == 0) {
445 445 mutex_enter(&cpu_lock);
446 446 register_cpu_setup_func(cmci_cpu_setup, NULL);
447 447 mutex_exit(&cpu_lock);
448 448 cmci_cpu_setup_registered = 1;
449 449 }
450 450 mutex_exit(&cmci_cpu_setup_lock);
451 451
452 452 if (apic_cmci_vect == 0) {
453 453 int ipl = 0x2;
454 454 int irq = apic_get_ipivect(ipl, -1);
455 455
456 456 ASSERT(irq != -1);
457 457 apic_cmci_vect = apic_irq_table[irq]->airq_vector;
458 458 ASSERT(apic_cmci_vect);
459 459
460 460 (void) add_avintr(NULL, ipl,
461 461 (avfunc)cmi_cmci_trap,
462 462 "apic cmci intr", irq, NULL, NULL, NULL, NULL);
463 463 }
464 464 apic_reg_ops->apic_write(APIC_CMCI_VECT, apic_cmci_vect);
465 465 }
466 466 }
467 467
468 468 static void
469 469 apic_picinit(void)
470 470 {
471 471 int i, j;
472 472 uint_t isr;
473 473
474 474 /*
475 475 * Initialize and enable interrupt remapping before apic
476 476 * hardware initialization
477 477 */
478 478 apic_intrmap_init(apic_mode);
479 479
480 480 /*
481 481 * On UniSys Model 6520, the BIOS leaves vector 0x20 isr
482 482 * bit on without clearing it with EOI. Since softint
483 483 * uses vector 0x20 to interrupt itself, so softint will
484 484 * not work on this machine. In order to fix this problem
485 485 * a check is made to verify all the isr bits are clear.
486 486 * If not, EOIs are issued to clear the bits.
487 487 */
488 488 for (i = 7; i >= 1; i--) {
489 489 isr = apic_reg_ops->apic_read(APIC_ISR_REG + (i * 4));
490 490 if (isr != 0)
491 491 for (j = 0; ((j < 32) && (isr != 0)); j++)
492 492 if (isr & (1 << j)) {
493 493 apic_reg_ops->apic_write(
494 494 APIC_EOI_REG, 0);
495 495 isr &= ~(1 << j);
496 496 apic_error |= APIC_ERR_BOOT_EOI;
497 497 }
498 498 }
499 499
500 500 /* set a flag so we know we have run apic_picinit() */
501 501 apic_picinit_called = 1;
502 502 LOCK_INIT_CLEAR(&apic_gethrtime_lock);
503 503 LOCK_INIT_CLEAR(&apic_ioapic_lock);
504 504 LOCK_INIT_CLEAR(&apic_error_lock);
505 505 LOCK_INIT_CLEAR(&apic_mode_switch_lock);
506 506
507 507 picsetup(); /* initialise the 8259 */
508 508
509 509 /* add nmi handler - least priority nmi handler */
510 510 LOCK_INIT_CLEAR(&apic_nmi_lock);
511 511
512 512 if (!psm_add_nmintr(0, (avfunc) apic_nmi_intr,
513 513 "pcplusmp NMI handler", (caddr_t)NULL))
514 514 cmn_err(CE_WARN, "pcplusmp: Unable to add nmi handler");
515 515
516 516 /*
517 517 * Check for directed-EOI capability in the local APIC.
518 518 */
519 519 if (apic_directed_EOI_supported() == 1) {
520 520 apic_set_directed_EOI_handler();
521 521 }
522 522
523 523 apic_init_intr();
524 524
525 525 /* enable apic mode if imcr present */
526 526 if (apic_imcrp) {
527 527 outb(APIC_IMCR_P1, (uchar_t)APIC_IMCR_SELECT);
528 528 outb(APIC_IMCR_P2, (uchar_t)APIC_IMCR_APIC);
529 529 }
530 530
531 531 ioapic_init_intr(IOAPIC_MASK);
532 532 }
533 533
534 534 #ifdef DEBUG
535 535 void
536 536 apic_break(void)
537 537 {
538 538 }
539 539 #endif /* DEBUG */
540 540
541 541 /*
542 542 * platform_intr_enter
543 543 *
544 544 * Called at the beginning of the interrupt service routine to
545 545 * mask all level equal to and below the interrupt priority
546 546 * of the interrupting vector. An EOI should be given to
547 547 * the interrupt controller to enable other HW interrupts.
548 548 *
549 549 * Return -1 for spurious interrupts
550 550 *
551 551 */
552 552 /*ARGSUSED*/
553 553 static int
554 554 apic_intr_enter(int ipl, int *vectorp)
555 555 {
556 556 uchar_t vector;
557 557 int nipl;
558 558 int irq;
559 559 ulong_t iflag;
560 560 apic_cpus_info_t *cpu_infop;
561 561
562 562 /*
563 563 * The real vector delivered is (*vectorp + 0x20), but our caller
564 564 * subtracts 0x20 from the vector before passing it to us.
565 565 * (That's why APIC_BASE_VECT is 0x20.)
566 566 */
567 567 vector = (uchar_t)*vectorp;
568 568
569 569 /* if interrupted by the clock, increment apic_nsec_since_boot */
570 570 if (vector == apic_clkvect) {
571 571 if (!apic_oneshot) {
572 572 /* NOTE: this is not MT aware */
573 573 apic_hrtime_stamp++;
574 574 apic_nsec_since_boot += apic_nsec_per_intr;
575 575 apic_hrtime_stamp++;
576 576 last_count_read = apic_hertz_count;
577 577 apic_redistribute_compute();
578 578 }
579 579
580 580 /* We will avoid all the book keeping overhead for clock */
581 581 nipl = apic_ipls[vector];
582 582
583 583 *vectorp = apic_vector_to_irq[vector + APIC_BASE_VECT];
584 584 if (apic_mode == LOCAL_APIC) {
585 585 #if defined(__amd64)
586 586 setcr8((ulong_t)(apic_ipltopri[nipl] >>
587 587 APIC_IPL_SHIFT));
588 588 #else
589 589 if (apic_have_32bit_cr8)
590 590 setcr8((ulong_t)(apic_ipltopri[nipl] >>
591 591 APIC_IPL_SHIFT));
592 592 else
593 593 LOCAL_APIC_WRITE_REG(APIC_TASK_REG,
594 594 (uint32_t)apic_ipltopri[nipl]);
595 595 #endif
596 596 LOCAL_APIC_WRITE_REG(APIC_EOI_REG, 0);
597 597 } else {
598 598 X2APIC_WRITE(APIC_TASK_REG, apic_ipltopri[nipl]);
599 599 X2APIC_WRITE(APIC_EOI_REG, 0);
600 600 }
601 601
602 602 return (nipl);
603 603 }
604 604
605 605 cpu_infop = &apic_cpus[psm_get_cpu_id()];
606 606
607 607 if (vector == (APIC_SPUR_INTR - APIC_BASE_VECT)) {
608 608 cpu_infop->aci_spur_cnt++;
609 609 return (APIC_INT_SPURIOUS);
610 610 }
611 611
612 612 /* Check if the vector we got is really what we need */
613 613 if (apic_revector_pending) {
614 614 /*
615 615 * Disable interrupts for the duration of
616 616 * the vector translation to prevent a self-race for
617 617 * the apic_revector_lock. This cannot be done
618 618 * in apic_xlate_vector because it is recursive and
619 619 * we want the vector translation to be atomic with
620 620 * respect to other (higher-priority) interrupts.
621 621 */
622 622 iflag = intr_clear();
623 623 vector = apic_xlate_vector(vector + APIC_BASE_VECT) -
624 624 APIC_BASE_VECT;
625 625 intr_restore(iflag);
626 626 }
627 627
628 628 nipl = apic_ipls[vector];
629 629 *vectorp = irq = apic_vector_to_irq[vector + APIC_BASE_VECT];
630 630
631 631 if (apic_mode == LOCAL_APIC) {
632 632 #if defined(__amd64)
633 633 setcr8((ulong_t)(apic_ipltopri[nipl] >> APIC_IPL_SHIFT));
634 634 #else
635 635 if (apic_have_32bit_cr8)
636 636 setcr8((ulong_t)(apic_ipltopri[nipl] >>
637 637 APIC_IPL_SHIFT));
638 638 else
639 639 LOCAL_APIC_WRITE_REG(APIC_TASK_REG,
640 640 (uint32_t)apic_ipltopri[nipl]);
641 641 #endif
642 642 } else {
643 643 X2APIC_WRITE(APIC_TASK_REG, apic_ipltopri[nipl]);
644 644 }
645 645
646 646 cpu_infop->aci_current[nipl] = (uchar_t)irq;
647 647 cpu_infop->aci_curipl = (uchar_t)nipl;
648 648 cpu_infop->aci_ISR_in_progress |= 1 << nipl;
649 649
650 650 /*
651 651 * apic_level_intr could have been assimilated into the irq struct.
652 652 * but, having it as a character array is more efficient in terms of
653 653 * cache usage. So, we leave it as is.
654 654 */
655 655 if (!apic_level_intr[irq]) {
656 656 if (apic_mode == LOCAL_APIC) {
657 657 LOCAL_APIC_WRITE_REG(APIC_EOI_REG, 0);
658 658 } else {
659 659 X2APIC_WRITE(APIC_EOI_REG, 0);
660 660 }
661 661 }
662 662
663 663 #ifdef DEBUG
664 664 APIC_DEBUG_BUF_PUT(vector);
665 665 APIC_DEBUG_BUF_PUT(irq);
666 666 APIC_DEBUG_BUF_PUT(nipl);
667 667 APIC_DEBUG_BUF_PUT(psm_get_cpu_id());
668 668 if ((apic_stretch_interrupts) && (apic_stretch_ISR & (1 << nipl)))
669 669 drv_usecwait(apic_stretch_interrupts);
670 670
671 671 if (apic_break_on_cpu == psm_get_cpu_id())
672 672 apic_break();
673 673 #endif /* DEBUG */
674 674 return (nipl);
675 675 }
676 676
677 677 /*
678 678 * This macro is a common code used by MMIO local apic and X2APIC
679 679 * local apic.
680 680 */
681 681 #define APIC_INTR_EXIT() \
682 682 { \
683 683 cpu_infop = &apic_cpus[psm_get_cpu_id()]; \
684 684 if (apic_level_intr[irq]) \
685 685 apic_reg_ops->apic_send_eoi(irq); \
686 686 cpu_infop->aci_curipl = (uchar_t)prev_ipl; \
687 687 /* ISR above current pri could not be in progress */ \
688 688 cpu_infop->aci_ISR_in_progress &= (2 << prev_ipl) - 1; \
689 689 }
690 690
691 691 /*
692 692 * Any changes made to this function must also change X2APIC
693 693 * version of intr_exit.
694 694 */
695 695 void
696 696 apic_intr_exit(int prev_ipl, int irq)
697 697 {
698 698 apic_cpus_info_t *cpu_infop;
699 699
700 700 #if defined(__amd64)
701 701 setcr8((ulong_t)apic_cr8pri[prev_ipl]);
702 702 #else
703 703 if (apic_have_32bit_cr8)
704 704 setcr8((ulong_t)(apic_ipltopri[prev_ipl] >> APIC_IPL_SHIFT));
705 705 else
706 706 apicadr[APIC_TASK_REG] = apic_ipltopri[prev_ipl];
707 707 #endif
708 708
709 709 APIC_INTR_EXIT();
710 710 }
711 711
712 712 /*
713 713 * Same as apic_intr_exit() except it uses MSR rather than MMIO
714 714 * to access local apic registers.
715 715 */
716 716 void
717 717 x2apic_intr_exit(int prev_ipl, int irq)
718 718 {
719 719 apic_cpus_info_t *cpu_infop;
720 720
721 721 X2APIC_WRITE(APIC_TASK_REG, apic_ipltopri[prev_ipl]);
722 722 APIC_INTR_EXIT();
723 723 }
724 724
725 725 intr_exit_fn_t
726 726 psm_intr_exit_fn(void)
727 727 {
728 728 if (apic_mode == LOCAL_X2APIC)
729 729 return (x2apic_intr_exit);
730 730
731 731 return (apic_intr_exit);
732 732 }
733 733
734 734 /*
735 735 * Mask all interrupts below or equal to the given IPL.
736 736 * Any changes made to this function must also change X2APIC
737 737 * version of setspl.
738 738 */
739 739 static void
740 740 apic_setspl(int ipl)
741 741 {
742 742 #if defined(__amd64)
743 743 setcr8((ulong_t)apic_cr8pri[ipl]);
744 744 #else
745 745 if (apic_have_32bit_cr8)
746 746 setcr8((ulong_t)(apic_ipltopri[ipl] >> APIC_IPL_SHIFT));
747 747 else
748 748 apicadr[APIC_TASK_REG] = apic_ipltopri[ipl];
749 749 #endif
750 750
751 751 /* interrupts at ipl above this cannot be in progress */
752 752 apic_cpus[psm_get_cpu_id()].aci_ISR_in_progress &= (2 << ipl) - 1;
753 753 /*
754 754 * this is a patch fix for the ALR QSMP P5 machine, so that interrupts
755 755 * have enough time to come in before the priority is raised again
756 756 * during the idle() loop.
757 757 */
758 758 if (apic_setspl_delay)
759 759 (void) apic_reg_ops->apic_get_pri();
760 760 }
761 761
762 762 /*
763 763 * X2APIC version of setspl.
764 764 * Mask all interrupts below or equal to the given IPL
765 765 */
766 766 static void
767 767 x2apic_setspl(int ipl)
768 768 {
769 769 X2APIC_WRITE(APIC_TASK_REG, apic_ipltopri[ipl]);
770 770
771 771 /* interrupts at ipl above this cannot be in progress */
772 772 apic_cpus[psm_get_cpu_id()].aci_ISR_in_progress &= (2 << ipl) - 1;
773 773 }
774 774
775 775 /*ARGSUSED*/
776 776 static int
777 777 apic_addspl(int irqno, int ipl, int min_ipl, int max_ipl)
778 778 {
779 779 return (apic_addspl_common(irqno, ipl, min_ipl, max_ipl));
780 780 }
781 781
782 782 static int
783 783 apic_delspl(int irqno, int ipl, int min_ipl, int max_ipl)
784 784 {
785 785 return (apic_delspl_common(irqno, ipl, min_ipl, max_ipl));
786 786 }
787 787
788 788 static int
789 789 apic_post_cpu_start(void)
790 790 {
791 791 int cpun;
792 792 static int cpus_started = 1;
793 793
794 794 /* We know this CPU + BSP started successfully. */
795 795 cpus_started++;
796 796
797 797 /*
798 798 * On BSP we would have enabled X2APIC, if supported by processor,
799 799 * in acpi_probe(), but on AP we do it here.
800 800 *
801 801 * We enable X2APIC mode only if BSP is running in X2APIC & the
802 802 * local APIC mode of the current CPU is MMIO (xAPIC).
803 803 */
804 804 if (apic_mode == LOCAL_X2APIC && apic_detect_x2apic() &&
805 805 apic_local_mode() == LOCAL_APIC) {
806 806 apic_enable_x2apic();
807 807 }
808 808
809 809 /*
810 810 * Switch back to x2apic IPI sending method for performance when target
811 811 * CPU has entered x2apic mode.
812 812 */
813 813 if (apic_mode == LOCAL_X2APIC) {
814 814 apic_switch_ipi_callback(B_FALSE);
815 815 }
816 816
817 817 splx(ipltospl(LOCK_LEVEL));
818 818 apic_init_intr();
819 819
820 820 /*
821 821 * since some systems don't enable the internal cache on the non-boot
822 822 * cpus, so we have to enable them here
823 823 */
824 824 setcr0(getcr0() & ~(CR0_CD | CR0_NW));
825 825
826 826 #ifdef DEBUG
827 827 APIC_AV_PENDING_SET();
828 828 #else
829 829 if (apic_mode == LOCAL_APIC)
830 830 APIC_AV_PENDING_SET();
831 831 #endif /* DEBUG */
832 832
833 833 /*
834 834 * We may be booting, or resuming from suspend; aci_status will
835 835 * be APIC_CPU_INTR_ENABLE if coming from suspend, so we add the
836 836 * APIC_CPU_ONLINE flag here rather than setting aci_status completely.
837 837 */
838 838 cpun = psm_get_cpu_id();
839 839 apic_cpus[cpun].aci_status |= APIC_CPU_ONLINE;
840 840
841 841 apic_reg_ops->apic_write(APIC_DIVIDE_REG, apic_divide_reg_init);
842 842 return (PSM_SUCCESS);
843 843 }
844 844
845 845 /*
846 846 * type == -1 indicates it is an internal request. Do not change
847 847 * resv_vector for these requests
848 848 */
849 849 static int
850 850 apic_get_ipivect(int ipl, int type)
851 851 {
852 852 uchar_t vector;
853 853 int irq;
854 854
855 855 if ((irq = apic_allocate_irq(APIC_VECTOR(ipl))) != -1) {
856 856 if (vector = apic_allocate_vector(ipl, irq, 1)) {
857 857 apic_irq_table[irq]->airq_mps_intr_index =
858 858 RESERVE_INDEX;
859 859 apic_irq_table[irq]->airq_vector = vector;
860 860 if (type != -1) {
861 861 apic_resv_vector[ipl] = vector;
862 862 }
863 863 return (irq);
864 864 }
865 865 }
866 866 apic_error |= APIC_ERR_GET_IPIVECT_FAIL;
867 867 return (-1); /* shouldn't happen */
868 868 }
869 869
870 870 static int
871 871 apic_getclkirq(int ipl)
872 872 {
873 873 int irq;
874 874
875 875 if ((irq = apic_get_ipivect(ipl, -1)) == -1)
876 876 return (-1);
877 877 /*
878 878 * Note the vector in apic_clkvect for per clock handling.
879 879 */
880 880 apic_clkvect = apic_irq_table[irq]->airq_vector - APIC_BASE_VECT;
881 881 APIC_VERBOSE_IOAPIC((CE_NOTE, "get_clkirq: vector = %x\n",
882 882 apic_clkvect));
883 883 return (irq);
884 884 }
885 885
886 886 /*
887 887 * Try and disable all interrupts. We just assign interrupts to other
888 888 * processors based on policy. If any were bound by user request, we
889 889 * let them continue and return failure. We do not bother to check
890 890 * for cache affinity while rebinding.
891 891 */
892 892
893 893 static int
894 894 apic_disable_intr(processorid_t cpun)
895 895 {
896 896 int bind_cpu = 0, i, hardbound = 0;
897 897 apic_irq_t *irq_ptr;
898 898 ulong_t iflag;
899 899
900 900 iflag = intr_clear();
901 901 lock_set(&apic_ioapic_lock);
902 902
903 903 for (i = 0; i <= APIC_MAX_VECTOR; i++) {
904 904 if (apic_reprogram_info[i].done == B_FALSE) {
905 905 if (apic_reprogram_info[i].bindcpu == cpun) {
906 906 /*
907 907 * CPU is busy -- it's the target of
908 908 * a pending reprogramming attempt
909 909 */
910 910 lock_clear(&apic_ioapic_lock);
911 911 intr_restore(iflag);
912 912 return (PSM_FAILURE);
913 913 }
914 914 }
915 915 }
916 916
917 917 apic_cpus[cpun].aci_status &= ~APIC_CPU_INTR_ENABLE;
918 918
919 919 apic_cpus[cpun].aci_curipl = 0;
920 920
921 921 i = apic_min_device_irq;
922 922 for (; i <= apic_max_device_irq; i++) {
923 923 /*
924 924 * If there are bound interrupts on this cpu, then
925 925 * rebind them to other processors.
926 926 */
927 927 if ((irq_ptr = apic_irq_table[i]) != NULL) {
928 928 ASSERT((irq_ptr->airq_temp_cpu == IRQ_UNBOUND) ||
929 929 (irq_ptr->airq_temp_cpu == IRQ_UNINIT) ||
930 930 (apic_cpu_in_range(irq_ptr->airq_temp_cpu)));
931 931
932 932 if (irq_ptr->airq_temp_cpu == (cpun | IRQ_USER_BOUND)) {
933 933 hardbound = 1;
934 934 continue;
935 935 }
936 936
937 937 if (irq_ptr->airq_temp_cpu == cpun) {
938 938 do {
939 939 bind_cpu =
940 940 apic_find_cpu(APIC_CPU_INTR_ENABLE);
941 941 } while (apic_rebind_all(irq_ptr, bind_cpu));
942 942 }
943 943 }
944 944 }
945 945
946 946 lock_clear(&apic_ioapic_lock);
947 947 intr_restore(iflag);
948 948
949 949 if (hardbound) {
950 950 cmn_err(CE_WARN, "Could not disable interrupts on %d"
951 951 "due to user bound interrupts", cpun);
952 952 return (PSM_FAILURE);
953 953 }
954 954 else
955 955 return (PSM_SUCCESS);
956 956 }
957 957
958 958 /*
959 959 * Bind interrupts to the CPU's local APIC.
960 960 * Interrupts should not be bound to a CPU's local APIC until the CPU
961 961 * is ready to receive interrupts.
962 962 */
963 963 static void
964 964 apic_enable_intr(processorid_t cpun)
965 965 {
966 966 int i;
967 967 apic_irq_t *irq_ptr;
968 968 ulong_t iflag;
969 969
970 970 iflag = intr_clear();
971 971 lock_set(&apic_ioapic_lock);
972 972
973 973 apic_cpus[cpun].aci_status |= APIC_CPU_INTR_ENABLE;
974 974
975 975 i = apic_min_device_irq;
976 976 for (i = apic_min_device_irq; i <= apic_max_device_irq; i++) {
977 977 if ((irq_ptr = apic_irq_table[i]) != NULL) {
978 978 if ((irq_ptr->airq_cpu & ~IRQ_USER_BOUND) == cpun) {
979 979 (void) apic_rebind_all(irq_ptr,
980 980 irq_ptr->airq_cpu);
981 981 }
982 982 }
983 983 }
984 984
985 985 if (apic_cpus[cpun].aci_status & APIC_CPU_SUSPEND)
986 986 apic_cpus[cpun].aci_status &= ~APIC_CPU_SUSPEND;
987 987
988 988 lock_clear(&apic_ioapic_lock);
989 989 intr_restore(iflag);
990 990 }
991 991
992 992 /*
993 993 * If this module needs a periodic handler for the interrupt distribution, it
994 994 * can be added here. The argument to the periodic handler is not currently
995 995 * used, but is reserved for future.
996 996 */
997 997 static void
998 998 apic_post_cyclic_setup(void *arg)
999 999 {
1000 1000 _NOTE(ARGUNUSED(arg))
1001 1001
1002 1002 cyc_handler_t cyh;
1003 1003 cyc_time_t cyt;
1004 1004
1005 1005 /* cpu_lock is held */
1006 1006 /* set up a periodic handler for intr redistribution */
1007 1007
1008 1008 /*
1009 1009 * In peridoc mode intr redistribution processing is done in
1010 1010 * apic_intr_enter during clk intr processing
1011 1011 */
1012 1012 if (!apic_oneshot)
1013 1013 return;
1014 1014
1015 1015 /*
1016 1016 * Register a periodical handler for the redistribution processing.
1017 1017 * Though we would generally prefer to use the DDI interface for
1018 1018 * periodic handler invocation, ddi_periodic_add(9F), we are
1019 1019 * unfortunately already holding cpu_lock, which ddi_periodic_add will
1020 1020 * attempt to take for us. Thus, we add our own cyclic directly:
1021 1021 */
1022 1022 cyh.cyh_func = (void (*)(void *))apic_redistribute_compute;
1023 1023 cyh.cyh_arg = NULL;
1024 1024 cyh.cyh_level = CY_LOW_LEVEL;
1025 1025
1026 1026 cyt.cyt_when = 0;
1027 1027 cyt.cyt_interval = apic_redistribute_sample_interval;
1028 1028
1029 1029 apic_cyclic_id = cyclic_add(&cyh, &cyt);
1030 1030 }
1031 1031
1032 1032 static void
1033 1033 apic_redistribute_compute(void)
1034 1034 {
1035 1035 int i, j, max_busy;
1036 1036
1037 1037 if (apic_enable_dynamic_migration) {
1038 1038 if (++apic_nticks == apic_sample_factor_redistribution) {
1039 1039 /*
1040 1040 * Time to call apic_intr_redistribute().
1041 1041 * reset apic_nticks. This will cause max_busy
1042 1042 * to be calculated below and if it is more than
1043 1043 * apic_int_busy, we will do the whole thing
1044 1044 */
1045 1045 apic_nticks = 0;
1046 1046 }
1047 1047 max_busy = 0;
1048 1048 for (i = 0; i < apic_nproc; i++) {
1049 1049 if (!apic_cpu_in_range(i))
1050 1050 continue;
1051 1051
1052 1052 /*
1053 1053 * Check if curipl is non zero & if ISR is in
1054 1054 * progress
1055 1055 */
1056 1056 if (((j = apic_cpus[i].aci_curipl) != 0) &&
1057 1057 (apic_cpus[i].aci_ISR_in_progress & (1 << j))) {
1058 1058
1059 1059 int irq;
1060 1060 apic_cpus[i].aci_busy++;
1061 1061 irq = apic_cpus[i].aci_current[j];
1062 1062 apic_irq_table[irq]->airq_busy++;
1063 1063 }
1064 1064
1065 1065 if (!apic_nticks &&
1066 1066 (apic_cpus[i].aci_busy > max_busy))
1067 1067 max_busy = apic_cpus[i].aci_busy;
1068 1068 }
1069 1069 if (!apic_nticks) {
1070 1070 if (max_busy > apic_int_busy_mark) {
1071 1071 /*
1072 1072 * We could make the following check be
1073 1073 * skipped > 1 in which case, we get a
1074 1074 * redistribution at half the busy mark (due to
1075 1075 * double interval). Need to be able to collect
1076 1076 * more empirical data to decide if that is a
1077 1077 * good strategy. Punt for now.
1078 1078 */
1079 1079 if (apic_skipped_redistribute) {
1080 1080 apic_cleanup_busy();
1081 1081 apic_skipped_redistribute = 0;
1082 1082 } else {
1083 1083 apic_intr_redistribute();
1084 1084 }
1085 1085 } else
1086 1086 apic_skipped_redistribute++;
1087 1087 }
1088 1088 }
1089 1089 }
1090 1090
1091 1091
1092 1092 /*
1093 1093 * The following functions are in the platform specific file so that they
1094 1094 * can be different functions depending on whether we are running on
1095 1095 * bare metal or a hypervisor.
1096 1096 */
1097 1097
1098 1098 /*
1099 1099 * Check to make sure there are enough irq slots
1100 1100 */
1101 1101 int
1102 1102 apic_check_free_irqs(int count)
1103 1103 {
1104 1104 int i, avail;
1105 1105
1106 1106 avail = 0;
1107 1107 for (i = APIC_FIRST_FREE_IRQ; i < APIC_RESV_IRQ; i++) {
1108 1108 if ((apic_irq_table[i] == NULL) ||
1109 1109 apic_irq_table[i]->airq_mps_intr_index == FREE_INDEX) {
1110 1110 if (++avail >= count)
1111 1111 return (PSM_SUCCESS);
1112 1112 }
1113 1113 }
1114 1114 return (PSM_FAILURE);
1115 1115 }
1116 1116
1117 1117 /*
1118 1118 * This function allocates "count" MSI vector(s) for the given "dip/pri/type"
1119 1119 */
1120 1120 int
1121 1121 apic_alloc_msi_vectors(dev_info_t *dip, int inum, int count, int pri,
1122 1122 int behavior)
1123 1123 {
1124 1124 int rcount, i;
1125 1125 uchar_t start, irqno;
1126 1126 uint32_t cpu;
1127 1127 major_t major;
1128 1128 apic_irq_t *irqptr;
1129 1129
1130 1130 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: dip=0x%p "
1131 1131 "inum=0x%x pri=0x%x count=0x%x behavior=%d\n",
1132 1132 (void *)dip, inum, pri, count, behavior));
1133 1133
1134 1134 if (count > 1) {
1135 1135 if (behavior == DDI_INTR_ALLOC_STRICT &&
1136 1136 apic_multi_msi_enable == 0)
1137 1137 return (0);
1138 1138 if (apic_multi_msi_enable == 0)
1139 1139 count = 1;
1140 1140 }
1141 1141
1142 1142 if ((rcount = apic_navail_vector(dip, pri)) > count)
1143 1143 rcount = count;
1144 1144 else if (rcount == 0 || (rcount < count &&
1145 1145 behavior == DDI_INTR_ALLOC_STRICT))
1146 1146 return (0);
1147 1147
1148 1148 /* if not ISP2, then round it down */
1149 1149 if (!ISP2(rcount))
1150 1150 rcount = 1 << (highbit(rcount) - 1);
1151 1151
1152 1152 mutex_enter(&airq_mutex);
1153 1153
1154 1154 for (start = 0; rcount > 0; rcount >>= 1) {
1155 1155 if ((start = apic_find_multi_vectors(pri, rcount)) != 0 ||
1156 1156 behavior == DDI_INTR_ALLOC_STRICT)
1157 1157 break;
1158 1158 }
1159 1159
1160 1160 if (start == 0) {
1161 1161 /* no vector available */
1162 1162 mutex_exit(&airq_mutex);
1163 1163 return (0);
1164 1164 }
1165 1165
1166 1166 if (apic_check_free_irqs(rcount) == PSM_FAILURE) {
1167 1167 /* not enough free irq slots available */
1168 1168 mutex_exit(&airq_mutex);
1169 1169 return (0);
1170 1170 }
1171 1171
1172 1172 major = (dip != NULL) ? ddi_driver_major(dip) : 0;
1173 1173 for (i = 0; i < rcount; i++) {
1174 1174 if ((irqno = apic_allocate_irq(apic_first_avail_irq)) ==
1175 1175 (uchar_t)-1) {
1176 1176 /*
1177 1177 * shouldn't happen because of the
1178 1178 * apic_check_free_irqs() check earlier
1179 1179 */
1180 1180 mutex_exit(&airq_mutex);
1181 1181 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: "
1182 1182 "apic_allocate_irq failed\n"));
1183 1183 return (i);
1184 1184 }
1185 1185 apic_max_device_irq = max(irqno, apic_max_device_irq);
1186 1186 apic_min_device_irq = min(irqno, apic_min_device_irq);
1187 1187 irqptr = apic_irq_table[irqno];
1188 1188 #ifdef DEBUG
1189 1189 if (apic_vector_to_irq[start + i] != APIC_RESV_IRQ)
1190 1190 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: "
1191 1191 "apic_vector_to_irq is not APIC_RESV_IRQ\n"));
1192 1192 #endif
1193 1193 apic_vector_to_irq[start + i] = (uchar_t)irqno;
1194 1194
1195 1195 irqptr->airq_vector = (uchar_t)(start + i);
1196 1196 irqptr->airq_ioapicindex = (uchar_t)inum; /* start */
1197 1197 irqptr->airq_intin_no = (uchar_t)rcount;
1198 1198 irqptr->airq_ipl = pri;
1199 1199 irqptr->airq_vector = start + i;
1200 1200 irqptr->airq_origirq = (uchar_t)(inum + i);
1201 1201 irqptr->airq_share_id = 0;
1202 1202 irqptr->airq_mps_intr_index = MSI_INDEX;
1203 1203 irqptr->airq_dip = dip;
1204 1204 irqptr->airq_major = major;
1205 1205 if (i == 0) /* they all bound to the same cpu */
1206 1206 cpu = irqptr->airq_cpu = apic_bind_intr(dip, irqno,
1207 1207 0xff, 0xff);
1208 1208 else
1209 1209 irqptr->airq_cpu = cpu;
1210 1210 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: irq=0x%x "
1211 1211 "dip=0x%p vector=0x%x origirq=0x%x pri=0x%x\n", irqno,
1212 1212 (void *)irqptr->airq_dip, irqptr->airq_vector,
1213 1213 irqptr->airq_origirq, pri));
1214 1214 }
1215 1215 mutex_exit(&airq_mutex);
1216 1216 return (rcount);
1217 1217 }
1218 1218
1219 1219 /*
1220 1220 * This function allocates "count" MSI-X vector(s) for the given "dip/pri/type"
1221 1221 */
1222 1222 int
1223 1223 apic_alloc_msix_vectors(dev_info_t *dip, int inum, int count, int pri,
1224 1224 int behavior)
1225 1225 {
1226 1226 int rcount, i;
1227 1227 major_t major;
1228 1228
1229 1229 mutex_enter(&airq_mutex);
1230 1230
1231 1231 if ((rcount = apic_navail_vector(dip, pri)) > count)
1232 1232 rcount = count;
1233 1233 else if (rcount == 0 || (rcount < count &&
1234 1234 behavior == DDI_INTR_ALLOC_STRICT)) {
1235 1235 rcount = 0;
1236 1236 goto out;
1237 1237 }
1238 1238
1239 1239 if (apic_check_free_irqs(rcount) == PSM_FAILURE) {
1240 1240 /* not enough free irq slots available */
1241 1241 rcount = 0;
1242 1242 goto out;
1243 1243 }
1244 1244
1245 1245 major = (dip != NULL) ? ddi_driver_major(dip) : 0;
1246 1246 for (i = 0; i < rcount; i++) {
1247 1247 uchar_t vector, irqno;
1248 1248 apic_irq_t *irqptr;
1249 1249
1250 1250 if ((irqno = apic_allocate_irq(apic_first_avail_irq)) ==
1251 1251 (uchar_t)-1) {
1252 1252 /*
1253 1253 * shouldn't happen because of the
1254 1254 * apic_check_free_irqs() check earlier
1255 1255 */
1256 1256 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msix_vectors: "
1257 1257 "apic_allocate_irq failed\n"));
1258 1258 rcount = i;
1259 1259 goto out;
1260 1260 }
1261 1261 if ((vector = apic_allocate_vector(pri, irqno, 1)) == 0) {
1262 1262 /*
1263 1263 * shouldn't happen because of the
1264 1264 * apic_navail_vector() call earlier
1265 1265 */
1266 1266 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msix_vectors: "
1267 1267 "apic_allocate_vector failed\n"));
1268 1268 rcount = i;
1269 1269 goto out;
1270 1270 }
1271 1271 apic_max_device_irq = max(irqno, apic_max_device_irq);
1272 1272 apic_min_device_irq = min(irqno, apic_min_device_irq);
1273 1273 irqptr = apic_irq_table[irqno];
1274 1274 irqptr->airq_vector = (uchar_t)vector;
1275 1275 irqptr->airq_ipl = pri;
1276 1276 irqptr->airq_origirq = (uchar_t)(inum + i);
1277 1277 irqptr->airq_share_id = 0;
1278 1278 irqptr->airq_mps_intr_index = MSIX_INDEX;
1279 1279 irqptr->airq_dip = dip;
1280 1280 irqptr->airq_major = major;
1281 1281 irqptr->airq_cpu = apic_bind_intr(dip, irqno, 0xff, 0xff);
1282 1282 }
1283 1283 out:
1284 1284 mutex_exit(&airq_mutex);
1285 1285 return (rcount);
1286 1286 }
1287 1287
1288 1288 /*
1289 1289 * Allocate a free vector for irq at ipl. Takes care of merging of multiple
1290 1290 * IPLs into a single APIC level as well as stretching some IPLs onto multiple
1291 1291 * levels. APIC_HI_PRI_VECTS interrupts are reserved for high priority
1292 1292 * requests and allocated only when pri is set.
1293 1293 */
1294 1294 uchar_t
1295 1295 apic_allocate_vector(int ipl, int irq, int pri)
1296 1296 {
1297 1297 int lowest, highest, i;
1298 1298
1299 1299 highest = apic_ipltopri[ipl] + APIC_VECTOR_MASK;
1300 1300 lowest = apic_ipltopri[ipl - 1] + APIC_VECTOR_PER_IPL;
1301 1301
1302 1302 if (highest < lowest) /* Both ipl and ipl - 1 map to same pri */
1303 1303 lowest -= APIC_VECTOR_PER_IPL;
1304 1304
1305 1305 #ifdef DEBUG
1306 1306 if (apic_restrict_vector) /* for testing shared interrupt logic */
1307 1307 highest = lowest + apic_restrict_vector + APIC_HI_PRI_VECTS;
1308 1308 #endif /* DEBUG */
1309 1309 if (pri == 0)
1310 1310 highest -= APIC_HI_PRI_VECTS;
1311 1311
1312 1312 for (i = lowest; i <= highest; i++) {
1313 1313 if (APIC_CHECK_RESERVE_VECTORS(i))
1314 1314 continue;
1315 1315 if (apic_vector_to_irq[i] == APIC_RESV_IRQ) {
1316 1316 apic_vector_to_irq[i] = (uchar_t)irq;
1317 1317 return (i);
1318 1318 }
1319 1319 }
1320 1320
1321 1321 return (0);
1322 1322 }
1323 1323
1324 1324 /* Mark vector as not being used by any irq */
1325 1325 void
1326 1326 apic_free_vector(uchar_t vector)
1327 1327 {
1328 1328 apic_vector_to_irq[vector] = APIC_RESV_IRQ;
1329 1329 }
1330 1330
1331 1331 /*
1332 1332 * Call rebind to do the actual programming.
1333 1333 * Must be called with interrupts disabled and apic_ioapic_lock held
1334 1334 * 'p' is polymorphic -- if this function is called to process a deferred
1335 1335 * reprogramming, p is of type 'struct ioapic_reprogram_data *', from which
1336 1336 * the irq pointer is retrieved. If not doing deferred reprogramming,
1337 1337 * p is of the type 'apic_irq_t *'.
1338 1338 *
1339 1339 * apic_ioapic_lock must be held across this call, as it protects apic_rebind
1340 1340 * and it protects apic_get_next_bind_cpu() from a race in which a CPU can be
1341 1341 * taken offline after a cpu is selected, but before apic_rebind is called to
1342 1342 * bind interrupts to it.
1343 1343 */
1344 1344 int
1345 1345 apic_setup_io_intr(void *p, int irq, boolean_t deferred)
1346 1346 {
1347 1347 apic_irq_t *irqptr;
1348 1348 struct ioapic_reprogram_data *drep = NULL;
1349 1349 int rv;
1350 1350
1351 1351 if (deferred) {
1352 1352 drep = (struct ioapic_reprogram_data *)p;
1353 1353 ASSERT(drep != NULL);
1354 1354 irqptr = drep->irqp;
1355 1355 } else
1356 1356 irqptr = (apic_irq_t *)p;
1357 1357
1358 1358 ASSERT(irqptr != NULL);
1359 1359
1360 1360 rv = apic_rebind(irqptr, apic_irq_table[irq]->airq_cpu, drep);
1361 1361 if (rv) {
1362 1362 /*
1363 1363 * CPU is not up or interrupts are disabled. Fall back to
1364 1364 * the first available CPU
1365 1365 */
1366 1366 rv = apic_rebind(irqptr, apic_find_cpu(APIC_CPU_INTR_ENABLE),
1367 1367 drep);
1368 1368 }
1369 1369
1370 1370 return (rv);
1371 1371 }
1372 1372
1373 1373
1374 1374 uchar_t
1375 1375 apic_modify_vector(uchar_t vector, int irq)
1376 1376 {
1377 1377 apic_vector_to_irq[vector] = (uchar_t)irq;
1378 1378 return (vector);
1379 1379 }
1380 1380
1381 1381 char *
1382 1382 apic_get_apic_type(void)
1383 1383 {
1384 1384 return (apic_psm_info.p_mach_idstring);
1385 1385 }
1386 1386
1387 1387 void
1388 1388 x2apic_update_psm(void)
1389 1389 {
1390 1390 struct psm_ops *pops = &apic_ops;
1391 1391
1392 1392 ASSERT(pops != NULL);
1393 1393
1394 1394 pops->psm_intr_exit = x2apic_intr_exit;
1395 1395 pops->psm_setspl = x2apic_setspl;
1396 1396
1397 1397 pops->psm_send_ipi = x2apic_send_ipi;
1398 1398 send_dirintf = pops->psm_send_ipi;
1399 1399
1400 1400 apic_mode = LOCAL_X2APIC;
1401 1401 apic_change_ops();
1402 1402 }
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