1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright (c) 1993, 2010, Oracle and/or its affiliates. All rights reserved.
24 */
25 /*
26 * Copyright (c) 2010, Intel Corporation.
27 * All rights reserved.
28 */
29 /*
30 * Copyright (c) 2013, Joyent, Inc. All rights reserved.
31 */
32
33 /*
34 * To understand how the pcplusmp module interacts with the interrupt subsystem
35 * read the theory statement in uts/i86pc/os/intr.c.
36 */
37
38 /*
39 * PSMI 1.1 extensions are supported only in 2.6 and later versions.
40 * PSMI 1.2 extensions are supported only in 2.7 and later versions.
41 * PSMI 1.3 and 1.4 extensions are supported in Solaris 10.
42 * PSMI 1.5 extensions are supported in Solaris Nevada.
43 * PSMI 1.6 extensions are supported in Solaris Nevada.
44 * PSMI 1.7 extensions are supported in Solaris Nevada.
45 */
46 #define PSMI_1_7
47
48 #include <sys/processor.h>
49 #include <sys/time.h>
50 #include <sys/psm.h>
51 #include <sys/smp_impldefs.h>
52 #include <sys/cram.h>
53 #include <acpica/include/acpi.h>
54 #include <sys/acpica.h>
55 #include <sys/psm_common.h>
56 #include <sys/apic.h>
57 #include <sys/pit.h>
58 #include <sys/ddi.h>
59 #include <sys/sunddi.h>
60 #include <sys/ddi_impldefs.h>
61 #include <sys/pci.h>
62 #include <sys/promif.h>
63 #include <sys/x86_archext.h>
64 #include <sys/cpc_impl.h>
65 #include <sys/uadmin.h>
66 #include <sys/panic.h>
67 #include <sys/debug.h>
68 #include <sys/archsystm.h>
69 #include <sys/trap.h>
70 #include <sys/machsystm.h>
71 #include <sys/sysmacros.h>
72 #include <sys/cpuvar.h>
73 #include <sys/rm_platter.h>
74 #include <sys/privregs.h>
75 #include <sys/note.h>
76 #include <sys/pci_intr_lib.h>
77 #include <sys/spl.h>
78 #include <sys/clock.h>
79 #include <sys/cyclic.h>
80 #include <sys/dditypes.h>
81 #include <sys/sunddi.h>
82 #include <sys/x_call.h>
83 #include <sys/reboot.h>
84 #include <sys/hpet.h>
85 #include <sys/apic_common.h>
86 #include <sys/apic_timer.h>
87
88 /*
89 * Local Function Prototypes
90 */
91 static void apic_init_intr(void);
92
93 /*
94 * standard MP entries
95 */
96 static int apic_probe(void);
97 static int apic_getclkirq(int ipl);
98 static void apic_init(void);
99 static void apic_picinit(void);
100 static int apic_post_cpu_start(void);
101 static int apic_intr_enter(int ipl, int *vect);
102 static void apic_setspl(int ipl);
103 static void x2apic_setspl(int ipl);
104 static int apic_addspl(int ipl, int vector, int min_ipl, int max_ipl);
105 static int apic_delspl(int ipl, int vector, int min_ipl, int max_ipl);
106 static int apic_disable_intr(processorid_t cpun);
107 static void apic_enable_intr(processorid_t cpun);
108 static int apic_get_ipivect(int ipl, int type);
109 static void apic_post_cyclic_setup(void *arg);
110
111 /*
112 * The following vector assignments influence the value of ipltopri and
113 * vectortoipl. Note that vectors 0 - 0x1f are not used. We can program
114 * idle to 0 and IPL 0 to 0xf to differentiate idle in case
115 * we care to do so in future. Note some IPLs which are rarely used
116 * will share the vector ranges and heavily used IPLs (5 and 6) have
117 * a wide range.
118 *
119 * This array is used to initialize apic_ipls[] (in apic_init()).
120 *
121 * IPL Vector range. as passed to intr_enter
122 * 0 none.
123 * 1,2,3 0x20-0x2f 0x0-0xf
124 * 4 0x30-0x3f 0x10-0x1f
125 * 5 0x40-0x5f 0x20-0x3f
126 * 6 0x60-0x7f 0x40-0x5f
127 * 7,8,9 0x80-0x8f 0x60-0x6f
128 * 10 0x90-0x9f 0x70-0x7f
129 * 11 0xa0-0xaf 0x80-0x8f
130 * ... ...
131 * 15 0xe0-0xef 0xc0-0xcf
132 * 15 0xf0-0xff 0xd0-0xdf
133 */
134 uchar_t apic_vectortoipl[APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL] = {
135 3, 4, 5, 5, 6, 6, 9, 10, 11, 12, 13, 14, 15, 15
136 };
137 /*
138 * The ipl of an ISR at vector X is apic_vectortoipl[X>>4]
139 * NOTE that this is vector as passed into intr_enter which is
140 * programmed vector - 0x20 (APIC_BASE_VECT)
141 */
142
143 uchar_t apic_ipltopri[MAXIPL + 1]; /* unix ipl to apic pri */
144 /* The taskpri to be programmed into apic to mask given ipl */
145
146 #if defined(__amd64)
147 uchar_t apic_cr8pri[MAXIPL + 1]; /* unix ipl to cr8 pri */
148 #endif
149
150 /*
151 * Correlation of the hardware vector to the IPL in use, initialized
152 * from apic_vectortoipl[] in apic_init(). The final IPLs may not correlate
153 * to the IPLs in apic_vectortoipl on some systems that share interrupt lines
154 * connected to errata-stricken IOAPICs
155 */
156 uchar_t apic_ipls[APIC_AVAIL_VECTOR];
157
158 /*
159 * Patchable global variables.
160 */
161 int apic_enable_hwsoftint = 0; /* 0 - disable, 1 - enable */
162 int apic_enable_bind_log = 1; /* 1 - display interrupt binding log */
163
164 /*
165 * Local static data
166 */
167 static struct psm_ops apic_ops = {
168 apic_probe,
169
170 apic_init,
171 apic_picinit,
172 apic_intr_enter,
173 apic_intr_exit,
174 apic_setspl,
175 apic_addspl,
176 apic_delspl,
177 apic_disable_intr,
178 apic_enable_intr,
179 (int (*)(int))NULL, /* psm_softlvl_to_irq */
180 (void (*)(int))NULL, /* psm_set_softintr */
181
182 apic_set_idlecpu,
183 apic_unset_idlecpu,
184
185 apic_clkinit,
186 apic_getclkirq,
187 (void (*)(void))NULL, /* psm_hrtimeinit */
188 apic_gethrtime,
189
190 apic_get_next_processorid,
191 apic_cpu_start,
192 apic_post_cpu_start,
193 apic_shutdown,
194 apic_get_ipivect,
195 apic_send_ipi,
196
197 (int (*)(dev_info_t *, int))NULL, /* psm_translate_irq */
198 (void (*)(int, char *))NULL, /* psm_notify_error */
199 (void (*)(int))NULL, /* psm_notify_func */
200 apic_timer_reprogram,
201 apic_timer_enable,
202 apic_timer_disable,
203 apic_post_cyclic_setup,
204 apic_preshutdown,
205 apic_intr_ops, /* Advanced DDI Interrupt framework */
206 apic_state, /* save, restore apic state for S3 */
207 apic_cpu_ops, /* CPU control interface. */
208 };
209
210 struct psm_ops *psmops = &apic_ops;
211
212 static struct psm_info apic_psm_info = {
213 PSM_INFO_VER01_7, /* version */
214 PSM_OWN_EXCLUSIVE, /* ownership */
215 (struct psm_ops *)&apic_ops, /* operation */
216 APIC_PCPLUSMP_NAME, /* machine name */
217 "pcplusmp v1.4 compatible",
218 };
219
220 static void *apic_hdlp;
221
222 /*
223 * apic_let_idle_redistribute can have the following values:
224 * 0 - If clock decremented it from 1 to 0, clock has to call redistribute.
225 * apic_redistribute_lock prevents multiple idle cpus from redistributing
226 */
227 int apic_num_idle_redistributions = 0;
228 static int apic_let_idle_redistribute = 0;
229
230 /* to gather intr data and redistribute */
231 static void apic_redistribute_compute(void);
232
233 /*
234 * This is the loadable module wrapper
235 */
236
237 int
238 _init(void)
239 {
240 if (apic_coarse_hrtime)
241 apic_ops.psm_gethrtime = &apic_gettime;
242 return (psm_mod_init(&apic_hdlp, &apic_psm_info));
243 }
244
245 int
246 _fini(void)
247 {
248 return (psm_mod_fini(&apic_hdlp, &apic_psm_info));
249 }
250
251 int
252 _info(struct modinfo *modinfop)
253 {
254 return (psm_mod_info(&apic_hdlp, &apic_psm_info, modinfop));
255 }
256
257 static int
258 apic_probe(void)
259 {
260 /* check if apix is initialized */
261 if (apix_enable && apix_loaded())
262 return (PSM_FAILURE);
263 else
264 apix_enable = 0; /* continue using pcplusmp PSM */
265
266 return (apic_probe_common(apic_psm_info.p_mach_idstring));
267 }
268
269 static uchar_t
270 apic_xlate_vector_by_irq(uchar_t irq)
271 {
272 if (apic_irq_table[irq] == NULL)
273 return (0);
274
275 return (apic_irq_table[irq]->airq_vector);
276 }
277
278 void
279 apic_init(void)
280 {
281 int i;
282 int j = 1;
283
284 psm_get_ioapicid = apic_get_ioapicid;
285 psm_get_localapicid = apic_get_localapicid;
286 psm_xlate_vector_by_irq = apic_xlate_vector_by_irq;
287
288 apic_ipltopri[0] = APIC_VECTOR_PER_IPL; /* leave 0 for idle */
289 for (i = 0; i < (APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL); i++) {
290 if ((i < ((APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL) - 1)) &&
291 (apic_vectortoipl[i + 1] == apic_vectortoipl[i]))
292 /* get to highest vector at the same ipl */
293 continue;
294 for (; j <= apic_vectortoipl[i]; j++) {
295 apic_ipltopri[j] = (i << APIC_IPL_SHIFT) +
296 APIC_BASE_VECT;
297 }
298 }
299 for (; j < MAXIPL + 1; j++)
300 /* fill up any empty ipltopri slots */
301 apic_ipltopri[j] = (i << APIC_IPL_SHIFT) + APIC_BASE_VECT;
302 apic_init_common();
303 #if defined(__amd64)
304 /*
305 * Make cpu-specific interrupt info point to cr8pri vector
306 */
307 for (i = 0; i <= MAXIPL; i++)
308 apic_cr8pri[i] = apic_ipltopri[i] >> APIC_IPL_SHIFT;
309 CPU->cpu_pri_data = apic_cr8pri;
310 #else
311 if (cpuid_have_cr8access(CPU))
312 apic_have_32bit_cr8 = 1;
313 #endif /* __amd64 */
314 }
315
316 static void
317 apic_init_intr(void)
318 {
319 processorid_t cpun = psm_get_cpu_id();
320 uint_t nlvt;
321 uint32_t svr = AV_UNIT_ENABLE | APIC_SPUR_INTR;
322
323 apic_reg_ops->apic_write_task_reg(APIC_MASK_ALL);
324
325 if (apic_mode == LOCAL_APIC) {
326 /*
327 * We are running APIC in MMIO mode.
328 */
329 if (apic_flat_model) {
330 apic_reg_ops->apic_write(APIC_FORMAT_REG,
331 APIC_FLAT_MODEL);
332 } else {
333 apic_reg_ops->apic_write(APIC_FORMAT_REG,
334 APIC_CLUSTER_MODEL);
335 }
336
337 apic_reg_ops->apic_write(APIC_DEST_REG,
338 AV_HIGH_ORDER >> cpun);
339 }
340
341 if (apic_directed_EOI_supported()) {
342 /*
343 * Setting the 12th bit in the Spurious Interrupt Vector
344 * Register suppresses broadcast EOIs generated by the local
345 * APIC. The suppression of broadcast EOIs happens only when
346 * interrupts are level-triggered.
347 */
348 svr |= APIC_SVR_SUPPRESS_BROADCAST_EOI;
349 }
350
351 /* need to enable APIC before unmasking NMI */
352 apic_reg_ops->apic_write(APIC_SPUR_INT_REG, svr);
353
354 /*
355 * Presence of an invalid vector with delivery mode AV_FIXED can
356 * cause an error interrupt, even if the entry is masked...so
357 * write a valid vector to LVT entries along with the mask bit
358 */
359
360 /* All APICs have timer and LINT0/1 */
361 apic_reg_ops->apic_write(APIC_LOCAL_TIMER, AV_MASK|APIC_RESV_IRQ);
362 apic_reg_ops->apic_write(APIC_INT_VECT0, AV_MASK|APIC_RESV_IRQ);
363 apic_reg_ops->apic_write(APIC_INT_VECT1, AV_NMI); /* enable NMI */
364
365 /*
366 * On integrated APICs, the number of LVT entries is
367 * 'Max LVT entry' + 1; on 82489DX's (non-integrated
368 * APICs), nlvt is "3" (LINT0, LINT1, and timer)
369 */
370
371 if (apic_cpus[cpun].aci_local_ver < APIC_INTEGRATED_VERS) {
372 nlvt = 3;
373 } else {
374 nlvt = ((apic_reg_ops->apic_read(APIC_VERS_REG) >> 16) &
375 0xFF) + 1;
376 }
377
378 if (nlvt >= 5) {
379 /* Enable performance counter overflow interrupt */
380
381 if (!is_x86_feature(x86_featureset, X86FSET_MSR))
382 apic_enable_cpcovf_intr = 0;
383 if (apic_enable_cpcovf_intr) {
384 if (apic_cpcovf_vect == 0) {
385 int ipl = APIC_PCINT_IPL;
386 int irq = apic_get_ipivect(ipl, -1);
387
388 ASSERT(irq != -1);
389 apic_cpcovf_vect =
390 apic_irq_table[irq]->airq_vector;
391 ASSERT(apic_cpcovf_vect);
392 (void) add_avintr(NULL, ipl,
393 (avfunc)kcpc_hw_overflow_intr,
394 "apic pcint", irq, NULL, NULL, NULL, NULL);
395 kcpc_hw_overflow_intr_installed = 1;
396 kcpc_hw_enable_cpc_intr =
397 apic_cpcovf_mask_clear;
398 }
399 apic_reg_ops->apic_write(APIC_PCINT_VECT,
400 apic_cpcovf_vect);
401 }
402 }
403
404 if (nlvt >= 6) {
405 /* Only mask TM intr if the BIOS apparently doesn't use it */
406
407 uint32_t lvtval;
408
409 lvtval = apic_reg_ops->apic_read(APIC_THERM_VECT);
410 if (((lvtval & AV_MASK) == AV_MASK) ||
411 ((lvtval & AV_DELIV_MODE) != AV_SMI)) {
412 apic_reg_ops->apic_write(APIC_THERM_VECT,
413 AV_MASK|APIC_RESV_IRQ);
414 }
415 }
416
417 /* Enable error interrupt */
418
419 if (nlvt >= 4 && apic_enable_error_intr) {
420 if (apic_errvect == 0) {
421 int ipl = 0xf; /* get highest priority intr */
422 int irq = apic_get_ipivect(ipl, -1);
423
424 ASSERT(irq != -1);
425 apic_errvect = apic_irq_table[irq]->airq_vector;
426 ASSERT(apic_errvect);
427 /*
428 * Not PSMI compliant, but we are going to merge
429 * with ON anyway
430 */
431 (void) add_avintr((void *)NULL, ipl,
432 (avfunc)apic_error_intr, "apic error intr",
433 irq, NULL, NULL, NULL, NULL);
434 }
435 apic_reg_ops->apic_write(APIC_ERR_VECT, apic_errvect);
436 apic_reg_ops->apic_write(APIC_ERROR_STATUS, 0);
437 apic_reg_ops->apic_write(APIC_ERROR_STATUS, 0);
438 }
439
440 /* Enable CMCI interrupt */
441 if (cmi_enable_cmci) {
442
443 mutex_enter(&cmci_cpu_setup_lock);
444 if (cmci_cpu_setup_registered == 0) {
445 mutex_enter(&cpu_lock);
446 register_cpu_setup_func(cmci_cpu_setup, NULL);
447 mutex_exit(&cpu_lock);
448 cmci_cpu_setup_registered = 1;
449 }
450 mutex_exit(&cmci_cpu_setup_lock);
451
452 if (apic_cmci_vect == 0) {
453 int ipl = 0x2;
454 int irq = apic_get_ipivect(ipl, -1);
455
456 ASSERT(irq != -1);
457 apic_cmci_vect = apic_irq_table[irq]->airq_vector;
458 ASSERT(apic_cmci_vect);
459
460 (void) add_avintr(NULL, ipl,
461 (avfunc)cmi_cmci_trap,
462 "apic cmci intr", irq, NULL, NULL, NULL, NULL);
463 }
464 apic_reg_ops->apic_write(APIC_CMCI_VECT, apic_cmci_vect);
465 }
466 }
467
468 static void
469 apic_picinit(void)
470 {
471 int i, j;
472 uint_t isr;
473
474 /*
475 * Initialize and enable interrupt remapping before apic
476 * hardware initialization
477 */
478 apic_intrmap_init(apic_mode);
479
480 /*
481 * On UniSys Model 6520, the BIOS leaves vector 0x20 isr
482 * bit on without clearing it with EOI. Since softint
483 * uses vector 0x20 to interrupt itself, so softint will
484 * not work on this machine. In order to fix this problem
485 * a check is made to verify all the isr bits are clear.
486 * If not, EOIs are issued to clear the bits.
487 */
488 for (i = 7; i >= 1; i--) {
489 isr = apic_reg_ops->apic_read(APIC_ISR_REG + (i * 4));
490 if (isr != 0)
491 for (j = 0; ((j < 32) && (isr != 0)); j++)
492 if (isr & (1 << j)) {
493 apic_reg_ops->apic_write(
494 APIC_EOI_REG, 0);
495 isr &= ~(1 << j);
496 apic_error |= APIC_ERR_BOOT_EOI;
497 }
498 }
499
500 /* set a flag so we know we have run apic_picinit() */
501 apic_picinit_called = 1;
502 LOCK_INIT_CLEAR(&apic_gethrtime_lock);
503 LOCK_INIT_CLEAR(&apic_ioapic_lock);
504 LOCK_INIT_CLEAR(&apic_error_lock);
505 LOCK_INIT_CLEAR(&apic_mode_switch_lock);
506
507 picsetup(); /* initialise the 8259 */
508
509 /* add nmi handler - least priority nmi handler */
510 LOCK_INIT_CLEAR(&apic_nmi_lock);
511
512 if (!psm_add_nmintr(0, (avfunc) apic_nmi_intr,
513 "pcplusmp NMI handler", (caddr_t)NULL))
514 cmn_err(CE_WARN, "pcplusmp: Unable to add nmi handler");
515
516 /*
517 * Check for directed-EOI capability in the local APIC.
518 */
519 if (apic_directed_EOI_supported() == 1) {
520 apic_set_directed_EOI_handler();
521 }
522
523 apic_init_intr();
524
525 /* enable apic mode if imcr present */
526 if (apic_imcrp) {
527 outb(APIC_IMCR_P1, (uchar_t)APIC_IMCR_SELECT);
528 outb(APIC_IMCR_P2, (uchar_t)APIC_IMCR_APIC);
529 }
530
531 ioapic_init_intr(IOAPIC_MASK);
532 }
533
534 #ifdef DEBUG
535 void
536 apic_break(void)
537 {
538 }
539 #endif /* DEBUG */
540
541 /*
542 * platform_intr_enter
543 *
544 * Called at the beginning of the interrupt service routine to
545 * mask all level equal to and below the interrupt priority
546 * of the interrupting vector. An EOI should be given to
547 * the interrupt controller to enable other HW interrupts.
548 *
549 * Return -1 for spurious interrupts
550 *
551 */
552 /*ARGSUSED*/
553 static int
554 apic_intr_enter(int ipl, int *vectorp)
555 {
556 uchar_t vector;
557 int nipl;
558 int irq;
559 ulong_t iflag;
560 apic_cpus_info_t *cpu_infop;
561
562 /*
563 * The real vector delivered is (*vectorp + 0x20), but our caller
564 * subtracts 0x20 from the vector before passing it to us.
565 * (That's why APIC_BASE_VECT is 0x20.)
566 */
567 vector = (uchar_t)*vectorp;
568
569 /* if interrupted by the clock, increment apic_nsec_since_boot */
570 if (vector == apic_clkvect) {
571 if (!apic_oneshot) {
572 /* NOTE: this is not MT aware */
573 apic_hrtime_stamp++;
574 apic_nsec_since_boot += apic_nsec_per_intr;
575 apic_hrtime_stamp++;
576 last_count_read = apic_hertz_count;
577 apic_redistribute_compute();
578 }
579
580 /* We will avoid all the book keeping overhead for clock */
581 nipl = apic_ipls[vector];
582
583 *vectorp = apic_vector_to_irq[vector + APIC_BASE_VECT];
584 if (apic_mode == LOCAL_APIC) {
585 #if defined(__amd64)
586 setcr8((ulong_t)(apic_ipltopri[nipl] >>
587 APIC_IPL_SHIFT));
588 #else
589 if (apic_have_32bit_cr8)
590 setcr8((ulong_t)(apic_ipltopri[nipl] >>
591 APIC_IPL_SHIFT));
592 else
593 LOCAL_APIC_WRITE_REG(APIC_TASK_REG,
594 (uint32_t)apic_ipltopri[nipl]);
595 #endif
596 LOCAL_APIC_WRITE_REG(APIC_EOI_REG, 0);
597 } else {
598 X2APIC_WRITE(APIC_TASK_REG, apic_ipltopri[nipl]);
599 X2APIC_WRITE(APIC_EOI_REG, 0);
600 }
601
602 return (nipl);
603 }
604
605 cpu_infop = &apic_cpus[psm_get_cpu_id()];
606
607 if (vector == (APIC_SPUR_INTR - APIC_BASE_VECT)) {
608 cpu_infop->aci_spur_cnt++;
609 return (APIC_INT_SPURIOUS);
610 }
611
612 /* Check if the vector we got is really what we need */
613 if (apic_revector_pending) {
614 /*
615 * Disable interrupts for the duration of
616 * the vector translation to prevent a self-race for
617 * the apic_revector_lock. This cannot be done
618 * in apic_xlate_vector because it is recursive and
619 * we want the vector translation to be atomic with
620 * respect to other (higher-priority) interrupts.
621 */
622 iflag = intr_clear();
623 vector = apic_xlate_vector(vector + APIC_BASE_VECT) -
624 APIC_BASE_VECT;
625 intr_restore(iflag);
626 }
627
628 nipl = apic_ipls[vector];
629 *vectorp = irq = apic_vector_to_irq[vector + APIC_BASE_VECT];
630
631 if (apic_mode == LOCAL_APIC) {
632 #if defined(__amd64)
633 setcr8((ulong_t)(apic_ipltopri[nipl] >> APIC_IPL_SHIFT));
634 #else
635 if (apic_have_32bit_cr8)
636 setcr8((ulong_t)(apic_ipltopri[nipl] >>
637 APIC_IPL_SHIFT));
638 else
639 LOCAL_APIC_WRITE_REG(APIC_TASK_REG,
640 (uint32_t)apic_ipltopri[nipl]);
641 #endif
642 } else {
643 X2APIC_WRITE(APIC_TASK_REG, apic_ipltopri[nipl]);
644 }
645
646 cpu_infop->aci_current[nipl] = (uchar_t)irq;
647 cpu_infop->aci_curipl = (uchar_t)nipl;
648 cpu_infop->aci_ISR_in_progress |= 1 << nipl;
649
650 /*
651 * apic_level_intr could have been assimilated into the irq struct.
652 * but, having it as a character array is more efficient in terms of
653 * cache usage. So, we leave it as is.
654 */
655 if (!apic_level_intr[irq]) {
656 if (apic_mode == LOCAL_APIC) {
657 LOCAL_APIC_WRITE_REG(APIC_EOI_REG, 0);
658 } else {
659 X2APIC_WRITE(APIC_EOI_REG, 0);
660 }
661 }
662
663 #ifdef DEBUG
664 APIC_DEBUG_BUF_PUT(vector);
665 APIC_DEBUG_BUF_PUT(irq);
666 APIC_DEBUG_BUF_PUT(nipl);
667 APIC_DEBUG_BUF_PUT(psm_get_cpu_id());
668 if ((apic_stretch_interrupts) && (apic_stretch_ISR & (1 << nipl)))
669 drv_usecwait(apic_stretch_interrupts);
670
671 if (apic_break_on_cpu == psm_get_cpu_id())
672 apic_break();
673 #endif /* DEBUG */
674 return (nipl);
675 }
676
677 /*
678 * This macro is a common code used by MMIO local apic and X2APIC
679 * local apic.
680 */
681 #define APIC_INTR_EXIT() \
682 { \
683 cpu_infop = &apic_cpus[psm_get_cpu_id()]; \
684 if (apic_level_intr[irq]) \
685 apic_reg_ops->apic_send_eoi(irq); \
686 cpu_infop->aci_curipl = (uchar_t)prev_ipl; \
687 /* ISR above current pri could not be in progress */ \
688 cpu_infop->aci_ISR_in_progress &= (2 << prev_ipl) - 1; \
689 }
690
691 /*
692 * Any changes made to this function must also change X2APIC
693 * version of intr_exit.
694 */
695 void
696 apic_intr_exit(int prev_ipl, int irq)
697 {
698 apic_cpus_info_t *cpu_infop;
699
700 #if defined(__amd64)
701 setcr8((ulong_t)apic_cr8pri[prev_ipl]);
702 #else
703 if (apic_have_32bit_cr8)
704 setcr8((ulong_t)(apic_ipltopri[prev_ipl] >> APIC_IPL_SHIFT));
705 else
706 apicadr[APIC_TASK_REG] = apic_ipltopri[prev_ipl];
707 #endif
708
709 APIC_INTR_EXIT();
710 }
711
712 /*
713 * Same as apic_intr_exit() except it uses MSR rather than MMIO
714 * to access local apic registers.
715 */
716 void
717 x2apic_intr_exit(int prev_ipl, int irq)
718 {
719 apic_cpus_info_t *cpu_infop;
720
721 X2APIC_WRITE(APIC_TASK_REG, apic_ipltopri[prev_ipl]);
722 APIC_INTR_EXIT();
723 }
724
725 intr_exit_fn_t
726 psm_intr_exit_fn(void)
727 {
728 if (apic_mode == LOCAL_X2APIC)
729 return (x2apic_intr_exit);
730
731 return (apic_intr_exit);
732 }
733
734 /*
735 * Mask all interrupts below or equal to the given IPL.
736 * Any changes made to this function must also change X2APIC
737 * version of setspl.
738 */
739 static void
740 apic_setspl(int ipl)
741 {
742 #if defined(__amd64)
743 setcr8((ulong_t)apic_cr8pri[ipl]);
744 #else
745 if (apic_have_32bit_cr8)
746 setcr8((ulong_t)(apic_ipltopri[ipl] >> APIC_IPL_SHIFT));
747 else
748 apicadr[APIC_TASK_REG] = apic_ipltopri[ipl];
749 #endif
750
751 /* interrupts at ipl above this cannot be in progress */
752 apic_cpus[psm_get_cpu_id()].aci_ISR_in_progress &= (2 << ipl) - 1;
753 /*
754 * this is a patch fix for the ALR QSMP P5 machine, so that interrupts
755 * have enough time to come in before the priority is raised again
756 * during the idle() loop.
757 */
758 if (apic_setspl_delay)
759 (void) apic_reg_ops->apic_get_pri();
760 }
761
762 /*
763 * X2APIC version of setspl.
764 * Mask all interrupts below or equal to the given IPL
765 */
766 static void
767 x2apic_setspl(int ipl)
768 {
769 X2APIC_WRITE(APIC_TASK_REG, apic_ipltopri[ipl]);
770
771 /* interrupts at ipl above this cannot be in progress */
772 apic_cpus[psm_get_cpu_id()].aci_ISR_in_progress &= (2 << ipl) - 1;
773 }
774
775 /*ARGSUSED*/
776 static int
777 apic_addspl(int irqno, int ipl, int min_ipl, int max_ipl)
778 {
779 return (apic_addspl_common(irqno, ipl, min_ipl, max_ipl));
780 }
781
782 static int
783 apic_delspl(int irqno, int ipl, int min_ipl, int max_ipl)
784 {
785 return (apic_delspl_common(irqno, ipl, min_ipl, max_ipl));
786 }
787
788 static int
789 apic_post_cpu_start(void)
790 {
791 int cpun;
792 static int cpus_started = 1;
793
794 /* We know this CPU + BSP started successfully. */
795 cpus_started++;
796
797 /*
798 * On BSP we would have enabled X2APIC, if supported by processor,
799 * in acpi_probe(), but on AP we do it here.
800 *
801 * We enable X2APIC mode only if BSP is running in X2APIC & the
802 * local APIC mode of the current CPU is MMIO (xAPIC).
803 */
804 if (apic_mode == LOCAL_X2APIC && apic_detect_x2apic() &&
805 apic_local_mode() == LOCAL_APIC) {
806 apic_enable_x2apic();
807 }
808
809 /*
810 * Switch back to x2apic IPI sending method for performance when target
811 * CPU has entered x2apic mode.
812 */
813 if (apic_mode == LOCAL_X2APIC) {
814 apic_switch_ipi_callback(B_FALSE);
815 }
816
817 splx(ipltospl(LOCK_LEVEL));
818 apic_init_intr();
819
820 /*
821 * since some systems don't enable the internal cache on the non-boot
822 * cpus, so we have to enable them here
823 */
824 setcr0(getcr0() & ~(CR0_CD | CR0_NW));
825
826 #ifdef DEBUG
827 APIC_AV_PENDING_SET();
828 #else
829 if (apic_mode == LOCAL_APIC)
830 APIC_AV_PENDING_SET();
831 #endif /* DEBUG */
832
833 /*
834 * We may be booting, or resuming from suspend; aci_status will
835 * be APIC_CPU_INTR_ENABLE if coming from suspend, so we add the
836 * APIC_CPU_ONLINE flag here rather than setting aci_status completely.
837 */
838 cpun = psm_get_cpu_id();
839 apic_cpus[cpun].aci_status |= APIC_CPU_ONLINE;
840
841 apic_reg_ops->apic_write(APIC_DIVIDE_REG, apic_divide_reg_init);
842 return (PSM_SUCCESS);
843 }
844
845 /*
846 * type == -1 indicates it is an internal request. Do not change
847 * resv_vector for these requests
848 */
849 static int
850 apic_get_ipivect(int ipl, int type)
851 {
852 uchar_t vector;
853 int irq;
854
855 if ((irq = apic_allocate_irq(APIC_VECTOR(ipl))) != -1) {
856 if (vector = apic_allocate_vector(ipl, irq, 1)) {
857 apic_irq_table[irq]->airq_mps_intr_index =
858 RESERVE_INDEX;
859 apic_irq_table[irq]->airq_vector = vector;
860 if (type != -1) {
861 apic_resv_vector[ipl] = vector;
862 }
863 return (irq);
864 }
865 }
866 apic_error |= APIC_ERR_GET_IPIVECT_FAIL;
867 return (-1); /* shouldn't happen */
868 }
869
870 static int
871 apic_getclkirq(int ipl)
872 {
873 int irq;
874
875 if ((irq = apic_get_ipivect(ipl, -1)) == -1)
876 return (-1);
877 /*
878 * Note the vector in apic_clkvect for per clock handling.
879 */
880 apic_clkvect = apic_irq_table[irq]->airq_vector - APIC_BASE_VECT;
881 APIC_VERBOSE_IOAPIC((CE_NOTE, "get_clkirq: vector = %x\n",
882 apic_clkvect));
883 return (irq);
884 }
885
886 /*
887 * Try and disable all interrupts. We just assign interrupts to other
888 * processors based on policy. If any were bound by user request, we
889 * let them continue and return failure. We do not bother to check
890 * for cache affinity while rebinding.
891 */
892
893 static int
894 apic_disable_intr(processorid_t cpun)
895 {
896 int bind_cpu = 0, i, hardbound = 0;
897 apic_irq_t *irq_ptr;
898 ulong_t iflag;
899
900 iflag = intr_clear();
901 lock_set(&apic_ioapic_lock);
902
903 for (i = 0; i <= APIC_MAX_VECTOR; i++) {
904 if (apic_reprogram_info[i].done == B_FALSE) {
905 if (apic_reprogram_info[i].bindcpu == cpun) {
906 /*
907 * CPU is busy -- it's the target of
908 * a pending reprogramming attempt
909 */
910 lock_clear(&apic_ioapic_lock);
911 intr_restore(iflag);
912 return (PSM_FAILURE);
913 }
914 }
915 }
916
917 apic_cpus[cpun].aci_status &= ~APIC_CPU_INTR_ENABLE;
918
919 apic_cpus[cpun].aci_curipl = 0;
920
921 i = apic_min_device_irq;
922 for (; i <= apic_max_device_irq; i++) {
923 /*
924 * If there are bound interrupts on this cpu, then
925 * rebind them to other processors.
926 */
927 if ((irq_ptr = apic_irq_table[i]) != NULL) {
928 ASSERT((irq_ptr->airq_temp_cpu == IRQ_UNBOUND) ||
929 (irq_ptr->airq_temp_cpu == IRQ_UNINIT) ||
930 (apic_cpu_in_range(irq_ptr->airq_temp_cpu)));
931
932 if (irq_ptr->airq_temp_cpu == (cpun | IRQ_USER_BOUND)) {
933 hardbound = 1;
934 continue;
935 }
936
937 if (irq_ptr->airq_temp_cpu == cpun) {
938 do {
939 bind_cpu =
940 apic_find_cpu(APIC_CPU_INTR_ENABLE);
941 } while (apic_rebind_all(irq_ptr, bind_cpu));
942 }
943 }
944 }
945
946 lock_clear(&apic_ioapic_lock);
947 intr_restore(iflag);
948
949 if (hardbound) {
950 cmn_err(CE_WARN, "Could not disable interrupts on %d"
951 "due to user bound interrupts", cpun);
952 return (PSM_FAILURE);
953 }
954 else
955 return (PSM_SUCCESS);
956 }
957
958 /*
959 * Bind interrupts to the CPU's local APIC.
960 * Interrupts should not be bound to a CPU's local APIC until the CPU
961 * is ready to receive interrupts.
962 */
963 static void
964 apic_enable_intr(processorid_t cpun)
965 {
966 int i;
967 apic_irq_t *irq_ptr;
968 ulong_t iflag;
969
970 iflag = intr_clear();
971 lock_set(&apic_ioapic_lock);
972
973 apic_cpus[cpun].aci_status |= APIC_CPU_INTR_ENABLE;
974
975 i = apic_min_device_irq;
976 for (i = apic_min_device_irq; i <= apic_max_device_irq; i++) {
977 if ((irq_ptr = apic_irq_table[i]) != NULL) {
978 if ((irq_ptr->airq_cpu & ~IRQ_USER_BOUND) == cpun) {
979 (void) apic_rebind_all(irq_ptr,
980 irq_ptr->airq_cpu);
981 }
982 }
983 }
984
985 if (apic_cpus[cpun].aci_status & APIC_CPU_SUSPEND)
986 apic_cpus[cpun].aci_status &= ~APIC_CPU_SUSPEND;
987
988 lock_clear(&apic_ioapic_lock);
989 intr_restore(iflag);
990 }
991
992 /*
993 * If this module needs a periodic handler for the interrupt distribution, it
994 * can be added here. The argument to the periodic handler is not currently
995 * used, but is reserved for future.
996 */
997 static void
998 apic_post_cyclic_setup(void *arg)
999 {
1000 _NOTE(ARGUNUSED(arg))
1001
1002 cyc_handler_t cyh;
1003 cyc_time_t cyt;
1004
1005 /* cpu_lock is held */
1006 /* set up a periodic handler for intr redistribution */
1007
1008 /*
1009 * In peridoc mode intr redistribution processing is done in
1010 * apic_intr_enter during clk intr processing
1011 */
1012 if (!apic_oneshot)
1013 return;
1014
1015 /*
1016 * Register a periodical handler for the redistribution processing.
1017 * Though we would generally prefer to use the DDI interface for
1018 * periodic handler invocation, ddi_periodic_add(9F), we are
1019 * unfortunately already holding cpu_lock, which ddi_periodic_add will
1020 * attempt to take for us. Thus, we add our own cyclic directly:
1021 */
1022 cyh.cyh_func = (void (*)(void *))apic_redistribute_compute;
1023 cyh.cyh_arg = NULL;
1024 cyh.cyh_level = CY_LOW_LEVEL;
1025
1026 cyt.cyt_when = 0;
1027 cyt.cyt_interval = apic_redistribute_sample_interval;
1028
1029 apic_cyclic_id = cyclic_add(&cyh, &cyt);
1030 }
1031
1032 static void
1033 apic_redistribute_compute(void)
1034 {
1035 int i, j, max_busy;
1036
1037 if (apic_enable_dynamic_migration) {
1038 if (++apic_nticks == apic_sample_factor_redistribution) {
1039 /*
1040 * Time to call apic_intr_redistribute().
1041 * reset apic_nticks. This will cause max_busy
1042 * to be calculated below and if it is more than
1043 * apic_int_busy, we will do the whole thing
1044 */
1045 apic_nticks = 0;
1046 }
1047 max_busy = 0;
1048 for (i = 0; i < apic_nproc; i++) {
1049 if (!apic_cpu_in_range(i))
1050 continue;
1051
1052 /*
1053 * Check if curipl is non zero & if ISR is in
1054 * progress
1055 */
1056 if (((j = apic_cpus[i].aci_curipl) != 0) &&
1057 (apic_cpus[i].aci_ISR_in_progress & (1 << j))) {
1058
1059 int irq;
1060 apic_cpus[i].aci_busy++;
1061 irq = apic_cpus[i].aci_current[j];
1062 apic_irq_table[irq]->airq_busy++;
1063 }
1064
1065 if (!apic_nticks &&
1066 (apic_cpus[i].aci_busy > max_busy))
1067 max_busy = apic_cpus[i].aci_busy;
1068 }
1069 if (!apic_nticks) {
1070 if (max_busy > apic_int_busy_mark) {
1071 /*
1072 * We could make the following check be
1073 * skipped > 1 in which case, we get a
1074 * redistribution at half the busy mark (due to
1075 * double interval). Need to be able to collect
1076 * more empirical data to decide if that is a
1077 * good strategy. Punt for now.
1078 */
1079 if (apic_skipped_redistribute) {
1080 apic_cleanup_busy();
1081 apic_skipped_redistribute = 0;
1082 } else {
1083 apic_intr_redistribute();
1084 }
1085 } else
1086 apic_skipped_redistribute++;
1087 }
1088 }
1089 }
1090
1091
1092 /*
1093 * The following functions are in the platform specific file so that they
1094 * can be different functions depending on whether we are running on
1095 * bare metal or a hypervisor.
1096 */
1097
1098 /*
1099 * Check to make sure there are enough irq slots
1100 */
1101 int
1102 apic_check_free_irqs(int count)
1103 {
1104 int i, avail;
1105
1106 avail = 0;
1107 for (i = APIC_FIRST_FREE_IRQ; i < APIC_RESV_IRQ; i++) {
1108 if ((apic_irq_table[i] == NULL) ||
1109 apic_irq_table[i]->airq_mps_intr_index == FREE_INDEX) {
1110 if (++avail >= count)
1111 return (PSM_SUCCESS);
1112 }
1113 }
1114 return (PSM_FAILURE);
1115 }
1116
1117 /*
1118 * This function allocates "count" MSI vector(s) for the given "dip/pri/type"
1119 */
1120 int
1121 apic_alloc_msi_vectors(dev_info_t *dip, int inum, int count, int pri,
1122 int behavior)
1123 {
1124 int rcount, i;
1125 uchar_t start, irqno;
1126 uint32_t cpu;
1127 major_t major;
1128 apic_irq_t *irqptr;
1129
1130 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: dip=0x%p "
1131 "inum=0x%x pri=0x%x count=0x%x behavior=%d\n",
1132 (void *)dip, inum, pri, count, behavior));
1133
1134 if (count > 1) {
1135 if (behavior == DDI_INTR_ALLOC_STRICT &&
1136 apic_multi_msi_enable == 0)
1137 return (0);
1138 if (apic_multi_msi_enable == 0)
1139 count = 1;
1140 }
1141
1142 if ((rcount = apic_navail_vector(dip, pri)) > count)
1143 rcount = count;
1144 else if (rcount == 0 || (rcount < count &&
1145 behavior == DDI_INTR_ALLOC_STRICT))
1146 return (0);
1147
1148 /* if not ISP2, then round it down */
1149 if (!ISP2(rcount))
1150 rcount = 1 << (highbit(rcount) - 1);
1151
1152 mutex_enter(&airq_mutex);
1153
1154 for (start = 0; rcount > 0; rcount >>= 1) {
1155 if ((start = apic_find_multi_vectors(pri, rcount)) != 0 ||
1156 behavior == DDI_INTR_ALLOC_STRICT)
1157 break;
1158 }
1159
1160 if (start == 0) {
1161 /* no vector available */
1162 mutex_exit(&airq_mutex);
1163 return (0);
1164 }
1165
1166 if (apic_check_free_irqs(rcount) == PSM_FAILURE) {
1167 /* not enough free irq slots available */
1168 mutex_exit(&airq_mutex);
1169 return (0);
1170 }
1171
1172 major = (dip != NULL) ? ddi_driver_major(dip) : 0;
1173 for (i = 0; i < rcount; i++) {
1174 if ((irqno = apic_allocate_irq(apic_first_avail_irq)) ==
1175 (uchar_t)-1) {
1176 /*
1177 * shouldn't happen because of the
1178 * apic_check_free_irqs() check earlier
1179 */
1180 mutex_exit(&airq_mutex);
1181 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: "
1182 "apic_allocate_irq failed\n"));
1183 return (i);
1184 }
1185 apic_max_device_irq = max(irqno, apic_max_device_irq);
1186 apic_min_device_irq = min(irqno, apic_min_device_irq);
1187 irqptr = apic_irq_table[irqno];
1188 #ifdef DEBUG
1189 if (apic_vector_to_irq[start + i] != APIC_RESV_IRQ)
1190 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: "
1191 "apic_vector_to_irq is not APIC_RESV_IRQ\n"));
1192 #endif
1193 apic_vector_to_irq[start + i] = (uchar_t)irqno;
1194
1195 irqptr->airq_vector = (uchar_t)(start + i);
1196 irqptr->airq_ioapicindex = (uchar_t)inum; /* start */
1197 irqptr->airq_intin_no = (uchar_t)rcount;
1198 irqptr->airq_ipl = pri;
1199 irqptr->airq_vector = start + i;
1200 irqptr->airq_origirq = (uchar_t)(inum + i);
1201 irqptr->airq_share_id = 0;
1202 irqptr->airq_mps_intr_index = MSI_INDEX;
1203 irqptr->airq_dip = dip;
1204 irqptr->airq_major = major;
1205 if (i == 0) /* they all bound to the same cpu */
1206 cpu = irqptr->airq_cpu = apic_bind_intr(dip, irqno,
1207 0xff, 0xff);
1208 else
1209 irqptr->airq_cpu = cpu;
1210 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: irq=0x%x "
1211 "dip=0x%p vector=0x%x origirq=0x%x pri=0x%x\n", irqno,
1212 (void *)irqptr->airq_dip, irqptr->airq_vector,
1213 irqptr->airq_origirq, pri));
1214 }
1215 mutex_exit(&airq_mutex);
1216 return (rcount);
1217 }
1218
1219 /*
1220 * This function allocates "count" MSI-X vector(s) for the given "dip/pri/type"
1221 */
1222 int
1223 apic_alloc_msix_vectors(dev_info_t *dip, int inum, int count, int pri,
1224 int behavior)
1225 {
1226 int rcount, i;
1227 major_t major;
1228
1229 mutex_enter(&airq_mutex);
1230
1231 if ((rcount = apic_navail_vector(dip, pri)) > count)
1232 rcount = count;
1233 else if (rcount == 0 || (rcount < count &&
1234 behavior == DDI_INTR_ALLOC_STRICT)) {
1235 rcount = 0;
1236 goto out;
1237 }
1238
1239 if (apic_check_free_irqs(rcount) == PSM_FAILURE) {
1240 /* not enough free irq slots available */
1241 rcount = 0;
1242 goto out;
1243 }
1244
1245 major = (dip != NULL) ? ddi_driver_major(dip) : 0;
1246 for (i = 0; i < rcount; i++) {
1247 uchar_t vector, irqno;
1248 apic_irq_t *irqptr;
1249
1250 if ((irqno = apic_allocate_irq(apic_first_avail_irq)) ==
1251 (uchar_t)-1) {
1252 /*
1253 * shouldn't happen because of the
1254 * apic_check_free_irqs() check earlier
1255 */
1256 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msix_vectors: "
1257 "apic_allocate_irq failed\n"));
1258 rcount = i;
1259 goto out;
1260 }
1261 if ((vector = apic_allocate_vector(pri, irqno, 1)) == 0) {
1262 /*
1263 * shouldn't happen because of the
1264 * apic_navail_vector() call earlier
1265 */
1266 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msix_vectors: "
1267 "apic_allocate_vector failed\n"));
1268 rcount = i;
1269 goto out;
1270 }
1271 apic_max_device_irq = max(irqno, apic_max_device_irq);
1272 apic_min_device_irq = min(irqno, apic_min_device_irq);
1273 irqptr = apic_irq_table[irqno];
1274 irqptr->airq_vector = (uchar_t)vector;
1275 irqptr->airq_ipl = pri;
1276 irqptr->airq_origirq = (uchar_t)(inum + i);
1277 irqptr->airq_share_id = 0;
1278 irqptr->airq_mps_intr_index = MSIX_INDEX;
1279 irqptr->airq_dip = dip;
1280 irqptr->airq_major = major;
1281 irqptr->airq_cpu = apic_bind_intr(dip, irqno, 0xff, 0xff);
1282 }
1283 out:
1284 mutex_exit(&airq_mutex);
1285 return (rcount);
1286 }
1287
1288 /*
1289 * Allocate a free vector for irq at ipl. Takes care of merging of multiple
1290 * IPLs into a single APIC level as well as stretching some IPLs onto multiple
1291 * levels. APIC_HI_PRI_VECTS interrupts are reserved for high priority
1292 * requests and allocated only when pri is set.
1293 */
1294 uchar_t
1295 apic_allocate_vector(int ipl, int irq, int pri)
1296 {
1297 int lowest, highest, i;
1298
1299 highest = apic_ipltopri[ipl] + APIC_VECTOR_MASK;
1300 lowest = apic_ipltopri[ipl - 1] + APIC_VECTOR_PER_IPL;
1301
1302 if (highest < lowest) /* Both ipl and ipl - 1 map to same pri */
1303 lowest -= APIC_VECTOR_PER_IPL;
1304
1305 #ifdef DEBUG
1306 if (apic_restrict_vector) /* for testing shared interrupt logic */
1307 highest = lowest + apic_restrict_vector + APIC_HI_PRI_VECTS;
1308 #endif /* DEBUG */
1309 if (pri == 0)
1310 highest -= APIC_HI_PRI_VECTS;
1311
1312 for (i = lowest; i <= highest; i++) {
1313 if (APIC_CHECK_RESERVE_VECTORS(i))
1314 continue;
1315 if (apic_vector_to_irq[i] == APIC_RESV_IRQ) {
1316 apic_vector_to_irq[i] = (uchar_t)irq;
1317 return (i);
1318 }
1319 }
1320
1321 return (0);
1322 }
1323
1324 /* Mark vector as not being used by any irq */
1325 void
1326 apic_free_vector(uchar_t vector)
1327 {
1328 apic_vector_to_irq[vector] = APIC_RESV_IRQ;
1329 }
1330
1331 /*
1332 * Call rebind to do the actual programming.
1333 * Must be called with interrupts disabled and apic_ioapic_lock held
1334 * 'p' is polymorphic -- if this function is called to process a deferred
1335 * reprogramming, p is of type 'struct ioapic_reprogram_data *', from which
1336 * the irq pointer is retrieved. If not doing deferred reprogramming,
1337 * p is of the type 'apic_irq_t *'.
1338 *
1339 * apic_ioapic_lock must be held across this call, as it protects apic_rebind
1340 * and it protects apic_get_next_bind_cpu() from a race in which a CPU can be
1341 * taken offline after a cpu is selected, but before apic_rebind is called to
1342 * bind interrupts to it.
1343 */
1344 int
1345 apic_setup_io_intr(void *p, int irq, boolean_t deferred)
1346 {
1347 apic_irq_t *irqptr;
1348 struct ioapic_reprogram_data *drep = NULL;
1349 int rv;
1350
1351 if (deferred) {
1352 drep = (struct ioapic_reprogram_data *)p;
1353 ASSERT(drep != NULL);
1354 irqptr = drep->irqp;
1355 } else
1356 irqptr = (apic_irq_t *)p;
1357
1358 ASSERT(irqptr != NULL);
1359
1360 rv = apic_rebind(irqptr, apic_irq_table[irq]->airq_cpu, drep);
1361 if (rv) {
1362 /*
1363 * CPU is not up or interrupts are disabled. Fall back to
1364 * the first available CPU
1365 */
1366 rv = apic_rebind(irqptr, apic_find_cpu(APIC_CPU_INTR_ENABLE),
1367 drep);
1368 }
1369
1370 return (rv);
1371 }
1372
1373
1374 uchar_t
1375 apic_modify_vector(uchar_t vector, int irq)
1376 {
1377 apic_vector_to_irq[vector] = (uchar_t)irq;
1378 return (vector);
1379 }
1380
1381 char *
1382 apic_get_apic_type(void)
1383 {
1384 return (apic_psm_info.p_mach_idstring);
1385 }
1386
1387 void
1388 x2apic_update_psm(void)
1389 {
1390 struct psm_ops *pops = &apic_ops;
1391
1392 ASSERT(pops != NULL);
1393
1394 pops->psm_intr_exit = x2apic_intr_exit;
1395 pops->psm_setspl = x2apic_setspl;
1396
1397 pops->psm_send_ipi = x2apic_send_ipi;
1398 send_dirintf = pops->psm_send_ipi;
1399
1400 apic_mode = LOCAL_X2APIC;
1401 apic_change_ops();
1402 }