1 /*
   2  * CDDL HEADER START
   3  *
   4  * The contents of this file are subject to the terms of the
   5  * Common Development and Distribution License (the "License").
   6  * You may not use this file except in compliance with the License.
   7  *
   8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
   9  * or http://www.opensolaris.org/os/licensing.
  10  * See the License for the specific language governing permissions
  11  * and limitations under the License.
  12  *
  13  * When distributing Covered Code, include this CDDL HEADER in each
  14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
  15  * If applicable, add the following below this CDDL HEADER, with the
  16  * fields enclosed by brackets "[]" replaced with your own identifying
  17  * information: Portions Copyright [yyyy] [name of copyright owner]
  18  *
  19  * CDDL HEADER END
  20  */
  21 
  22 /*
  23  * Copyright 2008-2013 Solarflare Communications Inc.  All rights reserved.
  24  * Use is subject to license terms.
  25  */
  26 
  27 #ifndef _SYS_SFXGE_IOC_H
  28 #define _SYS_SFXGE_IOC_H
  29 
  30 #ifdef  __cplusplus
  31 extern "C" {
  32 #endif
  33 
  34 #include <sys/types.h>
  35 
  36 /* Ensure no ambiguity over structure layouts */
  37 #pragma pack(1)
  38 
  39 #define SFXGE_IOC       ('S' << 24 | 'F' << 16 | 'C' << 8)
  40 
  41 #define SFXGE_STOP_IOC  (SFXGE_IOC | 0x01)
  42 #define SFXGE_START_IOC (SFXGE_IOC | 0x02)
  43 
  44 /* MDIO was SFXGE_IOC 0x03 */
  45 
  46 /* I2C was SFXGE_IOC 0x04 */
  47 
  48 /* SPI was SFXGE_IOC 0x05 */
  49 
  50 /* BAR */
  51 
  52 #define SFXGE_BAR_IOC   (SFXGE_IOC | 0x06)
  53 
  54 typedef struct sfxge_bar_ioc_s {
  55         uint32_t        sbi_op;
  56         uint32_t        sbi_addr;
  57         uint32_t        sbi_data[4];
  58 } sfxge_bar_ioc_t;
  59 
  60 #define SFXGE_BAR_OP_READ       0x00000001
  61 #define SFXGE_BAR_OP_WRITE      0x00000002
  62 
  63 /* PCI */
  64 
  65 #define SFXGE_PCI_IOC   (SFXGE_IOC | 0x07)
  66 
  67 typedef struct sfxge_pci_ioc_s {
  68         uint32_t        spi_op;
  69         uint8_t         spi_addr;
  70         uint8_t         spi_data;
  71 } sfxge_pci_ioc_t;
  72 
  73 #define SFXGE_PCI_OP_READ       0x00000001
  74 #define SFXGE_PCI_OP_WRITE      0x00000002
  75 
  76 /* MAC */
  77 
  78 #define SFXGE_MAC_IOC   (SFXGE_IOC | 0x08)
  79 
  80 typedef struct sfxge_mac_ioc_s {
  81         uint32_t        smi_op;
  82         uint32_t        smi_data;
  83 } sfxge_mac_ioc_t;
  84 
  85 #define SFXGE_MAC_OP_LOOPBACK   0x00000001
  86 
  87 /* PHY */
  88 
  89 #define SFXGE_PHY_IOC   (SFXGE_IOC | 0x09)
  90 
  91 typedef struct sfxge_phy_ioc_s {
  92         uint32_t        spi_op;
  93         uint32_t        spi_data;
  94 } sfxge_phy_ioc_t;
  95 
  96 #define SFXGE_PHY_OP_LOOPBACK   0x00000001
  97 #define SFXGE_PHY_OP_LINK       0x00000002
  98 #define SFXGE_PHY_OP_LED        0x00000003
  99 
 100 /* SRAM */
 101 
 102 #define SFXGE_SRAM_IOC  (SFXGE_IOC | 0x0a)
 103 
 104 typedef struct sfxge_sram_ioc_s {
 105         uint32_t        ssi_op;
 106         uint32_t        ssi_data;
 107 } sfxge_sram_ioc_t;
 108 
 109 #define SFXGE_SRAM_OP_TEST      0x00000001
 110 
 111 /* TX */
 112 
 113 #define SFXGE_TX_IOC    (SFXGE_IOC | 0x0b)
 114 
 115 typedef struct sfxge_tx_ioc_s {
 116         uint32_t        sti_op;
 117         uint32_t        sti_data;
 118 } sfxge_tx_ioc_t;
 119 
 120 #define SFXGE_TX_OP_LOOPBACK    0x00000001
 121 
 122 /* RX */
 123 
 124 #define SFXGE_RX_IOC    (SFXGE_IOC | 0x0c)
 125 
 126 typedef struct sfxge_rx_ioc_s {
 127         uint32_t        sri_op;
 128         uint32_t        sri_data;
 129 } sfxge_rx_ioc_t;
 130 
 131 #define SFXGE_RX_OP_LOOPBACK    0x00000001
 132 
 133 /* NVRAM */
 134 
 135 #define SFXGE_NVRAM_IOC (SFXGE_IOC | 0x0d)
 136 
 137 typedef struct sfxge_nvram_ioc_s {
 138         uint32_t        sni_op;
 139         uint32_t        sni_type;
 140         uint32_t        sni_offset;
 141         uint32_t        sni_size;
 142         uint32_t        sni_subtype;
 143         uint16_t        sni_version[4];         /* get/set_ver */
 144         /*
 145          * Streams STRMSGSZ limit (default 64kb)
 146          * See write(2) and I_STR in streamio(7i)
 147          */
 148         uint8_t         sni_data[32*1024];      /* read/write */
 149 } sfxge_nvram_ioc_t;
 150 
 151 #define SFXGE_NVRAM_OP_SIZE             0x00000001
 152 #define SFXGE_NVRAM_OP_READ             0x00000002
 153 #define SFXGE_NVRAM_OP_WRITE            0x00000003
 154 #define SFXGE_NVRAM_OP_ERASE            0x00000004
 155 #define SFXGE_NVRAM_OP_GET_VER          0x00000005
 156 #define SFXGE_NVRAM_OP_SET_VER          0x00000006
 157 
 158 #define SFXGE_NVRAM_TYPE_BOOTROM        0x00000001
 159 #define SFXGE_NVRAM_TYPE_BOOTROM_CFG    0x00000002
 160 #define SFXGE_NVRAM_TYPE_MC             0x00000003
 161 #define SFXGE_NVRAM_TYPE_MC_GOLDEN      0x00000004
 162 #define SFXGE_NVRAM_TYPE_PHY            0x00000005
 163 #define SFXGE_NVRAM_TYPE_NULL_PHY       0x00000006
 164 #define SFXGE_NVRAM_TYPE_FPGA           0x00000007
 165 
 166 /* PHY BIST */
 167 
 168 #define SFXGE_PHY_BIST_IOC      (SFXGE_IOC | 0x0e)
 169 
 170 typedef struct sfxge_phy_bist_ioc_s {
 171         boolean_t       spbi_break_link;
 172         uint8_t         spbi_status_a;
 173         uint8_t         spbi_status_b;
 174         uint8_t         spbi_status_c;
 175         uint8_t         spbi_status_d;
 176         uint16_t        spbi_length_ind_a;
 177         uint16_t        spbi_length_ind_b;
 178         uint16_t        spbi_length_ind_c;
 179         uint16_t        spbi_length_ind_d;
 180 } sfxge_phy_bist_ioc_t;
 181 
 182 #define SFXGE_PHY_BIST_CABLE_OK                 0
 183 #define SFXGE_PHY_BIST_CABLE_INVALID            1
 184 #define SFXGE_PHY_BIST_CABLE_OPEN               2
 185 #define SFXGE_PHY_BIST_CABLE_INTRAPAIRSHORT     3
 186 #define SFXGE_PHY_BIST_CABLE_INTERPAIRSHORT     4
 187 #define SFXGE_PHY_BIST_CABLE_BUSY               5
 188 #define SFXGE_PHY_BIST_CABLE_UNKNOWN            6
 189 
 190 /* MCDI */
 191 
 192 #define SFXGE_MCDI_IOC  (SFXGE_IOC | 0x0f)
 193 
 194 typedef struct sfxge_mcdi_ioc_s {
 195         uint8_t         smi_payload[256];
 196         uint8_t         smi_cmd;
 197         uint8_t         smi_len; /* In and out */
 198         uint8_t         smi_rc;
 199 } sfxge_mcdi_ioc_t;
 200 
 201 /* Reset the NIC */
 202 
 203 #define SFXGE_NIC_RESET_IOC     (SFXGE_IOC | 0x10)
 204 
 205 /* VPD */
 206 
 207 #define SFXGE_VPD_IOC   (SFXGE_IOC | 0x11)
 208 
 209 #define SFXGE_VPD_MAX_PAYLOAD 0x100
 210 
 211 typedef struct sfxge_vpd_ioc_s {
 212         uint8_t         svi_op;
 213         uint8_t         svi_tag;
 214         uint16_t        svi_keyword;
 215         uint8_t         svi_len; /* In or out */
 216         uint8_t         svi_payload[SFXGE_VPD_MAX_PAYLOAD]; /* In or out */
 217 } sfxge_vpd_ioc_t;
 218 
 219 #define SFXGE_VPD_OP_GET_KEYWORD        0x00000001
 220 #define SFXGE_VPD_OP_SET_KEYWORD        0x00000002
 221 
 222 #pragma pack()
 223 
 224 #ifdef  __cplusplus
 225 }
 226 #endif
 227 
 228 #endif  /* _SYS_SFXGE_IOC_H */