1 /*-
2 * Copyright 2006-2013 Solarflare Communications Inc. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 */
25
26 #ifndef _SYS_XPHY_H
27 #define _SYS_XPHY_H
28
29 #include "efx.h"
30
31 #ifdef __cplusplus
32 extern "C" {
33 #endif
34
35 /*
36 * Common
37 */
38
39 /* control register 1 */
40 #define MMD_CONTROL1_REG 0x00
41 #define MMD_PMA_LOOPBACK_LBN 0
42 #define MMD_PMA_LOOPBACK_WIDTH 1
43 #define MMD_LOOPBACK_LBN 14
44 #define MMD_LOOPBACK_WIDTH 1
45 #define MMD_RESET_LBN 15
46 #define MMD_RESET_WIDTH 1
47
48 /* status register 1 */
49 #define MMD_STATUS1_REG 0x01
50 #define MMD_LINK_UP_LBN 2
51 #define MMD_LINK_UP_WIDTH 1
52 #define MMD_FAULT_LBN 7
53 #define MMD_FAULT_WIDTH 1
54
55 /* identifier registers */
56 #define MMD_IDH_REG 0x02
57 #define MMD_IDH_LBN 0
58 #define MMD_IDH_WIDTH 16
59
60 #define MMD_IDL_REG 0x03
61 #define MMD_IDL_LBN 0
62 #define MMD_IDL_WIDTH 16
63
64 /* devices in package registers */
65 #define MMD_DEVICES1_REG 0x05
66 #define PMA_PMD_PRESENT_LBN 1
67 #define PMA_PMD_PRESENT_WIDTH 1
68 #define WIS_PRESENT_LBN 2
69 #define WIS_PRESENT_WIDTH 1
70 #define PCS_PRESENT_LBN 3
71 #define PCS_PRESENT_WIDTH 1
72 #define PHY_XS_PRESENT_LBN 4
73 #define PHY_XS_PRESENT_WIDTH 1
74 #define DTE_XS_PRESENT_LBN 5
75 #define DTE_XS_PRESENT_WIDTH 1
76 #define TC_PRESENT_LBN 6
77 #define TC_PRESENT_WIDTH 1
78 #define AN_PRESENT_LBN 7
79 #define AN_PRESENT_WIDTH 1
80
81 #define MMD_DEVICES2_REG 0x06
82 #define CL22EXT_PRESENT_LBN 13
83 #define CL22EXT_PRESENT_WIDTH 1
84 #define VENDOR_DEVICE1_PRESENT_LBN 14
85 #define VENDOR_DEVICE1_PRESENT_WIDTH 1
86 #define VENDOR_DEVICE2_PRESENT_LBN 15
87 #define VENDOR_DEVICE2_PRESENT_WIDTH 1
88
89 #define MMD_STATUS2_REG 0x08
90 #define MMD_RX_FAULT_LBN 10
91 #define MMD_RX_FAULT_WIDTH 1
92 #define MMD_TX_FAULT_LBN 11
93 #define MMD_TX_FAULT_WIDTH 1
94 #define MMD_RESPONDING_LBN 14
95 #define MMD_RESPONDING_WIDTH 2
96 #define MMD_RESPONDING_DECODE 0x2 /* 10 */
97
98 /*
99 * PMA/PMD
100 */
101
102 /* control register 1 */
103 #define PMA_PMD_CONTROL1_REG 0x00
104 #define PMA_PMD_LOOPBACK_EN_LBN 0
105 #define PMA_PMD_LOOPBACK_EN_WIDTH 1
106 #define PMA_PMD_LOW_POWER_EN_LBN 11
107 #define PMA_PMD_LOW_POWER_EN_WIDTH 1
108 #define PMA_PMD_RESET_LBN 15
109 #define PMA_PMD_RESET_WIDTH 1
110
111 /* status register 1 */
112 #define PMA_PMD_STATUS1_REG 0x01
113 #define PMA_PMD_POWER_CAP_LBN 1
114 #define PMA_PMD_POWER_CAP_WIDTH 1
115 #define PMA_PMD_LINK_UP_LBN 2
116 #define PMA_PMD_LINK_UP_WIDTH 1
117 #define PMA_PMD_FAULT_LBN 7
118 #define PMA_PMD_FAULT_WIDTH 1
119
120 /* control register 2 */
121 #define PMA_PMD_CONTROL2_REG 0x07
122 #define PMA_PMD_TYPE_LBN 0
123 #define PMA_PMD_TYPE_WIDTH 4
124 #define PMA_PMD_10BASE_T_DECODE 0xf /* 1111 */
125 #define PMA_PMD_100BASE_TX_DECODE 0xe /* 1110 */
126 #define PMA_PMD_1000BASE_KX_DECODE 0xd /* 1101 */
127 #define PMA_PMD_1000BASE_T_DECODE 0xc /* 1100 */
128 #define PMA_PMD_10GBASE_KR_DECODE 0xb /* 1011 */
129 #define PMA_PMD_10GBASE_KX4_DECODE 0xa /* 1010 */
130 #define PMA_PMD_10GBASE_T_DECODE 0x9 /* 1001 */
131 #define PMA_PMD_10GBASE_LRM_DECODE 0x8 /* 1001 */
132 #define PMA_PMD_10GBASE_SR_DECODE 0x7 /* 0111 */
133 #define PMA_PMD_10GBASE_LR_DECODE 0x6 /* 0110 */
134 #define PMA_PMD_10GBASE_ER_DECODE 0x5 /* 0101 */
135 #define PMA_PMD_10GBASE_SW_DECODE 0x3 /* 0011 */
136 #define PMA_PMD_10GBASE_LW_DECODE 0x2 /* 0010 */
137 #define PMA_PMD_10GBASE_EW_DECODE 0x1 /* 0001 */
138
139 /* status register 2 */
140 #define PMA_PMD_STATUS2_REG 0x08
141 #define PMA_PMD_LOOPBACK_CAP_LBN 0
142 #define PMA_PMD_LOOPBACK_CAP_WIDTH 1
143 #define PMA_PMD_10GBASE_EW_CAP_LBN 1
144 #define PMA_PMD_10GBASE_EW_CAP_WIDTH 1
145 #define PMA_PMD_10GBASE_LW_CAP_LBN 2
146 #define PMA_PMD_10GBASE_LW_CAP_WIDTH 1
147 #define PMA_PMD_10GBASE_SW_CAP_LBN 3
148 #define PMA_PMD_10GBASE_SW_CAP_WIDTH 1
149 #define PMA_PMD_10GBASE_ER_CAP_LBN 5
150 #define PMA_PMD_10GBASE_ER_CAP_WIDTH 1
151 #define PMA_PMD_10GBASE_LR_CAP_LBN 6
152 #define PMA_PMD_10GBASE_LR_CAP_WIDTH 1
153 #define PMA_PMD_10GBASE_SR_CAP_LBN 7
154 #define PMA_PMD_10GBASE_SR_CAP_WIDTH 1
155 #define PMA_PMD_TX_DISABLE_CAP_LBN 8
156 #define PMA_PMD_TX_DISABLE_CAP_WIDTH 1
157 #define PMA_PMD_EXT_CAP_LBN 9
158 #define PMA_PMD_EXT_CAP_WIDTH 1
159 #define PMA_PMD_RX_FAULT_LBN 10
160 #define PMA_PMD_RX_FAULT_WIDTH 1
161 #define PMA_PMD_TX_FAULT_LBN 11
162 #define PMA_PMD_TX_FAULT_WIDTH 1
163 #define PMA_PMD_RX_FAULT_CAP_LBN 12
164 #define PMA_PMD_RX_FAULT_CAP_WIDTH 1
165 #define PMA_PMD_TX_FAULT_CAP_LBN 13
166 #define PMA_PMD_TX_FAULT_CAP_WIDTH 1
167 #define PMA_PMD_RESPONDING_LBN 14
168 #define PMA_PMD_RESPONDING_WIDTH 2
169 #define PMA_PMD_RESPONDING_DECODE 0x2 /* 10 */
170
171 /* extended capabilities register */
172 #define PMA_PMD_EXT_CAP_REG 0x0b
173 #define PMA_PMD_10GBASE_CX4_CAP_LBN 0
174 #define PMA_PMD_10GBASE_CX4_CAP_WIDTH 1
175 #define PMA_PMD_10GBASE_LRM_CAP_LBN 1
176 #define PMA_PMD_10GBASE_LRM_CAP_WIDTH 1
177 #define PMA_PMD_10GBASE_T_CAP_LBN 2
178 #define PMA_PMD_10GBASE_T_CAP_WIDTH 1
179 #define PMA_PMD_10GBASE_KX4_CAP_LBN 3
180 #define PMA_PMD_10GBASE_KX4_CAP_WIDTH 1
181 #define PMA_PMD_10GBASE_KR_CAP_LBN 4
182 #define PMA_PMD_10GBASE_KR_CAP_WIDTH 1
183 #define PMA_PMD_1000BASE_T_CAP_LBN 5
184 #define PMA_PMD_1000BASE_T_CAP_WIDTH 1
185 #define PMA_PMD_1000BASE_KX_CAP_LBN 6
186 #define PMA_PMD_1000BASE_KX_CAP_WIDTH 1
187 #define PMA_PMD_100BASE_TX_CAP_LBN 7
188 #define PMA_PMD_100BASE_TX_CAP_WIDTH 1
189 #define PMA_PMD_10BASE_T_CAP_LBN 8
190 #define PMA_PMD_10BASE_T_CAP_WIDTH 1
191
192 /* channel A-D signal/noise ratio registers */
193 #define PMA_PMD_CHANNELA_SNR_REG 0x85
194 #define PMA_PMD_CHANNELB_SNR_REG 0x86
195 #define PMA_PMD_CHANNELC_SNR_REG 0x87
196 #define PMA_PMD_CHANNELD_SNR_REG 0x88
197 #define PMA_PMD_CHANNELA_MIN_SNR_REG 0x89
198 #define PMA_PMD_CHANNELB_MIN_SNR_REG 0x8a
199 #define PMA_PMD_CHANNELC_MIN_SNR_REG 0x8b
200 #define PMA_PMD_CHANNELD_MIN_SNR_REG 0x8c
201 #define PMA_PMD_SNR_LBN 0
202 #define PMA_PMD_SNR_WIDTH 16
203
204 /* LASI control register */
205 #define PMA_PMD_LASI_CONTROL_REG 0x9002
206 #define PMA_PMD_LS_ALARM_EN_LBN 0
207 #define PMA_PMD_LS_ALARM_EN_WIDTH 1
208 #define PMA_PMD_TX_ALARM_EN_LBN 1
209 #define PMA_PMD_TX_ALARM_EN_WIDTH 1
210 #define PMA_PMD_RX_ALARM_EN_LBN 2
211 #define PMA_PMD_RX_ALARM_EN_WIDTH 1
212
213 /* LASI status register */
214 #define PMA_PMD_LASI_STATUS_REG 0x9005
215 #define PMA_PMD_LS_ALARM_LBN 0
216 #define PMA_PMD_LS_ALARM_WIDTH 1
217 #define PMA_PMD_TX_ALARM_LBN 1
218 #define PMA_PMD_TX_ALARM_WIDTH 1
219 #define PMA_PMD_RX_ALARM_LBN 2
220 #define PMA_PMD_RX_ALARM_WIDTH 1
221
222 /*
223 * PCS
224 */
225
226 /* control register 1 */
227 #define PCS_CONTROL1_REG 0x00
228 #define PCS_LOW_POWER_EN_LBN 11
229 #define PCS_LOW_POWER_EN_WIDTH 1
230 #define PCS_LOOPBACK_EN_LBN 14
231 #define PCS_LOOPBACK_EN_WIDTH 1
232 #define PCS_RESET_LBN 15
233 #define PCS_RESET_WIDTH 1
234
235 /* status register 1 */
236 #define PCS_STATUS1_REG 0x01
237 #define PCS_POWER_CAP_LBN 1
238 #define PCS_POWER_CAP_WIDTH 1
239 #define PCS_LINK_UP_LBN 2
240 #define PCS_LINK_UP_WIDTH 1
241 #define PCS_FAULT_LBN 7
242 #define PCS_FAULT_WIDTH 1
243
244 /* control register 2 */
245 #define PCS_CONTROL2_REG 0x07
246 #define PCS_TYPE_LBN 0
247 #define PCS_TYPE_WIDTH 2
248 #define PCS_10GBASE_T_DECODE 0x3 /* 11 */
249 #define PCS_10GBASE_W_DECODE 0x2 /* 10 */
250 #define PCS_10GBASE_X_DECODE 0x1 /* 01 */
251 #define PCS_10GBASE_R_DECODE 0x0 /* 00 */
252
253 /* 10G status register 2 */
254 #define PCS_STATUS2_REG 0x08
255 #define PCS_10GBASE_R_CAP_LBN 0
256 #define PCS_10GBASE_R_CAP_WIDTH 1
257 #define PCS_10GBASE_X_CAP_LBN 1
258 #define PCS_10GBASE_X_CAP_WIDTH 1
259 #define PCS_10GBASE_W_CAP_LBN 2
260 #define PCS_10GBASE_W_CAP_WIDTH 1
261 #define PCS_10GBASE_T_CAP_LBN 3
262 #define PCS_10GBASE_T_CAP_WIDTH 1
263 #define PCS_RX_FAULT_LBN 10
264 #define PCS_RX_FAULT_WIDTH 1
265 #define PCS_TX_FAULT_LBN 11
266 #define PCS_TX_FAULT_WIDTH 1
267 #define PCS_RESPONDING_LBN 14
268 #define PCS_RESPONDING_WIDTH 2
269 #define PCS_RESPONDING_DECODE 0x2 /* 10 */
270
271 /* 10G-BASE-T/R status register 2 */
272 #define PCS_10GBASE_T_STATUS2_REG 0x21
273 #define PCS_10GBASE_R_STATUS2_REG 0x21
274 #define PCS_ERR_LBN 0
275 #define PCS_ERR_WIDTH 7
276 #define PCS_BER_LBN 8
277 #define PCS_BER_WIDTH 6
278 #define PCS_HIGH_BER_LBN 14
279 #define PCS_HIGH_BER_WIDTH 1
280 #define PCS_BLOCK_LOCK_LBN 15
281 #define PCS_BLOCK_LOCK_WIDTH 1
282
283 /*
284 * PHY_XS
285 */
286
287 /* control register 1 */
288 #define PHY_XS_CONTROL1_REG 0x00
289 #define PHY_XS_LOW_POWER_EN_LBN 11
290 #define PHY_XS_LOW_POWER_EN_WIDTH 1
291 #define PHY_XS_LOOPBACK_EN_LBN 14
292 #define PHY_XS_LOOPBACK_EN_WIDTH 1
293 #define PHY_XS_RESET_LBN 15
294 #define PHY_XS_RESET_WIDTH 1
295
296 /* status register 1 */
297 #define PHY_XS_STATUS1_REG 0x01
298 #define PHY_XS_POWER_CAP_LBN 1
299 #define PHY_XS_POWER_CAP_WIDTH 1
300 #define PHY_XS_LINK_UP_LBN 2
301 #define PHY_XS_LINK_UP_WIDTH 1
302 #define PHY_XS_FAULT_LBN 7
303 #define PHY_XS_FAULT_WIDTH 1
304
305 /* no control register 2 */
306
307 /* status register 2 */
308 #define PHY_XS_STATUS2_REG 0x08
309 #define PHY_XS_RX_FAULT_LBN 10
310 #define PHY_XS_RX_FAULT_WIDTH 1
311 #define PHY_XS_TX_FAULT_LBN 11
312 #define PHY_XS_TX_FAULT_WIDTH 1
313 #define PHY_XS_RESPONDING_LBN 14
314 #define PHY_XS_RESPONDING_WIDTH 2
315 #define PHY_XS_RESPONDING_DECODE 0x2 /* 10 */
316
317 /* lane status register */
318 #define PHY_XS_LANE_STATUS_REG 0x18
319 #define PHY_XS_ALIGNED_LBN 12
320 #define PHY_XS_ALIGNED_WIDTH 1
321 #define PHY_XS_LANE0_SYNC_LBN 0
322 #define PHY_XS_LANE0_SYNC_WIDTH 1
323 #define PHY_XS_LANE1_SYNC_LBN 1
324 #define PHY_XS_LANE1_SYNC_WIDTH 1
325 #define PHY_XS_LANE2_SYNC_LBN 2
326 #define PHY_XS_LANE2_SYNC_WIDTH 1
327 #define PHY_XS_LANE3_SYNC_LBN 3
328 #define PHY_XS_LANE3_SYNC_WIDTH 1
329
330 /*
331 * DTE_XS
332 */
333
334 /* control register 1 */
335 #define DTE_XS_CONTROL1_REG 0x00
336 #define DTE_XS_LOW_POWER_EN_LBN 11
337 #define DTE_XS_LOW_POWER_EN_WIDTH 1
338 #define DTE_XS_LOOPBACK_EN_LBN 14
339 #define DTE_XS_LOOPBACK_EN_WIDTH 1
340 #define DTE_XS_RESET_LBN 15
341 #define DTE_XS_RESET_WIDTH 1
342
343 /* status register 1 */
344 #define DTE_XS_STATUS1_REG 0x01
345 #define DTE_XS_POWER_CAP_LBN 1
346 #define DTE_XS_POWER_CAP_WIDTH 1
347 #define DTE_XS_LINK_UP_LBN 2
348 #define DTE_XS_LINK_UP_WIDTH 1
349 #define DTE_XS_FAULT_LBN 7
350 #define DTE_XS_FAULT_WIDTH 1
351
352 /* no control register 2 */
353
354 /* status register 2 */
355 #define DTE_XS_STATUS2_REG 0x08
356 #define DTE_XS_RX_FAULT_LBN 10
357 #define DTE_XS_RX_FAULT_WIDTH 1
358 #define DTE_XS_TX_FAULT_LBN 11
359 #define DTE_XS_TX_FAULT_WIDTH 1
360 #define DTE_XS_RESPONDING_LBN 14
361 #define DTE_XS_RESPONDING_WIDTH 2
362 #define DTE_XS_RESPONDING_DECODE 0x2 /* 10 */
363
364 /* lane status register */
365 #define DTE_XS_LANE_STATUS_REG 0x18
366 #define DTE_XS_ALIGNED_LBN 12
367 #define DTE_XS_ALIGNED_WIDTH 1
368 #define DTE_XS_LANE0_SYNC_LBN 0
369 #define DTE_XS_LANE0_SYNC_WIDTH 1
370 #define DTE_XS_LANE1_SYNC_LBN 1
371 #define DTE_XS_LANE1_SYNC_WIDTH 1
372 #define DTE_XS_LANE2_SYNC_LBN 2
373 #define DTE_XS_LANE2_SYNC_WIDTH 1
374 #define DTE_XS_LANE3_SYNC_LBN 3
375 #define DTE_XS_LANE3_SYNC_WIDTH 1
376
377 /*
378 * AN
379 */
380
381 /* control register 1 */
382 #define AN_CONTROL1_REG 0x00
383 #define AN_RESTART_LBN 9
384 #define AN_RESTART_WIDTH 1
385 #define AN_ENABLE_LBN 12
386 #define AN_ENABLE_WIDTH 1
387 #define AN_RESET_LBN 15
388 #define AN_RESET_WIDTH 1
389
390 /* status register 1 */
391 #define AN_STATUS1_REG 0x01
392 #define AN_LP_CAP_LBN 0
393 #define AN_LP_CAP_WIDTH 1
394 #define AN_LINK_UP_LBN 2
395 #define AN_LINK_UP_WIDTH 1
396 #define AN_FAULT_LBN 4
397 #define AN_FAULT_WIDTH 1
398 #define AN_COMPLETE_LBN 5
399 #define AN_COMPLETE_WIDTH 1
400 #define AN_PAGE_RCVD_LBN 6
401 #define AN_PAGE_RCVD_WIDTH 1
402 #define AN_XNP_CAP_LBN 7
403 #define AN_XNP_CAP_WIDTH 1
404
405 /* advertised capabilities register */
406 #define AN_ADV_BP_CAP_REG 0x10
407 #define AN_ADV_TA_10BASE_T_LBN 5
408 #define AN_ADV_TA_10BASE_T_WIDTH 1
409 #define AN_ADV_TA_10BASE_T_FDX_LBN 6
410 #define AN_ADV_TA_10BASE_T_FDX_WIDTH 1
411 #define AN_ADV_TA_100BASE_TX_LBN 7
412 #define AN_ADV_TA_100BASE_TX_WIDTH 1
413 #define AN_ADV_TA_100BASE_TX_FDX_LBN 8
414 #define AN_ADV_TA_100BASE_TX_FDX_WIDTH 1
415 #define AN_ADV_TA_100BASE_T4_LBN 9
416 #define AN_ADV_TA_100BASE_T4_WIDTH 1
417 #define AN_ADV_TA_PAUSE_LBN 10
418 #define AN_ADV_TA_PAUSE_WIDTH 1
419 #define AN_ADV_TA_ASM_DIR_LBN 11
420 #define AN_ADV_TA_ASM_DIR_WIDTH 1
421
422 /* link partner base page capabilities register */
423 #define AN_LP_BP_CAP_REG 0x13
424 #define AN_LP_TA_10BASE_T_LBN 5
425 #define AN_LP_TA_10BASE_T_WIDTH 1
426 #define AN_LP_TA_10BASE_T_FDX_LBN 6
427 #define AN_LP_TA_10BASE_T_FDX_WIDTH 1
428 #define AN_LP_TA_100BASE_TX_LBN 7
429 #define AN_LP_TA_100BASE_TX_WIDTH 1
430 #define AN_LP_TA_100BASE_TX_FDX_LBN 8
431 #define AN_LP_TA_100BASE_TX_FDX_WIDTH 1
432 #define AN_LP_TA_100BASE_T4_LBN 9
433 #define AN_LP_TA_100BASE_T4_WIDTH 1
434 #define AN_LP_TA_PAUSE_LBN 10
435 #define AN_LP_TA_PAUSE_WIDTH 1
436 #define AN_LP_TA_ASM_DIR_LBN 11
437 #define AN_LP_TA_ASM_DIR_WIDTH 1
438
439 /* 10GBASE-T control register */
440 #define AN_10G_BASE_T_CONTROL_REG 0x20
441 #define AN_10G_BASE_T_ADV_LBN 12
442 #define AN_10G_BASE_T_ADV_WIDTH 1
443
444 /* 10GBASE-T status register */
445 #define AN_10G_BASE_T_STATUS_REG 0x21
446 #define AN_10G_BASE_T_LP_LBN 11
447 #define AN_10G_BASE_T_LP_WIDTH 1
448 #define AN_CONFIG_FAULT_LBN 15
449 #define AN_CONFIG_FAULT_WIDTH 1
450 #define AN_MASTER_LBN 14
451 #define AN_MASTER_WIDTH 1
452 #define AN_LOCAL_RX_OK_LBN 13
453 #define AN_LOCAL_RX_OK_WIDTH 1
454 #define AN_REMOTE_RX_OK_LBN 12
455 #define AN_REMOTE_RX_OK_WIDTH 1
456
457 extern __checkReturn int
458 xphy_pkg_verify(
459 __in efx_nic_t *enp,
460 __in uint8_t port,
461 __in uint32_t mask);
462
463 extern __checkReturn int
464 xphy_pkg_wait(
465 __in efx_nic_t *enp,
466 __in uint8_t port,
467 __in uint32_t mask);
468
469 extern __checkReturn int
470 xphy_mmd_oui_get(
471 __in efx_nic_t *enp,
472 __in uint8_t port,
473 __in uint8_t mmd,
474 __out uint32_t *ouip);
475
476 extern __checkReturn int
477 xphy_mmd_check(
478 __in efx_nic_t *enp,
479 __in uint8_t port,
480 __in uint8_t mmd,
481 __out boolean_t *upp);
482
483 extern __checkReturn int
484 xphy_mmd_fault(
485 __in efx_nic_t *enp,
486 __in uint8_t port,
487 __out boolean_t *upp);
488
489 extern __checkReturn int
490 xphy_mmd_loopback_set(
491 __in efx_nic_t *enp,
492 __in uint8_t port,
493 __in uint8_t mmd,
494 __in boolean_t on);
495
496 #ifdef __cplusplus
497 }
498 #endif
499
500 #endif /* _SYS_XPHY_H */