1 /*-
2 * Copyright 2007-2013 Solarflare Communications Inc. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 */
25
26 #ifndef _SYS_SFX7101_IMPL_H
27 #define _SYS_SFX7101_IMPL_H
28
29 #ifdef __cplusplus
30 extern "C" {
31 #endif
32
33 #if EFSYS_OPT_PHY_SFX7101
34
35 #define SFX7101_MMD_MASK \
36 ((1 << PMA_PMD_MMD) | \
37 (1 << PCS_MMD) | \
38 (1 << PHY_XS_MMD) | \
39 (1 << AN_MMD))
40
41 /* IO expender */
42 #define PCA9539 0x74
43
44 #define P0_IN 0x00
45 #define P0_OUT 0x02
46 #define P0_INVERT 0x04
47 #define P0_CONFIG 0x06
48
49 #define P0_EN_1V0X_LBN 0
50 #define P0_EN_1V0X_WIDTH 1
51 #define P0_EN_1V2_LBN 1
52 #define P0_EN_1V2_WIDTH 1
53 #define P0_EN_2V5_LBN 2
54 #define P0_EN_2V5_WIDTH 1
55 #define P0_FLASH_CFG_EN_LBN 3
56 #define P0_FLASH_CFG_EN_WIDTH 1
57 #define P0_EN_5V_LBN 4
58 #define P0_EN_5V_WIDTH 1
59 #define P0_SHORTEN_JTAG_LBN 5
60 #define P0_SHORTEN_JTAG_WIDTH 1
61 #define P0_X_TRST_LBN 6
62 #define P0_X_TRST_WIDTH 1
63 #define P0_DSP_RESET_LBN 7
64 #define P0_DSP_RESET_WIDTH 1
65
66 #define P1_IN 0x01
67 #define P1_OUT 0x03
68 #define P1_INVERT 0x05
69 #define P1_CONFIG 0x07
70
71 #define P1_AFE_PWD_LBN 0
72 #define P1_AFE_PWD_WIDTH 1
73 #define P1_DSP_PWD25_LBN 1
74 #define P1_DSP_PWD25_WIDTH 1
75 #define P1_RESERVED_LBN 2
76 #define P1_RESERVED_WIDTH 2
77 #define P1_SPARE_LBN 4
78 #define P1_SPARE_WIDTH 4
79
80 #define PMA_PMD_XCONTROL_REG 0xc000
81 #define SSR_LBN 15
82 #define SSR_WIDTH 1
83 #define LNPGA_POWERDOWN_LBN 8
84 #define LNPGA_POWERDOWN_WIDTH 1
85 #define AFE_POWERDOWN_LBN 9
86 #define AFE_POWERDOWN_WIDTH 1
87 #define DSP_POWERDOWN_LBN 10
88 #define DSP_POWERDOWN_WIDTH 1
89 #define PHY_POWERDOWN_LBN 11
90 #define PHY_POWERDOWN_WIDTH 1
91
92 #define PMA_PMD_XSTATUS_REG 0xc001
93 #define FLP_RCVD_LBN 12
94 #define FLP_RCVD_WIDTH 1
95
96 #define PMA_PMD_LED_CONTROL_REG 0xc007
97 #define LED_ACTIVITY_EN_LBN 3
98 #define LED_ACTIVITY_EN_WIDTH 1
99 #define LED_FLASH_PERIOD_LBN 0
100 #define LED_FLASH_PERIOD_WIDTH 3
101
102 #define PMA_PMD_LED_OVERRIDE_REG 0xc009
103 #define LED_LINK_LBN 0 /* Green */
104 #define LED_LINK_WIDTH 2
105 #define LED_TX_LBN 4 /* Amber */
106 #define LED_TX_WIDTH 2
107 #define LED_RX_LBN 6 /* Red */
108 #define LED_RX_WIDTH 2
109 #define LED_NORMAL_DECODE 0x0
110 #define LED_ON_DECODE 0x1
111 #define LED_OFF_DECODE 0x2
112 #define LED_FLASH_DECODE 0x3
113
114 #define PMA_PMD_FW_REV0_REG 0xc026
115 #define PMA_PMD_FW_REV1_REG 0xc027
116
117 #define PCS_BOOT_STATUS_REG 0xd000 /* PRM 10.4.1 */
118 #define RESET_CAUSE_LBN 8
119 #define RESET_CAUSE_WIDTH 2
120 #define HW_RESET_DECODE 0x0
121 #define SW_RESET_DECODE 0x1
122 #define WD_RESET_DECODE 0x2
123 #define SW_WD_RESET_DECODE 0x3
124 #define UPLOAD_PROGRESS_LBN 7
125 #define UPLOAD_PROGRESS_WIDTH 1
126 #define CODE_DOWNLOAD_LBN 6
127 #define CODE_DOWNLOAD_WIDTH 1
128 #define CKSUM_OK_LBN 5
129 #define CKSUM_OK_WIDTH 1
130 #define CODE_STARTED_LBN 4
131 #define CODE_STARTED_WIDTH 1
132 #define BOOT_STATUS_LBN 3
133 #define BOOT_STATUS_WIDTH 1
134 #define BOOT_PROGRESS_LBN 1
135 #define BOOT_PROGRESS_WIDTH 2
136 #define INIT_DECODE 0x0
137 #define MDIO_WAIT_DECODE 0x1
138 #define CKSUM_START_DECODE 0x2
139 #define APP_JMP_DECODE 0x3
140 #define FATAL_ERR_LBN 0
141 #define FATAL_ERR_WIDTH 1
142
143 #define PCS_LM_RAM_LS_ADDR_REG 0xd004
144 #define LM_RAM_LS_ADDR_LBN 0
145 #define LM_RAM_LS_ADDR_WIDTH 16
146
147 #define PCS_LM_RAM_MS_ADDR_REG 0xd005
148 #define LM_RAM_MS_ADDR_LBN 0
149 #define LM_RAM_MS_ADDR_WIDTH 3
150 #define BYTE_ACCESS_LBN 15
151 #define BYTE_ACCESS_WIDTH 1
152
153 #define PCS_LM_RAM_DATA_REG 0xd006
154 #define LM_RAM_DATA_LBN 0
155 #define LM_RAM_DATA_WIDTH 16
156
157 #define PCS_TEST_SELECT_REG 0xd807 /* PRM 10.5.8 */
158 #define CLK312_EN_LBN 3
159 #define CLK312_EN_WIDTH 1
160
161 #define PCS_CLOCK_CTRL_REG 0xd801
162 #define PLL312_RST_N_LBN 2
163 #define PLL312_RST_N_WIDTH 1
164
165 #define PCS_SOFT_RST2_REG 0xd806
166 #define SERDES_RST_N_LBN 13
167 #define SERDES_RST_N_WIDTH 1
168 #define XGXS_RST_N_LBN 12
169 #define XGXS_RST_N_WIDTH 1
170
171 #define PHY_XS_XGXS_TEST_REG 0xc00a
172 #define SERDES_LOOPBACK_LBN 9
173 #define SERDES_LOOPBACK_WIDTH 1
174 #define NE_LOOPBACK_LBN 8
175 #define NE_LOOPBACK_WIDTH 1
176
177 #define LOADER_MMD 1
178 #define LOADER_MAX_BUFF_SZ_REG 49192
179 #define LOADER_ACTUAL_BUFF_SZ_REG 49193
180 #define LOADER_CMD_RESPONSE_REG 49194
181 #define LOADER_CMD_ERASE_FLASH 0x0001
182 #define LOADER_CMD_FILL_BUFFER 0x0002
183 #define LOADER_CMD_PROGRAM_FLASH 0x0003
184 #define LOADER_CMD_READ_FLASH 0x0004
185 #define LOADER_RESPONSE_OK 0x0100
186 #define LOADER_RESPONSE_ERROR 0x0200
187 #define LOADER_RESPONSE_BUSY 0x0300
188 #define LOADER_WORDS_WRITTEN_REG 49195
189 #define LOADER_WORDS_READ_REG 49195
190 #define LOADER_FLASH_ADDR_LOW_REG 49196
191 #define LOADER_FLASH_ADDR_HI_REG 49197
192 #define LOADER_DATA_REG 49198
193
194 #define FIRMWARE_BLOCK_SIZE 0x4000
195 #define FIRMWARE_MAX_SIZE 0x30000
196
197 #endif /* EFSYS_OPT_PHY_SFX7101 */
198
199 #ifdef __cplusplus
200 }
201 #endif
202
203 #endif /* _SYS_SFX7101_IMPL_H */