1 /*-
2 * Copyright 2008-2013 Solarflare Communications Inc. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 */
25
26 #ifndef _SYS_QT2025C_IMPL_H
27 #define _SYS_QT2025C_IMPL_H
28
29 #ifdef __cplusplus
30 extern "C" {
31 #endif
32
33 #if EFSYS_OPT_PHY_QT2025C
34
35 #define QT2025C_MMD_MASK \
36 ((1 << PMA_PMD_MMD) | \
37 (1 << PCS_MMD) | \
38 (1 << PHY_XS_MMD))
39
40 /* PMA/PMD */
41
42 #define MDIO_RESETS_REG 0xc300
43 #define KRDLL_RESETN_LBN 0
44 #define KRDLL_RESETN_WIDTH 1
45 #define MICRO_RESETN_LBN 1
46 #define MICRO_RESETN_WIDTH 1
47 #define EDC_RESETN_LBN 2
48 #define EDC_RESETN_WIDTH 1
49 #define PSDLL_RESETN_LBN 3
50 #define PSDLL_RESETN_WIDTH 1
51 #define PRDLL_RESETN_LBN 4
52 #define PRDLL_RESETN_WIDTH 1
53 #define RESLRN_RESETN_LBN 5
54 #define RESLRN_RESETN_WIDTH 1
55 #define IB_TX_RESETN_LBN 6
56 #define IB_TX_RESETN_WIDTH 1
57 #define IB_RX_RESETN_LBN 7
58 #define IB_RX_RESETN_WIDTH 1
59 #define SINUS_RESETN_LBN 8
60 #define SINUS_RESETN_WIDTH 1
61
62 #define PMA_UC8051_CFG_REG 0xc302
63 #define EREFCLK_FREQ_LBN 0
64 #define EREFCLK_FREQ_WIDTH 1
65 #define EREFCLK_FREQ_156_25_DECODE 0
66 #define EREFCLK_FREQ_52_08_DECODE 1
67 #define SREFCLK_FREQ_LBN 1
68 #define SREFCLK_FREQ_WIDTH 1
69 #define SREFCLK_FREQ_155_52_DECODE 0
70 #define SREFCLK_FREQ_51_84_DECODE 1
71 #define UC_CLK_SEL_LBN 2
72 #define UC_CLK_SEL_WIDTH 3
73 #define UC_CLK_156_25_DECODE 1
74 #define EEPROM_BOOT_MODE_LBN 5
75 #define EEPROM_BOOT_MODE_WIDTH 1
76 #define EEPROM_BOOT_0_DECODE 0
77 #define EEPROM_BOOT_1K_DECODE 1
78 #define UC_JTAG_CTRL_LBN 6
79 #define UC_JTAG_CTRL_WIDTH 1
80
81 #define PMA_FTX_CTRL2_REG 0xc309
82 #define FTX_STATIC_LBN 13
83 #define FTX_STATIC_WIDTH 1
84
85 #define PMA_UC8051_I2C_FREQ_REG 0xc316
86 #define UC_I2C_DIV_LBN 0
87 #define UC_I2C_DIV_WIDTH 8
88
89 #define PMA_UC8051_I2C_SLV_ADDR_REG 0xc318
90 #define UC_I2C_SLV_ADDR_LBN 0
91 #define UC_I2C_SLV_ADDR_WIDTH 7
92
93 #define PMA_UC8051_SPARE2_REG 0xc319
94 #define DISABLE_PORT_LBN 1
95 #define DISABLE_PORT_WIDTH 1
96 #define OP_MODE_CONFIG_LBN 3
97 #define OP_MODE_CONFIG_WIDTH 3
98 #define OP_MODE_LINEAR_DECODE 0
99 #define OP_MODE_LIMITING_DECODE 1
100 #define OP_MODE_KR_DECODE 2
101 #define OP_MODE_DIRECT_DECODE 4
102 #define OP_MODE_LOW_POWER_DECODE 5
103 #define OP_MODE_AUTO_DECODE 7
104 #define DATA_RATE_LBN 7
105 #define DATA_RATE_WIDTH 1
106 #define DATA_RATE_10G_DECODE 0
107 #define DATA_RATE_1_25G_DECODE 1
108
109 #define PMA_UC8051_SPARE3_REG 0xc31a
110 #define XDRV_OVRD_LBN 1
111 #define XDRV_OVRD_WIDTH 1
112 #define FTX_OVRD_LBN 2
113 #define FTX_OVRD_WIDTH 1
114 #define MODULE_TYPE_LBN 3
115 #define MODULE_TYPE_WIDTH 3
116 #define MODULE_TYPE_X2_DECODE 1
117 #define MODULE_TYPE_XFP_DECODE 2
118 #define MODULE_TYPE_SFP_DECODE 3
119
120 #define PRD_CODE1_REG 0xd000
121 #define PRODUCT_CODE_LBN 0
122 #define PRODUCT_CODE_WIDTH 16
123
124 #define PMA_PMD_LED1_REG 0xd006 /* Green */
125 #define PMA_PMD_LED2_REG 0xd007 /* Amber */
126 #define PMA_PMD_LED3_REG 0xd008 /* Red */
127
128 #define PMA_PMD_LED_CFG_LBN 0
129 #define PMA_PMD_LED_CFG_WIDTH 3
130 #define LED_CFG_LS_DECODE 0x1
131 #define LED_CFG_LA_DECODE 0x2
132 #define LED_CFG_LSA_DECODE 0x3
133 #define LED_CFG_OFF_DECODE 0x4
134 #define LED_CFG_ON_DECODE 0x5
135 #define PMA_PMD_LED_PATH_LBN 3
136 #define PMA_PMD_LED_PATH_WIDTH 1
137 #define LED_PATH_TX_DECODE 0x0
138 #define LED_PATH_RX_DECODE 0x1
139
140 /* PCS */
141
142 #define KR_BYPASS_CTRL_REG 0x0026
143 #define FREEZE_DIS_LBN 8
144 #define FREEZE_DIS_WIDTH 8
145 #define FREEZE_DIS_DECODE 0x0e
146
147 #define BOOT_CTRL_REG 0x0027
148 #define LED1_CTRL_LBN 0
149 #define LED1_CTRL_WIDTH 1
150 #define LED1_CTRL_FW_DECODE 0
151 #define LED1_CTRL_HW_DECODE 1
152 #define FTX_FR4_LOSS_LBN 1
153 #define FTX_FR4_LOSS_WIDTH 3
154 #define FRX_FR4_LOSS_LBN 4
155 #define FRX_FR4_LOSS_WIDTH 3
156 #define GE_PRBS_MODE_LBN 15
157 #define GE_PRBS_MODE_WIDTH 1
158
159 #define FW_CFG_REG 0x0028
160 #define FW_CFG_KEY_LBN 0
161 #define FW_CFG_KEY_WIDTH 16
162 #define FW_CFG_KEY_DECODE 0xa528
163
164 #define MICRO_RAM1_BASE 0x8000
165 #define MICRO_RAM1_SIZE 0x4000
166
167 #define OP_MODE_REG 0xd70c
168 #define OP_MODE_CURRENT_LBN 0
169 #define OP_MODE_CURRENT_WIDTH 4
170
171 #define LED_CFG_REG 0xd70d
172 #define LED3_CFG_LBN 0
173 #define LED3_CFG_WIDTH 2
174 #define LED2_CFG_LBN 2
175 #define LED2_CFG_WIDTH 2
176 #define LED1_CFG_LBN 4
177 #define LED1_CFG_WIDTH 2
178 #define LED_RXTX_DECODE 3
179 #define LED_RX_DECODE 2
180 #define LED_TX_DECODE 1
181 #define LED_ON_DECODE 0
182
183 #define CKSUM_STATUS1_REG 0xd716
184 #define CKSUM_STATUS1_BYTE_LBN 0
185 #define CKSUM_STATUS1_BYTE_WIDTH 1
186 #define CKSUM_STATUS1_BYTE_BAD_DECODE 0xde
187
188 #define CKSUM_STATUS2_REG 0xd717
189 #define CKSUM_STATUS2_BYTE_LBN 0
190 #define CKSUM_STATUS2_BYTE_WIDTH 1
191 #define CKSUM_STATUS2_BYTE_BAD_DECODE 0xad
192
193 #define FW_HEARTBEAT_REG 0xd7ee
194 #define FW_HEARTB_LBN 0
195 #define FW_HEARTB_WIDTH 8
196
197 #define FW_VERSION1_REG 0xd7f3
198 #define FW_VERSION2_REG 0xd7f4
199 #define FW_VERSION3_REG 0xd7f5
200
201 #define FW_BUILD1_REG 0xd7f6
202 #define FW_BUILD2_REG 0xd7f7
203 #define FW_BUILD3_REG 0xd7f8
204
205 #define UC8051_STATUS_REG 0xd7fd
206 #define UC_STATUS_LBN 0
207 #define UC_STATUS_WIDTH 8
208 #define UC_STATUS_INVALID_DECODE 0x00
209 #define UC_STATUS_FW_START_DECODE 0x10
210 #define UC_STATUS_FW_SAVE_DECODE 0x20
211 #define UC_STATUS_INIT_DECODE 0x40
212 #define UC_STATUS_AQ_IN_PROG_DECODE 0x50
213 #define UC_STATUS_AQ_COMPLETE_DECODE 0x60
214 #define UC_STATUS_TRACK_IN_PROG_DECODE 0x70
215 #define UC_STATUS_IN_AN_DECODE 0xa0
216
217 #define MICRO_GEN_CTL_REG 0xe854
218 #define UC_INT0_CNT_LBN 0
219 #define UC_INT0_CNT_WIDTH 1
220 #define UC_INT1_CNT_LBN 1
221 #define UC_INT1_CNT_WIDTH 1
222 #define UC_MDIO_SW_LBN 3
223 #define UC_MDIO_SW_WIDTH 1
224 #define UC_DIS_ROM_LBN 4
225 #define UC_DIS_ROM_WIDTH 1
226 #define UC_UPDATE_LBN 5
227 #define UC_UPDATE_WIDTH 1
228 #define UC_RUN_RAM_LBN 6
229 #define UC_RUN_RAM_WIDTH 1
230 #define UC_RST_LBN 7
231 #define UC_RST_WIDTH 1
232
233 /* PHY_XS */
234
235 #define XGXS_VENDOR_SPECIFIC_1_REG 0xc000
236 #define XGXS_SYSLPBK_LBN 14
237 #define XGXS_SYSLPBK_WIDTH 1
238
239 #define MICRO_RAM2_BASE 0x8000
240 #define MICRO_RAM2_SIZE 0x2000
241
242 #endif /* EFSYS_OPT_PHY_QT2025C */
243
244 #ifdef __cplusplus
245 }
246 #endif
247
248 #endif /* _SYS_QT2025C_IMPL_H */