1 /*-
   2  * Copyright 2007-2013 Solarflare Communications Inc.  All rights reserved.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions
   6  * are met:
   7  * 1. Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer.
   9  * 2. Redistributions in binary form must reproduce the above copyright
  10  *    notice, this list of conditions and the following disclaimer in the
  11  *    documentation and/or other materials provided with the distribution.
  12  *
  13  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND
  14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  16  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  23  * SUCH DAMAGE.
  24  */
  25 
  26 #ifndef _SYS_FALCON_NVRAM_H
  27 #define _SYS_FALCON_NVRAM_H
  28 
  29 #ifdef  __cplusplus
  30 extern "C" {
  31 #endif
  32 
  33 /* PCI subsystem vendor ID */
  34 #define PC_SS_VEND_ID_REG_SF_OFST 0x12c
  35 
  36 /* PCI subsystem device ID */
  37 #define PC_SS_ID_REG_SF_OFST 0x12e
  38 
  39 /* PCIe serial number */
  40 #define PCI_SN_SF_OFST 0x1c4
  41 
  42 /* NVRAM and VPD configuration */
  43 #define EE_VPD_CFG0_REG_SF_OFST 0x300
  44 
  45 /* MAC address */
  46 #define MAC_ADDRESS_SF_OFST 0x310
  47 
  48 /* NIC stat */
  49 #define NIC_STAT_SF_OFST 0x360
  50 
  51 /* Sram config */
  52 #define SRAM_CFG_SF_OFST 0x380
  53 
  54 /* Magic number */
  55 #define CFG_MAGIC_REG_SF_OFST 0x3a0
  56 
  57 #define MAGIC_LBN 0
  58 #define MAGIC_WIDTH 16
  59 #define MAGIC_DECODE 0xfa1c
  60 
  61 /* Version */
  62 #define CFG_VERSION_REG_SF_OFST 0x3a2
  63 
  64 #define VERSION_LBN 0
  65 #define VERSION_WIDTH 16
  66 
  67 /* Checksum */
  68 #define CFG_CKSUM_REG_SF_OFST 0x3a4
  69 
  70 #define CKSUM_LBN 0
  71 #define CKSUM_WIDTH 16
  72 
  73 /* PHY address */
  74 #define CFG_PHY_PORT_REG_SF_OFST 0x3a8
  75 
  76 #define PHY_PORT_LBN 0
  77 #define PHY_PORT_WIDTH 8
  78 #define PHY_PORT_INVALID_DECODE 0xff
  79 
  80 /* PHY type */
  81 #define CFG_PHY_TYPE_REG_SF_OFST 0x3a9
  82 
  83 #define PHY_TYPE_LBN 0
  84 #define PHY_TYPE_WIDTH 8
  85 #define PHY_TYPE_NONE_DECODE 0x00
  86 #define PHY_TYPE_TXC43128_DECODE 0x01
  87 #define PHY_TYPE_88E1111_DECODE 0x02
  88 #define PHY_TYPE_SFX7101_DECODE 0x03
  89 #define PHY_TYPE_QT2022C2_DECODE 0x04
  90 #define PHY_TYPE_SFT9001A_DECODE 0x08
  91 #define PHY_TYPE_QT2025C_DECODE 0x09
  92 #define PHY_TYPE_SFT9001B_DECODE 0x0a
  93 
  94 /* ASIC revision */
  95 #define CFG_ASIC_REV_REG_SF_OFST 0x3ac
  96 
  97 #define ASIC_REV_MINOR_LBN 0
  98 #define ASIC_REV_MINOR_WIDTH 8
  99 #define ASIC_REV_MAJOR_LBN 8
 100 #define ASIC_REV_MAJOR_WIDTH 16
 101 
 102 /* Board revision */
 103 #define CFG_BOARD_REV_REG_SF_OFST 0x3ae
 104 
 105 #define BOARD_REV_MINOR_LBN 0
 106 #define BOARD_REV_MINOR_WIDTH 4
 107 #define BOARD_REV_MAJOR_LBN 4
 108 #define BOARD_REV_MAJOR_WIDTH 4
 109 
 110 /* Board type */
 111 #define CFG_BOARD_TYPE_REG_SF_OFST 0x3af
 112 
 113 #define BOARD_TYPE_LBN 0
 114 #define BOARD_TYPE_WIDTH 8
 115 #define BOARD_TYPE_SFE4001_DECODE 0x01
 116 #define BOARD_TYPE_SFE4002_DECODE 0x02
 117 #define BOARD_TYPE_SFE4003_DECODE 0x03
 118 #define BOARD_TYPE_SFE4005_DECODE 0x04
 119 #define BOARD_TYPE_SFN4111T_DECODE 0x51
 120 #define BOARD_TYPE_SFN4112F_DECODE 0x52
 121 
 122 /* EEPROM information */
 123 #define CFG_EEPROM_DEV_REG_SF_OFST 0x3c0
 124 
 125 /* FLASH information */
 126 #define CFG_FLASH_DEV_REG_SF_OFST 0x3c4
 127 
 128 #define SPI_DEV_SIZE_LBN 0
 129 #define SPI_DEV_SIZE_WIDTH 5
 130 #define SPI_DEV_ADBCNT_LBN 6
 131 #define SPI_DEV_ADBCNT_WIDTH 2
 132 #define SPI_DEV_ERASE_CMD_LBN 8
 133 #define SPI_DEV_ERASE_CMD_WIDTH 8
 134 #define SPI_DEV_ERASE_SIZE_LBN 16
 135 #define SPI_DEV_ERASE_SIZE_WIDTH 5
 136 #define SPI_DEV_WRITE_SIZE_LBN 24
 137 #define SPI_DEV_WRITE_SIZE_WIDTH 5
 138 
 139 #ifdef  __cplusplus
 140 }
 141 #endif
 142 
 143 #endif  /* _SYS_FALCON_NVRAM_H */