1 /*-
2 * Copyright 2008-2013 Solarflare Communications Inc. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 */
25
26 /*! \cidoxg_firmware_mc_cmd */
27
28 #ifndef _SIENA_MC_DRIVER_PCOL_H
29 #define _SIENA_MC_DRIVER_PCOL_H
30
31
32 /* Values to be written into FMCR_CZ_RESET_STATE_REG to control boot. */
33 /* Power-on reset state */
34 #define MC_FW_STATE_POR (1)
35 /* If this is set in MC_RESET_STATE_REG then it should be
36 * possible to jump into IMEM without loading code from flash. */
37 #define MC_FW_WARM_BOOT_OK (2)
38 /* The MC main image has started to boot. */
39 #define MC_FW_STATE_BOOTING (4)
40 /* The Scheduler has started. */
41 #define MC_FW_STATE_SCHED (8)
42
43 /* Siena MC shared memmory offsets */
44 /* The 'doorbell' addresses are hard-wired to alert the MC when written */
45 #define MC_SMEM_P0_DOORBELL_OFST 0x000
46 #define MC_SMEM_P1_DOORBELL_OFST 0x004
47 /* The rest of these are firmware-defined */
48 #define MC_SMEM_P0_PDU_OFST 0x008
49 #define MC_SMEM_P1_PDU_OFST 0x108
50 #define MC_SMEM_PDU_LEN 0x100
51 #define MC_SMEM_P0_PTP_TIME_OFST 0x7f0
52 #define MC_SMEM_P0_STATUS_OFST 0x7f8
53 #define MC_SMEM_P1_STATUS_OFST 0x7fc
54
55 /* Values to be written to the per-port status dword in shared
56 * memory on reboot and assert */
57 #define MC_STATUS_DWORD_REBOOT (0xb007b007)
58 #define MC_STATUS_DWORD_ASSERT (0xdeaddead)
59
60 /* The current version of the MCDI protocol.
61 *
62 * Note that the ROM burnt into the card only talks V0, so at the very
63 * least every driver must support version 0 and MCDI_PCOL_VERSION
64 */
65 #ifdef WITH_MCDI_V2
66 #define MCDI_PCOL_VERSION 2
67 #else
68 #define MCDI_PCOL_VERSION 1
69 #endif
70
71 /* Unused commands: 0x23, 0x27, 0x30, 0x31 */
72
73 /**
74 * MCDI version 1
75 *
76 * Each MCDI request starts with an MCDI_HEADER, which is a 32byte
77 * structure, filled in by the client.
78 *
79 * 0 7 8 16 20 22 23 24 31
80 * | CODE | R | LEN | SEQ | Rsvd | E | R | XFLAGS |
81 * | | |
82 * | | \--- Response
83 * | \------- Error
84 * \------------------------------ Resync (always set)
85 *
86 * The client writes it's request into MC shared memory, and rings the
87 * doorbell. Each request is completed by either by the MC writting
88 * back into shared memory, or by writting out an event.
89 *
90 * All MCDI commands support completion by shared memory response. Each
91 * request may also contain additional data (accounted for by HEADER.LEN),
92 * and some response's may also contain additional data (again, accounted
93 * for by HEADER.LEN).
94 *
95 * Some MCDI commands support completion by event, in which any associated
96 * response data is included in the event.
97 *
98 * The protocol requires one response to be delivered for every request, a
99 * request should not be sent unless the response for the previous request
100 * has been received (either by polling shared memory, or by receiving
101 * an event).
102 */
103
104 /** Request/Response structure */
105 #define MCDI_HEADER_OFST 0
106 #define MCDI_HEADER_CODE_LBN 0
107 #define MCDI_HEADER_CODE_WIDTH 7
108 #define MCDI_HEADER_RESYNC_LBN 7
109 #define MCDI_HEADER_RESYNC_WIDTH 1
110 #define MCDI_HEADER_DATALEN_LBN 8
111 #define MCDI_HEADER_DATALEN_WIDTH 8
112 #define MCDI_HEADER_SEQ_LBN 16
113 #define MCDI_HEADER_RSVD_LBN 20
114 #define MCDI_HEADER_RSVD_WIDTH 2
115 #define MCDI_HEADER_SEQ_WIDTH 4
116 #define MCDI_HEADER_ERROR_LBN 22
117 #define MCDI_HEADER_ERROR_WIDTH 1
118 #define MCDI_HEADER_RESPONSE_LBN 23
119 #define MCDI_HEADER_RESPONSE_WIDTH 1
120 #define MCDI_HEADER_XFLAGS_LBN 24
121 #define MCDI_HEADER_XFLAGS_WIDTH 8
122 /* Request response using event */
123 #define MCDI_HEADER_XFLAGS_EVREQ 0x01
124
125 /* Maximum number of payload bytes */
126 #ifdef WITH_MCDI_V2
127 #define MCDI_CTL_SDU_LEN_MAX 0x400
128 #else
129 #define MCDI_CTL_SDU_LEN_MAX 0xfc
130 #endif
131
132 /* The MC can generate events for two reasons:
133 * - To complete a shared memory request if XFLAGS_EVREQ was set
134 * - As a notification (link state, i2c event), controlled
135 * via MC_CMD_LOG_CTRL
136 *
137 * Both events share a common structure:
138 *
139 * 0 32 33 36 44 52 60
140 * | Data | Cont | Level | Src | Code | Rsvd |
141 * |
142 * \ There is another event pending in this notification
143 *
144 * If Code==CMDDONE, then the fields are further interpreted as:
145 *
146 * - LEVEL==INFO Command succeeded
147 * - LEVEL==ERR Command failed
148 *
149 * 0 8 16 24 32
150 * | Seq | Datalen | Errno | Rsvd |
151 *
152 * These fields are taken directly out of the standard MCDI header, i.e.,
153 * LEVEL==ERR, Datalen == 0 => Reboot
154 *
155 * Events can be squirted out of the UART (using LOG_CTRL) without a
156 * MCDI header. An event can be distinguished from a MCDI response by
157 * examining the first byte which is 0xc0. This corresponds to the
158 * non-existent MCDI command MC_CMD_DEBUG_LOG.
159 *
160 * 0 7 8
161 * | command | Resync | = 0xc0
162 *
163 * Since the event is written in big-endian byte order, this works
164 * providing bits 56-63 of the event are 0xc0.
165 *
166 * 56 60 63
167 * | Rsvd | Code | = 0xc0
168 *
169 * Which means for convenience the event code is 0xc for all MC
170 * generated events.
171 */
172 #define FSE_AZ_EV_CODE_MCDI_EVRESPONSE 0xc
173
174
175 /* Non-existent command target */
176 #define MC_CMD_ERR_ENOENT 2
177 /* assert() has killed the MC */
178 #define MC_CMD_ERR_EINTR 4
179 /* Caller does not hold required locks */
180 #define MC_CMD_ERR_EACCES 13
181 /* Resource is currently unavailable (e.g. lock contention) */
182 #define MC_CMD_ERR_EBUSY 16
183 /* Invalid argument to target */
184 #define MC_CMD_ERR_EINVAL 22
185 /* Non-recursive resource is already acquired */
186 #define MC_CMD_ERR_EDEADLK 35
187 /* Operation not implemented */
188 #define MC_CMD_ERR_ENOSYS 38
189 /* Operation timed out */
190 #define MC_CMD_ERR_ETIME 62
191
192 #define MC_CMD_ERR_CODE_OFST 0
193
194 /* We define 8 "escape" commands to allow
195 for command number space extension */
196
197 #define MC_CMD_CMD_SPACE_ESCAPE_0 0x78
198 #define MC_CMD_CMD_SPACE_ESCAPE_1 0x79
199 #define MC_CMD_CMD_SPACE_ESCAPE_2 0x7A
200 #define MC_CMD_CMD_SPACE_ESCAPE_3 0x7B
201 #define MC_CMD_CMD_SPACE_ESCAPE_4 0x7C
202 #define MC_CMD_CMD_SPACE_ESCAPE_5 0x7D
203 #define MC_CMD_CMD_SPACE_ESCAPE_6 0x7E
204 #define MC_CMD_CMD_SPACE_ESCAPE_7 0x7F
205
206 /* Vectors in the boot ROM */
207 /* Point to the copycode entry point. */
208 #define MC_BOOTROM_COPYCODE_VEC (0x7f4)
209 /* Points to the recovery mode entry point. */
210 #define MC_BOOTROM_NOFLASH_VEC (0x7f8)
211
212 /* The command set exported by the boot ROM (MCDI v0) */
213 #define MC_CMD_GET_VERSION_V0_SUPPORTED_FUNCS { \
214 (1 << MC_CMD_READ32) | \
215 (1 << MC_CMD_WRITE32) | \
216 (1 << MC_CMD_COPYCODE) | \
217 (1 << MC_CMD_GET_VERSION), \
218 0, 0, 0 }
219
220 #define MC_CMD_SENSOR_INFO_OUT_OFFSET_OFST(_x) \
221 (MC_CMD_SENSOR_ENTRY_OFST + (_x))
222
223 #define MC_CMD_DBI_WRITE_IN_ADDRESS_OFST(n) ( \
224 (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST+ \
225 MC_CMD_DBIWROP_TYPEDEF_ADDRESS_OFST)+ \
226 ((n)*MC_CMD_DBIWROP_TYPEDEF_LEN))
227
228 #define MC_CMD_DBI_WRITE_IN_BYTE_MASK_OFST(n) ( \
229 (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST+ \
230 MC_CMD_DBIWROP_TYPEDEF_BYTE_MASK_OFST)+ \
231 ((n)*MC_CMD_DBIWROP_TYPEDEF_LEN))
232
233 #define MC_CMD_DBI_WRITE_IN_VALUE_OFST(n) ( \
234 (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST+ \
235 MC_CMD_DBIWROP_TYPEDEF_VALUE_OFST)+ \
236 ((n)*MC_CMD_DBIWROP_TYPEDEF_LEN))
237
238
239 #ifdef WITH_MCDI_V2
240
241 /* Version 2 adds an optional argument to error returns: the errno value
242 * may be followed by the (0-based) number of the first argument that
243 * could not be processed.
244 */
245 #define MC_CMD_ERR_ARG_OFST 4
246
247 /* Try again */
248 #define MC_CMD_ERR_EAGAIN 11
249 /* No space */
250 #define MC_CMD_ERR_ENOSPC 28
251
252 #endif
253
254 /* MCDI_EVENT structuredef */
255 #define MCDI_EVENT_LEN 8
256 #define MCDI_EVENT_CONT_LBN 32
257 #define MCDI_EVENT_CONT_WIDTH 1
258 #define MCDI_EVENT_LEVEL_LBN 33
259 #define MCDI_EVENT_LEVEL_WIDTH 3
260 #define MCDI_EVENT_LEVEL_INFO 0x0 /* enum */
261 #define MCDI_EVENT_LEVEL_WARN 0x1 /* enum */
262 #define MCDI_EVENT_LEVEL_ERR 0x2 /* enum */
263 #define MCDI_EVENT_LEVEL_FATAL 0x3 /* enum */
264 #define MCDI_EVENT_DATA_OFST 0
265 #define MCDI_EVENT_CMDDONE_SEQ_LBN 0
266 #define MCDI_EVENT_CMDDONE_SEQ_WIDTH 8
267 #define MCDI_EVENT_CMDDONE_DATALEN_LBN 8
268 #define MCDI_EVENT_CMDDONE_DATALEN_WIDTH 8
269 #define MCDI_EVENT_CMDDONE_ERRNO_LBN 16
270 #define MCDI_EVENT_CMDDONE_ERRNO_WIDTH 8
271 #define MCDI_EVENT_LINKCHANGE_LP_CAP_LBN 0
272 #define MCDI_EVENT_LINKCHANGE_LP_CAP_WIDTH 16
273 #define MCDI_EVENT_LINKCHANGE_SPEED_LBN 16
274 #define MCDI_EVENT_LINKCHANGE_SPEED_WIDTH 4
275 #define MCDI_EVENT_LINKCHANGE_SPEED_100M 0x1 /* enum */
276 #define MCDI_EVENT_LINKCHANGE_SPEED_1G 0x2 /* enum */
277 #define MCDI_EVENT_LINKCHANGE_SPEED_10G 0x3 /* enum */
278 #define MCDI_EVENT_LINKCHANGE_FCNTL_LBN 20
279 #define MCDI_EVENT_LINKCHANGE_FCNTL_WIDTH 4
280 #define MCDI_EVENT_LINKCHANGE_LINK_FLAGS_LBN 24
281 #define MCDI_EVENT_LINKCHANGE_LINK_FLAGS_WIDTH 8
282 #define MCDI_EVENT_SENSOREVT_MONITOR_LBN 0
283 #define MCDI_EVENT_SENSOREVT_MONITOR_WIDTH 8
284 #define MCDI_EVENT_SENSOREVT_STATE_LBN 8
285 #define MCDI_EVENT_SENSOREVT_STATE_WIDTH 8
286 #define MCDI_EVENT_SENSOREVT_VALUE_LBN 16
287 #define MCDI_EVENT_SENSOREVT_VALUE_WIDTH 16
288 #define MCDI_EVENT_FWALERT_DATA_LBN 8
289 #define MCDI_EVENT_FWALERT_DATA_WIDTH 24
290 #define MCDI_EVENT_FWALERT_REASON_LBN 0
291 #define MCDI_EVENT_FWALERT_REASON_WIDTH 8
292 #define MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS 0x1 /* enum */
293 #define MCDI_EVENT_FLR_VF_LBN 0
294 #define MCDI_EVENT_FLR_VF_WIDTH 8
295 #define MCDI_EVENT_TX_ERR_TXQ_LBN 0
296 #define MCDI_EVENT_TX_ERR_TXQ_WIDTH 12
297 #define MCDI_EVENT_TX_ERR_TYPE_LBN 12
298 #define MCDI_EVENT_TX_ERR_TYPE_WIDTH 4
299 #define MCDI_EVENT_TX_ERR_DL_FAIL 0x1 /* enum */
300 #define MCDI_EVENT_TX_ERR_NO_EOP 0x2 /* enum */
301 #define MCDI_EVENT_TX_ERR_2BIG 0x3 /* enum */
302 #define MCDI_EVENT_TX_ERR_INFO_LBN 16
303 #define MCDI_EVENT_TX_ERR_INFO_WIDTH 16
304 #define MCDI_EVENT_TX_FLUSH_TXQ_LBN 0
305 #define MCDI_EVENT_TX_FLUSH_TXQ_WIDTH 12
306 #define MCDI_EVENT_PTP_ERR_TYPE_LBN 0
307 #define MCDI_EVENT_PTP_ERR_TYPE_WIDTH 8
308 #define MCDI_EVENT_PTP_ERR_PLL_LOST 0x1 /* enum */
309 #define MCDI_EVENT_PTP_ERR_FILTER 0x2 /* enum */
310 #define MCDI_EVENT_PTP_ERR_FIFO 0x3 /* enum */
311 #define MCDI_EVENT_PTP_ERR_QUEUE 0x4 /* enum */
312 #define MCDI_EVENT_DATA_LBN 0
313 #define MCDI_EVENT_DATA_WIDTH 32
314 #define MCDI_EVENT_SRC_LBN 36
315 #define MCDI_EVENT_SRC_WIDTH 8
316 #define MCDI_EVENT_EV_CODE_LBN 60
317 #define MCDI_EVENT_EV_CODE_WIDTH 4
318 #define MCDI_EVENT_CODE_LBN 44
319 #define MCDI_EVENT_CODE_WIDTH 8
320 #define MCDI_EVENT_CODE_BADSSERT 0x1 /* enum */
321 #define MCDI_EVENT_CODE_PMNOTICE 0x2 /* enum */
322 #define MCDI_EVENT_CODE_CMDDONE 0x3 /* enum */
323 #define MCDI_EVENT_CODE_LINKCHANGE 0x4 /* enum */
324 #define MCDI_EVENT_CODE_SENSOREVT 0x5 /* enum */
325 #define MCDI_EVENT_CODE_SCHEDERR 0x6 /* enum */
326 #define MCDI_EVENT_CODE_REBOOT 0x7 /* enum */
327 #define MCDI_EVENT_CODE_MAC_STATS_DMA 0x8 /* enum */
328 #define MCDI_EVENT_CODE_FWALERT 0x9 /* enum */
329 #define MCDI_EVENT_CODE_FLR 0xa /* enum */
330 #define MCDI_EVENT_CODE_TX_ERR 0xb /* enum */
331 #define MCDI_EVENT_CODE_TX_FLUSH 0xc /* enum */
332 #define MCDI_EVENT_CODE_PTP_RX 0xd /* enum */
333 #define MCDI_EVENT_CODE_PTP_FAULT 0xe /* enum */
334 #define MCDI_EVENT_CODE_VCAL_FAIL 0x13 /* enum */
335 #define MCDI_EVENT_CMDDONE_DATA_OFST 0
336 #define MCDI_EVENT_CMDDONE_DATA_LBN 0
337 #define MCDI_EVENT_CMDDONE_DATA_WIDTH 32
338 #define MCDI_EVENT_LINKCHANGE_DATA_OFST 0
339 #define MCDI_EVENT_LINKCHANGE_DATA_LBN 0
340 #define MCDI_EVENT_LINKCHANGE_DATA_WIDTH 32
341 #define MCDI_EVENT_SENSOREVT_DATA_OFST 0
342 #define MCDI_EVENT_SENSOREVT_DATA_LBN 0
343 #define MCDI_EVENT_SENSOREVT_DATA_WIDTH 32
344 #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_OFST 0
345 #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_LBN 0
346 #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_WIDTH 32
347 #define MCDI_EVENT_TX_ERR_DATA_OFST 0
348 #define MCDI_EVENT_TX_ERR_DATA_LBN 0
349 #define MCDI_EVENT_TX_ERR_DATA_WIDTH 32
350 #define MCDI_EVENT_PTP_SECONDS_OFST 0
351 #define MCDI_EVENT_PTP_SECONDS_LBN 0
352 #define MCDI_EVENT_PTP_SECONDS_WIDTH 32
353 #define MCDI_EVENT_PTP_NANOSECONDS_OFST 0
354 #define MCDI_EVENT_PTP_NANOSECONDS_LBN 0
355 #define MCDI_EVENT_PTP_NANOSECONDS_WIDTH 32
356 #define MCDI_EVENT_PTP_UUID_OFST 0
357 #define MCDI_EVENT_PTP_UUID_LBN 0
358 #define MCDI_EVENT_PTP_UUID_WIDTH 32
359
360
361 /***********************************/
362 /* MC_CMD_READ32
363 * Read multiple 32byte words from MC memory.
364 */
365 #define MC_CMD_READ32 0x1
366
367 /* MC_CMD_READ32_IN msgrequest */
368 #define MC_CMD_READ32_IN_LEN 8
369 #define MC_CMD_READ32_IN_ADDR_OFST 0
370 #define MC_CMD_READ32_IN_NUMWORDS_OFST 4
371
372 /* MC_CMD_READ32_OUT msgresponse */
373 #define MC_CMD_READ32_OUT_LENMIN 4
374 #define MC_CMD_READ32_OUT_LENMAX 252
375 #define MC_CMD_READ32_OUT_LEN(num) (0+4*(num))
376 #define MC_CMD_READ32_OUT_BUFFER_OFST 0
377 #define MC_CMD_READ32_OUT_BUFFER_LEN 4
378 #define MC_CMD_READ32_OUT_BUFFER_MINNUM 1
379 #define MC_CMD_READ32_OUT_BUFFER_MAXNUM 63
380
381
382 /***********************************/
383 /* MC_CMD_WRITE32
384 * Write multiple 32byte words to MC memory.
385 */
386 #define MC_CMD_WRITE32 0x2
387
388 /* MC_CMD_WRITE32_IN msgrequest */
389 #define MC_CMD_WRITE32_IN_LENMIN 8
390 #define MC_CMD_WRITE32_IN_LENMAX 252
391 #define MC_CMD_WRITE32_IN_LEN(num) (4+4*(num))
392 #define MC_CMD_WRITE32_IN_ADDR_OFST 0
393 #define MC_CMD_WRITE32_IN_BUFFER_OFST 4
394 #define MC_CMD_WRITE32_IN_BUFFER_LEN 4
395 #define MC_CMD_WRITE32_IN_BUFFER_MINNUM 1
396 #define MC_CMD_WRITE32_IN_BUFFER_MAXNUM 62
397
398 /* MC_CMD_WRITE32_OUT msgresponse */
399 #define MC_CMD_WRITE32_OUT_LEN 0
400
401
402 /***********************************/
403 /* MC_CMD_COPYCODE
404 * Copy MC code between two locations and jump.
405 */
406 #define MC_CMD_COPYCODE 0x3
407
408 /* MC_CMD_COPYCODE_IN msgrequest */
409 #define MC_CMD_COPYCODE_IN_LEN 16
410 #define MC_CMD_COPYCODE_IN_SRC_ADDR_OFST 0
411 #define MC_CMD_COPYCODE_IN_DEST_ADDR_OFST 4
412 #define MC_CMD_COPYCODE_IN_NUMWORDS_OFST 8
413 #define MC_CMD_COPYCODE_IN_JUMP_OFST 12
414 #define MC_CMD_COPYCODE_JUMP_NONE 0x1 /* enum */
415
416 /* MC_CMD_COPYCODE_OUT msgresponse */
417 #define MC_CMD_COPYCODE_OUT_LEN 0
418
419
420 /***********************************/
421 /* MC_CMD_SET_FUNC
422 */
423 #define MC_CMD_SET_FUNC 0x4
424
425 /* MC_CMD_SET_FUNC_IN msgrequest */
426 #define MC_CMD_SET_FUNC_IN_LEN 4
427 #define MC_CMD_SET_FUNC_IN_FUNC_OFST 0
428
429 /* MC_CMD_SET_FUNC_OUT msgresponse */
430 #define MC_CMD_SET_FUNC_OUT_LEN 0
431
432
433 /***********************************/
434 /* MC_CMD_GET_BOOT_STATUS
435 */
436 #define MC_CMD_GET_BOOT_STATUS 0x5
437
438 /* MC_CMD_GET_BOOT_STATUS_IN msgrequest */
439 #define MC_CMD_GET_BOOT_STATUS_IN_LEN 0
440
441 /* MC_CMD_GET_BOOT_STATUS_OUT msgresponse */
442 #define MC_CMD_GET_BOOT_STATUS_OUT_LEN 8
443 #define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_OFST 0
444 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_OFST 4
445 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_LBN 0
446 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_WIDTH 1
447 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_LBN 1
448 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_WIDTH 1
449 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_LBN 2
450 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_WIDTH 1
451
452
453 /***********************************/
454 /* MC_CMD_GET_ASSERTS
455 * Get and clear any assertion status.
456 */
457 #define MC_CMD_GET_ASSERTS 0x6
458
459 /* MC_CMD_GET_ASSERTS_IN msgrequest */
460 #define MC_CMD_GET_ASSERTS_IN_LEN 4
461 #define MC_CMD_GET_ASSERTS_IN_CLEAR_OFST 0
462
463 /* MC_CMD_GET_ASSERTS_OUT msgresponse */
464 #define MC_CMD_GET_ASSERTS_OUT_LEN 140
465 #define MC_CMD_GET_ASSERTS_OUT_GLOBAL_FLAGS_OFST 0
466 #define MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS 0x1 /* enum */
467 #define MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL 0x2 /* enum */
468 #define MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL 0x3 /* enum */
469 #define MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED 0x4 /* enum */
470 #define MC_CMD_GET_ASSERTS_OUT_SAVED_PC_OFFS_OFST 4
471 #define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_OFST 8
472 #define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_LEN 4
473 #define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_NUM 31
474 #define MC_CMD_GET_ASSERTS_OUT_THREAD_OFFS_OFST 132
475 #define MC_CMD_GET_ASSERTS_OUT_RESERVED_OFST 136
476
477
478 /***********************************/
479 /* MC_CMD_LOG_CTRL
480 * Configure the output stream for various events and messages.
481 */
482 #define MC_CMD_LOG_CTRL 0x7
483
484 /* MC_CMD_LOG_CTRL_IN msgrequest */
485 #define MC_CMD_LOG_CTRL_IN_LEN 8
486 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_OFST 0
487 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_UART 0x1 /* enum */
488 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ 0x2 /* enum */
489 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ_OFST 4
490
491 /* MC_CMD_LOG_CTRL_OUT msgresponse */
492 #define MC_CMD_LOG_CTRL_OUT_LEN 0
493
494
495 /***********************************/
496 /* MC_CMD_GET_VERSION
497 * Get version information about the MC firmware.
498 */
499 #define MC_CMD_GET_VERSION 0x8
500
501 /* MC_CMD_GET_VERSION_IN msgrequest */
502 #define MC_CMD_GET_VERSION_IN_LEN 0
503
504 /* MC_CMD_GET_VERSION_V0_OUT msgresponse */
505 #define MC_CMD_GET_VERSION_V0_OUT_LEN 4
506 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0
507 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_ANY 0xffffffff /* enum */
508 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_BOOTROM 0xb0070000 /* enum */
509
510 /* MC_CMD_GET_VERSION_OUT msgresponse */
511 #define MC_CMD_GET_VERSION_OUT_LEN 32
512 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */
513 /* Enum values, see field(s): */
514 /* MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */
515 #define MC_CMD_GET_VERSION_OUT_PCOL_OFST 4
516 #define MC_CMD_GET_VERSION_OUT_SUPPORTED_FUNCS_OFST 8
517 #define MC_CMD_GET_VERSION_OUT_SUPPORTED_FUNCS_LEN 16
518 #define MC_CMD_GET_VERSION_OUT_VERSION_OFST 24
519 #define MC_CMD_GET_VERSION_OUT_VERSION_LEN 8
520 #define MC_CMD_GET_VERSION_OUT_VERSION_LO_OFST 24
521 #define MC_CMD_GET_VERSION_OUT_VERSION_HI_OFST 28
522
523
524 /***********************************/
525 /* MC_CMD_GET_FPGAREG
526 * Read multiple bytes from PTP FPGA.
527 */
528 #define MC_CMD_GET_FPGAREG 0x9
529
530 /* MC_CMD_GET_FPGAREG_IN msgrequest */
531 #define MC_CMD_GET_FPGAREG_IN_LEN 8
532 #define MC_CMD_GET_FPGAREG_IN_ADDR_OFST 0
533 #define MC_CMD_GET_FPGAREG_IN_NUMBYTES_OFST 4
534
535 /* MC_CMD_GET_FPGAREG_OUT msgresponse */
536 #define MC_CMD_GET_FPGAREG_OUT_LENMIN 1
537 #define MC_CMD_GET_FPGAREG_OUT_LENMAX 252
538 #define MC_CMD_GET_FPGAREG_OUT_LEN(num) (0+1*(num))
539 #define MC_CMD_GET_FPGAREG_OUT_BUFFER_OFST 0
540 #define MC_CMD_GET_FPGAREG_OUT_BUFFER_LEN 1
541 #define MC_CMD_GET_FPGAREG_OUT_BUFFER_MINNUM 1
542 #define MC_CMD_GET_FPGAREG_OUT_BUFFER_MAXNUM 252
543
544
545 /***********************************/
546 /* MC_CMD_PUT_FPGAREG
547 * Write multiple bytes to PTP FPGA.
548 */
549 #define MC_CMD_PUT_FPGAREG 0xa
550
551 /* MC_CMD_PUT_FPGAREG_IN msgrequest */
552 #define MC_CMD_PUT_FPGAREG_IN_LENMIN 5
553 #define MC_CMD_PUT_FPGAREG_IN_LENMAX 252
554 #define MC_CMD_PUT_FPGAREG_IN_LEN(num) (4+1*(num))
555 #define MC_CMD_PUT_FPGAREG_IN_ADDR_OFST 0
556 #define MC_CMD_PUT_FPGAREG_IN_BUFFER_OFST 4
557 #define MC_CMD_PUT_FPGAREG_IN_BUFFER_LEN 1
558 #define MC_CMD_PUT_FPGAREG_IN_BUFFER_MINNUM 1
559 #define MC_CMD_PUT_FPGAREG_IN_BUFFER_MAXNUM 248
560
561 /* MC_CMD_PUT_FPGAREG_OUT msgresponse */
562 #define MC_CMD_PUT_FPGAREG_OUT_LEN 0
563
564
565 /***********************************/
566 /* MC_CMD_PTP
567 * Perform PTP operation
568 */
569 #define MC_CMD_PTP 0xb
570
571 /* MC_CMD_PTP_IN msgrequest */
572 #define MC_CMD_PTP_IN_LEN 1
573 #define MC_CMD_PTP_IN_OP_OFST 0
574 #define MC_CMD_PTP_IN_OP_LEN 1
575 #define MC_CMD_PTP_OP_ENABLE 0x1 /* enum */
576 #define MC_CMD_PTP_OP_DISABLE 0x2 /* enum */
577 #define MC_CMD_PTP_OP_TRANSMIT 0x3 /* enum */
578 #define MC_CMD_PTP_OP_READ_NIC_TIME 0x4 /* enum */
579 #define MC_CMD_PTP_OP_STATUS 0x5 /* enum */
580 #define MC_CMD_PTP_OP_ADJUST 0x6 /* enum */
581 #define MC_CMD_PTP_OP_SYNCHRONIZE 0x7 /* enum */
582 #define MC_CMD_PTP_OP_MANFTEST_BASIC 0x8 /* enum */
583 #define MC_CMD_PTP_OP_MANFTEST_PACKET 0x9 /* enum */
584 #define MC_CMD_PTP_OP_RESET_STATS 0xa /* enum */
585 #define MC_CMD_PTP_OP_DEBUG 0xb /* enum */
586 #define MC_CMD_PTP_OP_MAX 0xc /* enum */
587
588 /* MC_CMD_PTP_IN_ENABLE msgrequest */
589 #define MC_CMD_PTP_IN_ENABLE_LEN 16
590 #define MC_CMD_PTP_IN_CMD_OFST 0
591 #define MC_CMD_PTP_IN_PERIPH_ID_OFST 4
592 #define MC_CMD_PTP_IN_ENABLE_QUEUE_OFST 8
593 #define MC_CMD_PTP_IN_ENABLE_MODE_OFST 12
594 #define MC_CMD_PTP_MODE_V1 0x0 /* enum */
595 #define MC_CMD_PTP_MODE_V1_VLAN 0x1 /* enum */
596 #define MC_CMD_PTP_MODE_V2 0x2 /* enum */
597 #define MC_CMD_PTP_MODE_V2_VLAN 0x3 /* enum */
598
599 /* MC_CMD_PTP_IN_DISABLE msgrequest */
600 #define MC_CMD_PTP_IN_DISABLE_LEN 8
601 /* MC_CMD_PTP_IN_CMD_OFST 0 */
602 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
603
604 /* MC_CMD_PTP_IN_TRANSMIT msgrequest */
605 #define MC_CMD_PTP_IN_TRANSMIT_LENMIN 13
606 #define MC_CMD_PTP_IN_TRANSMIT_LENMAX 252
607 #define MC_CMD_PTP_IN_TRANSMIT_LEN(num) (12+1*(num))
608 /* MC_CMD_PTP_IN_CMD_OFST 0 */
609 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
610 #define MC_CMD_PTP_IN_TRANSMIT_LENGTH_OFST 8
611 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_OFST 12
612 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_LEN 1
613 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_MINNUM 1
614 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_MAXNUM 240
615
616 /* MC_CMD_PTP_IN_READ_NIC_TIME msgrequest */
617 #define MC_CMD_PTP_IN_READ_NIC_TIME_LEN 8
618 /* MC_CMD_PTP_IN_CMD_OFST 0 */
619 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
620
621 /* MC_CMD_PTP_IN_STATUS msgrequest */
622 #define MC_CMD_PTP_IN_STATUS_LEN 8
623 /* MC_CMD_PTP_IN_CMD_OFST 0 */
624 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
625
626 /* MC_CMD_PTP_IN_ADJUST msgrequest */
627 #define MC_CMD_PTP_IN_ADJUST_LEN 24
628 /* MC_CMD_PTP_IN_CMD_OFST 0 */
629 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
630 #define MC_CMD_PTP_IN_ADJUST_FREQ_OFST 8
631 #define MC_CMD_PTP_IN_ADJUST_FREQ_LEN 8
632 #define MC_CMD_PTP_IN_ADJUST_FREQ_LO_OFST 8
633 #define MC_CMD_PTP_IN_ADJUST_FREQ_HI_OFST 12
634 #define MC_CMD_PTP_IN_ADJUST_BITS 0x28 /* enum */
635 #define MC_CMD_PTP_IN_ADJUST_SECONDS_OFST 16
636 #define MC_CMD_PTP_IN_ADJUST_NANOSECONDS_OFST 20
637
638 /* MC_CMD_PTP_IN_SYNCHRONIZE msgrequest */
639 #define MC_CMD_PTP_IN_SYNCHRONIZE_LEN 20
640 /* MC_CMD_PTP_IN_CMD_OFST 0 */
641 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
642 #define MC_CMD_PTP_IN_SYNCHRONIZE_NUMTIMESETS_OFST 8
643 #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_OFST 12
644 #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LEN 8
645 #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LO_OFST 12
646 #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_HI_OFST 16
647
648 /* MC_CMD_PTP_IN_MANFTEST_BASIC msgrequest */
649 #define MC_CMD_PTP_IN_MANFTEST_BASIC_LEN 8
650 /* MC_CMD_PTP_IN_CMD_OFST 0 */
651 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
652
653 /* MC_CMD_PTP_IN_MANFTEST_PACKET msgrequest */
654 #define MC_CMD_PTP_IN_MANFTEST_PACKET_LEN 12
655 /* MC_CMD_PTP_IN_CMD_OFST 0 */
656 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
657 #define MC_CMD_PTP_IN_MANFTEST_PACKET_TEST_ENABLE_OFST 8
658
659 /* MC_CMD_PTP_IN_RESET_STATS msgrequest */
660 #define MC_CMD_PTP_IN_RESET_STATS_LEN 8
661 /* MC_CMD_PTP_IN_CMD_OFST 0 */
662 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
663
664 /* MC_CMD_PTP_IN_DEBUG msgrequest */
665 #define MC_CMD_PTP_IN_DEBUG_LEN 12
666 /* MC_CMD_PTP_IN_CMD_OFST 0 */
667 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
668 #define MC_CMD_PTP_IN_DEBUG_DEBUG_PARAM_OFST 8
669
670 /* MC_CMD_PTP_OUT msgresponse */
671 #define MC_CMD_PTP_OUT_LEN 0
672
673 /* MC_CMD_PTP_OUT_TRANSMIT msgresponse */
674 #define MC_CMD_PTP_OUT_TRANSMIT_LEN 8
675 #define MC_CMD_PTP_OUT_TRANSMIT_SECONDS_OFST 0
676 #define MC_CMD_PTP_OUT_TRANSMIT_NANOSECONDS_OFST 4
677
678 /* MC_CMD_PTP_OUT_READ_NIC_TIME msgresponse */
679 #define MC_CMD_PTP_OUT_READ_NIC_TIME_LEN 8
680 #define MC_CMD_PTP_OUT_READ_NIC_TIME_SECONDS_OFST 0
681 #define MC_CMD_PTP_OUT_READ_NIC_TIME_NANOSECONDS_OFST 4
682
683 /* MC_CMD_PTP_OUT_STATUS msgresponse */
684 #define MC_CMD_PTP_OUT_STATUS_LEN 64
685 #define MC_CMD_PTP_OUT_STATUS_CLOCK_FREQ_OFST 0
686 #define MC_CMD_PTP_OUT_STATUS_STATS_TX_OFST 4
687 #define MC_CMD_PTP_OUT_STATUS_STATS_RX_OFST 8
688 #define MC_CMD_PTP_OUT_STATUS_STATS_TS_OFST 12
689 #define MC_CMD_PTP_OUT_STATUS_STATS_FM_OFST 16
690 #define MC_CMD_PTP_OUT_STATUS_STATS_NFM_OFST 20
691 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFLOW_OFST 24
692 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_BAD_OFST 28
693 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MIN_OFST 32
694 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MAX_OFST 36
695 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_LAST_OFST 40
696 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MEAN_OFST 44
697 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MIN_OFST 48
698 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MAX_OFST 52
699 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_LAST_OFST 56
700 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MEAN_OFST 60
701
702 /* MC_CMD_PTP_OUT_SYNCHRONIZE msgresponse */
703 #define MC_CMD_PTP_OUT_SYNCHRONIZE_LENMIN 20
704 #define MC_CMD_PTP_OUT_SYNCHRONIZE_LENMAX 240
705 #define MC_CMD_PTP_OUT_SYNCHRONIZE_LEN(num) (0+20*(num))
706 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_OFST 0
707 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_LEN 20
708 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MINNUM 1
709 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MAXNUM 12
710 #define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTSTART_OFST 0
711 #define MC_CMD_PTP_OUT_SYNCHRONIZE_SECONDS_OFST 4
712 #define MC_CMD_PTP_OUT_SYNCHRONIZE_NANOSECONDS_OFST 8
713 #define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTEND_OFST 12
714 #define MC_CMD_PTP_OUT_SYNCHRONIZE_WAITNS_OFST 16
715
716 /* MC_CMD_PTP_OUT_MANFTEST_BASIC msgresponse */
717 #define MC_CMD_PTP_OUT_MANFTEST_BASIC_LEN 8
718 #define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_RESULT_OFST 0
719 #define MC_CMD_PTP_MANF_SUCCESS 0x0 /* enum */
720 #define MC_CMD_PTP_MANF_FPGA_LOAD 0x1 /* enum */
721 #define MC_CMD_PTP_MANF_FPGA_VERSION 0x2 /* enum */
722 #define MC_CMD_PTP_MANF_FPGA_REGISTERS 0x3 /* enum */
723 #define MC_CMD_PTP_MANF_OSCILLATOR 0x4 /* enum */
724 #define MC_CMD_PTP_MANF_TIMESTAMPS 0x5 /* enum */
725 #define MC_CMD_PTP_MANF_PACKET_COUNT 0x6 /* enum */
726 #define MC_CMD_PTP_MANF_FILTER_COUNT 0x7 /* enum */
727 #define MC_CMD_PTP_MANF_PACKET_ENOUGH 0x8 /* enum */
728 #define MC_CMD_PTP_MANF_GPIO_TRIGGER 0x9 /* enum */
729 #define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_EXTOSC_OFST 4
730
731 /* MC_CMD_PTP_OUT_MANFTEST_PACKET msgresponse */
732 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_LEN 12
733 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_RESULT_OFST 0
734 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FPGACOUNT_OFST 4
735 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FILTERCOUNT_OFST 8
736
737
738 /***********************************/
739 /* MC_CMD_CSR_READ32
740 * Read 32bit words from the indirect memory map.
741 */
742 #define MC_CMD_CSR_READ32 0xc
743
744 /* MC_CMD_CSR_READ32_IN msgrequest */
745 #define MC_CMD_CSR_READ32_IN_LEN 12
746 #define MC_CMD_CSR_READ32_IN_ADDR_OFST 0
747 #define MC_CMD_CSR_READ32_IN_STEP_OFST 4
748 #define MC_CMD_CSR_READ32_IN_NUMWORDS_OFST 8
749
750 /* MC_CMD_CSR_READ32_OUT msgresponse */
751 #define MC_CMD_CSR_READ32_OUT_LENMIN 4
752 #define MC_CMD_CSR_READ32_OUT_LENMAX 252
753 #define MC_CMD_CSR_READ32_OUT_LEN(num) (0+4*(num))
754 #define MC_CMD_CSR_READ32_OUT_BUFFER_OFST 0
755 #define MC_CMD_CSR_READ32_OUT_BUFFER_LEN 4
756 #define MC_CMD_CSR_READ32_OUT_BUFFER_MINNUM 1
757 #define MC_CMD_CSR_READ32_OUT_BUFFER_MAXNUM 63
758
759
760 /***********************************/
761 /* MC_CMD_CSR_WRITE32
762 * Write 32bit dwords to the indirect memory map.
763 */
764 #define MC_CMD_CSR_WRITE32 0xd
765
766 /* MC_CMD_CSR_WRITE32_IN msgrequest */
767 #define MC_CMD_CSR_WRITE32_IN_LENMIN 12
768 #define MC_CMD_CSR_WRITE32_IN_LENMAX 252
769 #define MC_CMD_CSR_WRITE32_IN_LEN(num) (8+4*(num))
770 #define MC_CMD_CSR_WRITE32_IN_ADDR_OFST 0
771 #define MC_CMD_CSR_WRITE32_IN_STEP_OFST 4
772 #define MC_CMD_CSR_WRITE32_IN_BUFFER_OFST 8
773 #define MC_CMD_CSR_WRITE32_IN_BUFFER_LEN 4
774 #define MC_CMD_CSR_WRITE32_IN_BUFFER_MINNUM 1
775 #define MC_CMD_CSR_WRITE32_IN_BUFFER_MAXNUM 61
776
777 /* MC_CMD_CSR_WRITE32_OUT msgresponse */
778 #define MC_CMD_CSR_WRITE32_OUT_LEN 4
779 #define MC_CMD_CSR_WRITE32_OUT_STATUS_OFST 0
780
781
782 /***********************************/
783 /* MC_CMD_STACKINFO
784 * Get stack information.
785 */
786 #define MC_CMD_STACKINFO 0xf
787
788 /* MC_CMD_STACKINFO_IN msgrequest */
789 #define MC_CMD_STACKINFO_IN_LEN 0
790
791 /* MC_CMD_STACKINFO_OUT msgresponse */
792 #define MC_CMD_STACKINFO_OUT_LENMIN 12
793 #define MC_CMD_STACKINFO_OUT_LENMAX 252
794 #define MC_CMD_STACKINFO_OUT_LEN(num) (0+12*(num))
795 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_OFST 0
796 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_LEN 12
797 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_MINNUM 1
798 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_MAXNUM 21
799
800
801 /***********************************/
802 /* MC_CMD_MDIO_READ
803 * MDIO register read.
804 */
805 #define MC_CMD_MDIO_READ 0x10
806
807 /* MC_CMD_MDIO_READ_IN msgrequest */
808 #define MC_CMD_MDIO_READ_IN_LEN 16
809 #define MC_CMD_MDIO_READ_IN_BUS_OFST 0
810 #define MC_CMD_MDIO_BUS_INTERNAL 0x0 /* enum */
811 #define MC_CMD_MDIO_BUS_EXTERNAL 0x1 /* enum */
812 #define MC_CMD_MDIO_READ_IN_PRTAD_OFST 4
813 #define MC_CMD_MDIO_READ_IN_DEVAD_OFST 8
814 #define MC_CMD_MDIO_CLAUSE22 0x20 /* enum */
815 #define MC_CMD_MDIO_READ_IN_ADDR_OFST 12
816
817 /* MC_CMD_MDIO_READ_OUT msgresponse */
818 #define MC_CMD_MDIO_READ_OUT_LEN 8
819 #define MC_CMD_MDIO_READ_OUT_VALUE_OFST 0
820 #define MC_CMD_MDIO_READ_OUT_STATUS_OFST 4
821 #define MC_CMD_MDIO_STATUS_GOOD 0x8 /* enum */
822
823
824 /***********************************/
825 /* MC_CMD_MDIO_WRITE
826 * MDIO register write.
827 */
828 #define MC_CMD_MDIO_WRITE 0x11
829
830 /* MC_CMD_MDIO_WRITE_IN msgrequest */
831 #define MC_CMD_MDIO_WRITE_IN_LEN 20
832 #define MC_CMD_MDIO_WRITE_IN_BUS_OFST 0
833 /* MC_CMD_MDIO_BUS_INTERNAL 0x0 */
834 /* MC_CMD_MDIO_BUS_EXTERNAL 0x1 */
835 #define MC_CMD_MDIO_WRITE_IN_PRTAD_OFST 4
836 #define MC_CMD_MDIO_WRITE_IN_DEVAD_OFST 8
837 /* MC_CMD_MDIO_CLAUSE22 0x20 */
838 #define MC_CMD_MDIO_WRITE_IN_ADDR_OFST 12
839 #define MC_CMD_MDIO_WRITE_IN_VALUE_OFST 16
840
841 /* MC_CMD_MDIO_WRITE_OUT msgresponse */
842 #define MC_CMD_MDIO_WRITE_OUT_LEN 4
843 #define MC_CMD_MDIO_WRITE_OUT_STATUS_OFST 0
844 /* MC_CMD_MDIO_STATUS_GOOD 0x8 */
845
846
847 /***********************************/
848 /* MC_CMD_DBI_WRITE
849 * Write DBI register(s).
850 */
851 #define MC_CMD_DBI_WRITE 0x12
852
853 /* MC_CMD_DBI_WRITE_IN msgrequest */
854 #define MC_CMD_DBI_WRITE_IN_LENMIN 12
855 #define MC_CMD_DBI_WRITE_IN_LENMAX 252
856 #define MC_CMD_DBI_WRITE_IN_LEN(num) (0+12*(num))
857 #define MC_CMD_DBI_WRITE_IN_DBIWROP_OFST 0
858 #define MC_CMD_DBI_WRITE_IN_DBIWROP_LEN 12
859 #define MC_CMD_DBI_WRITE_IN_DBIWROP_MINNUM 1
860 #define MC_CMD_DBI_WRITE_IN_DBIWROP_MAXNUM 21
861
862 /* MC_CMD_DBI_WRITE_OUT msgresponse */
863 #define MC_CMD_DBI_WRITE_OUT_LEN 0
864
865 /* MC_CMD_DBIWROP_TYPEDEF structuredef */
866 #define MC_CMD_DBIWROP_TYPEDEF_LEN 12
867 #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_OFST 0
868 #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_LBN 0
869 #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_WIDTH 32
870 #define MC_CMD_DBIWROP_TYPEDEF_BYTE_MASK_OFST 4
871 #define MC_CMD_DBIWROP_TYPEDEF_BYTE_MASK_LBN 32
872 #define MC_CMD_DBIWROP_TYPEDEF_BYTE_MASK_WIDTH 32
873 #define MC_CMD_DBIWROP_TYPEDEF_VALUE_OFST 8
874 #define MC_CMD_DBIWROP_TYPEDEF_VALUE_LBN 64
875 #define MC_CMD_DBIWROP_TYPEDEF_VALUE_WIDTH 32
876
877
878 /***********************************/
879 /* MC_CMD_PORT_READ32
880 * Read a 32-bit register from the indirect port register map.
881 */
882 #define MC_CMD_PORT_READ32 0x14
883
884 /* MC_CMD_PORT_READ32_IN msgrequest */
885 #define MC_CMD_PORT_READ32_IN_LEN 4
886 #define MC_CMD_PORT_READ32_IN_ADDR_OFST 0
887
888 /* MC_CMD_PORT_READ32_OUT msgresponse */
889 #define MC_CMD_PORT_READ32_OUT_LEN 8
890 #define MC_CMD_PORT_READ32_OUT_VALUE_OFST 0
891 #define MC_CMD_PORT_READ32_OUT_STATUS_OFST 4
892
893
894 /***********************************/
895 /* MC_CMD_PORT_WRITE32
896 * Write a 32-bit register to the indirect port register map.
897 */
898 #define MC_CMD_PORT_WRITE32 0x15
899
900 /* MC_CMD_PORT_WRITE32_IN msgrequest */
901 #define MC_CMD_PORT_WRITE32_IN_LEN 8
902 #define MC_CMD_PORT_WRITE32_IN_ADDR_OFST 0
903 #define MC_CMD_PORT_WRITE32_IN_VALUE_OFST 4
904
905 /* MC_CMD_PORT_WRITE32_OUT msgresponse */
906 #define MC_CMD_PORT_WRITE32_OUT_LEN 4
907 #define MC_CMD_PORT_WRITE32_OUT_STATUS_OFST 0
908
909
910 /***********************************/
911 /* MC_CMD_PORT_READ128
912 * Read a 128-bit register from the indirect port register map.
913 */
914 #define MC_CMD_PORT_READ128 0x16
915
916 /* MC_CMD_PORT_READ128_IN msgrequest */
917 #define MC_CMD_PORT_READ128_IN_LEN 4
918 #define MC_CMD_PORT_READ128_IN_ADDR_OFST 0
919
920 /* MC_CMD_PORT_READ128_OUT msgresponse */
921 #define MC_CMD_PORT_READ128_OUT_LEN 20
922 #define MC_CMD_PORT_READ128_OUT_VALUE_OFST 0
923 #define MC_CMD_PORT_READ128_OUT_VALUE_LEN 16
924 #define MC_CMD_PORT_READ128_OUT_STATUS_OFST 16
925
926
927 /***********************************/
928 /* MC_CMD_PORT_WRITE128
929 * Write a 128-bit register to the indirect port register map.
930 */
931 #define MC_CMD_PORT_WRITE128 0x17
932
933 /* MC_CMD_PORT_WRITE128_IN msgrequest */
934 #define MC_CMD_PORT_WRITE128_IN_LEN 20
935 #define MC_CMD_PORT_WRITE128_IN_ADDR_OFST 0
936 #define MC_CMD_PORT_WRITE128_IN_VALUE_OFST 4
937 #define MC_CMD_PORT_WRITE128_IN_VALUE_LEN 16
938
939 /* MC_CMD_PORT_WRITE128_OUT msgresponse */
940 #define MC_CMD_PORT_WRITE128_OUT_LEN 4
941 #define MC_CMD_PORT_WRITE128_OUT_STATUS_OFST 0
942
943
944 /***********************************/
945 /* MC_CMD_GET_BOARD_CFG
946 * Returns the MC firmware configuration structure.
947 */
948 #define MC_CMD_GET_BOARD_CFG 0x18
949
950 /* MC_CMD_GET_BOARD_CFG_IN msgrequest */
951 #define MC_CMD_GET_BOARD_CFG_IN_LEN 0
952
953 /* MC_CMD_GET_BOARD_CFG_OUT msgresponse */
954 #define MC_CMD_GET_BOARD_CFG_OUT_LENMIN 96
955 #define MC_CMD_GET_BOARD_CFG_OUT_LENMAX 136
956 #define MC_CMD_GET_BOARD_CFG_OUT_LEN(num) (72+2*(num))
957 #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_TYPE_OFST 0
958 #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_OFST 4
959 #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_LEN 32
960 #define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT0_OFST 36
961 #define MC_CMD_CAPABILITIES_SMALL_BUF_TBL_LBN 0x0 /* enum */
962 #define MC_CMD_CAPABILITIES_SMALL_BUF_TBL_WIDTH 0x1 /* enum */
963 #define MC_CMD_CAPABILITIES_TURBO_LBN 0x1 /* enum */
964 #define MC_CMD_CAPABILITIES_TURBO_WIDTH 0x1 /* enum */
965 #define MC_CMD_CAPABILITIES_TURBO_ACTIVE_LBN 0x2 /* enum */
966 #define MC_CMD_CAPABILITIES_TURBO_ACTIVE_WIDTH 0x1 /* enum */
967 #define MC_CMD_CAPABILITIES_PTP_LBN 0x3 /* enum */
968 #define MC_CMD_CAPABILITIES_PTP_WIDTH 0x1 /* enum */
969 #define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT1_OFST 40
970 /* Enum values, see field(s): */
971 /* CAPABILITIES_PORT0 */
972 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_OFST 44
973 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_LEN 6
974 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_OFST 50
975 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_LEN 6
976 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT0_OFST 56
977 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT1_OFST 60
978 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT0_OFST 64
979 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT1_OFST 68
980 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_OFST 72
981 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_LEN 2
982 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MINNUM 12
983 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MAXNUM 32
984
985
986 /***********************************/
987 /* MC_CMD_DBI_READX
988 * Read DBI register(s).
989 */
990 #define MC_CMD_DBI_READX 0x19
991
992 /* MC_CMD_DBI_READX_IN msgrequest */
993 #define MC_CMD_DBI_READX_IN_LENMIN 8
994 #define MC_CMD_DBI_READX_IN_LENMAX 248
995 #define MC_CMD_DBI_READX_IN_LEN(num) (0+8*(num))
996 #define MC_CMD_DBI_READX_IN_DBIRDOP_OFST 0
997 #define MC_CMD_DBI_READX_IN_DBIRDOP_LEN 8
998 #define MC_CMD_DBI_READX_IN_DBIRDOP_LO_OFST 0
999 #define MC_CMD_DBI_READX_IN_DBIRDOP_HI_OFST 4
1000 #define MC_CMD_DBI_READX_IN_DBIRDOP_MINNUM 1
1001 #define MC_CMD_DBI_READX_IN_DBIRDOP_MAXNUM 31
1002
1003 /* MC_CMD_DBI_READX_OUT msgresponse */
1004 #define MC_CMD_DBI_READX_OUT_LENMIN 4
1005 #define MC_CMD_DBI_READX_OUT_LENMAX 252
1006 #define MC_CMD_DBI_READX_OUT_LEN(num) (0+4*(num))
1007 #define MC_CMD_DBI_READX_OUT_VALUE_OFST 0
1008 #define MC_CMD_DBI_READX_OUT_VALUE_LEN 4
1009 #define MC_CMD_DBI_READX_OUT_VALUE_MINNUM 1
1010 #define MC_CMD_DBI_READX_OUT_VALUE_MAXNUM 63
1011
1012
1013 /***********************************/
1014 /* MC_CMD_SET_RAND_SEED
1015 * Set the 16byte seed for the MC pseudo-random generator.
1016 */
1017 #define MC_CMD_SET_RAND_SEED 0x1a
1018
1019 /* MC_CMD_SET_RAND_SEED_IN msgrequest */
1020 #define MC_CMD_SET_RAND_SEED_IN_LEN 16
1021 #define MC_CMD_SET_RAND_SEED_IN_SEED_OFST 0
1022 #define MC_CMD_SET_RAND_SEED_IN_SEED_LEN 16
1023
1024 /* MC_CMD_SET_RAND_SEED_OUT msgresponse */
1025 #define MC_CMD_SET_RAND_SEED_OUT_LEN 0
1026
1027
1028 /***********************************/
1029 /* MC_CMD_LTSSM_HIST
1030 * Retrieve the history of the PCIE LTSSM.
1031 */
1032 #define MC_CMD_LTSSM_HIST 0x1b
1033
1034 /* MC_CMD_LTSSM_HIST_IN msgrequest */
1035 #define MC_CMD_LTSSM_HIST_IN_LEN 0
1036
1037 /* MC_CMD_LTSSM_HIST_OUT msgresponse */
1038 #define MC_CMD_LTSSM_HIST_OUT_LENMIN 0
1039 #define MC_CMD_LTSSM_HIST_OUT_LENMAX 252
1040 #define MC_CMD_LTSSM_HIST_OUT_LEN(num) (0+4*(num))
1041 #define MC_CMD_LTSSM_HIST_OUT_DATA_OFST 0
1042 #define MC_CMD_LTSSM_HIST_OUT_DATA_LEN 4
1043 #define MC_CMD_LTSSM_HIST_OUT_DATA_MINNUM 0
1044 #define MC_CMD_LTSSM_HIST_OUT_DATA_MAXNUM 63
1045
1046
1047 /***********************************/
1048 /* MC_CMD_DRV_ATTACH
1049 * Inform MCPU that this port is managed on the host.
1050 */
1051 #define MC_CMD_DRV_ATTACH 0x1c
1052
1053 /* MC_CMD_DRV_ATTACH_IN msgrequest */
1054 #define MC_CMD_DRV_ATTACH_IN_LEN 8
1055 #define MC_CMD_DRV_ATTACH_IN_NEW_STATE_OFST 0
1056 #define MC_CMD_DRV_ATTACH_IN_UPDATE_OFST 4
1057
1058 /* MC_CMD_DRV_ATTACH_OUT msgresponse */
1059 #define MC_CMD_DRV_ATTACH_OUT_LEN 4
1060 #define MC_CMD_DRV_ATTACH_OUT_OLD_STATE_OFST 0
1061
1062
1063 /***********************************/
1064 /* MC_CMD_NCSI_PROD
1065 * Trigger an NC-SI event.
1066 */
1067 #define MC_CMD_NCSI_PROD 0x1d
1068
1069 /* MC_CMD_NCSI_PROD_IN msgrequest */
1070 #define MC_CMD_NCSI_PROD_IN_LEN 4
1071 #define MC_CMD_NCSI_PROD_IN_EVENTS_OFST 0
1072 #define MC_CMD_NCSI_PROD_LINKCHANGE 0x0 /* enum */
1073 #define MC_CMD_NCSI_PROD_RESET 0x1 /* enum */
1074 #define MC_CMD_NCSI_PROD_DRVATTACH 0x2 /* enum */
1075 #define MC_CMD_NCSI_PROD_IN_LINKCHANGE_LBN 0
1076 #define MC_CMD_NCSI_PROD_IN_LINKCHANGE_WIDTH 1
1077 #define MC_CMD_NCSI_PROD_IN_RESET_LBN 1
1078 #define MC_CMD_NCSI_PROD_IN_RESET_WIDTH 1
1079 #define MC_CMD_NCSI_PROD_IN_DRVATTACH_LBN 2
1080 #define MC_CMD_NCSI_PROD_IN_DRVATTACH_WIDTH 1
1081
1082 /* MC_CMD_NCSI_PROD_OUT msgresponse */
1083 #define MC_CMD_NCSI_PROD_OUT_LEN 0
1084
1085
1086 /***********************************/
1087 /* MC_CMD_SHMUART
1088 * Route UART output to circular buffer in shared memory instead.
1089 */
1090 #define MC_CMD_SHMUART 0x1f
1091
1092 /* MC_CMD_SHMUART_IN msgrequest */
1093 #define MC_CMD_SHMUART_IN_LEN 4
1094 #define MC_CMD_SHMUART_IN_FLAG_OFST 0
1095
1096 /* MC_CMD_SHMUART_OUT msgresponse */
1097 #define MC_CMD_SHMUART_OUT_LEN 0
1098
1099
1100 /***********************************/
1101 /* MC_CMD_PORT_RESET
1102 * Generic per-port reset.
1103 */
1104 #define MC_CMD_PORT_RESET 0x20
1105
1106 /* MC_CMD_PORT_RESET_IN msgrequest */
1107 #define MC_CMD_PORT_RESET_IN_LEN 0
1108
1109 /* MC_CMD_PORT_RESET_OUT msgresponse */
1110 #define MC_CMD_PORT_RESET_OUT_LEN 0
1111
1112
1113 /***********************************/
1114 /* MC_CMD_PCIE_CREDITS
1115 * Read instantaneous and minimum flow control thresholds.
1116 */
1117 #define MC_CMD_PCIE_CREDITS 0x21
1118
1119 /* MC_CMD_PCIE_CREDITS_IN msgrequest */
1120 #define MC_CMD_PCIE_CREDITS_IN_LEN 8
1121 #define MC_CMD_PCIE_CREDITS_IN_POLL_PERIOD_OFST 0
1122 #define MC_CMD_PCIE_CREDITS_IN_WIPE_OFST 4
1123
1124 /* MC_CMD_PCIE_CREDITS_OUT msgresponse */
1125 #define MC_CMD_PCIE_CREDITS_OUT_LEN 16
1126 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_HDR_OFST 0
1127 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_HDR_LEN 2
1128 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_DATA_OFST 2
1129 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_DATA_LEN 2
1130 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_HDR_OFST 4
1131 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_HDR_LEN 2
1132 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_DATA_OFST 6
1133 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_DATA_LEN 2
1134 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_HDR_OFST 8
1135 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_HDR_LEN 2
1136 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_DATA_OFST 10
1137 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_DATA_LEN 2
1138 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_HDR_OFST 12
1139 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_HDR_LEN 2
1140 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_DATA_OFST 14
1141 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_DATA_LEN 2
1142
1143
1144 /***********************************/
1145 /* MC_CMD_RXD_MONITOR
1146 * Get histogram of RX queue fill level.
1147 */
1148 #define MC_CMD_RXD_MONITOR 0x22
1149
1150 /* MC_CMD_RXD_MONITOR_IN msgrequest */
1151 #define MC_CMD_RXD_MONITOR_IN_LEN 12
1152 #define MC_CMD_RXD_MONITOR_IN_QID_OFST 0
1153 #define MC_CMD_RXD_MONITOR_IN_POLL_PERIOD_OFST 4
1154 #define MC_CMD_RXD_MONITOR_IN_WIPE_OFST 8
1155
1156 /* MC_CMD_RXD_MONITOR_OUT msgresponse */
1157 #define MC_CMD_RXD_MONITOR_OUT_LEN 80
1158 #define MC_CMD_RXD_MONITOR_OUT_QID_OFST 0
1159 #define MC_CMD_RXD_MONITOR_OUT_RING_FILL_OFST 4
1160 #define MC_CMD_RXD_MONITOR_OUT_CACHE_FILL_OFST 8
1161 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_1_OFST 12
1162 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_2_OFST 16
1163 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_4_OFST 20
1164 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_8_OFST 24
1165 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_16_OFST 28
1166 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_32_OFST 32
1167 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_64_OFST 36
1168 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_128_OFST 40
1169 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_256_OFST 44
1170 #define MC_CMD_RXD_MONITOR_OUT_RING_GE_256_OFST 48
1171 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_1_OFST 52
1172 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_2_OFST 56
1173 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_4_OFST 60
1174 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_8_OFST 64
1175 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_16_OFST 68
1176 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_32_OFST 72
1177 #define MC_CMD_RXD_MONITOR_OUT_CACHE_GE_32_OFST 76
1178
1179
1180 /***********************************/
1181 /* MC_CMD_PUTS
1182 * puts(3) implementation over MCDI
1183 */
1184 #define MC_CMD_PUTS 0x23
1185
1186 /* MC_CMD_PUTS_IN msgrequest */
1187 #define MC_CMD_PUTS_IN_LENMIN 13
1188 #define MC_CMD_PUTS_IN_LENMAX 252
1189 #define MC_CMD_PUTS_IN_LEN(num) (12+1*(num))
1190 #define MC_CMD_PUTS_IN_DEST_OFST 0
1191 #define MC_CMD_PUTS_IN_UART_LBN 0
1192 #define MC_CMD_PUTS_IN_UART_WIDTH 1
1193 #define MC_CMD_PUTS_IN_PORT_LBN 1
1194 #define MC_CMD_PUTS_IN_PORT_WIDTH 1
1195 #define MC_CMD_PUTS_IN_DHOST_OFST 4
1196 #define MC_CMD_PUTS_IN_DHOST_LEN 6
1197 #define MC_CMD_PUTS_IN_STRING_OFST 12
1198 #define MC_CMD_PUTS_IN_STRING_LEN 1
1199 #define MC_CMD_PUTS_IN_STRING_MINNUM 1
1200 #define MC_CMD_PUTS_IN_STRING_MAXNUM 240
1201
1202 /* MC_CMD_PUTS_OUT msgresponse */
1203 #define MC_CMD_PUTS_OUT_LEN 0
1204
1205
1206 /***********************************/
1207 /* MC_CMD_GET_PHY_CFG
1208 * Report PHY configuration.
1209 */
1210 #define MC_CMD_GET_PHY_CFG 0x24
1211
1212 /* MC_CMD_GET_PHY_CFG_IN msgrequest */
1213 #define MC_CMD_GET_PHY_CFG_IN_LEN 0
1214
1215 /* MC_CMD_GET_PHY_CFG_OUT msgresponse */
1216 #define MC_CMD_GET_PHY_CFG_OUT_LEN 72
1217 #define MC_CMD_GET_PHY_CFG_OUT_FLAGS_OFST 0
1218 #define MC_CMD_GET_PHY_CFG_OUT_PRESENT_LBN 0
1219 #define MC_CMD_GET_PHY_CFG_OUT_PRESENT_WIDTH 1
1220 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_LBN 1
1221 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_WIDTH 1
1222 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_LBN 2
1223 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_WIDTH 1
1224 #define MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_LBN 3
1225 #define MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_WIDTH 1
1226 #define MC_CMD_GET_PHY_CFG_OUT_POWEROFF_LBN 4
1227 #define MC_CMD_GET_PHY_CFG_OUT_POWEROFF_WIDTH 1
1228 #define MC_CMD_GET_PHY_CFG_OUT_TXDIS_LBN 5
1229 #define MC_CMD_GET_PHY_CFG_OUT_TXDIS_WIDTH 1
1230 #define MC_CMD_GET_PHY_CFG_OUT_BIST_LBN 6
1231 #define MC_CMD_GET_PHY_CFG_OUT_BIST_WIDTH 1
1232 #define MC_CMD_GET_PHY_CFG_OUT_TYPE_OFST 4
1233 #define MC_CMD_GET_PHY_CFG_OUT_SUPPORTED_CAP_OFST 8
1234 #define MC_CMD_PHY_CAP_10HDX_LBN 1
1235 #define MC_CMD_PHY_CAP_10HDX_WIDTH 1
1236 #define MC_CMD_PHY_CAP_10FDX_LBN 2
1237 #define MC_CMD_PHY_CAP_10FDX_WIDTH 1
1238 #define MC_CMD_PHY_CAP_100HDX_LBN 3
1239 #define MC_CMD_PHY_CAP_100HDX_WIDTH 1
1240 #define MC_CMD_PHY_CAP_100FDX_LBN 4
1241 #define MC_CMD_PHY_CAP_100FDX_WIDTH 1
1242 #define MC_CMD_PHY_CAP_1000HDX_LBN 5
1243 #define MC_CMD_PHY_CAP_1000HDX_WIDTH 1
1244 #define MC_CMD_PHY_CAP_1000FDX_LBN 6
1245 #define MC_CMD_PHY_CAP_1000FDX_WIDTH 1
1246 #define MC_CMD_PHY_CAP_10000FDX_LBN 7
1247 #define MC_CMD_PHY_CAP_10000FDX_WIDTH 1
1248 #define MC_CMD_PHY_CAP_PAUSE_LBN 8
1249 #define MC_CMD_PHY_CAP_PAUSE_WIDTH 1
1250 #define MC_CMD_PHY_CAP_ASYM_LBN 9
1251 #define MC_CMD_PHY_CAP_ASYM_WIDTH 1
1252 #define MC_CMD_PHY_CAP_AN_LBN 10
1253 #define MC_CMD_PHY_CAP_AN_WIDTH 1
1254 #define MC_CMD_GET_PHY_CFG_OUT_CHANNEL_OFST 12
1255 #define MC_CMD_GET_PHY_CFG_OUT_PRT_OFST 16
1256 #define MC_CMD_GET_PHY_CFG_OUT_STATS_MASK_OFST 20
1257 #define MC_CMD_GET_PHY_CFG_OUT_NAME_OFST 24
1258 #define MC_CMD_GET_PHY_CFG_OUT_NAME_LEN 20
1259 #define MC_CMD_GET_PHY_CFG_OUT_MEDIA_TYPE_OFST 44
1260 #define MC_CMD_MEDIA_XAUI 0x1 /* enum */
1261 #define MC_CMD_MEDIA_CX4 0x2 /* enum */
1262 #define MC_CMD_MEDIA_KX4 0x3 /* enum */
1263 #define MC_CMD_MEDIA_XFP 0x4 /* enum */
1264 #define MC_CMD_MEDIA_SFP_PLUS 0x5 /* enum */
1265 #define MC_CMD_MEDIA_BASE_T 0x6 /* enum */
1266 #define MC_CMD_GET_PHY_CFG_OUT_MMD_MASK_OFST 48
1267 #define MC_CMD_MMD_CLAUSE22 0x0 /* enum */
1268 #define MC_CMD_MMD_CLAUSE45_PMAPMD 0x1 /* enum */
1269 #define MC_CMD_MMD_CLAUSE45_WIS 0x2 /* enum */
1270 #define MC_CMD_MMD_CLAUSE45_PCS 0x3 /* enum */
1271 #define MC_CMD_MMD_CLAUSE45_PHYXS 0x4 /* enum */
1272 #define MC_CMD_MMD_CLAUSE45_DTEXS 0x5 /* enum */
1273 #define MC_CMD_MMD_CLAUSE45_TC 0x6 /* enum */
1274 #define MC_CMD_MMD_CLAUSE45_AN 0x7 /* enum */
1275 #define MC_CMD_MMD_CLAUSE45_C22EXT 0x1d /* enum */
1276 #define MC_CMD_MMD_CLAUSE45_VEND1 0x1e /* enum */
1277 #define MC_CMD_MMD_CLAUSE45_VEND2 0x1f /* enum */
1278 #define MC_CMD_GET_PHY_CFG_OUT_REVISION_OFST 52
1279 #define MC_CMD_GET_PHY_CFG_OUT_REVISION_LEN 20
1280
1281
1282 /***********************************/
1283 /* MC_CMD_START_BIST
1284 * Start a BIST test on the PHY.
1285 */
1286 #define MC_CMD_START_BIST 0x25
1287
1288 /* MC_CMD_START_BIST_IN msgrequest */
1289 #define MC_CMD_START_BIST_IN_LEN 4
1290 #define MC_CMD_START_BIST_IN_TYPE_OFST 0
1291 #define MC_CMD_PHY_BIST_CABLE_SHORT 0x1 /* enum */
1292 #define MC_CMD_PHY_BIST_CABLE_LONG 0x2 /* enum */
1293 #define MC_CMD_BPX_SERDES_BIST 0x3 /* enum */
1294 #define MC_CMD_MC_LOOPBACK_BIST 0x4 /* enum */
1295 #define MC_CMD_PHY_BIST 0x5 /* enum */
1296
1297 /* MC_CMD_START_BIST_OUT msgresponse */
1298 #define MC_CMD_START_BIST_OUT_LEN 0
1299
1300
1301 /***********************************/
1302 /* MC_CMD_POLL_BIST
1303 * Poll for BIST completion.
1304 */
1305 #define MC_CMD_POLL_BIST 0x26
1306
1307 /* MC_CMD_POLL_BIST_IN msgrequest */
1308 #define MC_CMD_POLL_BIST_IN_LEN 0
1309
1310 /* MC_CMD_POLL_BIST_OUT msgresponse */
1311 #define MC_CMD_POLL_BIST_OUT_LEN 8
1312 #define MC_CMD_POLL_BIST_OUT_RESULT_OFST 0
1313 #define MC_CMD_POLL_BIST_RUNNING 0x1 /* enum */
1314 #define MC_CMD_POLL_BIST_PASSED 0x2 /* enum */
1315 #define MC_CMD_POLL_BIST_FAILED 0x3 /* enum */
1316 #define MC_CMD_POLL_BIST_TIMEOUT 0x4 /* enum */
1317 #define MC_CMD_POLL_BIST_OUT_PRIVATE_OFST 4
1318
1319 /* MC_CMD_POLL_BIST_OUT_SFT9001 msgresponse */
1320 #define MC_CMD_POLL_BIST_OUT_SFT9001_LEN 36
1321 /* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */
1322 /* Enum values, see field(s): */
1323 /* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */
1324 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_A_OFST 4
1325 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_B_OFST 8
1326 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_C_OFST 12
1327 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_D_OFST 16
1328 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_A_OFST 20
1329 #define MC_CMD_POLL_BIST_SFT9001_PAIR_OK 0x1 /* enum */
1330 #define MC_CMD_POLL_BIST_SFT9001_PAIR_OPEN 0x2 /* enum */
1331 #define MC_CMD_POLL_BIST_SFT9001_INTRA_PAIR_SHORT 0x3 /* enum */
1332 #define MC_CMD_POLL_BIST_SFT9001_INTER_PAIR_SHORT 0x4 /* enum */
1333 #define MC_CMD_POLL_BIST_SFT9001_PAIR_BUSY 0x9 /* enum */
1334 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_B_OFST 24
1335 /* Enum values, see field(s): */
1336 /* CABLE_STATUS_A */
1337 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_C_OFST 28
1338 /* Enum values, see field(s): */
1339 /* CABLE_STATUS_A */
1340 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_D_OFST 32
1341 /* Enum values, see field(s): */
1342 /* CABLE_STATUS_A */
1343
1344 /* MC_CMD_POLL_BIST_OUT_MRSFP msgresponse */
1345 #define MC_CMD_POLL_BIST_OUT_MRSFP_LEN 8
1346 /* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */
1347 /* Enum values, see field(s): */
1348 /* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */
1349 #define MC_CMD_POLL_BIST_OUT_MRSFP_TEST_OFST 4
1350 #define MC_CMD_POLL_BIST_MRSFP_TEST_COMPLETE 0x0 /* enum */
1351 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_WRITE 0x1 /* enum */
1352 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_IO_EXP 0x2 /* enum */
1353 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_MODULE 0x3 /* enum */
1354 #define MC_CMD_POLL_BIST_MRSFP_TEST_IO_EXP_I2C_CONFIGURE 0x4 /* enum */
1355 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_I2C_NO_CROSSTALK 0x5 /* enum */
1356 #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_PRESENCE 0x6 /* enum */
1357 #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_I2C_ACCESS 0x7 /* enum */
1358 #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_SANE_VALUE 0x8 /* enum */
1359
1360
1361 /***********************************/
1362 /* MC_CMD_FLUSH_RX_QUEUES
1363 * Flush receive queue(s).
1364 */
1365 #define MC_CMD_FLUSH_RX_QUEUES 0x27
1366
1367 /* MC_CMD_FLUSH_RX_QUEUES_IN msgrequest */
1368 #define MC_CMD_FLUSH_RX_QUEUES_IN_LENMIN 4
1369 #define MC_CMD_FLUSH_RX_QUEUES_IN_LENMAX 252
1370 #define MC_CMD_FLUSH_RX_QUEUES_IN_LEN(num) (0+4*(num))
1371 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_OFST 0
1372 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_LEN 4
1373 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MINNUM 1
1374 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MAXNUM 63
1375
1376 /* MC_CMD_FLUSH_RX_QUEUES_OUT msgresponse */
1377 #define MC_CMD_FLUSH_RX_QUEUES_OUT_LEN 0
1378
1379
1380 /***********************************/
1381 /* MC_CMD_GET_LOOPBACK_MODES
1382 * Get port's loopback modes.
1383 */
1384 #define MC_CMD_GET_LOOPBACK_MODES 0x28
1385
1386 /* MC_CMD_GET_LOOPBACK_MODES_IN msgrequest */
1387 #define MC_CMD_GET_LOOPBACK_MODES_IN_LEN 0
1388
1389 /* MC_CMD_GET_LOOPBACK_MODES_OUT msgresponse */
1390 #define MC_CMD_GET_LOOPBACK_MODES_OUT_LEN 32
1391 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_OFST 0
1392 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LEN 8
1393 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LO_OFST 0
1394 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_HI_OFST 4
1395 #define MC_CMD_LOOPBACK_NONE 0x0 /* enum */
1396 #define MC_CMD_LOOPBACK_DATA 0x1 /* enum */
1397 #define MC_CMD_LOOPBACK_GMAC 0x2 /* enum */
1398 #define MC_CMD_LOOPBACK_XGMII 0x3 /* enum */
1399 #define MC_CMD_LOOPBACK_XGXS 0x4 /* enum */
1400 #define MC_CMD_LOOPBACK_XAUI 0x5 /* enum */
1401 #define MC_CMD_LOOPBACK_GMII 0x6 /* enum */
1402 #define MC_CMD_LOOPBACK_SGMII 0x7 /* enum */
1403 #define MC_CMD_LOOPBACK_XGBR 0x8 /* enum */
1404 #define MC_CMD_LOOPBACK_XFI 0x9 /* enum */
1405 #define MC_CMD_LOOPBACK_XAUI_FAR 0xa /* enum */
1406 #define MC_CMD_LOOPBACK_GMII_FAR 0xb /* enum */
1407 #define MC_CMD_LOOPBACK_SGMII_FAR 0xc /* enum */
1408 #define MC_CMD_LOOPBACK_XFI_FAR 0xd /* enum */
1409 #define MC_CMD_LOOPBACK_GPHY 0xe /* enum */
1410 #define MC_CMD_LOOPBACK_PHYXS 0xf /* enum */
1411 #define MC_CMD_LOOPBACK_PCS 0x10 /* enum */
1412 #define MC_CMD_LOOPBACK_PMAPMD 0x11 /* enum */
1413 #define MC_CMD_LOOPBACK_XPORT 0x12 /* enum */
1414 #define MC_CMD_LOOPBACK_XGMII_WS 0x13 /* enum */
1415 #define MC_CMD_LOOPBACK_XAUI_WS 0x14 /* enum */
1416 #define MC_CMD_LOOPBACK_XAUI_WS_FAR 0x15 /* enum */
1417 #define MC_CMD_LOOPBACK_XAUI_WS_NEAR 0x16 /* enum */
1418 #define MC_CMD_LOOPBACK_GMII_WS 0x17 /* enum */
1419 #define MC_CMD_LOOPBACK_XFI_WS 0x18 /* enum */
1420 #define MC_CMD_LOOPBACK_XFI_WS_FAR 0x19 /* enum */
1421 #define MC_CMD_LOOPBACK_PHYXS_WS 0x1a /* enum */
1422 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_OFST 8
1423 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LEN 8
1424 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LO_OFST 8
1425 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_HI_OFST 12
1426 /* Enum values, see field(s): */
1427 /* 100M */
1428 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_OFST 16
1429 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LEN 8
1430 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LO_OFST 16
1431 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_HI_OFST 20
1432 /* Enum values, see field(s): */
1433 /* 100M */
1434 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_OFST 24
1435 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LEN 8
1436 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LO_OFST 24
1437 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_HI_OFST 28
1438 /* Enum values, see field(s): */
1439 /* 100M */
1440
1441
1442 /***********************************/
1443 /* MC_CMD_GET_LINK
1444 * Read the unified MAC/PHY link state.
1445 */
1446 #define MC_CMD_GET_LINK 0x29
1447
1448 /* MC_CMD_GET_LINK_IN msgrequest */
1449 #define MC_CMD_GET_LINK_IN_LEN 0
1450
1451 /* MC_CMD_GET_LINK_OUT msgresponse */
1452 #define MC_CMD_GET_LINK_OUT_LEN 28
1453 #define MC_CMD_GET_LINK_OUT_CAP_OFST 0
1454 #define MC_CMD_GET_LINK_OUT_LP_CAP_OFST 4
1455 #define MC_CMD_GET_LINK_OUT_LINK_SPEED_OFST 8
1456 #define MC_CMD_GET_LINK_OUT_LOOPBACK_MODE_OFST 12
1457 /* Enum values, see field(s): */
1458 /* MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */
1459 #define MC_CMD_GET_LINK_OUT_FLAGS_OFST 16
1460 #define MC_CMD_GET_LINK_OUT_LINK_UP_LBN 0
1461 #define MC_CMD_GET_LINK_OUT_LINK_UP_WIDTH 1
1462 #define MC_CMD_GET_LINK_OUT_FULL_DUPLEX_LBN 1
1463 #define MC_CMD_GET_LINK_OUT_FULL_DUPLEX_WIDTH 1
1464 #define MC_CMD_GET_LINK_OUT_BPX_LINK_LBN 2
1465 #define MC_CMD_GET_LINK_OUT_BPX_LINK_WIDTH 1
1466 #define MC_CMD_GET_LINK_OUT_PHY_LINK_LBN 3
1467 #define MC_CMD_GET_LINK_OUT_PHY_LINK_WIDTH 1
1468 #define MC_CMD_GET_LINK_OUT_FCNTL_OFST 20
1469 #define MC_CMD_FCNTL_OFF 0x0 /* enum */
1470 #define MC_CMD_FCNTL_RESPOND 0x1 /* enum */
1471 #define MC_CMD_FCNTL_BIDIR 0x2 /* enum */
1472 #define MC_CMD_GET_LINK_OUT_MAC_FAULT_OFST 24
1473 #define MC_CMD_MAC_FAULT_XGMII_LOCAL_LBN 0
1474 #define MC_CMD_MAC_FAULT_XGMII_LOCAL_WIDTH 1
1475 #define MC_CMD_MAC_FAULT_XGMII_REMOTE_LBN 1
1476 #define MC_CMD_MAC_FAULT_XGMII_REMOTE_WIDTH 1
1477 #define MC_CMD_MAC_FAULT_SGMII_REMOTE_LBN 2
1478 #define MC_CMD_MAC_FAULT_SGMII_REMOTE_WIDTH 1
1479 #define MC_CMD_MAC_FAULT_PENDING_RECONFIG_LBN 3
1480 #define MC_CMD_MAC_FAULT_PENDING_RECONFIG_WIDTH 1
1481
1482
1483 /***********************************/
1484 /* MC_CMD_SET_LINK
1485 * Write the unified MAC/PHY link configuration.
1486 */
1487 #define MC_CMD_SET_LINK 0x2a
1488
1489 /* MC_CMD_SET_LINK_IN msgrequest */
1490 #define MC_CMD_SET_LINK_IN_LEN 16
1491 #define MC_CMD_SET_LINK_IN_CAP_OFST 0
1492 #define MC_CMD_SET_LINK_IN_FLAGS_OFST 4
1493 #define MC_CMD_SET_LINK_IN_LOWPOWER_LBN 0
1494 #define MC_CMD_SET_LINK_IN_LOWPOWER_WIDTH 1
1495 #define MC_CMD_SET_LINK_IN_POWEROFF_LBN 1
1496 #define MC_CMD_SET_LINK_IN_POWEROFF_WIDTH 1
1497 #define MC_CMD_SET_LINK_IN_TXDIS_LBN 2
1498 #define MC_CMD_SET_LINK_IN_TXDIS_WIDTH 1
1499 #define MC_CMD_SET_LINK_IN_LOOPBACK_MODE_OFST 8
1500 /* Enum values, see field(s): */
1501 /* MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */
1502 #define MC_CMD_SET_LINK_IN_LOOPBACK_SPEED_OFST 12
1503
1504 /* MC_CMD_SET_LINK_OUT msgresponse */
1505 #define MC_CMD_SET_LINK_OUT_LEN 0
1506
1507
1508 /***********************************/
1509 /* MC_CMD_SET_ID_LED
1510 * Set indentification LED state.
1511 */
1512 #define MC_CMD_SET_ID_LED 0x2b
1513
1514 /* MC_CMD_SET_ID_LED_IN msgrequest */
1515 #define MC_CMD_SET_ID_LED_IN_LEN 4
1516 #define MC_CMD_SET_ID_LED_IN_STATE_OFST 0
1517 #define MC_CMD_LED_OFF 0x0 /* enum */
1518 #define MC_CMD_LED_ON 0x1 /* enum */
1519 #define MC_CMD_LED_DEFAULT 0x2 /* enum */
1520
1521 /* MC_CMD_SET_ID_LED_OUT msgresponse */
1522 #define MC_CMD_SET_ID_LED_OUT_LEN 0
1523
1524
1525 /***********************************/
1526 /* MC_CMD_SET_MAC
1527 * Set MAC configuration.
1528 */
1529 #define MC_CMD_SET_MAC 0x2c
1530
1531 /* MC_CMD_SET_MAC_IN msgrequest */
1532 #define MC_CMD_SET_MAC_IN_LEN 24
1533 #define MC_CMD_SET_MAC_IN_MTU_OFST 0
1534 #define MC_CMD_SET_MAC_IN_DRAIN_OFST 4
1535 #define MC_CMD_SET_MAC_IN_ADDR_OFST 8
1536 #define MC_CMD_SET_MAC_IN_ADDR_LEN 8
1537 #define MC_CMD_SET_MAC_IN_ADDR_LO_OFST 8
1538 #define MC_CMD_SET_MAC_IN_ADDR_HI_OFST 12
1539 #define MC_CMD_SET_MAC_IN_REJECT_OFST 16
1540 #define MC_CMD_SET_MAC_IN_REJECT_UNCST_LBN 0
1541 #define MC_CMD_SET_MAC_IN_REJECT_UNCST_WIDTH 1
1542 #define MC_CMD_SET_MAC_IN_REJECT_BRDCST_LBN 1
1543 #define MC_CMD_SET_MAC_IN_REJECT_BRDCST_WIDTH 1
1544 #define MC_CMD_SET_MAC_IN_FCNTL_OFST 20
1545 /* MC_CMD_FCNTL_OFF 0x0 */
1546 /* MC_CMD_FCNTL_RESPOND 0x1 */
1547 /* MC_CMD_FCNTL_BIDIR 0x2 */
1548 #define MC_CMD_FCNTL_AUTO 0x3 /* enum */
1549
1550 /* MC_CMD_SET_MAC_OUT msgresponse */
1551 #define MC_CMD_SET_MAC_OUT_LEN 0
1552
1553
1554 /***********************************/
1555 /* MC_CMD_PHY_STATS
1556 * Get generic PHY statistics.
1557 */
1558 #define MC_CMD_PHY_STATS 0x2d
1559
1560 /* MC_CMD_PHY_STATS_IN msgrequest */
1561 #define MC_CMD_PHY_STATS_IN_LEN 8
1562 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_OFST 0
1563 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_LEN 8
1564 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_LO_OFST 0
1565 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_HI_OFST 4
1566
1567 /* MC_CMD_PHY_STATS_OUT_DMA msgresponse */
1568 #define MC_CMD_PHY_STATS_OUT_DMA_LEN 0
1569
1570 /* MC_CMD_PHY_STATS_OUT_NO_DMA msgresponse */
1571 #define MC_CMD_PHY_STATS_OUT_NO_DMA_LEN (((MC_CMD_PHY_NSTATS*32))>>3)
1572 #define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_OFST 0
1573 #define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_LEN 4
1574 #define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_NUM MC_CMD_PHY_NSTATS
1575 #define MC_CMD_OUI 0x0 /* enum */
1576 #define MC_CMD_PMA_PMD_LINK_UP 0x1 /* enum */
1577 #define MC_CMD_PMA_PMD_RX_FAULT 0x2 /* enum */
1578 #define MC_CMD_PMA_PMD_TX_FAULT 0x3 /* enum */
1579 #define MC_CMD_PMA_PMD_SIGNAL 0x4 /* enum */
1580 #define MC_CMD_PMA_PMD_SNR_A 0x5 /* enum */
1581 #define MC_CMD_PMA_PMD_SNR_B 0x6 /* enum */
1582 #define MC_CMD_PMA_PMD_SNR_C 0x7 /* enum */
1583 #define MC_CMD_PMA_PMD_SNR_D 0x8 /* enum */
1584 #define MC_CMD_PCS_LINK_UP 0x9 /* enum */
1585 #define MC_CMD_PCS_RX_FAULT 0xa /* enum */
1586 #define MC_CMD_PCS_TX_FAULT 0xb /* enum */
1587 #define MC_CMD_PCS_BER 0xc /* enum */
1588 #define MC_CMD_PCS_BLOCK_ERRORS 0xd /* enum */
1589 #define MC_CMD_PHYXS_LINK_UP 0xe /* enum */
1590 #define MC_CMD_PHYXS_RX_FAULT 0xf /* enum */
1591 #define MC_CMD_PHYXS_TX_FAULT 0x10 /* enum */
1592 #define MC_CMD_PHYXS_ALIGN 0x11 /* enum */
1593 #define MC_CMD_PHYXS_SYNC 0x12 /* enum */
1594 #define MC_CMD_AN_LINK_UP 0x13 /* enum */
1595 #define MC_CMD_AN_COMPLETE 0x14 /* enum */
1596 #define MC_CMD_AN_10GBT_STATUS 0x15 /* enum */
1597 #define MC_CMD_CL22_LINK_UP 0x16 /* enum */
1598 #define MC_CMD_PHY_NSTATS 0x17 /* enum */
1599
1600
1601 /***********************************/
1602 /* MC_CMD_MAC_STATS
1603 * Get generic MAC statistics.
1604 */
1605 #define MC_CMD_MAC_STATS 0x2e
1606
1607 /* MC_CMD_MAC_STATS_IN msgrequest */
1608 #define MC_CMD_MAC_STATS_IN_LEN 16
1609 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_OFST 0
1610 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_LEN 8
1611 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_LO_OFST 0
1612 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_HI_OFST 4
1613 #define MC_CMD_MAC_STATS_IN_CMD_OFST 8
1614 #define MC_CMD_MAC_STATS_IN_DMA_LBN 0
1615 #define MC_CMD_MAC_STATS_IN_DMA_WIDTH 1
1616 #define MC_CMD_MAC_STATS_IN_CLEAR_LBN 1
1617 #define MC_CMD_MAC_STATS_IN_CLEAR_WIDTH 1
1618 #define MC_CMD_MAC_STATS_IN_PERIODIC_CHANGE_LBN 2
1619 #define MC_CMD_MAC_STATS_IN_PERIODIC_CHANGE_WIDTH 1
1620 #define MC_CMD_MAC_STATS_IN_PERIODIC_ENABLE_LBN 3
1621 #define MC_CMD_MAC_STATS_IN_PERIODIC_ENABLE_WIDTH 1
1622 #define MC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_LBN 4
1623 #define MC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_WIDTH 1
1624 #define MC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_LBN 5
1625 #define MC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_WIDTH 1
1626 #define MC_CMD_MAC_STATS_IN_PERIOD_MS_LBN 16
1627 #define MC_CMD_MAC_STATS_IN_PERIOD_MS_WIDTH 16
1628 #define MC_CMD_MAC_STATS_IN_DMA_LEN_OFST 12
1629
1630 /* MC_CMD_MAC_STATS_OUT_DMA msgresponse */
1631 #define MC_CMD_MAC_STATS_OUT_DMA_LEN 0
1632
1633 /* MC_CMD_MAC_STATS_OUT_NO_DMA msgresponse */
1634 #define MC_CMD_MAC_STATS_OUT_NO_DMA_LEN (((MC_CMD_MAC_NSTATS*64))>>3)
1635 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_OFST 0
1636 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LEN 8
1637 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LO_OFST 0
1638 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_HI_OFST 4
1639 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS
1640 #define MC_CMD_MAC_GENERATION_START 0x0 /* enum */
1641 #define MC_CMD_MAC_TX_PKTS 0x1 /* enum */
1642 #define MC_CMD_MAC_TX_PAUSE_PKTS 0x2 /* enum */
1643 #define MC_CMD_MAC_TX_CONTROL_PKTS 0x3 /* enum */
1644 #define MC_CMD_MAC_TX_UNICAST_PKTS 0x4 /* enum */
1645 #define MC_CMD_MAC_TX_MULTICAST_PKTS 0x5 /* enum */
1646 #define MC_CMD_MAC_TX_BROADCAST_PKTS 0x6 /* enum */
1647 #define MC_CMD_MAC_TX_BYTES 0x7 /* enum */
1648 #define MC_CMD_MAC_TX_BAD_BYTES 0x8 /* enum */
1649 #define MC_CMD_MAC_TX_LT64_PKTS 0x9 /* enum */
1650 #define MC_CMD_MAC_TX_64_PKTS 0xa /* enum */
1651 #define MC_CMD_MAC_TX_65_TO_127_PKTS 0xb /* enum */
1652 #define MC_CMD_MAC_TX_128_TO_255_PKTS 0xc /* enum */
1653 #define MC_CMD_MAC_TX_256_TO_511_PKTS 0xd /* enum */
1654 #define MC_CMD_MAC_TX_512_TO_1023_PKTS 0xe /* enum */
1655 #define MC_CMD_MAC_TX_1024_TO_15XX_PKTS 0xf /* enum */
1656 #define MC_CMD_MAC_TX_15XX_TO_JUMBO_PKTS 0x10 /* enum */
1657 #define MC_CMD_MAC_TX_GTJUMBO_PKTS 0x11 /* enum */
1658 #define MC_CMD_MAC_TX_BAD_FCS_PKTS 0x12 /* enum */
1659 #define MC_CMD_MAC_TX_SINGLE_COLLISION_PKTS 0x13 /* enum */
1660 #define MC_CMD_MAC_TX_MULTIPLE_COLLISION_PKTS 0x14 /* enum */
1661 #define MC_CMD_MAC_TX_EXCESSIVE_COLLISION_PKTS 0x15 /* enum */
1662 #define MC_CMD_MAC_TX_LATE_COLLISION_PKTS 0x16 /* enum */
1663 #define MC_CMD_MAC_TX_DEFERRED_PKTS 0x17 /* enum */
1664 #define MC_CMD_MAC_TX_EXCESSIVE_DEFERRED_PKTS 0x18 /* enum */
1665 #define MC_CMD_MAC_TX_NON_TCPUDP_PKTS 0x19 /* enum */
1666 #define MC_CMD_MAC_TX_MAC_SRC_ERR_PKTS 0x1a /* enum */
1667 #define MC_CMD_MAC_TX_IP_SRC_ERR_PKTS 0x1b /* enum */
1668 #define MC_CMD_MAC_RX_PKTS 0x1c /* enum */
1669 #define MC_CMD_MAC_RX_PAUSE_PKTS 0x1d /* enum */
1670 #define MC_CMD_MAC_RX_GOOD_PKTS 0x1e /* enum */
1671 #define MC_CMD_MAC_RX_CONTROL_PKTS 0x1f /* enum */
1672 #define MC_CMD_MAC_RX_UNICAST_PKTS 0x20 /* enum */
1673 #define MC_CMD_MAC_RX_MULTICAST_PKTS 0x21 /* enum */
1674 #define MC_CMD_MAC_RX_BROADCAST_PKTS 0x22 /* enum */
1675 #define MC_CMD_MAC_RX_BYTES 0x23 /* enum */
1676 #define MC_CMD_MAC_RX_BAD_BYTES 0x24 /* enum */
1677 #define MC_CMD_MAC_RX_64_PKTS 0x25 /* enum */
1678 #define MC_CMD_MAC_RX_65_TO_127_PKTS 0x26 /* enum */
1679 #define MC_CMD_MAC_RX_128_TO_255_PKTS 0x27 /* enum */
1680 #define MC_CMD_MAC_RX_256_TO_511_PKTS 0x28 /* enum */
1681 #define MC_CMD_MAC_RX_512_TO_1023_PKTS 0x29 /* enum */
1682 #define MC_CMD_MAC_RX_1024_TO_15XX_PKTS 0x2a /* enum */
1683 #define MC_CMD_MAC_RX_15XX_TO_JUMBO_PKTS 0x2b /* enum */
1684 #define MC_CMD_MAC_RX_GTJUMBO_PKTS 0x2c /* enum */
1685 #define MC_CMD_MAC_RX_UNDERSIZE_PKTS 0x2d /* enum */
1686 #define MC_CMD_MAC_RX_BAD_FCS_PKTS 0x2e /* enum */
1687 #define MC_CMD_MAC_RX_OVERFLOW_PKTS 0x2f /* enum */
1688 #define MC_CMD_MAC_RX_FALSE_CARRIER_PKTS 0x30 /* enum */
1689 #define MC_CMD_MAC_RX_SYMBOL_ERROR_PKTS 0x31 /* enum */
1690 #define MC_CMD_MAC_RX_ALIGN_ERROR_PKTS 0x32 /* enum */
1691 #define MC_CMD_MAC_RX_LENGTH_ERROR_PKTS 0x33 /* enum */
1692 #define MC_CMD_MAC_RX_INTERNAL_ERROR_PKTS 0x34 /* enum */
1693 #define MC_CMD_MAC_RX_JABBER_PKTS 0x35 /* enum */
1694 #define MC_CMD_MAC_RX_NODESC_DROPS 0x36 /* enum */
1695 #define MC_CMD_MAC_RX_LANES01_CHAR_ERR 0x37 /* enum */
1696 #define MC_CMD_MAC_RX_LANES23_CHAR_ERR 0x38 /* enum */
1697 #define MC_CMD_MAC_RX_LANES01_DISP_ERR 0x39 /* enum */
1698 #define MC_CMD_MAC_RX_LANES23_DISP_ERR 0x3a /* enum */
1699 #define MC_CMD_MAC_RX_MATCH_FAULT 0x3b /* enum */
1700 #define MC_CMD_GMAC_DMABUF_START 0x40 /* enum */
1701 #define MC_CMD_GMAC_DMABUF_END 0x5f /* enum */
1702 #define MC_CMD_MAC_GENERATION_END 0x60 /* enum */
1703 #define MC_CMD_MAC_NSTATS 0x61 /* enum */
1704
1705
1706 /***********************************/
1707 /* MC_CMD_SRIOV
1708 * to be documented
1709 */
1710 #define MC_CMD_SRIOV 0x30
1711
1712 /* MC_CMD_SRIOV_IN msgrequest */
1713 #define MC_CMD_SRIOV_IN_LEN 12
1714 #define MC_CMD_SRIOV_IN_ENABLE_OFST 0
1715 #define MC_CMD_SRIOV_IN_VI_BASE_OFST 4
1716 #define MC_CMD_SRIOV_IN_VF_COUNT_OFST 8
1717
1718 /* MC_CMD_SRIOV_OUT msgresponse */
1719 #define MC_CMD_SRIOV_OUT_LEN 8
1720 #define MC_CMD_SRIOV_OUT_VI_SCALE_OFST 0
1721 #define MC_CMD_SRIOV_OUT_VF_TOTAL_OFST 4
1722
1723 /* MC_CMD_MEMCPY_RECORD_TYPEDEF structuredef */
1724 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LEN 32
1725 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_OFST 0
1726 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_LBN 0
1727 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_WIDTH 32
1728 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_OFST 4
1729 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_LBN 32
1730 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_WIDTH 32
1731 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_OFST 8
1732 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LEN 8
1733 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LO_OFST 8
1734 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_HI_OFST 12
1735 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LBN 64
1736 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_WIDTH 64
1737 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_OFST 16
1738 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_RID_INLINE 0x100 /* enum */
1739 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_LBN 128
1740 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_WIDTH 32
1741 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_OFST 20
1742 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LEN 8
1743 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LO_OFST 20
1744 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_HI_OFST 24
1745 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LBN 160
1746 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_WIDTH 64
1747 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_OFST 28
1748 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_LBN 224
1749 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_WIDTH 32
1750
1751
1752 /***********************************/
1753 /* MC_CMD_MEMCPY
1754 * Perform memory copy operation.
1755 */
1756 #define MC_CMD_MEMCPY 0x31
1757
1758 /* MC_CMD_MEMCPY_IN msgrequest */
1759 #define MC_CMD_MEMCPY_IN_LENMIN 32
1760 #define MC_CMD_MEMCPY_IN_LENMAX 224
1761 #define MC_CMD_MEMCPY_IN_LEN(num) (0+32*(num))
1762 #define MC_CMD_MEMCPY_IN_RECORD_OFST 0
1763 #define MC_CMD_MEMCPY_IN_RECORD_LEN 32
1764 #define MC_CMD_MEMCPY_IN_RECORD_MINNUM 1
1765 #define MC_CMD_MEMCPY_IN_RECORD_MAXNUM 7
1766
1767 /* MC_CMD_MEMCPY_OUT msgresponse */
1768 #define MC_CMD_MEMCPY_OUT_LEN 0
1769
1770
1771 /***********************************/
1772 /* MC_CMD_WOL_FILTER_SET
1773 * Set a WoL filter.
1774 */
1775 #define MC_CMD_WOL_FILTER_SET 0x32
1776
1777 /* MC_CMD_WOL_FILTER_SET_IN msgrequest */
1778 #define MC_CMD_WOL_FILTER_SET_IN_LEN 192
1779 #define MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0
1780 #define MC_CMD_FILTER_MODE_SIMPLE 0x0 /* enum */
1781 #define MC_CMD_FILTER_MODE_STRUCTURED 0xffffffff /* enum */
1782 #define MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4
1783 #define MC_CMD_WOL_TYPE_MAGIC 0x0 /* enum */
1784 #define MC_CMD_WOL_TYPE_WIN_MAGIC 0x2 /* enum */
1785 #define MC_CMD_WOL_TYPE_IPV4_SYN 0x3 /* enum */
1786 #define MC_CMD_WOL_TYPE_IPV6_SYN 0x4 /* enum */
1787 #define MC_CMD_WOL_TYPE_BITMAP 0x5 /* enum */
1788 #define MC_CMD_WOL_TYPE_LINK 0x6 /* enum */
1789 #define MC_CMD_WOL_TYPE_MAX 0x7 /* enum */
1790 #define MC_CMD_WOL_FILTER_SET_IN_DATA_OFST 8
1791 #define MC_CMD_WOL_FILTER_SET_IN_DATA_LEN 4
1792 #define MC_CMD_WOL_FILTER_SET_IN_DATA_NUM 46
1793
1794 /* MC_CMD_WOL_FILTER_SET_IN_MAGIC msgrequest */
1795 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_LEN 16
1796 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */
1797 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */
1798 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_OFST 8
1799 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LEN 8
1800 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LO_OFST 8
1801 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_HI_OFST 12
1802
1803 /* MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN msgrequest */
1804 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_LEN 20
1805 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */
1806 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */
1807 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_IP_OFST 8
1808 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_IP_OFST 12
1809 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_PORT_OFST 16
1810 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_PORT_LEN 2
1811 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_PORT_OFST 18
1812 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_PORT_LEN 2
1813
1814 /* MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN msgrequest */
1815 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_LEN 44
1816 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */
1817 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */
1818 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_IP_OFST 8
1819 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_IP_LEN 16
1820 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_IP_OFST 24
1821 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_IP_LEN 16
1822 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_PORT_OFST 40
1823 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_PORT_LEN 2
1824 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_PORT_OFST 42
1825 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_PORT_LEN 2
1826
1827 /* MC_CMD_WOL_FILTER_SET_IN_BITMAP msgrequest */
1828 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN 187
1829 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */
1830 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */
1831 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_MASK_OFST 8
1832 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_MASK_LEN 48
1833 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_BITMAP_OFST 56
1834 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_BITMAP_LEN 128
1835 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN_OFST 184
1836 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN_LEN 1
1837 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER3_OFST 185
1838 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER3_LEN 1
1839 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER4_OFST 186
1840 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER4_LEN 1
1841
1842 /* MC_CMD_WOL_FILTER_SET_IN_LINK msgrequest */
1843 #define MC_CMD_WOL_FILTER_SET_IN_LINK_LEN 12
1844 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */
1845 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */
1846 #define MC_CMD_WOL_FILTER_SET_IN_LINK_MASK_OFST 8
1847 #define MC_CMD_WOL_FILTER_SET_IN_LINK_UP_LBN 0
1848 #define MC_CMD_WOL_FILTER_SET_IN_LINK_UP_WIDTH 1
1849 #define MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_LBN 1
1850 #define MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_WIDTH 1
1851
1852 /* MC_CMD_WOL_FILTER_SET_OUT msgresponse */
1853 #define MC_CMD_WOL_FILTER_SET_OUT_LEN 4
1854 #define MC_CMD_WOL_FILTER_SET_OUT_FILTER_ID_OFST 0
1855
1856
1857 /***********************************/
1858 /* MC_CMD_WOL_FILTER_REMOVE
1859 * Remove a WoL filter.
1860 */
1861 #define MC_CMD_WOL_FILTER_REMOVE 0x33
1862
1863 /* MC_CMD_WOL_FILTER_REMOVE_IN msgrequest */
1864 #define MC_CMD_WOL_FILTER_REMOVE_IN_LEN 4
1865 #define MC_CMD_WOL_FILTER_REMOVE_IN_FILTER_ID_OFST 0
1866
1867 /* MC_CMD_WOL_FILTER_REMOVE_OUT msgresponse */
1868 #define MC_CMD_WOL_FILTER_REMOVE_OUT_LEN 0
1869
1870
1871 /***********************************/
1872 /* MC_CMD_WOL_FILTER_RESET
1873 * Reset (i.e. remove all) WoL filters.
1874 */
1875 #define MC_CMD_WOL_FILTER_RESET 0x34
1876
1877 /* MC_CMD_WOL_FILTER_RESET_IN msgrequest */
1878 #define MC_CMD_WOL_FILTER_RESET_IN_LEN 4
1879 #define MC_CMD_WOL_FILTER_RESET_IN_MASK_OFST 0
1880 #define MC_CMD_WOL_FILTER_RESET_IN_WAKE_FILTERS 0x1 /* enum */
1881 #define MC_CMD_WOL_FILTER_RESET_IN_LIGHTSOUT_OFFLOADS 0x2 /* enum */
1882
1883 /* MC_CMD_WOL_FILTER_RESET_OUT msgresponse */
1884 #define MC_CMD_WOL_FILTER_RESET_OUT_LEN 0
1885
1886
1887 /***********************************/
1888 /* MC_CMD_SET_MCAST_HASH
1889 * Set the MCASH hash value.
1890 */
1891 #define MC_CMD_SET_MCAST_HASH 0x35
1892
1893 /* MC_CMD_SET_MCAST_HASH_IN msgrequest */
1894 #define MC_CMD_SET_MCAST_HASH_IN_LEN 32
1895 #define MC_CMD_SET_MCAST_HASH_IN_HASH0_OFST 0
1896 #define MC_CMD_SET_MCAST_HASH_IN_HASH0_LEN 16
1897 #define MC_CMD_SET_MCAST_HASH_IN_HASH1_OFST 16
1898 #define MC_CMD_SET_MCAST_HASH_IN_HASH1_LEN 16
1899
1900 /* MC_CMD_SET_MCAST_HASH_OUT msgresponse */
1901 #define MC_CMD_SET_MCAST_HASH_OUT_LEN 0
1902
1903
1904 /***********************************/
1905 /* MC_CMD_NVRAM_TYPES
1906 * Get virtual NVRAM partitions information.
1907 */
1908 #define MC_CMD_NVRAM_TYPES 0x36
1909
1910 /* MC_CMD_NVRAM_TYPES_IN msgrequest */
1911 #define MC_CMD_NVRAM_TYPES_IN_LEN 0
1912
1913 /* MC_CMD_NVRAM_TYPES_OUT msgresponse */
1914 #define MC_CMD_NVRAM_TYPES_OUT_LEN 4
1915 #define MC_CMD_NVRAM_TYPES_OUT_TYPES_OFST 0
1916 #define MC_CMD_NVRAM_TYPE_DISABLED_CALLISTO 0x0 /* enum */
1917 #define MC_CMD_NVRAM_TYPE_MC_FW 0x1 /* enum */
1918 #define MC_CMD_NVRAM_TYPE_MC_FW_BACKUP 0x2 /* enum */
1919 #define MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT0 0x3 /* enum */
1920 #define MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT1 0x4 /* enum */
1921 #define MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT0 0x5 /* enum */
1922 #define MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT1 0x6 /* enum */
1923 #define MC_CMD_NVRAM_TYPE_EXP_ROM 0x7 /* enum */
1924 #define MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT0 0x8 /* enum */
1925 #define MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT1 0x9 /* enum */
1926 #define MC_CMD_NVRAM_TYPE_PHY_PORT0 0xa /* enum */
1927 #define MC_CMD_NVRAM_TYPE_PHY_PORT1 0xb /* enum */
1928 #define MC_CMD_NVRAM_TYPE_LOG 0xc /* enum */
1929 #define MC_CMD_NVRAM_TYPE_FPGA 0xd /* enum */
1930
1931
1932 /***********************************/
1933 /* MC_CMD_NVRAM_INFO
1934 * Read info about a virtual NVRAM partition.
1935 */
1936 #define MC_CMD_NVRAM_INFO 0x37
1937
1938 /* MC_CMD_NVRAM_INFO_IN msgrequest */
1939 #define MC_CMD_NVRAM_INFO_IN_LEN 4
1940 #define MC_CMD_NVRAM_INFO_IN_TYPE_OFST 0
1941 /* Enum values, see field(s): */
1942 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
1943
1944 /* MC_CMD_NVRAM_INFO_OUT msgresponse */
1945 #define MC_CMD_NVRAM_INFO_OUT_LEN 24
1946 #define MC_CMD_NVRAM_INFO_OUT_TYPE_OFST 0
1947 /* Enum values, see field(s): */
1948 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
1949 #define MC_CMD_NVRAM_INFO_OUT_SIZE_OFST 4
1950 #define MC_CMD_NVRAM_INFO_OUT_ERASESIZE_OFST 8
1951 #define MC_CMD_NVRAM_INFO_OUT_FLAGS_OFST 12
1952 #define MC_CMD_NVRAM_INFO_OUT_PROTECTED_LBN 0
1953 #define MC_CMD_NVRAM_INFO_OUT_PROTECTED_WIDTH 1
1954 #define MC_CMD_NVRAM_INFO_OUT_PHYSDEV_OFST 16
1955 #define MC_CMD_NVRAM_INFO_OUT_PHYSADDR_OFST 20
1956
1957
1958 /***********************************/
1959 /* MC_CMD_NVRAM_UPDATE_START
1960 * Start a group of update operations on a virtual NVRAM partition.
1961 */
1962 #define MC_CMD_NVRAM_UPDATE_START 0x38
1963
1964 /* MC_CMD_NVRAM_UPDATE_START_IN msgrequest */
1965 #define MC_CMD_NVRAM_UPDATE_START_IN_LEN 4
1966 #define MC_CMD_NVRAM_UPDATE_START_IN_TYPE_OFST 0
1967 /* Enum values, see field(s): */
1968 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
1969
1970 /* MC_CMD_NVRAM_UPDATE_START_OUT msgresponse */
1971 #define MC_CMD_NVRAM_UPDATE_START_OUT_LEN 0
1972
1973
1974 /***********************************/
1975 /* MC_CMD_NVRAM_READ
1976 * Read data from a virtual NVRAM partition.
1977 */
1978 #define MC_CMD_NVRAM_READ 0x39
1979
1980 /* MC_CMD_NVRAM_READ_IN msgrequest */
1981 #define MC_CMD_NVRAM_READ_IN_LEN 12
1982 #define MC_CMD_NVRAM_READ_IN_TYPE_OFST 0
1983 /* Enum values, see field(s): */
1984 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
1985 #define MC_CMD_NVRAM_READ_IN_OFFSET_OFST 4
1986 #define MC_CMD_NVRAM_READ_IN_LENGTH_OFST 8
1987
1988 /* MC_CMD_NVRAM_READ_OUT msgresponse */
1989 #define MC_CMD_NVRAM_READ_OUT_LENMIN 1
1990 #define MC_CMD_NVRAM_READ_OUT_LENMAX 252
1991 #define MC_CMD_NVRAM_READ_OUT_LEN(num) (0+1*(num))
1992 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_OFST 0
1993 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_LEN 1
1994 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_MINNUM 1
1995 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_MAXNUM 252
1996
1997
1998 /***********************************/
1999 /* MC_CMD_NVRAM_WRITE
2000 * Write data to a virtual NVRAM partition.
2001 */
2002 #define MC_CMD_NVRAM_WRITE 0x3a
2003
2004 /* MC_CMD_NVRAM_WRITE_IN msgrequest */
2005 #define MC_CMD_NVRAM_WRITE_IN_LENMIN 13
2006 #define MC_CMD_NVRAM_WRITE_IN_LENMAX 252
2007 #define MC_CMD_NVRAM_WRITE_IN_LEN(num) (12+1*(num))
2008 #define MC_CMD_NVRAM_WRITE_IN_TYPE_OFST 0
2009 /* Enum values, see field(s): */
2010 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
2011 #define MC_CMD_NVRAM_WRITE_IN_OFFSET_OFST 4
2012 #define MC_CMD_NVRAM_WRITE_IN_LENGTH_OFST 8
2013 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_OFST 12
2014 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_LEN 1
2015 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_MINNUM 1
2016 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_MAXNUM 240
2017
2018 /* MC_CMD_NVRAM_WRITE_OUT msgresponse */
2019 #define MC_CMD_NVRAM_WRITE_OUT_LEN 0
2020
2021
2022 /***********************************/
2023 /* MC_CMD_NVRAM_ERASE
2024 * Erase sector(s) from a virtual NVRAM partition.
2025 */
2026 #define MC_CMD_NVRAM_ERASE 0x3b
2027
2028 /* MC_CMD_NVRAM_ERASE_IN msgrequest */
2029 #define MC_CMD_NVRAM_ERASE_IN_LEN 12
2030 #define MC_CMD_NVRAM_ERASE_IN_TYPE_OFST 0
2031 /* Enum values, see field(s): */
2032 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
2033 #define MC_CMD_NVRAM_ERASE_IN_OFFSET_OFST 4
2034 #define MC_CMD_NVRAM_ERASE_IN_LENGTH_OFST 8
2035
2036 /* MC_CMD_NVRAM_ERASE_OUT msgresponse */
2037 #define MC_CMD_NVRAM_ERASE_OUT_LEN 0
2038
2039
2040 /***********************************/
2041 /* MC_CMD_NVRAM_UPDATE_FINISH
2042 * Finish a group of update operations on a virtual NVRAM partition.
2043 */
2044 #define MC_CMD_NVRAM_UPDATE_FINISH 0x3c
2045
2046 /* MC_CMD_NVRAM_UPDATE_FINISH_IN msgrequest */
2047 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_LEN 8
2048 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_TYPE_OFST 0
2049 /* Enum values, see field(s): */
2050 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
2051 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_REBOOT_OFST 4
2052
2053 /* MC_CMD_NVRAM_UPDATE_FINISH_OUT msgresponse */
2054 #define MC_CMD_NVRAM_UPDATE_FINISH_OUT_LEN 0
2055
2056
2057 /***********************************/
2058 /* MC_CMD_REBOOT
2059 * Reboot the MC.
2060 */
2061 #define MC_CMD_REBOOT 0x3d
2062
2063 /* MC_CMD_REBOOT_IN msgrequest */
2064 #define MC_CMD_REBOOT_IN_LEN 4
2065 #define MC_CMD_REBOOT_IN_FLAGS_OFST 0
2066 #define MC_CMD_REBOOT_FLAGS_AFTER_ASSERTION 0x1 /* enum */
2067
2068 /* MC_CMD_REBOOT_OUT msgresponse */
2069 #define MC_CMD_REBOOT_OUT_LEN 0
2070
2071
2072 /***********************************/
2073 /* MC_CMD_SCHEDINFO
2074 * Request scheduler info.
2075 */
2076 #define MC_CMD_SCHEDINFO 0x3e
2077
2078 /* MC_CMD_SCHEDINFO_IN msgrequest */
2079 #define MC_CMD_SCHEDINFO_IN_LEN 0
2080
2081 /* MC_CMD_SCHEDINFO_OUT msgresponse */
2082 #define MC_CMD_SCHEDINFO_OUT_LENMIN 4
2083 #define MC_CMD_SCHEDINFO_OUT_LENMAX 252
2084 #define MC_CMD_SCHEDINFO_OUT_LEN(num) (0+4*(num))
2085 #define MC_CMD_SCHEDINFO_OUT_DATA_OFST 0
2086 #define MC_CMD_SCHEDINFO_OUT_DATA_LEN 4
2087 #define MC_CMD_SCHEDINFO_OUT_DATA_MINNUM 1
2088 #define MC_CMD_SCHEDINFO_OUT_DATA_MAXNUM 63
2089
2090
2091 /***********************************/
2092 /* MC_CMD_REBOOT_MODE
2093 */
2094 #define MC_CMD_REBOOT_MODE 0x3f
2095
2096 /* MC_CMD_REBOOT_MODE_IN msgrequest */
2097 #define MC_CMD_REBOOT_MODE_IN_LEN 4
2098 #define MC_CMD_REBOOT_MODE_IN_VALUE_OFST 0
2099 #define MC_CMD_REBOOT_MODE_NORMAL 0x0 /* enum */
2100 #define MC_CMD_REBOOT_MODE_SNAPPER 0x3 /* enum */
2101
2102 /* MC_CMD_REBOOT_MODE_OUT msgresponse */
2103 #define MC_CMD_REBOOT_MODE_OUT_LEN 4
2104 #define MC_CMD_REBOOT_MODE_OUT_VALUE_OFST 0
2105
2106
2107 /***********************************/
2108 /* MC_CMD_SENSOR_INFO
2109 * Returns information about every available sensor.
2110 */
2111 #define MC_CMD_SENSOR_INFO 0x41
2112
2113 /* MC_CMD_SENSOR_INFO_IN msgrequest */
2114 #define MC_CMD_SENSOR_INFO_IN_LEN 0
2115
2116 /* MC_CMD_SENSOR_INFO_OUT msgresponse */
2117 #define MC_CMD_SENSOR_INFO_OUT_LENMIN 12
2118 #define MC_CMD_SENSOR_INFO_OUT_LENMAX 252
2119 #define MC_CMD_SENSOR_INFO_OUT_LEN(num) (4+8*(num))
2120 #define MC_CMD_SENSOR_INFO_OUT_MASK_OFST 0
2121 #define MC_CMD_SENSOR_CONTROLLER_TEMP 0x0 /* enum */
2122 #define MC_CMD_SENSOR_PHY_COMMON_TEMP 0x1 /* enum */
2123 #define MC_CMD_SENSOR_CONTROLLER_COOLING 0x2 /* enum */
2124 #define MC_CMD_SENSOR_PHY0_TEMP 0x3 /* enum */
2125 #define MC_CMD_SENSOR_PHY0_COOLING 0x4 /* enum */
2126 #define MC_CMD_SENSOR_PHY1_TEMP 0x5 /* enum */
2127 #define MC_CMD_SENSOR_PHY1_COOLING 0x6 /* enum */
2128 #define MC_CMD_SENSOR_IN_1V0 0x7 /* enum */
2129 #define MC_CMD_SENSOR_IN_1V2 0x8 /* enum */
2130 #define MC_CMD_SENSOR_IN_1V8 0x9 /* enum */
2131 #define MC_CMD_SENSOR_IN_2V5 0xa /* enum */
2132 #define MC_CMD_SENSOR_IN_3V3 0xb /* enum */
2133 #define MC_CMD_SENSOR_IN_12V0 0xc /* enum */
2134 #define MC_CMD_SENSOR_IN_1V2A 0xd /* enum */
2135 #define MC_CMD_SENSOR_IN_VREF 0xe /* enum */
2136 #define MC_CMD_SENSOR_ENTRY_OFST 4
2137 #define MC_CMD_SENSOR_ENTRY_LEN 8
2138 #define MC_CMD_SENSOR_ENTRY_LO_OFST 4
2139 #define MC_CMD_SENSOR_ENTRY_HI_OFST 8
2140 #define MC_CMD_SENSOR_ENTRY_MINNUM 1
2141 #define MC_CMD_SENSOR_ENTRY_MAXNUM 31
2142
2143 /* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF structuredef */
2144 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_LEN 8
2145 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_OFST 0
2146 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_LEN 2
2147 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_LBN 0
2148 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_WIDTH 16
2149 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_OFST 2
2150 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_LEN 2
2151 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_LBN 16
2152 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_WIDTH 16
2153 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_OFST 4
2154 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_LEN 2
2155 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_LBN 32
2156 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_WIDTH 16
2157 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_OFST 6
2158 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_LEN 2
2159 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_LBN 48
2160 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_WIDTH 16
2161
2162
2163 /***********************************/
2164 /* MC_CMD_READ_SENSORS
2165 * Returns the current reading from each sensor.
2166 */
2167 #define MC_CMD_READ_SENSORS 0x42
2168
2169 /* MC_CMD_READ_SENSORS_IN msgrequest */
2170 #define MC_CMD_READ_SENSORS_IN_LEN 8
2171 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_OFST 0
2172 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LEN 8
2173 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LO_OFST 0
2174 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_HI_OFST 4
2175
2176 /* MC_CMD_READ_SENSORS_OUT msgresponse */
2177 #define MC_CMD_READ_SENSORS_OUT_LEN 0
2178
2179 /* MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF structuredef */
2180 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_LEN 3
2181 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_OFST 0
2182 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_LEN 2
2183 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_LBN 0
2184 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_WIDTH 16
2185 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_OFST 2
2186 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_LEN 1
2187 #define MC_CMD_SENSOR_STATE_OK 0x0 /* enum */
2188 #define MC_CMD_SENSOR_STATE_WARNING 0x1 /* enum */
2189 #define MC_CMD_SENSOR_STATE_FATAL 0x2 /* enum */
2190 #define MC_CMD_SENSOR_STATE_BROKEN 0x3 /* enum */
2191 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_LBN 16
2192 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_WIDTH 8
2193
2194
2195 /***********************************/
2196 /* MC_CMD_GET_PHY_STATE
2197 * Report current state of PHY.
2198 */
2199 #define MC_CMD_GET_PHY_STATE 0x43
2200
2201 /* MC_CMD_GET_PHY_STATE_IN msgrequest */
2202 #define MC_CMD_GET_PHY_STATE_IN_LEN 0
2203
2204 /* MC_CMD_GET_PHY_STATE_OUT msgresponse */
2205 #define MC_CMD_GET_PHY_STATE_OUT_LEN 4
2206 #define MC_CMD_GET_PHY_STATE_OUT_STATE_OFST 0
2207 #define MC_CMD_PHY_STATE_OK 0x1 /* enum */
2208 #define MC_CMD_PHY_STATE_ZOMBIE 0x2 /* enum */
2209
2210
2211 /***********************************/
2212 /* MC_CMD_SETUP_8021QBB
2213 * 802.1Qbb control.
2214 */
2215 #define MC_CMD_SETUP_8021QBB 0x44
2216
2217 /* MC_CMD_SETUP_8021QBB_IN msgrequest */
2218 #define MC_CMD_SETUP_8021QBB_IN_LEN 32
2219 #define MC_CMD_SETUP_8021QBB_IN_TXQS_OFST 0
2220 #define MC_CMD_SETUP_8021QBB_IN_TXQS_LEN 32
2221
2222 /* MC_CMD_SETUP_8021QBB_OUT msgresponse */
2223 #define MC_CMD_SETUP_8021QBB_OUT_LEN 0
2224
2225
2226 /***********************************/
2227 /* MC_CMD_WOL_FILTER_GET
2228 * Retrieve ID of any WoL filters.
2229 */
2230 #define MC_CMD_WOL_FILTER_GET 0x45
2231
2232 /* MC_CMD_WOL_FILTER_GET_IN msgrequest */
2233 #define MC_CMD_WOL_FILTER_GET_IN_LEN 0
2234
2235 /* MC_CMD_WOL_FILTER_GET_OUT msgresponse */
2236 #define MC_CMD_WOL_FILTER_GET_OUT_LEN 4
2237 #define MC_CMD_WOL_FILTER_GET_OUT_FILTER_ID_OFST 0
2238
2239
2240 /***********************************/
2241 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD
2242 * Add a protocol offload to NIC for lights-out state.
2243 */
2244 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD 0x46
2245
2246 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN msgrequest */
2247 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LENMIN 8
2248 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LENMAX 252
2249 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LEN(num) (4+4*(num))
2250 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0
2251 #define MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_ARP 0x1 /* enum */
2252 #define MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_NS 0x2 /* enum */
2253 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_OFST 4
2254 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_LEN 4
2255 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_MINNUM 1
2256 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_MAXNUM 62
2257
2258 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP msgrequest */
2259 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_LEN 14
2260 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 */
2261 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_MAC_OFST 4
2262 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_MAC_LEN 6
2263 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_IP_OFST 10
2264
2265 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS msgrequest */
2266 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_LEN 42
2267 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 */
2268 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_MAC_OFST 4
2269 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_MAC_LEN 6
2270 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_SNIPV6_OFST 10
2271 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_SNIPV6_LEN 16
2272 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_IPV6_OFST 26
2273 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_IPV6_LEN 16
2274
2275 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT msgresponse */
2276 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_LEN 4
2277 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_FILTER_ID_OFST 0
2278
2279
2280 /***********************************/
2281 /* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD
2282 * Remove a protocol offload from NIC for lights-out state.
2283 */
2284 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD 0x47
2285
2286 /* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN msgrequest */
2287 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_LEN 8
2288 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0
2289 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_FILTER_ID_OFST 4
2290
2291 /* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_OUT msgresponse */
2292 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_OUT_LEN 0
2293
2294
2295 /***********************************/
2296 /* MC_CMD_MAC_RESET_RESTORE
2297 * Restore MAC after block reset.
2298 */
2299 #define MC_CMD_MAC_RESET_RESTORE 0x48
2300
2301 /* MC_CMD_MAC_RESET_RESTORE_IN msgrequest */
2302 #define MC_CMD_MAC_RESET_RESTORE_IN_LEN 0
2303
2304 /* MC_CMD_MAC_RESET_RESTORE_OUT msgresponse */
2305 #define MC_CMD_MAC_RESET_RESTORE_OUT_LEN 0
2306
2307
2308 /***********************************/
2309 /* MC_CMD_TESTASSERT
2310 */
2311 #define MC_CMD_TESTASSERT 0x49
2312
2313 /* MC_CMD_TESTASSERT_IN msgrequest */
2314 #define MC_CMD_TESTASSERT_IN_LEN 0
2315
2316 /* MC_CMD_TESTASSERT_OUT msgresponse */
2317 #define MC_CMD_TESTASSERT_OUT_LEN 0
2318
2319
2320 /***********************************/
2321 /* MC_CMD_WORKAROUND
2322 * Enable/Disable a given workaround.
2323 */
2324 #define MC_CMD_WORKAROUND 0x4a
2325
2326 /* MC_CMD_WORKAROUND_IN msgrequest */
2327 #define MC_CMD_WORKAROUND_IN_LEN 8
2328 #define MC_CMD_WORKAROUND_IN_TYPE_OFST 0
2329 #define MC_CMD_WORKAROUND_BUG17230 0x1 /* enum */
2330 #define MC_CMD_WORKAROUND_IN_ENABLED_OFST 4
2331
2332 /* MC_CMD_WORKAROUND_OUT msgresponse */
2333 #define MC_CMD_WORKAROUND_OUT_LEN 0
2334
2335
2336 /***********************************/
2337 /* MC_CMD_GET_PHY_MEDIA_INFO
2338 * Read media-specific data from PHY.
2339 */
2340 #define MC_CMD_GET_PHY_MEDIA_INFO 0x4b
2341
2342 /* MC_CMD_GET_PHY_MEDIA_INFO_IN msgrequest */
2343 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_LEN 4
2344 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_PAGE_OFST 0
2345
2346 /* MC_CMD_GET_PHY_MEDIA_INFO_OUT msgresponse */
2347 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LENMIN 5
2348 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LENMAX 252
2349 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LEN(num) (4+1*(num))
2350 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATALEN_OFST 0
2351 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_OFST 4
2352 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_LEN 1
2353 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_MINNUM 1
2354 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_MAXNUM 248
2355
2356
2357 /***********************************/
2358 /* MC_CMD_NVRAM_TEST
2359 * Test a particular NVRAM partition.
2360 */
2361 #define MC_CMD_NVRAM_TEST 0x4c
2362
2363 /* MC_CMD_NVRAM_TEST_IN msgrequest */
2364 #define MC_CMD_NVRAM_TEST_IN_LEN 4
2365 #define MC_CMD_NVRAM_TEST_IN_TYPE_OFST 0
2366 /* Enum values, see field(s): */
2367 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
2368
2369 /* MC_CMD_NVRAM_TEST_OUT msgresponse */
2370 #define MC_CMD_NVRAM_TEST_OUT_LEN 4
2371 #define MC_CMD_NVRAM_TEST_OUT_RESULT_OFST 0
2372 #define MC_CMD_NVRAM_TEST_PASS 0x0 /* enum */
2373 #define MC_CMD_NVRAM_TEST_FAIL 0x1 /* enum */
2374 #define MC_CMD_NVRAM_TEST_NOTSUPP 0x2 /* enum */
2375
2376
2377 /***********************************/
2378 /* MC_CMD_MRSFP_TWEAK
2379 * Read status and/or set parameters for the 'mrsfp' driver.
2380 */
2381 #define MC_CMD_MRSFP_TWEAK 0x4d
2382
2383 /* MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG msgrequest */
2384 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_LEN 16
2385 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_LEVEL_OFST 0
2386 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_DT_CFG_OFST 4
2387 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_BOOST_OFST 8
2388 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_DT_CFG_OFST 12
2389
2390 /* MC_CMD_MRSFP_TWEAK_IN_READ_ONLY msgrequest */
2391 #define MC_CMD_MRSFP_TWEAK_IN_READ_ONLY_LEN 0
2392
2393 /* MC_CMD_MRSFP_TWEAK_OUT msgresponse */
2394 #define MC_CMD_MRSFP_TWEAK_OUT_LEN 12
2395 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_INPUTS_OFST 0
2396 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_OUTPUTS_OFST 4
2397 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_OFST 8
2398 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_OUT 0x0 /* enum */
2399 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_IN 0x1 /* enum */
2400
2401
2402 /***********************************/
2403 /* MC_CMD_SENSOR_SET_LIMS
2404 * Adjusts the sensor limits.
2405 */
2406 #define MC_CMD_SENSOR_SET_LIMS 0x4e
2407
2408 /* MC_CMD_SENSOR_SET_LIMS_IN msgrequest */
2409 #define MC_CMD_SENSOR_SET_LIMS_IN_LEN 20
2410 #define MC_CMD_SENSOR_SET_LIMS_IN_SENSOR_OFST 0
2411 /* Enum values, see field(s): */
2412 /* MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */
2413 #define MC_CMD_SENSOR_SET_LIMS_IN_LOW0_OFST 4
2414 #define MC_CMD_SENSOR_SET_LIMS_IN_HI0_OFST 8
2415 #define MC_CMD_SENSOR_SET_LIMS_IN_LOW1_OFST 12
2416 #define MC_CMD_SENSOR_SET_LIMS_IN_HI1_OFST 16
2417
2418 /* MC_CMD_SENSOR_SET_LIMS_OUT msgresponse */
2419 #define MC_CMD_SENSOR_SET_LIMS_OUT_LEN 0
2420
2421
2422 /***********************************/
2423 /* MC_CMD_GET_RESOURCE_LIMITS
2424 */
2425 #define MC_CMD_GET_RESOURCE_LIMITS 0x4f
2426
2427 /* MC_CMD_GET_RESOURCE_LIMITS_IN msgrequest */
2428 #define MC_CMD_GET_RESOURCE_LIMITS_IN_LEN 0
2429
2430 /* MC_CMD_GET_RESOURCE_LIMITS_OUT msgresponse */
2431 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_LEN 16
2432 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_BUFTBL_OFST 0
2433 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_EVQ_OFST 4
2434 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_RXQ_OFST 8
2435 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_TXQ_OFST 12
2436
2437 /* MC_CMD_RESOURCE_SPECIFIER enum */
2438 #define MC_CMD_RESOURCE_INSTANCE_ANY 0xffffffff /* enum */
2439 #define MC_CMD_RESOURCE_INSTANCE_NONE 0xfffffffe /* enum */
2440
2441
2442 /***********************************/
2443 /* MC_CMD_INIT_EVQ
2444 */
2445 #define MC_CMD_INIT_EVQ 0x50
2446
2447 /* MC_CMD_INIT_EVQ_IN msgrequest */
2448 #define MC_CMD_INIT_EVQ_IN_LENMIN 36
2449 #define MC_CMD_INIT_EVQ_IN_LENMAX 540
2450 #define MC_CMD_INIT_EVQ_IN_LEN(num) (28+8*(num))
2451 #define MC_CMD_INIT_EVQ_IN_SIZE_OFST 0
2452 #define MC_CMD_INIT_EVQ_IN_INSTANCE_OFST 4
2453 #define MC_CMD_INIT_EVQ_IN_TMR_LOAD_OFST 8
2454 #define MC_CMD_INIT_EVQ_IN_TMR_RELOAD_OFST 12
2455 #define MC_CMD_INIT_EVQ_IN_FLAGS_OFST 16
2456 #define MC_CMD_INIT_EVQ_IN_FLAG_INTERRUPTING_LBN 0
2457 #define MC_CMD_INIT_EVQ_IN_FLAG_INTERRUPTING_WIDTH 1
2458 #define MC_CMD_INIT_EVQ_IN_FLAG_RPTR_DOS_LBN 1
2459 #define MC_CMD_INIT_EVQ_IN_FLAG_RPTR_DOS_WIDTH 1
2460 #define MC_CMD_INIT_EVQ_IN_TMR_MODE_OFST 20
2461 #define MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS 0x0 /* enum */
2462 #define MC_CMD_INIT_EVQ_IN_TMR_IMMED_START 0x1 /* enum */
2463 #define MC_CMD_INIT_EVQ_IN_TMR_TRIG_START 0x2 /* enum */
2464 #define MC_CMD_INIT_EVQ_IN_TMR_INT_HLDOFF 0x3 /* enum */
2465 #define MC_CMD_INIT_EVQ_IN_TARGET_EVQ_OFST 24
2466 #define MC_CMD_INIT_EVQ_IN_IRQ_NUM_OFST 24
2467 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_OFST 28
2468 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_LEN 8
2469 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_LO_OFST 28
2470 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_HI_OFST 32
2471 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_MINNUM 1
2472 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_MAXNUM 64
2473
2474 /* MC_CMD_INIT_EVQ_OUT msgresponse */
2475 #define MC_CMD_INIT_EVQ_OUT_LEN 4
2476 #define MC_CMD_INIT_EVQ_OUT_IRQ_OFST 0
2477
2478 /* QUEUE_CRC_MODE structuredef */
2479 #define QUEUE_CRC_MODE_LEN 1
2480 #define QUEUE_CRC_MODE_MODE_LBN 0
2481 #define QUEUE_CRC_MODE_MODE_WIDTH 4
2482 #define QUEUE_CRC_MODE_NONE 0x0 /* enum */
2483 #define QUEUE_CRC_MODE_FCOE 0x1 /* enum */
2484 #define QUEUE_CRC_MODE_ISCSI_HDR 0x2 /* enum */
2485 #define QUEUE_CRC_MODE_ISCSI 0x3 /* enum */
2486 #define QUEUE_CRC_MODE_FCOIPOE 0x4 /* enum */
2487 #define QUEUE_CRC_MODE_MPA 0x5 /* enum */
2488 #define QUEUE_CRC_MODE_SPARE_LBN 4
2489 #define QUEUE_CRC_MODE_SPARE_WIDTH 4
2490
2491
2492 /***********************************/
2493 /* MC_CMD_INIT_RXQ
2494 */
2495 #define MC_CMD_INIT_RXQ 0x51
2496
2497 /* MC_CMD_INIT_RXQ_IN msgrequest */
2498 #define MC_CMD_INIT_RXQ_IN_LENMIN 32
2499 #define MC_CMD_INIT_RXQ_IN_LENMAX 248
2500 #define MC_CMD_INIT_RXQ_IN_LEN(num) (24+8*(num))
2501 #define MC_CMD_INIT_RXQ_IN_SIZE_OFST 0
2502 #define MC_CMD_INIT_RXQ_IN_TARGET_EVQ_OFST 4
2503 #define MC_CMD_INIT_RXQ_IN_LABEL_OFST 8
2504 #define MC_CMD_INIT_RXQ_IN_INSTANCE_OFST 12
2505 #define MC_CMD_INIT_RXQ_IN_FLAGS_OFST 16
2506 #define MC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_LBN 0
2507 #define MC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_WIDTH 1
2508 #define MC_CMD_INIT_RXQ_IN_FLAG_HDR_SPLIT_LBN 1
2509 #define MC_CMD_INIT_RXQ_IN_FLAG_HDR_SPLIT_WIDTH 1
2510 #define MC_CMD_INIT_RXQ_IN_FLAG_PKT_EDIT_LBN 2
2511 #define MC_CMD_INIT_RXQ_IN_FLAG_PKT_EDIT_WIDTH 1
2512 #define MC_CMD_INIT_RXQ_IN_CRC_MODE_LBN 3
2513 #define MC_CMD_INIT_RXQ_IN_CRC_MODE_WIDTH 4
2514 #define MC_CMD_INIT_RXQ_IN_OWNER_ID_OFST 20
2515 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_OFST 24
2516 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_LEN 8
2517 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_LO_OFST 24
2518 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_HI_OFST 28
2519 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_MINNUM 1
2520 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_MAXNUM 28
2521
2522 /* MC_CMD_INIT_RXQ_OUT msgresponse */
2523 #define MC_CMD_INIT_RXQ_OUT_LEN 0
2524
2525
2526 /***********************************/
2527 /* MC_CMD_INIT_TXQ
2528 */
2529 #define MC_CMD_INIT_TXQ 0x52
2530
2531 /* MC_CMD_INIT_TXQ_IN msgrequest */
2532 #define MC_CMD_INIT_TXQ_IN_LENMIN 32
2533 #define MC_CMD_INIT_TXQ_IN_LENMAX 248
2534 #define MC_CMD_INIT_TXQ_IN_LEN(num) (24+8*(num))
2535 #define MC_CMD_INIT_TXQ_IN_SIZE_OFST 0
2536 #define MC_CMD_INIT_TXQ_IN_TARGET_EVQ_OFST 4
2537 #define MC_CMD_INIT_TXQ_IN_LABEL_OFST 8
2538 #define MC_CMD_INIT_TXQ_IN_INSTANCE_OFST 12
2539 #define MC_CMD_INIT_TXQ_IN_FLAGS_OFST 16
2540 #define MC_CMD_INIT_TXQ_IN_FLAG_BUFF_MODE_LBN 0
2541 #define MC_CMD_INIT_TXQ_IN_FLAG_BUFF_MODE_WIDTH 1
2542 #define MC_CMD_INIT_TXQ_IN_FLAG_IP_CSUM_DIS_LBN 1
2543 #define MC_CMD_INIT_TXQ_IN_FLAG_IP_CSUM_DIS_WIDTH 1
2544 #define MC_CMD_INIT_TXQ_IN_FLAG_TCP_CSUM_DIS_LBN 2
2545 #define MC_CMD_INIT_TXQ_IN_FLAG_TCP_CSUM_DIS_WIDTH 1
2546 #define MC_CMD_INIT_TXQ_IN_CRC_MODE_LBN 4
2547 #define MC_CMD_INIT_TXQ_IN_CRC_MODE_WIDTH 4
2548 #define MC_CMD_INIT_TXQ_IN_OWNER_ID_OFST 20
2549 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_OFST 24
2550 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_LEN 8
2551 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_LO_OFST 24
2552 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_HI_OFST 28
2553 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_MINNUM 1
2554 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_MAXNUM 28
2555
2556 /* MC_CMD_INIT_TXQ_OUT msgresponse */
2557 #define MC_CMD_INIT_TXQ_OUT_LEN 0
2558
2559
2560 /***********************************/
2561 /* MC_CMD_FINI_EVQ
2562 */
2563 #define MC_CMD_FINI_EVQ 0x55
2564
2565 /* MC_CMD_FINI_EVQ_IN msgrequest */
2566 #define MC_CMD_FINI_EVQ_IN_LEN 4
2567 #define MC_CMD_FINI_EVQ_IN_INSTANCE_OFST 0
2568
2569 /* MC_CMD_FINI_EVQ_OUT msgresponse */
2570 #define MC_CMD_FINI_EVQ_OUT_LEN 0
2571
2572
2573 /***********************************/
2574 /* MC_CMD_FINI_RXQ
2575 */
2576 #define MC_CMD_FINI_RXQ 0x56
2577
2578 /* MC_CMD_FINI_RXQ_IN msgrequest */
2579 #define MC_CMD_FINI_RXQ_IN_LEN 4
2580 #define MC_CMD_FINI_RXQ_IN_INSTANCE_OFST 0
2581
2582 /* MC_CMD_FINI_RXQ_OUT msgresponse */
2583 #define MC_CMD_FINI_RXQ_OUT_LEN 0
2584
2585
2586 /***********************************/
2587 /* MC_CMD_FINI_TXQ
2588 */
2589 #define MC_CMD_FINI_TXQ 0x57
2590
2591 /* MC_CMD_FINI_TXQ_IN msgrequest */
2592 #define MC_CMD_FINI_TXQ_IN_LEN 4
2593 #define MC_CMD_FINI_TXQ_IN_INSTANCE_OFST 0
2594
2595 /* MC_CMD_FINI_TXQ_OUT msgresponse */
2596 #define MC_CMD_FINI_TXQ_OUT_LEN 0
2597
2598
2599 /***********************************/
2600 /* MC_CMD_DRIVER_EVENT
2601 */
2602 #define MC_CMD_DRIVER_EVENT 0x5a
2603
2604 /* MC_CMD_DRIVER_EVENT_IN msgrequest */
2605 #define MC_CMD_DRIVER_EVENT_IN_LEN 12
2606 #define MC_CMD_DRIVER_EVENT_IN_EVQ_OFST 0
2607 #define MC_CMD_DRIVER_EVENT_IN_DATA_OFST 4
2608 #define MC_CMD_DRIVER_EVENT_IN_DATA_LEN 8
2609 #define MC_CMD_DRIVER_EVENT_IN_DATA_LO_OFST 4
2610 #define MC_CMD_DRIVER_EVENT_IN_DATA_HI_OFST 8
2611
2612
2613 /***********************************/
2614 /* MC_CMD_PROXY_CMD
2615 */
2616 #define MC_CMD_PROXY_CMD 0x5b
2617
2618 /* MC_CMD_PROXY_CMD_IN msgrequest */
2619 #define MC_CMD_PROXY_CMD_IN_LEN 4
2620 #define MC_CMD_PROXY_CMD_IN_TARGET_OFST 0
2621
2622
2623 /***********************************/
2624 /* MC_CMD_ALLOC_OWNER_IDS
2625 */
2626 #define MC_CMD_ALLOC_OWNER_IDS 0x54
2627
2628 /* MC_CMD_ALLOC_OWNER_IDS_IN msgrequest */
2629 #define MC_CMD_ALLOC_OWNER_IDS_IN_LEN 4
2630 #define MC_CMD_ALLOC_OWNER_IDS_IN_NIDS_OFST 0
2631
2632 /* MC_CMD_ALLOC_OWNER_IDS_OUT msgresponse */
2633 #define MC_CMD_ALLOC_OWNER_IDS_OUT_LEN 12
2634 #define MC_CMD_ALLOC_OWNER_IDS_OUT_HANDLE_OFST 0
2635 #define MC_CMD_ALLOC_OWNER_IDS_OUT_NIDS_OFST 4
2636 #define MC_CMD_ALLOC_OWNER_IDS_OUT_BASE_OFST 8
2637
2638
2639 /***********************************/
2640 /* MC_CMD_FREE_OWNER_IDS
2641 */
2642 #define MC_CMD_FREE_OWNER_IDS 0x59
2643
2644 /* MC_CMD_FREE_OWNER_IDS_IN msgrequest */
2645 #define MC_CMD_FREE_OWNER_IDS_IN_LEN 4
2646 #define MC_CMD_FREE_OWNER_IDS_IN_HANDLE_OFST 0
2647
2648 /* MC_CMD_FREE_OWNER_IDS_OUT msgresponse */
2649 #define MC_CMD_FREE_OWNER_IDS_OUT_LEN 0
2650
2651
2652 /***********************************/
2653 /* MC_CMD_ALLOC_BUFTBL_CHUNK
2654 */
2655 #define MC_CMD_ALLOC_BUFTBL_CHUNK 0x5c
2656
2657 /* MC_CMD_ALLOC_BUFTBL_CHUNK_IN msgrequest */
2658 #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_LEN 8
2659 #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_OWNER_OFST 0
2660 #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_PAGE_SIZE_OFST 4
2661
2662 /* MC_CMD_ALLOC_BUFTBL_CHUNK_OUT msgresponse */
2663 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_LEN 12
2664 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_HANDLE_OFST 0
2665 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_NUMENTRIES_OFST 4
2666 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_ID_OFST 8
2667
2668
2669 /***********************************/
2670 /* MC_CMD_PROGRAM_BUFTBL_ENTRIES
2671 */
2672 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES 0x5d
2673
2674 /* MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN msgrequest */
2675 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LENMIN 20
2676 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LENMAX 252
2677 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LEN(num) (12+8*(num))
2678 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_HANDLE_OFST 0
2679 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_FIRSTID_OFST 4
2680 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_NUMENTRIES_OFST 8
2681 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_OFST 12
2682 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LEN 8
2683 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LO_OFST 12
2684 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_HI_OFST 16
2685 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_MINNUM 1
2686 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_MAXNUM 30
2687
2688 /* MC_CMD_PROGRAM_BUFTBL_ENTRIES_OUT msgresponse */
2689 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_OUT_LEN 0
2690
2691
2692 /***********************************/
2693 /* MC_CMD_FREE_BUFTBL_CHUNK
2694 */
2695 #define MC_CMD_FREE_BUFTBL_CHUNK 0x5e
2696
2697 /* MC_CMD_FREE_BUFTBL_CHUNK_IN msgrequest */
2698 #define MC_CMD_FREE_BUFTBL_CHUNK_IN_LEN 4
2699 #define MC_CMD_FREE_BUFTBL_CHUNK_IN_HANDLE_OFST 0
2700
2701 /* MC_CMD_FREE_BUFTBL_CHUNK_OUT msgresponse */
2702 #define MC_CMD_FREE_BUFTBL_CHUNK_OUT_LEN 0
2703
2704
2705 /***********************************/
2706 /* MC_CMD_GET_PF_COUNT
2707 */
2708 #define MC_CMD_GET_PF_COUNT 0x60
2709
2710 /* MC_CMD_GET_PF_COUNT_IN msgrequest */
2711 #define MC_CMD_GET_PF_COUNT_IN_LEN 0
2712
2713 /* MC_CMD_GET_PF_COUNT_OUT msgresponse */
2714 #define MC_CMD_GET_PF_COUNT_OUT_LEN 1
2715 #define MC_CMD_GET_PF_COUNT_OUT_PF_COUNT_OFST 0
2716 #define MC_CMD_GET_PF_COUNT_OUT_PF_COUNT_LEN 1
2717
2718
2719 /***********************************/
2720 /* MC_CMD_FILTER_OP
2721 */
2722 #define MC_CMD_FILTER_OP 0x61
2723
2724 /* MC_CMD_FILTER_OP_IN msgrequest */
2725 #define MC_CMD_FILTER_OP_IN_LEN 100
2726 #define MC_CMD_FILTER_OP_IN_OP_OFST 0
2727 #define MC_CMD_FILTER_OP_IN_OP_INSERT 0x0 /* enum */
2728 #define MC_CMD_FILTER_OP_IN_OP_REMOVE 0x1 /* enum */
2729 #define MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE 0x2 /* enum */
2730 #define MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE 0x3 /* enum */
2731 #define MC_CMD_FILTER_OP_IN_HANDLE_OFST 4
2732 #define MC_CMD_FILTER_OP_IN_MATCH_FIELDS_OFST 8
2733 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_IP_LBN 0
2734 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_IP_WIDTH 1
2735 #define MC_CMD_FILTER_OP_IN_MATCH_DST_IP_LBN 1
2736 #define MC_CMD_FILTER_OP_IN_MATCH_DST_IP_WIDTH 1
2737 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_MAC_LBN 2
2738 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_MAC_WIDTH 1
2739 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_PORT_LBN 3
2740 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_PORT_WIDTH 1
2741 #define MC_CMD_FILTER_OP_IN_MATCH_DST_MAC_LBN 4
2742 #define MC_CMD_FILTER_OP_IN_MATCH_DST_MAC_WIDTH 1
2743 #define MC_CMD_FILTER_OP_IN_MATCH_DST_PORT_LBN 5
2744 #define MC_CMD_FILTER_OP_IN_MATCH_DST_PORT_WIDTH 1
2745 #define MC_CMD_FILTER_OP_IN_MATCH_ETHER_TYPE_LBN 6
2746 #define MC_CMD_FILTER_OP_IN_MATCH_ETHER_TYPE_WIDTH 1
2747 #define MC_CMD_FILTER_OP_IN_MATCH_INNER_VLAN_LBN 7
2748 #define MC_CMD_FILTER_OP_IN_MATCH_INNER_VLAN_WIDTH 1
2749 #define MC_CMD_FILTER_OP_IN_MATCH_OUTER_VLAN_LBN 8
2750 #define MC_CMD_FILTER_OP_IN_MATCH_OUTER_VLAN_WIDTH 1
2751 #define MC_CMD_FILTER_OP_IN_MATCH_IP_PROTO_LBN 9
2752 #define MC_CMD_FILTER_OP_IN_MATCH_IP_PROTO_WIDTH 1
2753 #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF0_LBN 10
2754 #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF0_WIDTH 1
2755 #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF1_LBN 11
2756 #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF1_WIDTH 1
2757 #define MC_CMD_FILTER_OP_IN_RX_DEST_OFST 12
2758 #define MC_CMD_FILTER_OP_IN_RX_DEST_DROP 0x0 /* enum */
2759 #define MC_CMD_FILTER_OP_IN_RX_DEST_HOST 0x1 /* enum */
2760 #define MC_CMD_FILTER_OP_IN_RX_DEST_MC 0x2 /* enum */
2761 #define MC_CMD_FILTER_OP_IN_RX_DEST_TX0 0x3 /* enum */
2762 #define MC_CMD_FILTER_OP_IN_RX_DEST_TX1 0x4 /* enum */
2763 #define MC_CMD_FILTER_OP_IN_RX_QUEUE_OFST 16
2764 #define MC_CMD_FILTER_OP_IN_RX_FLAGS_OFST 20
2765 #define MC_CMD_FILTER_OP_IN_RX_FLAG_RSS_LBN 0
2766 #define MC_CMD_FILTER_OP_IN_RX_FLAG_RSS_WIDTH 1
2767 #define MC_CMD_FILTER_OP_IN_RSS_CONTEXT_OFST 24
2768 #define MC_CMD_FILTER_OP_IN_TX_DOMAIN_OFST 28
2769 #define MC_CMD_FILTER_OP_IN_TX_DEST_OFST 32
2770 #define MC_CMD_FILTER_OP_IN_TX_DEST_MAC_LBN 0
2771 #define MC_CMD_FILTER_OP_IN_TX_DEST_MAC_WIDTH 1
2772 #define MC_CMD_FILTER_OP_IN_TX_DEST_PM_LBN 1
2773 #define MC_CMD_FILTER_OP_IN_TX_DEST_PM_WIDTH 1
2774 #define MC_CMD_FILTER_OP_IN_SRC_MAC_OFST 36
2775 #define MC_CMD_FILTER_OP_IN_SRC_MAC_LEN 6
2776 #define MC_CMD_FILTER_OP_IN_SRC_PORT_OFST 42
2777 #define MC_CMD_FILTER_OP_IN_SRC_PORT_LEN 2
2778 #define MC_CMD_FILTER_OP_IN_DST_MAC_OFST 44
2779 #define MC_CMD_FILTER_OP_IN_DST_MAC_LEN 6
2780 #define MC_CMD_FILTER_OP_IN_DST_PORT_OFST 50
2781 #define MC_CMD_FILTER_OP_IN_DST_PORT_LEN 2
2782 #define MC_CMD_FILTER_OP_IN_ETHER_TYPE_OFST 52
2783 #define MC_CMD_FILTER_OP_IN_ETHER_TYPE_LEN 2
2784 #define MC_CMD_FILTER_OP_IN_INNER_VLAN_OFST 54
2785 #define MC_CMD_FILTER_OP_IN_INNER_VLAN_LEN 2
2786 #define MC_CMD_FILTER_OP_IN_OUTER_VLAN_OFST 56
2787 #define MC_CMD_FILTER_OP_IN_OUTER_VLAN_LEN 2
2788 #define MC_CMD_FILTER_OP_IN_IP_PROTO_OFST 58
2789 #define MC_CMD_FILTER_OP_IN_IP_PROTO_LEN 2
2790 #define MC_CMD_FILTER_OP_IN_FWDEF0_OFST 60
2791 #define MC_CMD_FILTER_OP_IN_FWDEF1_OFST 64
2792 #define MC_CMD_FILTER_OP_IN_SRC_IP_OFST 68
2793 #define MC_CMD_FILTER_OP_IN_SRC_IP_LEN 16
2794 #define MC_CMD_FILTER_OP_IN_DST_IP_OFST 84
2795 #define MC_CMD_FILTER_OP_IN_DST_IP_LEN 16
2796
2797 /* MC_CMD_FILTER_OP_OUT msgresponse */
2798 #define MC_CMD_FILTER_OP_OUT_LEN 8
2799 #define MC_CMD_FILTER_OP_OUT_OP_OFST 0
2800 #define MC_CMD_FILTER_OP_OUT_OP_INSERT 0x0 /* enum */
2801 #define MC_CMD_FILTER_OP_OUT_OP_REMOVE 0x1 /* enum */
2802 #define MC_CMD_FILTER_OP_OUT_OP_SUBSCRIBE 0x2 /* enum */
2803 #define MC_CMD_FILTER_OP_OUT_OP_UNSUBSCRIBE 0x3 /* enum */
2804 #define MC_CMD_FILTER_OP_OUT_HANDLE_OFST 4
2805
2806
2807 /***********************************/
2808 /* MC_CMD_SET_PF_COUNT
2809 */
2810 #define MC_CMD_SET_PF_COUNT 0x62
2811
2812 /* MC_CMD_SET_PF_COUNT_IN msgrequest */
2813 #define MC_CMD_SET_PF_COUNT_IN_LEN 4
2814 #define MC_CMD_SET_PF_COUNT_IN_PF_COUNT_OFST 0
2815
2816 /* MC_CMD_SET_PF_COUNT_OUT msgresponse */
2817 #define MC_CMD_SET_PF_COUNT_OUT_LEN 0
2818
2819
2820 /***********************************/
2821 /* MC_CMD_GET_PORT_ASSIGNMENT
2822 */
2823 #define MC_CMD_GET_PORT_ASSIGNMENT 0x63
2824
2825 /* MC_CMD_GET_PORT_ASSIGNMENT_IN msgrequest */
2826 #define MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN 0
2827
2828 /* MC_CMD_GET_PORT_ASSIGNMENT_OUT msgresponse */
2829 #define MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN 4
2830 #define MC_CMD_GET_PORT_ASSIGNMENT_OUT_PORT_OFST 0
2831
2832
2833 /***********************************/
2834 /* MC_CMD_SET_PORT_ASSIGNMENT
2835 */
2836 #define MC_CMD_SET_PORT_ASSIGNMENT 0x64
2837
2838 /* MC_CMD_SET_PORT_ASSIGNMENT_IN msgrequest */
2839 #define MC_CMD_SET_PORT_ASSIGNMENT_IN_LEN 4
2840 #define MC_CMD_SET_PORT_ASSIGNMENT_IN_PORT_OFST 0
2841
2842 /* MC_CMD_SET_PORT_ASSIGNMENT_OUT msgresponse */
2843 #define MC_CMD_SET_PORT_ASSIGNMENT_OUT_LEN 0
2844
2845
2846 /***********************************/
2847 /* MC_CMD_ALLOC_VIS
2848 */
2849 #define MC_CMD_ALLOC_VIS 0x65
2850
2851 /* MC_CMD_ALLOC_VIS_IN msgrequest */
2852 #define MC_CMD_ALLOC_VIS_IN_LEN 4
2853 #define MC_CMD_ALLOC_VIS_IN_VI_COUNT_OFST 0
2854
2855 /* MC_CMD_ALLOC_VIS_OUT msgresponse */
2856 #define MC_CMD_ALLOC_VIS_OUT_LEN 0
2857
2858
2859 /***********************************/
2860 /* MC_CMD_FREE_VIS
2861 */
2862 #define MC_CMD_FREE_VIS 0x66
2863
2864 /* MC_CMD_FREE_VIS_IN msgrequest */
2865 #define MC_CMD_FREE_VIS_IN_LEN 0
2866
2867 /* MC_CMD_FREE_VIS_OUT msgresponse */
2868 #define MC_CMD_FREE_VIS_OUT_LEN 0
2869
2870
2871 /***********************************/
2872 /* MC_CMD_GET_SRIOV_CFG
2873 */
2874 #define MC_CMD_GET_SRIOV_CFG 0x67
2875
2876 /* MC_CMD_GET_SRIOV_CFG_IN msgrequest */
2877 #define MC_CMD_GET_SRIOV_CFG_IN_LEN 0
2878
2879 /* MC_CMD_GET_SRIOV_CFG_OUT msgresponse */
2880 #define MC_CMD_GET_SRIOV_CFG_OUT_LEN 20
2881 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_CURRENT_OFST 0
2882 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_MAX_OFST 4
2883 #define MC_CMD_GET_SRIOV_CFG_OUT_FLAGS_OFST 8
2884 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_ENABLED_LBN 0
2885 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_ENABLED_WIDTH 1
2886 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_OFFSET_OFST 12
2887 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_STRIDE_OFST 16
2888
2889
2890 /***********************************/
2891 /* MC_CMD_SET_SRIOV_CFG
2892 */
2893 #define MC_CMD_SET_SRIOV_CFG 0x68
2894
2895 /* MC_CMD_SET_SRIOV_CFG_IN msgrequest */
2896 #define MC_CMD_SET_SRIOV_CFG_IN_LEN 20
2897 #define MC_CMD_SET_SRIOV_CFG_IN_VF_CURRENT_OFST 0
2898 #define MC_CMD_SET_SRIOV_CFG_IN_VF_MAX_OFST 4
2899 #define MC_CMD_SET_SRIOV_CFG_IN_FLAGS_OFST 8
2900 #define MC_CMD_SET_SRIOV_CFG_IN_VF_ENABLED_LBN 0
2901 #define MC_CMD_SET_SRIOV_CFG_IN_VF_ENABLED_WIDTH 1
2902 #define MC_CMD_SET_SRIOV_CFG_IN_VF_OFFSET_OFST 12
2903 #define MC_CMD_SET_SRIOV_CFG_IN_VF_STRIDE_OFST 16
2904
2905 /* MC_CMD_SET_SRIOV_CFG_OUT msgresponse */
2906 #define MC_CMD_SET_SRIOV_CFG_OUT_LEN 0
2907
2908
2909 /***********************************/
2910 /* MC_CMD_GET_VI_COUNT
2911 */
2912 #define MC_CMD_GET_VI_COUNT 0x69
2913
2914 /* MC_CMD_GET_VI_COUNT_IN msgrequest */
2915 #define MC_CMD_GET_VI_COUNT_IN_LEN 0
2916
2917 /* MC_CMD_GET_VI_COUNT_OUT msgresponse */
2918 #define MC_CMD_GET_VI_COUNT_OUT_LEN 4
2919 #define MC_CMD_GET_VI_COUNT_OUT_VI_COUNT_OFST 0
2920
2921
2922 /***********************************/
2923 /* MC_CMD_GET_VECTOR_CFG
2924 */
2925 #define MC_CMD_GET_VECTOR_CFG 0x70
2926
2927 /* MC_CMD_GET_VECTOR_CFG_IN msgrequest */
2928 #define MC_CMD_GET_VECTOR_CFG_IN_LEN 0
2929
2930 /* MC_CMD_GET_VECTOR_CFG_OUT msgresponse */
2931 #define MC_CMD_GET_VECTOR_CFG_OUT_LEN 12
2932 #define MC_CMD_GET_VECTOR_CFG_OUT_VEC_BASE_OFST 0
2933 #define MC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_PF_OFST 4
2934 #define MC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_VF_OFST 8
2935
2936
2937 /***********************************/
2938 /* MC_CMD_SET_VECTOR_CFG
2939 */
2940 #define MC_CMD_SET_VECTOR_CFG 0x71
2941
2942 /* MC_CMD_SET_VECTOR_CFG_IN msgrequest */
2943 #define MC_CMD_SET_VECTOR_CFG_IN_LEN 12
2944 #define MC_CMD_SET_VECTOR_CFG_IN_VEC_BASE_OFST 0
2945 #define MC_CMD_SET_VECTOR_CFG_IN_VECS_PER_PF_OFST 4
2946 #define MC_CMD_SET_VECTOR_CFG_IN_VECS_PER_VF_OFST 8
2947
2948 /* MC_CMD_SET_VECTOR_CFG_OUT msgresponse */
2949 #define MC_CMD_SET_VECTOR_CFG_OUT_LEN 0
2950
2951
2952 /***********************************/
2953 /* MC_CMD_ALLOC_PIOBUF
2954 */
2955 #define MC_CMD_ALLOC_PIOBUF 0x72
2956
2957 /* MC_CMD_ALLOC_PIOBUF_IN msgrequest */
2958 #define MC_CMD_ALLOC_PIOBUF_IN_LEN 0
2959
2960 /* MC_CMD_ALLOC_PIOBUF_OUT msgresponse */
2961 #define MC_CMD_ALLOC_PIOBUF_OUT_LEN 4
2962 #define MC_CMD_ALLOC_PIOBUF_OUT_PIOBUF_HANDLE_OFST 0
2963
2964
2965 /***********************************/
2966 /* MC_CMD_FREE_PIOBUF
2967 */
2968 #define MC_CMD_FREE_PIOBUF 0x73
2969
2970 /* MC_CMD_FREE_PIOBUF_IN msgrequest */
2971 #define MC_CMD_FREE_PIOBUF_IN_LEN 4
2972 #define MC_CMD_FREE_PIOBUF_IN_PIOBUF_HANDLE_OFST 0
2973
2974 /* MC_CMD_FREE_PIOBUF_OUT msgresponse */
2975 #define MC_CMD_FREE_PIOBUF_OUT_LEN 0
2976
2977
2978 /***********************************/
2979 /* MC_CMD_V2_EXTN
2980 */
2981 #define MC_CMD_V2_EXTN 0x7f
2982
2983 /* MC_CMD_V2_EXTN_IN msgrequest */
2984 #define MC_CMD_V2_EXTN_IN_LEN 4
2985 #define MC_CMD_V2_EXTN_IN_EXTENDED_CMD_LBN 0
2986 #define MC_CMD_V2_EXTN_IN_EXTENDED_CMD_WIDTH 15
2987 #define MC_CMD_V2_EXTN_IN_UNUSED_LBN 15
2988 #define MC_CMD_V2_EXTN_IN_UNUSED_WIDTH 1
2989 #define MC_CMD_V2_EXTN_IN_ACTUAL_LEN_LBN 16
2990 #define MC_CMD_V2_EXTN_IN_ACTUAL_LEN_WIDTH 10
2991 #define MC_CMD_V2_EXTN_IN_UNUSED2_LBN 26
2992 #define MC_CMD_V2_EXTN_IN_UNUSED2_WIDTH 6
2993
2994
2995 /***********************************/
2996 /* MC_CMD_TCM_BUCKET_ALLOC
2997 */
2998 #define MC_CMD_TCM_BUCKET_ALLOC 0x80
2999
3000 /* MC_CMD_TCM_BUCKET_ALLOC_IN msgrequest */
3001 #define MC_CMD_TCM_BUCKET_ALLOC_IN_LEN 0
3002
3003 /* MC_CMD_TCM_BUCKET_ALLOC_OUT msgresponse */
3004 #define MC_CMD_TCM_BUCKET_ALLOC_OUT_LEN 4
3005 #define MC_CMD_TCM_BUCKET_ALLOC_OUT_BUCKET_OFST 0
3006
3007
3008 /***********************************/
3009 /* MC_CMD_TCM_BUCKET_FREE
3010 */
3011 #define MC_CMD_TCM_BUCKET_FREE 0x81
3012
3013 /* MC_CMD_TCM_BUCKET_FREE_IN msgrequest */
3014 #define MC_CMD_TCM_BUCKET_FREE_IN_LEN 4
3015 #define MC_CMD_TCM_BUCKET_FREE_IN_BUCKET_OFST 0
3016
3017 /* MC_CMD_TCM_BUCKET_FREE_OUT msgresponse */
3018 #define MC_CMD_TCM_BUCKET_FREE_OUT_LEN 0
3019
3020
3021 /***********************************/
3022 /* MC_CMD_TCM_BUCKET_INIT
3023 */
3024 #define MC_CMD_TCM_BUCKET_INIT 0x82
3025
3026 /* MC_CMD_TCM_BUCKET_INIT_IN msgrequest */
3027 #define MC_CMD_TCM_BUCKET_INIT_IN_LEN 8
3028 #define MC_CMD_TCM_BUCKET_INIT_IN_BUCKET_OFST 0
3029 #define MC_CMD_TCM_BUCKET_INIT_IN_RATE_OFST 4
3030
3031 /* MC_CMD_TCM_BUCKET_INIT_OUT msgresponse */
3032 #define MC_CMD_TCM_BUCKET_INIT_OUT_LEN 0
3033
3034
3035 /***********************************/
3036 /* MC_CMD_TCM_TXQ_INIT
3037 */
3038 #define MC_CMD_TCM_TXQ_INIT 0x83
3039
3040 /* MC_CMD_TCM_TXQ_INIT_IN msgrequest */
3041 #define MC_CMD_TCM_TXQ_INIT_IN_LEN 28
3042 #define MC_CMD_TCM_TXQ_INIT_IN_QID_OFST 0
3043 #define MC_CMD_TCM_TXQ_INIT_IN_LABEL_OFST 4
3044 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAGS_OFST 8
3045 #define MC_CMD_TCM_TXQ_INIT_IN_RP_BKT_OFST 12
3046 #define MC_CMD_TCM_TXQ_INIT_IN_MAX_BKT1_OFST 16
3047 #define MC_CMD_TCM_TXQ_INIT_IN_MAX_BKT2_OFST 20
3048 #define MC_CMD_TCM_TXQ_INIT_IN_MIN_BKT_OFST 24
3049
3050 /* MC_CMD_TCM_TXQ_INIT_OUT msgresponse */
3051 #define MC_CMD_TCM_TXQ_INIT_OUT_LEN 0
3052
3053 #endif /* _SIENA_MC_DRIVER_PCOL_H */
3054 /*! \cidoxg_end */