1 /*-
2 * Copyright 2007-2013 Solarflare Communications Inc. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 */
25
26 #ifndef _SYS_EFX_REGS_H
27 #define _SYS_EFX_REGS_H
28
29
30 #ifdef __cplusplus
31 extern "C" {
32 #endif
33
34
35 /**************************************************************************
36 *
37 * Falcon/Siena registers and descriptors
38 *
39 **************************************************************************
40 */
41
42 /*
43 * FR_AB_EE_VPD_CFG0_REG_SF(128bit):
44 * SPI/VPD configuration register 0
45 */
46 #define FR_AB_EE_VPD_CFG0_REG_SF_OFST 0x00000300
47 /* falcona0,falconb0=eeprom_flash */
48 /*
49 * FR_AB_EE_VPD_CFG0_REG(128bit):
50 * SPI/VPD configuration register 0
51 */
52 #define FR_AB_EE_VPD_CFG0_REG_OFST 0x00000140
53 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
54
55 #define FRF_AB_EE_SF_FASTRD_EN_LBN 127
56 #define FRF_AB_EE_SF_FASTRD_EN_WIDTH 1
57 #define FRF_AB_EE_SF_CLOCK_DIV_LBN 120
58 #define FRF_AB_EE_SF_CLOCK_DIV_WIDTH 7
59 #define FRF_AB_EE_VPD_WIP_POLL_LBN 119
60 #define FRF_AB_EE_VPD_WIP_POLL_WIDTH 1
61 #define FRF_AB_EE_EE_CLOCK_DIV_LBN 112
62 #define FRF_AB_EE_EE_CLOCK_DIV_WIDTH 7
63 #define FRF_AB_EE_EE_WR_TMR_VALUE_LBN 96
64 #define FRF_AB_EE_EE_WR_TMR_VALUE_WIDTH 16
65 #define FRF_AB_EE_VPDW_LENGTH_LBN 80
66 #define FRF_AB_EE_VPDW_LENGTH_WIDTH 15
67 #define FRF_AB_EE_VPDW_BASE_LBN 64
68 #define FRF_AB_EE_VPDW_BASE_WIDTH 15
69 #define FRF_AB_EE_VPD_WR_CMD_EN_LBN 56
70 #define FRF_AB_EE_VPD_WR_CMD_EN_WIDTH 8
71 #define FRF_AB_EE_VPD_BASE_LBN 32
72 #define FRF_AB_EE_VPD_BASE_WIDTH 24
73 #define FRF_AB_EE_VPD_LENGTH_LBN 16
74 #define FRF_AB_EE_VPD_LENGTH_WIDTH 15
75 #define FRF_AB_EE_VPD_AD_SIZE_LBN 8
76 #define FRF_AB_EE_VPD_AD_SIZE_WIDTH 5
77 #define FRF_AB_EE_VPD_ACCESS_ON_LBN 5
78 #define FRF_AB_EE_VPD_ACCESS_ON_WIDTH 1
79 #define FRF_AB_EE_VPD_ACCESS_BLOCK_LBN 4
80 #define FRF_AB_EE_VPD_ACCESS_BLOCK_WIDTH 1
81 #define FRF_AB_EE_VPD_DEV_SF_SEL_LBN 2
82 #define FRF_AB_EE_VPD_DEV_SF_SEL_WIDTH 1
83 #define FRF_AB_EE_VPD_EN_AD9_MODE_LBN 1
84 #define FRF_AB_EE_VPD_EN_AD9_MODE_WIDTH 1
85 #define FRF_AB_EE_VPD_EN_LBN 0
86 #define FRF_AB_EE_VPD_EN_WIDTH 1
87
88
89 /*
90 * FR_AB_PCIE_SD_CTL0123_REG_SF(128bit):
91 * PCIE SerDes control register 0 to 3
92 */
93 #define FR_AB_PCIE_SD_CTL0123_REG_SF_OFST 0x00000320
94 /* falcona0,falconb0=eeprom_flash */
95 /*
96 * FR_AB_PCIE_SD_CTL0123_REG(128bit):
97 * PCIE SerDes control register 0 to 3
98 */
99 #define FR_AB_PCIE_SD_CTL0123_REG_OFST 0x00000320
100 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
101
102 #define FRF_AB_PCIE_TESTSIG_H_LBN 96
103 #define FRF_AB_PCIE_TESTSIG_H_WIDTH 19
104 #define FRF_AB_PCIE_TESTSIG_L_LBN 64
105 #define FRF_AB_PCIE_TESTSIG_L_WIDTH 19
106 #define FRF_AB_PCIE_OFFSET_LBN 56
107 #define FRF_AB_PCIE_OFFSET_WIDTH 8
108 #define FRF_AB_PCIE_OFFSETEN_H_LBN 55
109 #define FRF_AB_PCIE_OFFSETEN_H_WIDTH 1
110 #define FRF_AB_PCIE_OFFSETEN_L_LBN 54
111 #define FRF_AB_PCIE_OFFSETEN_L_WIDTH 1
112 #define FRF_AB_PCIE_HIVMODE_H_LBN 53
113 #define FRF_AB_PCIE_HIVMODE_H_WIDTH 1
114 #define FRF_AB_PCIE_HIVMODE_L_LBN 52
115 #define FRF_AB_PCIE_HIVMODE_L_WIDTH 1
116 #define FRF_AB_PCIE_PARRESET_H_LBN 51
117 #define FRF_AB_PCIE_PARRESET_H_WIDTH 1
118 #define FRF_AB_PCIE_PARRESET_L_LBN 50
119 #define FRF_AB_PCIE_PARRESET_L_WIDTH 1
120 #define FRF_AB_PCIE_LPBKWDRV_H_LBN 49
121 #define FRF_AB_PCIE_LPBKWDRV_H_WIDTH 1
122 #define FRF_AB_PCIE_LPBKWDRV_L_LBN 48
123 #define FRF_AB_PCIE_LPBKWDRV_L_WIDTH 1
124 #define FRF_AB_PCIE_LPBK_LBN 40
125 #define FRF_AB_PCIE_LPBK_WIDTH 8
126 #define FRF_AB_PCIE_PARLPBK_LBN 32
127 #define FRF_AB_PCIE_PARLPBK_WIDTH 8
128 #define FRF_AB_PCIE_RXTERMADJ_H_LBN 30
129 #define FRF_AB_PCIE_RXTERMADJ_H_WIDTH 2
130 #define FRF_AB_PCIE_RXTERMADJ_L_LBN 28
131 #define FRF_AB_PCIE_RXTERMADJ_L_WIDTH 2
132 #define FFE_AB_PCIE_RXTERMADJ_MIN15PCNT 3
133 #define FFE_AB_PCIE_RXTERMADJ_PL10PCNT 2
134 #define FFE_AB_PCIE_RXTERMADJ_MIN17PCNT 1
135 #define FFE_AB_PCIE_RXTERMADJ_NOMNL 0
136 #define FRF_AB_PCIE_TXTERMADJ_H_LBN 26
137 #define FRF_AB_PCIE_TXTERMADJ_H_WIDTH 2
138 #define FRF_AB_PCIE_TXTERMADJ_L_LBN 24
139 #define FRF_AB_PCIE_TXTERMADJ_L_WIDTH 2
140 #define FFE_AB_PCIE_TXTERMADJ_MIN15PCNT 3
141 #define FFE_AB_PCIE_TXTERMADJ_PL10PCNT 2
142 #define FFE_AB_PCIE_TXTERMADJ_MIN17PCNT 1
143 #define FFE_AB_PCIE_TXTERMADJ_NOMNL 0
144 #define FRF_AB_PCIE_RXEQCTL_H_LBN 18
145 #define FRF_AB_PCIE_RXEQCTL_H_WIDTH 2
146 #define FRF_AB_PCIE_RXEQCTL_L_LBN 16
147 #define FRF_AB_PCIE_RXEQCTL_L_WIDTH 2
148 #define FFE_AB_PCIE_RXEQCTL_OFF_ALT 3
149 #define FFE_AB_PCIE_RXEQCTL_OFF 2
150 #define FFE_AB_PCIE_RXEQCTL_MIN 1
151 #define FFE_AB_PCIE_RXEQCTL_MAX 0
152 #define FRF_AB_PCIE_HIDRV_LBN 8
153 #define FRF_AB_PCIE_HIDRV_WIDTH 8
154 #define FRF_AB_PCIE_LODRV_LBN 0
155 #define FRF_AB_PCIE_LODRV_WIDTH 8
156
157
158 /*
159 * FR_AB_PCIE_SD_CTL45_REG_SF(128bit):
160 * PCIE SerDes control register 4 and 5
161 */
162 #define FR_AB_PCIE_SD_CTL45_REG_SF_OFST 0x00000330
163 /* falcona0,falconb0=eeprom_flash */
164 /*
165 * FR_AB_PCIE_SD_CTL45_REG(128bit):
166 * PCIE SerDes control register 4 and 5
167 */
168 #define FR_AB_PCIE_SD_CTL45_REG_OFST 0x00000330
169 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
170
171 #define FRF_AB_PCIE_DTX7_LBN 60
172 #define FRF_AB_PCIE_DTX7_WIDTH 4
173 #define FRF_AB_PCIE_DTX6_LBN 56
174 #define FRF_AB_PCIE_DTX6_WIDTH 4
175 #define FRF_AB_PCIE_DTX5_LBN 52
176 #define FRF_AB_PCIE_DTX5_WIDTH 4
177 #define FRF_AB_PCIE_DTX4_LBN 48
178 #define FRF_AB_PCIE_DTX4_WIDTH 4
179 #define FRF_AB_PCIE_DTX3_LBN 44
180 #define FRF_AB_PCIE_DTX3_WIDTH 4
181 #define FRF_AB_PCIE_DTX2_LBN 40
182 #define FRF_AB_PCIE_DTX2_WIDTH 4
183 #define FRF_AB_PCIE_DTX1_LBN 36
184 #define FRF_AB_PCIE_DTX1_WIDTH 4
185 #define FRF_AB_PCIE_DTX0_LBN 32
186 #define FRF_AB_PCIE_DTX0_WIDTH 4
187 #define FRF_AB_PCIE_DEQ7_LBN 28
188 #define FRF_AB_PCIE_DEQ7_WIDTH 4
189 #define FRF_AB_PCIE_DEQ6_LBN 24
190 #define FRF_AB_PCIE_DEQ6_WIDTH 4
191 #define FRF_AB_PCIE_DEQ5_LBN 20
192 #define FRF_AB_PCIE_DEQ5_WIDTH 4
193 #define FRF_AB_PCIE_DEQ4_LBN 16
194 #define FRF_AB_PCIE_DEQ4_WIDTH 4
195 #define FRF_AB_PCIE_DEQ3_LBN 12
196 #define FRF_AB_PCIE_DEQ3_WIDTH 4
197 #define FRF_AB_PCIE_DEQ2_LBN 8
198 #define FRF_AB_PCIE_DEQ2_WIDTH 4
199 #define FRF_AB_PCIE_DEQ1_LBN 4
200 #define FRF_AB_PCIE_DEQ1_WIDTH 4
201 #define FRF_AB_PCIE_DEQ0_LBN 0
202 #define FRF_AB_PCIE_DEQ0_WIDTH 4
203
204
205 /*
206 * FR_AB_PCIE_PCS_CTL_STAT_REG_SF(128bit):
207 * PCIE PCS control and status register
208 */
209 #define FR_AB_PCIE_PCS_CTL_STAT_REG_SF_OFST 0x00000340
210 /* falcona0,falconb0=eeprom_flash */
211 /*
212 * FR_AB_PCIE_PCS_CTL_STAT_REG(128bit):
213 * PCIE PCS control and status register
214 */
215 #define FR_AB_PCIE_PCS_CTL_STAT_REG_OFST 0x00000340
216 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
217
218 #define FRF_AB_PCIE_PRBSERRCOUNT0_H_LBN 52
219 #define FRF_AB_PCIE_PRBSERRCOUNT0_H_WIDTH 4
220 #define FRF_AB_PCIE_PRBSERRCOUNT0_L_LBN 48
221 #define FRF_AB_PCIE_PRBSERRCOUNT0_L_WIDTH 4
222 #define FRF_AB_PCIE_PRBSERR_LBN 40
223 #define FRF_AB_PCIE_PRBSERR_WIDTH 8
224 #define FRF_AB_PCIE_PRBSERRH0_LBN 32
225 #define FRF_AB_PCIE_PRBSERRH0_WIDTH 8
226 #define FRF_AB_PCIE_FASTINIT_H_LBN 15
227 #define FRF_AB_PCIE_FASTINIT_H_WIDTH 1
228 #define FRF_AB_PCIE_FASTINIT_L_LBN 14
229 #define FRF_AB_PCIE_FASTINIT_L_WIDTH 1
230 #define FRF_AB_PCIE_CTCDISABLE_H_LBN 13
231 #define FRF_AB_PCIE_CTCDISABLE_H_WIDTH 1
232 #define FRF_AB_PCIE_CTCDISABLE_L_LBN 12
233 #define FRF_AB_PCIE_CTCDISABLE_L_WIDTH 1
234 #define FRF_AB_PCIE_PRBSSYNC_H_LBN 11
235 #define FRF_AB_PCIE_PRBSSYNC_H_WIDTH 1
236 #define FRF_AB_PCIE_PRBSSYNC_L_LBN 10
237 #define FRF_AB_PCIE_PRBSSYNC_L_WIDTH 1
238 #define FRF_AB_PCIE_PRBSERRACK_H_LBN 9
239 #define FRF_AB_PCIE_PRBSERRACK_H_WIDTH 1
240 #define FRF_AB_PCIE_PRBSERRACK_L_LBN 8
241 #define FRF_AB_PCIE_PRBSERRACK_L_WIDTH 1
242 #define FRF_AB_PCIE_PRBSSEL_LBN 0
243 #define FRF_AB_PCIE_PRBSSEL_WIDTH 8
244
245
246 /*
247 * FR_AB_HW_INIT_REG_SF(128bit):
248 * Hardware initialization register
249 */
250 #define FR_AB_HW_INIT_REG_SF_OFST 0x00000350
251 /* falcona0,falconb0=eeprom_flash */
252 /*
253 * FR_AZ_HW_INIT_REG(128bit):
254 * Hardware initialization register
255 */
256 #define FR_AZ_HW_INIT_REG_OFST 0x000000c0
257 /* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
258
259 #define FRF_BB_BDMRD_CPLF_FULL_LBN 124
260 #define FRF_BB_BDMRD_CPLF_FULL_WIDTH 1
261 #define FRF_BB_PCIE_CPL_TIMEOUT_CTRL_LBN 121
262 #define FRF_BB_PCIE_CPL_TIMEOUT_CTRL_WIDTH 3
263 #define FRF_CZ_TX_MRG_TAGS_LBN 120
264 #define FRF_CZ_TX_MRG_TAGS_WIDTH 1
265 #define FRF_AZ_TRGT_MASK_ALL_LBN 100
266 #define FRF_AZ_TRGT_MASK_ALL_WIDTH 1
267 #define FRF_AZ_DOORBELL_DROP_LBN 92
268 #define FRF_AZ_DOORBELL_DROP_WIDTH 8
269 #define FRF_AB_TX_RREQ_MASK_EN_LBN 76
270 #define FRF_AB_TX_RREQ_MASK_EN_WIDTH 1
271 #define FRF_AB_PE_EIDLE_DIS_LBN 75
272 #define FRF_AB_PE_EIDLE_DIS_WIDTH 1
273 #define FRF_AZ_FC_BLOCKING_EN_LBN 45
274 #define FRF_AZ_FC_BLOCKING_EN_WIDTH 1
275 #define FRF_AZ_B2B_REQ_EN_LBN 44
276 #define FRF_AZ_B2B_REQ_EN_WIDTH 1
277 #define FRF_AZ_POST_WR_MASK_LBN 40
278 #define FRF_AZ_POST_WR_MASK_WIDTH 4
279 #define FRF_AZ_TLP_TC_LBN 34
280 #define FRF_AZ_TLP_TC_WIDTH 3
281 #define FRF_AZ_TLP_ATTR_LBN 32
282 #define FRF_AZ_TLP_ATTR_WIDTH 2
283 #define FRF_AB_INTB_VEC_LBN 24
284 #define FRF_AB_INTB_VEC_WIDTH 5
285 #define FRF_AB_INTA_VEC_LBN 16
286 #define FRF_AB_INTA_VEC_WIDTH 5
287 #define FRF_AZ_WD_TIMER_LBN 8
288 #define FRF_AZ_WD_TIMER_WIDTH 8
289 #define FRF_AZ_US_DISABLE_LBN 5
290 #define FRF_AZ_US_DISABLE_WIDTH 1
291 #define FRF_AZ_TLP_EP_LBN 4
292 #define FRF_AZ_TLP_EP_WIDTH 1
293 #define FRF_AZ_ATTR_SEL_LBN 3
294 #define FRF_AZ_ATTR_SEL_WIDTH 1
295 #define FRF_AZ_TD_SEL_LBN 1
296 #define FRF_AZ_TD_SEL_WIDTH 1
297 #define FRF_AZ_TLP_TD_LBN 0
298 #define FRF_AZ_TLP_TD_WIDTH 1
299
300
301 /*
302 * FR_AB_NIC_STAT_REG_SF(128bit):
303 * NIC status register
304 */
305 #define FR_AB_NIC_STAT_REG_SF_OFST 0x00000360
306 /* falcona0,falconb0=eeprom_flash */
307 /*
308 * FR_AB_NIC_STAT_REG(128bit):
309 * NIC status register
310 */
311 #define FR_AB_NIC_STAT_REG_OFST 0x00000200
312 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
313
314 #define FRF_BB_AER_DIS_LBN 34
315 #define FRF_BB_AER_DIS_WIDTH 1
316 #define FRF_BB_EE_STRAP_EN_LBN 31
317 #define FRF_BB_EE_STRAP_EN_WIDTH 1
318 #define FRF_BB_EE_STRAP_LBN 24
319 #define FRF_BB_EE_STRAP_WIDTH 4
320 #define FRF_BB_REVISION_ID_LBN 17
321 #define FRF_BB_REVISION_ID_WIDTH 7
322 #define FRF_AB_ONCHIP_SRAM_LBN 16
323 #define FRF_AB_ONCHIP_SRAM_WIDTH 1
324 #define FRF_AB_SF_PRST_LBN 9
325 #define FRF_AB_SF_PRST_WIDTH 1
326 #define FRF_AB_EE_PRST_LBN 8
327 #define FRF_AB_EE_PRST_WIDTH 1
328 #define FRF_AB_ATE_MODE_LBN 3
329 #define FRF_AB_ATE_MODE_WIDTH 1
330 #define FRF_AB_STRAP_PINS_LBN 0
331 #define FRF_AB_STRAP_PINS_WIDTH 3
332
333
334 /*
335 * FR_AB_GLB_CTL_REG_SF(128bit):
336 * Global control register
337 */
338 #define FR_AB_GLB_CTL_REG_SF_OFST 0x00000370
339 /* falcona0,falconb0=eeprom_flash */
340 /*
341 * FR_AB_GLB_CTL_REG(128bit):
342 * Global control register
343 */
344 #define FR_AB_GLB_CTL_REG_OFST 0x00000220
345 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
346
347 #define FRF_AB_EXT_PHY_RST_CTL_LBN 63
348 #define FRF_AB_EXT_PHY_RST_CTL_WIDTH 1
349 #define FRF_AB_XAUI_SD_RST_CTL_LBN 62
350 #define FRF_AB_XAUI_SD_RST_CTL_WIDTH 1
351 #define FRF_AB_PCIE_SD_RST_CTL_LBN 61
352 #define FRF_AB_PCIE_SD_RST_CTL_WIDTH 1
353 #define FRF_AA_PCIX_RST_CTL_LBN 60
354 #define FRF_AA_PCIX_RST_CTL_WIDTH 1
355 #define FRF_BB_BIU_RST_CTL_LBN 60
356 #define FRF_BB_BIU_RST_CTL_WIDTH 1
357 #define FRF_AB_PCIE_STKY_RST_CTL_LBN 59
358 #define FRF_AB_PCIE_STKY_RST_CTL_WIDTH 1
359 #define FRF_AB_PCIE_NSTKY_RST_CTL_LBN 58
360 #define FRF_AB_PCIE_NSTKY_RST_CTL_WIDTH 1
361 #define FRF_AB_PCIE_CORE_RST_CTL_LBN 57
362 #define FRF_AB_PCIE_CORE_RST_CTL_WIDTH 1
363 #define FRF_AB_XGRX_RST_CTL_LBN 56
364 #define FRF_AB_XGRX_RST_CTL_WIDTH 1
365 #define FRF_AB_XGTX_RST_CTL_LBN 55
366 #define FRF_AB_XGTX_RST_CTL_WIDTH 1
367 #define FRF_AB_EM_RST_CTL_LBN 54
368 #define FRF_AB_EM_RST_CTL_WIDTH 1
369 #define FRF_AB_EV_RST_CTL_LBN 53
370 #define FRF_AB_EV_RST_CTL_WIDTH 1
371 #define FRF_AB_SR_RST_CTL_LBN 52
372 #define FRF_AB_SR_RST_CTL_WIDTH 1
373 #define FRF_AB_RX_RST_CTL_LBN 51
374 #define FRF_AB_RX_RST_CTL_WIDTH 1
375 #define FRF_AB_TX_RST_CTL_LBN 50
376 #define FRF_AB_TX_RST_CTL_WIDTH 1
377 #define FRF_AB_EE_RST_CTL_LBN 49
378 #define FRF_AB_EE_RST_CTL_WIDTH 1
379 #define FRF_AB_CS_RST_CTL_LBN 48
380 #define FRF_AB_CS_RST_CTL_WIDTH 1
381 #define FRF_AB_HOT_RST_CTL_LBN 40
382 #define FRF_AB_HOT_RST_CTL_WIDTH 2
383 #define FRF_AB_RST_EXT_PHY_LBN 31
384 #define FRF_AB_RST_EXT_PHY_WIDTH 1
385 #define FRF_AB_RST_XAUI_SD_LBN 30
386 #define FRF_AB_RST_XAUI_SD_WIDTH 1
387 #define FRF_AB_RST_PCIE_SD_LBN 29
388 #define FRF_AB_RST_PCIE_SD_WIDTH 1
389 #define FRF_AA_RST_PCIX_LBN 28
390 #define FRF_AA_RST_PCIX_WIDTH 1
391 #define FRF_BB_RST_BIU_LBN 28
392 #define FRF_BB_RST_BIU_WIDTH 1
393 #define FRF_AB_RST_PCIE_STKY_LBN 27
394 #define FRF_AB_RST_PCIE_STKY_WIDTH 1
395 #define FRF_AB_RST_PCIE_NSTKY_LBN 26
396 #define FRF_AB_RST_PCIE_NSTKY_WIDTH 1
397 #define FRF_AB_RST_PCIE_CORE_LBN 25
398 #define FRF_AB_RST_PCIE_CORE_WIDTH 1
399 #define FRF_AB_RST_XGRX_LBN 24
400 #define FRF_AB_RST_XGRX_WIDTH 1
401 #define FRF_AB_RST_XGTX_LBN 23
402 #define FRF_AB_RST_XGTX_WIDTH 1
403 #define FRF_AB_RST_EM_LBN 22
404 #define FRF_AB_RST_EM_WIDTH 1
405 #define FRF_AB_RST_EV_LBN 21
406 #define FRF_AB_RST_EV_WIDTH 1
407 #define FRF_AB_RST_SR_LBN 20
408 #define FRF_AB_RST_SR_WIDTH 1
409 #define FRF_AB_RST_RX_LBN 19
410 #define FRF_AB_RST_RX_WIDTH 1
411 #define FRF_AB_RST_TX_LBN 18
412 #define FRF_AB_RST_TX_WIDTH 1
413 #define FRF_AB_RST_SF_LBN 17
414 #define FRF_AB_RST_SF_WIDTH 1
415 #define FRF_AB_RST_CS_LBN 16
416 #define FRF_AB_RST_CS_WIDTH 1
417 #define FRF_AB_INT_RST_DUR_LBN 4
418 #define FRF_AB_INT_RST_DUR_WIDTH 3
419 #define FRF_AB_EXT_PHY_RST_DUR_LBN 1
420 #define FRF_AB_EXT_PHY_RST_DUR_WIDTH 3
421 #define FFE_AB_EXT_PHY_RST_DUR_10240US 7
422 #define FFE_AB_EXT_PHY_RST_DUR_5120US 6
423 #define FFE_AB_EXT_PHY_RST_DUR_2560US 5
424 #define FFE_AB_EXT_PHY_RST_DUR_1280US 4
425 #define FFE_AB_EXT_PHY_RST_DUR_640US 3
426 #define FFE_AB_EXT_PHY_RST_DUR_320US 2
427 #define FFE_AB_EXT_PHY_RST_DUR_160US 1
428 #define FFE_AB_EXT_PHY_RST_DUR_80US 0
429 #define FRF_AB_SWRST_LBN 0
430 #define FRF_AB_SWRST_WIDTH 1
431
432
433 /*
434 * FR_AZ_IOM_IND_ADR_REG(32bit):
435 * IO-mapped indirect access address register
436 */
437 #define FR_AZ_IOM_IND_ADR_REG_OFST 0x00000000
438 /* falcona0,falconb0,sienaa0=net_func_bar0 */
439
440 #define FRF_AZ_IOM_AUTO_ADR_INC_EN_LBN 24
441 #define FRF_AZ_IOM_AUTO_ADR_INC_EN_WIDTH 1
442 #define FRF_AZ_IOM_IND_ADR_LBN 0
443 #define FRF_AZ_IOM_IND_ADR_WIDTH 24
444
445
446 /*
447 * FR_AZ_IOM_IND_DAT_REG(32bit):
448 * IO-mapped indirect access data register
449 */
450 #define FR_AZ_IOM_IND_DAT_REG_OFST 0x00000004
451 /* falcona0,falconb0,sienaa0=net_func_bar0 */
452
453 #define FRF_AZ_IOM_IND_DAT_LBN 0
454 #define FRF_AZ_IOM_IND_DAT_WIDTH 32
455
456
457 /*
458 * FR_AZ_ADR_REGION_REG(128bit):
459 * Address region register
460 */
461 #define FR_AZ_ADR_REGION_REG_OFST 0x00000000
462 /* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
463
464 #define FRF_AZ_ADR_REGION3_LBN 96
465 #define FRF_AZ_ADR_REGION3_WIDTH 18
466 #define FRF_AZ_ADR_REGION2_LBN 64
467 #define FRF_AZ_ADR_REGION2_WIDTH 18
468 #define FRF_AZ_ADR_REGION1_LBN 32
469 #define FRF_AZ_ADR_REGION1_WIDTH 18
470 #define FRF_AZ_ADR_REGION0_LBN 0
471 #define FRF_AZ_ADR_REGION0_WIDTH 18
472
473
474 /*
475 * FR_AZ_INT_EN_REG_KER(128bit):
476 * Kernel driver Interrupt enable register
477 */
478 #define FR_AZ_INT_EN_REG_KER_OFST 0x00000010
479 /* falcona0,falconb0,sienaa0=net_func_bar2 */
480
481 #define FRF_AZ_KER_INT_LEVE_SEL_LBN 8
482 #define FRF_AZ_KER_INT_LEVE_SEL_WIDTH 6
483 #define FRF_AZ_KER_INT_CHAR_LBN 4
484 #define FRF_AZ_KER_INT_CHAR_WIDTH 1
485 #define FRF_AZ_KER_INT_KER_LBN 3
486 #define FRF_AZ_KER_INT_KER_WIDTH 1
487 #define FRF_AZ_DRV_INT_EN_KER_LBN 0
488 #define FRF_AZ_DRV_INT_EN_KER_WIDTH 1
489
490
491 /*
492 * FR_AZ_INT_EN_REG_CHAR(128bit):
493 * Char Driver interrupt enable register
494 */
495 #define FR_AZ_INT_EN_REG_CHAR_OFST 0x00000020
496 /* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
497
498 #define FRF_AZ_CHAR_INT_LEVE_SEL_LBN 8
499 #define FRF_AZ_CHAR_INT_LEVE_SEL_WIDTH 6
500 #define FRF_AZ_CHAR_INT_CHAR_LBN 4
501 #define FRF_AZ_CHAR_INT_CHAR_WIDTH 1
502 #define FRF_AZ_CHAR_INT_KER_LBN 3
503 #define FRF_AZ_CHAR_INT_KER_WIDTH 1
504 #define FRF_AZ_DRV_INT_EN_CHAR_LBN 0
505 #define FRF_AZ_DRV_INT_EN_CHAR_WIDTH 1
506
507
508 /*
509 * FR_AZ_INT_ADR_REG_KER(128bit):
510 * Interrupt host address for Kernel driver
511 */
512 #define FR_AZ_INT_ADR_REG_KER_OFST 0x00000030
513 /* falcona0,falconb0,sienaa0=net_func_bar2 */
514
515 #define FRF_AZ_NORM_INT_VEC_DIS_KER_LBN 64
516 #define FRF_AZ_NORM_INT_VEC_DIS_KER_WIDTH 1
517 #define FRF_AZ_INT_ADR_KER_LBN 0
518 #define FRF_AZ_INT_ADR_KER_WIDTH 64
519 #define FRF_AZ_INT_ADR_KER_DW0_LBN 0
520 #define FRF_AZ_INT_ADR_KER_DW0_WIDTH 32
521 #define FRF_AZ_INT_ADR_KER_DW1_LBN 32
522 #define FRF_AZ_INT_ADR_KER_DW1_WIDTH 32
523
524
525 /*
526 * FR_AZ_INT_ADR_REG_CHAR(128bit):
527 * Interrupt host address for Char driver
528 */
529 #define FR_AZ_INT_ADR_REG_CHAR_OFST 0x00000040
530 /* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
531
532 #define FRF_AZ_NORM_INT_VEC_DIS_CHAR_LBN 64
533 #define FRF_AZ_NORM_INT_VEC_DIS_CHAR_WIDTH 1
534 #define FRF_AZ_INT_ADR_CHAR_LBN 0
535 #define FRF_AZ_INT_ADR_CHAR_WIDTH 64
536 #define FRF_AZ_INT_ADR_CHAR_DW0_LBN 0
537 #define FRF_AZ_INT_ADR_CHAR_DW0_WIDTH 32
538 #define FRF_AZ_INT_ADR_CHAR_DW1_LBN 32
539 #define FRF_AZ_INT_ADR_CHAR_DW1_WIDTH 32
540
541
542 /*
543 * FR_AA_INT_ACK_KER(32bit):
544 * Kernel interrupt acknowledge register
545 */
546 #define FR_AA_INT_ACK_KER_OFST 0x00000050
547 /* falcona0=net_func_bar2 */
548
549 #define FRF_AA_INT_ACK_KER_FIELD_LBN 0
550 #define FRF_AA_INT_ACK_KER_FIELD_WIDTH 32
551
552
553 /*
554 * FR_BZ_INT_ISR0_REG(128bit):
555 * Function 0 Interrupt Acknowlege Status register
556 */
557 #define FR_BZ_INT_ISR0_REG_OFST 0x00000090
558 /* falconb0,sienaa0=net_func_bar2 */
559
560 #define FRF_BZ_INT_ISR_REG_LBN 0
561 #define FRF_BZ_INT_ISR_REG_WIDTH 64
562 #define FRF_BZ_INT_ISR_REG_DW0_LBN 0
563 #define FRF_BZ_INT_ISR_REG_DW0_WIDTH 32
564 #define FRF_BZ_INT_ISR_REG_DW1_LBN 32
565 #define FRF_BZ_INT_ISR_REG_DW1_WIDTH 32
566
567
568 /*
569 * FR_AB_EE_SPI_HCMD_REG(128bit):
570 * SPI host command register
571 */
572 #define FR_AB_EE_SPI_HCMD_REG_OFST 0x00000100
573 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
574
575 #define FRF_AB_EE_SPI_HCMD_CMD_EN_LBN 31
576 #define FRF_AB_EE_SPI_HCMD_CMD_EN_WIDTH 1
577 #define FRF_AB_EE_WR_TIMER_ACTIVE_LBN 28
578 #define FRF_AB_EE_WR_TIMER_ACTIVE_WIDTH 1
579 #define FRF_AB_EE_SPI_HCMD_SF_SEL_LBN 24
580 #define FRF_AB_EE_SPI_HCMD_SF_SEL_WIDTH 1
581 #define FRF_AB_EE_SPI_HCMD_DABCNT_LBN 16
582 #define FRF_AB_EE_SPI_HCMD_DABCNT_WIDTH 5
583 #define FRF_AB_EE_SPI_HCMD_READ_LBN 15
584 #define FRF_AB_EE_SPI_HCMD_READ_WIDTH 1
585 #define FRF_AB_EE_SPI_HCMD_DUBCNT_LBN 12
586 #define FRF_AB_EE_SPI_HCMD_DUBCNT_WIDTH 2
587 #define FRF_AB_EE_SPI_HCMD_ADBCNT_LBN 8
588 #define FRF_AB_EE_SPI_HCMD_ADBCNT_WIDTH 2
589 #define FRF_AB_EE_SPI_HCMD_ENC_LBN 0
590 #define FRF_AB_EE_SPI_HCMD_ENC_WIDTH 8
591
592
593 /*
594 * FR_CZ_USR_EV_CFG(32bit):
595 * User Level Event Configuration register
596 */
597 #define FR_CZ_USR_EV_CFG_OFST 0x00000100
598 /* sienaa0=net_func_bar2 */
599
600 #define FRF_CZ_USREV_DIS_LBN 16
601 #define FRF_CZ_USREV_DIS_WIDTH 1
602 #define FRF_CZ_DFLT_EVQ_LBN 0
603 #define FRF_CZ_DFLT_EVQ_WIDTH 10
604
605
606 /*
607 * FR_AB_EE_SPI_HADR_REG(128bit):
608 * SPI host address register
609 */
610 #define FR_AB_EE_SPI_HADR_REG_OFST 0x00000110
611 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
612
613 #define FRF_AB_EE_SPI_HADR_DUBYTE_LBN 24
614 #define FRF_AB_EE_SPI_HADR_DUBYTE_WIDTH 8
615 #define FRF_AB_EE_SPI_HADR_ADR_LBN 0
616 #define FRF_AB_EE_SPI_HADR_ADR_WIDTH 24
617
618
619 /*
620 * FR_AB_EE_SPI_HDATA_REG(128bit):
621 * SPI host data register
622 */
623 #define FR_AB_EE_SPI_HDATA_REG_OFST 0x00000120
624 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
625
626 #define FRF_AB_EE_SPI_HDATA3_LBN 96
627 #define FRF_AB_EE_SPI_HDATA3_WIDTH 32
628 #define FRF_AB_EE_SPI_HDATA2_LBN 64
629 #define FRF_AB_EE_SPI_HDATA2_WIDTH 32
630 #define FRF_AB_EE_SPI_HDATA1_LBN 32
631 #define FRF_AB_EE_SPI_HDATA1_WIDTH 32
632 #define FRF_AB_EE_SPI_HDATA0_LBN 0
633 #define FRF_AB_EE_SPI_HDATA0_WIDTH 32
634
635
636 /*
637 * FR_AB_EE_BASE_PAGE_REG(128bit):
638 * Expansion ROM base mirror register
639 */
640 #define FR_AB_EE_BASE_PAGE_REG_OFST 0x00000130
641 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
642
643 #define FRF_AB_EE_EXPROM_MASK_LBN 16
644 #define FRF_AB_EE_EXPROM_MASK_WIDTH 13
645 #define FRF_AB_EE_EXP_ROM_WINDOW_BASE_LBN 0
646 #define FRF_AB_EE_EXP_ROM_WINDOW_BASE_WIDTH 13
647
648
649 /*
650 * FR_AB_EE_VPD_SW_CNTL_REG(128bit):
651 * VPD access SW control register
652 */
653 #define FR_AB_EE_VPD_SW_CNTL_REG_OFST 0x00000150
654 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
655
656 #define FRF_AB_EE_VPD_CYCLE_PENDING_LBN 31
657 #define FRF_AB_EE_VPD_CYCLE_PENDING_WIDTH 1
658 #define FRF_AB_EE_VPD_CYC_WRITE_LBN 28
659 #define FRF_AB_EE_VPD_CYC_WRITE_WIDTH 1
660 #define FRF_AB_EE_VPD_CYC_ADR_LBN 0
661 #define FRF_AB_EE_VPD_CYC_ADR_WIDTH 15
662
663
664 /*
665 * FR_AB_EE_VPD_SW_DATA_REG(128bit):
666 * VPD access SW data register
667 */
668 #define FR_AB_EE_VPD_SW_DATA_REG_OFST 0x00000160
669 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
670
671 #define FRF_AB_EE_VPD_CYC_DAT_LBN 0
672 #define FRF_AB_EE_VPD_CYC_DAT_WIDTH 32
673
674
675 /*
676 * FR_BB_PCIE_CORE_INDIRECT_REG(64bit):
677 * Indirect Access to PCIE Core registers
678 */
679 #define FR_BB_PCIE_CORE_INDIRECT_REG_OFST 0x000001f0
680 /* falconb0=net_func_bar2 */
681
682 #define FRF_BB_PCIE_CORE_TARGET_DATA_LBN 32
683 #define FRF_BB_PCIE_CORE_TARGET_DATA_WIDTH 32
684 #define FRF_BB_PCIE_CORE_INDIRECT_ACCESS_DIR_LBN 15
685 #define FRF_BB_PCIE_CORE_INDIRECT_ACCESS_DIR_WIDTH 1
686 #define FRF_BB_PCIE_CORE_TARGET_REG_ADRS_LBN 0
687 #define FRF_BB_PCIE_CORE_TARGET_REG_ADRS_WIDTH 12
688
689
690 /*
691 * FR_AB_GPIO_CTL_REG(128bit):
692 * GPIO control register
693 */
694 #define FR_AB_GPIO_CTL_REG_OFST 0x00000210
695 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
696
697 #define FRF_AB_GPIO15_OEN_LBN 63
698 #define FRF_AB_GPIO15_OEN_WIDTH 1
699 #define FRF_AB_GPIO14_OEN_LBN 62
700 #define FRF_AB_GPIO14_OEN_WIDTH 1
701 #define FRF_AB_GPIO13_OEN_LBN 61
702 #define FRF_AB_GPIO13_OEN_WIDTH 1
703 #define FRF_AB_GPIO12_OEN_LBN 60
704 #define FRF_AB_GPIO12_OEN_WIDTH 1
705 #define FRF_AB_GPIO11_OEN_LBN 59
706 #define FRF_AB_GPIO11_OEN_WIDTH 1
707 #define FRF_AB_GPIO10_OEN_LBN 58
708 #define FRF_AB_GPIO10_OEN_WIDTH 1
709 #define FRF_AB_GPIO9_OEN_LBN 57
710 #define FRF_AB_GPIO9_OEN_WIDTH 1
711 #define FRF_AB_GPIO8_OEN_LBN 56
712 #define FRF_AB_GPIO8_OEN_WIDTH 1
713 #define FRF_AB_GPIO15_OUT_LBN 55
714 #define FRF_AB_GPIO15_OUT_WIDTH 1
715 #define FRF_AB_GPIO14_OUT_LBN 54
716 #define FRF_AB_GPIO14_OUT_WIDTH 1
717 #define FRF_AB_GPIO13_OUT_LBN 53
718 #define FRF_AB_GPIO13_OUT_WIDTH 1
719 #define FRF_AB_GPIO12_OUT_LBN 52
720 #define FRF_AB_GPIO12_OUT_WIDTH 1
721 #define FRF_AB_GPIO11_OUT_LBN 51
722 #define FRF_AB_GPIO11_OUT_WIDTH 1
723 #define FRF_AB_GPIO10_OUT_LBN 50
724 #define FRF_AB_GPIO10_OUT_WIDTH 1
725 #define FRF_AB_GPIO9_OUT_LBN 49
726 #define FRF_AB_GPIO9_OUT_WIDTH 1
727 #define FRF_AB_GPIO8_OUT_LBN 48
728 #define FRF_AB_GPIO8_OUT_WIDTH 1
729 #define FRF_AB_GPIO15_IN_LBN 47
730 #define FRF_AB_GPIO15_IN_WIDTH 1
731 #define FRF_AB_GPIO14_IN_LBN 46
732 #define FRF_AB_GPIO14_IN_WIDTH 1
733 #define FRF_AB_GPIO13_IN_LBN 45
734 #define FRF_AB_GPIO13_IN_WIDTH 1
735 #define FRF_AB_GPIO12_IN_LBN 44
736 #define FRF_AB_GPIO12_IN_WIDTH 1
737 #define FRF_AB_GPIO11_IN_LBN 43
738 #define FRF_AB_GPIO11_IN_WIDTH 1
739 #define FRF_AB_GPIO10_IN_LBN 42
740 #define FRF_AB_GPIO10_IN_WIDTH 1
741 #define FRF_AB_GPIO9_IN_LBN 41
742 #define FRF_AB_GPIO9_IN_WIDTH 1
743 #define FRF_AB_GPIO8_IN_LBN 40
744 #define FRF_AB_GPIO8_IN_WIDTH 1
745 #define FRF_AB_GPIO15_PWRUP_VALUE_LBN 39
746 #define FRF_AB_GPIO15_PWRUP_VALUE_WIDTH 1
747 #define FRF_AB_GPIO14_PWRUP_VALUE_LBN 38
748 #define FRF_AB_GPIO14_PWRUP_VALUE_WIDTH 1
749 #define FRF_AB_GPIO13_PWRUP_VALUE_LBN 37
750 #define FRF_AB_GPIO13_PWRUP_VALUE_WIDTH 1
751 #define FRF_AB_GPIO12_PWRUP_VALUE_LBN 36
752 #define FRF_AB_GPIO12_PWRUP_VALUE_WIDTH 1
753 #define FRF_AB_GPIO11_PWRUP_VALUE_LBN 35
754 #define FRF_AB_GPIO11_PWRUP_VALUE_WIDTH 1
755 #define FRF_AB_GPIO10_PWRUP_VALUE_LBN 34
756 #define FRF_AB_GPIO10_PWRUP_VALUE_WIDTH 1
757 #define FRF_AB_GPIO9_PWRUP_VALUE_LBN 33
758 #define FRF_AB_GPIO9_PWRUP_VALUE_WIDTH 1
759 #define FRF_AB_GPIO8_PWRUP_VALUE_LBN 32
760 #define FRF_AB_GPIO8_PWRUP_VALUE_WIDTH 1
761 #define FRF_BB_CLK156_OUT_EN_LBN 31
762 #define FRF_BB_CLK156_OUT_EN_WIDTH 1
763 #define FRF_BB_USE_NIC_CLK_LBN 30
764 #define FRF_BB_USE_NIC_CLK_WIDTH 1
765 #define FRF_AB_GPIO5_OEN_LBN 29
766 #define FRF_AB_GPIO5_OEN_WIDTH 1
767 #define FRF_AB_GPIO4_OEN_LBN 28
768 #define FRF_AB_GPIO4_OEN_WIDTH 1
769 #define FRF_AB_GPIO3_OEN_LBN 27
770 #define FRF_AB_GPIO3_OEN_WIDTH 1
771 #define FRF_AB_GPIO2_OEN_LBN 26
772 #define FRF_AB_GPIO2_OEN_WIDTH 1
773 #define FRF_AB_GPIO1_OEN_LBN 25
774 #define FRF_AB_GPIO1_OEN_WIDTH 1
775 #define FRF_AB_GPIO0_OEN_LBN 24
776 #define FRF_AB_GPIO0_OEN_WIDTH 1
777 #define FRF_AB_GPIO5_OUT_LBN 21
778 #define FRF_AB_GPIO5_OUT_WIDTH 1
779 #define FRF_AB_GPIO4_OUT_LBN 20
780 #define FRF_AB_GPIO4_OUT_WIDTH 1
781 #define FRF_AB_GPIO3_OUT_LBN 19
782 #define FRF_AB_GPIO3_OUT_WIDTH 1
783 #define FRF_AB_GPIO2_OUT_LBN 18
784 #define FRF_AB_GPIO2_OUT_WIDTH 1
785 #define FRF_AB_GPIO1_OUT_LBN 17
786 #define FRF_AB_GPIO1_OUT_WIDTH 1
787 #define FRF_AB_GPIO0_OUT_LBN 16
788 #define FRF_AB_GPIO0_OUT_WIDTH 1
789 #define FRF_AB_GPIO5_IN_LBN 13
790 #define FRF_AB_GPIO5_IN_WIDTH 1
791 #define FRF_AB_GPIO4_IN_LBN 12
792 #define FRF_AB_GPIO4_IN_WIDTH 1
793 #define FRF_AB_GPIO3_IN_LBN 11
794 #define FRF_AB_GPIO3_IN_WIDTH 1
795 #define FRF_AB_GPIO2_IN_LBN 10
796 #define FRF_AB_GPIO2_IN_WIDTH 1
797 #define FRF_AB_GPIO1_IN_LBN 9
798 #define FRF_AB_GPIO1_IN_WIDTH 1
799 #define FRF_AB_GPIO0_IN_LBN 8
800 #define FRF_AB_GPIO0_IN_WIDTH 1
801 #define FRF_AB_GPIO5_PWRUP_VALUE_LBN 5
802 #define FRF_AB_GPIO5_PWRUP_VALUE_WIDTH 1
803 #define FRF_AB_GPIO4_PWRUP_VALUE_LBN 4
804 #define FRF_AB_GPIO4_PWRUP_VALUE_WIDTH 1
805 #define FRF_AB_GPIO3_PWRUP_VALUE_LBN 3
806 #define FRF_AB_GPIO3_PWRUP_VALUE_WIDTH 1
807 #define FRF_AB_GPIO2_PWRUP_VALUE_LBN 2
808 #define FRF_AB_GPIO2_PWRUP_VALUE_WIDTH 1
809 #define FRF_AB_GPIO1_PWRUP_VALUE_LBN 1
810 #define FRF_AB_GPIO1_PWRUP_VALUE_WIDTH 1
811 #define FRF_AB_GPIO0_PWRUP_VALUE_LBN 0
812 #define FRF_AB_GPIO0_PWRUP_VALUE_WIDTH 1
813
814
815 /*
816 * FR_AZ_FATAL_INTR_REG_KER(128bit):
817 * Fatal interrupt register for Kernel
818 */
819 #define FR_AZ_FATAL_INTR_REG_KER_OFST 0x00000230
820 /* falcona0,falconb0,sienaa0=net_func_bar2 */
821
822 #define FRF_CZ_SRAM_PERR_INT_P_KER_EN_LBN 44
823 #define FRF_CZ_SRAM_PERR_INT_P_KER_EN_WIDTH 1
824 #define FRF_AB_PCI_BUSERR_INT_KER_EN_LBN 43
825 #define FRF_AB_PCI_BUSERR_INT_KER_EN_WIDTH 1
826 #define FRF_CZ_MBU_PERR_INT_KER_EN_LBN 43
827 #define FRF_CZ_MBU_PERR_INT_KER_EN_WIDTH 1
828 #define FRF_AZ_SRAM_OOB_INT_KER_EN_LBN 42
829 #define FRF_AZ_SRAM_OOB_INT_KER_EN_WIDTH 1
830 #define FRF_AZ_BUFID_OOB_INT_KER_EN_LBN 41
831 #define FRF_AZ_BUFID_OOB_INT_KER_EN_WIDTH 1
832 #define FRF_AZ_MEM_PERR_INT_KER_EN_LBN 40
833 #define FRF_AZ_MEM_PERR_INT_KER_EN_WIDTH 1
834 #define FRF_AZ_RBUF_OWN_INT_KER_EN_LBN 39
835 #define FRF_AZ_RBUF_OWN_INT_KER_EN_WIDTH 1
836 #define FRF_AZ_TBUF_OWN_INT_KER_EN_LBN 38
837 #define FRF_AZ_TBUF_OWN_INT_KER_EN_WIDTH 1
838 #define FRF_AZ_RDESCQ_OWN_INT_KER_EN_LBN 37
839 #define FRF_AZ_RDESCQ_OWN_INT_KER_EN_WIDTH 1
840 #define FRF_AZ_TDESCQ_OWN_INT_KER_EN_LBN 36
841 #define FRF_AZ_TDESCQ_OWN_INT_KER_EN_WIDTH 1
842 #define FRF_AZ_EVQ_OWN_INT_KER_EN_LBN 35
843 #define FRF_AZ_EVQ_OWN_INT_KER_EN_WIDTH 1
844 #define FRF_AZ_EVF_OFLO_INT_KER_EN_LBN 34
845 #define FRF_AZ_EVF_OFLO_INT_KER_EN_WIDTH 1
846 #define FRF_AZ_ILL_ADR_INT_KER_EN_LBN 33
847 #define FRF_AZ_ILL_ADR_INT_KER_EN_WIDTH 1
848 #define FRF_AZ_SRM_PERR_INT_KER_EN_LBN 32
849 #define FRF_AZ_SRM_PERR_INT_KER_EN_WIDTH 1
850 #define FRF_CZ_SRAM_PERR_INT_P_KER_LBN 12
851 #define FRF_CZ_SRAM_PERR_INT_P_KER_WIDTH 1
852 #define FRF_AB_PCI_BUSERR_INT_KER_LBN 11
853 #define FRF_AB_PCI_BUSERR_INT_KER_WIDTH 1
854 #define FRF_CZ_MBU_PERR_INT_KER_LBN 11
855 #define FRF_CZ_MBU_PERR_INT_KER_WIDTH 1
856 #define FRF_AZ_SRAM_OOB_INT_KER_LBN 10
857 #define FRF_AZ_SRAM_OOB_INT_KER_WIDTH 1
858 #define FRF_AZ_BUFID_DC_OOB_INT_KER_LBN 9
859 #define FRF_AZ_BUFID_DC_OOB_INT_KER_WIDTH 1
860 #define FRF_AZ_MEM_PERR_INT_KER_LBN 8
861 #define FRF_AZ_MEM_PERR_INT_KER_WIDTH 1
862 #define FRF_AZ_RBUF_OWN_INT_KER_LBN 7
863 #define FRF_AZ_RBUF_OWN_INT_KER_WIDTH 1
864 #define FRF_AZ_TBUF_OWN_INT_KER_LBN 6
865 #define FRF_AZ_TBUF_OWN_INT_KER_WIDTH 1
866 #define FRF_AZ_RDESCQ_OWN_INT_KER_LBN 5
867 #define FRF_AZ_RDESCQ_OWN_INT_KER_WIDTH 1
868 #define FRF_AZ_TDESCQ_OWN_INT_KER_LBN 4
869 #define FRF_AZ_TDESCQ_OWN_INT_KER_WIDTH 1
870 #define FRF_AZ_EVQ_OWN_INT_KER_LBN 3
871 #define FRF_AZ_EVQ_OWN_INT_KER_WIDTH 1
872 #define FRF_AZ_EVF_OFLO_INT_KER_LBN 2
873 #define FRF_AZ_EVF_OFLO_INT_KER_WIDTH 1
874 #define FRF_AZ_ILL_ADR_INT_KER_LBN 1
875 #define FRF_AZ_ILL_ADR_INT_KER_WIDTH 1
876 #define FRF_AZ_SRM_PERR_INT_KER_LBN 0
877 #define FRF_AZ_SRM_PERR_INT_KER_WIDTH 1
878
879
880 /*
881 * FR_AZ_FATAL_INTR_REG_CHAR(128bit):
882 * Fatal interrupt register for Char
883 */
884 #define FR_AZ_FATAL_INTR_REG_CHAR_OFST 0x00000240
885 /* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
886
887 #define FRF_CZ_SRAM_PERR_INT_P_CHAR_EN_LBN 44
888 #define FRF_CZ_SRAM_PERR_INT_P_CHAR_EN_WIDTH 1
889 #define FRF_AB_PCI_BUSERR_INT_CHAR_EN_LBN 43
890 #define FRF_AB_PCI_BUSERR_INT_CHAR_EN_WIDTH 1
891 #define FRF_CZ_MBU_PERR_INT_CHAR_EN_LBN 43
892 #define FRF_CZ_MBU_PERR_INT_CHAR_EN_WIDTH 1
893 #define FRF_AZ_SRAM_OOB_INT_CHAR_EN_LBN 42
894 #define FRF_AZ_SRAM_OOB_INT_CHAR_EN_WIDTH 1
895 #define FRF_AZ_BUFID_OOB_INT_CHAR_EN_LBN 41
896 #define FRF_AZ_BUFID_OOB_INT_CHAR_EN_WIDTH 1
897 #define FRF_AZ_MEM_PERR_INT_CHAR_EN_LBN 40
898 #define FRF_AZ_MEM_PERR_INT_CHAR_EN_WIDTH 1
899 #define FRF_AZ_RBUF_OWN_INT_CHAR_EN_LBN 39
900 #define FRF_AZ_RBUF_OWN_INT_CHAR_EN_WIDTH 1
901 #define FRF_AZ_TBUF_OWN_INT_CHAR_EN_LBN 38
902 #define FRF_AZ_TBUF_OWN_INT_CHAR_EN_WIDTH 1
903 #define FRF_AZ_RDESCQ_OWN_INT_CHAR_EN_LBN 37
904 #define FRF_AZ_RDESCQ_OWN_INT_CHAR_EN_WIDTH 1
905 #define FRF_AZ_TDESCQ_OWN_INT_CHAR_EN_LBN 36
906 #define FRF_AZ_TDESCQ_OWN_INT_CHAR_EN_WIDTH 1
907 #define FRF_AZ_EVQ_OWN_INT_CHAR_EN_LBN 35
908 #define FRF_AZ_EVQ_OWN_INT_CHAR_EN_WIDTH 1
909 #define FRF_AZ_EVF_OFLO_INT_CHAR_EN_LBN 34
910 #define FRF_AZ_EVF_OFLO_INT_CHAR_EN_WIDTH 1
911 #define FRF_AZ_ILL_ADR_INT_CHAR_EN_LBN 33
912 #define FRF_AZ_ILL_ADR_INT_CHAR_EN_WIDTH 1
913 #define FRF_AZ_SRM_PERR_INT_CHAR_EN_LBN 32
914 #define FRF_AZ_SRM_PERR_INT_CHAR_EN_WIDTH 1
915 #define FRF_CZ_SRAM_PERR_INT_P_CHAR_LBN 12
916 #define FRF_CZ_SRAM_PERR_INT_P_CHAR_WIDTH 1
917 #define FRF_AB_PCI_BUSERR_INT_CHAR_LBN 11
918 #define FRF_AB_PCI_BUSERR_INT_CHAR_WIDTH 1
919 #define FRF_CZ_MBU_PERR_INT_CHAR_LBN 11
920 #define FRF_CZ_MBU_PERR_INT_CHAR_WIDTH 1
921 #define FRF_AZ_SRAM_OOB_INT_CHAR_LBN 10
922 #define FRF_AZ_SRAM_OOB_INT_CHAR_WIDTH 1
923 #define FRF_AZ_BUFID_DC_OOB_INT_CHAR_LBN 9
924 #define FRF_AZ_BUFID_DC_OOB_INT_CHAR_WIDTH 1
925 #define FRF_AZ_MEM_PERR_INT_CHAR_LBN 8
926 #define FRF_AZ_MEM_PERR_INT_CHAR_WIDTH 1
927 #define FRF_AZ_RBUF_OWN_INT_CHAR_LBN 7
928 #define FRF_AZ_RBUF_OWN_INT_CHAR_WIDTH 1
929 #define FRF_AZ_TBUF_OWN_INT_CHAR_LBN 6
930 #define FRF_AZ_TBUF_OWN_INT_CHAR_WIDTH 1
931 #define FRF_AZ_RDESCQ_OWN_INT_CHAR_LBN 5
932 #define FRF_AZ_RDESCQ_OWN_INT_CHAR_WIDTH 1
933 #define FRF_AZ_TDESCQ_OWN_INT_CHAR_LBN 4
934 #define FRF_AZ_TDESCQ_OWN_INT_CHAR_WIDTH 1
935 #define FRF_AZ_EVQ_OWN_INT_CHAR_LBN 3
936 #define FRF_AZ_EVQ_OWN_INT_CHAR_WIDTH 1
937 #define FRF_AZ_EVF_OFLO_INT_CHAR_LBN 2
938 #define FRF_AZ_EVF_OFLO_INT_CHAR_WIDTH 1
939 #define FRF_AZ_ILL_ADR_INT_CHAR_LBN 1
940 #define FRF_AZ_ILL_ADR_INT_CHAR_WIDTH 1
941 #define FRF_AZ_SRM_PERR_INT_CHAR_LBN 0
942 #define FRF_AZ_SRM_PERR_INT_CHAR_WIDTH 1
943
944
945 /*
946 * FR_AZ_DP_CTRL_REG(128bit):
947 * Datapath control register
948 */
949 #define FR_AZ_DP_CTRL_REG_OFST 0x00000250
950 /* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
951
952 #define FRF_AZ_FLS_EVQ_ID_LBN 0
953 #define FRF_AZ_FLS_EVQ_ID_WIDTH 12
954
955
956 /*
957 * FR_AZ_MEM_STAT_REG(128bit):
958 * Memory status register
959 */
960 #define FR_AZ_MEM_STAT_REG_OFST 0x00000260
961 /* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
962
963 #define FRF_AB_MEM_PERR_VEC_LBN 53
964 #define FRF_AB_MEM_PERR_VEC_WIDTH 40
965 #define FRF_AB_MEM_PERR_VEC_DW0_LBN 53
966 #define FRF_AB_MEM_PERR_VEC_DW0_WIDTH 32
967 #define FRF_AB_MEM_PERR_VEC_DW1_LBN 85
968 #define FRF_AB_MEM_PERR_VEC_DW1_WIDTH 6
969 #define FRF_AB_MBIST_CORR_LBN 38
970 #define FRF_AB_MBIST_CORR_WIDTH 15
971 #define FRF_AB_MBIST_ERR_LBN 0
972 #define FRF_AB_MBIST_ERR_WIDTH 40
973 #define FRF_AB_MBIST_ERR_DW0_LBN 0
974 #define FRF_AB_MBIST_ERR_DW0_WIDTH 32
975 #define FRF_AB_MBIST_ERR_DW1_LBN 32
976 #define FRF_AB_MBIST_ERR_DW1_WIDTH 6
977 #define FRF_CZ_MEM_PERR_VEC_LBN 0
978 #define FRF_CZ_MEM_PERR_VEC_WIDTH 35
979 #define FRF_CZ_MEM_PERR_VEC_DW0_LBN 0
980 #define FRF_CZ_MEM_PERR_VEC_DW0_WIDTH 32
981 #define FRF_CZ_MEM_PERR_VEC_DW1_LBN 32
982 #define FRF_CZ_MEM_PERR_VEC_DW1_WIDTH 3
983
984
985 /*
986 * FR_PORT0_CS_DEBUG_REG(128bit):
987 * Debug register
988 */
989
990 #define FR_AZ_CS_DEBUG_REG_OFST 0x00000270
991 /* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
992
993 #define FRF_AB_GLB_DEBUG2_SEL_LBN 50
994 #define FRF_AB_GLB_DEBUG2_SEL_WIDTH 3
995 #define FRF_AB_DEBUG_BLK_SEL2_LBN 47
996 #define FRF_AB_DEBUG_BLK_SEL2_WIDTH 3
997 #define FRF_AB_DEBUG_BLK_SEL1_LBN 44
998 #define FRF_AB_DEBUG_BLK_SEL1_WIDTH 3
999 #define FRF_AB_DEBUG_BLK_SEL0_LBN 41
1000 #define FRF_AB_DEBUG_BLK_SEL0_WIDTH 3
1001 #define FRF_CZ_CS_PORT_NUM_LBN 40
1002 #define FRF_CZ_CS_PORT_NUM_WIDTH 2
1003 #define FRF_AB_MISC_DEBUG_ADDR_LBN 36
1004 #define FRF_AB_MISC_DEBUG_ADDR_WIDTH 5
1005 #define FRF_CZ_CS_RESERVED_LBN 36
1006 #define FRF_CZ_CS_RESERVED_WIDTH 4
1007 #define FRF_AB_SERDES_DEBUG_ADDR_LBN 31
1008 #define FRF_AB_SERDES_DEBUG_ADDR_WIDTH 5
1009 #define FRF_CZ_CS_PORT_FPE_DW0_LBN 1
1010 #define FRF_CZ_CS_PORT_FPE_DW0_WIDTH 32
1011 #define FRF_CZ_CS_PORT_FPE_DW1_LBN 33
1012 #define FRF_CZ_CS_PORT_FPE_DW1_WIDTH 3
1013 #define FRF_CZ_CS_PORT_FPE_LBN 1
1014 #define FRF_CZ_CS_PORT_FPE_WIDTH 35
1015 #define FRF_AB_EM_DEBUG_ADDR_LBN 26
1016 #define FRF_AB_EM_DEBUG_ADDR_WIDTH 5
1017 #define FRF_AB_SR_DEBUG_ADDR_LBN 21
1018 #define FRF_AB_SR_DEBUG_ADDR_WIDTH 5
1019 #define FRF_AB_EV_DEBUG_ADDR_LBN 16
1020 #define FRF_AB_EV_DEBUG_ADDR_WIDTH 5
1021 #define FRF_AB_RX_DEBUG_ADDR_LBN 11
1022 #define FRF_AB_RX_DEBUG_ADDR_WIDTH 5
1023 #define FRF_AB_TX_DEBUG_ADDR_LBN 6
1024 #define FRF_AB_TX_DEBUG_ADDR_WIDTH 5
1025 #define FRF_AB_CS_BIU_DEBUG_ADDR_LBN 1
1026 #define FRF_AB_CS_BIU_DEBUG_ADDR_WIDTH 5
1027 #define FRF_AZ_CS_DEBUG_EN_LBN 0
1028 #define FRF_AZ_CS_DEBUG_EN_WIDTH 1
1029
1030
1031 /*
1032 * FR_AZ_DRIVER_REG(128bit):
1033 * Driver scratch register [0-7]
1034 */
1035 #define FR_AZ_DRIVER_REG_OFST 0x00000280
1036 /* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
1037 #define FR_AZ_DRIVER_REG_STEP 16
1038 #define FR_AZ_DRIVER_REG_ROWS 8
1039
1040 #define FRF_AZ_DRIVER_DW0_LBN 0
1041 #define FRF_AZ_DRIVER_DW0_WIDTH 32
1042
1043
1044 /*
1045 * FR_AZ_ALTERA_BUILD_REG(128bit):
1046 * Altera build register
1047 */
1048 #define FR_AZ_ALTERA_BUILD_REG_OFST 0x00000300
1049 /* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
1050
1051 #define FRF_AZ_ALTERA_BUILD_VER_LBN 0
1052 #define FRF_AZ_ALTERA_BUILD_VER_WIDTH 32
1053
1054
1055 /*
1056 * FR_AZ_CSR_SPARE_REG(128bit):
1057 * Spare register
1058 */
1059 #define FR_AZ_CSR_SPARE_REG_OFST 0x00000310
1060 /* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
1061
1062 #define FRF_AZ_MEM_PERR_EN_TX_DATA_LBN 72
1063 #define FRF_AZ_MEM_PERR_EN_TX_DATA_WIDTH 2
1064 #define FRF_AZ_MEM_PERR_EN_LBN 64
1065 #define FRF_AZ_MEM_PERR_EN_WIDTH 38
1066 #define FRF_AZ_MEM_PERR_EN_DW0_LBN 64
1067 #define FRF_AZ_MEM_PERR_EN_DW0_WIDTH 32
1068 #define FRF_AZ_MEM_PERR_EN_DW1_LBN 96
1069 #define FRF_AZ_MEM_PERR_EN_DW1_WIDTH 6
1070 #define FRF_AZ_CSR_SPARE_BITS_LBN 0
1071 #define FRF_AZ_CSR_SPARE_BITS_WIDTH 32
1072
1073
1074 /*
1075 * FR_BZ_DEBUG_DATA_OUT_REG(128bit):
1076 * Live Debug and Debug 2 out ports
1077 */
1078 #define FR_BZ_DEBUG_DATA_OUT_REG_OFST 0x00000350
1079 /* falconb0,sienaa0=net_func_bar2 */
1080
1081 #define FRF_BZ_DEBUG2_PORT_LBN 25
1082 #define FRF_BZ_DEBUG2_PORT_WIDTH 15
1083 #define FRF_BZ_DEBUG1_PORT_LBN 0
1084 #define FRF_BZ_DEBUG1_PORT_WIDTH 25
1085
1086
1087 /*
1088 * FR_BZ_EVQ_RPTR_REGP0(32bit):
1089 * Event queue read pointer register
1090 */
1091 #define FR_BZ_EVQ_RPTR_REGP0_OFST 0x00000400
1092 /* falconb0,sienaa0=net_func_bar2 */
1093 #define FR_BZ_EVQ_RPTR_REGP0_STEP 8192
1094 #define FR_BZ_EVQ_RPTR_REGP0_ROWS 1024
1095 /*
1096 * FR_AA_EVQ_RPTR_REG_KER(32bit):
1097 * Event queue read pointer register
1098 */
1099 #define FR_AA_EVQ_RPTR_REG_KER_OFST 0x00011b00
1100 /* falcona0=net_func_bar2 */
1101 #define FR_AA_EVQ_RPTR_REG_KER_STEP 4
1102 #define FR_AA_EVQ_RPTR_REG_KER_ROWS 4
1103 /*
1104 * FR_AZ_EVQ_RPTR_REG(32bit):
1105 * Event queue read pointer register
1106 */
1107 #define FR_AZ_EVQ_RPTR_REG_OFST 0x00fa0000
1108 /* falconb0=net_func_bar2,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
1109 #define FR_AZ_EVQ_RPTR_REG_STEP 16
1110 #define FR_AB_EVQ_RPTR_REG_ROWS 4096
1111 #define FR_CZ_EVQ_RPTR_REG_ROWS 1024
1112 /*
1113 * FR_BB_EVQ_RPTR_REGP123(32bit):
1114 * Event queue read pointer register
1115 */
1116 #define FR_BB_EVQ_RPTR_REGP123_OFST 0x01000400
1117 /* falconb0=net_func_bar2 */
1118 #define FR_BB_EVQ_RPTR_REGP123_STEP 8192
1119 #define FR_BB_EVQ_RPTR_REGP123_ROWS 3072
1120
1121 #define FRF_AZ_EVQ_RPTR_VLD_LBN 15
1122 #define FRF_AZ_EVQ_RPTR_VLD_WIDTH 1
1123 #define FRF_AZ_EVQ_RPTR_LBN 0
1124 #define FRF_AZ_EVQ_RPTR_WIDTH 15
1125
1126
1127 /*
1128 * FR_BZ_TIMER_COMMAND_REGP0(128bit):
1129 * Timer Command Registers
1130 */
1131 #define FR_BZ_TIMER_COMMAND_REGP0_OFST 0x00000420
1132 /* falconb0,sienaa0=net_func_bar2 */
1133 #define FR_BZ_TIMER_COMMAND_REGP0_STEP 8192
1134 #define FR_BZ_TIMER_COMMAND_REGP0_ROWS 1024
1135 /*
1136 * FR_AA_TIMER_COMMAND_REG_KER(128bit):
1137 * Timer Command Registers
1138 */
1139 #define FR_AA_TIMER_COMMAND_REG_KER_OFST 0x00000420
1140 /* falcona0=net_func_bar2 */
1141 #define FR_AA_TIMER_COMMAND_REG_KER_STEP 8192
1142 #define FR_AA_TIMER_COMMAND_REG_KER_ROWS 4
1143 /*
1144 * FR_AB_TIMER_COMMAND_REGP123(128bit):
1145 * Timer Command Registers
1146 */
1147 #define FR_AB_TIMER_COMMAND_REGP123_OFST 0x01000420
1148 /* falconb0=net_func_bar2,falcona0=char_func_bar0 */
1149 #define FR_AB_TIMER_COMMAND_REGP123_STEP 8192
1150 #define FR_AB_TIMER_COMMAND_REGP123_ROWS 3072
1151 /*
1152 * FR_AA_TIMER_COMMAND_REGP0(128bit):
1153 * Timer Command Registers
1154 */
1155 #define FR_AA_TIMER_COMMAND_REGP0_OFST 0x00008420
1156 /* falcona0=char_func_bar0 */
1157 #define FR_AA_TIMER_COMMAND_REGP0_STEP 8192
1158 #define FR_AA_TIMER_COMMAND_REGP0_ROWS 1020
1159
1160 #define FRF_CZ_TC_TIMER_MODE_LBN 14
1161 #define FRF_CZ_TC_TIMER_MODE_WIDTH 2
1162 #define FRF_AB_TC_TIMER_MODE_LBN 12
1163 #define FRF_AB_TC_TIMER_MODE_WIDTH 2
1164 #define FRF_CZ_TC_TIMER_VAL_LBN 0
1165 #define FRF_CZ_TC_TIMER_VAL_WIDTH 14
1166 #define FRF_AB_TC_TIMER_VAL_LBN 0
1167 #define FRF_AB_TC_TIMER_VAL_WIDTH 12
1168
1169
1170 /*
1171 * FR_AZ_DRV_EV_REG(128bit):
1172 * Driver generated event register
1173 */
1174 #define FR_AZ_DRV_EV_REG_OFST 0x00000440
1175 /* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
1176
1177 #define FRF_AZ_DRV_EV_QID_LBN 64
1178 #define FRF_AZ_DRV_EV_QID_WIDTH 12
1179 #define FRF_AZ_DRV_EV_DATA_LBN 0
1180 #define FRF_AZ_DRV_EV_DATA_WIDTH 64
1181 #define FRF_AZ_DRV_EV_DATA_DW0_LBN 0
1182 #define FRF_AZ_DRV_EV_DATA_DW0_WIDTH 32
1183 #define FRF_AZ_DRV_EV_DATA_DW1_LBN 32
1184 #define FRF_AZ_DRV_EV_DATA_DW1_WIDTH 32
1185
1186
1187 /*
1188 * FR_AZ_EVQ_CTL_REG(128bit):
1189 * Event queue control register
1190 */
1191 #define FR_AZ_EVQ_CTL_REG_OFST 0x00000450
1192 /* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
1193
1194 #define FRF_CZ_RX_EVQ_WAKEUP_MASK_LBN 15
1195 #define FRF_CZ_RX_EVQ_WAKEUP_MASK_WIDTH 10
1196 #define FRF_BB_RX_EVQ_WAKEUP_MASK_LBN 15
1197 #define FRF_BB_RX_EVQ_WAKEUP_MASK_WIDTH 6
1198 #define FRF_AZ_EVQ_OWNERR_CTL_LBN 14
1199 #define FRF_AZ_EVQ_OWNERR_CTL_WIDTH 1
1200 #define FRF_AZ_EVQ_FIFO_AF_TH_LBN 7
1201 #define FRF_AZ_EVQ_FIFO_AF_TH_WIDTH 7
1202 #define FRF_AZ_EVQ_FIFO_NOTAF_TH_LBN 0
1203 #define FRF_AZ_EVQ_FIFO_NOTAF_TH_WIDTH 7
1204
1205
1206 /*
1207 * FR_AZ_EVQ_CNT1_REG(128bit):
1208 * Event counter 1 register
1209 */
1210 #define FR_AZ_EVQ_CNT1_REG_OFST 0x00000460
1211 /* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
1212
1213 #define FRF_AZ_EVQ_CNT_PRE_FIFO_LBN 120
1214 #define FRF_AZ_EVQ_CNT_PRE_FIFO_WIDTH 7
1215 #define FRF_AZ_EVQ_CNT_TOBIU_LBN 100
1216 #define FRF_AZ_EVQ_CNT_TOBIU_WIDTH 20
1217 #define FRF_AZ_EVQ_TX_REQ_CNT_LBN 80
1218 #define FRF_AZ_EVQ_TX_REQ_CNT_WIDTH 20
1219 #define FRF_AZ_EVQ_RX_REQ_CNT_LBN 60
1220 #define FRF_AZ_EVQ_RX_REQ_CNT_WIDTH 20
1221 #define FRF_AZ_EVQ_EM_REQ_CNT_LBN 40
1222 #define FRF_AZ_EVQ_EM_REQ_CNT_WIDTH 20
1223 #define FRF_AZ_EVQ_CSR_REQ_CNT_LBN 20
1224 #define FRF_AZ_EVQ_CSR_REQ_CNT_WIDTH 20
1225 #define FRF_AZ_EVQ_ERR_REQ_CNT_LBN 0
1226 #define FRF_AZ_EVQ_ERR_REQ_CNT_WIDTH 20
1227
1228
1229 /*
1230 * FR_AZ_EVQ_CNT2_REG(128bit):
1231 * Event counter 2 register
1232 */
1233 #define FR_AZ_EVQ_CNT2_REG_OFST 0x00000470
1234 /* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
1235
1236 #define FRF_AZ_EVQ_UPD_REQ_CNT_LBN 104
1237 #define FRF_AZ_EVQ_UPD_REQ_CNT_WIDTH 20
1238 #define FRF_AZ_EVQ_CLR_REQ_CNT_LBN 84
1239 #define FRF_AZ_EVQ_CLR_REQ_CNT_WIDTH 20
1240 #define FRF_AZ_EVQ_RDY_CNT_LBN 80
1241 #define FRF_AZ_EVQ_RDY_CNT_WIDTH 4
1242 #define FRF_AZ_EVQ_WU_REQ_CNT_LBN 60
1243 #define FRF_AZ_EVQ_WU_REQ_CNT_WIDTH 20
1244 #define FRF_AZ_EVQ_WET_REQ_CNT_LBN 40
1245 #define FRF_AZ_EVQ_WET_REQ_CNT_WIDTH 20
1246 #define FRF_AZ_EVQ_INIT_REQ_CNT_LBN 20
1247 #define FRF_AZ_EVQ_INIT_REQ_CNT_WIDTH 20
1248 #define FRF_AZ_EVQ_TM_REQ_CNT_LBN 0
1249 #define FRF_AZ_EVQ_TM_REQ_CNT_WIDTH 20
1250
1251
1252 /*
1253 * FR_CZ_USR_EV_REG(32bit):
1254 * Event mailbox register
1255 */
1256 #define FR_CZ_USR_EV_REG_OFST 0x00000540
1257 /* sienaa0=net_func_bar2 */
1258 #define FR_CZ_USR_EV_REG_STEP 8192
1259 #define FR_CZ_USR_EV_REG_ROWS 1024
1260
1261 #define FRF_CZ_USR_EV_DATA_LBN 0
1262 #define FRF_CZ_USR_EV_DATA_WIDTH 32
1263
1264
1265 /*
1266 * FR_AZ_BUF_TBL_CFG_REG(128bit):
1267 * Buffer table configuration register
1268 */
1269 #define FR_AZ_BUF_TBL_CFG_REG_OFST 0x00000600
1270 /* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
1271
1272 #define FRF_AZ_BUF_TBL_MODE_LBN 3
1273 #define FRF_AZ_BUF_TBL_MODE_WIDTH 1
1274
1275
1276 /*
1277 * FR_AZ_SRM_RX_DC_CFG_REG(128bit):
1278 * SRAM receive descriptor cache configuration register
1279 */
1280 #define FR_AZ_SRM_RX_DC_CFG_REG_OFST 0x00000610
1281 /* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
1282
1283 #define FRF_AZ_SRM_CLK_TMP_EN_LBN 21
1284 #define FRF_AZ_SRM_CLK_TMP_EN_WIDTH 1
1285 #define FRF_AZ_SRM_RX_DC_BASE_ADR_LBN 0
1286 #define FRF_AZ_SRM_RX_DC_BASE_ADR_WIDTH 21
1287
1288
1289 /*
1290 * FR_AZ_SRM_TX_DC_CFG_REG(128bit):
1291 * SRAM transmit descriptor cache configuration register
1292 */
1293 #define FR_AZ_SRM_TX_DC_CFG_REG_OFST 0x00000620
1294 /* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
1295
1296 #define FRF_AZ_SRM_TX_DC_BASE_ADR_LBN 0
1297 #define FRF_AZ_SRM_TX_DC_BASE_ADR_WIDTH 21
1298
1299
1300 /*
1301 * FR_AZ_SRM_CFG_REG(128bit):
1302 * SRAM configuration register
1303 */
1304 #define FR_AZ_SRM_CFG_REG_SF_OFST 0x00000380
1305 /* falcona0,falconb0=eeprom_flash */
1306 /*
1307 * FR_AZ_SRM_CFG_REG(128bit):
1308 * SRAM configuration register
1309 */
1310 #define FR_AZ_SRM_CFG_REG_OFST 0x00000630
1311 /* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
1312
1313 #define FRF_AZ_SRM_OOB_ADR_INTEN_LBN 5
1314 #define FRF_AZ_SRM_OOB_ADR_INTEN_WIDTH 1
1315 #define FRF_AZ_SRM_OOB_BUF_INTEN_LBN 4
1316 #define FRF_AZ_SRM_OOB_BUF_INTEN_WIDTH 1
1317 #define FRF_AZ_SRM_INIT_EN_LBN 3
1318 #define FRF_AZ_SRM_INIT_EN_WIDTH 1
1319 #define FRF_AZ_SRM_NUM_BANK_LBN 2
1320 #define FRF_AZ_SRM_NUM_BANK_WIDTH 1
1321 #define FRF_AZ_SRM_BANK_SIZE_LBN 0
1322 #define FRF_AZ_SRM_BANK_SIZE_WIDTH 2
1323
1324
1325 /*
1326 * FR_AZ_BUF_TBL_UPD_REG(128bit):
1327 * Buffer table update register
1328 */
1329 #define FR_AZ_BUF_TBL_UPD_REG_OFST 0x00000650
1330 /* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
1331
1332 #define FRF_AZ_BUF_UPD_CMD_LBN 63
1333 #define FRF_AZ_BUF_UPD_CMD_WIDTH 1
1334 #define FRF_AZ_BUF_CLR_CMD_LBN 62
1335 #define FRF_AZ_BUF_CLR_CMD_WIDTH 1
1336 #define FRF_AZ_BUF_CLR_END_ID_LBN 32
1337 #define FRF_AZ_BUF_CLR_END_ID_WIDTH 20
1338 #define FRF_AZ_BUF_CLR_START_ID_LBN 0
1339 #define FRF_AZ_BUF_CLR_START_ID_WIDTH 20
1340
1341
1342 /*
1343 * FR_AZ_SRM_UPD_EVQ_REG(128bit):
1344 * Buffer table update register
1345 */
1346 #define FR_AZ_SRM_UPD_EVQ_REG_OFST 0x00000660
1347 /* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
1348
1349 #define FRF_AZ_SRM_UPD_EVQ_ID_LBN 0
1350 #define FRF_AZ_SRM_UPD_EVQ_ID_WIDTH 12
1351
1352
1353 /*
1354 * FR_AZ_SRAM_PARITY_REG(128bit):
1355 * SRAM parity register.
1356 */
1357 #define FR_AZ_SRAM_PARITY_REG_OFST 0x00000670
1358 /* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
1359
1360 #define FRF_CZ_BYPASS_ECC_LBN 3
1361 #define FRF_CZ_BYPASS_ECC_WIDTH 1
1362 #define FRF_CZ_SEC_INT_LBN 2
1363 #define FRF_CZ_SEC_INT_WIDTH 1
1364 #define FRF_CZ_FORCE_SRAM_DOUBLE_ERR_LBN 1
1365 #define FRF_CZ_FORCE_SRAM_DOUBLE_ERR_WIDTH 1
1366 #define FRF_CZ_FORCE_SRAM_SINGLE_ERR_LBN 0
1367 #define FRF_CZ_FORCE_SRAM_SINGLE_ERR_WIDTH 1
1368 #define FRF_AB_FORCE_SRAM_PERR_LBN 0
1369 #define FRF_AB_FORCE_SRAM_PERR_WIDTH 1
1370
1371
1372 /*
1373 * FR_AZ_RX_CFG_REG(128bit):
1374 * Receive configuration register
1375 */
1376 #define FR_AZ_RX_CFG_REG_OFST 0x00000800
1377 /* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
1378
1379 #define FRF_CZ_RX_HDR_SPLIT_EN_LBN 71
1380 #define FRF_CZ_RX_HDR_SPLIT_EN_WIDTH 1
1381 #define FRF_CZ_RX_HDR_SPLIT_PLD_BUF_SIZE_LBN 62
1382 #define FRF_CZ_RX_HDR_SPLIT_PLD_BUF_SIZE_WIDTH 9
1383 #define FRF_CZ_RX_HDR_SPLIT_HDR_BUF_SIZE_LBN 53
1384 #define FRF_CZ_RX_HDR_SPLIT_HDR_BUF_SIZE_WIDTH 9
1385 #define FRF_CZ_RX_PRE_RFF_IPG_LBN 49
1386 #define FRF_CZ_RX_PRE_RFF_IPG_WIDTH 4
1387 #define FRF_BZ_RX_TCP_SUP_LBN 48
1388 #define FRF_BZ_RX_TCP_SUP_WIDTH 1
1389 #define FRF_BZ_RX_INGR_EN_LBN 47
1390 #define FRF_BZ_RX_INGR_EN_WIDTH 1
1391 #define FRF_BZ_RX_IP_HASH_LBN 46
1392 #define FRF_BZ_RX_IP_HASH_WIDTH 1
1393 #define FRF_BZ_RX_HASH_ALG_LBN 45
1394 #define FRF_BZ_RX_HASH_ALG_WIDTH 1
1395 #define FRF_BZ_RX_HASH_INSRT_HDR_LBN 44
1396 #define FRF_BZ_RX_HASH_INSRT_HDR_WIDTH 1
1397 #define FRF_BZ_RX_DESC_PUSH_EN_LBN 43
1398 #define FRF_BZ_RX_DESC_PUSH_EN_WIDTH 1
1399 #define FRF_BZ_RX_RDW_PATCH_EN_LBN 42
1400 #define FRF_BZ_RX_RDW_PATCH_EN_WIDTH 1
1401 #define FRF_BB_RX_PCI_BURST_SIZE_LBN 39
1402 #define FRF_BB_RX_PCI_BURST_SIZE_WIDTH 3
1403 #define FRF_BZ_RX_OWNERR_CTL_LBN 38
1404 #define FRF_BZ_RX_OWNERR_CTL_WIDTH 1
1405 #define FRF_BZ_RX_XON_TX_TH_LBN 33
1406 #define FRF_BZ_RX_XON_TX_TH_WIDTH 5
1407 #define FRF_AA_RX_DESC_PUSH_EN_LBN 35
1408 #define FRF_AA_RX_DESC_PUSH_EN_WIDTH 1
1409 #define FRF_AA_RX_RDW_PATCH_EN_LBN 34
1410 #define FRF_AA_RX_RDW_PATCH_EN_WIDTH 1
1411 #define FRF_AA_RX_PCI_BURST_SIZE_LBN 31
1412 #define FRF_AA_RX_PCI_BURST_SIZE_WIDTH 3
1413 #define FRF_BZ_RX_XOFF_TX_TH_LBN 28
1414 #define FRF_BZ_RX_XOFF_TX_TH_WIDTH 5
1415 #define FRF_AA_RX_OWNERR_CTL_LBN 30
1416 #define FRF_AA_RX_OWNERR_CTL_WIDTH 1
1417 #define FRF_AA_RX_XON_TX_TH_LBN 25
1418 #define FRF_AA_RX_XON_TX_TH_WIDTH 5
1419 #define FRF_BZ_RX_USR_BUF_SIZE_LBN 19
1420 #define FRF_BZ_RX_USR_BUF_SIZE_WIDTH 9
1421 #define FRF_AA_RX_XOFF_TX_TH_LBN 20
1422 #define FRF_AA_RX_XOFF_TX_TH_WIDTH 5
1423 #define FRF_AA_RX_USR_BUF_SIZE_LBN 11
1424 #define FRF_AA_RX_USR_BUF_SIZE_WIDTH 9
1425 #define FRF_BZ_RX_XON_MAC_TH_LBN 10
1426 #define FRF_BZ_RX_XON_MAC_TH_WIDTH 9
1427 #define FRF_AA_RX_XON_MAC_TH_LBN 6
1428 #define FRF_AA_RX_XON_MAC_TH_WIDTH 5
1429 #define FRF_BZ_RX_XOFF_MAC_TH_LBN 1
1430 #define FRF_BZ_RX_XOFF_MAC_TH_WIDTH 9
1431 #define FRF_AA_RX_XOFF_MAC_TH_LBN 1
1432 #define FRF_AA_RX_XOFF_MAC_TH_WIDTH 5
1433 #define FRF_AZ_RX_XOFF_MAC_EN_LBN 0
1434 #define FRF_AZ_RX_XOFF_MAC_EN_WIDTH 1
1435
1436
1437 /*
1438 * FR_AZ_RX_FILTER_CTL_REG(128bit):
1439 * Receive filter control registers
1440 */
1441 #define FR_AZ_RX_FILTER_CTL_REG_OFST 0x00000810
1442 /* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
1443
1444 #define FRF_CZ_ETHERNET_WILDCARD_SEARCH_LIMIT_LBN 94
1445 #define FRF_CZ_ETHERNET_WILDCARD_SEARCH_LIMIT_WIDTH 8
1446 #define FRF_CZ_ETHERNET_FULL_SEARCH_LIMIT_LBN 86
1447 #define FRF_CZ_ETHERNET_FULL_SEARCH_LIMIT_WIDTH 8
1448 #define FRF_CZ_RX_FILTER_ALL_VLAN_ETHERTYPES_LBN 85
1449 #define FRF_CZ_RX_FILTER_ALL_VLAN_ETHERTYPES_WIDTH 1
1450 #define FRF_CZ_RX_VLAN_MATCH_ETHERTYPE_LBN 69
1451 #define FRF_CZ_RX_VLAN_MATCH_ETHERTYPE_WIDTH 16
1452 #define FRF_CZ_MULTICAST_NOMATCH_Q_ID_LBN 57
1453 #define FRF_CZ_MULTICAST_NOMATCH_Q_ID_WIDTH 12
1454 #define FRF_CZ_MULTICAST_NOMATCH_RSS_ENABLED_LBN 56
1455 #define FRF_CZ_MULTICAST_NOMATCH_RSS_ENABLED_WIDTH 1
1456 #define FRF_CZ_MULTICAST_NOMATCH_IP_OVERRIDE_LBN 55
1457 #define FRF_CZ_MULTICAST_NOMATCH_IP_OVERRIDE_WIDTH 1
1458 #define FRF_CZ_UNICAST_NOMATCH_Q_ID_LBN 43
1459 #define FRF_CZ_UNICAST_NOMATCH_Q_ID_WIDTH 12
1460 #define FRF_CZ_UNICAST_NOMATCH_RSS_ENABLED_LBN 42
1461 #define FRF_CZ_UNICAST_NOMATCH_RSS_ENABLED_WIDTH 1
1462 #define FRF_CZ_UNICAST_NOMATCH_IP_OVERRIDE_LBN 41
1463 #define FRF_CZ_UNICAST_NOMATCH_IP_OVERRIDE_WIDTH 1
1464 #define FRF_BZ_SCATTER_ENBL_NO_MATCH_Q_LBN 40
1465 #define FRF_BZ_SCATTER_ENBL_NO_MATCH_Q_WIDTH 1
1466 #define FRF_AZ_UDP_FULL_SRCH_LIMIT_LBN 32
1467 #define FRF_AZ_UDP_FULL_SRCH_LIMIT_WIDTH 8
1468 #define FRF_AZ_NUM_KER_LBN 24
1469 #define FRF_AZ_NUM_KER_WIDTH 2
1470 #define FRF_AZ_UDP_WILD_SRCH_LIMIT_LBN 16
1471 #define FRF_AZ_UDP_WILD_SRCH_LIMIT_WIDTH 8
1472 #define FRF_AZ_TCP_WILD_SRCH_LIMIT_LBN 8
1473 #define FRF_AZ_TCP_WILD_SRCH_LIMIT_WIDTH 8
1474 #define FRF_AZ_TCP_FULL_SRCH_LIMIT_LBN 0
1475 #define FRF_AZ_TCP_FULL_SRCH_LIMIT_WIDTH 8
1476
1477
1478 /*
1479 * FR_AZ_RX_FLUSH_DESCQ_REG(128bit):
1480 * Receive flush descriptor queue register
1481 */
1482 #define FR_AZ_RX_FLUSH_DESCQ_REG_OFST 0x00000820
1483 /* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
1484
1485 #define FRF_AZ_RX_FLUSH_DESCQ_CMD_LBN 24
1486 #define FRF_AZ_RX_FLUSH_DESCQ_CMD_WIDTH 1
1487 #define FRF_AZ_RX_FLUSH_DESCQ_LBN 0
1488 #define FRF_AZ_RX_FLUSH_DESCQ_WIDTH 12
1489
1490
1491 /*
1492 * FR_BZ_RX_DESC_UPD_REGP0(128bit):
1493 * Receive descriptor update register.
1494 */
1495 #define FR_BZ_RX_DESC_UPD_REGP0_OFST 0x00000830
1496 /* falconb0,sienaa0=net_func_bar2 */
1497 #define FR_BZ_RX_DESC_UPD_REGP0_STEP 8192
1498 #define FR_BZ_RX_DESC_UPD_REGP0_ROWS 1024
1499 /*
1500 * FR_AA_RX_DESC_UPD_REG_KER(128bit):
1501 * Receive descriptor update register.
1502 */
1503 #define FR_AA_RX_DESC_UPD_REG_KER_OFST 0x00000830
1504 /* falcona0=net_func_bar2 */
1505 #define FR_AA_RX_DESC_UPD_REG_KER_STEP 8192
1506 #define FR_AA_RX_DESC_UPD_REG_KER_ROWS 4
1507 /*
1508 * FR_AB_RX_DESC_UPD_REGP123(128bit):
1509 * Receive descriptor update register.
1510 */
1511 #define FR_AB_RX_DESC_UPD_REGP123_OFST 0x01000830
1512 /* falconb0=net_func_bar2,falcona0=char_func_bar0 */
1513 #define FR_AB_RX_DESC_UPD_REGP123_STEP 8192
1514 #define FR_AB_RX_DESC_UPD_REGP123_ROWS 3072
1515 /*
1516 * FR_AA_RX_DESC_UPD_REGP0(128bit):
1517 * Receive descriptor update register.
1518 */
1519 #define FR_AA_RX_DESC_UPD_REGP0_OFST 0x00008830
1520 /* falcona0=char_func_bar0 */
1521 #define FR_AA_RX_DESC_UPD_REGP0_STEP 8192
1522 #define FR_AA_RX_DESC_UPD_REGP0_ROWS 1020
1523
1524 #define FRF_AZ_RX_DESC_WPTR_LBN 96
1525 #define FRF_AZ_RX_DESC_WPTR_WIDTH 12
1526 #define FRF_AZ_RX_DESC_PUSH_CMD_LBN 95
1527 #define FRF_AZ_RX_DESC_PUSH_CMD_WIDTH 1
1528 #define FRF_AZ_RX_DESC_LBN 0
1529 #define FRF_AZ_RX_DESC_WIDTH 64
1530 #define FRF_AZ_RX_DESC_DW0_LBN 0
1531 #define FRF_AZ_RX_DESC_DW0_WIDTH 32
1532 #define FRF_AZ_RX_DESC_DW1_LBN 32
1533 #define FRF_AZ_RX_DESC_DW1_WIDTH 32
1534
1535
1536 /*
1537 * FR_AZ_RX_DC_CFG_REG(128bit):
1538 * Receive descriptor cache configuration register
1539 */
1540 #define FR_AZ_RX_DC_CFG_REG_OFST 0x00000840
1541 /* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
1542
1543 #define FRF_AZ_RX_MAX_PF_LBN 2
1544 #define FRF_AZ_RX_MAX_PF_WIDTH 2
1545 #define FRF_AZ_RX_DC_SIZE_LBN 0
1546 #define FRF_AZ_RX_DC_SIZE_WIDTH 2
1547 #define FFE_AZ_RX_DC_SIZE_64 3
1548 #define FFE_AZ_RX_DC_SIZE_32 2
1549 #define FFE_AZ_RX_DC_SIZE_16 1
1550 #define FFE_AZ_RX_DC_SIZE_8 0
1551
1552
1553 /*
1554 * FR_AZ_RX_DC_PF_WM_REG(128bit):
1555 * Receive descriptor cache pre-fetch watermark register
1556 */
1557 #define FR_AZ_RX_DC_PF_WM_REG_OFST 0x00000850
1558 /* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
1559
1560 #define FRF_AZ_RX_DC_PF_HWM_LBN 6
1561 #define FRF_AZ_RX_DC_PF_HWM_WIDTH 6
1562 #define FRF_AZ_RX_DC_PF_LWM_LBN 0
1563 #define FRF_AZ_RX_DC_PF_LWM_WIDTH 6
1564
1565
1566 /*
1567 * FR_BZ_RX_RSS_TKEY_REG(128bit):
1568 * RSS Toeplitz hash key
1569 */
1570 #define FR_BZ_RX_RSS_TKEY_REG_OFST 0x00000860
1571 /* falconb0,sienaa0=net_func_bar2 */
1572
1573 #define FRF_BZ_RX_RSS_TKEY_LBN 96
1574 #define FRF_BZ_RX_RSS_TKEY_WIDTH 32
1575 #define FRF_BZ_RX_RSS_TKEY_DW3_LBN 96
1576 #define FRF_BZ_RX_RSS_TKEY_DW3_WIDTH 32
1577 #define FRF_BZ_RX_RSS_TKEY_DW2_LBN 64
1578 #define FRF_BZ_RX_RSS_TKEY_DW2_WIDTH 32
1579 #define FRF_BZ_RX_RSS_TKEY_DW1_LBN 32
1580 #define FRF_BZ_RX_RSS_TKEY_DW1_WIDTH 32
1581 #define FRF_BZ_RX_RSS_TKEY_DW0_LBN 0
1582 #define FRF_BZ_RX_RSS_TKEY_DW0_WIDTH 32
1583
1584
1585 /*
1586 * FR_AZ_RX_NODESC_DROP_REG(128bit):
1587 * Receive dropped packet counter register
1588 */
1589 #define FR_AZ_RX_NODESC_DROP_REG_OFST 0x00000880
1590 /* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
1591
1592 #define FRF_AZ_RX_NODESC_DROP_CNT_LBN 0
1593 #define FRF_AZ_RX_NODESC_DROP_CNT_WIDTH 16
1594
1595
1596 /*
1597 * FR_AZ_RX_SELF_RST_REG(128bit):
1598 * Receive self reset register
1599 */
1600 #define FR_AZ_RX_SELF_RST_REG_OFST 0x00000890
1601 /* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
1602
1603 #define FRF_AZ_RX_ISCSI_DIS_LBN 17
1604 #define FRF_AZ_RX_ISCSI_DIS_WIDTH 1
1605 #define FRF_AB_RX_SW_RST_REG_LBN 16
1606 #define FRF_AB_RX_SW_RST_REG_WIDTH 1
1607 #define FRF_AB_RX_SELF_RST_EN_LBN 8
1608 #define FRF_AB_RX_SELF_RST_EN_WIDTH 1
1609 #define FRF_AZ_RX_MAX_PF_LAT_LBN 4
1610 #define FRF_AZ_RX_MAX_PF_LAT_WIDTH 4
1611 #define FRF_AZ_RX_MAX_LU_LAT_LBN 0
1612 #define FRF_AZ_RX_MAX_LU_LAT_WIDTH 4
1613
1614
1615 /*
1616 * FR_AZ_RX_DEBUG_REG(128bit):
1617 * undocumented register
1618 */
1619 #define FR_AZ_RX_DEBUG_REG_OFST 0x000008a0
1620 /* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
1621
1622 #define FRF_AZ_RX_DEBUG_LBN 0
1623 #define FRF_AZ_RX_DEBUG_WIDTH 64
1624 #define FRF_AZ_RX_DEBUG_DW0_LBN 0
1625 #define FRF_AZ_RX_DEBUG_DW0_WIDTH 32
1626 #define FRF_AZ_RX_DEBUG_DW1_LBN 32
1627 #define FRF_AZ_RX_DEBUG_DW1_WIDTH 32
1628
1629
1630 /*
1631 * FR_AZ_RX_PUSH_DROP_REG(128bit):
1632 * Receive descriptor push dropped counter register
1633 */
1634 #define FR_AZ_RX_PUSH_DROP_REG_OFST 0x000008b0
1635 /* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
1636
1637 #define FRF_AZ_RX_PUSH_DROP_CNT_LBN 0
1638 #define FRF_AZ_RX_PUSH_DROP_CNT_WIDTH 32
1639
1640
1641 /*
1642 * FR_CZ_RX_RSS_IPV6_REG1(128bit):
1643 * IPv6 RSS Toeplitz hash key low bytes
1644 */
1645 #define FR_CZ_RX_RSS_IPV6_REG1_OFST 0x000008d0
1646 /* sienaa0=net_func_bar2 */
1647
1648 #define FRF_CZ_RX_RSS_IPV6_TKEY_LO_LBN 0
1649 #define FRF_CZ_RX_RSS_IPV6_TKEY_LO_WIDTH 128
1650 #define FRF_CZ_RX_RSS_IPV6_TKEY_LO_DW0_LBN 0
1651 #define FRF_CZ_RX_RSS_IPV6_TKEY_LO_DW0_WIDTH 32
1652 #define FRF_CZ_RX_RSS_IPV6_TKEY_LO_DW1_LBN 32
1653 #define FRF_CZ_RX_RSS_IPV6_TKEY_LO_DW1_WIDTH 32
1654 #define FRF_CZ_RX_RSS_IPV6_TKEY_LO_DW2_LBN 64
1655 #define FRF_CZ_RX_RSS_IPV6_TKEY_LO_DW2_WIDTH 32
1656 #define FRF_CZ_RX_RSS_IPV6_TKEY_LO_DW3_LBN 96
1657 #define FRF_CZ_RX_RSS_IPV6_TKEY_LO_DW3_WIDTH 32
1658
1659
1660 /*
1661 * FR_CZ_RX_RSS_IPV6_REG2(128bit):
1662 * IPv6 RSS Toeplitz hash key middle bytes
1663 */
1664 #define FR_CZ_RX_RSS_IPV6_REG2_OFST 0x000008e0
1665 /* sienaa0=net_func_bar2 */
1666
1667 #define FRF_CZ_RX_RSS_IPV6_TKEY_MID_LBN 0
1668 #define FRF_CZ_RX_RSS_IPV6_TKEY_MID_WIDTH 128
1669 #define FRF_CZ_RX_RSS_IPV6_TKEY_MID_DW0_LBN 0
1670 #define FRF_CZ_RX_RSS_IPV6_TKEY_MID_DW0_WIDTH 32
1671 #define FRF_CZ_RX_RSS_IPV6_TKEY_MID_DW1_LBN 32
1672 #define FRF_CZ_RX_RSS_IPV6_TKEY_MID_DW1_WIDTH 32
1673 #define FRF_CZ_RX_RSS_IPV6_TKEY_MID_DW2_LBN 64
1674 #define FRF_CZ_RX_RSS_IPV6_TKEY_MID_DW2_WIDTH 32
1675 #define FRF_CZ_RX_RSS_IPV6_TKEY_MID_DW3_LBN 96
1676 #define FRF_CZ_RX_RSS_IPV6_TKEY_MID_DW3_WIDTH 32
1677
1678
1679 /*
1680 * FR_CZ_RX_RSS_IPV6_REG3(128bit):
1681 * IPv6 RSS Toeplitz hash key upper bytes and IPv6 RSS settings
1682 */
1683 #define FR_CZ_RX_RSS_IPV6_REG3_OFST 0x000008f0
1684 /* sienaa0=net_func_bar2 */
1685
1686 #define FRF_CZ_RX_RSS_IPV6_THASH_ENABLE_LBN 66
1687 #define FRF_CZ_RX_RSS_IPV6_THASH_ENABLE_WIDTH 1
1688 #define FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE_LBN 65
1689 #define FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE_WIDTH 1
1690 #define FRF_CZ_RX_RSS_IPV6_TCP_SUPPRESS_LBN 64
1691 #define FRF_CZ_RX_RSS_IPV6_TCP_SUPPRESS_WIDTH 1
1692 #define FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN 0
1693 #define FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH 64
1694 #define FRF_CZ_RX_RSS_IPV6_TKEY_HI_DW0_LBN 0
1695 #define FRF_CZ_RX_RSS_IPV6_TKEY_HI_DW0_WIDTH 32
1696 #define FRF_CZ_RX_RSS_IPV6_TKEY_HI_DW1_LBN 32
1697 #define FRF_CZ_RX_RSS_IPV6_TKEY_HI_DW1_WIDTH 32
1698
1699
1700 /*
1701 * FR_AZ_TX_FLUSH_DESCQ_REG(128bit):
1702 * Transmit flush descriptor queue register
1703 */
1704 #define FR_AZ_TX_FLUSH_DESCQ_REG_OFST 0x00000a00
1705 /* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
1706
1707 #define FRF_AZ_TX_FLUSH_DESCQ_CMD_LBN 12
1708 #define FRF_AZ_TX_FLUSH_DESCQ_CMD_WIDTH 1
1709 #define FRF_AZ_TX_FLUSH_DESCQ_LBN 0
1710 #define FRF_AZ_TX_FLUSH_DESCQ_WIDTH 12
1711
1712
1713 /*
1714 * FR_BZ_TX_DESC_UPD_REGP0(128bit):
1715 * Transmit descriptor update register.
1716 */
1717 #define FR_BZ_TX_DESC_UPD_REGP0_OFST 0x00000a10
1718 /* falconb0,sienaa0=net_func_bar2 */
1719 #define FR_BZ_TX_DESC_UPD_REGP0_STEP 8192
1720 #define FR_BZ_TX_DESC_UPD_REGP0_ROWS 1024
1721 /*
1722 * FR_AA_TX_DESC_UPD_REG_KER(128bit):
1723 * Transmit descriptor update register.
1724 */
1725 #define FR_AA_TX_DESC_UPD_REG_KER_OFST 0x00000a10
1726 /* falcona0=net_func_bar2 */
1727 #define FR_AA_TX_DESC_UPD_REG_KER_STEP 8192
1728 #define FR_AA_TX_DESC_UPD_REG_KER_ROWS 8
1729 /*
1730 * FR_AB_TX_DESC_UPD_REGP123(128bit):
1731 * Transmit descriptor update register.
1732 */
1733 #define FR_AB_TX_DESC_UPD_REGP123_OFST 0x01000a10
1734 /* falconb0=net_func_bar2,falcona0=char_func_bar0 */
1735 #define FR_AB_TX_DESC_UPD_REGP123_STEP 8192
1736 #define FR_AB_TX_DESC_UPD_REGP123_ROWS 3072
1737 /*
1738 * FR_AA_TX_DESC_UPD_REGP0(128bit):
1739 * Transmit descriptor update register.
1740 */
1741 #define FR_AA_TX_DESC_UPD_REGP0_OFST 0x00008a10
1742 /* falcona0=char_func_bar0 */
1743 #define FR_AA_TX_DESC_UPD_REGP0_STEP 8192
1744 #define FR_AA_TX_DESC_UPD_REGP0_ROWS 1020
1745
1746 #define FRF_AZ_TX_DESC_WPTR_LBN 96
1747 #define FRF_AZ_TX_DESC_WPTR_WIDTH 12
1748 #define FRF_AZ_TX_DESC_PUSH_CMD_LBN 95
1749 #define FRF_AZ_TX_DESC_PUSH_CMD_WIDTH 1
1750 #define FRF_AZ_TX_DESC_LBN 0
1751 #define FRF_AZ_TX_DESC_WIDTH 95
1752 #define FRF_AZ_TX_DESC_DW0_LBN 0
1753 #define FRF_AZ_TX_DESC_DW0_WIDTH 32
1754 #define FRF_AZ_TX_DESC_DW1_LBN 32
1755 #define FRF_AZ_TX_DESC_DW1_WIDTH 32
1756 #define FRF_AZ_TX_DESC_DW2_LBN 64
1757 #define FRF_AZ_TX_DESC_DW2_WIDTH 31
1758
1759
1760 /*
1761 * FR_AZ_TX_DC_CFG_REG(128bit):
1762 * Transmit descriptor cache configuration register
1763 */
1764 #define FR_AZ_TX_DC_CFG_REG_OFST 0x00000a20
1765 /* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
1766
1767 #define FRF_AZ_TX_DC_SIZE_LBN 0
1768 #define FRF_AZ_TX_DC_SIZE_WIDTH 2
1769 #define FFE_AZ_TX_DC_SIZE_32 2
1770 #define FFE_AZ_TX_DC_SIZE_16 1
1771 #define FFE_AZ_TX_DC_SIZE_8 0
1772
1773
1774 /*
1775 * FR_AA_TX_CHKSM_CFG_REG(128bit):
1776 * Transmit checksum configuration register
1777 */
1778 #define FR_AA_TX_CHKSM_CFG_REG_OFST 0x00000a30
1779 /* falcona0=net_func_bar2,falcona0=char_func_bar0 */
1780
1781 #define FRF_AA_TX_Q_CHKSM_DIS_96_127_LBN 96
1782 #define FRF_AA_TX_Q_CHKSM_DIS_96_127_WIDTH 32
1783 #define FRF_AA_TX_Q_CHKSM_DIS_64_95_LBN 64
1784 #define FRF_AA_TX_Q_CHKSM_DIS_64_95_WIDTH 32
1785 #define FRF_AA_TX_Q_CHKSM_DIS_32_63_LBN 32
1786 #define FRF_AA_TX_Q_CHKSM_DIS_32_63_WIDTH 32
1787 #define FRF_AA_TX_Q_CHKSM_DIS_0_31_LBN 0
1788 #define FRF_AA_TX_Q_CHKSM_DIS_0_31_WIDTH 32
1789
1790
1791 /*
1792 * FR_AZ_TX_CFG_REG(128bit):
1793 * Transmit configuration register
1794 */
1795 #define FR_AZ_TX_CFG_REG_OFST 0x00000a50
1796 /* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
1797
1798 #define FRF_CZ_TX_CONT_LOOKUP_THRESH_RANGE_LBN 114
1799 #define FRF_CZ_TX_CONT_LOOKUP_THRESH_RANGE_WIDTH 8
1800 #define FRF_CZ_TX_FILTER_TEST_MODE_BIT_LBN 113
1801 #define FRF_CZ_TX_FILTER_TEST_MODE_BIT_WIDTH 1
1802 #define FRF_CZ_TX_ETH_FILTER_WILD_SEARCH_RANGE_LBN 105
1803 #define FRF_CZ_TX_ETH_FILTER_WILD_SEARCH_RANGE_WIDTH 8
1804 #define FRF_CZ_TX_ETH_FILTER_FULL_SEARCH_RANGE_LBN 97
1805 #define FRF_CZ_TX_ETH_FILTER_FULL_SEARCH_RANGE_WIDTH 8
1806 #define FRF_CZ_TX_UDPIP_FILTER_WILD_SEARCH_RANGE_LBN 89
1807 #define FRF_CZ_TX_UDPIP_FILTER_WILD_SEARCH_RANGE_WIDTH 8
1808 #define FRF_CZ_TX_UDPIP_FILTER_FULL_SEARCH_RANGE_LBN 81
1809 #define FRF_CZ_TX_UDPIP_FILTER_FULL_SEARCH_RANGE_WIDTH 8
1810 #define FRF_CZ_TX_TCPIP_FILTER_WILD_SEARCH_RANGE_LBN 73
1811 #define FRF_CZ_TX_TCPIP_FILTER_WILD_SEARCH_RANGE_WIDTH 8
1812 #define FRF_CZ_TX_TCPIP_FILTER_FULL_SEARCH_RANGE_LBN 65
1813 #define FRF_CZ_TX_TCPIP_FILTER_FULL_SEARCH_RANGE_WIDTH 8
1814 #define FRF_CZ_TX_FILTER_ALL_VLAN_ETHERTYPES_BIT_LBN 64
1815 #define FRF_CZ_TX_FILTER_ALL_VLAN_ETHERTYPES_BIT_WIDTH 1
1816 #define FRF_CZ_TX_VLAN_MATCH_ETHERTYPE_RANGE_LBN 48
1817 #define FRF_CZ_TX_VLAN_MATCH_ETHERTYPE_RANGE_WIDTH 16
1818 #define FRF_CZ_TX_FILTER_EN_BIT_LBN 47
1819 #define FRF_CZ_TX_FILTER_EN_BIT_WIDTH 1
1820 #define FRF_AZ_TX_IP_ID_P0_OFS_LBN 16
1821 #define FRF_AZ_TX_IP_ID_P0_OFS_WIDTH 15
1822 #define FRF_AZ_TX_NO_EOP_DISC_EN_LBN 5
1823 #define FRF_AZ_TX_NO_EOP_DISC_EN_WIDTH 1
1824 #define FRF_AZ_TX_P1_PRI_EN_LBN 4
1825 #define FRF_AZ_TX_P1_PRI_EN_WIDTH 1
1826 #define FRF_AZ_TX_OWNERR_CTL_LBN 2
1827 #define FRF_AZ_TX_OWNERR_CTL_WIDTH 1
1828 #define FRF_AA_TX_NON_IP_DROP_DIS_LBN 1
1829 #define FRF_AA_TX_NON_IP_DROP_DIS_WIDTH 1
1830 #define FRF_AZ_TX_IP_ID_REP_EN_LBN 0
1831 #define FRF_AZ_TX_IP_ID_REP_EN_WIDTH 1
1832
1833
1834 /*
1835 * FR_AZ_TX_PUSH_DROP_REG(128bit):
1836 * Transmit push dropped register
1837 */
1838 #define FR_AZ_TX_PUSH_DROP_REG_OFST 0x00000a60
1839 /* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
1840
1841 #define FRF_AZ_TX_PUSH_DROP_CNT_LBN 0
1842 #define FRF_AZ_TX_PUSH_DROP_CNT_WIDTH 32
1843
1844
1845 /*
1846 * FR_AZ_TX_RESERVED_REG(128bit):
1847 * Transmit configuration register
1848 */
1849 #define FR_AZ_TX_RESERVED_REG_OFST 0x00000a80
1850 /* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
1851
1852 #define FRF_AZ_TX_EVT_CNT_LBN 121
1853 #define FRF_AZ_TX_EVT_CNT_WIDTH 7
1854 #define FRF_AZ_TX_PREF_AGE_CNT_LBN 119
1855 #define FRF_AZ_TX_PREF_AGE_CNT_WIDTH 2
1856 #define FRF_AZ_TX_RD_COMP_TMR_LBN 96
1857 #define FRF_AZ_TX_RD_COMP_TMR_WIDTH 23
1858 #define FRF_AZ_TX_PUSH_EN_LBN 89
1859 #define FRF_AZ_TX_PUSH_EN_WIDTH 1
1860 #define FRF_AZ_TX_PUSH_CHK_DIS_LBN 88
1861 #define FRF_AZ_TX_PUSH_CHK_DIS_WIDTH 1
1862 #define FRF_AZ_TX_D_FF_FULL_P0_LBN 85
1863 #define FRF_AZ_TX_D_FF_FULL_P0_WIDTH 1
1864 #define FRF_AZ_TX_DMAR_ST_P0_LBN 81
1865 #define FRF_AZ_TX_DMAR_ST_P0_WIDTH 1
1866 #define FRF_AZ_TX_DMAQ_ST_LBN 78
1867 #define FRF_AZ_TX_DMAQ_ST_WIDTH 1
1868 #define FRF_AZ_TX_RX_SPACER_LBN 64
1869 #define FRF_AZ_TX_RX_SPACER_WIDTH 8
1870 #define FRF_AZ_TX_DROP_ABORT_EN_LBN 60
1871 #define FRF_AZ_TX_DROP_ABORT_EN_WIDTH 1
1872 #define FRF_AZ_TX_SOFT_EVT_EN_LBN 59
1873 #define FRF_AZ_TX_SOFT_EVT_EN_WIDTH 1
1874 #define FRF_AZ_TX_PS_EVT_DIS_LBN 58
1875 #define FRF_AZ_TX_PS_EVT_DIS_WIDTH 1
1876 #define FRF_AZ_TX_RX_SPACER_EN_LBN 57
1877 #define FRF_AZ_TX_RX_SPACER_EN_WIDTH 1
1878 #define FRF_AZ_TX_XP_TIMER_LBN 52
1879 #define FRF_AZ_TX_XP_TIMER_WIDTH 5
1880 #define FRF_AZ_TX_PREF_SPACER_LBN 44
1881 #define FRF_AZ_TX_PREF_SPACER_WIDTH 8
1882 #define FRF_AZ_TX_PREF_WD_TMR_LBN 22
1883 #define FRF_AZ_TX_PREF_WD_TMR_WIDTH 22
1884 #define FRF_AZ_TX_ONLY1TAG_LBN 21
1885 #define FRF_AZ_TX_ONLY1TAG_WIDTH 1
1886 #define FRF_AZ_TX_PREF_THRESHOLD_LBN 19
1887 #define FRF_AZ_TX_PREF_THRESHOLD_WIDTH 2
1888 #define FRF_AZ_TX_ONE_PKT_PER_Q_LBN 18
1889 #define FRF_AZ_TX_ONE_PKT_PER_Q_WIDTH 1
1890 #define FRF_AZ_TX_DIS_NON_IP_EV_LBN 17
1891 #define FRF_AZ_TX_DIS_NON_IP_EV_WIDTH 1
1892 #define FRF_AA_TX_DMA_FF_THR_LBN 16
1893 #define FRF_AA_TX_DMA_FF_THR_WIDTH 1
1894 #define FRF_AZ_TX_DMA_SPACER_LBN 8
1895 #define FRF_AZ_TX_DMA_SPACER_WIDTH 8
1896 #define FRF_AA_TX_TCP_DIS_LBN 7
1897 #define FRF_AA_TX_TCP_DIS_WIDTH 1
1898 #define FRF_BZ_TX_FLUSH_MIN_LEN_EN_LBN 7
1899 #define FRF_BZ_TX_FLUSH_MIN_LEN_EN_WIDTH 1
1900 #define FRF_AA_TX_IP_DIS_LBN 6
1901 #define FRF_AA_TX_IP_DIS_WIDTH 1
1902 #define FRF_AZ_TX_MAX_CPL_LBN 2
1903 #define FRF_AZ_TX_MAX_CPL_WIDTH 2
1904 #define FFE_AZ_TX_MAX_CPL_16 3
1905 #define FFE_AZ_TX_MAX_CPL_8 2
1906 #define FFE_AZ_TX_MAX_CPL_4 1
1907 #define FFE_AZ_TX_MAX_CPL_NOLIMIT 0
1908 #define FRF_AZ_TX_MAX_PREF_LBN 0
1909 #define FRF_AZ_TX_MAX_PREF_WIDTH 2
1910 #define FFE_AZ_TX_MAX_PREF_32 3
1911 #define FFE_AZ_TX_MAX_PREF_16 2
1912 #define FFE_AZ_TX_MAX_PREF_8 1
1913 #define FFE_AZ_TX_MAX_PREF_OFF 0
1914
1915
1916 /*
1917 * FR_BZ_TX_PACE_REG(128bit):
1918 * Transmit pace control register
1919 */
1920 #define FR_BZ_TX_PACE_REG_OFST 0x00000a90
1921 /* falconb0,sienaa0=net_func_bar2 */
1922 /*
1923 * FR_AA_TX_PACE_REG(128bit):
1924 * Transmit pace control register
1925 */
1926 #define FR_AA_TX_PACE_REG_OFST 0x00f80000
1927 /* falcona0=char_func_bar0 */
1928
1929 #define FRF_AZ_TX_PACE_SB_NOT_AF_LBN 19
1930 #define FRF_AZ_TX_PACE_SB_NOT_AF_WIDTH 10
1931 #define FRF_AZ_TX_PACE_SB_AF_LBN 9
1932 #define FRF_AZ_TX_PACE_SB_AF_WIDTH 10
1933 #define FRF_AZ_TX_PACE_FB_BASE_LBN 5
1934 #define FRF_AZ_TX_PACE_FB_BASE_WIDTH 4
1935 #define FRF_AZ_TX_PACE_BIN_TH_LBN 0
1936 #define FRF_AZ_TX_PACE_BIN_TH_WIDTH 5
1937
1938
1939 /*
1940 * FR_AZ_TX_PACE_DROP_QID_REG(128bit):
1941 * PACE Drop QID Counter
1942 */
1943 #define FR_AZ_TX_PACE_DROP_QID_REG_OFST 0x00000aa0
1944 /* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
1945
1946 #define FRF_AZ_TX_PACE_QID_DRP_CNT_LBN 0
1947 #define FRF_AZ_TX_PACE_QID_DRP_CNT_WIDTH 16
1948
1949
1950 /*
1951 * FR_AB_TX_VLAN_REG(128bit):
1952 * Transmit VLAN tag register
1953 */
1954 #define FR_AB_TX_VLAN_REG_OFST 0x00000ae0
1955 /* falconb0=net_func_bar2,falcona0=char_func_bar0 */
1956
1957 #define FRF_AB_TX_VLAN_EN_LBN 127
1958 #define FRF_AB_TX_VLAN_EN_WIDTH 1
1959 #define FRF_AB_TX_VLAN7_PORT1_EN_LBN 125
1960 #define FRF_AB_TX_VLAN7_PORT1_EN_WIDTH 1
1961 #define FRF_AB_TX_VLAN7_PORT0_EN_LBN 124
1962 #define FRF_AB_TX_VLAN7_PORT0_EN_WIDTH 1
1963 #define FRF_AB_TX_VLAN7_LBN 112
1964 #define FRF_AB_TX_VLAN7_WIDTH 12
1965 #define FRF_AB_TX_VLAN6_PORT1_EN_LBN 109
1966 #define FRF_AB_TX_VLAN6_PORT1_EN_WIDTH 1
1967 #define FRF_AB_TX_VLAN6_PORT0_EN_LBN 108
1968 #define FRF_AB_TX_VLAN6_PORT0_EN_WIDTH 1
1969 #define FRF_AB_TX_VLAN6_LBN 96
1970 #define FRF_AB_TX_VLAN6_WIDTH 12
1971 #define FRF_AB_TX_VLAN5_PORT1_EN_LBN 93
1972 #define FRF_AB_TX_VLAN5_PORT1_EN_WIDTH 1
1973 #define FRF_AB_TX_VLAN5_PORT0_EN_LBN 92
1974 #define FRF_AB_TX_VLAN5_PORT0_EN_WIDTH 1
1975 #define FRF_AB_TX_VLAN5_LBN 80
1976 #define FRF_AB_TX_VLAN5_WIDTH 12
1977 #define FRF_AB_TX_VLAN4_PORT1_EN_LBN 77
1978 #define FRF_AB_TX_VLAN4_PORT1_EN_WIDTH 1
1979 #define FRF_AB_TX_VLAN4_PORT0_EN_LBN 76
1980 #define FRF_AB_TX_VLAN4_PORT0_EN_WIDTH 1
1981 #define FRF_AB_TX_VLAN4_LBN 64
1982 #define FRF_AB_TX_VLAN4_WIDTH 12
1983 #define FRF_AB_TX_VLAN3_PORT1_EN_LBN 61
1984 #define FRF_AB_TX_VLAN3_PORT1_EN_WIDTH 1
1985 #define FRF_AB_TX_VLAN3_PORT0_EN_LBN 60
1986 #define FRF_AB_TX_VLAN3_PORT0_EN_WIDTH 1
1987 #define FRF_AB_TX_VLAN3_LBN 48
1988 #define FRF_AB_TX_VLAN3_WIDTH 12
1989 #define FRF_AB_TX_VLAN2_PORT1_EN_LBN 45
1990 #define FRF_AB_TX_VLAN2_PORT1_EN_WIDTH 1
1991 #define FRF_AB_TX_VLAN2_PORT0_EN_LBN 44
1992 #define FRF_AB_TX_VLAN2_PORT0_EN_WIDTH 1
1993 #define FRF_AB_TX_VLAN2_LBN 32
1994 #define FRF_AB_TX_VLAN2_WIDTH 12
1995 #define FRF_AB_TX_VLAN1_PORT1_EN_LBN 29
1996 #define FRF_AB_TX_VLAN1_PORT1_EN_WIDTH 1
1997 #define FRF_AB_TX_VLAN1_PORT0_EN_LBN 28
1998 #define FRF_AB_TX_VLAN1_PORT0_EN_WIDTH 1
1999 #define FRF_AB_TX_VLAN1_LBN 16
2000 #define FRF_AB_TX_VLAN1_WIDTH 12
2001 #define FRF_AB_TX_VLAN0_PORT1_EN_LBN 13
2002 #define FRF_AB_TX_VLAN0_PORT1_EN_WIDTH 1
2003 #define FRF_AB_TX_VLAN0_PORT0_EN_LBN 12
2004 #define FRF_AB_TX_VLAN0_PORT0_EN_WIDTH 1
2005 #define FRF_AB_TX_VLAN0_LBN 0
2006 #define FRF_AB_TX_VLAN0_WIDTH 12
2007
2008
2009 /*
2010 * FR_AZ_TX_IPFIL_PORTEN_REG(128bit):
2011 * Transmit filter control register
2012 */
2013 #define FR_AZ_TX_IPFIL_PORTEN_REG_OFST 0x00000af0
2014 /* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
2015
2016 #define FRF_AZ_TX_MADR0_FIL_EN_LBN 64
2017 #define FRF_AZ_TX_MADR0_FIL_EN_WIDTH 1
2018 #define FRF_AB_TX_IPFIL31_PORT_EN_LBN 62
2019 #define FRF_AB_TX_IPFIL31_PORT_EN_WIDTH 1
2020 #define FRF_AB_TX_IPFIL30_PORT_EN_LBN 60
2021 #define FRF_AB_TX_IPFIL30_PORT_EN_WIDTH 1
2022 #define FRF_AB_TX_IPFIL29_PORT_EN_LBN 58
2023 #define FRF_AB_TX_IPFIL29_PORT_EN_WIDTH 1
2024 #define FRF_AB_TX_IPFIL28_PORT_EN_LBN 56
2025 #define FRF_AB_TX_IPFIL28_PORT_EN_WIDTH 1
2026 #define FRF_AB_TX_IPFIL27_PORT_EN_LBN 54
2027 #define FRF_AB_TX_IPFIL27_PORT_EN_WIDTH 1
2028 #define FRF_AB_TX_IPFIL26_PORT_EN_LBN 52
2029 #define FRF_AB_TX_IPFIL26_PORT_EN_WIDTH 1
2030 #define FRF_AB_TX_IPFIL25_PORT_EN_LBN 50
2031 #define FRF_AB_TX_IPFIL25_PORT_EN_WIDTH 1
2032 #define FRF_AB_TX_IPFIL24_PORT_EN_LBN 48
2033 #define FRF_AB_TX_IPFIL24_PORT_EN_WIDTH 1
2034 #define FRF_AB_TX_IPFIL23_PORT_EN_LBN 46
2035 #define FRF_AB_TX_IPFIL23_PORT_EN_WIDTH 1
2036 #define FRF_AB_TX_IPFIL22_PORT_EN_LBN 44
2037 #define FRF_AB_TX_IPFIL22_PORT_EN_WIDTH 1
2038 #define FRF_AB_TX_IPFIL21_PORT_EN_LBN 42
2039 #define FRF_AB_TX_IPFIL21_PORT_EN_WIDTH 1
2040 #define FRF_AB_TX_IPFIL20_PORT_EN_LBN 40
2041 #define FRF_AB_TX_IPFIL20_PORT_EN_WIDTH 1
2042 #define FRF_AB_TX_IPFIL19_PORT_EN_LBN 38
2043 #define FRF_AB_TX_IPFIL19_PORT_EN_WIDTH 1
2044 #define FRF_AB_TX_IPFIL18_PORT_EN_LBN 36
2045 #define FRF_AB_TX_IPFIL18_PORT_EN_WIDTH 1
2046 #define FRF_AB_TX_IPFIL17_PORT_EN_LBN 34
2047 #define FRF_AB_TX_IPFIL17_PORT_EN_WIDTH 1
2048 #define FRF_AB_TX_IPFIL16_PORT_EN_LBN 32
2049 #define FRF_AB_TX_IPFIL16_PORT_EN_WIDTH 1
2050 #define FRF_AB_TX_IPFIL15_PORT_EN_LBN 30
2051 #define FRF_AB_TX_IPFIL15_PORT_EN_WIDTH 1
2052 #define FRF_AB_TX_IPFIL14_PORT_EN_LBN 28
2053 #define FRF_AB_TX_IPFIL14_PORT_EN_WIDTH 1
2054 #define FRF_AB_TX_IPFIL13_PORT_EN_LBN 26
2055 #define FRF_AB_TX_IPFIL13_PORT_EN_WIDTH 1
2056 #define FRF_AB_TX_IPFIL12_PORT_EN_LBN 24
2057 #define FRF_AB_TX_IPFIL12_PORT_EN_WIDTH 1
2058 #define FRF_AB_TX_IPFIL11_PORT_EN_LBN 22
2059 #define FRF_AB_TX_IPFIL11_PORT_EN_WIDTH 1
2060 #define FRF_AB_TX_IPFIL10_PORT_EN_LBN 20
2061 #define FRF_AB_TX_IPFIL10_PORT_EN_WIDTH 1
2062 #define FRF_AB_TX_IPFIL9_PORT_EN_LBN 18
2063 #define FRF_AB_TX_IPFIL9_PORT_EN_WIDTH 1
2064 #define FRF_AB_TX_IPFIL8_PORT_EN_LBN 16
2065 #define FRF_AB_TX_IPFIL8_PORT_EN_WIDTH 1
2066 #define FRF_AB_TX_IPFIL7_PORT_EN_LBN 14
2067 #define FRF_AB_TX_IPFIL7_PORT_EN_WIDTH 1
2068 #define FRF_AB_TX_IPFIL6_PORT_EN_LBN 12
2069 #define FRF_AB_TX_IPFIL6_PORT_EN_WIDTH 1
2070 #define FRF_AB_TX_IPFIL5_PORT_EN_LBN 10
2071 #define FRF_AB_TX_IPFIL5_PORT_EN_WIDTH 1
2072 #define FRF_AB_TX_IPFIL4_PORT_EN_LBN 8
2073 #define FRF_AB_TX_IPFIL4_PORT_EN_WIDTH 1
2074 #define FRF_AB_TX_IPFIL3_PORT_EN_LBN 6
2075 #define FRF_AB_TX_IPFIL3_PORT_EN_WIDTH 1
2076 #define FRF_AB_TX_IPFIL2_PORT_EN_LBN 4
2077 #define FRF_AB_TX_IPFIL2_PORT_EN_WIDTH 1
2078 #define FRF_AB_TX_IPFIL1_PORT_EN_LBN 2
2079 #define FRF_AB_TX_IPFIL1_PORT_EN_WIDTH 1
2080 #define FRF_AB_TX_IPFIL0_PORT_EN_LBN 0
2081 #define FRF_AB_TX_IPFIL0_PORT_EN_WIDTH 1
2082
2083
2084 /*
2085 * FR_AB_TX_IPFIL_TBL(128bit):
2086 * Transmit IP source address filter table
2087 */
2088 #define FR_AB_TX_IPFIL_TBL_OFST 0x00000b00
2089 /* falconb0=net_func_bar2,falcona0=char_func_bar0 */
2090 #define FR_AB_TX_IPFIL_TBL_STEP 16
2091 #define FR_AB_TX_IPFIL_TBL_ROWS 16
2092
2093 #define FRF_AB_TX_IPFIL_MASK_1_LBN 96
2094 #define FRF_AB_TX_IPFIL_MASK_1_WIDTH 32
2095 #define FRF_AB_TX_IP_SRC_ADR_1_LBN 64
2096 #define FRF_AB_TX_IP_SRC_ADR_1_WIDTH 32
2097 #define FRF_AB_TX_IPFIL_MASK_0_LBN 32
2098 #define FRF_AB_TX_IPFIL_MASK_0_WIDTH 32
2099 #define FRF_AB_TX_IP_SRC_ADR_0_LBN 0
2100 #define FRF_AB_TX_IP_SRC_ADR_0_WIDTH 32
2101
2102
2103 /*
2104 * FR_AB_MD_TXD_REG(128bit):
2105 * PHY management transmit data register
2106 */
2107 #define FR_AB_MD_TXD_REG_OFST 0x00000c00
2108 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
2109
2110 #define FRF_AB_MD_TXD_LBN 0
2111 #define FRF_AB_MD_TXD_WIDTH 16
2112
2113
2114 /*
2115 * FR_AB_MD_RXD_REG(128bit):
2116 * PHY management receive data register
2117 */
2118 #define FR_AB_MD_RXD_REG_OFST 0x00000c10
2119 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
2120
2121 #define FRF_AB_MD_RXD_LBN 0
2122 #define FRF_AB_MD_RXD_WIDTH 16
2123
2124
2125 /*
2126 * FR_AB_MD_CS_REG(128bit):
2127 * PHY management configuration & status register
2128 */
2129 #define FR_AB_MD_CS_REG_OFST 0x00000c20
2130 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
2131
2132 #define FRF_AB_MD_RD_EN_LBN 15
2133 #define FRF_AB_MD_RD_EN_WIDTH 1
2134 #define FRF_AB_MD_WR_EN_LBN 14
2135 #define FRF_AB_MD_WR_EN_WIDTH 1
2136 #define FRF_AB_MD_ADDR_CMD_LBN 13
2137 #define FRF_AB_MD_ADDR_CMD_WIDTH 1
2138 #define FRF_AB_MD_PT_LBN 7
2139 #define FRF_AB_MD_PT_WIDTH 3
2140 #define FRF_AB_MD_PL_LBN 6
2141 #define FRF_AB_MD_PL_WIDTH 1
2142 #define FRF_AB_MD_INT_CLR_LBN 5
2143 #define FRF_AB_MD_INT_CLR_WIDTH 1
2144 #define FRF_AB_MD_GC_LBN 4
2145 #define FRF_AB_MD_GC_WIDTH 1
2146 #define FRF_AB_MD_PRSP_LBN 3
2147 #define FRF_AB_MD_PRSP_WIDTH 1
2148 #define FRF_AB_MD_RIC_LBN 2
2149 #define FRF_AB_MD_RIC_WIDTH 1
2150 #define FRF_AB_MD_RDC_LBN 1
2151 #define FRF_AB_MD_RDC_WIDTH 1
2152 #define FRF_AB_MD_WRC_LBN 0
2153 #define FRF_AB_MD_WRC_WIDTH 1
2154
2155
2156 /*
2157 * FR_AB_MD_PHY_ADR_REG(128bit):
2158 * PHY management PHY address register
2159 */
2160 #define FR_AB_MD_PHY_ADR_REG_OFST 0x00000c30
2161 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
2162
2163 #define FRF_AB_MD_PHY_ADR_LBN 0
2164 #define FRF_AB_MD_PHY_ADR_WIDTH 16
2165
2166
2167 /*
2168 * FR_AB_MD_ID_REG(128bit):
2169 * PHY management ID register
2170 */
2171 #define FR_AB_MD_ID_REG_OFST 0x00000c40
2172 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
2173
2174 #define FRF_AB_MD_PRT_ADR_LBN 11
2175 #define FRF_AB_MD_PRT_ADR_WIDTH 5
2176 #define FRF_AB_MD_DEV_ADR_LBN 6
2177 #define FRF_AB_MD_DEV_ADR_WIDTH 5
2178
2179
2180 /*
2181 * FR_AB_MD_STAT_REG(128bit):
2182 * PHY management status & mask register
2183 */
2184 #define FR_AB_MD_STAT_REG_OFST 0x00000c50
2185 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
2186
2187 #define FRF_AB_MD_PINT_LBN 4
2188 #define FRF_AB_MD_PINT_WIDTH 1
2189 #define FRF_AB_MD_DONE_LBN 3
2190 #define FRF_AB_MD_DONE_WIDTH 1
2191 #define FRF_AB_MD_BSERR_LBN 2
2192 #define FRF_AB_MD_BSERR_WIDTH 1
2193 #define FRF_AB_MD_LNFL_LBN 1
2194 #define FRF_AB_MD_LNFL_WIDTH 1
2195 #define FRF_AB_MD_BSY_LBN 0
2196 #define FRF_AB_MD_BSY_WIDTH 1
2197
2198
2199 /*
2200 * FR_AB_MAC_STAT_DMA_REG(128bit):
2201 * Port MAC statistical counter DMA register
2202 */
2203 #define FR_AB_MAC_STAT_DMA_REG_OFST 0x00000c60
2204 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
2205
2206 #define FRF_AB_MAC_STAT_DMA_CMD_LBN 48
2207 #define FRF_AB_MAC_STAT_DMA_CMD_WIDTH 1
2208 #define FRF_AB_MAC_STAT_DMA_ADR_LBN 0
2209 #define FRF_AB_MAC_STAT_DMA_ADR_WIDTH 48
2210 #define FRF_AB_MAC_STAT_DMA_ADR_DW0_LBN 0
2211 #define FRF_AB_MAC_STAT_DMA_ADR_DW0_WIDTH 32
2212 #define FRF_AB_MAC_STAT_DMA_ADR_DW1_LBN 32
2213 #define FRF_AB_MAC_STAT_DMA_ADR_DW1_WIDTH 16
2214
2215
2216 /*
2217 * FR_AB_MAC_CTRL_REG(128bit):
2218 * Port MAC control register
2219 */
2220 #define FR_AB_MAC_CTRL_REG_OFST 0x00000c80
2221 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
2222
2223 #define FRF_AB_MAC_XOFF_VAL_LBN 16
2224 #define FRF_AB_MAC_XOFF_VAL_WIDTH 16
2225 #define FRF_BB_TXFIFO_DRAIN_EN_LBN 7
2226 #define FRF_BB_TXFIFO_DRAIN_EN_WIDTH 1
2227 #define FRF_AB_MAC_XG_DISTXCRC_LBN 5
2228 #define FRF_AB_MAC_XG_DISTXCRC_WIDTH 1
2229 #define FRF_AB_MAC_BCAD_ACPT_LBN 4
2230 #define FRF_AB_MAC_BCAD_ACPT_WIDTH 1
2231 #define FRF_AB_MAC_UC_PROM_LBN 3
2232 #define FRF_AB_MAC_UC_PROM_WIDTH 1
2233 #define FRF_AB_MAC_LINK_STATUS_LBN 2
2234 #define FRF_AB_MAC_LINK_STATUS_WIDTH 1
2235 #define FRF_AB_MAC_SPEED_LBN 0
2236 #define FRF_AB_MAC_SPEED_WIDTH 2
2237 #define FRF_AB_MAC_SPEED_10M 0
2238 #define FRF_AB_MAC_SPEED_100M 1
2239 #define FRF_AB_MAC_SPEED_1G 2
2240 #define FRF_AB_MAC_SPEED_10G 3
2241
2242 /*
2243 * FR_BB_GEN_MODE_REG(128bit):
2244 * General Purpose mode register (external interrupt mask)
2245 */
2246 #define FR_BB_GEN_MODE_REG_OFST 0x00000c90
2247 /* falconb0=net_func_bar2 */
2248
2249 #define FRF_BB_XFP_PHY_INT_POL_SEL_LBN 3
2250 #define FRF_BB_XFP_PHY_INT_POL_SEL_WIDTH 1
2251 #define FRF_BB_XG_PHY_INT_POL_SEL_LBN 2
2252 #define FRF_BB_XG_PHY_INT_POL_SEL_WIDTH 1
2253 #define FRF_BB_XFP_PHY_INT_MASK_LBN 1
2254 #define FRF_BB_XFP_PHY_INT_MASK_WIDTH 1
2255 #define FRF_BB_XG_PHY_INT_MASK_LBN 0
2256 #define FRF_BB_XG_PHY_INT_MASK_WIDTH 1
2257
2258
2259 /*
2260 * FR_AB_MAC_MC_HASH_REG0(128bit):
2261 * Multicast address hash table
2262 */
2263 #define FR_AB_MAC_MC_HASH0_REG_OFST 0x00000ca0
2264 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
2265
2266 #define FRF_AB_MAC_MCAST_HASH0_LBN 0
2267 #define FRF_AB_MAC_MCAST_HASH0_WIDTH 128
2268 #define FRF_AB_MAC_MCAST_HASH0_DW0_LBN 0
2269 #define FRF_AB_MAC_MCAST_HASH0_DW0_WIDTH 32
2270 #define FRF_AB_MAC_MCAST_HASH0_DW1_LBN 32
2271 #define FRF_AB_MAC_MCAST_HASH0_DW1_WIDTH 32
2272 #define FRF_AB_MAC_MCAST_HASH0_DW2_LBN 64
2273 #define FRF_AB_MAC_MCAST_HASH0_DW2_WIDTH 32
2274 #define FRF_AB_MAC_MCAST_HASH0_DW3_LBN 96
2275 #define FRF_AB_MAC_MCAST_HASH0_DW3_WIDTH 32
2276
2277
2278 /*
2279 * FR_AB_MAC_MC_HASH_REG1(128bit):
2280 * Multicast address hash table
2281 */
2282 #define FR_AB_MAC_MC_HASH1_REG_OFST 0x00000cb0
2283 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
2284
2285 #define FRF_AB_MAC_MCAST_HASH1_LBN 0
2286 #define FRF_AB_MAC_MCAST_HASH1_WIDTH 128
2287 #define FRF_AB_MAC_MCAST_HASH1_DW0_LBN 0
2288 #define FRF_AB_MAC_MCAST_HASH1_DW0_WIDTH 32
2289 #define FRF_AB_MAC_MCAST_HASH1_DW1_LBN 32
2290 #define FRF_AB_MAC_MCAST_HASH1_DW1_WIDTH 32
2291 #define FRF_AB_MAC_MCAST_HASH1_DW2_LBN 64
2292 #define FRF_AB_MAC_MCAST_HASH1_DW2_WIDTH 32
2293 #define FRF_AB_MAC_MCAST_HASH1_DW3_LBN 96
2294 #define FRF_AB_MAC_MCAST_HASH1_DW3_WIDTH 32
2295
2296
2297 /*
2298 * FR_AB_GM_CFG1_REG(32bit):
2299 * GMAC configuration register 1
2300 */
2301 #define FR_AB_GM_CFG1_REG_OFST 0x00000e00
2302 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
2303
2304 #define FRF_AB_GM_SW_RST_LBN 31
2305 #define FRF_AB_GM_SW_RST_WIDTH 1
2306 #define FRF_AB_GM_SIM_RST_LBN 30
2307 #define FRF_AB_GM_SIM_RST_WIDTH 1
2308 #define FRF_AB_GM_RST_RX_MAC_CTL_LBN 19
2309 #define FRF_AB_GM_RST_RX_MAC_CTL_WIDTH 1
2310 #define FRF_AB_GM_RST_TX_MAC_CTL_LBN 18
2311 #define FRF_AB_GM_RST_TX_MAC_CTL_WIDTH 1
2312 #define FRF_AB_GM_RST_RX_FUNC_LBN 17
2313 #define FRF_AB_GM_RST_RX_FUNC_WIDTH 1
2314 #define FRF_AB_GM_RST_TX_FUNC_LBN 16
2315 #define FRF_AB_GM_RST_TX_FUNC_WIDTH 1
2316 #define FRF_AB_GM_LOOP_LBN 8
2317 #define FRF_AB_GM_LOOP_WIDTH 1
2318 #define FRF_AB_GM_RX_FC_EN_LBN 5
2319 #define FRF_AB_GM_RX_FC_EN_WIDTH 1
2320 #define FRF_AB_GM_TX_FC_EN_LBN 4
2321 #define FRF_AB_GM_TX_FC_EN_WIDTH 1
2322 #define FRF_AB_GM_SYNC_RXEN_LBN 3
2323 #define FRF_AB_GM_SYNC_RXEN_WIDTH 1
2324 #define FRF_AB_GM_RX_EN_LBN 2
2325 #define FRF_AB_GM_RX_EN_WIDTH 1
2326 #define FRF_AB_GM_SYNC_TXEN_LBN 1
2327 #define FRF_AB_GM_SYNC_TXEN_WIDTH 1
2328 #define FRF_AB_GM_TX_EN_LBN 0
2329 #define FRF_AB_GM_TX_EN_WIDTH 1
2330
2331
2332 /*
2333 * FR_AB_GM_CFG2_REG(32bit):
2334 * GMAC configuration register 2
2335 */
2336 #define FR_AB_GM_CFG2_REG_OFST 0x00000e10
2337 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
2338
2339 #define FRF_AB_GM_PAMBL_LEN_LBN 12
2340 #define FRF_AB_GM_PAMBL_LEN_WIDTH 4
2341 #define FRF_AB_GM_IF_MODE_LBN 8
2342 #define FRF_AB_GM_IF_MODE_WIDTH 2
2343 #define FRF_AB_GM_IF_MODE_BYTE_MODE 2
2344 #define FRF_AB_GM_IF_MODE_NIBBLE_MODE 1
2345 #define FRF_AB_GM_HUGE_FRM_EN_LBN 5
2346 #define FRF_AB_GM_HUGE_FRM_EN_WIDTH 1
2347 #define FRF_AB_GM_LEN_CHK_LBN 4
2348 #define FRF_AB_GM_LEN_CHK_WIDTH 1
2349 #define FRF_AB_GM_PAD_CRC_EN_LBN 2
2350 #define FRF_AB_GM_PAD_CRC_EN_WIDTH 1
2351 #define FRF_AB_GM_CRC_EN_LBN 1
2352 #define FRF_AB_GM_CRC_EN_WIDTH 1
2353 #define FRF_AB_GM_FD_LBN 0
2354 #define FRF_AB_GM_FD_WIDTH 1
2355
2356
2357 /*
2358 * FR_AB_GM_IPG_REG(32bit):
2359 * GMAC IPG register
2360 */
2361 #define FR_AB_GM_IPG_REG_OFST 0x00000e20
2362 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
2363
2364 #define FRF_AB_GM_NONB2B_IPG1_LBN 24
2365 #define FRF_AB_GM_NONB2B_IPG1_WIDTH 7
2366 #define FRF_AB_GM_NONB2B_IPG2_LBN 16
2367 #define FRF_AB_GM_NONB2B_IPG2_WIDTH 7
2368 #define FRF_AB_GM_MIN_IPG_ENF_LBN 8
2369 #define FRF_AB_GM_MIN_IPG_ENF_WIDTH 8
2370 #define FRF_AB_GM_B2B_IPG_LBN 0
2371 #define FRF_AB_GM_B2B_IPG_WIDTH 7
2372
2373
2374 /*
2375 * FR_AB_GM_HD_REG(32bit):
2376 * GMAC half duplex register
2377 */
2378 #define FR_AB_GM_HD_REG_OFST 0x00000e30
2379 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
2380
2381 #define FRF_AB_GM_ALT_BOFF_VAL_LBN 20
2382 #define FRF_AB_GM_ALT_BOFF_VAL_WIDTH 4
2383 #define FRF_AB_GM_ALT_BOFF_EN_LBN 19
2384 #define FRF_AB_GM_ALT_BOFF_EN_WIDTH 1
2385 #define FRF_AB_GM_BP_NO_BOFF_LBN 18
2386 #define FRF_AB_GM_BP_NO_BOFF_WIDTH 1
2387 #define FRF_AB_GM_DIS_BOFF_LBN 17
2388 #define FRF_AB_GM_DIS_BOFF_WIDTH 1
2389 #define FRF_AB_GM_EXDEF_TX_EN_LBN 16
2390 #define FRF_AB_GM_EXDEF_TX_EN_WIDTH 1
2391 #define FRF_AB_GM_RTRY_LIMIT_LBN 12
2392 #define FRF_AB_GM_RTRY_LIMIT_WIDTH 4
2393 #define FRF_AB_GM_COL_WIN_LBN 0
2394 #define FRF_AB_GM_COL_WIN_WIDTH 10
2395
2396
2397 /*
2398 * FR_AB_GM_MAX_FLEN_REG(32bit):
2399 * GMAC maximum frame length register
2400 */
2401 #define FR_AB_GM_MAX_FLEN_REG_OFST 0x00000e40
2402 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
2403
2404 #define FRF_AB_GM_MAX_FLEN_LBN 0
2405 #define FRF_AB_GM_MAX_FLEN_WIDTH 16
2406
2407
2408 /*
2409 * FR_AB_GM_TEST_REG(32bit):
2410 * GMAC test register
2411 */
2412 #define FR_AB_GM_TEST_REG_OFST 0x00000e70
2413 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
2414
2415 #define FRF_AB_GM_MAX_BOFF_LBN 3
2416 #define FRF_AB_GM_MAX_BOFF_WIDTH 1
2417 #define FRF_AB_GM_REG_TX_FLOW_EN_LBN 2
2418 #define FRF_AB_GM_REG_TX_FLOW_EN_WIDTH 1
2419 #define FRF_AB_GM_TEST_PAUSE_LBN 1
2420 #define FRF_AB_GM_TEST_PAUSE_WIDTH 1
2421 #define FRF_AB_GM_SHORT_SLOT_LBN 0
2422 #define FRF_AB_GM_SHORT_SLOT_WIDTH 1
2423
2424
2425 /*
2426 * FR_AB_GM_ADR1_REG(32bit):
2427 * GMAC station address register 1
2428 */
2429 #define FR_AB_GM_ADR1_REG_OFST 0x00000f00
2430 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
2431
2432 #define FRF_AB_GM_ADR_B0_LBN 24
2433 #define FRF_AB_GM_ADR_B0_WIDTH 8
2434 #define FRF_AB_GM_ADR_B1_LBN 16
2435 #define FRF_AB_GM_ADR_B1_WIDTH 8
2436 #define FRF_AB_GM_ADR_B2_LBN 8
2437 #define FRF_AB_GM_ADR_B2_WIDTH 8
2438 #define FRF_AB_GM_ADR_B3_LBN 0
2439 #define FRF_AB_GM_ADR_B3_WIDTH 8
2440
2441
2442 /*
2443 * FR_AB_GM_ADR2_REG(32bit):
2444 * GMAC station address register 2
2445 */
2446 #define FR_AB_GM_ADR2_REG_OFST 0x00000f10
2447 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
2448
2449 #define FRF_AB_GM_ADR_B4_LBN 24
2450 #define FRF_AB_GM_ADR_B4_WIDTH 8
2451 #define FRF_AB_GM_ADR_B5_LBN 16
2452 #define FRF_AB_GM_ADR_B5_WIDTH 8
2453
2454
2455 /*
2456 * FR_AB_GMF_CFG0_REG(32bit):
2457 * GMAC FIFO configuration register 0
2458 */
2459 #define FR_AB_GMF_CFG0_REG_OFST 0x00000f20
2460 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
2461
2462 #define FRF_AB_GMF_FTFENRPLY_LBN 20
2463 #define FRF_AB_GMF_FTFENRPLY_WIDTH 1
2464 #define FRF_AB_GMF_STFENRPLY_LBN 19
2465 #define FRF_AB_GMF_STFENRPLY_WIDTH 1
2466 #define FRF_AB_GMF_FRFENRPLY_LBN 18
2467 #define FRF_AB_GMF_FRFENRPLY_WIDTH 1
2468 #define FRF_AB_GMF_SRFENRPLY_LBN 17
2469 #define FRF_AB_GMF_SRFENRPLY_WIDTH 1
2470 #define FRF_AB_GMF_WTMENRPLY_LBN 16
2471 #define FRF_AB_GMF_WTMENRPLY_WIDTH 1
2472 #define FRF_AB_GMF_FTFENREQ_LBN 12
2473 #define FRF_AB_GMF_FTFENREQ_WIDTH 1
2474 #define FRF_AB_GMF_STFENREQ_LBN 11
2475 #define FRF_AB_GMF_STFENREQ_WIDTH 1
2476 #define FRF_AB_GMF_FRFENREQ_LBN 10
2477 #define FRF_AB_GMF_FRFENREQ_WIDTH 1
2478 #define FRF_AB_GMF_SRFENREQ_LBN 9
2479 #define FRF_AB_GMF_SRFENREQ_WIDTH 1
2480 #define FRF_AB_GMF_WTMENREQ_LBN 8
2481 #define FRF_AB_GMF_WTMENREQ_WIDTH 1
2482 #define FRF_AB_GMF_HSTRSTFT_LBN 4
2483 #define FRF_AB_GMF_HSTRSTFT_WIDTH 1
2484 #define FRF_AB_GMF_HSTRSTST_LBN 3
2485 #define FRF_AB_GMF_HSTRSTST_WIDTH 1
2486 #define FRF_AB_GMF_HSTRSTFR_LBN 2
2487 #define FRF_AB_GMF_HSTRSTFR_WIDTH 1
2488 #define FRF_AB_GMF_HSTRSTSR_LBN 1
2489 #define FRF_AB_GMF_HSTRSTSR_WIDTH 1
2490 #define FRF_AB_GMF_HSTRSTWT_LBN 0
2491 #define FRF_AB_GMF_HSTRSTWT_WIDTH 1
2492
2493
2494 /*
2495 * FR_AB_GMF_CFG1_REG(32bit):
2496 * GMAC FIFO configuration register 1
2497 */
2498 #define FR_AB_GMF_CFG1_REG_OFST 0x00000f30
2499 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
2500
2501 #define FRF_AB_GMF_CFGFRTH_LBN 16
2502 #define FRF_AB_GMF_CFGFRTH_WIDTH 5
2503 #define FRF_AB_GMF_CFGXOFFRTX_LBN 0
2504 #define FRF_AB_GMF_CFGXOFFRTX_WIDTH 16
2505
2506
2507 /*
2508 * FR_AB_GMF_CFG2_REG(32bit):
2509 * GMAC FIFO configuration register 2
2510 */
2511 #define FR_AB_GMF_CFG2_REG_OFST 0x00000f40
2512 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
2513
2514 #define FRF_AB_GMF_CFGHWM_LBN 16
2515 #define FRF_AB_GMF_CFGHWM_WIDTH 6
2516 #define FRF_AB_GMF_CFGLWM_LBN 0
2517 #define FRF_AB_GMF_CFGLWM_WIDTH 6
2518
2519
2520 /*
2521 * FR_AB_GMF_CFG3_REG(32bit):
2522 * GMAC FIFO configuration register 3
2523 */
2524 #define FR_AB_GMF_CFG3_REG_OFST 0x00000f50
2525 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
2526
2527 #define FRF_AB_GMF_CFGHWMFT_LBN 16
2528 #define FRF_AB_GMF_CFGHWMFT_WIDTH 6
2529 #define FRF_AB_GMF_CFGFTTH_LBN 0
2530 #define FRF_AB_GMF_CFGFTTH_WIDTH 6
2531
2532
2533 /*
2534 * FR_AB_GMF_CFG4_REG(32bit):
2535 * GMAC FIFO configuration register 4
2536 */
2537 #define FR_AB_GMF_CFG4_REG_OFST 0x00000f60
2538 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
2539
2540 #define FRF_AB_GMF_HSTFLTRFRM_LBN 0
2541 #define FRF_AB_GMF_HSTFLTRFRM_WIDTH 18
2542
2543
2544 /*
2545 * FR_AB_GMF_CFG5_REG(32bit):
2546 * GMAC FIFO configuration register 5
2547 */
2548 #define FR_AB_GMF_CFG5_REG_OFST 0x00000f70
2549 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
2550
2551 #define FRF_AB_GMF_CFGHDPLX_LBN 22
2552 #define FRF_AB_GMF_CFGHDPLX_WIDTH 1
2553 #define FRF_AB_GMF_SRFULL_LBN 21
2554 #define FRF_AB_GMF_SRFULL_WIDTH 1
2555 #define FRF_AB_GMF_HSTSRFULLCLR_LBN 20
2556 #define FRF_AB_GMF_HSTSRFULLCLR_WIDTH 1
2557 #define FRF_AB_GMF_CFGBYTMODE_LBN 19
2558 #define FRF_AB_GMF_CFGBYTMODE_WIDTH 1
2559 #define FRF_AB_GMF_HSTDRPLT64_LBN 18
2560 #define FRF_AB_GMF_HSTDRPLT64_WIDTH 1
2561 #define FRF_AB_GMF_HSTFLTRFRMDC_LBN 0
2562 #define FRF_AB_GMF_HSTFLTRFRMDC_WIDTH 18
2563
2564
2565 /*
2566 * FR_BB_TX_SRC_MAC_TBL(128bit):
2567 * Transmit IP source address filter table
2568 */
2569 #define FR_BB_TX_SRC_MAC_TBL_OFST 0x00001000
2570 /* falconb0=net_func_bar2 */
2571 #define FR_BB_TX_SRC_MAC_TBL_STEP 16
2572 #define FR_BB_TX_SRC_MAC_TBL_ROWS 16
2573
2574 #define FRF_BB_TX_SRC_MAC_ADR_1_LBN 64
2575 #define FRF_BB_TX_SRC_MAC_ADR_1_WIDTH 48
2576 #define FRF_BB_TX_SRC_MAC_ADR_1_DW0_LBN 64
2577 #define FRF_BB_TX_SRC_MAC_ADR_1_DW0_WIDTH 32
2578 #define FRF_BB_TX_SRC_MAC_ADR_1_DW1_LBN 96
2579 #define FRF_BB_TX_SRC_MAC_ADR_1_DW1_WIDTH 16
2580 #define FRF_BB_TX_SRC_MAC_ADR_0_LBN 0
2581 #define FRF_BB_TX_SRC_MAC_ADR_0_WIDTH 48
2582 #define FRF_BB_TX_SRC_MAC_ADR_0_DW0_LBN 0
2583 #define FRF_BB_TX_SRC_MAC_ADR_0_DW0_WIDTH 32
2584 #define FRF_BB_TX_SRC_MAC_ADR_0_DW1_LBN 32
2585 #define FRF_BB_TX_SRC_MAC_ADR_0_DW1_WIDTH 16
2586
2587
2588 /*
2589 * FR_BB_TX_SRC_MAC_CTL_REG(128bit):
2590 * Transmit MAC source address filter control
2591 */
2592 #define FR_BB_TX_SRC_MAC_CTL_REG_OFST 0x00001100
2593 /* falconb0=net_func_bar2 */
2594
2595 #define FRF_BB_TX_SRC_DROP_CTR_LBN 16
2596 #define FRF_BB_TX_SRC_DROP_CTR_WIDTH 16
2597 #define FRF_BB_TX_SRC_FLTR_EN_LBN 15
2598 #define FRF_BB_TX_SRC_FLTR_EN_WIDTH 1
2599 #define FRF_BB_TX_DROP_CTR_CLR_LBN 12
2600 #define FRF_BB_TX_DROP_CTR_CLR_WIDTH 1
2601 #define FRF_BB_TX_MAC_QID_SEL_LBN 0
2602 #define FRF_BB_TX_MAC_QID_SEL_WIDTH 3
2603
2604
2605 /*
2606 * FR_AB_XM_ADR_LO_REG(128bit):
2607 * XGMAC address register low
2608 */
2609 #define FR_AB_XM_ADR_LO_REG_OFST 0x00001200
2610 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
2611
2612 #define FRF_AB_XM_ADR_LO_LBN 0
2613 #define FRF_AB_XM_ADR_LO_WIDTH 32
2614
2615
2616 /*
2617 * FR_AB_XM_ADR_HI_REG(128bit):
2618 * XGMAC address register high
2619 */
2620 #define FR_AB_XM_ADR_HI_REG_OFST 0x00001210
2621 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
2622
2623 #define FRF_AB_XM_ADR_HI_LBN 0
2624 #define FRF_AB_XM_ADR_HI_WIDTH 16
2625
2626
2627 /*
2628 * FR_AB_XM_GLB_CFG_REG(128bit):
2629 * XGMAC global configuration
2630 */
2631 #define FR_AB_XM_GLB_CFG_REG_OFST 0x00001220
2632 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
2633
2634 #define FRF_AB_XM_RMTFLT_GEN_LBN 17
2635 #define FRF_AB_XM_RMTFLT_GEN_WIDTH 1
2636 #define FRF_AB_XM_DEBUG_MODE_LBN 16
2637 #define FRF_AB_XM_DEBUG_MODE_WIDTH 1
2638 #define FRF_AB_XM_RX_STAT_EN_LBN 11
2639 #define FRF_AB_XM_RX_STAT_EN_WIDTH 1
2640 #define FRF_AB_XM_TX_STAT_EN_LBN 10
2641 #define FRF_AB_XM_TX_STAT_EN_WIDTH 1
2642 #define FRF_AB_XM_RX_JUMBO_MODE_LBN 6
2643 #define FRF_AB_XM_RX_JUMBO_MODE_WIDTH 1
2644 #define FRF_AB_XM_WAN_MODE_LBN 5
2645 #define FRF_AB_XM_WAN_MODE_WIDTH 1
2646 #define FRF_AB_XM_INTCLR_MODE_LBN 3
2647 #define FRF_AB_XM_INTCLR_MODE_WIDTH 1
2648 #define FRF_AB_XM_CORE_RST_LBN 0
2649 #define FRF_AB_XM_CORE_RST_WIDTH 1
2650
2651
2652 /*
2653 * FR_AB_XM_TX_CFG_REG(128bit):
2654 * XGMAC transmit configuration
2655 */
2656 #define FR_AB_XM_TX_CFG_REG_OFST 0x00001230
2657 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
2658
2659 #define FRF_AB_XM_TX_PROG_LBN 24
2660 #define FRF_AB_XM_TX_PROG_WIDTH 1
2661 #define FRF_AB_XM_IPG_LBN 16
2662 #define FRF_AB_XM_IPG_WIDTH 4
2663 #define FRF_AB_XM_FCNTL_LBN 10
2664 #define FRF_AB_XM_FCNTL_WIDTH 1
2665 #define FRF_AB_XM_TXCRC_LBN 8
2666 #define FRF_AB_XM_TXCRC_WIDTH 1
2667 #define FRF_AB_XM_EDRC_LBN 6
2668 #define FRF_AB_XM_EDRC_WIDTH 1
2669 #define FRF_AB_XM_AUTO_PAD_LBN 5
2670 #define FRF_AB_XM_AUTO_PAD_WIDTH 1
2671 #define FRF_AB_XM_TX_PRMBL_LBN 2
2672 #define FRF_AB_XM_TX_PRMBL_WIDTH 1
2673 #define FRF_AB_XM_TXEN_LBN 1
2674 #define FRF_AB_XM_TXEN_WIDTH 1
2675 #define FRF_AB_XM_TX_RST_LBN 0
2676 #define FRF_AB_XM_TX_RST_WIDTH 1
2677
2678
2679 /*
2680 * FR_AB_XM_RX_CFG_REG(128bit):
2681 * XGMAC receive configuration
2682 */
2683 #define FR_AB_XM_RX_CFG_REG_OFST 0x00001240
2684 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
2685
2686 #define FRF_AB_XM_PASS_LENERR_LBN 26
2687 #define FRF_AB_XM_PASS_LENERR_WIDTH 1
2688 #define FRF_AB_XM_PASS_CRC_ERR_LBN 25
2689 #define FRF_AB_XM_PASS_CRC_ERR_WIDTH 1
2690 #define FRF_AB_XM_PASS_PRMBLE_ERR_LBN 24
2691 #define FRF_AB_XM_PASS_PRMBLE_ERR_WIDTH 1
2692 #define FRF_AB_XM_REJ_BCAST_LBN 20
2693 #define FRF_AB_XM_REJ_BCAST_WIDTH 1
2694 #define FRF_AB_XM_ACPT_ALL_MCAST_LBN 11
2695 #define FRF_AB_XM_ACPT_ALL_MCAST_WIDTH 1
2696 #define FRF_AB_XM_ACPT_ALL_UCAST_LBN 9
2697 #define FRF_AB_XM_ACPT_ALL_UCAST_WIDTH 1
2698 #define FRF_AB_XM_AUTO_DEPAD_LBN 8
2699 #define FRF_AB_XM_AUTO_DEPAD_WIDTH 1
2700 #define FRF_AB_XM_RXCRC_LBN 3
2701 #define FRF_AB_XM_RXCRC_WIDTH 1
2702 #define FRF_AB_XM_RX_PRMBL_LBN 2
2703 #define FRF_AB_XM_RX_PRMBL_WIDTH 1
2704 #define FRF_AB_XM_RXEN_LBN 1
2705 #define FRF_AB_XM_RXEN_WIDTH 1
2706 #define FRF_AB_XM_RX_RST_LBN 0
2707 #define FRF_AB_XM_RX_RST_WIDTH 1
2708
2709
2710 /*
2711 * FR_AB_XM_MGT_INT_MASK(128bit):
2712 * documentation to be written for sum_XM_MGT_INT_MASK
2713 */
2714 #define FR_AB_XM_MGT_INT_MASK_OFST 0x00001250
2715 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
2716
2717 #define FRF_AB_XM_MSK_STA_INTR_LBN 16
2718 #define FRF_AB_XM_MSK_STA_INTR_WIDTH 1
2719 #define FRF_AB_XM_MSK_STAT_CNTR_HF_LBN 9
2720 #define FRF_AB_XM_MSK_STAT_CNTR_HF_WIDTH 1
2721 #define FRF_AB_XM_MSK_STAT_CNTR_OF_LBN 8
2722 #define FRF_AB_XM_MSK_STAT_CNTR_OF_WIDTH 1
2723 #define FRF_AB_XM_MSK_PRMBLE_ERR_LBN 2
2724 #define FRF_AB_XM_MSK_PRMBLE_ERR_WIDTH 1
2725 #define FRF_AB_XM_MSK_RMTFLT_LBN 1
2726 #define FRF_AB_XM_MSK_RMTFLT_WIDTH 1
2727 #define FRF_AB_XM_MSK_LCLFLT_LBN 0
2728 #define FRF_AB_XM_MSK_LCLFLT_WIDTH 1
2729
2730
2731 /*
2732 * FR_AB_XM_FC_REG(128bit):
2733 * XGMAC flow control register
2734 */
2735 #define FR_AB_XM_FC_REG_OFST 0x00001270
2736 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
2737
2738 #define FRF_AB_XM_PAUSE_TIME_LBN 16
2739 #define FRF_AB_XM_PAUSE_TIME_WIDTH 16
2740 #define FRF_AB_XM_RX_MAC_STAT_LBN 11
2741 #define FRF_AB_XM_RX_MAC_STAT_WIDTH 1
2742 #define FRF_AB_XM_TX_MAC_STAT_LBN 10
2743 #define FRF_AB_XM_TX_MAC_STAT_WIDTH 1
2744 #define FRF_AB_XM_MCNTL_PASS_LBN 8
2745 #define FRF_AB_XM_MCNTL_PASS_WIDTH 2
2746 #define FRF_AB_XM_REJ_CNTL_UCAST_LBN 6
2747 #define FRF_AB_XM_REJ_CNTL_UCAST_WIDTH 1
2748 #define FRF_AB_XM_REJ_CNTL_MCAST_LBN 5
2749 #define FRF_AB_XM_REJ_CNTL_MCAST_WIDTH 1
2750 #define FRF_AB_XM_ZPAUSE_LBN 2
2751 #define FRF_AB_XM_ZPAUSE_WIDTH 1
2752 #define FRF_AB_XM_XMIT_PAUSE_LBN 1
2753 #define FRF_AB_XM_XMIT_PAUSE_WIDTH 1
2754 #define FRF_AB_XM_DIS_FCNTL_LBN 0
2755 #define FRF_AB_XM_DIS_FCNTL_WIDTH 1
2756
2757
2758 /*
2759 * FR_AB_XM_PAUSE_TIME_REG(128bit):
2760 * XGMAC pause time register
2761 */
2762 #define FR_AB_XM_PAUSE_TIME_REG_OFST 0x00001290
2763 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
2764
2765 #define FRF_AB_XM_TX_PAUSE_CNT_LBN 16
2766 #define FRF_AB_XM_TX_PAUSE_CNT_WIDTH 16
2767 #define FRF_AB_XM_RX_PAUSE_CNT_LBN 0
2768 #define FRF_AB_XM_RX_PAUSE_CNT_WIDTH 16
2769
2770
2771 /*
2772 * FR_AB_XM_TX_PARAM_REG(128bit):
2773 * XGMAC transmit parameter register
2774 */
2775 #define FR_AB_XM_TX_PARAM_REG_OFST 0x000012d0
2776 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
2777
2778 #define FRF_AB_XM_TX_JUMBO_MODE_LBN 31
2779 #define FRF_AB_XM_TX_JUMBO_MODE_WIDTH 1
2780 #define FRF_AB_XM_MAX_TX_FRM_SIZE_HI_LBN 19
2781 #define FRF_AB_XM_MAX_TX_FRM_SIZE_HI_WIDTH 11
2782 #define FRF_AB_XM_MAX_TX_FRM_SIZE_LO_LBN 16
2783 #define FRF_AB_XM_MAX_TX_FRM_SIZE_LO_WIDTH 3
2784 #define FRF_AB_XM_PAD_CHAR_LBN 0
2785 #define FRF_AB_XM_PAD_CHAR_WIDTH 8
2786
2787
2788 /*
2789 * FR_AB_XM_RX_PARAM_REG(128bit):
2790 * XGMAC receive parameter register
2791 */
2792 #define FR_AB_XM_RX_PARAM_REG_OFST 0x000012e0
2793 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
2794
2795 #define FRF_AB_XM_MAX_RX_FRM_SIZE_HI_LBN 3
2796 #define FRF_AB_XM_MAX_RX_FRM_SIZE_HI_WIDTH 11
2797 #define FRF_AB_XM_MAX_RX_FRM_SIZE_LO_LBN 0
2798 #define FRF_AB_XM_MAX_RX_FRM_SIZE_LO_WIDTH 3
2799
2800
2801 /*
2802 * FR_AB_XM_MGT_INT_MSK_REG(128bit):
2803 * XGMAC management interrupt mask register
2804 */
2805 #define FR_AB_XM_MGT_INT_REG_OFST 0x000012f0
2806 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
2807
2808 #define FRF_AB_XM_STAT_CNTR_OF_LBN 9
2809 #define FRF_AB_XM_STAT_CNTR_OF_WIDTH 1
2810 #define FRF_AB_XM_STAT_CNTR_HF_LBN 8
2811 #define FRF_AB_XM_STAT_CNTR_HF_WIDTH 1
2812 #define FRF_AB_XM_PRMBLE_ERR_LBN 2
2813 #define FRF_AB_XM_PRMBLE_ERR_WIDTH 1
2814 #define FRF_AB_XM_RMTFLT_LBN 1
2815 #define FRF_AB_XM_RMTFLT_WIDTH 1
2816 #define FRF_AB_XM_LCLFLT_LBN 0
2817 #define FRF_AB_XM_LCLFLT_WIDTH 1
2818
2819
2820 /*
2821 * FR_AB_XX_PWR_RST_REG(128bit):
2822 * XGXS/XAUI powerdown/reset register
2823 */
2824 #define FR_AB_XX_PWR_RST_REG_OFST 0x00001300
2825 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
2826
2827 #define FRF_AB_XX_PWRDND_SIG_LBN 31
2828 #define FRF_AB_XX_PWRDND_SIG_WIDTH 1
2829 #define FRF_AB_XX_PWRDNC_SIG_LBN 30
2830 #define FRF_AB_XX_PWRDNC_SIG_WIDTH 1
2831 #define FRF_AB_XX_PWRDNB_SIG_LBN 29
2832 #define FRF_AB_XX_PWRDNB_SIG_WIDTH 1
2833 #define FRF_AB_XX_PWRDNA_SIG_LBN 28
2834 #define FRF_AB_XX_PWRDNA_SIG_WIDTH 1
2835 #define FRF_AB_XX_SIM_MODE_LBN 27
2836 #define FRF_AB_XX_SIM_MODE_WIDTH 1
2837 #define FRF_AB_XX_RSTPLLCD_SIG_LBN 25
2838 #define FRF_AB_XX_RSTPLLCD_SIG_WIDTH 1
2839 #define FRF_AB_XX_RSTPLLAB_SIG_LBN 24
2840 #define FRF_AB_XX_RSTPLLAB_SIG_WIDTH 1
2841 #define FRF_AB_XX_RESETD_SIG_LBN 23
2842 #define FRF_AB_XX_RESETD_SIG_WIDTH 1
2843 #define FRF_AB_XX_RESETC_SIG_LBN 22
2844 #define FRF_AB_XX_RESETC_SIG_WIDTH 1
2845 #define FRF_AB_XX_RESETB_SIG_LBN 21
2846 #define FRF_AB_XX_RESETB_SIG_WIDTH 1
2847 #define FRF_AB_XX_RESETA_SIG_LBN 20
2848 #define FRF_AB_XX_RESETA_SIG_WIDTH 1
2849 #define FRF_AB_XX_RSTXGXSRX_SIG_LBN 18
2850 #define FRF_AB_XX_RSTXGXSRX_SIG_WIDTH 1
2851 #define FRF_AB_XX_RSTXGXSTX_SIG_LBN 17
2852 #define FRF_AB_XX_RSTXGXSTX_SIG_WIDTH 1
2853 #define FRF_AB_XX_SD_RST_ACT_LBN 16
2854 #define FRF_AB_XX_SD_RST_ACT_WIDTH 1
2855 #define FRF_AB_XX_PWRDND_EN_LBN 15
2856 #define FRF_AB_XX_PWRDND_EN_WIDTH 1
2857 #define FRF_AB_XX_PWRDNC_EN_LBN 14
2858 #define FRF_AB_XX_PWRDNC_EN_WIDTH 1
2859 #define FRF_AB_XX_PWRDNB_EN_LBN 13
2860 #define FRF_AB_XX_PWRDNB_EN_WIDTH 1
2861 #define FRF_AB_XX_PWRDNA_EN_LBN 12
2862 #define FRF_AB_XX_PWRDNA_EN_WIDTH 1
2863 #define FRF_AB_XX_RSTPLLCD_EN_LBN 9
2864 #define FRF_AB_XX_RSTPLLCD_EN_WIDTH 1
2865 #define FRF_AB_XX_RSTPLLAB_EN_LBN 8
2866 #define FRF_AB_XX_RSTPLLAB_EN_WIDTH 1
2867 #define FRF_AB_XX_RESETD_EN_LBN 7
2868 #define FRF_AB_XX_RESETD_EN_WIDTH 1
2869 #define FRF_AB_XX_RESETC_EN_LBN 6
2870 #define FRF_AB_XX_RESETC_EN_WIDTH 1
2871 #define FRF_AB_XX_RESETB_EN_LBN 5
2872 #define FRF_AB_XX_RESETB_EN_WIDTH 1
2873 #define FRF_AB_XX_RESETA_EN_LBN 4
2874 #define FRF_AB_XX_RESETA_EN_WIDTH 1
2875 #define FRF_AB_XX_RSTXGXSRX_EN_LBN 2
2876 #define FRF_AB_XX_RSTXGXSRX_EN_WIDTH 1
2877 #define FRF_AB_XX_RSTXGXSTX_EN_LBN 1
2878 #define FRF_AB_XX_RSTXGXSTX_EN_WIDTH 1
2879 #define FRF_AB_XX_RST_XX_EN_LBN 0
2880 #define FRF_AB_XX_RST_XX_EN_WIDTH 1
2881
2882
2883 /*
2884 * FR_AB_XX_SD_CTL_REG(128bit):
2885 * XGXS/XAUI powerdown/reset control register
2886 */
2887 #define FR_AB_XX_SD_CTL_REG_OFST 0x00001310
2888 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
2889
2890 #define FRF_AB_XX_TERMADJ1_LBN 17
2891 #define FRF_AB_XX_TERMADJ1_WIDTH 1
2892 #define FRF_AB_XX_TERMADJ0_LBN 16
2893 #define FRF_AB_XX_TERMADJ0_WIDTH 1
2894 #define FRF_AB_XX_HIDRVD_LBN 15
2895 #define FRF_AB_XX_HIDRVD_WIDTH 1
2896 #define FRF_AB_XX_LODRVD_LBN 14
2897 #define FRF_AB_XX_LODRVD_WIDTH 1
2898 #define FRF_AB_XX_HIDRVC_LBN 13
2899 #define FRF_AB_XX_HIDRVC_WIDTH 1
2900 #define FRF_AB_XX_LODRVC_LBN 12
2901 #define FRF_AB_XX_LODRVC_WIDTH 1
2902 #define FRF_AB_XX_HIDRVB_LBN 11
2903 #define FRF_AB_XX_HIDRVB_WIDTH 1
2904 #define FRF_AB_XX_LODRVB_LBN 10
2905 #define FRF_AB_XX_LODRVB_WIDTH 1
2906 #define FRF_AB_XX_HIDRVA_LBN 9
2907 #define FRF_AB_XX_HIDRVA_WIDTH 1
2908 #define FRF_AB_XX_LODRVA_LBN 8
2909 #define FRF_AB_XX_LODRVA_WIDTH 1
2910 #define FRF_AB_XX_LPBKD_LBN 3
2911 #define FRF_AB_XX_LPBKD_WIDTH 1
2912 #define FRF_AB_XX_LPBKC_LBN 2
2913 #define FRF_AB_XX_LPBKC_WIDTH 1
2914 #define FRF_AB_XX_LPBKB_LBN 1
2915 #define FRF_AB_XX_LPBKB_WIDTH 1
2916 #define FRF_AB_XX_LPBKA_LBN 0
2917 #define FRF_AB_XX_LPBKA_WIDTH 1
2918
2919
2920 /*
2921 * FR_AB_XX_TXDRV_CTL_REG(128bit):
2922 * XAUI SerDes transmit drive control register
2923 */
2924 #define FR_AB_XX_TXDRV_CTL_REG_OFST 0x00001320
2925 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
2926
2927 #define FRF_AB_XX_DEQD_LBN 28
2928 #define FRF_AB_XX_DEQD_WIDTH 4
2929 #define FRF_AB_XX_DEQC_LBN 24
2930 #define FRF_AB_XX_DEQC_WIDTH 4
2931 #define FRF_AB_XX_DEQB_LBN 20
2932 #define FRF_AB_XX_DEQB_WIDTH 4
2933 #define FRF_AB_XX_DEQA_LBN 16
2934 #define FRF_AB_XX_DEQA_WIDTH 4
2935 #define FRF_AB_XX_DTXD_LBN 12
2936 #define FRF_AB_XX_DTXD_WIDTH 4
2937 #define FRF_AB_XX_DTXC_LBN 8
2938 #define FRF_AB_XX_DTXC_WIDTH 4
2939 #define FRF_AB_XX_DTXB_LBN 4
2940 #define FRF_AB_XX_DTXB_WIDTH 4
2941 #define FRF_AB_XX_DTXA_LBN 0
2942 #define FRF_AB_XX_DTXA_WIDTH 4
2943
2944
2945 /*
2946 * FR_AB_XX_PRBS_CTL_REG(128bit):
2947 * documentation to be written for sum_XX_PRBS_CTL_REG
2948 */
2949 #define FR_AB_XX_PRBS_CTL_REG_OFST 0x00001330
2950 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
2951
2952 #define FRF_AB_XX_CH3_RX_PRBS_SEL_LBN 30
2953 #define FRF_AB_XX_CH3_RX_PRBS_SEL_WIDTH 2
2954 #define FRF_AB_XX_CH3_RX_PRBS_INV_LBN 29
2955 #define FRF_AB_XX_CH3_RX_PRBS_INV_WIDTH 1
2956 #define FRF_AB_XX_CH3_RX_PRBS_CHKEN_LBN 28
2957 #define FRF_AB_XX_CH3_RX_PRBS_CHKEN_WIDTH 1
2958 #define FRF_AB_XX_CH2_RX_PRBS_SEL_LBN 26
2959 #define FRF_AB_XX_CH2_RX_PRBS_SEL_WIDTH 2
2960 #define FRF_AB_XX_CH2_RX_PRBS_INV_LBN 25
2961 #define FRF_AB_XX_CH2_RX_PRBS_INV_WIDTH 1
2962 #define FRF_AB_XX_CH2_RX_PRBS_CHKEN_LBN 24
2963 #define FRF_AB_XX_CH2_RX_PRBS_CHKEN_WIDTH 1
2964 #define FRF_AB_XX_CH1_RX_PRBS_SEL_LBN 22
2965 #define FRF_AB_XX_CH1_RX_PRBS_SEL_WIDTH 2
2966 #define FRF_AB_XX_CH1_RX_PRBS_INV_LBN 21
2967 #define FRF_AB_XX_CH1_RX_PRBS_INV_WIDTH 1
2968 #define FRF_AB_XX_CH1_RX_PRBS_CHKEN_LBN 20
2969 #define FRF_AB_XX_CH1_RX_PRBS_CHKEN_WIDTH 1
2970 #define FRF_AB_XX_CH0_RX_PRBS_SEL_LBN 18
2971 #define FRF_AB_XX_CH0_RX_PRBS_SEL_WIDTH 2
2972 #define FRF_AB_XX_CH0_RX_PRBS_INV_LBN 17
2973 #define FRF_AB_XX_CH0_RX_PRBS_INV_WIDTH 1
2974 #define FRF_AB_XX_CH0_RX_PRBS_CHKEN_LBN 16
2975 #define FRF_AB_XX_CH0_RX_PRBS_CHKEN_WIDTH 1
2976 #define FRF_AB_XX_CH3_TX_PRBS_SEL_LBN 14
2977 #define FRF_AB_XX_CH3_TX_PRBS_SEL_WIDTH 2
2978 #define FRF_AB_XX_CH3_TX_PRBS_INV_LBN 13
2979 #define FRF_AB_XX_CH3_TX_PRBS_INV_WIDTH 1
2980 #define FRF_AB_XX_CH3_TX_PRBS_CHKEN_LBN 12
2981 #define FRF_AB_XX_CH3_TX_PRBS_CHKEN_WIDTH 1
2982 #define FRF_AB_XX_CH2_TX_PRBS_SEL_LBN 10
2983 #define FRF_AB_XX_CH2_TX_PRBS_SEL_WIDTH 2
2984 #define FRF_AB_XX_CH2_TX_PRBS_INV_LBN 9
2985 #define FRF_AB_XX_CH2_TX_PRBS_INV_WIDTH 1
2986 #define FRF_AB_XX_CH2_TX_PRBS_CHKEN_LBN 8
2987 #define FRF_AB_XX_CH2_TX_PRBS_CHKEN_WIDTH 1
2988 #define FRF_AB_XX_CH1_TX_PRBS_SEL_LBN 6
2989 #define FRF_AB_XX_CH1_TX_PRBS_SEL_WIDTH 2
2990 #define FRF_AB_XX_CH1_TX_PRBS_INV_LBN 5
2991 #define FRF_AB_XX_CH1_TX_PRBS_INV_WIDTH 1
2992 #define FRF_AB_XX_CH1_TX_PRBS_CHKEN_LBN 4
2993 #define FRF_AB_XX_CH1_TX_PRBS_CHKEN_WIDTH 1
2994 #define FRF_AB_XX_CH0_TX_PRBS_SEL_LBN 2
2995 #define FRF_AB_XX_CH0_TX_PRBS_SEL_WIDTH 2
2996 #define FRF_AB_XX_CH0_TX_PRBS_INV_LBN 1
2997 #define FRF_AB_XX_CH0_TX_PRBS_INV_WIDTH 1
2998 #define FRF_AB_XX_CH0_TX_PRBS_CHKEN_LBN 0
2999 #define FRF_AB_XX_CH0_TX_PRBS_CHKEN_WIDTH 1
3000
3001
3002 /*
3003 * FR_AB_XX_PRBS_CHK_REG(128bit):
3004 * documentation to be written for sum_XX_PRBS_CHK_REG
3005 */
3006 #define FR_AB_XX_PRBS_CHK_REG_OFST 0x00001340
3007 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
3008
3009 #define FRF_AB_XX_REV_LB_EN_LBN 16
3010 #define FRF_AB_XX_REV_LB_EN_WIDTH 1
3011 #define FRF_AB_XX_CH3_DEG_DET_LBN 15
3012 #define FRF_AB_XX_CH3_DEG_DET_WIDTH 1
3013 #define FRF_AB_XX_CH3_LFSR_LOCK_IND_LBN 14
3014 #define FRF_AB_XX_CH3_LFSR_LOCK_IND_WIDTH 1
3015 #define FRF_AB_XX_CH3_PRBS_FRUN_LBN 13
3016 #define FRF_AB_XX_CH3_PRBS_FRUN_WIDTH 1
3017 #define FRF_AB_XX_CH3_ERR_CHK_LBN 12
3018 #define FRF_AB_XX_CH3_ERR_CHK_WIDTH 1
3019 #define FRF_AB_XX_CH2_DEG_DET_LBN 11
3020 #define FRF_AB_XX_CH2_DEG_DET_WIDTH 1
3021 #define FRF_AB_XX_CH2_LFSR_LOCK_IND_LBN 10
3022 #define FRF_AB_XX_CH2_LFSR_LOCK_IND_WIDTH 1
3023 #define FRF_AB_XX_CH2_PRBS_FRUN_LBN 9
3024 #define FRF_AB_XX_CH2_PRBS_FRUN_WIDTH 1
3025 #define FRF_AB_XX_CH2_ERR_CHK_LBN 8
3026 #define FRF_AB_XX_CH2_ERR_CHK_WIDTH 1
3027 #define FRF_AB_XX_CH1_DEG_DET_LBN 7
3028 #define FRF_AB_XX_CH1_DEG_DET_WIDTH 1
3029 #define FRF_AB_XX_CH1_LFSR_LOCK_IND_LBN 6
3030 #define FRF_AB_XX_CH1_LFSR_LOCK_IND_WIDTH 1
3031 #define FRF_AB_XX_CH1_PRBS_FRUN_LBN 5
3032 #define FRF_AB_XX_CH1_PRBS_FRUN_WIDTH 1
3033 #define FRF_AB_XX_CH1_ERR_CHK_LBN 4
3034 #define FRF_AB_XX_CH1_ERR_CHK_WIDTH 1
3035 #define FRF_AB_XX_CH0_DEG_DET_LBN 3
3036 #define FRF_AB_XX_CH0_DEG_DET_WIDTH 1
3037 #define FRF_AB_XX_CH0_LFSR_LOCK_IND_LBN 2
3038 #define FRF_AB_XX_CH0_LFSR_LOCK_IND_WIDTH 1
3039 #define FRF_AB_XX_CH0_PRBS_FRUN_LBN 1
3040 #define FRF_AB_XX_CH0_PRBS_FRUN_WIDTH 1
3041 #define FRF_AB_XX_CH0_ERR_CHK_LBN 0
3042 #define FRF_AB_XX_CH0_ERR_CHK_WIDTH 1
3043
3044
3045 /*
3046 * FR_AB_XX_PRBS_ERR_REG(128bit):
3047 * documentation to be written for sum_XX_PRBS_ERR_REG
3048 */
3049 #define FR_AB_XX_PRBS_ERR_REG_OFST 0x00001350
3050 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
3051
3052 #define FRF_AB_XX_CH3_PRBS_ERR_CNT_LBN 24
3053 #define FRF_AB_XX_CH3_PRBS_ERR_CNT_WIDTH 8
3054 #define FRF_AB_XX_CH2_PRBS_ERR_CNT_LBN 16
3055 #define FRF_AB_XX_CH2_PRBS_ERR_CNT_WIDTH 8
3056 #define FRF_AB_XX_CH1_PRBS_ERR_CNT_LBN 8
3057 #define FRF_AB_XX_CH1_PRBS_ERR_CNT_WIDTH 8
3058 #define FRF_AB_XX_CH0_PRBS_ERR_CNT_LBN 0
3059 #define FRF_AB_XX_CH0_PRBS_ERR_CNT_WIDTH 8
3060
3061
3062 /*
3063 * FR_AB_XX_CORE_STAT_REG(128bit):
3064 * XAUI XGXS core status register
3065 */
3066 #define FR_AB_XX_CORE_STAT_REG_OFST 0x00001360
3067 /* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
3068
3069 #define FRF_AB_XX_FORCE_SIG3_LBN 31
3070 #define FRF_AB_XX_FORCE_SIG3_WIDTH 1
3071 #define FRF_AB_XX_FORCE_SIG3_VAL_LBN 30
3072 #define FRF_AB_XX_FORCE_SIG3_VAL_WIDTH 1
3073 #define FRF_AB_XX_FORCE_SIG2_LBN 29
3074 #define FRF_AB_XX_FORCE_SIG2_WIDTH 1
3075 #define FRF_AB_XX_FORCE_SIG2_VAL_LBN 28
3076 #define FRF_AB_XX_FORCE_SIG2_VAL_WIDTH 1
3077 #define FRF_AB_XX_FORCE_SIG1_LBN 27
3078 #define FRF_AB_XX_FORCE_SIG1_WIDTH 1
3079 #define FRF_AB_XX_FORCE_SIG1_VAL_LBN 26
3080 #define FRF_AB_XX_FORCE_SIG1_VAL_WIDTH 1
3081 #define FRF_AB_XX_FORCE_SIG0_LBN 25
3082 #define FRF_AB_XX_FORCE_SIG0_WIDTH 1
3083 #define FRF_AB_XX_FORCE_SIG0_VAL_LBN 24
3084 #define FRF_AB_XX_FORCE_SIG0_VAL_WIDTH 1
3085 #define FRF_AB_XX_XGXS_LB_EN_LBN 23
3086 #define FRF_AB_XX_XGXS_LB_EN_WIDTH 1
3087 #define FRF_AB_XX_XGMII_LB_EN_LBN 22
3088 #define FRF_AB_XX_XGMII_LB_EN_WIDTH 1
3089 #define FRF_AB_XX_MATCH_FAULT_LBN 21
3090 #define FRF_AB_XX_MATCH_FAULT_WIDTH 1
3091 #define FRF_AB_XX_ALIGN_DONE_LBN 20
3092 #define FRF_AB_XX_ALIGN_DONE_WIDTH 1
3093 #define FRF_AB_XX_SYNC_STAT3_LBN 19
3094 #define FRF_AB_XX_SYNC_STAT3_WIDTH 1
3095 #define FRF_AB_XX_SYNC_STAT2_LBN 18
3096 #define FRF_AB_XX_SYNC_STAT2_WIDTH 1
3097 #define FRF_AB_XX_SYNC_STAT1_LBN 17
3098 #define FRF_AB_XX_SYNC_STAT1_WIDTH 1
3099 #define FRF_AB_XX_SYNC_STAT0_LBN 16
3100 #define FRF_AB_XX_SYNC_STAT0_WIDTH 1
3101 #define FRF_AB_XX_COMMA_DET_CH3_LBN 15
3102 #define FRF_AB_XX_COMMA_DET_CH3_WIDTH 1
3103 #define FRF_AB_XX_COMMA_DET_CH2_LBN 14
3104 #define FRF_AB_XX_COMMA_DET_CH2_WIDTH 1
3105 #define FRF_AB_XX_COMMA_DET_CH1_LBN 13
3106 #define FRF_AB_XX_COMMA_DET_CH1_WIDTH 1
3107 #define FRF_AB_XX_COMMA_DET_CH0_LBN 12
3108 #define FRF_AB_XX_COMMA_DET_CH0_WIDTH 1
3109 #define FRF_AB_XX_CGRP_ALIGN_CH3_LBN 11
3110 #define FRF_AB_XX_CGRP_ALIGN_CH3_WIDTH 1
3111 #define FRF_AB_XX_CGRP_ALIGN_CH2_LBN 10
3112 #define FRF_AB_XX_CGRP_ALIGN_CH2_WIDTH 1
3113 #define FRF_AB_XX_CGRP_ALIGN_CH1_LBN 9
3114 #define FRF_AB_XX_CGRP_ALIGN_CH1_WIDTH 1
3115 #define FRF_AB_XX_CGRP_ALIGN_CH0_LBN 8
3116 #define FRF_AB_XX_CGRP_ALIGN_CH0_WIDTH 1
3117 #define FRF_AB_XX_CHAR_ERR_CH3_LBN 7
3118 #define FRF_AB_XX_CHAR_ERR_CH3_WIDTH 1
3119 #define FRF_AB_XX_CHAR_ERR_CH2_LBN 6
3120 #define FRF_AB_XX_CHAR_ERR_CH2_WIDTH 1
3121 #define FRF_AB_XX_CHAR_ERR_CH1_LBN 5
3122 #define FRF_AB_XX_CHAR_ERR_CH1_WIDTH 1
3123 #define FRF_AB_XX_CHAR_ERR_CH0_LBN 4
3124 #define FRF_AB_XX_CHAR_ERR_CH0_WIDTH 1
3125 #define FRF_AB_XX_DISPERR_CH3_LBN 3
3126 #define FRF_AB_XX_DISPERR_CH3_WIDTH 1
3127 #define FRF_AB_XX_DISPERR_CH2_LBN 2
3128 #define FRF_AB_XX_DISPERR_CH2_WIDTH 1
3129 #define FRF_AB_XX_DISPERR_CH1_LBN 1
3130 #define FRF_AB_XX_DISPERR_CH1_WIDTH 1
3131 #define FRF_AB_XX_DISPERR_CH0_LBN 0
3132 #define FRF_AB_XX_DISPERR_CH0_WIDTH 1
3133
3134
3135 /*
3136 * FR_AA_RX_DESC_PTR_TBL_KER(128bit):
3137 * Receive descriptor pointer table
3138 */
3139 #define FR_AA_RX_DESC_PTR_TBL_KER_OFST 0x00011800
3140 /* falcona0=net_func_bar2 */
3141 #define FR_AA_RX_DESC_PTR_TBL_KER_STEP 16
3142 #define FR_AA_RX_DESC_PTR_TBL_KER_ROWS 4
3143 /*
3144 * FR_AZ_RX_DESC_PTR_TBL(128bit):
3145 * Receive descriptor pointer table
3146 */
3147 #define FR_AZ_RX_DESC_PTR_TBL_OFST 0x00f40000
3148 /* sienaa0=net_func_bar2,falconb0=net_func_bar2,falcona0=char_func_bar0 */
3149 #define FR_AZ_RX_DESC_PTR_TBL_STEP 16
3150 #define FR_CZ_RX_DESC_PTR_TBL_ROWS 1024
3151 #define FR_AB_RX_DESC_PTR_TBL_ROWS 4096
3152
3153 #define FRF_CZ_RX_HDR_SPLIT_LBN 90
3154 #define FRF_CZ_RX_HDR_SPLIT_WIDTH 1
3155 #define FRF_AZ_RX_RESET_LBN 89
3156 #define FRF_AZ_RX_RESET_WIDTH 1
3157 #define FRF_AZ_RX_ISCSI_DDIG_EN_LBN 88
3158 #define FRF_AZ_RX_ISCSI_DDIG_EN_WIDTH 1
3159 #define FRF_AZ_RX_ISCSI_HDIG_EN_LBN 87
3160 #define FRF_AZ_RX_ISCSI_HDIG_EN_WIDTH 1
3161 #define FRF_AZ_RX_DESC_PREF_ACT_LBN 86
3162 #define FRF_AZ_RX_DESC_PREF_ACT_WIDTH 1
3163 #define FRF_AZ_RX_DC_HW_RPTR_LBN 80
3164 #define FRF_AZ_RX_DC_HW_RPTR_WIDTH 6
3165 #define FRF_AZ_RX_DESCQ_HW_RPTR_LBN 68
3166 #define FRF_AZ_RX_DESCQ_HW_RPTR_WIDTH 12
3167 #define FRF_AZ_RX_DESCQ_SW_WPTR_LBN 56
3168 #define FRF_AZ_RX_DESCQ_SW_WPTR_WIDTH 12
3169 #define FRF_AZ_RX_DESCQ_BUF_BASE_ID_LBN 36
3170 #define FRF_AZ_RX_DESCQ_BUF_BASE_ID_WIDTH 20
3171 #define FRF_AZ_RX_DESCQ_EVQ_ID_LBN 24
3172 #define FRF_AZ_RX_DESCQ_EVQ_ID_WIDTH 12
3173 #define FRF_AZ_RX_DESCQ_OWNER_ID_LBN 10
3174 #define FRF_AZ_RX_DESCQ_OWNER_ID_WIDTH 14
3175 #define FRF_AZ_RX_DESCQ_LABEL_LBN 5
3176 #define FRF_AZ_RX_DESCQ_LABEL_WIDTH 5
3177 #define FRF_AZ_RX_DESCQ_SIZE_LBN 3
3178 #define FRF_AZ_RX_DESCQ_SIZE_WIDTH 2
3179 #define FFE_AZ_RX_DESCQ_SIZE_4K 3
3180 #define FFE_AZ_RX_DESCQ_SIZE_2K 2
3181 #define FFE_AZ_RX_DESCQ_SIZE_1K 1
3182 #define FFE_AZ_RX_DESCQ_SIZE_512 0
3183 #define FRF_AZ_RX_DESCQ_TYPE_LBN 2
3184 #define FRF_AZ_RX_DESCQ_TYPE_WIDTH 1
3185 #define FRF_AZ_RX_DESCQ_JUMBO_LBN 1
3186 #define FRF_AZ_RX_DESCQ_JUMBO_WIDTH 1
3187 #define FRF_AZ_RX_DESCQ_EN_LBN 0
3188 #define FRF_AZ_RX_DESCQ_EN_WIDTH 1
3189
3190
3191 /*
3192 * FR_AA_TX_DESC_PTR_TBL_KER(128bit):
3193 * Transmit descriptor pointer
3194 */
3195 #define FR_AA_TX_DESC_PTR_TBL_KER_OFST 0x00011900
3196 /* falcona0=net_func_bar2 */
3197 #define FR_AA_TX_DESC_PTR_TBL_KER_STEP 16
3198 #define FR_AA_TX_DESC_PTR_TBL_KER_ROWS 8
3199 /*
3200 * FR_AZ_TX_DESC_PTR_TBL(128bit):
3201 * Transmit descriptor pointer
3202 */
3203 #define FR_AZ_TX_DESC_PTR_TBL_OFST 0x00f50000
3204 /* falconb0=net_func_bar2,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
3205 #define FR_AZ_TX_DESC_PTR_TBL_STEP 16
3206 #define FR_AB_TX_DESC_PTR_TBL_ROWS 4096
3207 #define FR_CZ_TX_DESC_PTR_TBL_ROWS 1024
3208
3209 #define FRF_CZ_TX_DPT_Q_MASK_WIDTH_LBN 94
3210 #define FRF_CZ_TX_DPT_Q_MASK_WIDTH_WIDTH 2
3211 #define FRF_CZ_TX_DPT_ETH_FILT_EN_LBN 93
3212 #define FRF_CZ_TX_DPT_ETH_FILT_EN_WIDTH 1
3213 #define FRF_CZ_TX_DPT_IP_FILT_EN_LBN 92
3214 #define FRF_CZ_TX_DPT_IP_FILT_EN_WIDTH 1
3215 #define FRF_BZ_TX_NON_IP_DROP_DIS_LBN 91
3216 #define FRF_BZ_TX_NON_IP_DROP_DIS_WIDTH 1
3217 #define FRF_BZ_TX_IP_CHKSM_DIS_LBN 90
3218 #define FRF_BZ_TX_IP_CHKSM_DIS_WIDTH 1
3219 #define FRF_BZ_TX_TCP_CHKSM_DIS_LBN 89
3220 #define FRF_BZ_TX_TCP_CHKSM_DIS_WIDTH 1
3221 #define FRF_AZ_TX_DESCQ_EN_LBN 88
3222 #define FRF_AZ_TX_DESCQ_EN_WIDTH 1
3223 #define FRF_AZ_TX_ISCSI_DDIG_EN_LBN 87
3224 #define FRF_AZ_TX_ISCSI_DDIG_EN_WIDTH 1
3225 #define FRF_AZ_TX_ISCSI_HDIG_EN_LBN 86
3226 #define FRF_AZ_TX_ISCSI_HDIG_EN_WIDTH 1
3227 #define FRF_AZ_TX_DC_HW_RPTR_LBN 80
3228 #define FRF_AZ_TX_DC_HW_RPTR_WIDTH 6
3229 #define FRF_AZ_TX_DESCQ_HW_RPTR_LBN 68
3230 #define FRF_AZ_TX_DESCQ_HW_RPTR_WIDTH 12
3231 #define FRF_AZ_TX_DESCQ_SW_WPTR_LBN 56
3232 #define FRF_AZ_TX_DESCQ_SW_WPTR_WIDTH 12
3233 #define FRF_AZ_TX_DESCQ_BUF_BASE_ID_LBN 36
3234 #define FRF_AZ_TX_DESCQ_BUF_BASE_ID_WIDTH 20
3235 #define FRF_AZ_TX_DESCQ_EVQ_ID_LBN 24
3236 #define FRF_AZ_TX_DESCQ_EVQ_ID_WIDTH 12
3237 #define FRF_AZ_TX_DESCQ_OWNER_ID_LBN 10
3238 #define FRF_AZ_TX_DESCQ_OWNER_ID_WIDTH 14
3239 #define FRF_AZ_TX_DESCQ_LABEL_LBN 5
3240 #define FRF_AZ_TX_DESCQ_LABEL_WIDTH 5
3241 #define FRF_AZ_TX_DESCQ_SIZE_LBN 3
3242 #define FRF_AZ_TX_DESCQ_SIZE_WIDTH 2
3243 #define FFE_AZ_TX_DESCQ_SIZE_4K 3
3244 #define FFE_AZ_TX_DESCQ_SIZE_2K 2
3245 #define FFE_AZ_TX_DESCQ_SIZE_1K 1
3246 #define FFE_AZ_TX_DESCQ_SIZE_512 0
3247 #define FRF_AZ_TX_DESCQ_TYPE_LBN 1
3248 #define FRF_AZ_TX_DESCQ_TYPE_WIDTH 2
3249 #define FRF_AZ_TX_DESCQ_FLUSH_LBN 0
3250 #define FRF_AZ_TX_DESCQ_FLUSH_WIDTH 1
3251
3252
3253 /*
3254 * FR_AA_EVQ_PTR_TBL_KER(128bit):
3255 * Event queue pointer table
3256 */
3257 #define FR_AA_EVQ_PTR_TBL_KER_OFST 0x00011a00
3258 /* falcona0=net_func_bar2 */
3259 #define FR_AA_EVQ_PTR_TBL_KER_STEP 16
3260 #define FR_AA_EVQ_PTR_TBL_KER_ROWS 4
3261 /*
3262 * FR_AZ_EVQ_PTR_TBL(128bit):
3263 * Event queue pointer table
3264 */
3265 #define FR_AZ_EVQ_PTR_TBL_OFST 0x00f60000
3266 /* sienaa0=net_func_bar2,falconb0=net_func_bar2,falcona0=char_func_bar0 */
3267 #define FR_AZ_EVQ_PTR_TBL_STEP 16
3268 #define FR_CZ_EVQ_PTR_TBL_ROWS 1024
3269 #define FR_AB_EVQ_PTR_TBL_ROWS 4096
3270
3271 #define FRF_BZ_EVQ_RPTR_IGN_LBN 40
3272 #define FRF_BZ_EVQ_RPTR_IGN_WIDTH 1
3273 #define FRF_AZ_EVQ_WKUP_OR_INT_EN_LBN 39
3274 #define FRF_AZ_EVQ_WKUP_OR_INT_EN_WIDTH 1
3275 #define FRF_AZ_EVQ_NXT_WPTR_LBN 24
3276 #define FRF_AZ_EVQ_NXT_WPTR_WIDTH 15
3277 #define FRF_AZ_EVQ_EN_LBN 23
3278 #define FRF_AZ_EVQ_EN_WIDTH 1
3279 #define FRF_AZ_EVQ_SIZE_LBN 20
3280 #define FRF_AZ_EVQ_SIZE_WIDTH 3
3281 #define FFE_AZ_EVQ_SIZE_32K 6
3282 #define FFE_AZ_EVQ_SIZE_16K 5
3283 #define FFE_AZ_EVQ_SIZE_8K 4
3284 #define FFE_AZ_EVQ_SIZE_4K 3
3285 #define FFE_AZ_EVQ_SIZE_2K 2
3286 #define FFE_AZ_EVQ_SIZE_1K 1
3287 #define FFE_AZ_EVQ_SIZE_512 0
3288 #define FRF_AZ_EVQ_BUF_BASE_ID_LBN 0
3289 #define FRF_AZ_EVQ_BUF_BASE_ID_WIDTH 20
3290
3291
3292 /*
3293 * FR_AA_BUF_HALF_TBL_KER(64bit):
3294 * Buffer table in half buffer table mode direct access by driver
3295 */
3296 #define FR_AA_BUF_HALF_TBL_KER_OFST 0x00018000
3297 /* falcona0=net_func_bar2 */
3298 #define FR_AA_BUF_HALF_TBL_KER_STEP 8
3299 #define FR_AA_BUF_HALF_TBL_KER_ROWS 4096
3300 /*
3301 * FR_AZ_BUF_HALF_TBL(64bit):
3302 * Buffer table in half buffer table mode direct access by driver
3303 */
3304 #define FR_AZ_BUF_HALF_TBL_OFST 0x00800000
3305 /* sienaa0=net_func_bar2,falconb0=net_func_bar2,falcona0=char_func_bar0 */
3306 #define FR_AZ_BUF_HALF_TBL_STEP 8
3307 #define FR_CZ_BUF_HALF_TBL_ROWS 147456
3308 #define FR_AB_BUF_HALF_TBL_ROWS 524288
3309
3310 #define FRF_AZ_BUF_ADR_HBUF_ODD_LBN 44
3311 #define FRF_AZ_BUF_ADR_HBUF_ODD_WIDTH 20
3312 #define FRF_AZ_BUF_OWNER_ID_HBUF_ODD_LBN 32
3313 #define FRF_AZ_BUF_OWNER_ID_HBUF_ODD_WIDTH 12
3314 #define FRF_AZ_BUF_ADR_HBUF_EVEN_LBN 12
3315 #define FRF_AZ_BUF_ADR_HBUF_EVEN_WIDTH 20
3316 #define FRF_AZ_BUF_OWNER_ID_HBUF_EVEN_LBN 0
3317 #define FRF_AZ_BUF_OWNER_ID_HBUF_EVEN_WIDTH 12
3318
3319
3320 /*
3321 * FR_AA_BUF_FULL_TBL_KER(64bit):
3322 * Buffer table in full buffer table mode direct access by driver
3323 */
3324 #define FR_AA_BUF_FULL_TBL_KER_OFST 0x00018000
3325 /* falcona0=net_func_bar2 */
3326 #define FR_AA_BUF_FULL_TBL_KER_STEP 8
3327 #define FR_AA_BUF_FULL_TBL_KER_ROWS 4096
3328 /*
3329 * FR_AZ_BUF_FULL_TBL(64bit):
3330 * Buffer table in full buffer table mode direct access by driver
3331 */
3332 #define FR_AZ_BUF_FULL_TBL_OFST 0x00800000
3333 /* sienaa0=net_func_bar2,falconb0=net_func_bar2,falcona0=char_func_bar0 */
3334 #define FR_AZ_BUF_FULL_TBL_STEP 8
3335
3336 #define FR_CZ_BUF_FULL_TBL_ROWS 147456
3337 #define FR_AB_BUF_FULL_TBL_ROWS 917504
3338
3339 #define FRF_AZ_BUF_FULL_UNUSED_LBN 51
3340 #define FRF_AZ_BUF_FULL_UNUSED_WIDTH 13
3341 #define FRF_AZ_IP_DAT_BUF_SIZE_LBN 50
3342 #define FRF_AZ_IP_DAT_BUF_SIZE_WIDTH 1
3343 #define FRF_AZ_BUF_ADR_REGION_LBN 48
3344 #define FRF_AZ_BUF_ADR_REGION_WIDTH 2
3345 #define FFE_AZ_BUF_ADR_REGN3 3
3346 #define FFE_AZ_BUF_ADR_REGN2 2
3347 #define FFE_AZ_BUF_ADR_REGN1 1
3348 #define FFE_AZ_BUF_ADR_REGN0 0
3349 #define FRF_AZ_BUF_ADR_FBUF_LBN 14
3350 #define FRF_AZ_BUF_ADR_FBUF_WIDTH 34
3351 #define FRF_AZ_BUF_ADR_FBUF_DW0_LBN 14
3352 #define FRF_AZ_BUF_ADR_FBUF_DW0_WIDTH 32
3353 #define FRF_AZ_BUF_ADR_FBUF_DW1_LBN 46
3354 #define FRF_AZ_BUF_ADR_FBUF_DW1_WIDTH 2
3355 #define FRF_AZ_BUF_OWNER_ID_FBUF_LBN 0
3356 #define FRF_AZ_BUF_OWNER_ID_FBUF_WIDTH 14
3357
3358
3359 /*
3360 * FR_AZ_RX_FILTER_TBL0(128bit):
3361 * TCP/IPv4 Receive filter table
3362 */
3363 #define FR_AZ_RX_FILTER_TBL0_OFST 0x00f00000
3364 /* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
3365 #define FR_AZ_RX_FILTER_TBL0_STEP 32
3366 #define FR_AZ_RX_FILTER_TBL0_ROWS 8192
3367 /*
3368 * FR_AB_RX_FILTER_TBL1(128bit):
3369 * TCP/IPv4 Receive filter table
3370 */
3371 #define FR_AB_RX_FILTER_TBL1_OFST 0x00f00010
3372 /* falconb0=net_func_bar2,falcona0=char_func_bar0 */
3373 #define FR_AB_RX_FILTER_TBL1_STEP 32
3374 #define FR_AB_RX_FILTER_TBL1_ROWS 8192
3375
3376 #define FRF_BZ_RSS_EN_LBN 110
3377 #define FRF_BZ_RSS_EN_WIDTH 1
3378 #define FRF_BZ_SCATTER_EN_LBN 109
3379 #define FRF_BZ_SCATTER_EN_WIDTH 1
3380 #define FRF_AZ_TCP_UDP_LBN 108
3381 #define FRF_AZ_TCP_UDP_WIDTH 1
3382 #define FRF_AZ_RXQ_ID_LBN 96
3383 #define FRF_AZ_RXQ_ID_WIDTH 12
3384 #define FRF_AZ_DEST_IP_LBN 64
3385 #define FRF_AZ_DEST_IP_WIDTH 32
3386 #define FRF_AZ_DEST_PORT_TCP_LBN 48
3387 #define FRF_AZ_DEST_PORT_TCP_WIDTH 16
3388 #define FRF_AZ_SRC_IP_LBN 16
3389 #define FRF_AZ_SRC_IP_WIDTH 32
3390 #define FRF_AZ_SRC_TCP_DEST_UDP_LBN 0
3391 #define FRF_AZ_SRC_TCP_DEST_UDP_WIDTH 16
3392
3393
3394 /*
3395 * FR_CZ_RX_MAC_FILTER_TBL0(128bit):
3396 * Receive Ethernet filter table
3397 */
3398 #define FR_CZ_RX_MAC_FILTER_TBL0_OFST 0x00f00010
3399 /* sienaa0=net_func_bar2 */
3400 #define FR_CZ_RX_MAC_FILTER_TBL0_STEP 32
3401 #define FR_CZ_RX_MAC_FILTER_TBL0_ROWS 512
3402
3403 #define FRF_CZ_RMFT_RSS_EN_LBN 75
3404 #define FRF_CZ_RMFT_RSS_EN_WIDTH 1
3405 #define FRF_CZ_RMFT_SCATTER_EN_LBN 74
3406 #define FRF_CZ_RMFT_SCATTER_EN_WIDTH 1
3407 #define FRF_CZ_RMFT_IP_OVERRIDE_LBN 73
3408 #define FRF_CZ_RMFT_IP_OVERRIDE_WIDTH 1
3409 #define FRF_CZ_RMFT_RXQ_ID_LBN 61
3410 #define FRF_CZ_RMFT_RXQ_ID_WIDTH 12
3411 #define FRF_CZ_RMFT_WILDCARD_MATCH_LBN 60
3412 #define FRF_CZ_RMFT_WILDCARD_MATCH_WIDTH 1
3413 #define FRF_CZ_RMFT_DEST_MAC_LBN 12
3414 #define FRF_CZ_RMFT_DEST_MAC_WIDTH 48
3415 #define FRF_CZ_RMFT_DEST_MAC_DW0_LBN 12
3416 #define FRF_CZ_RMFT_DEST_MAC_DW0_WIDTH 32
3417 #define FRF_CZ_RMFT_DEST_MAC_DW1_LBN 44
3418 #define FRF_CZ_RMFT_DEST_MAC_DW1_WIDTH 16
3419 #define FRF_CZ_RMFT_VLAN_ID_LBN 0
3420 #define FRF_CZ_RMFT_VLAN_ID_WIDTH 12
3421
3422
3423 /*
3424 * FR_AZ_TIMER_TBL(128bit):
3425 * Timer table
3426 */
3427 #define FR_AZ_TIMER_TBL_OFST 0x00f70000
3428 /* sienaa0=net_func_bar2,falconb0=net_func_bar2,falcona0=char_func_bar0 */
3429 #define FR_AZ_TIMER_TBL_STEP 16
3430 #define FR_CZ_TIMER_TBL_ROWS 1024
3431 #define FR_AB_TIMER_TBL_ROWS 4096
3432
3433 #define FRF_CZ_TIMER_Q_EN_LBN 33
3434 #define FRF_CZ_TIMER_Q_EN_WIDTH 1
3435 #define FRF_CZ_INT_ARMD_LBN 32
3436 #define FRF_CZ_INT_ARMD_WIDTH 1
3437 #define FRF_CZ_INT_PEND_LBN 31
3438 #define FRF_CZ_INT_PEND_WIDTH 1
3439 #define FRF_CZ_HOST_NOTIFY_MODE_LBN 30
3440 #define FRF_CZ_HOST_NOTIFY_MODE_WIDTH 1
3441 #define FRF_CZ_RELOAD_TIMER_VAL_LBN 16
3442 #define FRF_CZ_RELOAD_TIMER_VAL_WIDTH 14
3443 #define FRF_CZ_TIMER_MODE_LBN 14
3444 #define FRF_CZ_TIMER_MODE_WIDTH 2
3445 #define FFE_CZ_TIMER_MODE_INT_HLDOFF 3
3446 #define FFE_CZ_TIMER_MODE_TRIG_START 2
3447 #define FFE_CZ_TIMER_MODE_IMMED_START 1
3448 #define FFE_CZ_TIMER_MODE_DIS 0
3449 #define FRF_AB_TIMER_MODE_LBN 12
3450 #define FRF_AB_TIMER_MODE_WIDTH 2
3451 #define FFE_AB_TIMER_MODE_INT_HLDOFF 2
3452 #define FFE_AB_TIMER_MODE_TRIG_START 2
3453 #define FFE_AB_TIMER_MODE_IMMED_START 1
3454 #define FFE_AB_TIMER_MODE_DIS 0
3455 #define FRF_CZ_TIMER_VAL_LBN 0
3456 #define FRF_CZ_TIMER_VAL_WIDTH 14
3457 #define FRF_AB_TIMER_VAL_LBN 0
3458 #define FRF_AB_TIMER_VAL_WIDTH 12
3459
3460
3461 /*
3462 * FR_BZ_TX_PACE_TBL(128bit):
3463 * Transmit pacing table
3464 */
3465 #define FR_BZ_TX_PACE_TBL_OFST 0x00f80000
3466 /* sienaa0=net_func_bar2,falconb0=net_func_bar2 */
3467 #define FR_AZ_TX_PACE_TBL_STEP 16
3468 #define FR_CZ_TX_PACE_TBL_ROWS 1024
3469 #define FR_BB_TX_PACE_TBL_ROWS 4096
3470 /*
3471 * FR_AA_TX_PACE_TBL(128bit):
3472 * Transmit pacing table
3473 */
3474 #define FR_AA_TX_PACE_TBL_OFST 0x00f80040
3475 /* falcona0=char_func_bar0 */
3476 /* FR_AZ_TX_PACE_TBL_STEP 16 */
3477 #define FR_AA_TX_PACE_TBL_ROWS 4092
3478
3479 #define FRF_AZ_TX_PACE_LBN 0
3480 #define FRF_AZ_TX_PACE_WIDTH 5
3481
3482
3483 /*
3484 * FR_BZ_RX_INDIRECTION_TBL(7bit):
3485 * RX Indirection Table
3486 */
3487 #define FR_BZ_RX_INDIRECTION_TBL_OFST 0x00fb0000
3488 /* falconb0,sienaa0=net_func_bar2 */
3489 #define FR_BZ_RX_INDIRECTION_TBL_STEP 16
3490 #define FR_BZ_RX_INDIRECTION_TBL_ROWS 128
3491
3492 #define FRF_BZ_IT_QUEUE_LBN 0
3493 #define FRF_BZ_IT_QUEUE_WIDTH 6
3494
3495
3496 /*
3497 * FR_CZ_TX_FILTER_TBL0(128bit):
3498 * TCP/IPv4 Transmit filter table
3499 */
3500 #define FR_CZ_TX_FILTER_TBL0_OFST 0x00fc0000
3501 /* sienaa0=net_func_bar2 */
3502 #define FR_CZ_TX_FILTER_TBL0_STEP 16
3503 #define FR_CZ_TX_FILTER_TBL0_ROWS 8192
3504
3505 #define FRF_CZ_TIFT_TCP_UDP_LBN 108
3506 #define FRF_CZ_TIFT_TCP_UDP_WIDTH 1
3507 #define FRF_CZ_TIFT_TXQ_ID_LBN 96
3508 #define FRF_CZ_TIFT_TXQ_ID_WIDTH 12
3509 #define FRF_CZ_TIFT_DEST_IP_LBN 64
3510 #define FRF_CZ_TIFT_DEST_IP_WIDTH 32
3511 #define FRF_CZ_TIFT_DEST_PORT_TCP_LBN 48
3512 #define FRF_CZ_TIFT_DEST_PORT_TCP_WIDTH 16
3513 #define FRF_CZ_TIFT_SRC_IP_LBN 16
3514 #define FRF_CZ_TIFT_SRC_IP_WIDTH 32
3515 #define FRF_CZ_TIFT_SRC_TCP_DEST_UDP_LBN 0
3516 #define FRF_CZ_TIFT_SRC_TCP_DEST_UDP_WIDTH 16
3517
3518
3519 /*
3520 * FR_CZ_TX_MAC_FILTER_TBL0(128bit):
3521 * Transmit Ethernet filter table
3522 */
3523 #define FR_CZ_TX_MAC_FILTER_TBL0_OFST 0x00fe0000
3524 /* sienaa0=net_func_bar2 */
3525 #define FR_CZ_TX_MAC_FILTER_TBL0_STEP 16
3526 #define FR_CZ_TX_MAC_FILTER_TBL0_ROWS 512
3527
3528 #define FRF_CZ_TMFT_TXQ_ID_LBN 61
3529 #define FRF_CZ_TMFT_TXQ_ID_WIDTH 12
3530 #define FRF_CZ_TMFT_WILDCARD_MATCH_LBN 60
3531 #define FRF_CZ_TMFT_WILDCARD_MATCH_WIDTH 1
3532 #define FRF_CZ_TMFT_SRC_MAC_LBN 12
3533 #define FRF_CZ_TMFT_SRC_MAC_WIDTH 48
3534 #define FRF_CZ_TMFT_SRC_MAC_DW0_LBN 12
3535 #define FRF_CZ_TMFT_SRC_MAC_DW0_WIDTH 32
3536 #define FRF_CZ_TMFT_SRC_MAC_DW1_LBN 44
3537 #define FRF_CZ_TMFT_SRC_MAC_DW1_WIDTH 16
3538 #define FRF_CZ_TMFT_VLAN_ID_LBN 0
3539 #define FRF_CZ_TMFT_VLAN_ID_WIDTH 12
3540
3541
3542 /*
3543 * FR_CZ_MC_TREG_SMEM(32bit):
3544 * MC Shared Memory
3545 */
3546 #define FR_CZ_MC_TREG_SMEM_OFST 0x00ff0000
3547 /* sienaa0=net_func_bar2 */
3548 #define FR_CZ_MC_TREG_SMEM_STEP 4
3549 #define FR_CZ_MC_TREG_SMEM_ROWS 512
3550
3551 #define FRF_CZ_MC_TREG_SMEM_ROW_LBN 0
3552 #define FRF_CZ_MC_TREG_SMEM_ROW_WIDTH 32
3553
3554
3555 /*
3556 * FR_BB_MSIX_VECTOR_TABLE(128bit):
3557 * MSIX Vector Table
3558 */
3559 #define FR_BB_MSIX_VECTOR_TABLE_OFST 0x00ff0000
3560 /* falconb0=net_func_bar2 */
3561 #define FR_BZ_MSIX_VECTOR_TABLE_STEP 16
3562 #define FR_BB_MSIX_VECTOR_TABLE_ROWS 64
3563 /*
3564 * FR_CZ_MSIX_VECTOR_TABLE(128bit):
3565 * MSIX Vector Table
3566 */
3567 #define FR_CZ_MSIX_VECTOR_TABLE_OFST 0x00000000
3568 /* sienaa0=pci_f0_bar4 */
3569 /* FR_BZ_MSIX_VECTOR_TABLE_STEP 16 */
3570 #define FR_CZ_MSIX_VECTOR_TABLE_ROWS 1024
3571
3572 #define FRF_BZ_MSIX_VECTOR_RESERVED_LBN 97
3573 #define FRF_BZ_MSIX_VECTOR_RESERVED_WIDTH 31
3574 #define FRF_BZ_MSIX_VECTOR_MASK_LBN 96
3575 #define FRF_BZ_MSIX_VECTOR_MASK_WIDTH 1
3576 #define FRF_BZ_MSIX_MESSAGE_DATA_LBN 64
3577 #define FRF_BZ_MSIX_MESSAGE_DATA_WIDTH 32
3578 #define FRF_BZ_MSIX_MESSAGE_ADDRESS_HI_LBN 32
3579 #define FRF_BZ_MSIX_MESSAGE_ADDRESS_HI_WIDTH 32
3580 #define FRF_BZ_MSIX_MESSAGE_ADDRESS_LO_LBN 0
3581 #define FRF_BZ_MSIX_MESSAGE_ADDRESS_LO_WIDTH 32
3582
3583
3584 /*
3585 * FR_BB_MSIX_PBA_TABLE(32bit):
3586 * MSIX Pending Bit Array
3587 */
3588 #define FR_BB_MSIX_PBA_TABLE_OFST 0x00ff2000
3589 /* falconb0=net_func_bar2 */
3590 #define FR_BZ_MSIX_PBA_TABLE_STEP 4
3591 #define FR_BB_MSIX_PBA_TABLE_ROWS 2
3592 /*
3593 * FR_CZ_MSIX_PBA_TABLE(32bit):
3594 * MSIX Pending Bit Array
3595 */
3596 #define FR_CZ_MSIX_PBA_TABLE_OFST 0x00008000
3597 /* sienaa0=pci_f0_bar4 */
3598 /* FR_BZ_MSIX_PBA_TABLE_STEP 4 */
3599 #define FR_CZ_MSIX_PBA_TABLE_ROWS 32
3600
3601 #define FRF_BZ_MSIX_PBA_PEND_DWORD_LBN 0
3602 #define FRF_BZ_MSIX_PBA_PEND_DWORD_WIDTH 32
3603
3604
3605 /*
3606 * FR_AZ_SRM_DBG_REG(64bit):
3607 * SRAM debug access
3608 */
3609 #define FR_AZ_SRM_DBG_REG_OFST 0x03000000
3610 /* sienaa0=net_func_bar2,falconb0=net_func_bar2,falcona0=char_func_bar0 */
3611 #define FR_AZ_SRM_DBG_REG_STEP 8
3612
3613 #define FR_CZ_SRM_DBG_REG_ROWS 262144
3614 #define FR_AB_SRM_DBG_REG_ROWS 2097152
3615
3616 #define FRF_AZ_SRM_DBG_LBN 0
3617 #define FRF_AZ_SRM_DBG_WIDTH 64
3618 #define FRF_AZ_SRM_DBG_DW0_LBN 0
3619 #define FRF_AZ_SRM_DBG_DW0_WIDTH 32
3620 #define FRF_AZ_SRM_DBG_DW1_LBN 32
3621 #define FRF_AZ_SRM_DBG_DW1_WIDTH 32
3622
3623
3624 /*
3625 * FR_AA_INT_ACK_CHAR(32bit):
3626 * CHAR interrupt acknowledge register
3627 */
3628 #define FR_AA_INT_ACK_CHAR_OFST 0x00000060
3629 /* falcona0=char_func_bar0 */
3630
3631 #define FRF_AA_INT_ACK_CHAR_FIELD_LBN 0
3632 #define FRF_AA_INT_ACK_CHAR_FIELD_WIDTH 32
3633
3634
3635 /* FS_DRIVER_EV */
3636 #define FSF_AZ_DRIVER_EV_SUBCODE_LBN 56
3637 #define FSF_AZ_DRIVER_EV_SUBCODE_WIDTH 4
3638 #define FSE_AZ_TX_DSC_ERROR_EV 15
3639 #define FSE_AZ_RX_DSC_ERROR_EV 14
3640 #define FSE_AZ_RX_RECOVER_EV 11
3641 #define FSE_AZ_TIMER_EV 10
3642 #define FSE_AZ_TX_PKT_NON_TCP_UDP 9
3643 #define FSE_AZ_WAKE_UP_EV 6
3644 #define FSE_AZ_SRM_UPD_DONE_EV 5
3645 #define FSE_AZ_EVQ_NOT_EN_EV 3
3646 #define FSE_AZ_EVQ_INIT_DONE_EV 2
3647 #define FSE_AZ_RX_DESCQ_FLS_DONE_EV 1
3648 #define FSE_AZ_TX_DESCQ_FLS_DONE_EV 0
3649 #define FSF_AZ_DRIVER_EV_SUBDATA_LBN 0
3650 #define FSF_AZ_DRIVER_EV_SUBDATA_WIDTH 14
3651
3652
3653 /* FS_EVENT_ENTRY */
3654 #define FSF_AZ_EV_CODE_LBN 60
3655 #define FSF_AZ_EV_CODE_WIDTH 4
3656 #define FSE_AZ_EV_CODE_USER_EV 8
3657 #define FSE_AZ_EV_CODE_DRV_GEN_EV 7
3658 #define FSE_AZ_EV_CODE_GLOBAL_EV 6
3659 #define FSE_AZ_EV_CODE_DRIVER_EV 5
3660 #define FSE_AZ_EV_CODE_TX_EV 2
3661 #define FSE_AZ_EV_CODE_RX_EV 0
3662 #define FSF_AZ_EV_DATA_LBN 0
3663 #define FSF_AZ_EV_DATA_WIDTH 60
3664 #define FSF_AZ_EV_DATA_DW0_LBN 0
3665 #define FSF_AZ_EV_DATA_DW0_WIDTH 32
3666 #define FSF_AZ_EV_DATA_DW1_LBN 32
3667 #define FSF_AZ_EV_DATA_DW1_WIDTH 28
3668
3669
3670 /* FS_GLOBAL_EV */
3671 #define FSF_AA_GLB_EV_RX_RECOVERY_LBN 12
3672 #define FSF_AA_GLB_EV_RX_RECOVERY_WIDTH 1
3673 #define FSF_BZ_GLB_EV_XG_MNT_INTR_LBN 11
3674 #define FSF_BZ_GLB_EV_XG_MNT_INTR_WIDTH 1
3675 #define FSF_AZ_GLB_EV_XFP_PHY0_INTR_LBN 10
3676 #define FSF_AZ_GLB_EV_XFP_PHY0_INTR_WIDTH 1
3677 #define FSF_AZ_GLB_EV_XG_PHY0_INTR_LBN 9
3678 #define FSF_AZ_GLB_EV_XG_PHY0_INTR_WIDTH 1
3679 #define FSF_AZ_GLB_EV_G_PHY0_INTR_LBN 7
3680 #define FSF_AZ_GLB_EV_G_PHY0_INTR_WIDTH 1
3681
3682
3683 /* FS_RX_EV */
3684 #define FSF_CZ_RX_EV_PKT_NOT_PARSED_LBN 58
3685 #define FSF_CZ_RX_EV_PKT_NOT_PARSED_WIDTH 1
3686 #define FSF_CZ_RX_EV_IPV6_PKT_LBN 57
3687 #define FSF_CZ_RX_EV_IPV6_PKT_WIDTH 1
3688 #define FSF_AZ_RX_EV_PKT_OK_LBN 56
3689 #define FSF_AZ_RX_EV_PKT_OK_WIDTH 1
3690 #define FSF_AZ_RX_EV_PAUSE_FRM_ERR_LBN 55
3691 #define FSF_AZ_RX_EV_PAUSE_FRM_ERR_WIDTH 1
3692 #define FSF_AZ_RX_EV_BUF_OWNER_ID_ERR_LBN 54
3693 #define FSF_AZ_RX_EV_BUF_OWNER_ID_ERR_WIDTH 1
3694 #define FSF_AZ_RX_EV_IP_FRAG_ERR_LBN 53
3695 #define FSF_AZ_RX_EV_IP_FRAG_ERR_WIDTH 1
3696 #define FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR_LBN 52
3697 #define FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR_WIDTH 1
3698 #define FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR_LBN 51
3699 #define FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR_WIDTH 1
3700 #define FSF_AZ_RX_EV_ETH_CRC_ERR_LBN 50
3701 #define FSF_AZ_RX_EV_ETH_CRC_ERR_WIDTH 1
3702 #define FSF_AZ_RX_EV_FRM_TRUNC_LBN 49
3703 #define FSF_AZ_RX_EV_FRM_TRUNC_WIDTH 1
3704 #define FSF_AZ_RX_EV_TOBE_DISC_LBN 47
3705 #define FSF_AZ_RX_EV_TOBE_DISC_WIDTH 1
3706 #define FSF_AZ_RX_EV_PKT_TYPE_LBN 44
3707 #define FSF_AZ_RX_EV_PKT_TYPE_WIDTH 3
3708 #define FSE_AZ_RX_EV_PKT_TYPE_VLAN_JUMBO 5
3709 #define FSE_AZ_RX_EV_PKT_TYPE_VLAN_LLC 4
3710 #define FSE_AZ_RX_EV_PKT_TYPE_VLAN 3
3711 #define FSE_AZ_RX_EV_PKT_TYPE_JUMBO 2
3712 #define FSE_AZ_RX_EV_PKT_TYPE_LLC 1
3713 #define FSE_AZ_RX_EV_PKT_TYPE_ETH 0
3714 #define FSF_AZ_RX_EV_HDR_TYPE_LBN 42
3715 #define FSF_AZ_RX_EV_HDR_TYPE_WIDTH 2
3716 #define FSE_AZ_RX_EV_HDR_TYPE_OTHER 3
3717 #define FSE_AZ_RX_EV_HDR_TYPE_IPV4_OTHER 2
3718 #define FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_OTHER 2
3719 #define FSE_AZ_RX_EV_HDR_TYPE_IPV4_UDP 1
3720 #define FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_UDP 1
3721 #define FSE_AZ_RX_EV_HDR_TYPE_IPV4_TCP 0
3722 #define FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_TCP 0
3723 #define FSF_AZ_RX_EV_DESC_Q_EMPTY_LBN 41
3724 #define FSF_AZ_RX_EV_DESC_Q_EMPTY_WIDTH 1
3725 #define FSF_AZ_RX_EV_MCAST_HASH_MATCH_LBN 40
3726 #define FSF_AZ_RX_EV_MCAST_HASH_MATCH_WIDTH 1
3727 #define FSF_AZ_RX_EV_MCAST_PKT_LBN 39
3728 #define FSF_AZ_RX_EV_MCAST_PKT_WIDTH 1
3729 #define FSF_AA_RX_EV_RECOVERY_FLAG_LBN 37
3730 #define FSF_AA_RX_EV_RECOVERY_FLAG_WIDTH 1
3731 #define FSF_AZ_RX_EV_Q_LABEL_LBN 32
3732 #define FSF_AZ_RX_EV_Q_LABEL_WIDTH 5
3733 #define FSF_AZ_RX_EV_JUMBO_CONT_LBN 31
3734 #define FSF_AZ_RX_EV_JUMBO_CONT_WIDTH 1
3735 #define FSF_AZ_RX_EV_PORT_LBN 30
3736 #define FSF_AZ_RX_EV_PORT_WIDTH 1
3737 #define FSF_AZ_RX_EV_BYTE_CNT_LBN 16
3738 #define FSF_AZ_RX_EV_BYTE_CNT_WIDTH 14
3739 #define FSF_AZ_RX_EV_SOP_LBN 15
3740 #define FSF_AZ_RX_EV_SOP_WIDTH 1
3741 #define FSF_AZ_RX_EV_ISCSI_PKT_OK_LBN 14
3742 #define FSF_AZ_RX_EV_ISCSI_PKT_OK_WIDTH 1
3743 #define FSF_AZ_RX_EV_ISCSI_DDIG_ERR_LBN 13
3744 #define FSF_AZ_RX_EV_ISCSI_DDIG_ERR_WIDTH 1
3745 #define FSF_AZ_RX_EV_ISCSI_HDIG_ERR_LBN 12
3746 #define FSF_AZ_RX_EV_ISCSI_HDIG_ERR_WIDTH 1
3747 #define FSF_AZ_RX_EV_DESC_PTR_LBN 0
3748 #define FSF_AZ_RX_EV_DESC_PTR_WIDTH 12
3749
3750
3751 /* FS_RX_KER_DESC */
3752 #define FSF_AZ_RX_KER_BUF_SIZE_LBN 48
3753 #define FSF_AZ_RX_KER_BUF_SIZE_WIDTH 14
3754 #define FSF_AZ_RX_KER_BUF_REGION_LBN 46
3755 #define FSF_AZ_RX_KER_BUF_REGION_WIDTH 2
3756 #define FSF_AZ_RX_KER_BUF_ADDR_LBN 0
3757 #define FSF_AZ_RX_KER_BUF_ADDR_WIDTH 46
3758 #define FSF_AZ_RX_KER_BUF_ADDR_DW0_LBN 0
3759 #define FSF_AZ_RX_KER_BUF_ADDR_DW0_WIDTH 32
3760 #define FSF_AZ_RX_KER_BUF_ADDR_DW1_LBN 32
3761 #define FSF_AZ_RX_KER_BUF_ADDR_DW1_WIDTH 14
3762
3763
3764 /* FS_RX_USER_DESC */
3765 #define FSF_AZ_RX_USER_2BYTE_OFFSET_LBN 20
3766 #define FSF_AZ_RX_USER_2BYTE_OFFSET_WIDTH 12
3767 #define FSF_AZ_RX_USER_BUF_ID_LBN 0
3768 #define FSF_AZ_RX_USER_BUF_ID_WIDTH 20
3769
3770
3771 /* FS_TX_EV */
3772 #define FSF_AZ_TX_EV_PKT_ERR_LBN 38
3773 #define FSF_AZ_TX_EV_PKT_ERR_WIDTH 1
3774 #define FSF_AZ_TX_EV_PKT_TOO_BIG_LBN 37
3775 #define FSF_AZ_TX_EV_PKT_TOO_BIG_WIDTH 1
3776 #define FSF_AZ_TX_EV_Q_LABEL_LBN 32
3777 #define FSF_AZ_TX_EV_Q_LABEL_WIDTH 5
3778 #define FSF_AZ_TX_EV_PORT_LBN 16
3779 #define FSF_AZ_TX_EV_PORT_WIDTH 1
3780 #define FSF_AZ_TX_EV_WQ_FF_FULL_LBN 15
3781 #define FSF_AZ_TX_EV_WQ_FF_FULL_WIDTH 1
3782 #define FSF_AZ_TX_EV_BUF_OWNER_ID_ERR_LBN 14
3783 #define FSF_AZ_TX_EV_BUF_OWNER_ID_ERR_WIDTH 1
3784 #define FSF_AZ_TX_EV_COMP_LBN 12
3785 #define FSF_AZ_TX_EV_COMP_WIDTH 1
3786 #define FSF_AZ_TX_EV_DESC_PTR_LBN 0
3787 #define FSF_AZ_TX_EV_DESC_PTR_WIDTH 12
3788
3789
3790 /* FS_TX_KER_DESC */
3791 #define FSF_AZ_TX_KER_CONT_LBN 62
3792 #define FSF_AZ_TX_KER_CONT_WIDTH 1
3793 #define FSF_AZ_TX_KER_BYTE_COUNT_LBN 48
3794 #define FSF_AZ_TX_KER_BYTE_COUNT_WIDTH 14
3795 #define FSF_AZ_TX_KER_BUF_REGION_LBN 46
3796 #define FSF_AZ_TX_KER_BUF_REGION_WIDTH 2
3797 #define FSF_AZ_TX_KER_BUF_ADDR_LBN 0
3798 #define FSF_AZ_TX_KER_BUF_ADDR_WIDTH 46
3799 #define FSF_AZ_TX_KER_BUF_ADDR_DW0_LBN 0
3800 #define FSF_AZ_TX_KER_BUF_ADDR_DW0_WIDTH 32
3801 #define FSF_AZ_TX_KER_BUF_ADDR_DW1_LBN 32
3802 #define FSF_AZ_TX_KER_BUF_ADDR_DW1_WIDTH 14
3803
3804
3805 /* FS_TX_USER_DESC */
3806 #define FSF_AZ_TX_USER_SW_EV_EN_LBN 48
3807 #define FSF_AZ_TX_USER_SW_EV_EN_WIDTH 1
3808 #define FSF_AZ_TX_USER_CONT_LBN 46
3809 #define FSF_AZ_TX_USER_CONT_WIDTH 1
3810 #define FSF_AZ_TX_USER_BYTE_CNT_LBN 33
3811 #define FSF_AZ_TX_USER_BYTE_CNT_WIDTH 13
3812 #define FSF_AZ_TX_USER_BUF_ID_LBN 13
3813 #define FSF_AZ_TX_USER_BUF_ID_WIDTH 20
3814 #define FSF_AZ_TX_USER_BYTE_OFS_LBN 0
3815 #define FSF_AZ_TX_USER_BYTE_OFS_WIDTH 13
3816
3817
3818 /* FS_USER_EV */
3819 #define FSF_CZ_USER_QID_LBN 32
3820 #define FSF_CZ_USER_QID_WIDTH 10
3821 #define FSF_CZ_USER_EV_REG_VALUE_LBN 0
3822 #define FSF_CZ_USER_EV_REG_VALUE_WIDTH 32
3823
3824
3825 /* FS_NET_IVEC */
3826 #define FSF_AZ_NET_IVEC_FATAL_INT_LBN 64
3827 #define FSF_AZ_NET_IVEC_FATAL_INT_WIDTH 1
3828 #define FSF_AZ_NET_IVEC_INT_Q_LBN 40
3829 #define FSF_AZ_NET_IVEC_INT_Q_WIDTH 4
3830 #define FSF_AZ_NET_IVEC_INT_FLAG_LBN 32
3831 #define FSF_AZ_NET_IVEC_INT_FLAG_WIDTH 1
3832 #define FSF_AZ_NET_IVEC_EVQ_FIFO_HF_LBN 1
3833 #define FSF_AZ_NET_IVEC_EVQ_FIFO_HF_WIDTH 1
3834 #define FSF_AZ_NET_IVEC_EVQ_FIFO_AF_LBN 0
3835 #define FSF_AZ_NET_IVEC_EVQ_FIFO_AF_WIDTH 1
3836
3837
3838 /* DRIVER_EV */
3839 /* Sub-fields of an RX flush completion event */
3840 #define FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL_LBN 12
3841 #define FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL_WIDTH 1
3842 #define FSF_AZ_DRIVER_EV_RX_DESCQ_ID_LBN 0
3843 #define FSF_AZ_DRIVER_EV_RX_DESCQ_ID_WIDTH 12
3844
3845
3846
3847 /**************************************************************************
3848 *
3849 * Falcon non-volatile configuration
3850 *
3851 **************************************************************************
3852 */
3853
3854
3855 #define FR_AZ_TX_PACE_TBL_OFST FR_BZ_TX_PACE_TBL_OFST
3856
3857
3858 #ifdef __cplusplus
3859 }
3860 #endif
3861
3862
3863
3864
3865 #endif /* _SYS_EFX_REGS_H */