1 /*-
2 * Copyright 2007-2013 Solarflare Communications Inc. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 */
25
26 #ifndef _SYS_EFX_IMPL_H
27 #define _SYS_EFX_IMPL_H
28
29 #include "efsys.h"
30 #include "efx.h"
31 #include "efx_regs.h"
32
33 #if EFSYS_OPT_FALCON
34 #include "falcon_impl.h"
35 #endif /* EFSYS_OPT_FALCON */
36
37 #if EFSYS_OPT_SIENA
38 #include "siena_impl.h"
39 #endif /* EFSYS_OPT_SIENA */
40
41 #ifdef __cplusplus
42 extern "C" {
43 #endif
44
45 #define EFX_MOD_MCDI 0x00000001
46 #define EFX_MOD_PROBE 0x00000002
47 #define EFX_MOD_NVRAM 0x00000004
48 #define EFX_MOD_VPD 0x00000008
49 #define EFX_MOD_NIC 0x00000010
50 #define EFX_MOD_INTR 0x00000020
51 #define EFX_MOD_EV 0x00000040
52 #define EFX_MOD_RX 0x00000080
53 #define EFX_MOD_TX 0x00000100
54 #define EFX_MOD_PORT 0x00000200
55 #define EFX_MOD_MON 0x00000400
56 #define EFX_MOD_WOL 0x00000800
57 #define EFX_MOD_FILTER 0x00001000
58
59 #define EFX_RESET_MAC 0x00000001
60 #define EFX_RESET_PHY 0x00000002
61
62 typedef enum efx_mac_type_e {
63 EFX_MAC_INVALID = 0,
64 EFX_MAC_FALCON_GMAC,
65 EFX_MAC_FALCON_XMAC,
66 EFX_MAC_SIENA,
67 EFX_MAC_NTYPES
68 } efx_mac_type_t;
69
70 typedef struct efx_mac_ops_s {
71 int (*emo_reset)(efx_nic_t *); /* optional */
72 int (*emo_poll)(efx_nic_t *, efx_link_mode_t *);
73 int (*emo_up)(efx_nic_t *, boolean_t *);
74 int (*emo_reconfigure)(efx_nic_t *);
75 #if EFSYS_OPT_LOOPBACK
76 int (*emo_loopback_set)(efx_nic_t *, efx_link_mode_t,
77 efx_loopback_type_t);
78 #endif /* EFSYS_OPT_LOOPBACK */
79 #if EFSYS_OPT_MAC_STATS
80 int (*emo_stats_upload)(efx_nic_t *, efsys_mem_t *);
81 int (*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *,
82 uint16_t, boolean_t);
83 int (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
84 efsys_stat_t *, uint32_t *);
85 #endif /* EFSYS_OPT_MAC_STATS */
86 } efx_mac_ops_t;
87
88 typedef struct efx_phy_ops_s {
89 int (*epo_power)(efx_nic_t *, boolean_t); /* optional */
90 int (*epo_reset)(efx_nic_t *);
91 int (*epo_reconfigure)(efx_nic_t *);
92 int (*epo_verify)(efx_nic_t *);
93 int (*epo_uplink_check)(efx_nic_t *,
94 boolean_t *); /* optional */
95 int (*epo_downlink_check)(efx_nic_t *, efx_link_mode_t *,
96 unsigned int *, uint32_t *);
97 int (*epo_oui_get)(efx_nic_t *, uint32_t *);
98 #if EFSYS_OPT_PHY_STATS
99 int (*epo_stats_update)(efx_nic_t *, efsys_mem_t *,
100 uint32_t *);
101 #endif /* EFSYS_OPT_PHY_STATS */
102 #if EFSYS_OPT_PHY_PROPS
103 #if EFSYS_OPT_NAMES
104 const char __cs *(*epo_prop_name)(efx_nic_t *, unsigned int);
105 #endif /* EFSYS_OPT_PHY_PROPS */
106 int (*epo_prop_get)(efx_nic_t *, unsigned int, uint32_t,
107 uint32_t *);
108 int (*epo_prop_set)(efx_nic_t *, unsigned int, uint32_t);
109 #endif /* EFSYS_OPT_PHY_PROPS */
110 #if EFSYS_OPT_PHY_BIST
111 int (*epo_bist_start)(efx_nic_t *, efx_phy_bist_type_t);
112 int (*epo_bist_poll)(efx_nic_t *, efx_phy_bist_type_t,
113 efx_phy_bist_result_t *, uint32_t *,
114 unsigned long *, size_t);
115 void (*epo_bist_stop)(efx_nic_t *, efx_phy_bist_type_t);
116 #endif /* EFSYS_OPT_PHY_BIST */
117 } efx_phy_ops_t;
118
119 typedef struct efx_port_s {
120 efx_mac_type_t ep_mac_type;
121 uint32_t ep_phy_type;
122 uint8_t ep_port;
123 uint32_t ep_mac_pdu;
124 uint8_t ep_mac_addr[6];
125 efx_link_mode_t ep_link_mode;
126 boolean_t ep_unicst;
127 boolean_t ep_brdcst;
128 unsigned int ep_fcntl;
129 boolean_t ep_fcntl_autoneg;
130 efx_oword_t ep_multicst_hash[2];
131 #if EFSYS_OPT_LOOPBACK
132 efx_loopback_type_t ep_loopback_type;
133 efx_link_mode_t ep_loopback_link_mode;
134 #endif /* EFSYS_OPT_LOOPBACK */
135 #if EFSYS_OPT_PHY_FLAGS
136 uint32_t ep_phy_flags;
137 #endif /* EFSYS_OPT_PHY_FLAGS */
138 #if EFSYS_OPT_PHY_LED_CONTROL
139 efx_phy_led_mode_t ep_phy_led_mode;
140 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
141 efx_phy_media_type_t ep_fixed_port_type;
142 efx_phy_media_type_t ep_module_type;
143 uint32_t ep_adv_cap_mask;
144 uint32_t ep_lp_cap_mask;
145 uint32_t ep_default_adv_cap_mask;
146 uint32_t ep_phy_cap_mask;
147 #if EFSYS_OPT_PHY_TXC43128 || EFSYS_OPT_PHY_QT2025C
148 union {
149 struct {
150 unsigned int bug10934_count;
151 } ep_txc43128;
152 struct {
153 unsigned int bug17190_count;
154 } ep_qt2025c;
155 };
156 #endif
157 boolean_t ep_mac_poll_needed; /* falcon only */
158 boolean_t ep_mac_up; /* falcon only */
159 uint32_t ep_fwver; /* falcon only */
160 boolean_t ep_mac_drain;
161 boolean_t ep_mac_stats_pending;
162 #if EFSYS_OPT_PHY_BIST
163 efx_phy_bist_type_t ep_current_bist;
164 #endif
165 efx_mac_ops_t *ep_emop;
166 efx_phy_ops_t *ep_epop;
167 } efx_port_t;
168
169 typedef struct efx_mon_ops_s {
170 int (*emo_reset)(efx_nic_t *);
171 int (*emo_reconfigure)(efx_nic_t *);
172 #if EFSYS_OPT_MON_STATS
173 int (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
174 efx_mon_stat_value_t *);
175 #endif /* EFSYS_OPT_MON_STATS */
176 } efx_mon_ops_t;
177
178 typedef struct efx_mon_s {
179 efx_mon_type_t em_type;
180 efx_mon_ops_t *em_emop;
181 } efx_mon_t;
182
183 typedef struct efx_intr_s {
184 efx_intr_type_t ei_type;
185 efsys_mem_t *ei_esmp;
186 unsigned int ei_level;
187 } efx_intr_t;
188
189 typedef struct efx_nic_ops_s {
190 int (*eno_probe)(efx_nic_t *);
191 int (*eno_reset)(efx_nic_t *);
192 int (*eno_init)(efx_nic_t *);
193 #if EFSYS_OPT_DIAG
194 int (*eno_sram_test)(efx_nic_t *, efx_sram_pattern_fn_t);
195 int (*eno_register_test)(efx_nic_t *);
196 #endif /* EFSYS_OPT_DIAG */
197 void (*eno_fini)(efx_nic_t *);
198 void (*eno_unprobe)(efx_nic_t *);
199 } efx_nic_ops_t;
200
201 #ifndef EFX_TXQ_LIMIT_TARGET
202 # define EFX_TXQ_LIMIT_TARGET 259
203 #endif
204 #ifndef EFX_RXQ_LIMIT_TARGET
205 # define EFX_RXQ_LIMIT_TARGET 768
206 #endif
207 #ifndef EFX_TXQ_DC_SIZE
208 #define EFX_TXQ_DC_SIZE 1 /* 16 descriptors */
209 #endif
210 #ifndef EFX_RXQ_DC_SIZE
211 #define EFX_RXQ_DC_SIZE 3 /* 64 descriptors */
212 #endif
213
214 #if EFSYS_OPT_FILTER
215
216 typedef enum efx_filter_type_e {
217 EFX_FILTER_RX_TCP_FULL, /* TCP/IPv4 4-tuple {dIP,dTCP,sIP,sTCP} */
218 EFX_FILTER_RX_TCP_WILD, /* TCP/IPv4 dest {dIP,dTCP, -, -} */
219 EFX_FILTER_RX_UDP_FULL, /* UDP/IPv4 4-tuple {dIP,dUDP,sIP,sUDP} */
220 EFX_FILTER_RX_UDP_WILD, /* UDP/IPv4 dest {dIP,dUDP, -, -} */
221
222 #if EFSYS_OPT_SIENA
223 EFX_FILTER_RX_MAC_FULL, /* Ethernet {dMAC,VLAN} */
224 EFX_FILTER_RX_MAC_WILD, /* Ethernet {dMAC, -} */
225
226 EFX_FILTER_TX_TCP_FULL, /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
227 EFX_FILTER_TX_TCP_WILD, /* TCP/IPv4 { -, -,sIP,sTCP} */
228 EFX_FILTER_TX_UDP_FULL, /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */
229 EFX_FILTER_TX_UDP_WILD, /* UDP/IPv4 source (host, port) */
230
231 EFX_FILTER_TX_MAC_FULL, /* Ethernet source (MAC address, VLAN ID) */
232 EFX_FILTER_TX_MAC_WILD, /* Ethernet source (MAC address) */
233 #endif /* EFSYS_OPT_SIENA */
234
235 EFX_FILTER_NTYPES
236 } efx_filter_type_t;
237
238 typedef enum efx_filter_tbl_id_e {
239 EFX_FILTER_TBL_RX_IP = 0,
240 EFX_FILTER_TBL_RX_MAC,
241 EFX_FILTER_TBL_TX_IP,
242 EFX_FILTER_TBL_TX_MAC,
243 EFX_FILTER_NTBLS
244 } efx_filter_tbl_id_t;
245
246 typedef struct efx_filter_tbl_s {
247 int eft_size; /* number of entries */
248 int eft_used; /* active count */
249 uint32_t *eft_bitmap; /* active bitmap */
250 efx_filter_spec_t *eft_spec; /* array of saved specs */
251 } efx_filter_tbl_t;
252
253 typedef struct efx_filter_s {
254 efx_filter_tbl_t ef_tbl[EFX_FILTER_NTBLS];
255 unsigned int ef_depth[EFX_FILTER_NTYPES];
256 } efx_filter_t;
257
258
259 extern __checkReturn int
260 efx_filter_insert_filter(
261 __in efx_nic_t *enp,
262 __in efx_filter_spec_t *spec,
263 __in boolean_t replace);
264
265 extern __checkReturn int
266 efx_filter_remove_filter(
267 __in efx_nic_t *enp,
268 __in efx_filter_spec_t *spec);
269
270 extern void
271 efx_filter_remove_index(
272 __inout efx_nic_t *enp,
273 __in efx_filter_type_t type,
274 __in int filter_idx);
275
276 extern void
277 efx_filter_redirect_index(
278 __inout efx_nic_t *enp,
279 __in efx_filter_type_t type,
280 __in int filter_index,
281 __in int rxq_index);
282
283 extern __checkReturn int
284 efx_filter_clear_tbl(
285 __in efx_nic_t *enp,
286 __in efx_filter_tbl_id_t tbl);
287
288 #endif /* EFSYS_OPT_FILTER */
289
290 #if EFSYS_OPT_NVRAM
291 typedef struct efx_nvram_ops_s {
292 #if EFSYS_OPT_DIAG
293 int (*envo_test)(efx_nic_t *);
294 #endif /* EFSYS_OPT_DIAG */
295 int (*envo_size)(efx_nic_t *, efx_nvram_type_t, size_t *);
296 int (*envo_get_version)(efx_nic_t *, efx_nvram_type_t,
297 uint32_t *, uint16_t *);
298 int (*envo_rw_start)(efx_nic_t *, efx_nvram_type_t, size_t *);
299 int (*envo_read_chunk)(efx_nic_t *, efx_nvram_type_t,
300 unsigned int, caddr_t, size_t);
301 int (*envo_erase)(efx_nic_t *, efx_nvram_type_t);
302 int (*envo_write_chunk)(efx_nic_t *, efx_nvram_type_t,
303 unsigned int, caddr_t, size_t);
304 void (*envo_rw_finish)(efx_nic_t *, efx_nvram_type_t);
305 int (*envo_set_version)(efx_nic_t *, efx_nvram_type_t, uint16_t *);
306
307 } efx_nvram_ops_t;
308 #endif /* EFSYS_OPT_NVRAM */
309
310 #if EFSYS_OPT_VPD
311 typedef struct efx_vpd_ops_s {
312 int (*evpdo_init)(efx_nic_t *);
313 int (*evpdo_size)(efx_nic_t *, size_t *);
314 int (*evpdo_read)(efx_nic_t *, caddr_t, size_t);
315 int (*evpdo_verify)(efx_nic_t *, caddr_t, size_t);
316 int (*evpdo_reinit)(efx_nic_t *, caddr_t, size_t);
317 int (*evpdo_get)(efx_nic_t *, caddr_t, size_t, efx_vpd_value_t *);
318 int (*evpdo_set)(efx_nic_t *, caddr_t, size_t, efx_vpd_value_t *);
319 int (*evpdo_next)(efx_nic_t *, caddr_t, size_t, efx_vpd_value_t *,
320 unsigned int *);
321 int (*evpdo_write)(efx_nic_t *, caddr_t, size_t);
322 void (*evpdo_fini)(efx_nic_t *);
323 } efx_vpd_ops_t;
324 #endif /* EFSYS_OPT_VPD */
325
326 struct efx_nic_s {
327 uint32_t en_magic;
328 efx_family_t en_family;
329 uint32_t en_features;
330 efsys_identifier_t *en_esip;
331 efsys_lock_t *en_eslp;
332 efsys_bar_t *en_esbp;
333 unsigned int en_mod_flags;
334 unsigned int en_reset_flags;
335 efx_nic_cfg_t en_nic_cfg;
336 efx_port_t en_port;
337 efx_mon_t en_mon;
338 efx_intr_t en_intr;
339 uint32_t en_ev_qcount;
340 uint32_t en_rx_qcount;
341 uint32_t en_tx_qcount;
342 efx_nic_ops_t *en_enop;
343 #if EFSYS_OPT_FILTER
344 efx_filter_t en_filter;
345 #endif /* EFSYS_OPT_FILTER */
346 #if EFSYS_OPT_NVRAM
347 efx_nvram_type_t en_nvram_locked;
348 efx_nvram_ops_t *en_envop;
349 #endif /* EFSYS_OPT_NVRAM */
350 #if EFSYS_OPT_VPD
351 efx_vpd_ops_t *en_evpdop;
352 #endif /* EFSYS_OPT_VPD */
353 union {
354 #if EFSYS_OPT_FALCON
355 struct {
356 falcon_spi_dev_t enu_fsd[FALCON_SPI_NTYPES];
357 falcon_i2c_t enu_fip;
358 boolean_t enu_i2c_locked;
359 #if EFSYS_OPT_FALCON_NIC_CFG_OVERRIDE
360 const uint8_t *enu_forced_cfg;
361 #endif /* EFSYS_OPT_FALCON_NIC_CFG_OVERRIDE */
362 uint8_t enu_mon_devid;
363 #if EFSYS_OPT_PCIE_TUNE
364 unsigned int enu_nlanes;
365 #endif /* EFSYS_OPT_PCIE_TUNE */
366 uint16_t enu_board_rev;
367 boolean_t enu_internal_sram;
368 uint8_t enu_sram_num_bank;
369 uint8_t enu_sram_bank_size;
370 } falcon;
371 #endif /* EFSYS_OPT_FALCON */
372 #if EFSYS_OPT_SIENA
373 struct {
374 #if EFSYS_OPT_MCDI
375 efx_mcdi_iface_t enu_mip;
376 #endif /* EFSYS_OPT_MCDI */
377 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
378 unsigned int enu_partn_mask;
379 #endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
380 #if EFSYS_OPT_VPD
381 caddr_t enu_svpd;
382 size_t enu_svpd_length;
383 #endif /* EFSYS_OPT_VPD */
384 } siena;
385 #endif /* EFSYS_OPT_SIENA */
386 } en_u;
387 };
388
389
390 #define EFX_NIC_MAGIC 0x02121996
391
392 typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *,
393 const efx_ev_callbacks_t *, void *);
394
395 struct efx_evq_s {
396 uint32_t ee_magic;
397 efx_nic_t *ee_enp;
398 unsigned int ee_index;
399 unsigned int ee_mask;
400 efsys_mem_t *ee_esmp;
401 #if EFSYS_OPT_QSTATS
402 uint32_t ee_stat[EV_NQSTATS];
403 #endif /* EFSYS_OPT_QSTATS */
404 efx_ev_handler_t ee_handler[1 << FSF_AZ_EV_CODE_WIDTH];
405 };
406
407 #define EFX_EVQ_MAGIC 0x08081997
408
409 #define EFX_EVQ_FALCON_TIMER_QUANTUM_NS 4968 /* 621 cycles */
410 #define EFX_EVQ_SIENA_TIMER_QUANTUM_NS 6144 /* 768 cycles */
411
412 struct efx_rxq_s {
413 uint32_t er_magic;
414 efx_nic_t *er_enp;
415 unsigned int er_index;
416 unsigned int er_mask;
417 efsys_mem_t *er_esmp;
418 };
419
420 #define EFX_RXQ_MAGIC 0x15022005
421
422 struct efx_txq_s {
423 uint32_t et_magic;
424 efx_nic_t *et_enp;
425 unsigned int et_index;
426 unsigned int et_mask;
427 efsys_mem_t *et_esmp;
428 #if EFSYS_OPT_QSTATS
429 uint32_t et_stat[TX_NQSTATS];
430 #endif /* EFSYS_OPT_QSTATS */
431 };
432
433 #define EFX_TXQ_MAGIC 0x05092005
434
435 #define EFX_MAC_ADDR_COPY(_dst, _src) \
436 do { \
437 (_dst)[0] = (_src)[0]; \
438 (_dst)[1] = (_src)[1]; \
439 (_dst)[2] = (_src)[2]; \
440 (_dst)[3] = (_src)[3]; \
441 (_dst)[4] = (_src)[4]; \
442 (_dst)[5] = (_src)[5]; \
443 _NOTE(CONSTANTCONDITION) \
444 } while (B_FALSE)
445
446 #if EFSYS_OPT_CHECK_REG
447 #define EFX_CHECK_REG(_enp, _reg) \
448 do { \
449 const char __cs *name = #_reg; \
450 char min = name[4]; \
451 char max = name[5]; \
452 char rev; \
453 \
454 switch ((_enp)->en_family) { \
455 case EFX_FAMILY_FALCON: \
456 rev = 'B'; \
457 break; \
458 \
459 case EFX_FAMILY_SIENA: \
460 rev = 'C'; \
461 break; \
462 \
463 default: \
464 rev = '?'; \
465 break; \
466 } \
467 \
468 EFSYS_ASSERT3S(rev, >=, min); \
469 EFSYS_ASSERT3S(rev, <=, max); \
470 \
471 _NOTE(CONSTANTCONDITION) \
472 } while (B_FALSE)
473 #else
474 #define EFX_CHECK_REG(_enp, _reg) do { \
475 _NOTE(CONSTANTCONDITION) \
476 } while(B_FALSE)
477 #endif
478
479 #define EFX_BAR_READD(_enp, _reg, _edp, _lock) \
480 do { \
481 EFX_CHECK_REG((_enp), (_reg)); \
482 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST, \
483 (_edp), (_lock)); \
484 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg, \
485 uint32_t, _reg ## _OFST, \
486 uint32_t, (_edp)->ed_u32[0]); \
487 _NOTE(CONSTANTCONDITION) \
488 } while (B_FALSE)
489
490 #define EFX_BAR_WRITED(_enp, _reg, _edp, _lock) \
491 do { \
492 EFX_CHECK_REG((_enp), (_reg)); \
493 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg, \
494 uint32_t, _reg ## _OFST, \
495 uint32_t, (_edp)->ed_u32[0]); \
496 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST, \
497 (_edp), (_lock)); \
498 _NOTE(CONSTANTCONDITION) \
499 } while (B_FALSE)
500
501 #define EFX_BAR_READQ(_enp, _reg, _eqp) \
502 do { \
503 EFX_CHECK_REG((_enp), (_reg)); \
504 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST, \
505 (_eqp)); \
506 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg, \
507 uint32_t, _reg ## _OFST, \
508 uint32_t, (_eqp)->eq_u32[1], \
509 uint32_t, (_eqp)->eq_u32[0]); \
510 _NOTE(CONSTANTCONDITION) \
511 } while (B_FALSE)
512
513 #define EFX_BAR_WRITEQ(_enp, _reg, _eqp) \
514 do { \
515 EFX_CHECK_REG((_enp), (_reg)); \
516 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg, \
517 uint32_t, _reg ## _OFST, \
518 uint32_t, (_eqp)->eq_u32[1], \
519 uint32_t, (_eqp)->eq_u32[0]); \
520 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST, \
521 (_eqp)); \
522 _NOTE(CONSTANTCONDITION) \
523 } while (B_FALSE)
524
525 #define EFX_BAR_READO(_enp, _reg, _eop) \
526 do { \
527 EFX_CHECK_REG((_enp), (_reg)); \
528 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST, \
529 (_eop), B_TRUE); \
530 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg, \
531 uint32_t, _reg ## _OFST, \
532 uint32_t, (_eop)->eo_u32[3], \
533 uint32_t, (_eop)->eo_u32[2], \
534 uint32_t, (_eop)->eo_u32[1], \
535 uint32_t, (_eop)->eo_u32[0]); \
536 _NOTE(CONSTANTCONDITION) \
537 } while (B_FALSE)
538
539 #define EFX_BAR_WRITEO(_enp, _reg, _eop) \
540 do { \
541 EFX_CHECK_REG((_enp), (_reg)); \
542 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg, \
543 uint32_t, _reg ## _OFST, \
544 uint32_t, (_eop)->eo_u32[3], \
545 uint32_t, (_eop)->eo_u32[2], \
546 uint32_t, (_eop)->eo_u32[1], \
547 uint32_t, (_eop)->eo_u32[0]); \
548 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST, \
549 (_eop), B_TRUE); \
550 _NOTE(CONSTANTCONDITION) \
551 } while (B_FALSE)
552
553 #define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock) \
554 do { \
555 EFX_CHECK_REG((_enp), (_reg)); \
556 EFSYS_BAR_READD((_enp)->en_esbp, \
557 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
558 (_edp), (_lock)); \
559 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg, \
560 uint32_t, (_index), \
561 uint32_t, _reg ## _OFST, \
562 uint32_t, (_edp)->ed_u32[0]); \
563 _NOTE(CONSTANTCONDITION) \
564 } while (B_FALSE)
565
566 #define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock) \
567 do { \
568 EFX_CHECK_REG((_enp), (_reg)); \
569 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
570 uint32_t, (_index), \
571 uint32_t, _reg ## _OFST, \
572 uint32_t, (_edp)->ed_u32[0]); \
573 EFSYS_BAR_WRITED((_enp)->en_esbp, \
574 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
575 (_edp), (_lock)); \
576 _NOTE(CONSTANTCONDITION) \
577 } while (B_FALSE)
578
579 #define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock) \
580 do { \
581 EFX_CHECK_REG((_enp), (_reg)); \
582 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg, \
583 uint32_t, (_index), \
584 uint32_t, _reg ## _OFST, \
585 uint32_t, (_edp)->ed_u32[0]); \
586 EFSYS_BAR_WRITED((_enp)->en_esbp, \
587 (_reg ## _OFST + \
588 (3 * sizeof (efx_dword_t)) + \
589 ((_index) * _reg ## _STEP)), \
590 (_edp), (_lock)); \
591 _NOTE(CONSTANTCONDITION) \
592 } while (B_FALSE)
593
594 #define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp) \
595 do { \
596 EFX_CHECK_REG((_enp), (_reg)); \
597 EFSYS_BAR_READQ((_enp)->en_esbp, \
598 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
599 (_eqp)); \
600 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg, \
601 uint32_t, (_index), \
602 uint32_t, _reg ## _OFST, \
603 uint32_t, (_eqp)->eq_u32[1], \
604 uint32_t, (_eqp)->eq_u32[0]); \
605 _NOTE(CONSTANTCONDITION) \
606 } while (B_FALSE)
607
608 #define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp) \
609 do { \
610 EFX_CHECK_REG((_enp), (_reg)); \
611 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg, \
612 uint32_t, (_index), \
613 uint32_t, _reg ## _OFST, \
614 uint32_t, (_eqp)->eq_u32[1], \
615 uint32_t, (_eqp)->eq_u32[0]); \
616 EFSYS_BAR_WRITEQ((_enp)->en_esbp, \
617 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
618 (_eqp)); \
619 _NOTE(CONSTANTCONDITION) \
620 } while (B_FALSE)
621
622 #define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop) \
623 do { \
624 EFX_CHECK_REG((_enp), (_reg)); \
625 EFSYS_BAR_READO((_enp)->en_esbp, \
626 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
627 (_eop), B_TRUE); \
628 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg, \
629 uint32_t, (_index), \
630 uint32_t, _reg ## _OFST, \
631 uint32_t, (_eop)->eo_u32[3], \
632 uint32_t, (_eop)->eo_u32[2], \
633 uint32_t, (_eop)->eo_u32[1], \
634 uint32_t, (_eop)->eo_u32[0]); \
635 _NOTE(CONSTANTCONDITION) \
636 } while (B_FALSE)
637
638 #define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop) \
639 do { \
640 EFX_CHECK_REG((_enp), (_reg)); \
641 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg, \
642 uint32_t, (_index), \
643 uint32_t, _reg ## _OFST, \
644 uint32_t, (_eop)->eo_u32[3], \
645 uint32_t, (_eop)->eo_u32[2], \
646 uint32_t, (_eop)->eo_u32[1], \
647 uint32_t, (_eop)->eo_u32[0]); \
648 EFSYS_BAR_WRITEO((_enp)->en_esbp, \
649 (_reg ## _OFST + ((_index) * _reg ## _STEP)), \
650 (_eop), B_TRUE); \
651 _NOTE(CONSTANTCONDITION) \
652 } while (B_FALSE)
653
654 extern __checkReturn int
655 efx_mac_select(
656 __in efx_nic_t *enp);
657
658 extern __checkReturn int
659 efx_phy_probe(
660 __in efx_nic_t *enp);
661
662 extern void
663 efx_phy_unprobe(
664 __in efx_nic_t *enp);
665
666 #if EFSYS_OPT_VPD
667
668 /* VPD utility functions */
669
670 extern __checkReturn int
671 efx_vpd_hunk_length(
672 __in_bcount(size) caddr_t data,
673 __in size_t size,
674 __out size_t *lengthp);
675
676 extern __checkReturn int
677 efx_vpd_hunk_verify(
678 __in_bcount(size) caddr_t data,
679 __in size_t size,
680 __out_opt boolean_t *cksummedp);
681
682 extern __checkReturn int
683 efx_vpd_hunk_reinit(
684 __in caddr_t data,
685 __in size_t size,
686 __in boolean_t wantpid);
687
688 extern __checkReturn int
689 efx_vpd_hunk_get(
690 __in_bcount(size) caddr_t data,
691 __in size_t size,
692 __in efx_vpd_tag_t tag,
693 __in efx_vpd_keyword_t keyword,
694 __out unsigned int *payloadp,
695 __out uint8_t *paylenp);
696
697 extern __checkReturn int
698 efx_vpd_hunk_next(
699 __in_bcount(size) caddr_t data,
700 __in size_t size,
701 __out efx_vpd_tag_t *tagp,
702 __out efx_vpd_keyword_t *keyword,
703 __out_bcount_opt(*paylenp) unsigned int *payloadp,
704 __out_opt uint8_t *paylenp,
705 __inout unsigned int *contp);
706
707 extern __checkReturn int
708 efx_vpd_hunk_set(
709 __in_bcount(size) caddr_t data,
710 __in size_t size,
711 __in efx_vpd_value_t *evvp);
712
713 #endif /* EFSYS_OPT_VPD */
714
715 #if EFSYS_OPT_DIAG
716
717 extern efx_sram_pattern_fn_t __cs __efx_sram_pattern_fns[];
718
719 typedef struct efx_register_set_s {
720 unsigned int address;
721 unsigned int step;
722 unsigned int rows;
723 efx_oword_t mask;
724 } efx_register_set_t;
725
726 extern __checkReturn int
727 efx_nic_test_registers(
728 __in efx_nic_t *enp,
729 __in efx_register_set_t *rsp,
730 __in size_t count);
731
732 extern __checkReturn int
733 efx_nic_test_tables(
734 __in efx_nic_t *enp,
735 __in efx_register_set_t *rsp,
736 __in efx_pattern_type_t pattern,
737 __in size_t count);
738
739 #endif /* EFSYS_OPT_DIAG */
740
741 #ifdef __cplusplus
742 }
743 #endif
744
745 #endif /* _SYS_EFX_IMPL_H */