1 /*-
2 * Copyright 2006-2013 Solarflare Communications Inc. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 */
25
26 #ifndef _SYS_EFX_H
27 #define _SYS_EFX_H
28
29 #include "efsys.h"
30
31 #ifdef __cplusplus
32 extern "C" {
33 #endif
34
35 #define EFX_STATIC_ASSERT(_cond) ((void)sizeof(char[(_cond) ? 1 : -1]))
36
37 #define EFX_ARRAY_SIZE(_array) (sizeof(_array) / sizeof((_array)[0]))
38
39 #ifndef EFSYS_MEM_IS_NULL
40 #define EFSYS_MEM_IS_NULL(_esmp) ((_esmp)->esm_base == NULL)
41 #endif
42
43 typedef enum efx_family_e {
44 EFX_FAMILY_INVALID,
45 EFX_FAMILY_FALCON,
46 EFX_FAMILY_SIENA,
47 EFX_FAMILY_NTYPES
48 } efx_family_t;
49
50 extern __checkReturn int
51 efx_family(
52 __in uint16_t venid,
53 __in uint16_t devid,
54 __out efx_family_t *efp);
55
56 extern __checkReturn int
57 efx_infer_family(
58 __in efsys_bar_t *esbp,
59 __out efx_family_t *efp);
60
61 #define EFX_PCI_VENID_SFC 0x1924
62 #define EFX_PCI_DEVID_FALCON 0x0710
63 #define EFX_PCI_DEVID_BETHPAGE 0x0803
64 #define EFX_PCI_DEVID_SIENA 0x0813
65 #define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810
66
67 #define EFX_MEM_BAR 2
68
69 /* Error codes */
70
71 enum {
72 EFX_ERR_INVALID,
73 EFX_ERR_SRAM_OOB,
74 EFX_ERR_BUFID_DC_OOB,
75 EFX_ERR_MEM_PERR,
76 EFX_ERR_RBUF_OWN,
77 EFX_ERR_TBUF_OWN,
78 EFX_ERR_RDESQ_OWN,
79 EFX_ERR_TDESQ_OWN,
80 EFX_ERR_EVQ_OWN,
81 EFX_ERR_EVFF_OFLO,
82 EFX_ERR_ILL_ADDR,
83 EFX_ERR_SRAM_PERR,
84 EFX_ERR_NCODES
85 };
86
87 /* NIC */
88
89 typedef struct efx_nic_s efx_nic_t;
90
91 extern __checkReturn int
92 efx_nic_create(
93 __in efx_family_t family,
94 __in efsys_identifier_t *esip,
95 __in efsys_bar_t *esbp,
96 __in efsys_lock_t *eslp,
97 __deref_out efx_nic_t **enpp);
98
99 extern __checkReturn int
100 efx_nic_probe(
101 __in efx_nic_t *enp);
102
103 #if EFSYS_OPT_PCIE_TUNE
104
105 extern __checkReturn int
106 efx_nic_pcie_tune(
107 __in efx_nic_t *enp,
108 unsigned int nlanes);
109
110 extern __checkReturn int
111 efx_nic_pcie_extended_sync(
112 __in efx_nic_t *enp);
113
114 #endif /* EFSYS_OPT_PCIE_TUNE */
115
116 extern __checkReturn int
117 efx_nic_init(
118 __in efx_nic_t *enp);
119
120 extern __checkReturn int
121 efx_nic_reset(
122 __in efx_nic_t *enp);
123
124 #if EFSYS_OPT_DIAG
125
126 extern __checkReturn int
127 efx_nic_register_test(
128 __in efx_nic_t *enp);
129
130 #endif /* EFSYS_OPT_DIAG */
131
132 extern void
133 efx_nic_fini(
134 __in efx_nic_t *enp);
135
136 extern void
137 efx_nic_unprobe(
138 __in efx_nic_t *enp);
139
140 extern void
141 efx_nic_destroy(
142 __in efx_nic_t *enp);
143
144 #if EFSYS_OPT_MCDI
145
146 typedef struct efx_mcdi_req_s efx_mcdi_req_t;
147
148 typedef enum efx_mcdi_exception_e {
149 EFX_MCDI_EXCEPTION_MC_REBOOT,
150 EFX_MCDI_EXCEPTION_MC_BADASSERT,
151 } efx_mcdi_exception_t;
152
153 typedef struct efx_mcdi_transport_s {
154 void *emt_context;
155 void (*emt_execute)(void *, efx_mcdi_req_t *);
156 void (*emt_ev_cpl)(void *);
157 void (*emt_exception)(void *, efx_mcdi_exception_t);
158 } efx_mcdi_transport_t;
159
160 extern __checkReturn int
161 efx_mcdi_init(
162 __in efx_nic_t *enp,
163 __in const efx_mcdi_transport_t *mtp);
164
165 extern __checkReturn int
166 efx_mcdi_reboot(
167 __in efx_nic_t *enp);
168
169 extern void
170 efx_mcdi_request_start(
171 __in efx_nic_t *enp,
172 __in efx_mcdi_req_t *emrp,
173 __in boolean_t ev_cpl);
174
175 extern __checkReturn boolean_t
176 efx_mcdi_request_poll(
177 __in efx_nic_t *enp);
178
179 extern __checkReturn boolean_t
180 efx_mcdi_request_abort(
181 __in efx_nic_t *enp);
182
183 extern void
184 efx_mcdi_fini(
185 __in efx_nic_t *enp);
186
187 #endif /* EFSYS_OPT_MCDI */
188
189 /* INTR */
190
191 #define EFX_NINTR_FALCON 64
192 #define EFX_NINTR_SIENA 1024
193
194 typedef enum efx_intr_type_e {
195 EFX_INTR_INVALID = 0,
196 EFX_INTR_LINE,
197 EFX_INTR_MESSAGE,
198 EFX_INTR_NTYPES
199 } efx_intr_type_t;
200
201 #define EFX_INTR_SIZE (sizeof (efx_oword_t))
202
203 extern __checkReturn int
204 efx_intr_init(
205 __in efx_nic_t *enp,
206 __in efx_intr_type_t type,
207 __in efsys_mem_t *esmp);
208
209 extern void
210 efx_intr_enable(
211 __in efx_nic_t *enp);
212
213 extern void
214 efx_intr_disable(
215 __in efx_nic_t *enp);
216
217 extern void
218 efx_intr_disable_unlocked(
219 __in efx_nic_t *enp);
220
221 #define EFX_INTR_NEVQS 32
222
223 extern __checkReturn int
224 efx_intr_trigger(
225 __in efx_nic_t *enp,
226 __in unsigned int level);
227
228 extern void
229 efx_intr_status_line(
230 __in efx_nic_t *enp,
231 __out boolean_t *fatalp,
232 __out uint32_t *maskp);
233
234 extern void
235 efx_intr_status_message(
236 __in efx_nic_t *enp,
237 __in unsigned int message,
238 __out boolean_t *fatalp);
239
240 extern void
241 efx_intr_fatal(
242 __in efx_nic_t *enp);
243
244 extern void
245 efx_intr_fini(
246 __in efx_nic_t *enp);
247
248 /* MAC */
249
250 #if EFSYS_OPT_MAC_STATS
251
252 /* START MKCONFIG GENERATED EfxHeaderMacBlock bb8d39428b6fdcf5 */
253 typedef enum efx_mac_stat_e {
254 EFX_MAC_RX_OCTETS,
255 EFX_MAC_RX_PKTS,
256 EFX_MAC_RX_UNICST_PKTS,
257 EFX_MAC_RX_MULTICST_PKTS,
258 EFX_MAC_RX_BRDCST_PKTS,
259 EFX_MAC_RX_PAUSE_PKTS,
260 EFX_MAC_RX_LE_64_PKTS,
261 EFX_MAC_RX_65_TO_127_PKTS,
262 EFX_MAC_RX_128_TO_255_PKTS,
263 EFX_MAC_RX_256_TO_511_PKTS,
264 EFX_MAC_RX_512_TO_1023_PKTS,
265 EFX_MAC_RX_1024_TO_15XX_PKTS,
266 EFX_MAC_RX_GE_15XX_PKTS,
267 EFX_MAC_RX_ERRORS,
268 EFX_MAC_RX_FCS_ERRORS,
269 EFX_MAC_RX_DROP_EVENTS,
270 EFX_MAC_RX_FALSE_CARRIER_ERRORS,
271 EFX_MAC_RX_SYMBOL_ERRORS,
272 EFX_MAC_RX_ALIGN_ERRORS,
273 EFX_MAC_RX_INTERNAL_ERRORS,
274 EFX_MAC_RX_JABBER_PKTS,
275 EFX_MAC_RX_LANE0_CHAR_ERR,
276 EFX_MAC_RX_LANE1_CHAR_ERR,
277 EFX_MAC_RX_LANE2_CHAR_ERR,
278 EFX_MAC_RX_LANE3_CHAR_ERR,
279 EFX_MAC_RX_LANE0_DISP_ERR,
280 EFX_MAC_RX_LANE1_DISP_ERR,
281 EFX_MAC_RX_LANE2_DISP_ERR,
282 EFX_MAC_RX_LANE3_DISP_ERR,
283 EFX_MAC_RX_MATCH_FAULT,
284 EFX_MAC_RX_NODESC_DROP_CNT,
285 EFX_MAC_TX_OCTETS,
286 EFX_MAC_TX_PKTS,
287 EFX_MAC_TX_UNICST_PKTS,
288 EFX_MAC_TX_MULTICST_PKTS,
289 EFX_MAC_TX_BRDCST_PKTS,
290 EFX_MAC_TX_PAUSE_PKTS,
291 EFX_MAC_TX_LE_64_PKTS,
292 EFX_MAC_TX_65_TO_127_PKTS,
293 EFX_MAC_TX_128_TO_255_PKTS,
294 EFX_MAC_TX_256_TO_511_PKTS,
295 EFX_MAC_TX_512_TO_1023_PKTS,
296 EFX_MAC_TX_1024_TO_15XX_PKTS,
297 EFX_MAC_TX_GE_15XX_PKTS,
298 EFX_MAC_TX_ERRORS,
299 EFX_MAC_TX_SGL_COL_PKTS,
300 EFX_MAC_TX_MULT_COL_PKTS,
301 EFX_MAC_TX_EX_COL_PKTS,
302 EFX_MAC_TX_LATE_COL_PKTS,
303 EFX_MAC_TX_DEF_PKTS,
304 EFX_MAC_TX_EX_DEF_PKTS,
305 EFX_MAC_NSTATS
306 } efx_mac_stat_t;
307
308 /* END MKCONFIG GENERATED EfxHeaderMacBlock */
309
310 #endif /* EFSYS_OPT_MAC_STATS */
311
312 typedef enum efx_link_mode_e {
313 EFX_LINK_UNKNOWN = 0,
314 EFX_LINK_DOWN,
315 EFX_LINK_10HDX,
316 EFX_LINK_10FDX,
317 EFX_LINK_100HDX,
318 EFX_LINK_100FDX,
319 EFX_LINK_1000HDX,
320 EFX_LINK_1000FDX,
321 EFX_LINK_10000FDX,
322 EFX_LINK_NMODES
323 } efx_link_mode_t;
324
325 #define EFX_MAC_SDU_MAX 9202
326
327 #define EFX_MAC_PDU(_sdu) \
328 P2ROUNDUP(((_sdu) \
329 + /* EtherII */ 14 \
330 + /* VLAN */ 4 \
331 + /* CRC */ 4 \
332 + /* bug16011 */ 16), \
333 (1 << 3))
334
335 #define EFX_MAC_PDU_MIN 60
336 #define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX)
337
338 extern __checkReturn int
339 efx_mac_pdu_set(
340 __in efx_nic_t *enp,
341 __in size_t pdu);
342
343 extern __checkReturn int
344 efx_mac_addr_set(
345 __in efx_nic_t *enp,
346 __in uint8_t *addr);
347
348 extern __checkReturn int
349 efx_mac_filter_set(
350 __in efx_nic_t *enp,
351 __in boolean_t unicst,
352 __in boolean_t brdcst);
353
354 extern __checkReturn int
355 efx_mac_drain(
356 __in efx_nic_t *enp,
357 __in boolean_t enabled);
358
359 extern __checkReturn int
360 efx_mac_up(
361 __in efx_nic_t *enp,
362 __out boolean_t *mac_upp);
363
364 #define EFX_FCNTL_RESPOND 0x00000001
365 #define EFX_FCNTL_GENERATE 0x00000002
366
367 extern __checkReturn int
368 efx_mac_fcntl_set(
369 __in efx_nic_t *enp,
370 __in unsigned int fcntl,
371 __in boolean_t autoneg);
372
373 extern void
374 efx_mac_fcntl_get(
375 __in efx_nic_t *enp,
376 __out unsigned int *fcntl_wantedp,
377 __out unsigned int *fcntl_linkp);
378
379 #define EFX_MAC_HASH_BITS (1 << 8)
380
381 extern __checkReturn int
382 efx_mac_hash_set(
383 __in efx_nic_t *enp,
384 __in_ecount(EFX_MAC_HASH_BITS) unsigned int const *bucket);
385
386 #if EFSYS_OPT_MAC_STATS
387
388 #if EFSYS_OPT_NAMES
389
390 extern __checkReturn const char __cs *
391 efx_mac_stat_name(
392 __in efx_nic_t *enp,
393 __in unsigned int id);
394
395 #endif /* EFSYS_OPT_NAMES */
396
397 #define EFX_MAC_STATS_SIZE 0x400
398
399 /*
400 * Upload mac statistics supported by the hardware into the given buffer.
401 *
402 * The reference buffer must be at least %EFX_MAC_STATS_SIZE bytes,
403 * and page aligned.
404 *
405 * The hardware will only DMA statistics that it understands (of course).
406 * Drivers should not make any assumptions about which statistics are
407 * supported, especially when the statistics are generated by firmware.
408 *
409 * Thus, drivers should zero this buffer before use, so that not-understood
410 * statistics read back as zero.
411 */
412 extern __checkReturn int
413 efx_mac_stats_upload(
414 __in efx_nic_t *enp,
415 __in efsys_mem_t *esmp);
416
417 extern __checkReturn int
418 efx_mac_stats_periodic(
419 __in efx_nic_t *enp,
420 __in efsys_mem_t *esmp,
421 __in uint16_t period_ms,
422 __in boolean_t events);
423
424 extern __checkReturn int
425 efx_mac_stats_update(
426 __in efx_nic_t *enp,
427 __in efsys_mem_t *esmp,
428 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
429 __out_opt uint32_t *generationp);
430
431 #endif /* EFSYS_OPT_MAC_STATS */
432
433 /* MON */
434
435 typedef enum efx_mon_type_e {
436 EFX_MON_INVALID = 0,
437 EFX_MON_NULL,
438 EFX_MON_LM87,
439 EFX_MON_MAX6647,
440 EFX_MON_SFC90X0,
441 EFX_MON_NTYPES
442 } efx_mon_type_t;
443
444 #if EFSYS_OPT_NAMES
445
446 extern const char __cs *
447 efx_mon_name(
448 __in efx_nic_t *enp);
449
450 #endif /* EFSYS_OPT_NAMES */
451
452 extern __checkReturn int
453 efx_mon_init(
454 __in efx_nic_t *enp);
455
456 #if EFSYS_OPT_MON_STATS
457
458 #define EFX_MON_STATS_SIZE 0x100
459
460 /* START MKCONFIG GENERATED MonitorHeaderStatsBlock 2a60d293f55d0285 */
461 typedef enum efx_mon_stat_e {
462 EFX_MON_STAT_2_5V,
463 EFX_MON_STAT_VCCP1,
464 EFX_MON_STAT_VCC,
465 EFX_MON_STAT_5V,
466 EFX_MON_STAT_12V,
467 EFX_MON_STAT_VCCP2,
468 EFX_MON_STAT_EXT_TEMP,
469 EFX_MON_STAT_INT_TEMP,
470 EFX_MON_STAT_AIN1,
471 EFX_MON_STAT_AIN2,
472 EFX_MON_STAT_INT_COOLING,
473 EFX_MON_STAT_EXT_COOLING,
474 EFX_MON_STAT_1V,
475 EFX_MON_STAT_1_2V,
476 EFX_MON_STAT_1_8V,
477 EFX_MON_STAT_3_3V,
478 EFX_MON_STAT_1_2VA,
479 EFX_MON_STAT_VREF,
480 EFX_MON_NSTATS
481 } efx_mon_stat_t;
482
483 /* END MKCONFIG GENERATED MonitorHeaderStatsBlock */
484
485 typedef enum efx_mon_stat_state_e {
486 EFX_MON_STAT_STATE_OK = 0,
487 EFX_MON_STAT_STATE_WARNING = 1,
488 EFX_MON_STAT_STATE_FATAL = 2,
489 EFX_MON_STAT_STATE_BROKEN = 3,
490 } efx_mon_stat_state_t;
491
492 typedef struct efx_mon_stat_value_t {
493 uint16_t emsv_value;
494 uint16_t emsv_state;
495 } efx_mon_stat_value_t;
496
497 #if EFSYS_OPT_NAMES
498
499 extern const char __cs *
500 efx_mon_stat_name(
501 __in efx_nic_t *enp,
502 __in efx_mon_stat_t id);
503
504 #endif /* EFSYS_OPT_NAMES */
505
506 extern __checkReturn int
507 efx_mon_stats_update(
508 __in efx_nic_t *enp,
509 __in efsys_mem_t *esmp,
510 __out_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values);
511
512 #endif /* EFSYS_OPT_MON_STATS */
513
514 extern void
515 efx_mon_fini(
516 __in efx_nic_t *enp);
517
518 /* PHY */
519
520 #define PMA_PMD_MMD 1
521 #define PCS_MMD 3
522 #define PHY_XS_MMD 4
523 #define DTE_XS_MMD 5
524 #define AN_MMD 7
525 #define CL22EXT_MMD 29
526
527 #define MAXMMD ((1 << 5) - 1)
528
529 /* PHY types */
530 #define EFX_PHY_NULL 0x0
531 #define EFX_PHY_TXC43128 0x1
532 #define EFX_PHY_SFX7101 0x3
533 #define EFX_PHY_QT2022C2 0x4
534 #define EFX_PHY_SFT9001A 0x8
535 #define EFX_PHY_QT2025C 0x9
536 #define EFX_PHY_SFT9001B 0xa
537 #define EFX_PHY_QLX111V 0xc
538
539 extern __checkReturn int
540 efx_phy_verify(
541 __in efx_nic_t *enp);
542
543 #if EFSYS_OPT_PHY_LED_CONTROL
544
545 typedef enum efx_phy_led_mode_e {
546 EFX_PHY_LED_DEFAULT = 0,
547 EFX_PHY_LED_OFF,
548 EFX_PHY_LED_ON,
549 EFX_PHY_LED_FLASH,
550 EFX_PHY_LED_NMODES
551 } efx_phy_led_mode_t;
552
553 extern __checkReturn int
554 efx_phy_led_set(
555 __in efx_nic_t *enp,
556 __in efx_phy_led_mode_t mode);
557
558 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
559
560 extern __checkReturn int
561 efx_port_init(
562 __in efx_nic_t *enp);
563
564 #if EFSYS_OPT_LOOPBACK
565
566 typedef enum efx_loopback_type_e {
567 EFX_LOOPBACK_OFF = 0,
568 EFX_LOOPBACK_DATA = 1,
569 EFX_LOOPBACK_GMAC = 2,
570 EFX_LOOPBACK_XGMII = 3,
571 EFX_LOOPBACK_XGXS = 4,
572 EFX_LOOPBACK_XAUI = 5,
573 EFX_LOOPBACK_GMII = 6,
574 EFX_LOOPBACK_SGMII = 7,
575 EFX_LOOPBACK_XGBR = 8,
576 EFX_LOOPBACK_XFI = 9,
577 EFX_LOOPBACK_XAUI_FAR = 10,
578 EFX_LOOPBACK_GMII_FAR = 11,
579 EFX_LOOPBACK_SGMII_FAR = 12,
580 EFX_LOOPBACK_XFI_FAR = 13,
581 EFX_LOOPBACK_GPHY = 14,
582 EFX_LOOPBACK_PHY_XS = 15,
583 EFX_LOOPBACK_PCS = 16,
584 EFX_LOOPBACK_PMA_PMD = 17,
585 EFX_LOOPBACK_NTYPES
586 } efx_loopback_type_t;
587
588 #define EFX_LOOPBACK_MAC_MASK \
589 ((1 << EFX_LOOPBACK_DATA) | \
590 (1 << EFX_LOOPBACK_GMAC) | \
591 (1 << EFX_LOOPBACK_XGMII) | \
592 (1 << EFX_LOOPBACK_XGXS) | \
593 (1 << EFX_LOOPBACK_XAUI) | \
594 (1 << EFX_LOOPBACK_GMII) | \
595 (1 << EFX_LOOPBACK_SGMII) | \
596 (1 << EFX_LOOPBACK_XGBR) | \
597 (1 << EFX_LOOPBACK_XFI) | \
598 (1 << EFX_LOOPBACK_XAUI_FAR) | \
599 (1 << EFX_LOOPBACK_GMII_FAR) | \
600 (1 << EFX_LOOPBACK_SGMII_FAR) | \
601 (1 << EFX_LOOPBACK_XFI_FAR))
602
603 #define EFX_LOOPBACK_MASK \
604 ((1 << EFX_LOOPBACK_NTYPES) - 1)
605
606 extern __checkReturn int
607 efx_port_loopback_set(
608 __in efx_nic_t *enp,
609 __in efx_link_mode_t link_mode,
610 __in efx_loopback_type_t type);
611
612 #if EFSYS_OPT_NAMES
613
614 extern __checkReturn const char __cs *
615 efx_loopback_type_name(
616 __in efx_nic_t *enp,
617 __in efx_loopback_type_t type);
618
619 #endif /* EFSYS_OPT_NAMES */
620
621 #endif /* EFSYS_OPT_LOOPBACK */
622
623 extern __checkReturn int
624 efx_port_poll(
625 __in efx_nic_t *enp,
626 __out efx_link_mode_t *link_modep);
627
628 extern void
629 efx_port_fini(
630 __in efx_nic_t *enp);
631
632 typedef enum efx_phy_cap_type_e {
633 EFX_PHY_CAP_INVALID = 0,
634 EFX_PHY_CAP_10HDX,
635 EFX_PHY_CAP_10FDX,
636 EFX_PHY_CAP_100HDX,
637 EFX_PHY_CAP_100FDX,
638 EFX_PHY_CAP_1000HDX,
639 EFX_PHY_CAP_1000FDX,
640 EFX_PHY_CAP_10000FDX,
641 EFX_PHY_CAP_PAUSE,
642 EFX_PHY_CAP_ASYM,
643 EFX_PHY_CAP_AN,
644 EFX_PHY_CAP_NTYPES
645 } efx_phy_cap_type_t;
646
647
648 #define EFX_PHY_CAP_CURRENT 0x00000000
649 #define EFX_PHY_CAP_DEFAULT 0x00000001
650 #define EFX_PHY_CAP_PERM 0x00000002
651
652 extern void
653 efx_phy_adv_cap_get(
654 __in efx_nic_t *enp,
655 __in uint32_t flag,
656 __out uint32_t *maskp);
657
658 extern __checkReturn int
659 efx_phy_adv_cap_set(
660 __in efx_nic_t *enp,
661 __in uint32_t mask);
662
663 extern void
664 efx_phy_lp_cap_get(
665 __in efx_nic_t *enp,
666 __out uint32_t *maskp);
667
668 extern __checkReturn int
669 efx_phy_oui_get(
670 __in efx_nic_t *enp,
671 __out uint32_t *ouip);
672
673 typedef enum efx_phy_media_type_e {
674 EFX_PHY_MEDIA_INVALID = 0,
675 EFX_PHY_MEDIA_XAUI,
676 EFX_PHY_MEDIA_CX4,
677 EFX_PHY_MEDIA_KX4,
678 EFX_PHY_MEDIA_XFP,
679 EFX_PHY_MEDIA_SFP_PLUS,
680 EFX_PHY_MEDIA_BASE_T,
681 EFX_PHY_MEDIA_NTYPES
682 } efx_phy_media_type_t;
683
684 /* Get the type of medium currently used. If the board has ports for
685 * modules, a module is present, and we recognise the media type of
686 * the module, then this will be the media type of the module.
687 * Otherwise it will be the media type of the port.
688 */
689 extern void
690 efx_phy_media_type_get(
691 __in efx_nic_t *enp,
692 __out efx_phy_media_type_t *typep);
693
694 #if EFSYS_OPT_PHY_STATS
695
696 /* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */
697 typedef enum efx_phy_stat_e {
698 EFX_PHY_STAT_OUI,
699 EFX_PHY_STAT_PMA_PMD_LINK_UP,
700 EFX_PHY_STAT_PMA_PMD_RX_FAULT,
701 EFX_PHY_STAT_PMA_PMD_TX_FAULT,
702 EFX_PHY_STAT_PMA_PMD_REV_A,
703 EFX_PHY_STAT_PMA_PMD_REV_B,
704 EFX_PHY_STAT_PMA_PMD_REV_C,
705 EFX_PHY_STAT_PMA_PMD_REV_D,
706 EFX_PHY_STAT_PCS_LINK_UP,
707 EFX_PHY_STAT_PCS_RX_FAULT,
708 EFX_PHY_STAT_PCS_TX_FAULT,
709 EFX_PHY_STAT_PCS_BER,
710 EFX_PHY_STAT_PCS_BLOCK_ERRORS,
711 EFX_PHY_STAT_PHY_XS_LINK_UP,
712 EFX_PHY_STAT_PHY_XS_RX_FAULT,
713 EFX_PHY_STAT_PHY_XS_TX_FAULT,
714 EFX_PHY_STAT_PHY_XS_ALIGN,
715 EFX_PHY_STAT_PHY_XS_SYNC_A,
716 EFX_PHY_STAT_PHY_XS_SYNC_B,
717 EFX_PHY_STAT_PHY_XS_SYNC_C,
718 EFX_PHY_STAT_PHY_XS_SYNC_D,
719 EFX_PHY_STAT_AN_LINK_UP,
720 EFX_PHY_STAT_AN_MASTER,
721 EFX_PHY_STAT_AN_LOCAL_RX_OK,
722 EFX_PHY_STAT_AN_REMOTE_RX_OK,
723 EFX_PHY_STAT_CL22EXT_LINK_UP,
724 EFX_PHY_STAT_SNR_A,
725 EFX_PHY_STAT_SNR_B,
726 EFX_PHY_STAT_SNR_C,
727 EFX_PHY_STAT_SNR_D,
728 EFX_PHY_STAT_PMA_PMD_SIGNAL_A,
729 EFX_PHY_STAT_PMA_PMD_SIGNAL_B,
730 EFX_PHY_STAT_PMA_PMD_SIGNAL_C,
731 EFX_PHY_STAT_PMA_PMD_SIGNAL_D,
732 EFX_PHY_STAT_AN_COMPLETE,
733 EFX_PHY_STAT_PMA_PMD_REV_MAJOR,
734 EFX_PHY_STAT_PMA_PMD_REV_MINOR,
735 EFX_PHY_STAT_PMA_PMD_REV_MICRO,
736 EFX_PHY_STAT_PCS_FW_VERSION_0,
737 EFX_PHY_STAT_PCS_FW_VERSION_1,
738 EFX_PHY_STAT_PCS_FW_VERSION_2,
739 EFX_PHY_STAT_PCS_FW_VERSION_3,
740 EFX_PHY_STAT_PCS_FW_BUILD_YY,
741 EFX_PHY_STAT_PCS_FW_BUILD_MM,
742 EFX_PHY_STAT_PCS_FW_BUILD_DD,
743 EFX_PHY_STAT_PCS_OP_MODE,
744 EFX_PHY_NSTATS
745 } efx_phy_stat_t;
746
747 /* END MKCONFIG GENERATED PhyHeaderStatsBlock */
748
749 #if EFSYS_OPT_NAMES
750
751 extern const char __cs *
752 efx_phy_stat_name(
753 __in efx_nic_t *enp,
754 __in efx_phy_stat_t stat);
755
756 #endif /* EFSYS_OPT_NAMES */
757
758 #define EFX_PHY_STATS_SIZE 0x100
759
760 extern __checkReturn int
761 efx_phy_stats_update(
762 __in efx_nic_t *enp,
763 __in efsys_mem_t *esmp,
764 __out_ecount(EFX_PHY_NSTATS) uint32_t *stat);
765
766 #endif /* EFSYS_OPT_PHY_STATS */
767
768 #if EFSYS_OPT_PHY_PROPS
769
770 #if EFSYS_OPT_NAMES
771
772 extern const char __cs *
773 efx_phy_prop_name(
774 __in efx_nic_t *enp,
775 __in unsigned int id);
776
777 #endif /* EFSYS_OPT_NAMES */
778
779 #define EFX_PHY_PROP_DEFAULT 0x00000001
780
781 extern __checkReturn int
782 efx_phy_prop_get(
783 __in efx_nic_t *enp,
784 __in unsigned int id,
785 __in uint32_t flags,
786 __out uint32_t *valp);
787
788 extern __checkReturn int
789 efx_phy_prop_set(
790 __in efx_nic_t *enp,
791 __in unsigned int id,
792 __in uint32_t val);
793
794 #endif /* EFSYS_OPT_PHY_PROPS */
795
796 #if EFSYS_OPT_PHY_BIST
797
798 typedef enum efx_phy_bist_type_e {
799 EFX_PHY_BIST_TYPE_UNKNOWN,
800 EFX_PHY_BIST_TYPE_NORMAL,
801 EFX_PHY_BIST_TYPE_CABLE_SHORT,
802 EFX_PHY_BIST_TYPE_CABLE_LONG,
803 EFX_PHY_BIST_TYPE_NTYPES,
804 } efx_phy_bist_type_t;
805
806 typedef enum efx_phy_bist_result_e {
807 EFX_PHY_BIST_RESULT_UNKNOWN,
808 EFX_PHY_BIST_RESULT_RUNNING,
809 EFX_PHY_BIST_RESULT_PASSED,
810 EFX_PHY_BIST_RESULT_FAILED,
811 } efx_phy_bist_result_t;
812
813 typedef enum efx_phy_cable_status_e {
814 EFX_PHY_CABLE_STATUS_OK,
815 EFX_PHY_CABLE_STATUS_INVALID,
816 EFX_PHY_CABLE_STATUS_OPEN,
817 EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT,
818 EFX_PHY_CABLE_STATUS_INTERPAIRSHORT,
819 EFX_PHY_CABLE_STATUS_BUSY,
820 } efx_phy_cable_status_t;
821
822 typedef enum efx_phy_bist_value_e {
823 EFX_PHY_BIST_CABLE_LENGTH_A,
824 EFX_PHY_BIST_CABLE_LENGTH_B,
825 EFX_PHY_BIST_CABLE_LENGTH_C,
826 EFX_PHY_BIST_CABLE_LENGTH_D,
827 EFX_PHY_BIST_CABLE_STATUS_A,
828 EFX_PHY_BIST_CABLE_STATUS_B,
829 EFX_PHY_BIST_CABLE_STATUS_C,
830 EFX_PHY_BIST_CABLE_STATUS_D,
831 EFX_PHY_BIST_FAULT_CODE,
832 EFX_PHY_BIST_NVALUES,
833 } efx_phy_bist_value_t;
834
835 extern __checkReturn int
836 efx_phy_bist_start(
837 __in efx_nic_t *enp,
838 __in efx_phy_bist_type_t type);
839
840 extern __checkReturn int
841 efx_phy_bist_poll(
842 __in efx_nic_t *enp,
843 __in efx_phy_bist_type_t type,
844 __out efx_phy_bist_result_t *resultp,
845 __out_opt uint32_t *value_maskp,
846 __out_ecount_opt(count) unsigned long *valuesp,
847 __in size_t count);
848
849 extern void
850 efx_phy_bist_stop(
851 __in efx_nic_t *enp,
852 __in efx_phy_bist_type_t type);
853
854 #endif /* EFSYS_OPT_PHY_BIST */
855
856 #define EFX_FEATURE_IPV6 0x00000001
857 #define EFX_FEATURE_LFSR_HASH_INSERT 0x00000002
858 #define EFX_FEATURE_LINK_EVENTS 0x00000004
859 #define EFX_FEATURE_PERIODIC_MAC_STATS 0x00000008
860 #define EFX_FEATURE_WOL 0x00000010
861 #define EFX_FEATURE_MCDI 0x00000020
862 #define EFX_FEATURE_LOOKAHEAD_SPLIT 0x00000040
863 #define EFX_FEATURE_MAC_HEADER_FILTERS 0x00000080
864 #define EFX_FEATURE_TURBO 0x00000100
865
866 typedef struct efx_nic_cfg_s {
867 uint32_t enc_board_type;
868 uint32_t enc_phy_type;
869 #if EFSYS_OPT_NAMES
870 char enc_phy_name[21];
871 #endif
872 char enc_phy_revision[21];
873 efx_mon_type_t enc_mon_type;
874 #if EFSYS_OPT_MON_STATS
875 uint32_t enc_mon_stat_mask;
876 #endif
877 unsigned int enc_features;
878 uint8_t enc_mac_addr[6];
879 uint8_t enc_port;
880 uint32_t enc_evq_limit;
881 uint32_t enc_txq_limit;
882 uint32_t enc_rxq_limit;
883 uint32_t enc_buftbl_limit;
884 uint32_t enc_evq_timer_quantum_ns;
885 uint32_t enc_evq_timer_max_us;
886 uint32_t enc_clk_mult;
887 #if EFSYS_OPT_LOOPBACK
888 uint32_t enc_loopback_types[EFX_LINK_NMODES];
889 #endif /* EFSYS_OPT_LOOPBACK */
890 #if EFSYS_OPT_PHY_FLAGS
891 uint32_t enc_phy_flags_mask;
892 #endif /* EFSYS_OPT_PHY_FLAGS */
893 #if EFSYS_OPT_PHY_LED_CONTROL
894 uint32_t enc_led_mask;
895 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
896 #if EFSYS_OPT_PHY_STATS
897 uint64_t enc_phy_stat_mask;
898 #endif /* EFSYS_OPT_PHY_STATS */
899 #if EFSYS_OPT_PHY_PROPS
900 unsigned int enc_phy_nprops;
901 #endif /* EFSYS_OPT_PHY_PROPS */
902 #if EFSYS_OPT_SIENA
903 uint8_t enc_siena_channel;
904 #if EFSYS_OPT_PHY_STATS
905 uint32_t enc_siena_phy_stat_mask;
906 #endif /* EFSYS_OPT_PHY_STATS */
907 #if EFSYS_OPT_MON_STATS
908 uint32_t enc_siena_mon_stat_mask;
909 #endif /* EFSYS_OPT_MON_STATS */
910 #endif /* EFSYS_OPT_SIENA */
911 #if EFSYS_OPT_PHY_BIST
912 uint32_t enc_bist_mask;
913 #endif /* EFSYS_OPT_PHY_BIST */
914 } efx_nic_cfg_t;
915
916 extern const efx_nic_cfg_t *
917 efx_nic_cfg_get(
918 __in efx_nic_t *enp);
919
920 #if EFSYS_OPT_VPD
921
922 typedef enum efx_vpd_tag_e {
923 EFX_VPD_ID = 0x02,
924 EFX_VPD_END = 0x0f,
925 EFX_VPD_RO = 0x10,
926 EFX_VPD_RW = 0x11,
927 } efx_vpd_tag_t;
928
929 typedef uint16_t efx_vpd_keyword_t;
930
931 typedef struct efx_vpd_value_s {
932 efx_vpd_tag_t evv_tag;
933 efx_vpd_keyword_t evv_keyword;
934 uint8_t evv_length;
935 uint8_t evv_value[0x100];
936 } efx_vpd_value_t;
937
938
939 #define EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8))
940
941 extern __checkReturn int
942 efx_vpd_init(
943 __in efx_nic_t *enp);
944
945 extern __checkReturn int
946 efx_vpd_size(
947 __in efx_nic_t *enp,
948 __out size_t *sizep);
949
950 extern __checkReturn int
951 efx_vpd_read(
952 __in efx_nic_t *enp,
953 __out_bcount(size) caddr_t data,
954 __in size_t size);
955
956 extern __checkReturn int
957 efx_vpd_verify(
958 __in efx_nic_t *enp,
959 __in_bcount(size) caddr_t data,
960 __in size_t size);
961
962 extern __checkReturn int
963 efx_vpd_reinit(
964 __in efx_nic_t *enp,
965 __in_bcount(size) caddr_t data,
966 __in size_t size);
967
968 extern __checkReturn int
969 efx_vpd_get(
970 __in efx_nic_t *enp,
971 __in_bcount(size) caddr_t data,
972 __in size_t size,
973 __inout efx_vpd_value_t *evvp);
974
975 extern __checkReturn int
976 efx_vpd_set(
977 __in efx_nic_t *enp,
978 __inout_bcount(size) caddr_t data,
979 __in size_t size,
980 __in efx_vpd_value_t *evvp);
981
982 extern __checkReturn int
983 efx_vpd_next(
984 __in efx_nic_t *enp,
985 __inout_bcount(size) caddr_t data,
986 __in size_t size,
987 __out efx_vpd_value_t *evvp,
988 __inout unsigned int *contp);
989
990 extern __checkReturn int
991 efx_vpd_write(
992 __in efx_nic_t *enp,
993 __in_bcount(size) caddr_t data,
994 __in size_t size);
995
996 extern void
997 efx_vpd_fini(
998 __in efx_nic_t *enp);
999
1000 #endif /* EFSYS_OPT_VPD */
1001
1002 /* NVRAM */
1003
1004 #if EFSYS_OPT_NVRAM
1005
1006 typedef enum efx_nvram_type_e {
1007 EFX_NVRAM_INVALID = 0,
1008 EFX_NVRAM_BOOTROM,
1009 EFX_NVRAM_BOOTROM_CFG,
1010 EFX_NVRAM_MC_FIRMWARE,
1011 EFX_NVRAM_MC_GOLDEN,
1012 EFX_NVRAM_PHY,
1013 EFX_NVRAM_NULLPHY,
1014 EFX_NVRAM_FPGA,
1015 EFX_NVRAM_NTYPES,
1016 } efx_nvram_type_t;
1017
1018 extern __checkReturn int
1019 efx_nvram_init(
1020 __in efx_nic_t *enp);
1021
1022 #if EFSYS_OPT_DIAG
1023
1024 extern __checkReturn int
1025 efx_nvram_test(
1026 __in efx_nic_t *enp);
1027
1028 #endif /* EFSYS_OPT_DIAG */
1029
1030 extern __checkReturn int
1031 efx_nvram_size(
1032 __in efx_nic_t *enp,
1033 __in efx_nvram_type_t type,
1034 __out size_t *sizep);
1035
1036 extern __checkReturn int
1037 efx_nvram_rw_start(
1038 __in efx_nic_t *enp,
1039 __in efx_nvram_type_t type,
1040 __out_opt size_t *pref_chunkp);
1041
1042 extern void
1043 efx_nvram_rw_finish(
1044 __in efx_nic_t *enp,
1045 __in efx_nvram_type_t type);
1046
1047 extern __checkReturn int
1048 efx_nvram_get_version(
1049 __in efx_nic_t *enp,
1050 __in efx_nvram_type_t type,
1051 __out uint32_t *subtypep,
1052 __out_ecount(4) uint16_t version[4]);
1053
1054 extern __checkReturn int
1055 efx_nvram_read_chunk(
1056 __in efx_nic_t *enp,
1057 __in efx_nvram_type_t type,
1058 __in unsigned int offset,
1059 __out_bcount(size) caddr_t data,
1060 __in size_t size);
1061
1062 extern __checkReturn int
1063 efx_nvram_set_version(
1064 __in efx_nic_t *enp,
1065 __in efx_nvram_type_t type,
1066 __out uint16_t version[4]);
1067
1068 extern __checkReturn int
1069 efx_nvram_erase(
1070 __in efx_nic_t *enp,
1071 __in efx_nvram_type_t type);
1072
1073 extern __checkReturn int
1074 efx_nvram_write_chunk(
1075 __in efx_nic_t *enp,
1076 __in efx_nvram_type_t type,
1077 __in unsigned int offset,
1078 __in_bcount(size) caddr_t data,
1079 __in size_t size);
1080
1081 extern void
1082 efx_nvram_fini(
1083 __in efx_nic_t *enp);
1084
1085 #endif /* EFSYS_OPT_NVRAM */
1086
1087 #if EFSYS_OPT_BOOTCFG
1088
1089 extern int
1090 efx_bootcfg_read(
1091 __in efx_nic_t *enp,
1092 __out_bcount(size) caddr_t data,
1093 __in size_t size);
1094
1095 extern int
1096 efx_bootcfg_write(
1097 __in efx_nic_t *enp,
1098 __in_bcount(size) caddr_t data,
1099 __in size_t size);
1100
1101 #endif /* EFSYS_OPT_BOOTCFG */
1102
1103 #if EFSYS_OPT_WOL
1104
1105 typedef enum efx_wol_type_e {
1106 EFX_WOL_TYPE_INVALID,
1107 EFX_WOL_TYPE_MAGIC,
1108 EFX_WOL_TYPE_BITMAP,
1109 EFX_WOL_TYPE_LINK,
1110 EFX_WOL_NTYPES,
1111 } efx_wol_type_t;
1112
1113 typedef enum efx_lightsout_offload_type_e {
1114 EFX_LIGHTSOUT_OFFLOAD_TYPE_INVALID,
1115 EFX_LIGHTSOUT_OFFLOAD_TYPE_ARP,
1116 EFX_LIGHTSOUT_OFFLOAD_TYPE_NS,
1117 } efx_lightsout_offload_type_t;
1118
1119 #define EFX_WOL_BITMAP_MASK_SIZE (48)
1120 #define EFX_WOL_BITMAP_VALUE_SIZE (128)
1121
1122 typedef union efx_wol_param_u {
1123 struct {
1124 uint8_t mac_addr[6];
1125 } ewp_magic;
1126 struct {
1127 uint8_t mask[EFX_WOL_BITMAP_MASK_SIZE]; /* 1 bit per byte */
1128 uint8_t value[EFX_WOL_BITMAP_VALUE_SIZE]; /* value to match */
1129 uint8_t value_len;
1130 } ewp_bitmap;
1131 } efx_wol_param_t;
1132
1133 typedef union efx_lightsout_offload_param_u {
1134 struct {
1135 uint8_t mac_addr[6];
1136 uint32_t ip;
1137 } elop_arp;
1138 struct {
1139 uint8_t mac_addr[6];
1140 uint32_t solicited_node[4];
1141 uint32_t ip[4];
1142 } elop_ns;
1143 } efx_lightsout_offload_param_t;
1144
1145 extern __checkReturn int
1146 efx_wol_init(
1147 __in efx_nic_t *enp);
1148
1149 extern __checkReturn int
1150 efx_wol_filter_clear(
1151 __in efx_nic_t *enp);
1152
1153 extern __checkReturn int
1154 efx_wol_filter_add(
1155 __in efx_nic_t *enp,
1156 __in efx_wol_type_t type,
1157 __in efx_wol_param_t *paramp,
1158 __out uint32_t *filter_idp);
1159
1160 extern __checkReturn int
1161 efx_wol_filter_remove(
1162 __in efx_nic_t *enp,
1163 __in uint32_t filter_id);
1164
1165 extern __checkReturn int
1166 efx_lightsout_offload_add(
1167 __in efx_nic_t *enp,
1168 __in efx_lightsout_offload_type_t type,
1169 __in efx_lightsout_offload_param_t *paramp,
1170 __out uint32_t *filter_idp);
1171
1172 extern __checkReturn int
1173 efx_lightsout_offload_remove(
1174 __in efx_nic_t *enp,
1175 __in efx_lightsout_offload_type_t type,
1176 __in uint32_t filter_id);
1177
1178 extern void
1179 efx_wol_fini(
1180 __in efx_nic_t *enp);
1181
1182 #endif /* EFSYS_OPT_WOL */
1183
1184 #if EFSYS_OPT_DIAG
1185
1186 typedef enum efx_pattern_type_t {
1187 EFX_PATTERN_BYTE_INCREMENT = 0,
1188 EFX_PATTERN_ALL_THE_SAME,
1189 EFX_PATTERN_BIT_ALTERNATE,
1190 EFX_PATTERN_BYTE_ALTERNATE,
1191 EFX_PATTERN_BYTE_CHANGING,
1192 EFX_PATTERN_BIT_SWEEP,
1193 EFX_PATTERN_NTYPES
1194 } efx_pattern_type_t;
1195
1196 typedef void
1197 (*efx_sram_pattern_fn_t)(
1198 __in size_t row,
1199 __in boolean_t negate,
1200 __out efx_qword_t *eqp);
1201
1202 extern __checkReturn int
1203 efx_sram_test(
1204 __in efx_nic_t *enp,
1205 __in efx_pattern_type_t type);
1206
1207 #endif /* EFSYS_OPT_DIAG */
1208
1209 extern __checkReturn int
1210 efx_sram_buf_tbl_set(
1211 __in efx_nic_t *enp,
1212 __in uint32_t id,
1213 __in efsys_mem_t *esmp,
1214 __in size_t n);
1215
1216 extern void
1217 efx_sram_buf_tbl_clear(
1218 __in efx_nic_t *enp,
1219 __in uint32_t id,
1220 __in size_t n);
1221
1222 #define EFX_BUF_TBL_SIZE 0x20000
1223
1224 #define EFX_BUF_SIZE 4096
1225
1226 /* EV */
1227
1228 typedef struct efx_evq_s efx_evq_t;
1229
1230 #if EFSYS_OPT_QSTATS
1231
1232 /* START MKCONFIG GENERATED EfxHeaderEventQueueBlock d5614a5d669c8ca3 */
1233 typedef enum efx_ev_qstat_e {
1234 EV_ALL,
1235 EV_RX,
1236 EV_RX_OK,
1237 EV_RX_RECOVERY,
1238 EV_RX_FRM_TRUNC,
1239 EV_RX_TOBE_DISC,
1240 EV_RX_PAUSE_FRM_ERR,
1241 EV_RX_BUF_OWNER_ID_ERR,
1242 EV_RX_IPV4_HDR_CHKSUM_ERR,
1243 EV_RX_TCP_UDP_CHKSUM_ERR,
1244 EV_RX_ETH_CRC_ERR,
1245 EV_RX_IP_FRAG_ERR,
1246 EV_RX_MCAST_PKT,
1247 EV_RX_MCAST_HASH_MATCH,
1248 EV_RX_TCP_IPV4,
1249 EV_RX_TCP_IPV6,
1250 EV_RX_UDP_IPV4,
1251 EV_RX_UDP_IPV6,
1252 EV_RX_OTHER_IPV4,
1253 EV_RX_OTHER_IPV6,
1254 EV_RX_NON_IP,
1255 EV_RX_OVERRUN,
1256 EV_TX,
1257 EV_TX_WQ_FF_FULL,
1258 EV_TX_PKT_ERR,
1259 EV_TX_PKT_TOO_BIG,
1260 EV_TX_UNEXPECTED,
1261 EV_GLOBAL,
1262 EV_GLOBAL_PHY,
1263 EV_GLOBAL_MNT,
1264 EV_GLOBAL_RX_RECOVERY,
1265 EV_DRIVER,
1266 EV_DRIVER_SRM_UPD_DONE,
1267 EV_DRIVER_TX_DESCQ_FLS_DONE,
1268 EV_DRIVER_RX_DESCQ_FLS_DONE,
1269 EV_DRIVER_RX_DESCQ_FLS_FAILED,
1270 EV_DRIVER_RX_DSC_ERROR,
1271 EV_DRIVER_TX_DSC_ERROR,
1272 EV_DRV_GEN,
1273 EV_MCDI_RESPONSE,
1274 EV_NQSTATS
1275 } efx_ev_qstat_t;
1276
1277 /* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */
1278
1279 #endif /* EFSYS_OPT_QSTATS */
1280
1281 extern __checkReturn int
1282 efx_ev_init(
1283 __in efx_nic_t *enp);
1284
1285 extern void
1286 efx_ev_fini(
1287 __in efx_nic_t *enp);
1288
1289 #define EFX_MASK(_max, _min) (-((_max) << 1) ^ -(_min))
1290
1291 #define EFX_EVQ_MAXNEVS 32768
1292 #define EFX_EVQ_MINNEVS 512
1293
1294 #define EFX_EVQ_NEVS_MASK EFX_MASK(EFX_EVQ_MAXNEVS, EFX_EVQ_MINNEVS)
1295
1296 #define EFX_EVQ_SIZE(_nevs) ((_nevs) * sizeof (efx_qword_t))
1297 #define EFX_EVQ_NBUFS(_nevs) (EFX_EVQ_SIZE(_nevs) / EFX_BUF_SIZE)
1298
1299 extern __checkReturn int
1300 efx_ev_qcreate(
1301 __in efx_nic_t *enp,
1302 __in unsigned int index,
1303 __in efsys_mem_t *esmp,
1304 __in size_t n,
1305 __in uint32_t id,
1306 __deref_out efx_evq_t **eepp);
1307
1308 extern void
1309 efx_ev_qpost(
1310 __in efx_evq_t *eep,
1311 __in uint16_t data);
1312
1313 typedef __checkReturn boolean_t
1314 (*efx_initialized_ev_t)(
1315 __in_opt void *arg);
1316
1317 #define EFX_PKT_UNICAST 0x0004
1318 #define EFX_PKT_START 0x0008
1319
1320 #define EFX_PKT_VLAN_TAGGED 0x0010
1321 #define EFX_CKSUM_TCPUDP 0x0020
1322 #define EFX_CKSUM_IPV4 0x0040
1323 #define EFX_PKT_CONT 0x0080
1324
1325 #define EFX_CHECK_VLAN 0x0100
1326 #define EFX_PKT_TCP 0x0200
1327 #define EFX_PKT_UDP 0x0400
1328 #define EFX_PKT_IPV4 0x0800
1329
1330 #define EFX_PKT_IPV6 0x1000
1331 #define EFX_ADDR_MISMATCH 0x4000
1332 #define EFX_DISCARD 0x8000
1333
1334 #define EFX_EV_RX_NLABELS 32
1335 #define EFX_EV_TX_NLABELS 32
1336
1337 typedef __checkReturn boolean_t
1338 (*efx_rx_ev_t)(
1339 __in_opt void *arg,
1340 __in uint32_t label,
1341 __in uint32_t id,
1342 __in uint32_t size,
1343 __in uint16_t flags);
1344
1345 typedef __checkReturn boolean_t
1346 (*efx_tx_ev_t)(
1347 __in_opt void *arg,
1348 __in uint32_t label,
1349 __in uint32_t id);
1350
1351 #define EFX_EXCEPTION_RX_RECOVERY 0x00000001
1352 #define EFX_EXCEPTION_RX_DSC_ERROR 0x00000002
1353 #define EFX_EXCEPTION_TX_DSC_ERROR 0x00000003
1354 #define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004
1355 #define EFX_EXCEPTION_FWALERT_SRAM 0x00000005
1356 #define EFX_EXCEPTION_UNKNOWN_FWALERT 0x00000006
1357
1358 typedef __checkReturn boolean_t
1359 (*efx_exception_ev_t)(
1360 __in_opt void *arg,
1361 __in uint32_t label,
1362 __in uint32_t data);
1363
1364 typedef __checkReturn boolean_t
1365 (*efx_rxq_flush_done_ev_t)(
1366 __in_opt void *arg,
1367 __in uint32_t label);
1368
1369 typedef __checkReturn boolean_t
1370 (*efx_rxq_flush_failed_ev_t)(
1371 __in_opt void *arg,
1372 __in uint32_t label);
1373
1374 typedef __checkReturn boolean_t
1375 (*efx_txq_flush_done_ev_t)(
1376 __in_opt void *arg,
1377 __in uint32_t label);
1378
1379 typedef __checkReturn boolean_t
1380 (*efx_software_ev_t)(
1381 __in_opt void *arg,
1382 __in uint16_t magic);
1383
1384 typedef __checkReturn boolean_t
1385 (*efx_sram_ev_t)(
1386 __in_opt void *arg,
1387 __in uint32_t code);
1388
1389 #define EFX_SRAM_CLEAR 0
1390 #define EFX_SRAM_UPDATE 1
1391 #define EFX_SRAM_ILLEGAL_CLEAR 2
1392
1393 typedef __checkReturn boolean_t
1394 (*efx_wake_up_ev_t)(
1395 __in_opt void *arg,
1396 __in uint32_t label);
1397
1398 typedef __checkReturn boolean_t
1399 (*efx_timer_ev_t)(
1400 __in_opt void *arg,
1401 __in uint32_t label);
1402
1403 typedef __checkReturn boolean_t
1404 (*efx_link_change_ev_t)(
1405 __in_opt void *arg,
1406 __in efx_link_mode_t link_mode);
1407
1408 #if EFSYS_OPT_MON_STATS
1409
1410 typedef __checkReturn boolean_t
1411 (*efx_monitor_ev_t)(
1412 __in_opt void *arg,
1413 __in efx_mon_stat_t id,
1414 __in efx_mon_stat_value_t value);
1415
1416 #endif /* EFSYS_OPT_MON_STATS */
1417
1418 #if EFSYS_OPT_MAC_STATS
1419
1420 typedef __checkReturn boolean_t
1421 (*efx_mac_stats_ev_t)(
1422 __in_opt void *arg,
1423 __in uint32_t generation
1424 );
1425
1426 #endif /* EFSYS_OPT_MAC_STATS */
1427
1428 typedef struct efx_ev_callbacks_s {
1429 efx_initialized_ev_t eec_initialized;
1430 efx_rx_ev_t eec_rx;
1431 efx_tx_ev_t eec_tx;
1432 efx_exception_ev_t eec_exception;
1433 efx_rxq_flush_done_ev_t eec_rxq_flush_done;
1434 efx_rxq_flush_failed_ev_t eec_rxq_flush_failed;
1435 efx_txq_flush_done_ev_t eec_txq_flush_done;
1436 efx_software_ev_t eec_software;
1437 efx_sram_ev_t eec_sram;
1438 efx_wake_up_ev_t eec_wake_up;
1439 efx_timer_ev_t eec_timer;
1440 efx_link_change_ev_t eec_link_change;
1441 #if EFSYS_OPT_MON_STATS
1442 efx_monitor_ev_t eec_monitor;
1443 #endif /* EFSYS_OPT_MON_STATS */
1444 #if EFSYS_OPT_MAC_STATS
1445 efx_mac_stats_ev_t eec_mac_stats;
1446 #endif /* EFSYS_OPT_MON_STATS */
1447 } efx_ev_callbacks_t;
1448
1449 extern __checkReturn boolean_t
1450 efx_ev_qpending(
1451 __in efx_evq_t *eep,
1452 __in unsigned int count);
1453
1454 #if EFSYS_OPT_EV_PREFETCH
1455
1456 extern void
1457 efx_ev_qprefetch(
1458 __in efx_evq_t *eep,
1459 __in unsigned int count);
1460
1461 #endif /* EFSYS_OPT_EV_PREFETCH */
1462
1463 extern void
1464 efx_ev_qpoll(
1465 __in efx_evq_t *eep,
1466 __inout unsigned int *countp,
1467 __in const efx_ev_callbacks_t *eecp,
1468 __in_opt void *arg);
1469
1470 extern __checkReturn int
1471 efx_ev_qmoderate(
1472 __in efx_evq_t *eep,
1473 __in unsigned int us);
1474
1475 extern __checkReturn int
1476 efx_ev_qprime(
1477 __in efx_evq_t *eep,
1478 __in unsigned int count);
1479
1480 #if EFSYS_OPT_QSTATS
1481
1482 #if EFSYS_OPT_NAMES
1483
1484 extern const char __cs *
1485 efx_ev_qstat_name(
1486 __in efx_nic_t *enp,
1487 __in unsigned int id);
1488
1489 #endif /* EFSYS_OPT_NAMES */
1490
1491 extern void
1492 efx_ev_qstats_update(
1493 __in efx_evq_t *eep,
1494 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
1495
1496 #endif /* EFSYS_OPT_QSTATS */
1497
1498 extern void
1499 efx_ev_qdestroy(
1500 __in efx_evq_t *eep);
1501
1502 /* RX */
1503
1504 typedef struct efx_rxq_s efx_rxq_t;
1505
1506 extern __checkReturn int
1507 efx_rx_init(
1508 __in efx_nic_t *enp);
1509
1510 extern void
1511 efx_rx_fini(
1512 __in efx_nic_t *enp);
1513
1514 #if EFSYS_OPT_RX_HDR_SPLIT
1515 __checkReturn int
1516 efx_rx_hdr_split_enable(
1517 __in efx_nic_t *enp,
1518 __in unsigned int hdr_buf_size,
1519 __in unsigned int pld_buf_size);
1520
1521 #endif /* EFSYS_OPT_RX_HDR_SPLIT */
1522
1523 #if EFSYS_OPT_RX_SCATTER
1524 __checkReturn int
1525 efx_rx_scatter_enable(
1526 __in efx_nic_t *enp,
1527 __in unsigned int buf_size);
1528 #endif /* EFSYS_OPT_RX_SCATTER */
1529
1530 #if EFSYS_OPT_RX_SCALE
1531
1532 typedef enum efx_rx_hash_alg_e {
1533 EFX_RX_HASHALG_LFSR = 0,
1534 EFX_RX_HASHALG_TOEPLITZ
1535 } efx_rx_hash_alg_t;
1536
1537 typedef enum efx_rx_hash_type_e {
1538 EFX_RX_HASH_IPV4 = 0,
1539 EFX_RX_HASH_TCPIPV4,
1540 EFX_RX_HASH_IPV6,
1541 EFX_RX_HASH_TCPIPV6,
1542 } efx_rx_hash_type_t;
1543
1544 #define EFX_RSS_TBL_SIZE 128 /* Rows in RX indirection table */
1545 #define EFX_MAXRSS 64 /* RX indirection entry range */
1546 #define EFX_MAXRSS_LEGACY 16 /* See bug16611 and bug17213 */
1547
1548 extern __checkReturn int
1549 efx_rx_scale_mode_set(
1550 __in efx_nic_t *enp,
1551 __in efx_rx_hash_alg_t alg,
1552 __in efx_rx_hash_type_t type,
1553 __in boolean_t insert);
1554
1555 extern __checkReturn int
1556 efx_rx_scale_tbl_set(
1557 __in efx_nic_t *enp,
1558 __in_ecount(n) unsigned int *table,
1559 __in size_t n);
1560
1561 extern __checkReturn int
1562 efx_rx_scale_toeplitz_ipv4_key_set(
1563 __in efx_nic_t *enp,
1564 __in_ecount(n) uint8_t *key,
1565 __in size_t n);
1566
1567 extern __checkReturn int
1568 efx_rx_scale_toeplitz_ipv6_key_set(
1569 __in efx_nic_t *enp,
1570 __in_ecount(n) uint8_t *key,
1571 __in size_t n);
1572
1573 /*
1574 * The prefix is a byte array of one of the forms:
1575 *
1576 * 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1577 * XX.XX.XX.XX.XX.XX.XX.XX.XX.XX.XX.XX.TT.TT.TT.TT
1578 * XX.XX.XX.XX.XX.XX.XX.XX.XX.XX.XX.XX.XX.XX.LL.LL
1579 *
1580 * where:
1581 *
1582 * TT.TT.TT.TT is a 32-bit Toeplitz hash
1583 * LL.LL is a 16-bit LFSR hash
1584 *
1585 * Hash values are in network (big-endian) byte order.
1586 */
1587
1588 #define EFX_RX_PREFIX_SIZE 16
1589
1590 #define EFX_RX_HASH_VALUE(_func, _buffer) \
1591 (((_func) == EFX_RX_HASHALG_LFSR) ? \
1592 ((uint16_t)(((_buffer)[14] << 8) | (_buffer)[15])) : \
1593 ((uint32_t)(((_buffer)[12] << 24) | \
1594 ((_buffer)[13] << 16) | \
1595 ((_buffer)[14] << 8) | \
1596 (_buffer)[15])))
1597
1598 #define EFX_RX_HASH_SIZE(_func) \
1599 (((_func) == EFX_RX_HASHALG_LFSR) ? \
1600 sizeof (uint16_t) : \
1601 sizeof (uint32_t))
1602
1603 #endif /* EFSYS_OPT_RX_SCALE */
1604
1605 #define EFX_RXQ_MAXNDESCS 4096
1606 #define EFX_RXQ_MINNDESCS 512
1607
1608 #define EFX_RXQ_NDESCS_MASK EFX_MASK(EFX_RXQ_MAXNDESCS, EFX_RXQ_MINNDESCS)
1609
1610 #define EFX_RXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
1611 #define EFX_RXQ_NBUFS(_ndescs) (EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
1612 #define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16)
1613 #define EFX_RXQ_DC_NDESCS(_dcsize) (8 << _dcsize)
1614
1615 typedef enum efx_rxq_type_e {
1616 EFX_RXQ_TYPE_DEFAULT,
1617 EFX_RXQ_TYPE_SPLIT_HEADER,
1618 EFX_RXQ_TYPE_SPLIT_PAYLOAD,
1619 EFX_RXQ_TYPE_SCATTER,
1620 EFX_RXQ_NTYPES
1621 } efx_rxq_type_t;
1622
1623 extern __checkReturn int
1624 efx_rx_qcreate(
1625 __in efx_nic_t *enp,
1626 __in unsigned int index,
1627 __in unsigned int label,
1628 __in efx_rxq_type_t type,
1629 __in efsys_mem_t *esmp,
1630 __in size_t n,
1631 __in uint32_t id,
1632 __in efx_evq_t *eep,
1633 __deref_out efx_rxq_t **erpp);
1634
1635 typedef struct efx_buffer_s {
1636 efsys_dma_addr_t eb_addr;
1637 size_t eb_size;
1638 boolean_t eb_eop;
1639 } efx_buffer_t;
1640
1641 extern void
1642 efx_rx_qpost(
1643 __in efx_rxq_t *erp,
1644 __in_ecount(n) efsys_dma_addr_t *addrp,
1645 __in size_t size,
1646 __in unsigned int n,
1647 __in unsigned int completed,
1648 __in unsigned int added);
1649
1650 extern void
1651 efx_rx_qpush(
1652 __in efx_rxq_t *erp,
1653 __in unsigned int added);
1654
1655 extern void
1656 efx_rx_qflush(
1657 __in efx_rxq_t *erp);
1658
1659 extern void
1660 efx_rx_qenable(
1661 __in efx_rxq_t *erp);
1662
1663 extern void
1664 efx_rx_qdestroy(
1665 __in efx_rxq_t *erp);
1666
1667 /* TX */
1668
1669 typedef struct efx_txq_s efx_txq_t;
1670
1671 #if EFSYS_OPT_QSTATS
1672
1673 /* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 536c5fa5014944bf */
1674 typedef enum efx_tx_qstat_e {
1675 TX_POST,
1676 TX_UNALIGNED_SPLIT,
1677 TX_NQSTATS
1678 } efx_tx_qstat_t;
1679
1680 /* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */
1681
1682 #endif /* EFSYS_OPT_QSTATS */
1683
1684 extern __checkReturn int
1685 efx_tx_init(
1686 __in efx_nic_t *enp);
1687
1688 extern void
1689 efx_tx_fini(
1690 __in efx_nic_t *enp);
1691
1692 #define EFX_TXQ_MAXNDESCS 4096
1693 #define EFX_TXQ_MINNDESCS 512
1694
1695 #define EFX_TXQ_NDESCS_MASK EFX_MASK(EFX_TXQ_MAXNDESCS, EFX_TXQ_MINNDESCS)
1696
1697 #define EFX_TXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
1698 #define EFX_TXQ_NBUFS(_ndescs) (EFX_TXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
1699 #define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16)
1700 #define EFX_TXQ_DC_NDESCS(_dcsize) (8 << _dcsize)
1701
1702 extern __checkReturn int
1703 efx_tx_qcreate(
1704 __in efx_nic_t *enp,
1705 __in unsigned int index,
1706 __in unsigned int label,
1707 __in efsys_mem_t *esmp,
1708 __in size_t n,
1709 __in uint32_t id,
1710 __in uint16_t flags,
1711 __in efx_evq_t *eep,
1712 __deref_out efx_txq_t **etpp);
1713
1714 extern __checkReturn int
1715 efx_tx_qpost(
1716 __in efx_txq_t *etp,
1717 __in_ecount(n) efx_buffer_t *eb,
1718 __in unsigned int n,
1719 __in unsigned int completed,
1720 __inout unsigned int *addedp);
1721
1722 extern __checkReturn int
1723 efx_tx_qpace(
1724 __in efx_txq_t *etp,
1725 __in unsigned int ns);
1726
1727 extern void
1728 efx_tx_qpush(
1729 __in efx_txq_t *etp,
1730 __in unsigned int added);
1731
1732 extern void
1733 efx_tx_qflush(
1734 __in efx_txq_t *etp);
1735
1736 extern void
1737 efx_tx_qenable(
1738 __in efx_txq_t *etp);
1739
1740 #if EFSYS_OPT_QSTATS
1741
1742 #if EFSYS_OPT_NAMES
1743
1744 extern const char __cs *
1745 efx_tx_qstat_name(
1746 __in efx_nic_t *etp,
1747 __in unsigned int id);
1748
1749 #endif /* EFSYS_OPT_NAMES */
1750
1751 extern void
1752 efx_tx_qstats_update(
1753 __in efx_txq_t *etp,
1754 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
1755
1756 #endif /* EFSYS_OPT_QSTATS */
1757
1758 extern void
1759 efx_tx_qdestroy(
1760 __in efx_txq_t *etp);
1761
1762
1763 /* FILTER */
1764
1765 #if EFSYS_OPT_FILTER
1766
1767 typedef enum efx_filter_flag_e {
1768 EFX_FILTER_FLAG_RX_RSS = 0x01, /* use RSS to spread across
1769 * multiple queues */
1770 EFX_FILTER_FLAG_RX_SCATTER = 0x02, /* enable RX scatter */
1771 EFX_FILTER_FLAG_RX_OVERRIDE_IP = 0x04, /* MAC filter overrides
1772 * any matching IP filter */
1773 } efx_filter_flag_t;
1774
1775 typedef struct efx_filter_spec_s {
1776 uint8_t efs_type;
1777 uint8_t efs_flags;
1778 uint16_t efs_dmaq_id;
1779 uint32_t efs_dword[3];
1780 } efx_filter_spec_t;
1781
1782 extern __checkReturn int
1783 efx_filter_init(
1784 __in efx_nic_t *enp);
1785
1786 extern void
1787 efx_filter_fini(
1788 __in efx_nic_t *enp);
1789
1790 extern __checkReturn int
1791 efx_rx_filter_insert(
1792 __in efx_rxq_t *erp,
1793 __inout efx_filter_spec_t *spec);
1794
1795 extern __checkReturn int
1796 efx_rx_filter_remove(
1797 __in efx_rxq_t *erp,
1798 __inout efx_filter_spec_t *spec);
1799
1800 void
1801 efx_filter_restore(
1802 __in efx_nic_t *enp);
1803
1804 extern void
1805 efx_filter_spec_rx_ipv4_tcp_full(
1806 __inout efx_filter_spec_t *spec,
1807 __in unsigned int flags,
1808 __in uint32_t src_ip,
1809 __in uint16_t src_tcp,
1810 __in uint32_t dest_ip,
1811 __in uint16_t dest_tcp);
1812
1813 extern void
1814 efx_filter_spec_rx_ipv4_tcp_wild(
1815 __inout efx_filter_spec_t *spec,
1816 __in unsigned int flags,
1817 __in uint32_t dest_ip,
1818 __in uint16_t dest_tcp);
1819
1820 extern void
1821 efx_filter_spec_rx_ipv4_udp_full(
1822 __inout efx_filter_spec_t *spec,
1823 __in unsigned int flags,
1824 __in uint32_t src_ip,
1825 __in uint16_t src_udp,
1826 __in uint32_t dest_ip,
1827 __in uint16_t dest_udp);
1828
1829 extern void
1830 efx_filter_spec_rx_ipv4_udp_wild(
1831 __inout efx_filter_spec_t *spec,
1832 __in unsigned int flags,
1833 __in uint32_t dest_ip,
1834 __in uint16_t dest_udp);
1835
1836 extern void
1837 efx_filter_spec_rx_mac_full(
1838 __inout efx_filter_spec_t *spec,
1839 __in unsigned int flags,
1840 __in uint16_t vlan_id,
1841 __in uint8_t *dest_mac);
1842
1843 extern void
1844 efx_filter_spec_rx_mac_wild(
1845 __inout efx_filter_spec_t *spec,
1846 __in unsigned int flags,
1847 __in uint8_t *dest_mac);
1848
1849
1850 extern __checkReturn int
1851 efx_tx_filter_insert(
1852 __in efx_txq_t *etp,
1853 __inout efx_filter_spec_t *spec);
1854
1855 extern __checkReturn int
1856 efx_tx_filter_remove(
1857 __in efx_txq_t *etp,
1858 __inout efx_filter_spec_t *spec);
1859
1860 extern void
1861 efx_filter_spec_tx_ipv4_tcp_full(
1862 __inout efx_filter_spec_t *spec,
1863 __in uint32_t src_ip,
1864 __in uint16_t src_tcp,
1865 __in uint32_t dest_ip,
1866 __in uint16_t dest_tcp);
1867
1868 extern void
1869 efx_filter_spec_tx_ipv4_tcp_wild(
1870 __inout efx_filter_spec_t *spec,
1871 __in uint32_t src_ip,
1872 __in uint16_t src_tcp);
1873
1874 extern void
1875 efx_filter_spec_tx_ipv4_udp_full(
1876 __inout efx_filter_spec_t *spec,
1877 __in uint32_t src_ip,
1878 __in uint16_t src_udp,
1879 __in uint32_t dest_ip,
1880 __in uint16_t dest_udp);
1881
1882 extern void
1883 efx_filter_spec_tx_ipv4_udp_wild(
1884 __inout efx_filter_spec_t *spec,
1885 __in uint32_t src_ip,
1886 __in uint16_t src_udp);
1887
1888 extern void
1889 efx_filter_spec_tx_mac_full(
1890 __inout efx_filter_spec_t *spec,
1891 __in uint16_t vlan_id,
1892 __in uint8_t *src_mac);
1893
1894 extern void
1895 efx_filter_spec_tx_mac_wild(
1896 __inout efx_filter_spec_t *spec,
1897 __in uint8_t *src_mac);
1898
1899 #endif /* EFSYS_OPT_FILTER */
1900
1901
1902 #ifdef __cplusplus
1903 }
1904 #endif
1905
1906 #endif /* _SYS_EFX_H */