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--- old/usr/src/uts/common/sys/scsi/adapters/mpt_sas/mptsas_var.h
+++ new/usr/src/uts/common/sys/scsi/adapters/mpt_sas/mptsas_var.h
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21
22 22 /*
23 23 * Copyright (c) 2009, 2010, Oracle and/or its affiliates. All rights reserved.
24 24 * Copyright 2014 Nexenta Systems, Inc. All rights reserved.
25 25 * Copyright (c) 2013, Joyent, Inc. All rights reserved.
26 26 * Copyright (c) 2014, Tegile Systems Inc. All rights reserved.
27 27 */
28 28
29 29 /*
30 30 * Copyright (c) 2000 to 2010, LSI Corporation.
31 31 * All rights reserved.
32 32 *
33 33 * Redistribution and use in source and binary forms of all code within
34 34 * this file that is exclusively owned by LSI, with or without
35 35 * modification, is permitted provided that, in addition to the CDDL 1.0
36 36 * License requirements, the following conditions are met:
37 37 *
38 38 * Neither the name of the author nor the names of its contributors may be
39 39 * used to endorse or promote products derived from this software without
40 40 * specific prior written permission.
41 41 *
42 42 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
43 43 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
44 44 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
45 45 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
46 46 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
47 47 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
48 48 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
49 49 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
50 50 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
51 51 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
52 52 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
53 53 * DAMAGE.
54 54 */
55 55
56 56 #ifndef _SYS_SCSI_ADAPTERS_MPTVAR_H
57 57 #define _SYS_SCSI_ADAPTERS_MPTVAR_H
58 58
59 59 #include <sys/byteorder.h>
60 60 #include <sys/queue.h>
61 61 #include <sys/isa_defs.h>
62 62 #include <sys/sunmdi.h>
63 63 #include <sys/mdi_impldefs.h>
64 64 #include <sys/scsi/adapters/mpt_sas/mptsas_hash.h>
65 65 #include <sys/scsi/adapters/mpt_sas/mptsas_ioctl.h>
66 66 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_tool.h>
67 67 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_cnfg.h>
68 68
69 69 #ifdef __cplusplus
70 70 extern "C" {
71 71 #endif
72 72
73 73 /*
74 74 * Compile options
75 75 */
76 76 #ifdef DEBUG
77 77 #define MPTSAS_DEBUG /* turn on debugging code */
78 78 #endif /* DEBUG */
79 79
80 80 #define MPTSAS_INITIAL_SOFT_SPACE 4
81 81
82 82 #define MAX_MPI_PORTS 16
83 83
84 84 /*
85 85 * Note below macro definition and data type definition
86 86 * are used for phy mask handling, it should be changed
87 87 * simultaneously.
88 88 */
89 89 #define MPTSAS_MAX_PHYS 16
90 90 typedef uint16_t mptsas_phymask_t;
91 91
92 92 #define MPTSAS_INVALID_DEVHDL 0xffff
93 93 #define MPTSAS_SATA_GUID "sata-guid"
94 94
95 95 /*
96 96 * Hash table sizes for SMP targets (i.e., expanders) and ordinary SSP/STP
97 97 * targets. There's no need to go overboard here, as the ordinary paths for
98 98 * I/O do not normally require hashed target lookups. These should be good
99 99 * enough and then some for any fabric within the hardware's capabilities.
100 100 */
101 101 #define MPTSAS_SMP_BUCKET_COUNT 23
102 102 #define MPTSAS_TARGET_BUCKET_COUNT 97
103 103
104 104 /*
105 105 * MPT HW defines
106 106 */
107 107 #define MPTSAS_MAX_DISKS_IN_CONFIG 14
108 108 #define MPTSAS_MAX_DISKS_IN_VOL 10
109 109 #define MPTSAS_MAX_HOTSPARES 2
110 110 #define MPTSAS_MAX_RAIDVOLS 2
111 111 #define MPTSAS_MAX_RAIDCONFIGS 5
112 112
113 113 /*
114 114 * 64-bit SAS WWN is displayed as 16 characters as HEX characters,
115 115 * plus two means the prefix 'w' and end of the string '\0'.
116 116 */
117 117 #define MPTSAS_WWN_STRLEN (16 + 2)
118 118 #define MPTSAS_MAX_GUID_LEN 64
119 119
120 120 /*
121 121 * DMA routine flags
122 122 */
123 123 #define MPTSAS_DMA_HANDLE_ALLOCD 0x2
124 124 #define MPTSAS_DMA_MEMORY_ALLOCD 0x4
125 125 #define MPTSAS_DMA_HANDLE_BOUND 0x8
126 126
127 127 /*
128 128 * If the HBA supports DMA or bus-mastering, you may have your own
129 129 * scatter-gather list for physically non-contiguous memory in one
130 130 * I/O operation; if so, there's probably a size for that list.
131 131 * It must be placed in the ddi_dma_lim_t structure, so that the system
132 132 * DMA-support routines can use it to break up the I/O request, so we
133 133 * define it here.
134 134 */
135 135 #if defined(__sparc)
136 136 #define MPTSAS_MAX_DMA_SEGS 1
137 137 #define MPTSAS_MAX_CMD_SEGS 1
138 138 #else
139 139 #define MPTSAS_MAX_DMA_SEGS 256
140 140 #define MPTSAS_MAX_CMD_SEGS 257
141 141 #endif
142 142 #define MPTSAS_MAX_FRAME_SGES(mpt) \
143 143 (((mpt->m_req_frame_size - (sizeof (MPI2_SCSI_IO_REQUEST))) / 8) + 1)
144 144
145 145 #define MPTSAS_SGE_SIZE(mpt) \
146 146 ((mpt)->m_MPI25 ? sizeof (MPI2_IEEE_SGE_SIMPLE64) : \
147 147 sizeof (MPI2_SGE_SIMPLE64))
148 148
149 149 /*
150 150 * Calculating how many 64-bit DMA simple elements can be stored in the first
151 151 * frame. Note that msg_scsi_io_request contains 2 double-words (8 bytes) for
152 152 * element storage. And 64-bit dma element is 3 double-words (12 bytes) in
153 153 * size. IEEE 64-bit dma element used for SAS3 controllers is 4 double-words
154 154 * (16 bytes).
155 155 */
156 156 #define MPTSAS_MAX_FRAME_SGES64(mpt) \
157 157 ((mpt->m_req_frame_size - \
158 158 sizeof (MPI2_SCSI_IO_REQUEST) + sizeof (MPI2_SGE_IO_UNION)) / \
159 159 MPTSAS_SGE_SIZE(mpt))
160 160
161 161 /*
162 162 * Scatter-gather list structure defined by HBA hardware
163 163 */
164 164 typedef struct NcrTableIndirect { /* Table Indirect entries */
165 165 uint32_t count; /* 24 bit count */
166 166 union {
167 167 uint32_t address32; /* 32 bit address */
168 168 struct {
169 169 uint32_t Low;
170 170 uint32_t High;
171 171 } address64; /* 64 bit address */
172 172 } addr;
173 173 } mptti_t;
174 174
175 175 /*
176 176 * preferred pkt_private length in 64-bit quantities
177 177 */
178 178 #ifdef _LP64
179 179 #define PKT_PRIV_SIZE 2
180 180 #define PKT_PRIV_LEN 16 /* in bytes */
181 181 #else /* _ILP32 */
182 182 #define PKT_PRIV_SIZE 1
183 183 #define PKT_PRIV_LEN 8 /* in bytes */
184 184 #endif
185 185
186 186 #define PKT2CMD(pkt) ((struct mptsas_cmd *)((pkt)->pkt_ha_private))
187 187 #define CMD2PKT(cmdp) ((struct scsi_pkt *)((cmdp)->cmd_pkt))
188 188 #define EXTCMDS_STATUS_SIZE (sizeof (struct scsi_arq_status))
189 189
190 190 /*
191 191 * get offset of item in structure
192 192 */
193 193 #define MPTSAS_GET_ITEM_OFF(type, member) ((size_t)(&((type *)0)->member))
194 194
195 195 /*
196 196 * WWID provided by LSI firmware is generated by firmware but the WWID is not
197 197 * IEEE NAA standard format, OBP has no chance to distinguish format of unit
198 198 * address. According LSI's confirmation, the top nibble of RAID WWID is
199 199 * meanless, so the consensus between Solaris and OBP is to replace top nibble
200 200 * of WWID provided by LSI to "3" always to hint OBP that this is a RAID WWID
201 201 * format unit address.
202 202 */
203 203 #define MPTSAS_RAID_WWID(wwid) \
204 204 ((wwid & 0x0FFFFFFFFFFFFFFF) | 0x3000000000000000)
205 205
206 206 typedef struct mptsas_target_addr {
207 207 uint64_t mta_wwn;
208 208 mptsas_phymask_t mta_phymask;
209 209 } mptsas_target_addr_t;
210 210
211 211 TAILQ_HEAD(mptsas_active_cmdq, mptsas_cmd);
212 212 typedef struct mptsas_active_cmdq mptsas_active_cmdq_t;
213 213
214 214 typedef struct mptsas_target {
215 215 mptsas_target_addr_t m_addr;
216 216 refhash_link_t m_link;
217 217 uint8_t m_dr_flag;
218 218 uint16_t m_devhdl;
219 219 uint32_t m_deviceinfo;
220 220 uint8_t m_phynum;
221 221 uint32_t m_dups;
222 222 mptsas_active_cmdq_t m_active_cmdq;
223 223 int32_t m_t_throttle;
224 224 int32_t m_t_ncmds;
225 225 int32_t m_reset_delay;
226 226 int32_t m_t_nwait;
227 227
228 228 uint16_t m_qfull_retry_interval;
229 229 uint8_t m_qfull_retries;
230 230 uint16_t m_io_flags;
231 231 uint16_t m_enclosure;
232 232 uint16_t m_slot_num;
233 233 uint32_t m_tgt_unconfigured;
234 234 uint8_t m_led_status;
235 235 uint8_t m_scsi_req_desc_type;
236 236
237 237 } mptsas_target_t;
238 238
239 239 /*
240 240 * If you change this structure, be sure that mptsas_smp_target_copy()
241 241 * does the right thing.
242 242 */
243 243 typedef struct mptsas_smp {
244 244 mptsas_target_addr_t m_addr;
245 245 refhash_link_t m_link;
246 246 uint16_t m_devhdl;
247 247 uint32_t m_deviceinfo;
248 248 uint16_t m_pdevhdl;
249 249 uint32_t m_pdevinfo;
250 250 } mptsas_smp_t;
251 251
252 252 typedef struct mptsas_cache_frames {
253 253 ddi_dma_handle_t m_dma_hdl;
254 254 ddi_acc_handle_t m_acc_hdl;
255 255 caddr_t m_frames_addr;
256 256 uint64_t m_phys_addr;
257 257 } mptsas_cache_frames_t;
258 258
259 259 typedef struct mptsas_cmd {
260 260 uint_t cmd_flags; /* flags from scsi_init_pkt */
261 261 ddi_dma_handle_t cmd_dmahandle; /* dma handle */
262 262 ddi_dma_cookie_t cmd_cookie;
263 263 uint_t cmd_cookiec;
264 264 uint_t cmd_winindex;
265 265 uint_t cmd_nwin;
266 266 uint_t cmd_cur_cookie;
267 267 off_t cmd_dma_offset;
268 268 size_t cmd_dma_len;
269 269 uint32_t cmd_totaldmacount;
270 270 caddr_t cmd_arq_buf;
271 271
272 272 int cmd_pkt_flags;
273 273
274 274 /* pending expiration time for command in active slot */
275 275 hrtime_t cmd_active_expiration;
276 276 TAILQ_ENTRY(mptsas_cmd) cmd_active_link;
277 277
278 278 struct scsi_pkt *cmd_pkt;
279 279 struct scsi_arq_status cmd_scb;
280 280 uchar_t cmd_cdblen; /* length of cdb */
281 281 uchar_t cmd_rqslen; /* len of requested rqsense */
282 282 uchar_t cmd_privlen;
283 283 uint16_t cmd_extrqslen; /* len of extended rqsense */
284 284 uint16_t cmd_extrqschunks; /* len in map chunks */
285 285 uint16_t cmd_extrqsidx; /* Index into map */
286 286 uint_t cmd_scblen;
287 287 uint32_t cmd_dmacount;
288 288 uint64_t cmd_dma_addr;
289 289 uchar_t cmd_age;
290 290 ushort_t cmd_qfull_retries;
291 291 uchar_t cmd_queued; /* true if queued */
292 292 struct mptsas_cmd *cmd_linkp;
293 293 mptti_t *cmd_sg; /* Scatter/Gather structure */
294 294 uchar_t cmd_cdb[SCSI_CDB_SIZE];
295 295 uint64_t cmd_pkt_private[PKT_PRIV_LEN];
296 296 uint32_t cmd_slot;
297 297 uint32_t ioc_cmd_slot;
298 298
299 299 mptsas_cache_frames_t *cmd_extra_frames;
300 300
301 301 uint32_t cmd_rfm;
302 302 mptsas_target_t *cmd_tgt_addr;
303 303 } mptsas_cmd_t;
304 304
305 305 /*
306 306 * These are the defined cmd_flags for this structure.
307 307 */
308 308 #define CFLAG_CMDDISC 0x000001 /* cmd currently disconnected */
309 309 #define CFLAG_WATCH 0x000002 /* watchdog time for this command */
310 310 #define CFLAG_FINISHED 0x000004 /* command completed */
311 311 #define CFLAG_CHKSEG 0x000008 /* check cmd_data within seg */
312 312 #define CFLAG_COMPLETED 0x000010 /* completion routine called */
313 313 #define CFLAG_PREPARED 0x000020 /* pkt has been init'ed */
314 314 #define CFLAG_IN_TRANSPORT 0x000040 /* in use by host adapter driver */
315 315 #define CFLAG_RESTORE_PTRS 0x000080 /* implicit restore ptr on reconnect */
316 316 #define CFLAG_ARQ_IN_PROGRESS 0x000100 /* auto request sense in progress */
317 317 #define CFLAG_TRANFLAG 0x0001ff /* covers transport part of flags */
318 318 #define CFLAG_TM_CMD 0x000200 /* cmd is a task management command */
319 319 #define CFLAG_CMDARQ 0x000400 /* cmd is a 'rqsense' command */
320 320 #define CFLAG_DMAVALID 0x000800 /* dma mapping valid */
321 321 #define CFLAG_DMASEND 0x001000 /* data is going 'out' */
322 322 #define CFLAG_CMDIOPB 0x002000 /* this is an 'iopb' packet */
323 323 #define CFLAG_CDBEXTERN 0x004000 /* cdb kmem_alloc'd */
324 324 #define CFLAG_SCBEXTERN 0x008000 /* scb kmem_alloc'd */
325 325 #define CFLAG_FREE 0x010000 /* packet is on free list */
326 326 #define CFLAG_PRIVEXTERN 0x020000 /* target private kmem_alloc'd */
327 327 #define CFLAG_DMA_PARTIAL 0x040000 /* partial xfer OK */
328 328 #define CFLAG_QFULL_STATUS 0x080000 /* pkt got qfull status */
329 329 #define CFLAG_TIMEOUT 0x100000 /* passthru/config command timeout */
330 330 #define CFLAG_PMM_RECEIVED 0x200000 /* use cmd_pmm* for saving pointers */
331 331 #define CFLAG_RETRY 0x400000 /* cmd has been retried */
332 332 #define CFLAG_CMDIOC 0x800000 /* cmd is just for for ioc, no io */
333 333 #define CFLAG_PASSTHRU 0x2000000 /* cmd is a passthrough command */
334 334 #define CFLAG_XARQ 0x4000000 /* cmd requests for extra sense */
335 335 #define CFLAG_CMDACK 0x8000000 /* cmd for event ack */
336 336 #define CFLAG_TXQ 0x10000000 /* cmd queued in the tx_waitq */
337 337 #define CFLAG_FW_CMD 0x20000000 /* cmd is a fw up/down command */
338 338 #define CFLAG_CONFIG 0x40000000 /* cmd is for config header/page */
339 339 #define CFLAG_FW_DIAG 0x80000000 /* cmd is for FW diag buffers */
340 340
341 341 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_SIZE 8
342 342 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_MASK 0xC0
343 343 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_PERIPHERAL 0x00
344 344 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_FLAT_SPACE 0x40
345 345 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT 0x80
346 346 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_EXTENDED_UNIT 0xC0
347 347 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_2B 0x00
348 348 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_4B 0x01
349 349 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_6B 0x10
350 350 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_8B 0x20
351 351 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_SIZE 0x30
352 352
353 353 #define MPTSAS_HASH_ARRAY_SIZE 16
354 354 /*
355 355 * hash table definition
356 356 */
357 357
358 358 #define MPTSAS_HASH_FIRST 0xffff
359 359 #define MPTSAS_HASH_NEXT 0x0000
360 360
361 361 typedef struct mptsas_dma_alloc_state
362 362 {
363 363 ddi_dma_handle_t handle;
364 364 caddr_t memp;
365 365 size_t size;
366 366 ddi_acc_handle_t accessp;
367 367 ddi_dma_cookie_t cookie;
368 368 } mptsas_dma_alloc_state_t;
369 369
370 370 /*
371 371 * passthrough request structure
372 372 */
373 373 typedef struct mptsas_pt_request {
374 374 uint8_t *request;
375 375 uint32_t request_size;
376 376 uint32_t data_size;
377 377 uint32_t dataout_size;
378 378 uint32_t direction;
379 379 uint8_t simple;
380 380 uint16_t sgl_offset;
381 381 ddi_dma_cookie_t data_cookie;
382 382 ddi_dma_cookie_t dataout_cookie;
383 383 } mptsas_pt_request_t;
384 384
385 385 /*
386 386 * config page request structure
387 387 */
388 388 typedef struct mptsas_config_request {
389 389 uint32_t page_address;
390 390 uint8_t action;
391 391 uint8_t page_type;
392 392 uint8_t page_number;
393 393 uint8_t page_length;
394 394 uint8_t page_version;
395 395 uint8_t ext_page_type;
396 396 uint16_t ext_page_length;
397 397 } mptsas_config_request_t;
398 398
399 399 typedef struct mptsas_fw_diagnostic_buffer {
400 400 mptsas_dma_alloc_state_t buffer_data;
401 401 uint8_t extended_type;
402 402 uint8_t buffer_type;
403 403 uint8_t force_release;
404 404 uint32_t product_specific[23];
405 405 uint8_t immediate;
406 406 uint8_t enabled;
407 407 uint8_t valid_data;
408 408 uint8_t owned_by_firmware;
409 409 uint32_t unique_id;
410 410 } mptsas_fw_diagnostic_buffer_t;
411 411
412 412 /*
413 413 * FW diag request structure
414 414 */
415 415 typedef struct mptsas_diag_request {
416 416 mptsas_fw_diagnostic_buffer_t *pBuffer;
417 417 uint8_t function;
418 418 } mptsas_diag_request_t;
419 419
420 420 typedef struct mptsas_hash_node {
421 421 void *data;
422 422 struct mptsas_hash_node *next;
423 423 } mptsas_hash_node_t;
424 424
425 425 typedef struct mptsas_hash_table {
426 426 struct mptsas_hash_node *head[MPTSAS_HASH_ARRAY_SIZE];
427 427 /*
428 428 * last position in traverse
429 429 */
430 430 struct mptsas_hash_node *cur;
431 431 uint16_t line;
432 432
433 433 } mptsas_hash_table_t;
434 434
435 435 /*
436 436 * RAID volume information
437 437 */
438 438 typedef struct mptsas_raidvol {
439 439 ushort_t m_israid;
440 440 uint16_t m_raidhandle;
441 441 uint64_t m_raidwwid;
442 442 uint8_t m_state;
443 443 uint32_t m_statusflags;
444 444 uint32_t m_settings;
445 445 uint16_t m_devhdl[MPTSAS_MAX_DISKS_IN_VOL];
446 446 uint8_t m_disknum[MPTSAS_MAX_DISKS_IN_VOL];
447 447 ushort_t m_diskstatus[MPTSAS_MAX_DISKS_IN_VOL];
448 448 uint64_t m_raidsize;
449 449 int m_raidlevel;
450 450 int m_ndisks;
451 451 mptsas_target_t *m_raidtgt;
452 452 } mptsas_raidvol_t;
453 453
454 454 /*
455 455 * RAID configurations
456 456 */
457 457 typedef struct mptsas_raidconfig {
458 458 mptsas_raidvol_t m_raidvol[MPTSAS_MAX_RAIDVOLS];
459 459 uint16_t m_physdisk_devhdl[
460 460 MPTSAS_MAX_DISKS_IN_CONFIG];
461 461 uint8_t m_native;
462 462 } m_raidconfig_t;
463 463
464 464 /*
465 465 * Track outstanding commands. The index into the m_slot array is the SMID
466 466 * (system message ID) of the outstanding command. SMID 0 is reserved by the
467 467 * software/firmware protocol and is never used for any command we generate;
468 468 * as such, the assertion m_slot[0] == NULL is universally true. The last
469 469 * entry in the array is slot number MPTSAS_TM_SLOT(mpt) and is used ONLY for
470 470 * task management commands. No normal SCSI or ATA command will ever occupy
471 471 * that slot. Finally, the relationship m_slot[X]->cmd_slot == X holds at any
472 472 * time that a consistent view of the target array is obtainable.
473 473 *
474 474 * As such, m_n_normal is the maximum number of slots available to ordinary
475 475 * commands, and the relationship:
476 476 * mpt->m_active->m_n_normal == mpt->m_max_requests - 2
477 477 * always holds after initialisation.
478 478 */
479 479 typedef struct mptsas_slots {
480 480 size_t m_size; /* size of struct, bytes */
481 481 uint_t m_n_normal; /* see above */
482 482 uint_t m_rotor; /* next slot idx to consider */
483 483 mptsas_cmd_t *m_slot[1];
484 484 } mptsas_slots_t;
485 485
486 486 /*
487 487 * Structure to hold command and packets for event ack
488 488 * and task management commands.
489 489 */
490 490 typedef struct m_event_struct {
491 491 struct mptsas_cmd m_event_cmd;
492 492 struct m_event_struct *m_event_linkp;
493 493 /*
494 494 * event member record the failure event and eventcntx
495 495 * event member would be used in send ack pending process
496 496 */
497 497 uint32_t m_event;
498 498 uint32_t m_eventcntx;
499 499 uint_t in_use;
500 500 struct scsi_pkt m_event_pkt; /* must be last */
501 501 /* ... scsi_pkt_size() */
502 502 } m_event_struct_t;
503 503 #define M_EVENT_STRUCT_SIZE (sizeof (m_event_struct_t) - \
504 504 sizeof (struct scsi_pkt) + scsi_pkt_size())
505 505
506 506 #define MAX_IOC_COMMANDS 8
507 507
508 508 /*
509 509 * A pool of MAX_IOC_COMMANDS is maintained for event ack commands.
510 510 * A new event ack command requests mptsas_cmd and scsi_pkt structures
511 511 * from this pool, and returns it back when done.
512 512 */
513 513
514 514 typedef struct m_replyh_arg {
515 515 void *mpt;
516 516 uint32_t rfm;
517 517 } m_replyh_arg_t;
518 518 _NOTE(DATA_READABLE_WITHOUT_LOCK(m_replyh_arg_t::mpt))
519 519 _NOTE(DATA_READABLE_WITHOUT_LOCK(m_replyh_arg_t::rfm))
520 520
521 521 /*
522 522 * Flags for DR handler topology change
523 523 */
524 524 #define MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE 0x0
525 525 #define MPTSAS_TOPO_FLAG_EXPANDER_ASSOCIATED 0x1
526 526 #define MPTSAS_TOPO_FLAG_LUN_ASSOCIATED 0x2
527 527 #define MPTSAS_TOPO_FLAG_RAID_ASSOCIATED 0x4
528 528 #define MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED 0x8
529 529 #define MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE 0x10
530 530
531 531 typedef struct mptsas_topo_change_list {
532 532 void *mpt;
533 533 uint_t event;
534 534 union {
535 535 uint8_t physport;
536 536 mptsas_phymask_t phymask;
537 537 } un;
538 538 uint16_t devhdl;
539 539 void *object;
540 540 uint8_t flags;
541 541 struct mptsas_topo_change_list *next;
542 542 } mptsas_topo_change_list_t;
543 543
544 544
545 545 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::mpt))
546 546 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::event))
547 547 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::physport))
548 548 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::devhdl))
549 549 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::object))
550 550 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::flags))
551 551
552 552 /*
553 553 * Status types when calling mptsas_get_target_device_info
554 554 */
555 555 #define DEV_INFO_SUCCESS 0x0
556 556 #define DEV_INFO_FAIL_PAGE0 0x1
557 557 #define DEV_INFO_WRONG_DEVICE_TYPE 0x2
558 558 #define DEV_INFO_PHYS_DISK 0x3
559 559 #define DEV_INFO_FAIL_ALLOC 0x4
560 560
561 561 /*
562 562 * mpt hotplug event defines
563 563 */
564 564 #define MPTSAS_DR_EVENT_RECONFIG_TARGET 0x01
565 565 #define MPTSAS_DR_EVENT_OFFLINE_TARGET 0x02
566 566 #define MPTSAS_TOPO_FLAG_REMOVE_HANDLE 0x04
567 567
568 568 /*
569 569 * SMP target hotplug events
570 570 */
571 571 #define MPTSAS_DR_EVENT_RECONFIG_SMP 0x10
572 572 #define MPTSAS_DR_EVENT_OFFLINE_SMP 0x20
573 573 #define MPTSAS_DR_EVENT_MASK 0x3F
574 574
575 575 /*
576 576 * mpt hotplug status definition for m_dr_flag
577 577 */
578 578
579 579 /*
580 580 * MPTSAS_DR_INACTIVE
581 581 *
582 582 * The target is in a normal operating state.
583 583 * No dynamic reconfiguration operation is in progress.
584 584 */
585 585 #define MPTSAS_DR_INACTIVE 0x0
586 586 /*
587 587 * MPTSAS_DR_INTRANSITION
588 588 *
589 589 * The target is in a transition mode since
590 590 * hotplug event happens and offline procedure has not
591 591 * been finished
592 592 */
593 593 #define MPTSAS_DR_INTRANSITION 0x1
594 594
595 595 typedef struct mptsas_tgt_private {
596 596 int t_lun;
597 597 struct mptsas_target *t_private;
598 598 } mptsas_tgt_private_t;
599 599
600 600 /*
601 601 * The following defines are used in mptsas_set_init_mode to track the current
602 602 * state as we progress through reprogramming the HBA from target mode into
603 603 * initiator mode.
604 604 */
605 605
606 606 #define IOUC_READ_PAGE0 0x00000100
607 607 #define IOUC_READ_PAGE1 0x00000200
608 608 #define IOUC_WRITE_PAGE1 0x00000400
609 609 #define IOUC_DONE 0x00000800
610 610 #define DISCOVERY_IN_PROGRESS MPI2_SASIOUNIT0_PORTFLAGS_DISCOVERY_IN_PROGRESS
611 611 #define AUTO_PORT_CONFIGURATION MPI2_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG
612 612
613 613 /*
614 614 * Last allocated slot is used for TM requests. Since only m_max_requests
615 615 * frames are allocated, the last SMID will be m_max_requests - 1.
616 616 */
617 617 #define MPTSAS_SLOTS_SIZE(mpt) \
618 618 (sizeof (struct mptsas_slots) + (sizeof (struct mptsas_cmd *) * \
619 619 mpt->m_max_requests))
620 620 #define MPTSAS_TM_SLOT(mpt) (mpt->m_max_requests - 1)
621 621
622 622 /*
623 623 * Macro for phy_flags
624 624 */
625 625
626 626 typedef struct smhba_info {
627 627 kmutex_t phy_mutex;
628 628 uint8_t phy_id;
629 629 uint64_t sas_addr;
630 630 char path[8];
631 631 uint16_t owner_devhdl;
632 632 uint16_t attached_devhdl;
633 633 uint8_t attached_phy_identify;
634 634 uint32_t attached_phy_info;
635 635 uint8_t programmed_link_rate;
636 636 uint8_t hw_link_rate;
637 637 uint8_t change_count;
638 638 uint32_t phy_info;
639 639 uint8_t negotiated_link_rate;
640 640 uint8_t port_num;
641 641 kstat_t *phy_stats;
642 642 uint32_t invalid_dword_count;
643 643 uint32_t running_disparity_error_count;
644 644 uint32_t loss_of_dword_sync_count;
645 645 uint32_t phy_reset_problem_count;
646 646 void *mpt;
647 647 } smhba_info_t;
648 648
649 649 typedef struct mptsas_phy_info {
650 650 uint8_t port_num;
651 651 uint8_t port_flags;
652 652 uint16_t ctrl_devhdl;
653 653 uint32_t phy_device_type;
654 654 uint16_t attached_devhdl;
655 655 mptsas_phymask_t phy_mask;
656 656 smhba_info_t smhba_info;
657 657 } mptsas_phy_info_t;
658 658
659 659
660 660 typedef struct mptsas_doneq_thread_arg {
661 661 void *mpt;
662 662 uint64_t t;
663 663 } mptsas_doneq_thread_arg_t;
664 664
665 665 #define MPTSAS_DONEQ_THREAD_ACTIVE 0x1
666 666 typedef struct mptsas_doneq_thread_list {
667 667 mptsas_cmd_t *doneq;
668 668 mptsas_cmd_t **donetail;
669 669 kthread_t *threadp;
670 670 kcondvar_t cv;
671 671 ushort_t reserv1;
672 672 uint32_t reserv2;
673 673 kmutex_t mutex;
674 674 uint32_t flag;
675 675 uint32_t len;
676 676 mptsas_doneq_thread_arg_t arg;
677 677 } mptsas_doneq_thread_list_t;
678 678
679 679 typedef struct mptsas {
680 680 int m_instance;
681 681
682 682 struct mptsas *m_next;
683 683
684 684 scsi_hba_tran_t *m_tran;
685 685 smp_hba_tran_t *m_smptran;
686 686 kmutex_t m_mutex;
687 687 kmutex_t m_passthru_mutex;
688 688 kcondvar_t m_cv;
689 689 kcondvar_t m_passthru_cv;
690 690 kcondvar_t m_fw_cv;
691 691 kcondvar_t m_config_cv;
692 692 kcondvar_t m_fw_diag_cv;
693 693 dev_info_t *m_dip;
694 694
695 695 /*
696 696 * soft state flags
697 697 */
698 698 uint_t m_softstate;
699 699
700 700 refhash_t *m_targets;
701 701 refhash_t *m_smp_targets;
702 702
703 703 m_raidconfig_t m_raidconfig[MPTSAS_MAX_RAIDCONFIGS];
704 704 uint8_t m_num_raid_configs;
705 705
706 706 struct mptsas_slots *m_active; /* outstanding cmds */
707 707
708 708 mptsas_cmd_t *m_waitq; /* cmd queue for active request */
709 709 mptsas_cmd_t **m_waitqtail; /* wait queue tail ptr */
710 710
711 711 kmutex_t m_tx_waitq_mutex;
712 712 mptsas_cmd_t *m_tx_waitq; /* TX cmd queue for active request */
713 713 mptsas_cmd_t **m_tx_waitqtail; /* tx_wait queue tail ptr */
714 714 int m_tx_draining; /* TX queue draining flag */
715 715
716 716 mptsas_cmd_t *m_doneq; /* queue of completed commands */
717 717 mptsas_cmd_t **m_donetail; /* queue tail ptr */
718 718
719 719 /*
720 720 * variables for helper threads (fan-out interrupts)
721 721 */
722 722 mptsas_doneq_thread_list_t *m_doneq_thread_id;
723 723 uint32_t m_doneq_thread_n;
724 724 uint32_t m_doneq_thread_threshold;
725 725 uint32_t m_doneq_length_threshold;
726 726 uint32_t m_doneq_len;
727 727 kcondvar_t m_doneq_thread_cv;
728 728 kmutex_t m_doneq_mutex;
729 729
730 730 int m_ncmds; /* number of outstanding commands */
731 731 m_event_struct_t *m_ioc_event_cmdq; /* cmd queue for ioc event */
732 732 m_event_struct_t **m_ioc_event_cmdtail; /* ioc cmd queue tail */
733 733
734 734 ddi_acc_handle_t m_datap; /* operating regs data access handle */
735 735
736 736 struct _MPI2_SYSTEM_INTERFACE_REGS *m_reg;
737 737
738 738 ushort_t m_devid; /* device id of chip. */
739 739 uchar_t m_revid; /* revision of chip. */
740 740 uint16_t m_svid; /* subsystem Vendor ID of chip */
741 741 uint16_t m_ssid; /* subsystem Device ID of chip */
742 742
743 743 uchar_t m_sync_offset; /* default offset for this chip. */
744 744
745 745 timeout_id_t m_quiesce_timeid;
746 746
747 747 ddi_dma_handle_t m_dma_req_frame_hdl;
748 748 ddi_acc_handle_t m_acc_req_frame_hdl;
749 749 ddi_dma_handle_t m_dma_req_sense_hdl;
750 750 ddi_acc_handle_t m_acc_req_sense_hdl;
751 751 ddi_dma_handle_t m_dma_reply_frame_hdl;
752 752 ddi_acc_handle_t m_acc_reply_frame_hdl;
753 753 ddi_dma_handle_t m_dma_free_queue_hdl;
754 754 ddi_acc_handle_t m_acc_free_queue_hdl;
755 755 ddi_dma_handle_t m_dma_post_queue_hdl;
756 756 ddi_acc_handle_t m_acc_post_queue_hdl;
757 757
758 758 /*
759 759 * list of reset notification requests
760 760 */
761 761 struct scsi_reset_notify_entry *m_reset_notify_listf;
762 762
763 763 /*
764 764 * qfull handling
765 765 */
766 766 timeout_id_t m_restart_cmd_timeid;
767 767
768 768 /*
769 769 * scsi reset delay per bus
770 770 */
771 771 uint_t m_scsi_reset_delay;
772 772
773 773 int m_pm_idle_delay;
774 774
775 775 uchar_t m_polled_intr; /* intr was polled. */
776 776 uchar_t m_suspended; /* true if driver is suspended */
777 777
778 778 struct kmem_cache *m_kmem_cache;
779 779 struct kmem_cache *m_cache_frames;
780 780
781 781 /*
782 782 * hba options.
783 783 */
784 784 uint_t m_options;
785 785
786 786 int m_in_callback;
787 787
788 788 int m_power_level; /* current power level */
789 789
790 790 int m_busy; /* power management busy state */
791 791
792 792 off_t m_pmcsr_offset; /* PMCSR offset */
793 793
794 794 ddi_acc_handle_t m_config_handle;
795 795
796 796 ddi_dma_attr_t m_io_dma_attr; /* Used for data I/O */
797 797 ddi_dma_attr_t m_msg_dma_attr; /* Used for message frames */
798 798 ddi_device_acc_attr_t m_dev_acc_attr;
799 799 ddi_device_acc_attr_t m_reg_acc_attr;
800 800
801 801 /*
802 802 * request/reply variables
803 803 */
804 804 caddr_t m_req_frame;
805 805 uint64_t m_req_frame_dma_addr;
806 806 caddr_t m_req_sense;
807 807 caddr_t m_extreq_sense;
808 808 uint64_t m_req_sense_dma_addr;
809 809 caddr_t m_reply_frame;
810 810 uint64_t m_reply_frame_dma_addr;
811 811 caddr_t m_free_queue;
812 812 uint64_t m_free_queue_dma_addr;
813 813 caddr_t m_post_queue;
814 814 uint64_t m_post_queue_dma_addr;
815 815 struct map *m_erqsense_map;
816 816
817 817 m_replyh_arg_t *m_replyh_args;
818 818
819 819 uint16_t m_max_requests;
820 820 uint16_t m_req_frame_size;
821 821 uint16_t m_req_sense_size;
822 822
823 823 /*
824 824 * Max frames per request reprted in IOC Facts
825 825 */
826 826 uint8_t m_max_chain_depth;
827 827 /*
828 828 * Max frames per request which is used in reality. It's adjusted
829 829 * according DMA SG length attribute, and shall not exceed the
830 830 * m_max_chain_depth.
831 831 */
832 832 uint8_t m_max_request_frames;
833 833
834 834 uint16_t m_free_queue_depth;
835 835 uint16_t m_post_queue_depth;
836 836 uint16_t m_max_replies;
837 837 uint32_t m_free_index;
838 838 uint32_t m_post_index;
839 839 uint8_t m_reply_frame_size;
840 840 uint32_t m_ioc_capabilities;
841 841
842 842 /*
843 843 * indicates if the firmware was upload by the driver
844 844 * at boot time
845 845 */
846 846 ushort_t m_fwupload;
847 847
848 848 uint16_t m_productid;
849 849
850 850 /*
851 851 * per instance data structures for dma memory resources for
852 852 * MPI handshake protocol. only one handshake cmd can run at a time.
853 853 */
854 854 ddi_dma_handle_t m_hshk_dma_hdl;
855 855 ddi_acc_handle_t m_hshk_acc_hdl;
856 856 caddr_t m_hshk_memp;
857 857 size_t m_hshk_dma_size;
858 858
859 859 /* Firmware version on the card at boot time */
860 860 uint32_t m_fwversion;
861 861
862 862 /* MSI specific fields */
863 863 ddi_intr_handle_t *m_htable; /* For array of interrupts */
864 864 int m_intr_type; /* What type of interrupt */
865 865 int m_intr_cnt; /* # of intrs count returned */
866 866 size_t m_intr_size; /* Size of intr array */
867 867 uint_t m_intr_pri; /* Interrupt priority */
868 868 int m_intr_cap; /* Interrupt capabilities */
869 869 ddi_taskq_t *m_event_taskq;
870 870
871 871 /* SAS specific information */
872 872
873 873 union {
874 874 uint64_t m_base_wwid; /* Base WWID */
875 875 struct {
876 876 #ifdef _BIG_ENDIAN
877 877 uint32_t m_base_wwid_hi;
878 878 uint32_t m_base_wwid_lo;
879 879 #else
880 880 uint32_t m_base_wwid_lo;
881 881 uint32_t m_base_wwid_hi;
882 882 #endif
883 883 } sasaddr;
884 884 } un;
885 885
886 886 uint8_t m_num_phys; /* # of PHYs */
887 887 mptsas_phy_info_t m_phy_info[MPTSAS_MAX_PHYS];
888 888 uint8_t m_port_chng; /* initiator port changes */
889 889 MPI2_CONFIG_PAGE_MAN_0 m_MANU_page0; /* Manufactor page 0 info */
890 890 MPI2_CONFIG_PAGE_MAN_1 m_MANU_page1; /* Manufactor page 1 info */
891 891
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892 892 /* FMA Capabilities */
893 893 int m_fm_capabilities;
894 894 ddi_taskq_t *m_dr_taskq;
895 895 int m_mpxio_enable;
896 896 uint8_t m_done_traverse_dev;
897 897 uint8_t m_done_traverse_smp;
898 898 int m_diag_action_in_progress;
899 899 uint16_t m_dev_handle;
900 900 uint16_t m_smp_devhdl;
901 901
902 + /* In case of reset */
903 + ddi_taskq_t *m_reset_taskq;
904 +
902 905 /*
903 906 * Event recording
904 907 */
905 908 uint8_t m_event_index;
906 909 uint32_t m_event_number;
907 910 uint32_t m_event_mask[4];
908 911 mptsas_event_entry_t m_events[MPTSAS_EVENT_QUEUE_SIZE];
909 912
910 913 /*
911 914 * FW diag Buffer List
912 915 */
913 916 mptsas_fw_diagnostic_buffer_t
914 917 m_fw_diag_buffer_list[MPI2_DIAG_BUF_TYPE_COUNT];
915 918
916 919 /* GEN3 support */
917 920 uint8_t m_MPI25;
918 921
919 922 /*
920 923 * Event Replay flag (MUR support)
921 924 */
922 925 uint8_t m_event_replay;
923 926
924 927 /*
925 928 * IR Capable flag
926 929 */
927 930 uint8_t m_ir_capable;
928 931
929 932 /*
930 933 * Is HBA processing a diag reset?
931 934 */
932 935 uint8_t m_in_reset;
933 936
934 937 /*
935 938 * per instance cmd data structures for task management cmds
936 939 */
937 940 m_event_struct_t m_event_task_mgmt; /* must be last */
938 941 /* ... scsi_pkt_size */
939 942 } mptsas_t;
940 943 #define MPTSAS_SIZE (sizeof (struct mptsas) - \
941 944 sizeof (struct scsi_pkt) + scsi_pkt_size())
942 945 /*
943 946 * Only one of below two conditions is satisfied, we
944 947 * think the target is associated to the iport and
945 948 * allow call into mptsas_probe_lun().
946 949 * 1. physicalsport == physport
947 950 * 2. (phymask & (1 << physport)) == 0
948 951 * The condition #2 is because LSI uses lowest PHY
949 952 * number as the value of physical port when auto port
950 953 * configuration.
951 954 */
952 955 #define IS_SAME_PORT(physicalport, physport, phymask, dynamicport) \
953 956 ((physicalport == physport) || (dynamicport && (phymask & \
954 957 (1 << physport))))
955 958
956 959 _NOTE(MUTEX_PROTECTS_DATA(mptsas::m_mutex, mptsas))
957 960 _NOTE(SCHEME_PROTECTS_DATA("safe sharing", mptsas::m_next))
958 961 _NOTE(SCHEME_PROTECTS_DATA("stable data", mptsas::m_dip mptsas::m_tran))
959 962 _NOTE(SCHEME_PROTECTS_DATA("stable data", mptsas::m_kmem_cache))
960 963 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_io_dma_attr.dma_attr_sgllen))
961 964 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_devid))
962 965 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_productid))
963 966 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_mpxio_enable))
964 967 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_instance))
965 968
966 969 /*
967 970 * These should eventually migrate into the mpt header files
968 971 * that may become the /kernel/misc/mpt module...
969 972 */
970 973 #define mptsas_init_std_hdr(hdl, mp, DevHandle, Lun, ChainOffset, Function) \
971 974 mptsas_put_msg_DevHandle(hdl, mp, DevHandle); \
972 975 mptsas_put_msg_ChainOffset(hdl, mp, ChainOffset); \
973 976 mptsas_put_msg_Function(hdl, mp, Function); \
974 977 mptsas_put_msg_Lun(hdl, mp, Lun)
975 978
976 979 #define mptsas_put_msg_DevHandle(hdl, mp, val) \
977 980 ddi_put16(hdl, &(mp)->DevHandle, (val))
978 981 #define mptsas_put_msg_ChainOffset(hdl, mp, val) \
979 982 ddi_put8(hdl, &(mp)->ChainOffset, (val))
980 983 #define mptsas_put_msg_Function(hdl, mp, val) \
981 984 ddi_put8(hdl, &(mp)->Function, (val))
982 985 #define mptsas_put_msg_Lun(hdl, mp, val) \
983 986 ddi_put8(hdl, &(mp)->LUN[1], (val))
984 987
985 988 #define mptsas_get_msg_Function(hdl, mp) \
986 989 ddi_get8(hdl, &(mp)->Function)
987 990
988 991 #define mptsas_get_msg_MsgFlags(hdl, mp) \
989 992 ddi_get8(hdl, &(mp)->MsgFlags)
990 993
991 994 #define MPTSAS_ENABLE_DRWE(hdl) \
992 995 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \
993 996 MPI2_WRSEQ_FLUSH_KEY_VALUE); \
994 997 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \
995 998 MPI2_WRSEQ_1ST_KEY_VALUE); \
996 999 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \
997 1000 MPI2_WRSEQ_2ND_KEY_VALUE); \
998 1001 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \
999 1002 MPI2_WRSEQ_3RD_KEY_VALUE); \
1000 1003 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \
1001 1004 MPI2_WRSEQ_4TH_KEY_VALUE); \
1002 1005 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \
1003 1006 MPI2_WRSEQ_5TH_KEY_VALUE); \
1004 1007 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \
1005 1008 MPI2_WRSEQ_6TH_KEY_VALUE);
1006 1009
1007 1010 /*
1008 1011 * m_options flags
1009 1012 */
1010 1013 #define MPTSAS_OPT_PM 0x01 /* Power Management */
1011 1014
1012 1015 /*
1013 1016 * m_softstate flags
1014 1017 */
1015 1018 #define MPTSAS_SS_DRAINING 0x02
1016 1019 #define MPTSAS_SS_QUIESCED 0x04
1017 1020 #define MPTSAS_SS_MSG_UNIT_RESET 0x08
1018 1021 #define MPTSAS_DID_MSG_UNIT_RESET 0x10
1019 1022
1020 1023 /*
1021 1024 * regspec defines.
1022 1025 */
1023 1026 #define CONFIG_SPACE 0 /* regset[0] - configuration space */
1024 1027 #define IO_SPACE 1 /* regset[1] - used for i/o mapped device */
1025 1028 #define MEM_SPACE 2 /* regset[2] - used for memory mapped device */
1026 1029 #define BASE_REG2 3 /* regset[3] - used for 875 scripts ram */
1027 1030
1028 1031 /*
1029 1032 * Handy constants
1030 1033 */
1031 1034 #define FALSE 0
1032 1035 #define TRUE 1
1033 1036 #define UNDEFINED -1
1034 1037 #define FAILED -2
1035 1038
1036 1039 /*
1037 1040 * power management.
1038 1041 */
1039 1042 #define MPTSAS_POWER_ON(mpt) { \
1040 1043 pci_config_put16(mpt->m_config_handle, mpt->m_pmcsr_offset, \
1041 1044 PCI_PMCSR_D0); \
1042 1045 delay(drv_usectohz(10000)); \
1043 1046 (void) pci_restore_config_regs(mpt->m_dip); \
1044 1047 mptsas_setup_cmd_reg(mpt); \
1045 1048 }
1046 1049
1047 1050 #define MPTSAS_POWER_OFF(mpt) { \
1048 1051 (void) pci_save_config_regs(mpt->m_dip); \
1049 1052 pci_config_put16(mpt->m_config_handle, mpt->m_pmcsr_offset, \
1050 1053 PCI_PMCSR_D3HOT); \
1051 1054 mpt->m_power_level = PM_LEVEL_D3; \
1052 1055 }
1053 1056
1054 1057 /*
1055 1058 * inq_dtype:
1056 1059 * Bits 5 through 7 are the Peripheral Device Qualifier
1057 1060 * 001b: device not connected to the LUN
1058 1061 * Bits 0 through 4 are the Peripheral Device Type
1059 1062 * 1fh: Unknown or no device type
1060 1063 *
1061 1064 * Although the inquiry may return success, the following value
1062 1065 * means no valid LUN connected.
1063 1066 */
1064 1067 #define MPTSAS_VALID_LUN(sd_inq) \
1065 1068 (((sd_inq->inq_dtype & 0xe0) != 0x20) && \
1066 1069 ((sd_inq->inq_dtype & 0x1f) != 0x1f))
1067 1070
1068 1071 /*
1069 1072 * Default is to have 10 retries on receiving QFULL status and
1070 1073 * each retry to be after 100 ms.
1071 1074 */
1072 1075 #define QFULL_RETRIES 10
1073 1076 #define QFULL_RETRY_INTERVAL 100
1074 1077
1075 1078 /*
1076 1079 * Handy macros
1077 1080 */
1078 1081 #define Tgt(sp) ((sp)->cmd_pkt->pkt_address.a_target)
1079 1082 #define Lun(sp) ((sp)->cmd_pkt->pkt_address.a_lun)
1080 1083
1081 1084 #define IS_HEX_DIGIT(n) (((n) >= '0' && (n) <= '9') || \
1082 1085 ((n) >= 'a' && (n) <= 'f') || ((n) >= 'A' && (n) <= 'F'))
1083 1086
1084 1087 /*
1085 1088 * poll time for mptsas_pollret() and mptsas_wait_intr()
1086 1089 */
1087 1090 #define MPTSAS_POLL_TIME 30000 /* 30 seconds */
1088 1091
1089 1092 /*
1090 1093 * default time for mptsas_do_passthru
1091 1094 */
1092 1095 #define MPTSAS_PASS_THRU_TIME_DEFAULT 60 /* 60 seconds */
1093 1096
1094 1097 /*
1095 1098 * macro to return the effective address of a given per-target field
1096 1099 */
1097 1100 #define EFF_ADDR(start, offset) ((start) + (offset))
1098 1101
1099 1102 #define SDEV2ADDR(devp) (&((devp)->sd_address))
1100 1103 #define SDEV2TRAN(devp) ((devp)->sd_address.a_hba_tran)
1101 1104 #define PKT2TRAN(pkt) ((pkt)->pkt_address.a_hba_tran)
1102 1105 #define ADDR2TRAN(ap) ((ap)->a_hba_tran)
1103 1106 #define DIP2TRAN(dip) (ddi_get_driver_private(dip))
1104 1107
1105 1108
1106 1109 #define TRAN2MPT(hba) ((mptsas_t *)(hba)->tran_hba_private)
1107 1110 #define DIP2MPT(dip) (TRAN2MPT((scsi_hba_tran_t *)DIP2TRAN(dip)))
1108 1111 #define SDEV2MPT(sd) (TRAN2MPT(SDEV2TRAN(sd)))
1109 1112 #define PKT2MPT(pkt) (TRAN2MPT(PKT2TRAN(pkt)))
1110 1113
1111 1114 #define ADDR2MPT(ap) (TRAN2MPT(ADDR2TRAN(ap)))
1112 1115
1113 1116 #define POLL_TIMEOUT (2 * SCSI_POLL_TIMEOUT * 1000000)
1114 1117 #define SHORT_POLL_TIMEOUT (1000000) /* in usec, about 1 secs */
1115 1118 #define MPTSAS_QUIESCE_TIMEOUT 1 /* 1 sec */
1116 1119 #define MPTSAS_PM_IDLE_TIMEOUT 60 /* 60 seconds */
1117 1120
1118 1121 #define MPTSAS_GET_ISTAT(mpt) (ddi_get32((mpt)->m_datap, \
1119 1122 &(mpt)->m_reg->HostInterruptStatus))
1120 1123
1121 1124 #define MPTSAS_SET_SIGP(P) \
1122 1125 ClrSetBits(mpt->m_devaddr + NREG_ISTAT, 0, NB_ISTAT_SIGP)
1123 1126
1124 1127 #define MPTSAS_RESET_SIGP(P) (void) ddi_get8(mpt->m_datap, \
1125 1128 (uint8_t *)(mpt->m_devaddr + NREG_CTEST2))
1126 1129
1127 1130 #define MPTSAS_GET_INTCODE(P) (ddi_get32(mpt->m_datap, \
1128 1131 (uint32_t *)(mpt->m_devaddr + NREG_DSPS)))
1129 1132
1130 1133
1131 1134 #define MPTSAS_START_CMD(mpt, req_desc) \
1132 1135 ddi_put32(mpt->m_datap, &mpt->m_reg->RequestDescriptorPostLow, \
1133 1136 req_desc & 0xffffffffu); \
1134 1137 ddi_put32(mpt->m_datap, &mpt->m_reg->RequestDescriptorPostHigh, \
1135 1138 (req_desc >> 32) & 0xffffffffu);
1136 1139
1137 1140 #define INTPENDING(mpt) \
1138 1141 (MPTSAS_GET_ISTAT(mpt) & MPI2_HIS_REPLY_DESCRIPTOR_INTERRUPT)
1139 1142
1140 1143 /*
1141 1144 * Mask all interrupts to disable
1142 1145 */
1143 1146 #define MPTSAS_DISABLE_INTR(mpt) \
1144 1147 ddi_put32((mpt)->m_datap, &(mpt)->m_reg->HostInterruptMask, \
1145 1148 (MPI2_HIM_RIM | MPI2_HIM_DIM | MPI2_HIM_RESET_IRQ_MASK))
1146 1149
1147 1150 /*
1148 1151 * Mask Doorbell and Reset interrupts to enable reply desc int.
1149 1152 */
1150 1153 #define MPTSAS_ENABLE_INTR(mpt) \
1151 1154 ddi_put32(mpt->m_datap, &mpt->m_reg->HostInterruptMask, \
1152 1155 (MPI2_HIM_DIM | MPI2_HIM_RESET_IRQ_MASK))
1153 1156
1154 1157 #define MPTSAS_GET_NEXT_REPLY(mpt, index) \
1155 1158 &((uint64_t *)(void *)mpt->m_post_queue)[index]
1156 1159
1157 1160 #define MPTSAS_GET_NEXT_FRAME(mpt, SMID) \
1158 1161 (mpt->m_req_frame + (mpt->m_req_frame_size * SMID))
1159 1162
1160 1163 #define ClrSetBits32(hdl, reg, clr, set) \
1161 1164 ddi_put32(hdl, (reg), \
1162 1165 ((ddi_get32(mpt->m_datap, (reg)) & ~(clr)) | (set)))
1163 1166
1164 1167 #define ClrSetBits(reg, clr, set) \
1165 1168 ddi_put8(mpt->m_datap, (uint8_t *)(reg), \
1166 1169 ((ddi_get8(mpt->m_datap, (uint8_t *)(reg)) & ~(clr)) | (set)))
1167 1170
1168 1171 #define MPTSAS_WAITQ_RM(mpt, cmdp) \
1169 1172 if ((cmdp = mpt->m_waitq) != NULL) { \
1170 1173 /* If the queue is now empty fix the tail pointer */ \
1171 1174 if ((mpt->m_waitq = cmdp->cmd_linkp) == NULL) \
1172 1175 mpt->m_waitqtail = &mpt->m_waitq; \
1173 1176 cmdp->cmd_linkp = NULL; \
1174 1177 cmdp->cmd_queued = FALSE; \
1175 1178 }
1176 1179
1177 1180 #define MPTSAS_TX_WAITQ_RM(mpt, cmdp) \
1178 1181 if ((cmdp = mpt->m_tx_waitq) != NULL) { \
1179 1182 /* If the queue is now empty fix the tail pointer */ \
1180 1183 if ((mpt->m_tx_waitq = cmdp->cmd_linkp) == NULL) \
1181 1184 mpt->m_tx_waitqtail = &mpt->m_tx_waitq; \
1182 1185 cmdp->cmd_linkp = NULL; \
1183 1186 cmdp->cmd_queued = FALSE; \
1184 1187 }
1185 1188
1186 1189 /*
1187 1190 * defaults for the global properties
1188 1191 */
1189 1192 #define DEFAULT_SCSI_OPTIONS SCSI_OPTIONS_DR
1190 1193 #define DEFAULT_TAG_AGE_LIMIT 2
1191 1194 #define DEFAULT_WD_TICK 1
1192 1195
1193 1196 /*
1194 1197 * invalid hostid.
1195 1198 */
1196 1199 #define MPTSAS_INVALID_HOSTID -1
1197 1200
1198 1201 /*
1199 1202 * Get/Set hostid from SCSI port configuration page
1200 1203 */
1201 1204 #define MPTSAS_GET_HOST_ID(configuration) (configuration & 0xFF)
1202 1205 #define MPTSAS_SET_HOST_ID(hostid) (hostid | ((1 << hostid) << 16))
1203 1206
1204 1207 /*
1205 1208 * Config space.
1206 1209 */
1207 1210 #define MPTSAS_LATENCY_TIMER 0x40
1208 1211
1209 1212 /*
1210 1213 * Offset to firmware version
1211 1214 */
1212 1215 #define MPTSAS_FW_VERSION_OFFSET 9
1213 1216
1214 1217 /*
1215 1218 * Offset and masks to get at the ProductId field
1216 1219 */
1217 1220 #define MPTSAS_FW_PRODUCTID_OFFSET 8
1218 1221 #define MPTSAS_FW_PRODUCTID_MASK 0xFFFF0000
1219 1222 #define MPTSAS_FW_PRODUCTID_SHIFT 16
1220 1223
1221 1224 /*
1222 1225 * Subsystem ID for HBAs.
1223 1226 */
1224 1227 #define MPTSAS_HBA_SUBSYSTEM_ID 0x10C0
1225 1228 #define MPTSAS_RHEA_SUBSYSTEM_ID 0x10B0
1226 1229
1227 1230 /*
1228 1231 * reset delay tick
1229 1232 */
1230 1233 #define MPTSAS_WATCH_RESET_DELAY_TICK 50 /* specified in milli seconds */
1231 1234
1232 1235 /*
1233 1236 * Ioc reset return values
1234 1237 */
1235 1238 #define MPTSAS_RESET_FAIL -1
1236 1239 #define MPTSAS_NO_RESET 0
1237 1240 #define MPTSAS_SUCCESS_HARDRESET 1
1238 1241 #define MPTSAS_SUCCESS_MUR 2
1239 1242
1240 1243 /*
1241 1244 * throttle support.
1242 1245 */
1243 1246 #define MAX_THROTTLE 32
1244 1247 #define HOLD_THROTTLE 0
1245 1248 #define DRAIN_THROTTLE -1
1246 1249 #define QFULL_THROTTLE -2
1247 1250
1248 1251 /*
1249 1252 * Passthrough/config request flags
1250 1253 */
1251 1254 #define MPTSAS_DATA_ALLOCATED 0x0001
1252 1255 #define MPTSAS_DATAOUT_ALLOCATED 0x0002
1253 1256 #define MPTSAS_REQUEST_POOL_CMD 0x0004
1254 1257 #define MPTSAS_ADDRESS_REPLY 0x0008
1255 1258 #define MPTSAS_CMD_TIMEOUT 0x0010
1256 1259
1257 1260 /*
1258 1261 * response code tlr flag
1259 1262 */
1260 1263 #define MPTSAS_SCSI_RESPONSE_CODE_TLR_OFF 0x02
1261 1264
1262 1265 /*
1263 1266 * System Events
1264 1267 */
1265 1268 #ifndef DDI_VENDOR_LSI
1266 1269 #define DDI_VENDOR_LSI "LSI"
1267 1270 #endif /* DDI_VENDOR_LSI */
1268 1271
1269 1272 /*
1270 1273 * Shared functions
1271 1274 */
1272 1275 int mptsas_save_cmd(struct mptsas *mpt, struct mptsas_cmd *cmd);
1273 1276 void mptsas_remove_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd);
1274 1277 void mptsas_waitq_add(mptsas_t *mpt, mptsas_cmd_t *cmd);
1275 1278 void mptsas_log(struct mptsas *mpt, int level, char *fmt, ...);
1276 1279 int mptsas_poll(mptsas_t *mpt, mptsas_cmd_t *poll_cmd, int polltime);
1277 1280 int mptsas_do_dma(mptsas_t *mpt, uint32_t size, int var, int (*callback)());
1278 1281 int mptsas_update_flash(mptsas_t *mpt, caddr_t ptrbuffer, uint32_t size,
1279 1282 uint8_t type, int mode);
1280 1283 int mptsas_check_flash(mptsas_t *mpt, caddr_t origfile, uint32_t size,
1281 1284 uint8_t type, int mode);
1282 1285 int mptsas_download_firmware();
1283 1286 int mptsas_can_download_firmware();
1284 1287 int mptsas_dma_alloc(mptsas_t *mpt, mptsas_dma_alloc_state_t *dma_statep);
1285 1288 void mptsas_dma_free(mptsas_dma_alloc_state_t *dma_statep);
1286 1289 mptsas_phymask_t mptsas_physport_to_phymask(mptsas_t *mpt, uint8_t physport);
1287 1290 void mptsas_fma_check(mptsas_t *mpt, mptsas_cmd_t *cmd);
1288 1291 int mptsas_check_acc_handle(ddi_acc_handle_t handle);
1289 1292 int mptsas_check_dma_handle(ddi_dma_handle_t handle);
1290 1293 void mptsas_fm_ereport(mptsas_t *mpt, char *detail);
1291 1294 int mptsas_dma_addr_create(mptsas_t *mpt, ddi_dma_attr_t dma_attr,
1292 1295 ddi_dma_handle_t *dma_hdp, ddi_acc_handle_t *acc_hdp, caddr_t *dma_memp,
1293 1296 uint32_t alloc_size, ddi_dma_cookie_t *cookiep);
1294 1297 void mptsas_dma_addr_destroy(ddi_dma_handle_t *, ddi_acc_handle_t *);
1295 1298
1296 1299 /*
1297 1300 * impl functions
1298 1301 */
1299 1302 int mptsas_ioc_wait_for_response(mptsas_t *mpt);
1300 1303 int mptsas_ioc_wait_for_doorbell(mptsas_t *mpt);
1301 1304 int mptsas_ioc_reset(mptsas_t *mpt, int);
1302 1305 int mptsas_send_handshake_msg(mptsas_t *mpt, caddr_t memp, int numbytes,
1303 1306 ddi_acc_handle_t accessp);
1304 1307 int mptsas_get_handshake_msg(mptsas_t *mpt, caddr_t memp, int numbytes,
1305 1308 ddi_acc_handle_t accessp);
1306 1309 int mptsas_send_config_request_msg(mptsas_t *mpt, uint8_t action,
1307 1310 uint8_t pagetype, uint32_t pageaddress, uint8_t pagenumber,
1308 1311 uint8_t pageversion, uint8_t pagelength, uint32_t SGEflagslength,
1309 1312 uint64_t SGEaddress);
1310 1313 int mptsas_send_extended_config_request_msg(mptsas_t *mpt, uint8_t action,
1311 1314 uint8_t extpagetype, uint32_t pageaddress, uint8_t pagenumber,
1312 1315 uint8_t pageversion, uint16_t extpagelength,
1313 1316 uint32_t SGEflagslength, uint64_t SGEaddress);
1314 1317
1315 1318 int mptsas_request_from_pool(mptsas_t *mpt, mptsas_cmd_t **cmd,
1316 1319 struct scsi_pkt **pkt);
1317 1320 void mptsas_return_to_pool(mptsas_t *mpt, mptsas_cmd_t *cmd);
1318 1321 void mptsas_destroy_ioc_event_cmd(mptsas_t *mpt);
1319 1322 void mptsas_start_config_page_access(mptsas_t *mpt, mptsas_cmd_t *cmd);
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1320 1323 int mptsas_access_config_page(mptsas_t *mpt, uint8_t action, uint8_t page_type,
1321 1324 uint8_t page_number, uint32_t page_address, int (*callback) (mptsas_t *,
1322 1325 caddr_t, ddi_acc_handle_t, uint16_t, uint32_t, va_list), ...);
1323 1326
1324 1327 int mptsas_ioc_task_management(mptsas_t *mpt, int task_type,
1325 1328 uint16_t dev_handle, int lun, uint8_t *reply, uint32_t reply_size,
1326 1329 int mode);
1327 1330 int mptsas_send_event_ack(mptsas_t *mpt, uint32_t event, uint32_t eventcntx);
1328 1331 void mptsas_send_pending_event_ack(mptsas_t *mpt);
1329 1332 void mptsas_set_throttle(struct mptsas *mpt, mptsas_target_t *ptgt, int what);
1333 +void mptsas_handle_restart_ioc(void *mpt);
1330 1334 int mptsas_restart_ioc(mptsas_t *mpt);
1331 1335 void mptsas_update_driver_data(struct mptsas *mpt);
1332 1336 uint64_t mptsas_get_sata_guid(mptsas_t *mpt, mptsas_target_t *ptgt, int lun);
1333 1337
1334 1338 /*
1335 1339 * init functions
1336 1340 */
1337 1341 int mptsas_ioc_get_facts(mptsas_t *mpt);
1338 1342 int mptsas_ioc_get_port_facts(mptsas_t *mpt, int port);
1339 1343 int mptsas_ioc_enable_port(mptsas_t *mpt);
1340 1344 int mptsas_ioc_enable_event_notification(mptsas_t *mpt);
1341 1345 int mptsas_ioc_init(mptsas_t *mpt);
1342 1346
1343 1347 /*
1344 1348 * configuration pages operation
1345 1349 */
1346 1350 int mptsas_get_sas_device_page0(mptsas_t *mpt, uint32_t page_address,
1347 1351 uint16_t *dev_handle, uint64_t *sas_wwn, uint32_t *dev_info,
1348 1352 uint8_t *physport, uint8_t *phynum, uint16_t *pdevhandle,
1349 1353 uint16_t *slot_num, uint16_t *enclosure, uint16_t *io_flags);
1350 1354 int mptsas_get_sas_io_unit_page(mptsas_t *mpt);
1351 1355 int mptsas_get_sas_io_unit_page_hndshk(mptsas_t *mpt);
1352 1356 int mptsas_get_sas_expander_page0(mptsas_t *mpt, uint32_t page_address,
1353 1357 mptsas_smp_t *info);
1354 1358 int mptsas_set_ioc_params(mptsas_t *mpt);
1355 1359 int mptsas_get_manufacture_page5(mptsas_t *mpt);
1356 1360 int mptsas_get_sas_port_page0(mptsas_t *mpt, uint32_t page_address,
1357 1361 uint64_t *sas_wwn, uint8_t *portwidth);
1358 1362 int mptsas_get_bios_page3(mptsas_t *mpt, uint32_t *bios_version);
1359 1363 int
1360 1364 mptsas_get_sas_phy_page0(mptsas_t *mpt, uint32_t page_address,
1361 1365 smhba_info_t *info);
1362 1366 int
1363 1367 mptsas_get_sas_phy_page1(mptsas_t *mpt, uint32_t page_address,
1364 1368 smhba_info_t *info);
1365 1369 int
1366 1370 mptsas_get_manufacture_page0(mptsas_t *mpt);
1367 1371 void
1368 1372 mptsas_create_phy_stats(mptsas_t *mpt, char *iport, dev_info_t *dip);
1369 1373 void mptsas_destroy_phy_stats(mptsas_t *mpt);
1370 1374 int mptsas_smhba_phy_init(mptsas_t *mpt);
1371 1375 /*
1372 1376 * RAID functions
1373 1377 */
1374 1378 int mptsas_get_raid_settings(mptsas_t *mpt, mptsas_raidvol_t *raidvol);
1375 1379 int mptsas_get_raid_info(mptsas_t *mpt);
1376 1380 int mptsas_get_physdisk_settings(mptsas_t *mpt, mptsas_raidvol_t *raidvol,
1377 1381 uint8_t physdisknum);
1378 1382 int mptsas_delete_volume(mptsas_t *mpt, uint16_t volid);
1379 1383 void mptsas_raid_action_system_shutdown(mptsas_t *mpt);
1380 1384
1381 1385 #define MPTSAS_IOCSTATUS(status) (status & MPI2_IOCSTATUS_MASK)
1382 1386 /*
1383 1387 * debugging.
1384 1388 * MPTSAS_DBGLOG_LINECNT must be a power of 2.
1385 1389 */
1386 1390 #define MPTSAS_DBGLOG_LINECNT 128
1387 1391 #define MPTSAS_DBGLOG_LINELEN 256
1388 1392 #define MPTSAS_DBGLOG_BUFSIZE (MPTSAS_DBGLOG_LINECNT * MPTSAS_DBGLOG_LINELEN)
1389 1393
1390 1394 #if defined(MPTSAS_DEBUG)
1391 1395
1392 1396 extern uint32_t mptsas_debugprt_flags;
1393 1397 extern uint32_t mptsas_debuglog_flags;
1394 1398
1395 1399 void mptsas_printf(char *fmt, ...);
1396 1400 void mptsas_debug_log(char *fmt, ...);
1397 1401
1398 1402 #define MPTSAS_DBGPR(m, args) \
1399 1403 if (mptsas_debugprt_flags & (m)) \
1400 1404 mptsas_printf args; \
1401 1405 if (mptsas_debuglog_flags & (m)) \
1402 1406 mptsas_debug_log args
1403 1407 #else /* ! defined(MPTSAS_DEBUG) */
1404 1408 #define MPTSAS_DBGPR(m, args)
1405 1409 #endif /* defined(MPTSAS_DEBUG) */
1406 1410
1407 1411 #define NDBG0(args) MPTSAS_DBGPR(0x01, args) /* init */
1408 1412 #define NDBG1(args) MPTSAS_DBGPR(0x02, args) /* normal running */
1409 1413 #define NDBG2(args) MPTSAS_DBGPR(0x04, args) /* property handling */
1410 1414 #define NDBG3(args) MPTSAS_DBGPR(0x08, args) /* pkt handling */
1411 1415
1412 1416 #define NDBG4(args) MPTSAS_DBGPR(0x10, args) /* kmem alloc/free */
1413 1417 #define NDBG5(args) MPTSAS_DBGPR(0x20, args) /* polled cmds */
1414 1418 #define NDBG6(args) MPTSAS_DBGPR(0x40, args) /* interrupts */
1415 1419 #define NDBG7(args) MPTSAS_DBGPR(0x80, args) /* queue handling */
1416 1420
1417 1421 #define NDBG8(args) MPTSAS_DBGPR(0x0100, args) /* arq */
1418 1422 #define NDBG9(args) MPTSAS_DBGPR(0x0200, args) /* Tagged Q'ing */
1419 1423 #define NDBG10(args) MPTSAS_DBGPR(0x0400, args) /* halting chip */
1420 1424 #define NDBG11(args) MPTSAS_DBGPR(0x0800, args) /* power management */
1421 1425
1422 1426 #define NDBG12(args) MPTSAS_DBGPR(0x1000, args) /* enumeration */
1423 1427 #define NDBG13(args) MPTSAS_DBGPR(0x2000, args) /* configuration page */
1424 1428 #define NDBG14(args) MPTSAS_DBGPR(0x4000, args) /* LED control */
1425 1429 #define NDBG15(args) MPTSAS_DBGPR(0x8000, args) /* Passthrough */
1426 1430
1427 1431 #define NDBG16(args) MPTSAS_DBGPR(0x010000, args) /* SAS Broadcasts */
1428 1432 #define NDBG17(args) MPTSAS_DBGPR(0x020000, args) /* scatter/gather */
1429 1433 #define NDBG18(args) MPTSAS_DBGPR(0x040000, args)
1430 1434 #define NDBG19(args) MPTSAS_DBGPR(0x080000, args) /* handshaking */
1431 1435
1432 1436 #define NDBG20(args) MPTSAS_DBGPR(0x100000, args) /* events */
1433 1437 #define NDBG21(args) MPTSAS_DBGPR(0x200000, args) /* dma */
1434 1438 #define NDBG22(args) MPTSAS_DBGPR(0x400000, args) /* reset */
1435 1439 #define NDBG23(args) MPTSAS_DBGPR(0x800000, args) /* abort */
1436 1440
1437 1441 #define NDBG24(args) MPTSAS_DBGPR(0x1000000, args) /* capabilities */
1438 1442 #define NDBG25(args) MPTSAS_DBGPR(0x2000000, args) /* flushing */
1439 1443 #define NDBG26(args) MPTSAS_DBGPR(0x4000000, args)
1440 1444 #define NDBG27(args) MPTSAS_DBGPR(0x8000000, args) /* passthrough */
1441 1445
1442 1446 #define NDBG28(args) MPTSAS_DBGPR(0x10000000, args) /* hotplug */
1443 1447 #define NDBG29(args) MPTSAS_DBGPR(0x20000000, args) /* timeouts */
1444 1448 #define NDBG30(args) MPTSAS_DBGPR(0x40000000, args) /* mptsas_watch */
1445 1449 #define NDBG31(args) MPTSAS_DBGPR(0x80000000, args) /* negotations */
1446 1450
1447 1451 /*
1448 1452 * auto request sense
1449 1453 */
1450 1454 #define RQ_MAKECOM_COMMON(pkt, flag, cmd) \
1451 1455 (pkt)->pkt_flags = (flag), \
1452 1456 ((union scsi_cdb *)(pkt)->pkt_cdbp)->scc_cmd = (cmd), \
1453 1457 ((union scsi_cdb *)(pkt)->pkt_cdbp)->scc_lun = \
1454 1458 (pkt)->pkt_address.a_lun
1455 1459
1456 1460 #define RQ_MAKECOM_G0(pkt, flag, cmd, addr, cnt) \
1457 1461 RQ_MAKECOM_COMMON((pkt), (flag), (cmd)), \
1458 1462 FORMG0ADDR(((union scsi_cdb *)(pkt)->pkt_cdbp), (addr)), \
1459 1463 FORMG0COUNT(((union scsi_cdb *)(pkt)->pkt_cdbp), (cnt))
1460 1464
1461 1465
1462 1466 #ifdef __cplusplus
1463 1467 }
1464 1468 #endif
1465 1469
1466 1470 #endif /* _SYS_SCSI_ADAPTERS_MPTVAR_H */
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