1 /*
   2  * CDDL HEADER START
   3  *
   4  * The contents of this file are subject to the terms of the
   5  * Common Development and Distribution License (the "License").
   6  * You may not use this file except in compliance with the License.
   7  *
   8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
   9  * or http://www.opensolaris.org/os/licensing.
  10  * See the License for the specific language governing permissions
  11  * and limitations under the License.
  12  *
  13  * When distributing Covered Code, include this CDDL HEADER in each
  14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
  15  * If applicable, add the following below this CDDL HEADER, with the
  16  * fields enclosed by brackets "[]" replaced with your own identifying
  17  * information: Portions Copyright [yyyy] [name of copyright owner]
  18  *
  19  * CDDL HEADER END
  20  */
  21 
  22 /*
  23  * Copyright (c) 2009, 2010, Oracle and/or its affiliates. All rights reserved.
  24  * Copyright 2014 Nexenta Systems, Inc. All rights reserved.
  25  * Copyright (c) 2013, Joyent, Inc. All rights reserved.
  26  * Copyright (c) 2014, Tegile Systems Inc. All rights reserved.
  27  */
  28 
  29 /*
  30  * Copyright (c) 2000 to 2010, LSI Corporation.
  31  * All rights reserved.
  32  *
  33  * Redistribution and use in source and binary forms of all code within
  34  * this file that is exclusively owned by LSI, with or without
  35  * modification, is permitted provided that, in addition to the CDDL 1.0
  36  * License requirements, the following conditions are met:
  37  *
  38  *    Neither the name of the author nor the names of its contributors may be
  39  *    used to endorse or promote products derived from this software without
  40  *    specific prior written permission.
  41  *
  42  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  43  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  44  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
  45  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
  46  * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  47  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  48  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
  49  * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  50  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  51  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
  52  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
  53  * DAMAGE.
  54  */
  55 
  56 #ifndef _SYS_SCSI_ADAPTERS_MPTVAR_H
  57 #define _SYS_SCSI_ADAPTERS_MPTVAR_H
  58 
  59 #include <sys/byteorder.h>
  60 #include <sys/queue.h>
  61 #include <sys/isa_defs.h>
  62 #include <sys/sunmdi.h>
  63 #include <sys/mdi_impldefs.h>
  64 #include <sys/scsi/adapters/mpt_sas/mptsas_hash.h>
  65 #include <sys/scsi/adapters/mpt_sas/mptsas_ioctl.h>
  66 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_tool.h>
  67 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_cnfg.h>
  68 
  69 #ifdef  __cplusplus
  70 extern "C" {
  71 #endif
  72 
  73 /*
  74  * Compile options
  75  */
  76 #ifdef DEBUG
  77 #define MPTSAS_DEBUG            /* turn on debugging code */
  78 #endif  /* DEBUG */
  79 
  80 #define MPTSAS_INITIAL_SOFT_SPACE       4
  81 
  82 #define MAX_MPI_PORTS           16
  83 
  84 /*
  85  * Note below macro definition and data type definition
  86  * are used for phy mask handling, it should be changed
  87  * simultaneously.
  88  */
  89 #define MPTSAS_MAX_PHYS         16
  90 typedef uint16_t                mptsas_phymask_t;
  91 
  92 #define MPTSAS_INVALID_DEVHDL   0xffff
  93 #define MPTSAS_SATA_GUID        "sata-guid"
  94 
  95 /*
  96  * Hash table sizes for SMP targets (i.e., expanders) and ordinary SSP/STP
  97  * targets.  There's no need to go overboard here, as the ordinary paths for
  98  * I/O do not normally require hashed target lookups.  These should be good
  99  * enough and then some for any fabric within the hardware's capabilities.
 100  */
 101 #define MPTSAS_SMP_BUCKET_COUNT         23
 102 #define MPTSAS_TARGET_BUCKET_COUNT      97
 103 
 104 /*
 105  * MPT HW defines
 106  */
 107 #define MPTSAS_MAX_DISKS_IN_CONFIG      14
 108 #define MPTSAS_MAX_DISKS_IN_VOL         10
 109 #define MPTSAS_MAX_HOTSPARES            2
 110 #define MPTSAS_MAX_RAIDVOLS             2
 111 #define MPTSAS_MAX_RAIDCONFIGS          5
 112 
 113 /*
 114  * 64-bit SAS WWN is displayed as 16 characters as HEX characters,
 115  * plus two means the prefix 'w' and end of the string '\0'.
 116  */
 117 #define MPTSAS_WWN_STRLEN       (16 + 2)
 118 #define MPTSAS_MAX_GUID_LEN     64
 119 
 120 /*
 121  * DMA routine flags
 122  */
 123 #define MPTSAS_DMA_HANDLE_ALLOCD        0x2
 124 #define MPTSAS_DMA_MEMORY_ALLOCD        0x4
 125 #define MPTSAS_DMA_HANDLE_BOUND 0x8
 126 
 127 /*
 128  * If the HBA supports DMA or bus-mastering, you may have your own
 129  * scatter-gather list for physically non-contiguous memory in one
 130  * I/O operation; if so, there's probably a size for that list.
 131  * It must be placed in the ddi_dma_lim_t structure, so that the system
 132  * DMA-support routines can use it to break up the I/O request, so we
 133  * define it here.
 134  */
 135 #if defined(__sparc)
 136 #define MPTSAS_MAX_DMA_SEGS     1
 137 #define MPTSAS_MAX_CMD_SEGS     1
 138 #else
 139 #define MPTSAS_MAX_DMA_SEGS     256
 140 #define MPTSAS_MAX_CMD_SEGS     257
 141 #endif
 142 #define MPTSAS_MAX_FRAME_SGES(mpt) \
 143         (((mpt->m_req_frame_size - (sizeof (MPI2_SCSI_IO_REQUEST))) / 8) + 1)
 144 
 145 #define MPTSAS_SGE_SIZE(mpt)                                    \
 146         ((mpt)->m_MPI25 ? sizeof (MPI2_IEEE_SGE_SIMPLE64) :  \
 147             sizeof (MPI2_SGE_SIMPLE64))
 148 
 149 /*
 150  * Calculating how many 64-bit DMA simple elements can be stored in the first
 151  * frame. Note that msg_scsi_io_request contains 2 double-words (8 bytes) for
 152  * element storage.  And 64-bit dma element is 3 double-words (12 bytes) in
 153  * size. IEEE 64-bit dma element used for SAS3 controllers is 4 double-words
 154  * (16 bytes).
 155  */
 156 #define MPTSAS_MAX_FRAME_SGES64(mpt) \
 157         ((mpt->m_req_frame_size - \
 158         sizeof (MPI2_SCSI_IO_REQUEST) + sizeof (MPI2_SGE_IO_UNION)) / \
 159         MPTSAS_SGE_SIZE(mpt))
 160 
 161 /*
 162  * Scatter-gather list structure defined by HBA hardware
 163  */
 164 typedef struct NcrTableIndirect {       /* Table Indirect entries */
 165         uint32_t count;         /* 24 bit count */
 166         union {
 167                 uint32_t address32;     /* 32 bit address */
 168                 struct {
 169                         uint32_t Low;
 170                         uint32_t High;
 171                 } address64;            /* 64 bit address */
 172         } addr;
 173 } mptti_t;
 174 
 175 /*
 176  * preferred pkt_private length in 64-bit quantities
 177  */
 178 #ifdef  _LP64
 179 #define PKT_PRIV_SIZE   2
 180 #define PKT_PRIV_LEN    16      /* in bytes */
 181 #else /* _ILP32 */
 182 #define PKT_PRIV_SIZE   1
 183 #define PKT_PRIV_LEN    8       /* in bytes */
 184 #endif
 185 
 186 #define PKT2CMD(pkt)    ((struct mptsas_cmd *)((pkt)->pkt_ha_private))
 187 #define CMD2PKT(cmdp)   ((struct scsi_pkt *)((cmdp)->cmd_pkt))
 188 #define EXTCMDS_STATUS_SIZE (sizeof (struct scsi_arq_status))
 189 
 190 /*
 191  * get offset of item in structure
 192  */
 193 #define MPTSAS_GET_ITEM_OFF(type, member) ((size_t)(&((type *)0)->member))
 194 
 195 /*
 196  * WWID provided by LSI firmware is generated by firmware but the WWID is not
 197  * IEEE NAA standard format, OBP has no chance to distinguish format of unit
 198  * address. According LSI's confirmation, the top nibble of RAID WWID is
 199  * meanless, so the consensus between Solaris and OBP is to replace top nibble
 200  * of WWID provided by LSI to "3" always to hint OBP that this is a RAID WWID
 201  * format unit address.
 202  */
 203 #define MPTSAS_RAID_WWID(wwid) \
 204         ((wwid & 0x0FFFFFFFFFFFFFFF) | 0x3000000000000000)
 205 
 206 typedef struct mptsas_target_addr {
 207         uint64_t mta_wwn;
 208         mptsas_phymask_t mta_phymask;
 209 } mptsas_target_addr_t;
 210 
 211 TAILQ_HEAD(mptsas_active_cmdq, mptsas_cmd);
 212 typedef struct mptsas_active_cmdq mptsas_active_cmdq_t;
 213 
 214 typedef struct mptsas_target {
 215                 mptsas_target_addr_t    m_addr;
 216                 refhash_link_t          m_link;
 217                 uint8_t                 m_dr_flag;
 218                 uint16_t                m_devhdl;
 219                 uint32_t                m_deviceinfo;
 220                 uint8_t                 m_phynum;
 221                 uint32_t                m_dups;
 222                 mptsas_active_cmdq_t    m_active_cmdq;
 223                 int32_t                 m_t_throttle;
 224                 int32_t                 m_t_ncmds;
 225                 int32_t                 m_reset_delay;
 226                 int32_t                 m_t_nwait;
 227 
 228                 uint16_t                m_qfull_retry_interval;
 229                 uint8_t                 m_qfull_retries;
 230                 uint16_t                m_io_flags;
 231                 uint16_t                m_enclosure;
 232                 uint16_t                m_slot_num;
 233                 uint32_t                m_tgt_unconfigured;
 234                 uint8_t                 m_led_status;
 235                 uint8_t                 m_scsi_req_desc_type;
 236 
 237 } mptsas_target_t;
 238 
 239 /*
 240  * If you change this structure, be sure that mptsas_smp_target_copy()
 241  * does the right thing.
 242  */
 243 typedef struct mptsas_smp {
 244         mptsas_target_addr_t    m_addr;
 245         refhash_link_t          m_link;
 246         uint16_t                m_devhdl;
 247         uint32_t                m_deviceinfo;
 248         uint16_t                m_pdevhdl;
 249         uint32_t                m_pdevinfo;
 250 } mptsas_smp_t;
 251 
 252 typedef struct mptsas_cache_frames {
 253         ddi_dma_handle_t m_dma_hdl;
 254         ddi_acc_handle_t m_acc_hdl;
 255         caddr_t m_frames_addr;
 256         uint64_t m_phys_addr;
 257 } mptsas_cache_frames_t;
 258 
 259 typedef struct  mptsas_cmd {
 260         uint_t                  cmd_flags;      /* flags from scsi_init_pkt */
 261         ddi_dma_handle_t        cmd_dmahandle;  /* dma handle */
 262         ddi_dma_cookie_t        cmd_cookie;
 263         uint_t                  cmd_cookiec;
 264         uint_t                  cmd_winindex;
 265         uint_t                  cmd_nwin;
 266         uint_t                  cmd_cur_cookie;
 267         off_t                   cmd_dma_offset;
 268         size_t                  cmd_dma_len;
 269         uint32_t                cmd_totaldmacount;
 270         caddr_t                 cmd_arq_buf;
 271 
 272         int                     cmd_pkt_flags;
 273 
 274         /* pending expiration time for command in active slot */
 275         hrtime_t                cmd_active_expiration;
 276         TAILQ_ENTRY(mptsas_cmd) cmd_active_link;
 277 
 278         struct scsi_pkt         *cmd_pkt;
 279         struct scsi_arq_status  cmd_scb;
 280         uchar_t                 cmd_cdblen;     /* length of cdb */
 281         uchar_t                 cmd_rqslen;     /* len of requested rqsense */
 282         uchar_t                 cmd_privlen;
 283         uint16_t                cmd_extrqslen;  /* len of extended rqsense */
 284         uint16_t                cmd_extrqschunks; /* len in map chunks */
 285         uint16_t                cmd_extrqsidx;  /* Index into map */
 286         uint_t                  cmd_scblen;
 287         uint32_t                cmd_dmacount;
 288         uint64_t                cmd_dma_addr;
 289         uchar_t                 cmd_age;
 290         ushort_t                cmd_qfull_retries;
 291         uchar_t                 cmd_queued;     /* true if queued */
 292         struct mptsas_cmd       *cmd_linkp;
 293         mptti_t                 *cmd_sg; /* Scatter/Gather structure */
 294         uchar_t                 cmd_cdb[SCSI_CDB_SIZE];
 295         uint64_t                cmd_pkt_private[PKT_PRIV_LEN];
 296         uint32_t                cmd_slot;
 297         uint32_t                ioc_cmd_slot;
 298 
 299         mptsas_cache_frames_t   *cmd_extra_frames;
 300 
 301         uint32_t                cmd_rfm;
 302         mptsas_target_t         *cmd_tgt_addr;
 303 } mptsas_cmd_t;
 304 
 305 /*
 306  * These are the defined cmd_flags for this structure.
 307  */
 308 #define CFLAG_CMDDISC           0x000001 /* cmd currently disconnected */
 309 #define CFLAG_WATCH             0x000002 /* watchdog time for this command */
 310 #define CFLAG_FINISHED          0x000004 /* command completed */
 311 #define CFLAG_CHKSEG            0x000008 /* check cmd_data within seg */
 312 #define CFLAG_COMPLETED         0x000010 /* completion routine called */
 313 #define CFLAG_PREPARED          0x000020 /* pkt has been init'ed */
 314 #define CFLAG_IN_TRANSPORT      0x000040 /* in use by host adapter driver */
 315 #define CFLAG_RESTORE_PTRS      0x000080 /* implicit restore ptr on reconnect */
 316 #define CFLAG_ARQ_IN_PROGRESS   0x000100 /* auto request sense in progress */
 317 #define CFLAG_TRANFLAG          0x0001ff /* covers transport part of flags */
 318 #define CFLAG_TM_CMD            0x000200 /* cmd is a task management command */
 319 #define CFLAG_CMDARQ            0x000400 /* cmd is a 'rqsense' command */
 320 #define CFLAG_DMAVALID          0x000800 /* dma mapping valid */
 321 #define CFLAG_DMASEND           0x001000 /* data is going 'out' */
 322 #define CFLAG_CMDIOPB           0x002000 /* this is an 'iopb' packet */
 323 #define CFLAG_CDBEXTERN         0x004000 /* cdb kmem_alloc'd */
 324 #define CFLAG_SCBEXTERN         0x008000 /* scb kmem_alloc'd */
 325 #define CFLAG_FREE              0x010000 /* packet is on free list */
 326 #define CFLAG_PRIVEXTERN        0x020000 /* target private kmem_alloc'd */
 327 #define CFLAG_DMA_PARTIAL       0x040000 /* partial xfer OK */
 328 #define CFLAG_QFULL_STATUS      0x080000 /* pkt got qfull status */
 329 #define CFLAG_TIMEOUT           0x100000 /* passthru/config command timeout */
 330 #define CFLAG_PMM_RECEIVED      0x200000 /* use cmd_pmm* for saving pointers */
 331 #define CFLAG_RETRY             0x400000 /* cmd has been retried */
 332 #define CFLAG_CMDIOC            0x800000 /* cmd is just for for ioc, no io */
 333 #define CFLAG_PASSTHRU          0x2000000 /* cmd is a passthrough command */
 334 #define CFLAG_XARQ              0x4000000 /* cmd requests for extra sense */
 335 #define CFLAG_CMDACK            0x8000000 /* cmd for event ack */
 336 #define CFLAG_TXQ               0x10000000 /* cmd queued in the tx_waitq */
 337 #define CFLAG_FW_CMD            0x20000000 /* cmd is a fw up/down command */
 338 #define CFLAG_CONFIG            0x40000000 /* cmd is for config header/page */
 339 #define CFLAG_FW_DIAG           0x80000000 /* cmd is for FW diag buffers */
 340 
 341 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_SIZE                     8
 342 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_MASK                     0xC0
 343 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_PERIPHERAL                       0x00
 344 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_FLAT_SPACE                       0x40
 345 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT             0x80
 346 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_EXTENDED_UNIT            0xC0
 347 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_2B          0x00
 348 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_4B          0x01
 349 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_6B          0x10
 350 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_8B          0x20
 351 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_SIZE                0x30
 352 
 353 #define MPTSAS_HASH_ARRAY_SIZE  16
 354 /*
 355  * hash table definition
 356  */
 357 
 358 #define MPTSAS_HASH_FIRST       0xffff
 359 #define MPTSAS_HASH_NEXT        0x0000
 360 
 361 typedef struct mptsas_dma_alloc_state
 362 {
 363         ddi_dma_handle_t        handle;
 364         caddr_t                 memp;
 365         size_t                  size;
 366         ddi_acc_handle_t        accessp;
 367         ddi_dma_cookie_t        cookie;
 368 } mptsas_dma_alloc_state_t;
 369 
 370 /*
 371  * passthrough request structure
 372  */
 373 typedef struct mptsas_pt_request {
 374         uint8_t *request;
 375         uint32_t request_size;
 376         uint32_t data_size;
 377         uint32_t dataout_size;
 378         uint32_t direction;
 379         uint8_t simple;
 380         uint16_t sgl_offset;
 381         ddi_dma_cookie_t data_cookie;
 382         ddi_dma_cookie_t dataout_cookie;
 383 } mptsas_pt_request_t;
 384 
 385 /*
 386  * config page request structure
 387  */
 388 typedef struct mptsas_config_request {
 389         uint32_t        page_address;
 390         uint8_t         action;
 391         uint8_t         page_type;
 392         uint8_t         page_number;
 393         uint8_t         page_length;
 394         uint8_t         page_version;
 395         uint8_t         ext_page_type;
 396         uint16_t        ext_page_length;
 397 } mptsas_config_request_t;
 398 
 399 typedef struct mptsas_fw_diagnostic_buffer {
 400         mptsas_dma_alloc_state_t        buffer_data;
 401         uint8_t                         extended_type;
 402         uint8_t                         buffer_type;
 403         uint8_t                         force_release;
 404         uint32_t                        product_specific[23];
 405         uint8_t                         immediate;
 406         uint8_t                         enabled;
 407         uint8_t                         valid_data;
 408         uint8_t                         owned_by_firmware;
 409         uint32_t                        unique_id;
 410 } mptsas_fw_diagnostic_buffer_t;
 411 
 412 /*
 413  * FW diag request structure
 414  */
 415 typedef struct mptsas_diag_request {
 416         mptsas_fw_diagnostic_buffer_t   *pBuffer;
 417         uint8_t                         function;
 418 } mptsas_diag_request_t;
 419 
 420 typedef struct mptsas_hash_node {
 421         void *data;
 422         struct mptsas_hash_node *next;
 423 } mptsas_hash_node_t;
 424 
 425 typedef struct mptsas_hash_table {
 426         struct mptsas_hash_node *head[MPTSAS_HASH_ARRAY_SIZE];
 427         /*
 428          * last position in traverse
 429          */
 430         struct mptsas_hash_node *cur;
 431         uint16_t line;
 432 
 433 } mptsas_hash_table_t;
 434 
 435 /*
 436  * RAID volume information
 437  */
 438 typedef struct mptsas_raidvol {
 439         ushort_t        m_israid;
 440         uint16_t        m_raidhandle;
 441         uint64_t        m_raidwwid;
 442         uint8_t         m_state;
 443         uint32_t        m_statusflags;
 444         uint32_t        m_settings;
 445         uint16_t        m_devhdl[MPTSAS_MAX_DISKS_IN_VOL];
 446         uint8_t         m_disknum[MPTSAS_MAX_DISKS_IN_VOL];
 447         ushort_t        m_diskstatus[MPTSAS_MAX_DISKS_IN_VOL];
 448         uint64_t        m_raidsize;
 449         int             m_raidlevel;
 450         int             m_ndisks;
 451         mptsas_target_t *m_raidtgt;
 452 } mptsas_raidvol_t;
 453 
 454 /*
 455  * RAID configurations
 456  */
 457 typedef struct mptsas_raidconfig {
 458                 mptsas_raidvol_t        m_raidvol[MPTSAS_MAX_RAIDVOLS];
 459                 uint16_t                m_physdisk_devhdl[
 460                                             MPTSAS_MAX_DISKS_IN_CONFIG];
 461                 uint8_t                 m_native;
 462 } m_raidconfig_t;
 463 
 464 /*
 465  * Track outstanding commands.  The index into the m_slot array is the SMID
 466  * (system message ID) of the outstanding command.  SMID 0 is reserved by the
 467  * software/firmware protocol and is never used for any command we generate;
 468  * as such, the assertion m_slot[0] == NULL is universally true.  The last
 469  * entry in the array is slot number MPTSAS_TM_SLOT(mpt) and is used ONLY for
 470  * task management commands.  No normal SCSI or ATA command will ever occupy
 471  * that slot.  Finally, the relationship m_slot[X]->cmd_slot == X holds at any
 472  * time that a consistent view of the target array is obtainable.
 473  *
 474  * As such, m_n_normal is the maximum number of slots available to ordinary
 475  * commands, and the relationship:
 476  * mpt->m_active->m_n_normal == mpt->m_max_requests - 2
 477  * always holds after initialisation.
 478  */
 479 typedef struct mptsas_slots {
 480         size_t                  m_size;         /* size of struct, bytes */
 481         uint_t                  m_n_normal;     /* see above */
 482         uint_t                  m_rotor;        /* next slot idx to consider */
 483         mptsas_cmd_t            *m_slot[1];
 484 } mptsas_slots_t;
 485 
 486 /*
 487  * Structure to hold command and packets for event ack
 488  * and task management commands.
 489  */
 490 typedef struct  m_event_struct {
 491         struct mptsas_cmd               m_event_cmd;
 492         struct m_event_struct   *m_event_linkp;
 493         /*
 494          * event member record the failure event and eventcntx
 495          * event member would be used in send ack pending process
 496          */
 497         uint32_t                m_event;
 498         uint32_t                m_eventcntx;
 499         uint_t                  in_use;
 500         struct scsi_pkt         m_event_pkt;    /* must be last */
 501                                                 /* ... scsi_pkt_size() */
 502 } m_event_struct_t;
 503 #define M_EVENT_STRUCT_SIZE     (sizeof (m_event_struct_t) - \
 504                                 sizeof (struct scsi_pkt) + scsi_pkt_size())
 505 
 506 #define MAX_IOC_COMMANDS        8
 507 
 508 /*
 509  * A pool of MAX_IOC_COMMANDS is maintained for event ack commands.
 510  * A new event ack command requests mptsas_cmd and scsi_pkt structures
 511  * from this pool, and returns it back when done.
 512  */
 513 
 514 typedef struct m_replyh_arg {
 515         void *mpt;
 516         uint32_t rfm;
 517 } m_replyh_arg_t;
 518 _NOTE(DATA_READABLE_WITHOUT_LOCK(m_replyh_arg_t::mpt))
 519 _NOTE(DATA_READABLE_WITHOUT_LOCK(m_replyh_arg_t::rfm))
 520 
 521 /*
 522  * Flags for DR handler topology change
 523  */
 524 #define MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE         0x0
 525 #define MPTSAS_TOPO_FLAG_EXPANDER_ASSOCIATED            0x1
 526 #define MPTSAS_TOPO_FLAG_LUN_ASSOCIATED                 0x2
 527 #define MPTSAS_TOPO_FLAG_RAID_ASSOCIATED                0x4
 528 #define MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED        0x8
 529 #define MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE       0x10
 530 
 531 typedef struct mptsas_topo_change_list {
 532         void *mpt;
 533         uint_t  event;
 534         union {
 535                 uint8_t physport;
 536                 mptsas_phymask_t phymask;
 537         } un;
 538         uint16_t devhdl;
 539         void *object;
 540         uint8_t flags;
 541         struct mptsas_topo_change_list *next;
 542 } mptsas_topo_change_list_t;
 543 
 544 
 545 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::mpt))
 546 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::event))
 547 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::physport))
 548 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::devhdl))
 549 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::object))
 550 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::flags))
 551 
 552 /*
 553  * Status types when calling mptsas_get_target_device_info
 554  */
 555 #define DEV_INFO_SUCCESS                0x0
 556 #define DEV_INFO_FAIL_PAGE0             0x1
 557 #define DEV_INFO_WRONG_DEVICE_TYPE      0x2
 558 #define DEV_INFO_PHYS_DISK              0x3
 559 #define DEV_INFO_FAIL_ALLOC             0x4
 560 
 561 /*
 562  * mpt hotplug event defines
 563  */
 564 #define MPTSAS_DR_EVENT_RECONFIG_TARGET 0x01
 565 #define MPTSAS_DR_EVENT_OFFLINE_TARGET  0x02
 566 #define MPTSAS_TOPO_FLAG_REMOVE_HANDLE  0x04
 567 
 568 /*
 569  * SMP target hotplug events
 570  */
 571 #define MPTSAS_DR_EVENT_RECONFIG_SMP    0x10
 572 #define MPTSAS_DR_EVENT_OFFLINE_SMP     0x20
 573 #define MPTSAS_DR_EVENT_MASK            0x3F
 574 
 575 /*
 576  * mpt hotplug status definition for m_dr_flag
 577  */
 578 
 579 /*
 580  * MPTSAS_DR_INACTIVE
 581  *
 582  * The target is in a normal operating state.
 583  * No dynamic reconfiguration operation is in progress.
 584  */
 585 #define MPTSAS_DR_INACTIVE                              0x0
 586 /*
 587  * MPTSAS_DR_INTRANSITION
 588  *
 589  * The target is in a transition mode since
 590  * hotplug event happens and offline procedure has not
 591  * been finished
 592  */
 593 #define MPTSAS_DR_INTRANSITION                  0x1
 594 
 595 typedef struct mptsas_tgt_private {
 596         int t_lun;
 597         struct mptsas_target *t_private;
 598 } mptsas_tgt_private_t;
 599 
 600 /*
 601  * The following defines are used in mptsas_set_init_mode to track the current
 602  * state as we progress through reprogramming the HBA from target mode into
 603  * initiator mode.
 604  */
 605 
 606 #define IOUC_READ_PAGE0         0x00000100
 607 #define IOUC_READ_PAGE1         0x00000200
 608 #define IOUC_WRITE_PAGE1        0x00000400
 609 #define IOUC_DONE               0x00000800
 610 #define DISCOVERY_IN_PROGRESS   MPI2_SASIOUNIT0_PORTFLAGS_DISCOVERY_IN_PROGRESS
 611 #define AUTO_PORT_CONFIGURATION MPI2_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG
 612 
 613 /*
 614  * Last allocated slot is used for TM requests.  Since only m_max_requests
 615  * frames are allocated, the last SMID will be m_max_requests - 1.
 616  */
 617 #define MPTSAS_SLOTS_SIZE(mpt) \
 618         (sizeof (struct mptsas_slots) + (sizeof (struct mptsas_cmd *) * \
 619                 mpt->m_max_requests))
 620 #define MPTSAS_TM_SLOT(mpt)     (mpt->m_max_requests - 1)
 621 
 622 /*
 623  * Macro for phy_flags
 624  */
 625 
 626 typedef struct smhba_info {
 627         kmutex_t        phy_mutex;
 628         uint8_t         phy_id;
 629         uint64_t        sas_addr;
 630         char            path[8];
 631         uint16_t        owner_devhdl;
 632         uint16_t        attached_devhdl;
 633         uint8_t         attached_phy_identify;
 634         uint32_t        attached_phy_info;
 635         uint8_t         programmed_link_rate;
 636         uint8_t         hw_link_rate;
 637         uint8_t         change_count;
 638         uint32_t        phy_info;
 639         uint8_t         negotiated_link_rate;
 640         uint8_t         port_num;
 641         kstat_t         *phy_stats;
 642         uint32_t        invalid_dword_count;
 643         uint32_t        running_disparity_error_count;
 644         uint32_t        loss_of_dword_sync_count;
 645         uint32_t        phy_reset_problem_count;
 646         void            *mpt;
 647 } smhba_info_t;
 648 
 649 typedef struct mptsas_phy_info {
 650         uint8_t                 port_num;
 651         uint8_t                 port_flags;
 652         uint16_t                ctrl_devhdl;
 653         uint32_t                phy_device_type;
 654         uint16_t                attached_devhdl;
 655         mptsas_phymask_t        phy_mask;
 656         smhba_info_t            smhba_info;
 657 } mptsas_phy_info_t;
 658 
 659 
 660 typedef struct mptsas_doneq_thread_arg {
 661         void            *mpt;
 662         uint64_t        t;
 663 } mptsas_doneq_thread_arg_t;
 664 
 665 #define MPTSAS_DONEQ_THREAD_ACTIVE      0x1
 666 typedef struct mptsas_doneq_thread_list {
 667         mptsas_cmd_t            *doneq;
 668         mptsas_cmd_t            **donetail;
 669         kthread_t               *threadp;
 670         kcondvar_t              cv;
 671         ushort_t                reserv1;
 672         uint32_t                reserv2;
 673         kmutex_t                mutex;
 674         uint32_t                flag;
 675         uint32_t                len;
 676         mptsas_doneq_thread_arg_t       arg;
 677 } mptsas_doneq_thread_list_t;
 678 
 679 typedef struct mptsas {
 680         int             m_instance;
 681 
 682         struct mptsas *m_next;
 683 
 684         scsi_hba_tran_t         *m_tran;
 685         smp_hba_tran_t          *m_smptran;
 686         kmutex_t                m_mutex;
 687         kmutex_t                m_passthru_mutex;
 688         kcondvar_t              m_cv;
 689         kcondvar_t              m_passthru_cv;
 690         kcondvar_t              m_fw_cv;
 691         kcondvar_t              m_config_cv;
 692         kcondvar_t              m_fw_diag_cv;
 693         dev_info_t              *m_dip;
 694 
 695         /*
 696          * soft state flags
 697          */
 698         uint_t          m_softstate;
 699 
 700         refhash_t       *m_targets;
 701         refhash_t       *m_smp_targets;
 702 
 703         m_raidconfig_t  m_raidconfig[MPTSAS_MAX_RAIDCONFIGS];
 704         uint8_t         m_num_raid_configs;
 705 
 706         struct mptsas_slots *m_active;  /* outstanding cmds */
 707 
 708         mptsas_cmd_t    *m_waitq;       /* cmd queue for active request */
 709         mptsas_cmd_t    **m_waitqtail;  /* wait queue tail ptr */
 710 
 711         kmutex_t        m_tx_waitq_mutex;
 712         mptsas_cmd_t    *m_tx_waitq;    /* TX cmd queue for active request */
 713         mptsas_cmd_t    **m_tx_waitqtail;       /* tx_wait queue tail ptr */
 714         int             m_tx_draining;  /* TX queue draining flag */
 715 
 716         mptsas_cmd_t    *m_doneq;       /* queue of completed commands */
 717         mptsas_cmd_t    **m_donetail;   /* queue tail ptr */
 718 
 719         /*
 720          * variables for helper threads (fan-out interrupts)
 721          */
 722         mptsas_doneq_thread_list_t      *m_doneq_thread_id;
 723         uint32_t                m_doneq_thread_n;
 724         uint32_t                m_doneq_thread_threshold;
 725         uint32_t                m_doneq_length_threshold;
 726         uint32_t                m_doneq_len;
 727         kcondvar_t              m_doneq_thread_cv;
 728         kmutex_t                m_doneq_mutex;
 729 
 730         int             m_ncmds;        /* number of outstanding commands */
 731         m_event_struct_t *m_ioc_event_cmdq;     /* cmd queue for ioc event */
 732         m_event_struct_t **m_ioc_event_cmdtail; /* ioc cmd queue tail */
 733 
 734         ddi_acc_handle_t m_datap;       /* operating regs data access handle */
 735 
 736         struct _MPI2_SYSTEM_INTERFACE_REGS      *m_reg;
 737 
 738         ushort_t        m_devid;        /* device id of chip. */
 739         uchar_t         m_revid;        /* revision of chip. */
 740         uint16_t        m_svid;         /* subsystem Vendor ID of chip */
 741         uint16_t        m_ssid;         /* subsystem Device ID of chip */
 742 
 743         uchar_t         m_sync_offset;  /* default offset for this chip. */
 744 
 745         timeout_id_t    m_quiesce_timeid;
 746 
 747         ddi_dma_handle_t m_dma_req_frame_hdl;
 748         ddi_acc_handle_t m_acc_req_frame_hdl;
 749         ddi_dma_handle_t m_dma_req_sense_hdl;
 750         ddi_acc_handle_t m_acc_req_sense_hdl;
 751         ddi_dma_handle_t m_dma_reply_frame_hdl;
 752         ddi_acc_handle_t m_acc_reply_frame_hdl;
 753         ddi_dma_handle_t m_dma_free_queue_hdl;
 754         ddi_acc_handle_t m_acc_free_queue_hdl;
 755         ddi_dma_handle_t m_dma_post_queue_hdl;
 756         ddi_acc_handle_t m_acc_post_queue_hdl;
 757 
 758         /*
 759          * list of reset notification requests
 760          */
 761         struct scsi_reset_notify_entry  *m_reset_notify_listf;
 762 
 763         /*
 764          * qfull handling
 765          */
 766         timeout_id_t    m_restart_cmd_timeid;
 767 
 768         /*
 769          * scsi reset delay per bus
 770          */
 771         uint_t          m_scsi_reset_delay;
 772 
 773         int             m_pm_idle_delay;
 774 
 775         uchar_t         m_polled_intr;  /* intr was polled. */
 776         uchar_t         m_suspended;    /* true if driver is suspended */
 777 
 778         struct kmem_cache *m_kmem_cache;
 779         struct kmem_cache *m_cache_frames;
 780 
 781         /*
 782          * hba options.
 783          */
 784         uint_t          m_options;
 785 
 786         int             m_in_callback;
 787 
 788         int             m_power_level;  /* current power level */
 789 
 790         int             m_busy;         /* power management busy state */
 791 
 792         off_t           m_pmcsr_offset; /* PMCSR offset */
 793 
 794         ddi_acc_handle_t m_config_handle;
 795 
 796         ddi_dma_attr_t          m_io_dma_attr;  /* Used for data I/O */
 797         ddi_dma_attr_t          m_msg_dma_attr; /* Used for message frames */
 798         ddi_device_acc_attr_t   m_dev_acc_attr;
 799         ddi_device_acc_attr_t   m_reg_acc_attr;
 800 
 801         /*
 802          * request/reply variables
 803          */
 804         caddr_t         m_req_frame;
 805         uint64_t        m_req_frame_dma_addr;
 806         caddr_t         m_req_sense;
 807         caddr_t         m_extreq_sense;
 808         uint64_t        m_req_sense_dma_addr;
 809         caddr_t         m_reply_frame;
 810         uint64_t        m_reply_frame_dma_addr;
 811         caddr_t         m_free_queue;
 812         uint64_t        m_free_queue_dma_addr;
 813         caddr_t         m_post_queue;
 814         uint64_t        m_post_queue_dma_addr;
 815         struct map      *m_erqsense_map;
 816 
 817         m_replyh_arg_t *m_replyh_args;
 818 
 819         uint16_t        m_max_requests;
 820         uint16_t        m_req_frame_size;
 821         uint16_t        m_req_sense_size;
 822 
 823         /*
 824          * Max frames per request reprted in IOC Facts
 825          */
 826         uint8_t         m_max_chain_depth;
 827         /*
 828          * Max frames per request which is used in reality. It's adjusted
 829          * according DMA SG length attribute, and shall not exceed the
 830          * m_max_chain_depth.
 831          */
 832         uint8_t         m_max_request_frames;
 833 
 834         uint16_t        m_free_queue_depth;
 835         uint16_t        m_post_queue_depth;
 836         uint16_t        m_max_replies;
 837         uint32_t        m_free_index;
 838         uint32_t        m_post_index;
 839         uint8_t         m_reply_frame_size;
 840         uint32_t        m_ioc_capabilities;
 841 
 842         /*
 843          * indicates if the firmware was upload by the driver
 844          * at boot time
 845          */
 846         ushort_t        m_fwupload;
 847 
 848         uint16_t        m_productid;
 849 
 850         /*
 851          * per instance data structures for dma memory resources for
 852          * MPI handshake protocol. only one handshake cmd can run at a time.
 853          */
 854         ddi_dma_handle_t        m_hshk_dma_hdl;
 855         ddi_acc_handle_t        m_hshk_acc_hdl;
 856         caddr_t                 m_hshk_memp;
 857         size_t                  m_hshk_dma_size;
 858 
 859         /* Firmware version on the card at boot time */
 860         uint32_t                m_fwversion;
 861 
 862         /* MSI specific fields */
 863         ddi_intr_handle_t       *m_htable;      /* For array of interrupts */
 864         int                     m_intr_type;    /* What type of interrupt */
 865         int                     m_intr_cnt;     /* # of intrs count returned */
 866         size_t                  m_intr_size;    /* Size of intr array */
 867         uint_t                  m_intr_pri;     /* Interrupt priority   */
 868         int                     m_intr_cap;     /* Interrupt capabilities */
 869         ddi_taskq_t             *m_event_taskq;
 870 
 871         /* SAS specific information */
 872 
 873         union {
 874                 uint64_t        m_base_wwid;    /* Base WWID */
 875                 struct {
 876 #ifdef _BIG_ENDIAN
 877                         uint32_t        m_base_wwid_hi;
 878                         uint32_t        m_base_wwid_lo;
 879 #else
 880                         uint32_t        m_base_wwid_lo;
 881                         uint32_t        m_base_wwid_hi;
 882 #endif
 883                 } sasaddr;
 884         } un;
 885 
 886         uint8_t                 m_num_phys;             /* # of PHYs */
 887         mptsas_phy_info_t       m_phy_info[MPTSAS_MAX_PHYS];
 888         uint8_t                 m_port_chng;    /* initiator port changes */
 889         MPI2_CONFIG_PAGE_MAN_0   m_MANU_page0;   /* Manufactor page 0 info */
 890         MPI2_CONFIG_PAGE_MAN_1   m_MANU_page1;   /* Manufactor page 1 info */
 891 
 892         /* FMA Capabilities */
 893         int                     m_fm_capabilities;
 894         ddi_taskq_t             *m_dr_taskq;
 895         int                     m_mpxio_enable;
 896         uint8_t                 m_done_traverse_dev;
 897         uint8_t                 m_done_traverse_smp;
 898         int                     m_diag_action_in_progress;
 899         uint16_t                m_dev_handle;
 900         uint16_t                m_smp_devhdl;
 901 
 902         /* In case of reset */
 903         ddi_taskq_t             *m_reset_taskq;
 904 
 905         /*
 906          * Event recording
 907          */
 908         uint8_t                 m_event_index;
 909         uint32_t                m_event_number;
 910         uint32_t                m_event_mask[4];
 911         mptsas_event_entry_t    m_events[MPTSAS_EVENT_QUEUE_SIZE];
 912 
 913         /*
 914          * FW diag Buffer List
 915          */
 916         mptsas_fw_diagnostic_buffer_t
 917                 m_fw_diag_buffer_list[MPI2_DIAG_BUF_TYPE_COUNT];
 918 
 919         /* GEN3 support */
 920         uint8_t                 m_MPI25;
 921 
 922         /*
 923          * Event Replay flag (MUR support)
 924          */
 925         uint8_t                 m_event_replay;
 926 
 927         /*
 928          * IR Capable flag
 929          */
 930         uint8_t                 m_ir_capable;
 931 
 932         /*
 933          * Is HBA processing a diag reset?
 934          */
 935         uint8_t                 m_in_reset;
 936 
 937         /*
 938          * per instance cmd data structures for task management cmds
 939          */
 940         m_event_struct_t        m_event_task_mgmt;      /* must be last */
 941                                                         /* ... scsi_pkt_size */
 942 } mptsas_t;
 943 #define MPTSAS_SIZE     (sizeof (struct mptsas) - \
 944                         sizeof (struct scsi_pkt) + scsi_pkt_size())
 945 /*
 946  * Only one of below two conditions is satisfied, we
 947  * think the target is associated to the iport and
 948  * allow call into mptsas_probe_lun().
 949  * 1. physicalsport == physport
 950  * 2. (phymask & (1 << physport)) == 0
 951  * The condition #2 is because LSI uses lowest PHY
 952  * number as the value of physical port when auto port
 953  * configuration.
 954  */
 955 #define IS_SAME_PORT(physicalport, physport, phymask, dynamicport) \
 956         ((physicalport == physport) || (dynamicport && (phymask & \
 957         (1 << physport))))
 958 
 959 _NOTE(MUTEX_PROTECTS_DATA(mptsas::m_mutex, mptsas))
 960 _NOTE(SCHEME_PROTECTS_DATA("safe sharing", mptsas::m_next))
 961 _NOTE(SCHEME_PROTECTS_DATA("stable data", mptsas::m_dip mptsas::m_tran))
 962 _NOTE(SCHEME_PROTECTS_DATA("stable data", mptsas::m_kmem_cache))
 963 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_io_dma_attr.dma_attr_sgllen))
 964 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_devid))
 965 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_productid))
 966 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_mpxio_enable))
 967 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_instance))
 968 
 969 /*
 970  * These should eventually migrate into the mpt header files
 971  * that may become the /kernel/misc/mpt module...
 972  */
 973 #define mptsas_init_std_hdr(hdl, mp, DevHandle, Lun, ChainOffset, Function) \
 974         mptsas_put_msg_DevHandle(hdl, mp, DevHandle); \
 975         mptsas_put_msg_ChainOffset(hdl, mp, ChainOffset); \
 976         mptsas_put_msg_Function(hdl, mp, Function); \
 977         mptsas_put_msg_Lun(hdl, mp, Lun)
 978 
 979 #define mptsas_put_msg_DevHandle(hdl, mp, val) \
 980         ddi_put16(hdl, &(mp)->DevHandle, (val))
 981 #define mptsas_put_msg_ChainOffset(hdl, mp, val) \
 982         ddi_put8(hdl, &(mp)->ChainOffset, (val))
 983 #define mptsas_put_msg_Function(hdl, mp, val) \
 984         ddi_put8(hdl, &(mp)->Function, (val))
 985 #define mptsas_put_msg_Lun(hdl, mp, val) \
 986         ddi_put8(hdl, &(mp)->LUN[1], (val))
 987 
 988 #define mptsas_get_msg_Function(hdl, mp) \
 989         ddi_get8(hdl, &(mp)->Function)
 990 
 991 #define mptsas_get_msg_MsgFlags(hdl, mp) \
 992         ddi_get8(hdl, &(mp)->MsgFlags)
 993 
 994 #define MPTSAS_ENABLE_DRWE(hdl) \
 995         ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \
 996                 MPI2_WRSEQ_FLUSH_KEY_VALUE); \
 997         ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \
 998                 MPI2_WRSEQ_1ST_KEY_VALUE); \
 999         ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \
1000                 MPI2_WRSEQ_2ND_KEY_VALUE); \
1001         ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \
1002                 MPI2_WRSEQ_3RD_KEY_VALUE); \
1003         ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \
1004                 MPI2_WRSEQ_4TH_KEY_VALUE); \
1005         ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \
1006                 MPI2_WRSEQ_5TH_KEY_VALUE); \
1007         ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \
1008                 MPI2_WRSEQ_6TH_KEY_VALUE);
1009 
1010 /*
1011  * m_options flags
1012  */
1013 #define MPTSAS_OPT_PM           0x01    /* Power Management */
1014 
1015 /*
1016  * m_softstate flags
1017  */
1018 #define MPTSAS_SS_DRAINING              0x02
1019 #define MPTSAS_SS_QUIESCED              0x04
1020 #define MPTSAS_SS_MSG_UNIT_RESET        0x08
1021 #define MPTSAS_DID_MSG_UNIT_RESET       0x10
1022 
1023 /*
1024  * regspec defines.
1025  */
1026 #define CONFIG_SPACE    0       /* regset[0] - configuration space */
1027 #define IO_SPACE        1       /* regset[1] - used for i/o mapped device */
1028 #define MEM_SPACE       2       /* regset[2] - used for memory mapped device */
1029 #define BASE_REG2       3       /* regset[3] - used for 875 scripts ram */
1030 
1031 /*
1032  * Handy constants
1033  */
1034 #define FALSE           0
1035 #define TRUE            1
1036 #define UNDEFINED       -1
1037 #define FAILED          -2
1038 
1039 /*
1040  * power management.
1041  */
1042 #define MPTSAS_POWER_ON(mpt) { \
1043         pci_config_put16(mpt->m_config_handle, mpt->m_pmcsr_offset, \
1044             PCI_PMCSR_D0); \
1045         delay(drv_usectohz(10000)); \
1046         (void) pci_restore_config_regs(mpt->m_dip); \
1047         mptsas_setup_cmd_reg(mpt); \
1048 }
1049 
1050 #define MPTSAS_POWER_OFF(mpt) { \
1051         (void) pci_save_config_regs(mpt->m_dip); \
1052         pci_config_put16(mpt->m_config_handle, mpt->m_pmcsr_offset, \
1053             PCI_PMCSR_D3HOT); \
1054         mpt->m_power_level = PM_LEVEL_D3; \
1055 }
1056 
1057 /*
1058  * inq_dtype:
1059  * Bits 5 through 7 are the Peripheral Device Qualifier
1060  * 001b: device not connected to the LUN
1061  * Bits 0 through 4 are the Peripheral Device Type
1062  * 1fh: Unknown or no device type
1063  *
1064  * Although the inquiry may return success, the following value
1065  * means no valid LUN connected.
1066  */
1067 #define MPTSAS_VALID_LUN(sd_inq) \
1068         (((sd_inq->inq_dtype & 0xe0) != 0x20) && \
1069         ((sd_inq->inq_dtype & 0x1f) != 0x1f))
1070 
1071 /*
1072  * Default is to have 10 retries on receiving QFULL status and
1073  * each retry to be after 100 ms.
1074  */
1075 #define QFULL_RETRIES           10
1076 #define QFULL_RETRY_INTERVAL    100
1077 
1078 /*
1079  * Handy macros
1080  */
1081 #define Tgt(sp) ((sp)->cmd_pkt->pkt_address.a_target)
1082 #define Lun(sp) ((sp)->cmd_pkt->pkt_address.a_lun)
1083 
1084 #define IS_HEX_DIGIT(n) (((n) >= '0' && (n) <= '9') || \
1085         ((n) >= 'a' && (n) <= 'f') || ((n) >= 'A' && (n) <= 'F'))
1086 
1087 /*
1088  * poll time for mptsas_pollret() and mptsas_wait_intr()
1089  */
1090 #define MPTSAS_POLL_TIME        30000   /* 30 seconds */
1091 
1092 /*
1093  * default time for mptsas_do_passthru
1094  */
1095 #define MPTSAS_PASS_THRU_TIME_DEFAULT   60      /* 60 seconds */
1096 
1097 /*
1098  * macro to return the effective address of a given per-target field
1099  */
1100 #define EFF_ADDR(start, offset)         ((start) + (offset))
1101 
1102 #define SDEV2ADDR(devp)         (&((devp)->sd_address))
1103 #define SDEV2TRAN(devp)         ((devp)->sd_address.a_hba_tran)
1104 #define PKT2TRAN(pkt)           ((pkt)->pkt_address.a_hba_tran)
1105 #define ADDR2TRAN(ap)           ((ap)->a_hba_tran)
1106 #define DIP2TRAN(dip)           (ddi_get_driver_private(dip))
1107 
1108 
1109 #define TRAN2MPT(hba)           ((mptsas_t *)(hba)->tran_hba_private)
1110 #define DIP2MPT(dip)            (TRAN2MPT((scsi_hba_tran_t *)DIP2TRAN(dip)))
1111 #define SDEV2MPT(sd)            (TRAN2MPT(SDEV2TRAN(sd)))
1112 #define PKT2MPT(pkt)            (TRAN2MPT(PKT2TRAN(pkt)))
1113 
1114 #define ADDR2MPT(ap)            (TRAN2MPT(ADDR2TRAN(ap)))
1115 
1116 #define POLL_TIMEOUT            (2 * SCSI_POLL_TIMEOUT * 1000000)
1117 #define SHORT_POLL_TIMEOUT      (1000000)       /* in usec, about 1 secs */
1118 #define MPTSAS_QUIESCE_TIMEOUT  1               /* 1 sec */
1119 #define MPTSAS_PM_IDLE_TIMEOUT  60              /* 60 seconds */
1120 
1121 #define MPTSAS_GET_ISTAT(mpt)  (ddi_get32((mpt)->m_datap, \
1122                         &(mpt)->m_reg->HostInterruptStatus))
1123 
1124 #define MPTSAS_SET_SIGP(P) \
1125                 ClrSetBits(mpt->m_devaddr + NREG_ISTAT, 0, NB_ISTAT_SIGP)
1126 
1127 #define MPTSAS_RESET_SIGP(P) (void) ddi_get8(mpt->m_datap, \
1128                         (uint8_t *)(mpt->m_devaddr + NREG_CTEST2))
1129 
1130 #define MPTSAS_GET_INTCODE(P) (ddi_get32(mpt->m_datap, \
1131                         (uint32_t *)(mpt->m_devaddr + NREG_DSPS)))
1132 
1133 
1134 #define MPTSAS_START_CMD(mpt, req_desc) \
1135         ddi_put32(mpt->m_datap, &mpt->m_reg->RequestDescriptorPostLow,     \
1136             req_desc & 0xffffffffu);                                        \
1137         ddi_put32(mpt->m_datap, &mpt->m_reg->RequestDescriptorPostHigh,    \
1138             (req_desc >> 32) & 0xffffffffu);
1139 
1140 #define INTPENDING(mpt) \
1141         (MPTSAS_GET_ISTAT(mpt) & MPI2_HIS_REPLY_DESCRIPTOR_INTERRUPT)
1142 
1143 /*
1144  * Mask all interrupts to disable
1145  */
1146 #define MPTSAS_DISABLE_INTR(mpt)        \
1147         ddi_put32((mpt)->m_datap, &(mpt)->m_reg->HostInterruptMask, \
1148             (MPI2_HIM_RIM | MPI2_HIM_DIM | MPI2_HIM_RESET_IRQ_MASK))
1149 
1150 /*
1151  * Mask Doorbell and Reset interrupts to enable reply desc int.
1152  */
1153 #define MPTSAS_ENABLE_INTR(mpt) \
1154         ddi_put32(mpt->m_datap, &mpt->m_reg->HostInterruptMask, \
1155         (MPI2_HIM_DIM | MPI2_HIM_RESET_IRQ_MASK))
1156 
1157 #define MPTSAS_GET_NEXT_REPLY(mpt, index)  \
1158         &((uint64_t *)(void *)mpt->m_post_queue)[index]
1159 
1160 #define MPTSAS_GET_NEXT_FRAME(mpt, SMID) \
1161         (mpt->m_req_frame + (mpt->m_req_frame_size * SMID))
1162 
1163 #define ClrSetBits32(hdl, reg, clr, set) \
1164         ddi_put32(hdl, (reg), \
1165             ((ddi_get32(mpt->m_datap, (reg)) & ~(clr)) | (set)))
1166 
1167 #define ClrSetBits(reg, clr, set) \
1168         ddi_put8(mpt->m_datap, (uint8_t *)(reg), \
1169                 ((ddi_get8(mpt->m_datap, (uint8_t *)(reg)) & ~(clr)) | (set)))
1170 
1171 #define MPTSAS_WAITQ_RM(mpt, cmdp)      \
1172         if ((cmdp = mpt->m_waitq) != NULL) { \
1173                 /* If the queue is now empty fix the tail pointer */    \
1174                 if ((mpt->m_waitq = cmdp->cmd_linkp) == NULL) \
1175                         mpt->m_waitqtail = &mpt->m_waitq; \
1176                 cmdp->cmd_linkp = NULL; \
1177                 cmdp->cmd_queued = FALSE; \
1178         }
1179 
1180 #define MPTSAS_TX_WAITQ_RM(mpt, cmdp)   \
1181         if ((cmdp = mpt->m_tx_waitq) != NULL) { \
1182                 /* If the queue is now empty fix the tail pointer */    \
1183                 if ((mpt->m_tx_waitq = cmdp->cmd_linkp) == NULL) \
1184                         mpt->m_tx_waitqtail = &mpt->m_tx_waitq; \
1185                 cmdp->cmd_linkp = NULL; \
1186                 cmdp->cmd_queued = FALSE; \
1187         }
1188 
1189 /*
1190  * defaults for the global properties
1191  */
1192 #define DEFAULT_SCSI_OPTIONS    SCSI_OPTIONS_DR
1193 #define DEFAULT_TAG_AGE_LIMIT   2
1194 #define DEFAULT_WD_TICK         1
1195 
1196 /*
1197  * invalid hostid.
1198  */
1199 #define MPTSAS_INVALID_HOSTID  -1
1200 
1201 /*
1202  * Get/Set hostid from SCSI port configuration page
1203  */
1204 #define MPTSAS_GET_HOST_ID(configuration) (configuration & 0xFF)
1205 #define MPTSAS_SET_HOST_ID(hostid) (hostid | ((1 << hostid) << 16))
1206 
1207 /*
1208  * Config space.
1209  */
1210 #define MPTSAS_LATENCY_TIMER    0x40
1211 
1212 /*
1213  * Offset to firmware version
1214  */
1215 #define MPTSAS_FW_VERSION_OFFSET        9
1216 
1217 /*
1218  * Offset and masks to get at the ProductId field
1219  */
1220 #define MPTSAS_FW_PRODUCTID_OFFSET      8
1221 #define MPTSAS_FW_PRODUCTID_MASK        0xFFFF0000
1222 #define MPTSAS_FW_PRODUCTID_SHIFT       16
1223 
1224 /*
1225  * Subsystem ID for HBAs.
1226  */
1227 #define MPTSAS_HBA_SUBSYSTEM_ID    0x10C0
1228 #define MPTSAS_RHEA_SUBSYSTEM_ID        0x10B0
1229 
1230 /*
1231  * reset delay tick
1232  */
1233 #define MPTSAS_WATCH_RESET_DELAY_TICK 50        /* specified in milli seconds */
1234 
1235 /*
1236  * Ioc reset return values
1237  */
1238 #define MPTSAS_RESET_FAIL       -1
1239 #define MPTSAS_NO_RESET         0
1240 #define MPTSAS_SUCCESS_HARDRESET        1
1241 #define MPTSAS_SUCCESS_MUR      2
1242 
1243 /*
1244  * throttle support.
1245  */
1246 #define MAX_THROTTLE    32
1247 #define HOLD_THROTTLE   0
1248 #define DRAIN_THROTTLE  -1
1249 #define QFULL_THROTTLE  -2
1250 
1251 /*
1252  * Passthrough/config request flags
1253  */
1254 #define MPTSAS_DATA_ALLOCATED           0x0001
1255 #define MPTSAS_DATAOUT_ALLOCATED        0x0002
1256 #define MPTSAS_REQUEST_POOL_CMD         0x0004
1257 #define MPTSAS_ADDRESS_REPLY            0x0008
1258 #define MPTSAS_CMD_TIMEOUT              0x0010
1259 
1260 /*
1261  * response code tlr flag
1262  */
1263 #define MPTSAS_SCSI_RESPONSE_CODE_TLR_OFF       0x02
1264 
1265 /*
1266  * System Events
1267  */
1268 #ifndef DDI_VENDOR_LSI
1269 #define DDI_VENDOR_LSI  "LSI"
1270 #endif  /* DDI_VENDOR_LSI */
1271 
1272 /*
1273  * Shared functions
1274  */
1275 int mptsas_save_cmd(struct mptsas *mpt, struct mptsas_cmd *cmd);
1276 void mptsas_remove_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd);
1277 void mptsas_waitq_add(mptsas_t *mpt, mptsas_cmd_t *cmd);
1278 void mptsas_log(struct mptsas *mpt, int level, char *fmt, ...);
1279 int mptsas_poll(mptsas_t *mpt, mptsas_cmd_t *poll_cmd, int polltime);
1280 int mptsas_do_dma(mptsas_t *mpt, uint32_t size, int var, int (*callback)());
1281 int mptsas_update_flash(mptsas_t *mpt, caddr_t ptrbuffer, uint32_t size,
1282         uint8_t type, int mode);
1283 int mptsas_check_flash(mptsas_t *mpt, caddr_t origfile, uint32_t size,
1284         uint8_t type, int mode);
1285 int mptsas_download_firmware();
1286 int mptsas_can_download_firmware();
1287 int mptsas_dma_alloc(mptsas_t *mpt, mptsas_dma_alloc_state_t *dma_statep);
1288 void mptsas_dma_free(mptsas_dma_alloc_state_t *dma_statep);
1289 mptsas_phymask_t mptsas_physport_to_phymask(mptsas_t *mpt, uint8_t physport);
1290 void mptsas_fma_check(mptsas_t *mpt, mptsas_cmd_t *cmd);
1291 int mptsas_check_acc_handle(ddi_acc_handle_t handle);
1292 int mptsas_check_dma_handle(ddi_dma_handle_t handle);
1293 void mptsas_fm_ereport(mptsas_t *mpt, char *detail);
1294 int mptsas_dma_addr_create(mptsas_t *mpt, ddi_dma_attr_t dma_attr,
1295     ddi_dma_handle_t *dma_hdp, ddi_acc_handle_t *acc_hdp, caddr_t *dma_memp,
1296     uint32_t alloc_size, ddi_dma_cookie_t *cookiep);
1297 void mptsas_dma_addr_destroy(ddi_dma_handle_t *, ddi_acc_handle_t *);
1298 
1299 /*
1300  * impl functions
1301  */
1302 int mptsas_ioc_wait_for_response(mptsas_t *mpt);
1303 int mptsas_ioc_wait_for_doorbell(mptsas_t *mpt);
1304 int mptsas_ioc_reset(mptsas_t *mpt, int);
1305 int mptsas_send_handshake_msg(mptsas_t *mpt, caddr_t memp, int numbytes,
1306     ddi_acc_handle_t accessp);
1307 int mptsas_get_handshake_msg(mptsas_t *mpt, caddr_t memp, int numbytes,
1308     ddi_acc_handle_t accessp);
1309 int mptsas_send_config_request_msg(mptsas_t *mpt, uint8_t action,
1310     uint8_t pagetype, uint32_t pageaddress, uint8_t pagenumber,
1311     uint8_t pageversion, uint8_t pagelength, uint32_t SGEflagslength,
1312     uint64_t SGEaddress);
1313 int mptsas_send_extended_config_request_msg(mptsas_t *mpt, uint8_t action,
1314     uint8_t extpagetype, uint32_t pageaddress, uint8_t pagenumber,
1315     uint8_t pageversion, uint16_t extpagelength,
1316     uint32_t SGEflagslength, uint64_t SGEaddress);
1317 
1318 int mptsas_request_from_pool(mptsas_t *mpt, mptsas_cmd_t **cmd,
1319     struct scsi_pkt **pkt);
1320 void mptsas_return_to_pool(mptsas_t *mpt, mptsas_cmd_t *cmd);
1321 void mptsas_destroy_ioc_event_cmd(mptsas_t *mpt);
1322 void mptsas_start_config_page_access(mptsas_t *mpt, mptsas_cmd_t *cmd);
1323 int mptsas_access_config_page(mptsas_t *mpt, uint8_t action, uint8_t page_type,
1324     uint8_t page_number, uint32_t page_address, int (*callback) (mptsas_t *,
1325     caddr_t, ddi_acc_handle_t, uint16_t, uint32_t, va_list), ...);
1326 
1327 int mptsas_ioc_task_management(mptsas_t *mpt, int task_type,
1328     uint16_t dev_handle, int lun, uint8_t *reply, uint32_t reply_size,
1329     int mode);
1330 int mptsas_send_event_ack(mptsas_t *mpt, uint32_t event, uint32_t eventcntx);
1331 void mptsas_send_pending_event_ack(mptsas_t *mpt);
1332 void mptsas_set_throttle(struct mptsas *mpt, mptsas_target_t *ptgt, int what);
1333 void mptsas_handle_restart_ioc(void *mpt);
1334 int mptsas_restart_ioc(mptsas_t *mpt);
1335 void mptsas_update_driver_data(struct mptsas *mpt);
1336 uint64_t mptsas_get_sata_guid(mptsas_t *mpt, mptsas_target_t *ptgt, int lun);
1337 
1338 /*
1339  * init functions
1340  */
1341 int mptsas_ioc_get_facts(mptsas_t *mpt);
1342 int mptsas_ioc_get_port_facts(mptsas_t *mpt, int port);
1343 int mptsas_ioc_enable_port(mptsas_t *mpt);
1344 int mptsas_ioc_enable_event_notification(mptsas_t *mpt);
1345 int mptsas_ioc_init(mptsas_t *mpt);
1346 
1347 /*
1348  * configuration pages operation
1349  */
1350 int mptsas_get_sas_device_page0(mptsas_t *mpt, uint32_t page_address,
1351     uint16_t *dev_handle, uint64_t *sas_wwn, uint32_t *dev_info,
1352     uint8_t *physport, uint8_t *phynum, uint16_t *pdevhandle,
1353     uint16_t *slot_num, uint16_t *enclosure, uint16_t *io_flags);
1354 int mptsas_get_sas_io_unit_page(mptsas_t *mpt);
1355 int mptsas_get_sas_io_unit_page_hndshk(mptsas_t *mpt);
1356 int mptsas_get_sas_expander_page0(mptsas_t *mpt, uint32_t page_address,
1357     mptsas_smp_t *info);
1358 int mptsas_set_ioc_params(mptsas_t *mpt);
1359 int mptsas_get_manufacture_page5(mptsas_t *mpt);
1360 int mptsas_get_sas_port_page0(mptsas_t *mpt, uint32_t page_address,
1361     uint64_t *sas_wwn, uint8_t *portwidth);
1362 int mptsas_get_bios_page3(mptsas_t *mpt,  uint32_t *bios_version);
1363 int
1364 mptsas_get_sas_phy_page0(mptsas_t *mpt, uint32_t page_address,
1365     smhba_info_t *info);
1366 int
1367 mptsas_get_sas_phy_page1(mptsas_t *mpt, uint32_t page_address,
1368     smhba_info_t *info);
1369 int
1370 mptsas_get_manufacture_page0(mptsas_t *mpt);
1371 void
1372 mptsas_create_phy_stats(mptsas_t *mpt, char *iport, dev_info_t *dip);
1373 void mptsas_destroy_phy_stats(mptsas_t *mpt);
1374 int mptsas_smhba_phy_init(mptsas_t *mpt);
1375 /*
1376  * RAID functions
1377  */
1378 int mptsas_get_raid_settings(mptsas_t *mpt, mptsas_raidvol_t *raidvol);
1379 int mptsas_get_raid_info(mptsas_t *mpt);
1380 int mptsas_get_physdisk_settings(mptsas_t *mpt, mptsas_raidvol_t *raidvol,
1381     uint8_t physdisknum);
1382 int mptsas_delete_volume(mptsas_t *mpt, uint16_t volid);
1383 void mptsas_raid_action_system_shutdown(mptsas_t *mpt);
1384 
1385 #define MPTSAS_IOCSTATUS(status) (status & MPI2_IOCSTATUS_MASK)
1386 /*
1387  * debugging.
1388  * MPTSAS_DBGLOG_LINECNT must be a power of 2.
1389  */
1390 #define MPTSAS_DBGLOG_LINECNT   128
1391 #define MPTSAS_DBGLOG_LINELEN   256
1392 #define MPTSAS_DBGLOG_BUFSIZE   (MPTSAS_DBGLOG_LINECNT * MPTSAS_DBGLOG_LINELEN)
1393 
1394 #if defined(MPTSAS_DEBUG)
1395 
1396 extern uint32_t mptsas_debugprt_flags;
1397 extern uint32_t mptsas_debuglog_flags;
1398 
1399 void mptsas_printf(char *fmt, ...);
1400 void mptsas_debug_log(char *fmt, ...);
1401 
1402 #define MPTSAS_DBGPR(m, args)   \
1403         if (mptsas_debugprt_flags & (m)) \
1404                 mptsas_printf args;   \
1405         if (mptsas_debuglog_flags & (m)) \
1406                 mptsas_debug_log args
1407 #else   /* ! defined(MPTSAS_DEBUG) */
1408 #define MPTSAS_DBGPR(m, args)
1409 #endif  /* defined(MPTSAS_DEBUG) */
1410 
1411 #define NDBG0(args)     MPTSAS_DBGPR(0x01, args)        /* init */
1412 #define NDBG1(args)     MPTSAS_DBGPR(0x02, args)        /* normal running */
1413 #define NDBG2(args)     MPTSAS_DBGPR(0x04, args)        /* property handling */
1414 #define NDBG3(args)     MPTSAS_DBGPR(0x08, args)        /* pkt handling */
1415 
1416 #define NDBG4(args)     MPTSAS_DBGPR(0x10, args)        /* kmem alloc/free */
1417 #define NDBG5(args)     MPTSAS_DBGPR(0x20, args)        /* polled cmds */
1418 #define NDBG6(args)     MPTSAS_DBGPR(0x40, args)        /* interrupts */
1419 #define NDBG7(args)     MPTSAS_DBGPR(0x80, args)        /* queue handling */
1420 
1421 #define NDBG8(args)     MPTSAS_DBGPR(0x0100, args)      /* arq */
1422 #define NDBG9(args)     MPTSAS_DBGPR(0x0200, args)      /* Tagged Q'ing */
1423 #define NDBG10(args)    MPTSAS_DBGPR(0x0400, args)      /* halting chip */
1424 #define NDBG11(args)    MPTSAS_DBGPR(0x0800, args)      /* power management */
1425 
1426 #define NDBG12(args)    MPTSAS_DBGPR(0x1000, args)      /* enumeration */
1427 #define NDBG13(args)    MPTSAS_DBGPR(0x2000, args)      /* configuration page */
1428 #define NDBG14(args)    MPTSAS_DBGPR(0x4000, args)      /* LED control */
1429 #define NDBG15(args)    MPTSAS_DBGPR(0x8000, args)      /* Passthrough */
1430 
1431 #define NDBG16(args)    MPTSAS_DBGPR(0x010000, args)    /* SAS Broadcasts */
1432 #define NDBG17(args)    MPTSAS_DBGPR(0x020000, args)    /* scatter/gather */
1433 #define NDBG18(args)    MPTSAS_DBGPR(0x040000, args)
1434 #define NDBG19(args)    MPTSAS_DBGPR(0x080000, args)    /* handshaking */
1435 
1436 #define NDBG20(args)    MPTSAS_DBGPR(0x100000, args)    /* events */
1437 #define NDBG21(args)    MPTSAS_DBGPR(0x200000, args)    /* dma */
1438 #define NDBG22(args)    MPTSAS_DBGPR(0x400000, args)    /* reset */
1439 #define NDBG23(args)    MPTSAS_DBGPR(0x800000, args)    /* abort */
1440 
1441 #define NDBG24(args)    MPTSAS_DBGPR(0x1000000, args)   /* capabilities */
1442 #define NDBG25(args)    MPTSAS_DBGPR(0x2000000, args)   /* flushing */
1443 #define NDBG26(args)    MPTSAS_DBGPR(0x4000000, args)
1444 #define NDBG27(args)    MPTSAS_DBGPR(0x8000000, args)   /* passthrough */
1445 
1446 #define NDBG28(args)    MPTSAS_DBGPR(0x10000000, args)  /* hotplug */
1447 #define NDBG29(args)    MPTSAS_DBGPR(0x20000000, args)  /* timeouts */
1448 #define NDBG30(args)    MPTSAS_DBGPR(0x40000000, args)  /* mptsas_watch */
1449 #define NDBG31(args)    MPTSAS_DBGPR(0x80000000, args)  /* negotations */
1450 
1451 /*
1452  * auto request sense
1453  */
1454 #define RQ_MAKECOM_COMMON(pkt, flag, cmd) \
1455         (pkt)->pkt_flags = (flag), \
1456         ((union scsi_cdb *)(pkt)->pkt_cdbp)->scc_cmd = (cmd), \
1457         ((union scsi_cdb *)(pkt)->pkt_cdbp)->scc_lun = \
1458             (pkt)->pkt_address.a_lun
1459 
1460 #define RQ_MAKECOM_G0(pkt, flag, cmd, addr, cnt) \
1461         RQ_MAKECOM_COMMON((pkt), (flag), (cmd)), \
1462         FORMG0ADDR(((union scsi_cdb *)(pkt)->pkt_cdbp), (addr)), \
1463         FORMG0COUNT(((union scsi_cdb *)(pkt)->pkt_cdbp), (cnt))
1464 
1465 
1466 #ifdef  __cplusplus
1467 }
1468 #endif
1469 
1470 #endif  /* _SYS_SCSI_ADAPTERS_MPTVAR_H */