455 #define AR5416_EEP_RXGAIN_13DB_BACKOFF 1
456 #define AR5416_EEP_RXGAIN_ORIG 2
457
458 /* Tx gain type values */
459 #define AR5416_EEP_TXGAIN_ORIGINAL 0
460 #define AR5416_EEP_TXGAIN_HIGH_POWER 1
461
462 #define AR5416_EEP4K_START_LOC 64
463 #define AR5416_EEP4K_NUM_2G_CAL_PIERS 3
464 #define AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS 3
465 #define AR5416_EEP4K_NUM_2G_20_TARGET_POWERS 3
466 #define AR5416_EEP4K_NUM_2G_40_TARGET_POWERS 3
467 #define AR5416_EEP4K_NUM_CTLS 12
468 #define AR5416_EEP4K_NUM_BAND_EDGES 4
469 #define AR5416_EEP4K_NUM_PD_GAINS 2
470 #define AR5416_EEP4K_PD_GAINS_IN_MASK 4
471 #define AR5416_EEP4K_PD_GAIN_ICEPTS 5
472 #define AR5416_EEP4K_MAX_CHAINS 1
473
474 enum eeprom_param {
475 EEP_NFTHRESH_5,
476 EEP_NFTHRESH_2,
477 EEP_MAC_MSW,
478 EEP_MAC_MID,
479 EEP_MAC_LSW,
480 EEP_REG_0,
481 EEP_REG_1,
482 EEP_OP_CAP,
483 EEP_OP_MODE,
484 EEP_RF_SILENT,
485 EEP_OB_5,
486 EEP_DB_5,
487 EEP_OB_2,
488 EEP_DB_2,
489 EEP_MINOR_REV,
490 EEP_TX_MASK,
491 EEP_RX_MASK,
492 EEP_RXGAIN_TYPE,
493 EEP_TXGAIN_TYPE,
494 EEP_OL_PWRCTRL,
495 EEP_RC_CHAIN_MASK,
496 EEP_DAC_HPWR_5G,
497 EEP_FRAC_N_5G
498 };
499
500 enum ar5416_rates {
501 rate6mb, rate9mb, rate12mb, rate18mb,
502 rate24mb, rate36mb, rate48mb, rate54mb,
503 rate1l, rate2l, rate2s, rate5_5l,
504 rate5_5s, rate11l, rate11s, rateXr,
505 rateHt20_0, rateHt20_1, rateHt20_2, rateHt20_3,
506 rateHt20_4, rateHt20_5, rateHt20_6, rateHt20_7,
507 rateHt40_0, rateHt40_1, rateHt40_2, rateHt40_3,
508 rateHt40_4, rateHt40_5, rateHt40_6, rateHt40_7,
509 rateDupCck, rateDupOfdm, rateExtCck, rateExtOfdm,
510 Ar5416RateSize
511 };
512
513 enum ath9k_hal_freq_band {
514 ATH9K_HAL_FREQ_BAND_5GHZ = 0,
515 ATH9K_HAL_FREQ_BAND_2GHZ = 1
516 };
517
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455 #define AR5416_EEP_RXGAIN_13DB_BACKOFF 1
456 #define AR5416_EEP_RXGAIN_ORIG 2
457
458 /* Tx gain type values */
459 #define AR5416_EEP_TXGAIN_ORIGINAL 0
460 #define AR5416_EEP_TXGAIN_HIGH_POWER 1
461
462 #define AR5416_EEP4K_START_LOC 64
463 #define AR5416_EEP4K_NUM_2G_CAL_PIERS 3
464 #define AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS 3
465 #define AR5416_EEP4K_NUM_2G_20_TARGET_POWERS 3
466 #define AR5416_EEP4K_NUM_2G_40_TARGET_POWERS 3
467 #define AR5416_EEP4K_NUM_CTLS 12
468 #define AR5416_EEP4K_NUM_BAND_EDGES 4
469 #define AR5416_EEP4K_NUM_PD_GAINS 2
470 #define AR5416_EEP4K_PD_GAINS_IN_MASK 4
471 #define AR5416_EEP4K_PD_GAIN_ICEPTS 5
472 #define AR5416_EEP4K_MAX_CHAINS 1
473
474 enum eeprom_param {
475 EEP_NFTHRESH_5 = 0,
476 EEP_NFTHRESH_2,
477 EEP_MAC_MSW,
478 EEP_MAC_MID,
479 EEP_MAC_LSW,
480 EEP_REG_0,
481 EEP_REG_1,
482 EEP_OP_CAP,
483 EEP_OP_MODE,
484 EEP_RF_SILENT,
485 EEP_OB_5,
486 EEP_DB_5,
487 EEP_OB_2,
488 EEP_DB_2,
489 EEP_MINOR_REV,
490 EEP_TX_MASK,
491 EEP_RX_MASK,
492 EEP_RXGAIN_TYPE,
493 EEP_TXGAIN_TYPE,
494 EEP_OL_PWRCTRL,
495 EEP_RC_CHAIN_MASK,
496 EEP_DAC_HPWR_5G,
497 EEP_FRAC_N_5G,
498 EEP_MAC_0 = AR_EEPROM_MAC(0),
499 EEP_MAC_1 = AR_EEPROM_MAC(1),
500 EEP_MAC_2 = AR_EEPROM_MAC(2)
501 };
502
503 enum ar5416_rates {
504 rate6mb, rate9mb, rate12mb, rate18mb,
505 rate24mb, rate36mb, rate48mb, rate54mb,
506 rate1l, rate2l, rate2s, rate5_5l,
507 rate5_5s, rate11l, rate11s, rateXr,
508 rateHt20_0, rateHt20_1, rateHt20_2, rateHt20_3,
509 rateHt20_4, rateHt20_5, rateHt20_6, rateHt20_7,
510 rateHt40_0, rateHt40_1, rateHt40_2, rateHt40_3,
511 rateHt40_4, rateHt40_5, rateHt40_6, rateHt40_7,
512 rateDupCck, rateDupOfdm, rateExtCck, rateExtOfdm,
513 Ar5416RateSize
514 };
515
516 enum ath9k_hal_freq_band {
517 ATH9K_HAL_FREQ_BAND_5GHZ = 0,
518 ATH9K_HAL_FREQ_BAND_2GHZ = 1
519 };
520
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