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5083 avoid undefined order of operations in assignments
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--- old/usr/src/uts/common/io/nxge/nxge_virtual.c
+++ new/usr/src/uts/common/io/nxge/nxge_virtual.c
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21 /*
22 22 * Copyright (c) 2006, 2010, Oracle and/or its affiliates. All rights reserved.
23 23 */
24 24
25 25 #include <sys/nxge/nxge_impl.h>
26 26 #include <sys/nxge/nxge_mac.h>
27 27 #include <sys/nxge/nxge_hio.h>
28 28
29 29 /*
30 30 * Local defines for FWARC 2006/556
31 31 */
32 32 #define NXGE_NIU_TDMA_PROP_LEN 2
33 33 #define NXGE_NIU_RDMA_PROP_LEN 2
34 34 #define NXGE_NIU_0_INTR_PROP_LEN 19
35 35 #define NXGE_NIU_1_INTR_PROP_LEN 17
36 36
37 37 /*
38 38 * Local functions.
39 39 */
40 40 static void nxge_get_niu_property(dev_info_t *, niu_type_t *);
41 41 static nxge_status_t nxge_get_mac_addr_properties(p_nxge_t);
42 42 static nxge_status_t nxge_use_cfg_n2niu_properties(p_nxge_t);
43 43 static void nxge_use_cfg_neptune_properties(p_nxge_t);
44 44 static void nxge_use_cfg_dma_config(p_nxge_t);
45 45 static void nxge_use_cfg_vlan_class_config(p_nxge_t);
46 46 static void nxge_use_cfg_mac_class_config(p_nxge_t);
47 47 static void nxge_use_cfg_class_config(p_nxge_t);
48 48 static void nxge_use_cfg_link_cfg(p_nxge_t);
49 49 static void nxge_set_hw_dma_config(p_nxge_t);
50 50 static void nxge_set_hw_vlan_class_config(p_nxge_t);
51 51 static void nxge_set_hw_mac_class_config(p_nxge_t);
52 52 static void nxge_set_hw_class_config(p_nxge_t);
53 53 static nxge_status_t nxge_use_default_dma_config_n2(p_nxge_t);
54 54 static void nxge_ldgv_setup(p_nxge_ldg_t *, p_nxge_ldv_t *, uint8_t,
55 55 uint8_t, int *);
56 56 static void nxge_init_mmac(p_nxge_t, boolean_t);
57 57 static void nxge_set_rdc_intr_property(p_nxge_t);
58 58
59 59 uint32_t nxge_use_hw_property = 1;
60 60 uint32_t nxge_groups_per_port = 2;
61 61
62 62 extern uint32_t nxge_use_partition;
63 63 extern uint32_t nxge_dma_obp_props_only;
64 64
65 65 extern uint_t nxge_rx_intr(void *, void *);
66 66 extern uint_t nxge_tx_intr(void *, void *);
67 67 extern uint_t nxge_mif_intr(void *, void *);
68 68 extern uint_t nxge_mac_intr(void *, void *);
69 69 extern uint_t nxge_syserr_intr(void *, void *);
70 70 extern void *nxge_list;
71 71
72 72 #define NXGE_SHARED_REG_SW_SIM
73 73
74 74 #ifdef NXGE_SHARED_REG_SW_SIM
75 75 uint64_t global_dev_ctrl = 0;
76 76 #endif
77 77
78 78 #define MAX_SIBLINGS NXGE_MAX_PORTS
79 79
80 80 extern uint32_t nxge_rbr_size;
81 81 extern uint32_t nxge_rcr_size;
82 82 extern uint32_t nxge_tx_ring_size;
83 83 extern uint32_t nxge_rbr_spare_size;
84 84
85 85 extern npi_status_t npi_mac_altaddr_disable(npi_handle_t, uint8_t, uint8_t);
86 86
87 87 static uint8_t p2_tx_fair[2] = {12, 12};
88 88 static uint8_t p2_tx_equal[2] = {12, 12};
89 89 static uint8_t p4_tx_fair[4] = {6, 6, 6, 6};
90 90 static uint8_t p4_tx_equal[4] = {6, 6, 6, 6};
91 91 static uint8_t p2_rx_fair[2] = {8, 8};
92 92 static uint8_t p2_rx_equal[2] = {8, 8};
93 93 static uint8_t p4_rx_fair[4] = {4, 4, 4, 4};
94 94 static uint8_t p4_rx_equal[4] = {4, 4, 4, 4};
95 95
96 96 static uint8_t p2_rdcgrp_fair[2] = {4, 4};
97 97 static uint8_t p2_rdcgrp_equal[2] = {4, 4};
98 98 static uint8_t p4_rdcgrp_fair[4] = {2, 2, 1, 1};
99 99 static uint8_t p4_rdcgrp_equal[4] = {2, 2, 2, 2};
100 100 static uint8_t p2_rdcgrp_cls[2] = {1, 1};
101 101 static uint8_t p4_rdcgrp_cls[4] = {1, 1, 1, 1};
102 102
103 103 static uint8_t rx_4_1G[4] = {4, 4, 4, 4};
104 104 static uint8_t rx_2_10G[2] = {8, 8};
105 105 static uint8_t rx_2_10G_2_1G[4] = {6, 6, 2, 2};
106 106 static uint8_t rx_1_10G_3_1G[4] = {10, 2, 2, 2};
107 107 static uint8_t rx_1_1G_1_10G_2_1G[4] = {2, 10, 2, 2};
108 108
109 109 static uint8_t tx_4_1G[4] = {6, 6, 6, 6};
110 110 static uint8_t tx_2_10G[2] = {12, 12};
111 111 static uint8_t tx_2_10G_2_1G[4] = {10, 10, 2, 2};
112 112 static uint8_t tx_1_10G_3_1G[4] = {12, 4, 4, 4};
113 113 static uint8_t tx_1_1G_1_10G_2_1G[4] = {4, 12, 4, 4};
114 114
115 115 typedef enum {
116 116 DEFAULT = 0,
117 117 EQUAL,
118 118 FAIR,
119 119 CUSTOM,
120 120 CLASSIFY,
121 121 L2_CLASSIFY,
122 122 L3_DISTRIBUTE,
123 123 L3_CLASSIFY,
124 124 L3_TCAM,
125 125 CONFIG_TOKEN_NONE
126 126 } config_token_t;
127 127
128 128 static char *token_names[] = {
129 129 "default",
130 130 "equal",
131 131 "fair",
132 132 "custom",
133 133 "classify",
134 134 "l2_classify",
135 135 "l3_distribute",
136 136 "l3_classify",
137 137 "l3_tcam",
138 138 "none",
139 139 };
140 140
141 141 void nxge_virint_regs_dump(p_nxge_t nxgep);
142 142
143 143 void
144 144 nxge_virint_regs_dump(p_nxge_t nxgep)
145 145 {
146 146 npi_handle_t handle;
147 147
148 148 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_virint_regs_dump"));
149 149 handle = NXGE_DEV_NPI_HANDLE(nxgep);
150 150 (void) npi_vir_dump_pio_fzc_regs_one(handle);
151 151 (void) npi_vir_dump_ldgnum(handle);
152 152 (void) npi_vir_dump_ldsv(handle);
153 153 (void) npi_vir_dump_imask0(handle);
154 154 (void) npi_vir_dump_sid(handle);
155 155 (void) npi_mac_dump_regs(handle, nxgep->function_num);
156 156 (void) npi_ipp_dump_regs(handle, nxgep->function_num);
157 157 (void) npi_fflp_dump_regs(handle);
158 158 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_virint_regs_dump"));
159 159 }
160 160
161 161 /*
162 162 * For now: we hard coded the DMA configurations.
163 163 * and assume for one partition only.
164 164 *
165 165 * OBP. Then OBP will pass this partition's
166 166 * Neptune configurations to fcode to create
167 167 * properties for them.
168 168 *
169 169 * Since Neptune(PCI-E) and NIU (Niagara-2) has
170 170 * different bus interfaces, the driver needs
171 171 * to know which bus it is connected to.
172 172 * Ravinder suggested: create a device property.
173 173 * In partitioning environment, we cannot
174 174 * use .conf file (need to check). If conf changes,
175 175 * need to reboot the system.
176 176 * The following function assumes that we will
177 177 * retrieve its properties from a virtualized nexus driver.
178 178 */
179 179
180 180 nxge_status_t
181 181 nxge_cntlops(dev_info_t *dip, nxge_ctl_enum_t ctlop, void *arg, void *result)
182 182 {
183 183 nxge_status_t status = NXGE_OK;
184 184 int instance;
185 185 p_nxge_t nxgep;
186 186
187 187 #ifndef NXGE_SHARED_REG_SW_SIM
188 188 npi_handle_t handle;
189 189 uint16_t sr16, cr16;
190 190 #endif
191 191 instance = ddi_get_instance(dip);
192 192 NXGE_DEBUG_MSG((NULL, VIR_CTL, "Instance %d ", instance));
193 193
194 194 if (nxge_list == NULL) {
195 195 NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL,
196 196 "nxge_cntlops: nxge_list null"));
197 197 return (NXGE_ERROR);
198 198 }
199 199 nxgep = (p_nxge_t)ddi_get_soft_state(nxge_list, instance);
200 200 if (nxgep == NULL) {
201 201 NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL,
202 202 "nxge_cntlops: nxgep null"));
203 203 return (NXGE_ERROR);
204 204 }
205 205 #ifndef NXGE_SHARED_REG_SW_SIM
206 206 handle = nxgep->npi_reg_handle;
207 207 #endif
208 208 switch (ctlop) {
209 209 case NXGE_CTLOPS_NIUTYPE:
210 210 nxge_get_niu_property(dip, (niu_type_t *)result);
211 211 return (status);
212 212
213 213 case NXGE_CTLOPS_GET_SHARED_REG:
214 214 #ifdef NXGE_SHARED_REG_SW_SIM
215 215 *(uint64_t *)result = global_dev_ctrl;
216 216 return (0);
217 217 #else
218 218 status = npi_dev_func_sr_sr_get(handle, &sr16);
219 219 *(uint16_t *)result = sr16;
220 220 NXGE_DEBUG_MSG((NULL, VIR_CTL,
221 221 "nxge_cntlops: NXGE_CTLOPS_GET_SHARED_REG"));
222 222 return (0);
223 223 #endif
224 224
225 225 case NXGE_CTLOPS_SET_SHARED_REG_LOCK:
226 226 #ifdef NXGE_SHARED_REG_SW_SIM
227 227 global_dev_ctrl = *(uint64_t *)arg;
228 228 return (0);
229 229 #else
230 230 status = NPI_FAILURE;
231 231 while (status != NPI_SUCCESS)
232 232 status = npi_dev_func_sr_lock_enter(handle);
233 233
234 234 sr16 = *(uint16_t *)arg;
235 235 status = npi_dev_func_sr_sr_set_only(handle, &sr16);
236 236 status = npi_dev_func_sr_lock_free(handle);
237 237 NXGE_DEBUG_MSG((NULL, VIR_CTL,
238 238 "nxge_cntlops: NXGE_CTLOPS_SET_SHARED_REG"));
239 239 return (0);
240 240 #endif
241 241
242 242 case NXGE_CTLOPS_UPDATE_SHARED_REG:
243 243 #ifdef NXGE_SHARED_REG_SW_SIM
244 244 global_dev_ctrl |= *(uint64_t *)arg;
245 245 return (0);
246 246 #else
247 247 status = NPI_FAILURE;
248 248 while (status != NPI_SUCCESS)
249 249 status = npi_dev_func_sr_lock_enter(handle);
250 250 status = npi_dev_func_sr_sr_get(handle, &sr16);
251 251 sr16 |= *(uint16_t *)arg;
252 252 status = npi_dev_func_sr_sr_set_only(handle, &sr16);
253 253 status = npi_dev_func_sr_lock_free(handle);
254 254 NXGE_DEBUG_MSG((NULL, VIR_CTL,
255 255 "nxge_cntlops: NXGE_CTLOPS_SET_SHARED_REG"));
256 256 return (0);
257 257 #endif
258 258
259 259 case NXGE_CTLOPS_CLEAR_BIT_SHARED_REG_UL:
260 260 #ifdef NXGE_SHARED_REG_SW_SIM
261 261 global_dev_ctrl |= *(uint64_t *)arg;
262 262 return (0);
263 263 #else
264 264 status = npi_dev_func_sr_sr_get(handle, &sr16);
265 265 cr16 = *(uint16_t *)arg;
266 266 sr16 &= ~cr16;
267 267 status = npi_dev_func_sr_sr_set_only(handle, &sr16);
268 268 NXGE_DEBUG_MSG((NULL, VIR_CTL,
269 269 "nxge_cntlops: NXGE_CTLOPS_SET_SHARED_REG"));
270 270 return (0);
271 271 #endif
272 272
273 273 case NXGE_CTLOPS_CLEAR_BIT_SHARED_REG:
274 274 #ifdef NXGE_SHARED_REG_SW_SIM
275 275 global_dev_ctrl |= *(uint64_t *)arg;
276 276 return (0);
277 277 #else
278 278 status = NPI_FAILURE;
279 279 while (status != NPI_SUCCESS)
280 280 status = npi_dev_func_sr_lock_enter(handle);
281 281 status = npi_dev_func_sr_sr_get(handle, &sr16);
282 282 cr16 = *(uint16_t *)arg;
283 283 sr16 &= ~cr16;
284 284 status = npi_dev_func_sr_sr_set_only(handle, &sr16);
285 285 status = npi_dev_func_sr_lock_free(handle);
286 286 NXGE_DEBUG_MSG((NULL, VIR_CTL,
287 287 "nxge_cntlops: NXGE_CTLOPS_SET_SHARED_REG"));
288 288 return (0);
289 289 #endif
290 290
291 291 case NXGE_CTLOPS_GET_LOCK_BLOCK:
292 292 #ifdef NXGE_SHARED_REG_SW_SIM
293 293 global_dev_ctrl |= *(uint64_t *)arg;
294 294 return (0);
295 295 #else
296 296 status = NPI_FAILURE;
297 297 while (status != NPI_SUCCESS)
298 298 status = npi_dev_func_sr_lock_enter(handle);
299 299 NXGE_DEBUG_MSG((NULL, VIR_CTL,
300 300 "nxge_cntlops: NXGE_CTLOPS_GET_LOCK_BLOCK"));
301 301 return (0);
302 302 #endif
303 303 case NXGE_CTLOPS_GET_LOCK_TRY:
304 304 #ifdef NXGE_SHARED_REG_SW_SIM
305 305 global_dev_ctrl |= *(uint64_t *)arg;
306 306 return (0);
307 307 #else
308 308 status = npi_dev_func_sr_lock_enter(handle);
309 309 NXGE_DEBUG_MSG((NULL, VIR_CTL,
310 310 "nxge_cntlops: NXGE_CTLOPS_GET_LOCK_TRY"));
311 311 if (status == NPI_SUCCESS)
312 312 return (NXGE_OK);
313 313 else
314 314 return (NXGE_ERROR);
315 315 #endif
316 316 case NXGE_CTLOPS_FREE_LOCK:
317 317 #ifdef NXGE_SHARED_REG_SW_SIM
318 318 global_dev_ctrl |= *(uint64_t *)arg;
319 319 return (0);
320 320 #else
321 321 status = npi_dev_func_sr_lock_free(handle);
322 322 NXGE_DEBUG_MSG((NULL, VIR_CTL,
323 323 "nxge_cntlops: NXGE_CTLOPS_GET_LOCK_FREE"));
324 324 if (status == NPI_SUCCESS)
325 325 return (NXGE_OK);
326 326 else
327 327 return (NXGE_ERROR);
328 328 #endif
329 329
330 330 default:
331 331 status = NXGE_ERROR;
332 332 }
333 333
334 334 return (status);
335 335 }
336 336
337 337 void
338 338 nxge_common_lock_get(p_nxge_t nxgep)
339 339 {
340 340 uint32_t status = NPI_FAILURE;
341 341 npi_handle_t handle;
342 342
343 343 #if defined(NXGE_SHARE_REG_SW_SIM)
344 344 return;
345 345 #endif
346 346 handle = nxgep->npi_reg_handle;
347 347 while (status != NPI_SUCCESS)
348 348 status = npi_dev_func_sr_lock_enter(handle);
349 349 }
350 350
351 351 void
352 352 nxge_common_lock_free(p_nxge_t nxgep)
353 353 {
354 354 npi_handle_t handle;
355 355
356 356 #if defined(NXGE_SHARE_REG_SW_SIM)
357 357 return;
358 358 #endif
359 359 handle = nxgep->npi_reg_handle;
360 360 (void) npi_dev_func_sr_lock_free(handle);
361 361 }
362 362
363 363
364 364 static void
365 365 nxge_get_niu_property(dev_info_t *dip, niu_type_t *niu_type)
366 366 {
367 367 uchar_t *prop_val;
368 368 uint_t prop_len;
369 369
370 370 *niu_type = NIU_TYPE_NONE;
371 371 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, dip, 0,
372 372 "niu-type", (uchar_t **)&prop_val,
373 373 &prop_len) == DDI_PROP_SUCCESS) {
374 374 if (strncmp("niu", (caddr_t)prop_val, (size_t)prop_len) == 0) {
375 375 *niu_type = N2_NIU;
376 376 }
377 377 ddi_prop_free(prop_val);
378 378 }
379 379 }
380 380
381 381 static config_token_t
382 382 nxge_get_config_token(char *prop)
383 383 {
384 384 config_token_t token = DEFAULT;
385 385
386 386 while (token < CONFIG_TOKEN_NONE) {
387 387 if (strncmp(prop, token_names[token], 4) == 0)
388 388 break;
389 389 token++;
390 390 }
391 391 return (token);
392 392 }
393 393
394 394 /* per port */
395 395
396 396 static nxge_status_t
397 397 nxge_update_rxdma_grp_properties(p_nxge_t nxgep, config_token_t token,
398 398 dev_info_t *s_dip[])
399 399 {
400 400 nxge_status_t status = NXGE_OK;
401 401 int ddi_status;
402 402 int num_ports = nxgep->nports;
403 403 int port, bits, j;
404 404 uint8_t start_grp = 0, num_grps = 0;
405 405 p_nxge_param_t param_arr;
406 406 uint32_t grp_bitmap[MAX_SIBLINGS];
407 407 int custom_start_grp[MAX_SIBLINGS];
408 408 int custom_num_grp[MAX_SIBLINGS];
409 409 uint8_t bad_config = B_FALSE;
410 410 char *start_prop, *num_prop, *cfg_prop;
411 411
412 412 start_grp = 0;
413 413 param_arr = nxgep->param_arr;
414 414 start_prop = param_arr[param_rdc_grps_start].fcode_name;
415 415 num_prop = param_arr[param_rx_rdc_grps].fcode_name;
416 416
417 417 switch (token) {
418 418 case FAIR:
419 419 cfg_prop = "fair";
420 420 for (port = 0; port < num_ports; port++) {
421 421 custom_num_grp[port] =
422 422 (num_ports == 4) ?
423 423 p4_rdcgrp_fair[port] :
424 424 p2_rdcgrp_fair[port];
425 425 custom_start_grp[port] = start_grp;
426 426 start_grp += custom_num_grp[port];
427 427 }
428 428 break;
429 429
430 430 case EQUAL:
431 431 cfg_prop = "equal";
432 432 for (port = 0; port < num_ports; port++) {
433 433 custom_num_grp[port] =
434 434 (num_ports == 4) ?
435 435 p4_rdcgrp_equal[port] :
436 436 p2_rdcgrp_equal[port];
437 437 custom_start_grp[port] = start_grp;
438 438 start_grp += custom_num_grp[port];
439 439 }
440 440 break;
441 441
442 442
443 443 case CLASSIFY:
444 444 cfg_prop = "classify";
445 445 for (port = 0; port < num_ports; port++) {
446 446 custom_num_grp[port] = (num_ports == 4) ?
447 447 p4_rdcgrp_cls[port] : p2_rdcgrp_cls[port];
448 448 custom_start_grp[port] = start_grp;
449 449 start_grp += custom_num_grp[port];
450 450 }
451 451 break;
452 452
453 453 case CUSTOM:
454 454 cfg_prop = "custom";
455 455 /* See if it is good config */
456 456 num_grps = 0;
457 457 for (port = 0; port < num_ports; port++) {
458 458 custom_start_grp[port] =
459 459 ddi_prop_get_int(DDI_DEV_T_NONE, s_dip[port],
460 460 DDI_PROP_DONTPASS, start_prop, -1);
461 461 if ((custom_start_grp[port] == -1) ||
462 462 (custom_start_grp[port] >=
463 463 NXGE_MAX_RDC_GRPS)) {
464 464 bad_config = B_TRUE;
465 465 break;
466 466 }
467 467 custom_num_grp[port] = ddi_prop_get_int(
468 468 DDI_DEV_T_NONE,
469 469 s_dip[port],
470 470 DDI_PROP_DONTPASS,
471 471 num_prop, -1);
472 472
473 473 if ((custom_num_grp[port] == -1) ||
474 474 (custom_num_grp[port] >
475 475 NXGE_MAX_RDC_GRPS) ||
476 476 ((custom_num_grp[port] +
477 477 custom_start_grp[port]) >=
478 478 NXGE_MAX_RDC_GRPS)) {
479 479 bad_config = B_TRUE;
480 480 break;
481 481 }
482 482 num_grps += custom_num_grp[port];
483 483 if (num_grps > NXGE_MAX_RDC_GRPS) {
484 484 bad_config = B_TRUE;
485 485 break;
486 486 }
487 487 grp_bitmap[port] = 0;
488 488 for (bits = 0;
489 489 bits < custom_num_grp[port];
490 490 bits++) {
491 491 grp_bitmap[port] |=
492 492 (1 << (bits + custom_start_grp[port]));
493 493 }
494 494
495 495 }
496 496
497 497 if (bad_config == B_FALSE) {
498 498 /* check for overlap */
499 499 for (port = 0; port < num_ports - 1; port++) {
500 500 for (j = port + 1; j < num_ports; j++) {
501 501 if (grp_bitmap[port] &
502 502 grp_bitmap[j]) {
503 503 bad_config = B_TRUE;
504 504 break;
505 505 }
506 506 }
507 507 if (bad_config == B_TRUE)
508 508 break;
509 509 }
510 510 }
511 511 if (bad_config == B_TRUE) {
512 512 /* use default config */
513 513 for (port = 0; port < num_ports; port++) {
514 514 custom_num_grp[port] =
515 515 (num_ports == 4) ?
516 516 p4_rx_fair[port] : p2_rx_fair[port];
517 517 custom_start_grp[port] = start_grp;
518 518 start_grp += custom_num_grp[port];
519 519 }
520 520 }
521 521 break;
522 522
523 523 default:
524 524 /* use default config */
525 525 cfg_prop = "fair";
526 526 for (port = 0; port < num_ports; port++) {
527 527 custom_num_grp[port] = (num_ports == 4) ?
528 528 p4_rx_fair[port] : p2_rx_fair[port];
529 529 custom_start_grp[port] = start_grp;
530 530 start_grp += custom_num_grp[port];
531 531 }
532 532 break;
533 533 }
534 534
535 535 /* Now Update the rx properties */
536 536 for (port = 0; port < num_ports; port++) {
537 537 ddi_status = ddi_prop_update_string(DDI_DEV_T_NONE, s_dip[port],
538 538 "rxdma-grp-cfg", cfg_prop);
539 539 if (ddi_status != DDI_PROP_SUCCESS) {
540 540 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
541 541 " property %s not updating",
542 542 cfg_prop));
543 543 status |= NXGE_DDI_FAILED;
544 544 }
545 545 ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE, s_dip[port],
546 546 num_prop, custom_num_grp[port]);
547 547
548 548 if (ddi_status != DDI_PROP_SUCCESS) {
549 549 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
550 550 " property %s not updating",
551 551 num_prop));
552 552 status |= NXGE_DDI_FAILED;
553 553 }
554 554 ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE, s_dip[port],
555 555 start_prop, custom_start_grp[port]);
556 556
557 557 if (ddi_status != DDI_PROP_SUCCESS) {
558 558 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
559 559 " property %s not updating",
560 560 start_prop));
561 561 status |= NXGE_DDI_FAILED;
562 562 }
563 563 }
564 564 if (status & NXGE_DDI_FAILED)
565 565 status |= NXGE_ERROR;
566 566
567 567 return (status);
568 568 }
569 569
570 570 static nxge_status_t
571 571 nxge_update_rxdma_properties(p_nxge_t nxgep, config_token_t token,
572 572 dev_info_t *s_dip[])
573 573 {
574 574 nxge_status_t status = NXGE_OK;
575 575 int ddi_status;
576 576 int num_ports = nxgep->nports;
577 577 int port, bits, j;
578 578 uint8_t start_rdc = 0, num_rdc = 0;
579 579 p_nxge_param_t param_arr;
580 580 uint32_t rdc_bitmap[MAX_SIBLINGS];
581 581 int custom_start_rdc[MAX_SIBLINGS];
582 582 int custom_num_rdc[MAX_SIBLINGS];
583 583 uint8_t bad_config = B_FALSE;
584 584 int *prop_val;
585 585 uint_t prop_len;
586 586 char *start_rdc_prop, *num_rdc_prop, *cfg_prop;
587 587
588 588 start_rdc = 0;
589 589 param_arr = nxgep->param_arr;
590 590 start_rdc_prop = param_arr[param_rxdma_channels_begin].fcode_name;
591 591 num_rdc_prop = param_arr[param_rxdma_channels].fcode_name;
592 592
593 593 switch (token) {
594 594 case FAIR:
595 595 cfg_prop = "fair";
596 596 for (port = 0; port < num_ports; port++) {
597 597 custom_num_rdc[port] = (num_ports == 4) ?
598 598 p4_rx_fair[port] : p2_rx_fair[port];
599 599 custom_start_rdc[port] = start_rdc;
600 600 start_rdc += custom_num_rdc[port];
601 601 }
602 602 break;
603 603
604 604 case EQUAL:
605 605 cfg_prop = "equal";
606 606 for (port = 0; port < num_ports; port++) {
607 607 custom_num_rdc[port] = (num_ports == 4) ?
608 608 p4_rx_equal[port] :
609 609 p2_rx_equal[port];
610 610 custom_start_rdc[port] = start_rdc;
611 611 start_rdc += custom_num_rdc[port];
612 612 }
613 613 break;
614 614
615 615 case CUSTOM:
616 616 cfg_prop = "custom";
617 617 /* See if it is good config */
618 618 num_rdc = 0;
619 619 for (port = 0; port < num_ports; port++) {
620 620 ddi_status = ddi_prop_lookup_int_array(
621 621 DDI_DEV_T_ANY,
622 622 s_dip[port], 0,
623 623 start_rdc_prop,
624 624 &prop_val,
625 625 &prop_len);
626 626 if (ddi_status == DDI_SUCCESS)
627 627 custom_start_rdc[port] = *prop_val;
628 628 else {
629 629 NXGE_DEBUG_MSG((nxgep, CFG_CTL,
630 630 " %s custom start port %d"
631 631 " read failed ",
632 632 " rxdma-cfg", port));
633 633 bad_config = B_TRUE;
634 634 status |= NXGE_DDI_FAILED;
635 635 }
636 636 if ((custom_start_rdc[port] == -1) ||
637 637 (custom_start_rdc[port] >=
638 638 NXGE_MAX_RDCS)) {
639 639 NXGE_DEBUG_MSG((nxgep, CFG_CTL,
640 640 " %s custom start %d"
641 641 " out of range %x ",
642 642 " rxdma-cfg",
643 643 port,
644 644 custom_start_rdc[port]));
645 645 bad_config = B_TRUE;
646 646 break;
647 647 }
648 648 ddi_status = ddi_prop_lookup_int_array(
649 649 DDI_DEV_T_ANY,
650 650 s_dip[port],
651 651 0,
652 652 num_rdc_prop,
653 653 &prop_val,
654 654 &prop_len);
655 655
656 656 if (ddi_status == DDI_SUCCESS)
657 657 custom_num_rdc[port] = *prop_val;
658 658 else {
659 659 NXGE_DEBUG_MSG((nxgep, CFG_CTL,
660 660 " %s custom num port %d"
661 661 " read failed ",
662 662 "rxdma-cfg", port));
663 663 bad_config = B_TRUE;
664 664 status |= NXGE_DDI_FAILED;
665 665 }
666 666
667 667 if ((custom_num_rdc[port] == -1) ||
668 668 (custom_num_rdc[port] >
669 669 NXGE_MAX_RDCS) ||
670 670 ((custom_num_rdc[port] +
671 671 custom_start_rdc[port]) >
672 672 NXGE_MAX_RDCS)) {
673 673 NXGE_DEBUG_MSG((nxgep, CFG_CTL,
674 674 " %s custom num %d"
675 675 " out of range %x ",
676 676 " rxdma-cfg",
677 677 port, custom_num_rdc[port]));
678 678 bad_config = B_TRUE;
679 679 break;
680 680 }
681 681 num_rdc += custom_num_rdc[port];
682 682 if (num_rdc > NXGE_MAX_RDCS) {
683 683 bad_config = B_TRUE;
684 684 break;
685 685 }
686 686 rdc_bitmap[port] = 0;
687 687 for (bits = 0;
688 688 bits < custom_num_rdc[port]; bits++) {
689 689 rdc_bitmap[port] |=
690 690 (1 << (bits + custom_start_rdc[port]));
691 691 }
692 692 }
693 693
694 694 if (bad_config == B_FALSE) {
695 695 /* check for overlap */
696 696 for (port = 0; port < num_ports - 1; port++) {
697 697 for (j = port + 1; j < num_ports; j++) {
698 698 if (rdc_bitmap[port] &
699 699 rdc_bitmap[j]) {
700 700 NXGE_DEBUG_MSG((nxgep,
701 701 CFG_CTL,
702 702 " rxdma-cfg"
703 703 " property custom"
704 704 " bit overlap"
705 705 " %d %d ",
706 706 port, j));
707 707 bad_config = B_TRUE;
708 708 break;
709 709 }
710 710 }
711 711 if (bad_config == B_TRUE)
712 712 break;
713 713 }
714 714 }
715 715 if (bad_config == B_TRUE) {
716 716 /* use default config */
717 717 NXGE_DEBUG_MSG((nxgep, CFG_CTL,
718 718 " rxdma-cfg property:"
719 719 " bad custom config:"
720 720 " use default"));
721 721 for (port = 0; port < num_ports; port++) {
722 722 custom_num_rdc[port] =
723 723 (num_ports == 4) ?
724 724 p4_rx_fair[port] :
725 725 p2_rx_fair[port];
726 726 custom_start_rdc[port] = start_rdc;
727 727 start_rdc += custom_num_rdc[port];
728 728 }
729 729 }
730 730 break;
731 731
732 732 default:
733 733 /* use default config */
734 734 cfg_prop = "fair";
735 735 for (port = 0; port < num_ports; port++) {
736 736 custom_num_rdc[port] = (num_ports == 4) ?
737 737 p4_rx_fair[port] : p2_rx_fair[port];
738 738 custom_start_rdc[port] = start_rdc;
739 739 start_rdc += custom_num_rdc[port];
740 740 }
741 741 break;
742 742 }
743 743
744 744 /* Now Update the rx properties */
745 745 for (port = 0; port < num_ports; port++) {
746 746 NXGE_DEBUG_MSG((nxgep, CFG_CTL,
747 747 " update property rxdma-cfg with %s ", cfg_prop));
748 748 ddi_status = ddi_prop_update_string(DDI_DEV_T_NONE, s_dip[port],
749 749 "rxdma-cfg", cfg_prop);
750 750 if (ddi_status != DDI_PROP_SUCCESS) {
751 751 NXGE_DEBUG_MSG((nxgep, CFG_CTL,
752 752 " property rxdma-cfg is not updating to %s",
753 753 cfg_prop));
754 754 status |= NXGE_DDI_FAILED;
755 755 }
756 756 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " update property %s with %d ",
757 757 num_rdc_prop, custom_num_rdc[port]));
758 758
759 759 ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE, s_dip[port],
760 760 num_rdc_prop, custom_num_rdc[port]);
761 761
762 762 if (ddi_status != DDI_PROP_SUCCESS) {
763 763 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
764 764 " property %s not updating with %d",
765 765 num_rdc_prop, custom_num_rdc[port]));
766 766 status |= NXGE_DDI_FAILED;
767 767 }
768 768 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " update property %s with %d ",
769 769 start_rdc_prop, custom_start_rdc[port]));
770 770 ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE, s_dip[port],
771 771 start_rdc_prop, custom_start_rdc[port]);
772 772
773 773 if (ddi_status != DDI_PROP_SUCCESS) {
774 774 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
775 775 " property %s not updating with %d ",
776 776 start_rdc_prop, custom_start_rdc[port]));
777 777 status |= NXGE_DDI_FAILED;
778 778 }
779 779 }
780 780 if (status & NXGE_DDI_FAILED)
781 781 status |= NXGE_ERROR;
782 782 return (status);
783 783 }
784 784
785 785 static nxge_status_t
786 786 nxge_update_txdma_properties(p_nxge_t nxgep, config_token_t token,
787 787 dev_info_t *s_dip[])
788 788 {
789 789 nxge_status_t status = NXGE_OK;
790 790 int ddi_status = DDI_SUCCESS;
791 791 int num_ports = nxgep->nports;
792 792 int port, bits, j;
793 793 uint8_t start_tdc, num_tdc = 0;
794 794 p_nxge_param_t param_arr;
795 795 uint32_t tdc_bitmap[MAX_SIBLINGS];
796 796 int custom_start_tdc[MAX_SIBLINGS];
797 797 int custom_num_tdc[MAX_SIBLINGS];
798 798 uint8_t bad_config = B_FALSE;
799 799 int *prop_val;
800 800 uint_t prop_len;
801 801 char *start_tdc_prop, *num_tdc_prop, *cfg_prop;
802 802
803 803 start_tdc = 0;
804 804 param_arr = nxgep->param_arr;
805 805 start_tdc_prop = param_arr[param_txdma_channels_begin].fcode_name;
806 806 num_tdc_prop = param_arr[param_txdma_channels].fcode_name;
807 807
808 808 switch (token) {
809 809 case FAIR:
810 810 cfg_prop = "fair";
811 811 for (port = 0; port < num_ports; port++) {
812 812 custom_num_tdc[port] = (num_ports == 4) ?
813 813 p4_tx_fair[port] : p2_tx_fair[port];
814 814 custom_start_tdc[port] = start_tdc;
815 815 start_tdc += custom_num_tdc[port];
816 816 }
817 817 break;
818 818
819 819 case EQUAL:
820 820 cfg_prop = "equal";
821 821 for (port = 0; port < num_ports; port++) {
822 822 custom_num_tdc[port] = (num_ports == 4) ?
823 823 p4_tx_equal[port] : p2_tx_equal[port];
824 824 custom_start_tdc[port] = start_tdc;
825 825 start_tdc += custom_num_tdc[port];
826 826 }
827 827 break;
828 828
829 829 case CUSTOM:
830 830 cfg_prop = "custom";
831 831 /* See if it is good config */
832 832 num_tdc = 0;
833 833 for (port = 0; port < num_ports; port++) {
834 834 ddi_status = ddi_prop_lookup_int_array(
835 835 DDI_DEV_T_ANY, s_dip[port], 0, start_tdc_prop,
836 836 &prop_val, &prop_len);
837 837 if (ddi_status == DDI_SUCCESS)
838 838 custom_start_tdc[port] = *prop_val;
839 839 else {
840 840 NXGE_DEBUG_MSG((nxgep, CFG_CTL,
841 841 " %s custom start port %d"
842 842 " read failed ", " txdma-cfg", port));
843 843 bad_config = B_TRUE;
844 844 status |= NXGE_DDI_FAILED;
845 845 }
846 846
847 847 if ((custom_start_tdc[port] == -1) ||
848 848 (custom_start_tdc[port] >=
849 849 NXGE_MAX_RDCS)) {
850 850 NXGE_DEBUG_MSG((nxgep, CFG_CTL,
851 851 " %s custom start %d"
852 852 " out of range %x ", " txdma-cfg",
853 853 port, custom_start_tdc[port]));
854 854 bad_config = B_TRUE;
855 855 break;
856 856 }
857 857
858 858 ddi_status = ddi_prop_lookup_int_array(
859 859 DDI_DEV_T_ANY, s_dip[port], 0, num_tdc_prop,
860 860 &prop_val, &prop_len);
861 861 if (ddi_status == DDI_SUCCESS)
862 862 custom_num_tdc[port] = *prop_val;
863 863 else {
864 864 NXGE_DEBUG_MSG((nxgep, CFG_CTL,
865 865 " %s custom num port %d"
866 866 " read failed ", " txdma-cfg", port));
867 867 bad_config = B_TRUE;
868 868 status |= NXGE_DDI_FAILED;
869 869 }
870 870
871 871 if ((custom_num_tdc[port] == -1) ||
872 872 (custom_num_tdc[port] >
873 873 NXGE_MAX_TDCS) ||
874 874 ((custom_num_tdc[port] +
875 875 custom_start_tdc[port]) >
876 876 NXGE_MAX_TDCS)) {
877 877 NXGE_DEBUG_MSG((nxgep, CFG_CTL,
878 878 " %s custom num %d"
879 879 " out of range %x ", " rxdma-cfg",
880 880 port, custom_num_tdc[port]));
881 881 bad_config = B_TRUE;
882 882 break;
883 883 }
884 884 num_tdc += custom_num_tdc[port];
885 885 if (num_tdc > NXGE_MAX_TDCS) {
886 886 bad_config = B_TRUE;
887 887 break;
888 888 }
889 889 tdc_bitmap[port] = 0;
890 890 for (bits = 0;
891 891 bits < custom_num_tdc[port]; bits++) {
892 892 tdc_bitmap[port] |=
893 893 (1 <<
894 894 (bits + custom_start_tdc[port]));
895 895 }
896 896
897 897 }
898 898
899 899 if (bad_config == B_FALSE) {
900 900 /* check for overlap */
901 901 for (port = 0; port < num_ports - 1; port++) {
902 902 for (j = port + 1; j < num_ports; j++) {
903 903 if (tdc_bitmap[port] &
904 904 tdc_bitmap[j]) {
905 905 NXGE_DEBUG_MSG((nxgep, CFG_CTL,
906 906 " rxdma-cfg"
907 907 " property custom"
908 908 " bit overlap"
909 909 " %d %d ",
910 910 port, j));
911 911 bad_config = B_TRUE;
912 912 break;
913 913 }
914 914 }
915 915 if (bad_config == B_TRUE)
916 916 break;
917 917 }
918 918 }
919 919 if (bad_config == B_TRUE) {
920 920 /* use default config */
921 921 NXGE_DEBUG_MSG((nxgep, CFG_CTL,
922 922 " txdma-cfg property:"
923 923 " bad custom config:" " use default"));
924 924
925 925 for (port = 0; port < num_ports; port++) {
926 926 custom_num_tdc[port] = (num_ports == 4) ?
927 927 p4_tx_fair[port] : p2_tx_fair[port];
928 928 custom_start_tdc[port] = start_tdc;
929 929 start_tdc += custom_num_tdc[port];
930 930 }
931 931 }
932 932 break;
933 933
934 934 default:
935 935 /* use default config */
936 936 cfg_prop = "fair";
937 937 for (port = 0; port < num_ports; port++) {
938 938 custom_num_tdc[port] = (num_ports == 4) ?
939 939 p4_tx_fair[port] : p2_tx_fair[port];
940 940 custom_start_tdc[port] = start_tdc;
941 941 start_tdc += custom_num_tdc[port];
942 942 }
943 943 break;
944 944 }
945 945
946 946 /* Now Update the tx properties */
947 947 for (port = 0; port < num_ports; port++) {
948 948 NXGE_DEBUG_MSG((nxgep, CFG_CTL,
949 949 " update property txdma-cfg with %s ", cfg_prop));
950 950 ddi_status = ddi_prop_update_string(DDI_DEV_T_NONE, s_dip[port],
951 951 "txdma-cfg", cfg_prop);
952 952 if (ddi_status != DDI_PROP_SUCCESS) {
953 953 NXGE_DEBUG_MSG((nxgep, CFG_CTL,
954 954 " property txdma-cfg is not updating to %s",
955 955 cfg_prop));
956 956 status |= NXGE_DDI_FAILED;
957 957 }
958 958 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " update property %s with %d ",
959 959 num_tdc_prop, custom_num_tdc[port]));
960 960
961 961 ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE, s_dip[port],
962 962 num_tdc_prop, custom_num_tdc[port]);
963 963
964 964 if (ddi_status != DDI_PROP_SUCCESS) {
965 965 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
966 966 " property %s not updating with %d",
967 967 num_tdc_prop,
968 968 custom_num_tdc[port]));
969 969 status |= NXGE_DDI_FAILED;
970 970 }
971 971
972 972 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " update property %s with %d ",
973 973 start_tdc_prop, custom_start_tdc[port]));
974 974
975 975 ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE, s_dip[port],
976 976 start_tdc_prop, custom_start_tdc[port]);
977 977 if (ddi_status != DDI_PROP_SUCCESS) {
978 978 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
979 979 " property %s not updating with %d ",
980 980 start_tdc_prop, custom_start_tdc[port]));
981 981 status |= NXGE_DDI_FAILED;
982 982 }
983 983 }
984 984 if (status & NXGE_DDI_FAILED)
985 985 status |= NXGE_ERROR;
986 986 return (status);
987 987 }
988 988
989 989 static nxge_status_t
990 990 nxge_update_cfg_properties(p_nxge_t nxgep, uint32_t flags,
991 991 config_token_t token, dev_info_t *s_dip[])
992 992 {
993 993 nxge_status_t status = NXGE_OK;
994 994
995 995 switch (flags) {
996 996 case COMMON_TXDMA_CFG:
997 997 if (nxge_dma_obp_props_only == 0)
998 998 status = nxge_update_txdma_properties(nxgep,
999 999 token, s_dip);
1000 1000 break;
1001 1001 case COMMON_RXDMA_CFG:
1002 1002 if (nxge_dma_obp_props_only == 0)
1003 1003 status = nxge_update_rxdma_properties(nxgep,
1004 1004 token, s_dip);
1005 1005
1006 1006 break;
1007 1007 case COMMON_RXDMA_GRP_CFG:
1008 1008 status = nxge_update_rxdma_grp_properties(nxgep,
1009 1009 token, s_dip);
1010 1010 break;
1011 1011 default:
1012 1012 return (NXGE_ERROR);
1013 1013 }
1014 1014 return (status);
1015 1015 }
1016 1016
1017 1017 /*
1018 1018 * verify consistence.
1019 1019 * (May require publishing the properties on all the ports.
1020 1020 *
1021 1021 * What if properties are published on function 0 device only?
1022 1022 *
1023 1023 *
1024 1024 * rxdma-cfg, txdma-cfg, rxdma-grp-cfg (required )
1025 1025 * What about class configs?
1026 1026 *
1027 1027 * If consistent, update the property on all the siblings.
1028 1028 * set a flag on hardware shared register
1029 1029 * The rest of the siblings will check the flag
1030 1030 * if the flag is set, they will use the updated property
1031 1031 * without doing any validation.
1032 1032 */
1033 1033
1034 1034 nxge_status_t
1035 1035 nxge_cfg_verify_set_classify_prop(p_nxge_t nxgep, char *prop,
1036 1036 uint64_t known_cfg, uint32_t override, dev_info_t *c_dip[])
1037 1037 {
1038 1038 nxge_status_t status = NXGE_OK;
1039 1039 int ddi_status = DDI_SUCCESS;
1040 1040 int i = 0, found = 0, update_prop = B_TRUE;
1041 1041 int *cfg_val;
1042 1042 uint_t new_value, cfg_value[MAX_SIBLINGS];
1043 1043 uint_t prop_len;
1044 1044 uint_t known_cfg_value;
1045 1045
1046 1046 known_cfg_value = (uint_t)known_cfg;
1047 1047
1048 1048 if (override == B_TRUE) {
1049 1049 new_value = known_cfg_value;
1050 1050 for (i = 0; i < nxgep->nports; i++) {
1051 1051 ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE,
1052 1052 c_dip[i], prop, new_value);
1053 1053 #ifdef NXGE_DEBUG_ERROR
1054 1054 if (ddi_status != DDI_PROP_SUCCESS)
1055 1055 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1056 1056 " property %s failed update ", prop));
1057 1057 #endif
1058 1058 }
1059 1059 if (ddi_status != DDI_PROP_SUCCESS)
1060 1060 return (NXGE_ERROR | NXGE_DDI_FAILED);
1061 1061 }
1062 1062 for (i = 0; i < nxgep->nports; i++) {
1063 1063 cfg_value[i] = known_cfg_value;
1064 1064 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, c_dip[i], 0,
1065 1065 prop, &cfg_val,
1066 1066 &prop_len) == DDI_PROP_SUCCESS) {
1067 1067 cfg_value[i] = *cfg_val;
1068 1068 ddi_prop_free(cfg_val);
1069 1069 found++;
1070 1070 }
1071 1071 }
1072 1072
1073 1073 if (found != i) {
1074 1074 NXGE_DEBUG_MSG((nxgep, CFG_CTL,
1075 1075 " property %s not specified on all ports", prop));
1076 1076 if (found == 0) {
1077 1077 /* not specified: Use default */
1078 1078 NXGE_DEBUG_MSG((nxgep, CFG_CTL,
1079 1079 " property %s not specified on any port:"
1080 1080 " Using default", prop));
1081 1081 new_value = known_cfg_value;
1082 1082 } else {
1083 1083 /* specified on some */
1084 1084 NXGE_DEBUG_MSG((nxgep, CFG_CTL,
1085 1085 " property %s not specified"
1086 1086 " on some ports: Using default", prop));
1087 1087 /* ? use p0 value instead ? */
1088 1088 new_value = known_cfg_value;
1089 1089 }
1090 1090 } else {
1091 1091 /* check type and consistence */
1092 1092 /* found on all devices */
1093 1093 for (i = 1; i < found; i++) {
1094 1094 if (cfg_value[i] != cfg_value[i - 1]) {
1095 1095 NXGE_DEBUG_MSG((nxgep, CFG_CTL,
1096 1096 " property %s inconsistent:"
1097 1097 " Using default", prop));
1098 1098 new_value = known_cfg_value;
1099 1099 break;
1100 1100 }
1101 1101 /*
1102 1102 * Found on all the ports and consistent. Nothing to
1103 1103 * do.
1104 1104 */
1105 1105 update_prop = B_FALSE;
1106 1106 }
1107 1107 }
1108 1108
1109 1109 if (update_prop == B_TRUE) {
1110 1110 for (i = 0; i < nxgep->nports; i++) {
1111 1111 ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE,
1112 1112 c_dip[i], prop, new_value);
1113 1113 #ifdef NXGE_DEBUG_ERROR
1114 1114 if (ddi_status != DDI_SUCCESS)
1115 1115 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1116 1116 " property %s not updating with %d"
1117 1117 " Using default",
1118 1118 prop, new_value));
1119 1119 #endif
1120 1120 if (ddi_status != DDI_PROP_SUCCESS)
1121 1121 status |= NXGE_DDI_FAILED;
1122 1122 }
1123 1123 }
1124 1124 if (status & NXGE_DDI_FAILED)
1125 1125 status |= NXGE_ERROR;
1126 1126
1127 1127 return (status);
1128 1128 }
1129 1129
1130 1130 static uint64_t
1131 1131 nxge_class_get_known_cfg(p_nxge_t nxgep, int class_prop, int rx_quick_cfg)
1132 1132 {
1133 1133 int start_prop;
1134 1134 uint64_t cfg_value;
1135 1135 p_nxge_param_t param_arr;
1136 1136
1137 1137 param_arr = nxgep->param_arr;
1138 1138 cfg_value = param_arr[class_prop].value;
1139 1139 start_prop = param_h1_init_value;
1140 1140
1141 1141 /* update the properties per quick config */
1142 1142 switch (rx_quick_cfg) {
1143 1143 case CFG_L3_WEB:
1144 1144 case CFG_L3_DISTRIBUTE:
1145 1145 cfg_value = nxge_classify_get_cfg_value(nxgep,
1146 1146 rx_quick_cfg, class_prop - start_prop);
1147 1147 break;
1148 1148 default:
1149 1149 cfg_value = param_arr[class_prop].value;
1150 1150 break;
1151 1151 }
1152 1152 return (cfg_value);
1153 1153 }
1154 1154
1155 1155 static nxge_status_t
1156 1156 nxge_cfg_verify_set_classify(p_nxge_t nxgep, dev_info_t *c_dip[])
1157 1157 {
1158 1158 nxge_status_t status = NXGE_OK;
1159 1159 int rx_quick_cfg, class_prop, start_prop, end_prop;
1160 1160 char *prop_name;
1161 1161 int override = B_TRUE;
1162 1162 uint64_t cfg_value;
1163 1163 p_nxge_param_t param_arr;
1164 1164
1165 1165 param_arr = nxgep->param_arr;
1166 1166 rx_quick_cfg = param_arr[param_rx_quick_cfg].value;
1167 1167 start_prop = param_h1_init_value;
1168 1168 end_prop = param_class_opt_ipv6_sctp;
1169 1169
1170 1170 /* update the properties per quick config */
1171 1171 if (rx_quick_cfg == CFG_NOT_SPECIFIED)
1172 1172 override = B_FALSE;
1173 1173
1174 1174 /*
1175 1175 * these parameter affect the classification outcome.
1176 1176 * these parameters are used to configure the Flow key and
1177 1177 * the TCAM key for each of the IP classes.
1178 1178 * Included here are also the H1 and H2 initial values
1179 1179 * which affect the distribution as well as final hash value
1180 1180 * (hence the offset into RDC table and FCRAM bucket location)
1181 1181 *
1182 1182 */
1183 1183 for (class_prop = start_prop; class_prop <= end_prop; class_prop++) {
1184 1184 prop_name = param_arr[class_prop].fcode_name;
1185 1185 cfg_value = nxge_class_get_known_cfg(nxgep,
1186 1186 class_prop, rx_quick_cfg);
1187 1187 status = nxge_cfg_verify_set_classify_prop(nxgep, prop_name,
1188 1188 cfg_value, override, c_dip);
1189 1189 }
1190 1190
1191 1191 /*
1192 1192 * these properties do not affect the actual classification outcome.
1193 1193 * used to enable/disable or tune the fflp hardware
1194 1194 *
1195 1195 * fcram_access_ratio, tcam_access_ratio, tcam_enable, llc_snap_enable
1196 1196 *
1197 1197 */
1198 1198 override = B_FALSE;
1199 1199 for (class_prop = param_fcram_access_ratio;
1200 1200 class_prop <= param_llc_snap_enable; class_prop++) {
1201 1201 prop_name = param_arr[class_prop].fcode_name;
1202 1202 cfg_value = param_arr[class_prop].value;
1203 1203 status = nxge_cfg_verify_set_classify_prop(nxgep, prop_name,
1204 1204 cfg_value, override, c_dip);
1205 1205 }
1206 1206
1207 1207 return (status);
1208 1208 }
1209 1209
1210 1210 nxge_status_t
1211 1211 nxge_cfg_verify_set(p_nxge_t nxgep, uint32_t flag)
1212 1212 {
1213 1213 nxge_status_t status = NXGE_OK;
1214 1214 int i = 0, found = 0;
1215 1215 int num_siblings;
1216 1216 dev_info_t *c_dip[MAX_SIBLINGS + 1];
1217 1217 char *prop_val[MAX_SIBLINGS];
1218 1218 config_token_t c_token[MAX_SIBLINGS];
1219 1219 char *prop;
1220 1220
1221 1221 if (nxge_dma_obp_props_only)
1222 1222 return (NXGE_OK);
1223 1223
1224 1224 num_siblings = 0;
1225 1225 c_dip[num_siblings] = ddi_get_child(nxgep->p_dip);
1226 1226 while (c_dip[num_siblings]) {
1227 1227 c_dip[num_siblings + 1] =
1228 1228 ddi_get_next_sibling(c_dip[num_siblings]);
1229 1229 num_siblings++;
1230 1230 }
1231 1231
1232 1232 switch (flag) {
1233 1233 case COMMON_TXDMA_CFG:
1234 1234 prop = "txdma-cfg";
1235 1235 break;
1236 1236 case COMMON_RXDMA_CFG:
1237 1237 prop = "rxdma-cfg";
1238 1238 break;
1239 1239 case COMMON_RXDMA_GRP_CFG:
1240 1240 prop = "rxdma-grp-cfg";
1241 1241 break;
1242 1242 case COMMON_CLASS_CFG:
1243 1243 status = nxge_cfg_verify_set_classify(nxgep, c_dip);
1244 1244 return (status);
1245 1245 default:
1246 1246 return (NXGE_ERROR);
1247 1247 }
1248 1248
1249 1249 i = 0;
1250 1250 while (i < num_siblings) {
1251 1251 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, c_dip[i], 0, prop,
1252 1252 (char **)&prop_val[i]) == DDI_PROP_SUCCESS) {
1253 1253 c_token[i] = nxge_get_config_token(prop_val[i]);
1254 1254 ddi_prop_free(prop_val[i]);
1255 1255 found++;
1256 1256 } else
1257 1257 c_token[i] = CONFIG_TOKEN_NONE;
1258 1258 i++;
1259 1259 }
1260 1260
1261 1261 if (found != i) {
1262 1262 if (found == 0) {
1263 1263 /* not specified: Use default */
1264 1264 NXGE_DEBUG_MSG((nxgep, CFG_CTL,
1265 1265 " property %s not specified on any port:"
1266 1266 " Using default", prop));
1267 1267
1268 1268 status = nxge_update_cfg_properties(nxgep,
1269 1269 flag, FAIR, c_dip);
1270 1270 return (status);
1271 1271 } else {
1272 1272 /*
1273 1273 * if the convention is to use function 0 device then
1274 1274 * populate the other devices with this configuration.
1275 1275 *
1276 1276 * The other alternative is to use the default config.
1277 1277 */
1278 1278 /* not specified: Use default */
1279 1279 NXGE_DEBUG_MSG((nxgep, CFG_CTL,
1280 1280 " property %s not specified on some ports:"
1281 1281 " Using default", prop));
1282 1282 status = nxge_update_cfg_properties(nxgep,
1283 1283 flag, FAIR, c_dip);
1284 1284 return (status);
1285 1285 }
1286 1286 }
1287 1287
1288 1288 /* check type and consistence */
1289 1289 /* found on all devices */
1290 1290 for (i = 1; i < found; i++) {
1291 1291 if (c_token[i] != c_token[i - 1]) {
1292 1292 NXGE_DEBUG_MSG((nxgep, CFG_CTL,
1293 1293 " property %s inconsistent:"
1294 1294 " Using default", prop));
1295 1295 status = nxge_update_cfg_properties(nxgep,
1296 1296 flag, FAIR, c_dip);
1297 1297 return (status);
1298 1298 }
1299 1299 }
1300 1300
1301 1301 /*
1302 1302 * Found on all the ports check if it is custom configuration. if
1303 1303 * custom, then verify consistence
1304 1304 *
1305 1305 * finally create soft properties
1306 1306 */
1307 1307 status = nxge_update_cfg_properties(nxgep, flag, c_token[0], c_dip);
1308 1308 return (status);
1309 1309 }
1310 1310
1311 1311 nxge_status_t
1312 1312 nxge_cfg_verify_set_quick_config(p_nxge_t nxgep)
1313 1313 {
1314 1314 nxge_status_t status = NXGE_OK;
1315 1315 int ddi_status = DDI_SUCCESS;
1316 1316 char *prop_val;
1317 1317 char *rx_prop;
1318 1318 char *prop;
1319 1319 uint32_t cfg_value = CFG_NOT_SPECIFIED;
1320 1320 p_nxge_param_t param_arr;
1321 1321
1322 1322 param_arr = nxgep->param_arr;
1323 1323 rx_prop = param_arr[param_rx_quick_cfg].fcode_name;
1324 1324
1325 1325 prop = "rx-quick-cfg";
1326 1326
1327 1327 /*
1328 1328 * good value are
1329 1329 *
1330 1330 * "web-server" "generic-server" "l3-classify" "flow-classify"
1331 1331 */
1332 1332 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, nxgep->dip, 0,
1333 1333 prop, (char **)&prop_val) != DDI_PROP_SUCCESS) {
1334 1334 NXGE_DEBUG_MSG((nxgep, VPD_CTL,
1335 1335 " property %s not specified: using default ", prop));
1336 1336 cfg_value = CFG_NOT_SPECIFIED;
1337 1337 } else {
1338 1338 cfg_value = CFG_L3_DISTRIBUTE;
1339 1339 if (strncmp("web-server", (caddr_t)prop_val, 8) == 0) {
1340 1340 cfg_value = CFG_L3_WEB;
1341 1341 NXGE_DEBUG_MSG((nxgep, CFG_CTL,
1342 1342 " %s: web server ", prop));
1343 1343 }
1344 1344 if (strncmp("generic-server", (caddr_t)prop_val, 8) == 0) {
1345 1345 cfg_value = CFG_L3_DISTRIBUTE;
1346 1346 NXGE_DEBUG_MSG((nxgep, CFG_CTL,
1347 1347 " %s: distribute ", prop));
1348 1348 }
1349 1349 /* more */
1350 1350 ddi_prop_free(prop_val);
1351 1351 }
1352 1352
1353 1353 ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE, nxgep->dip,
1354 1354 rx_prop, cfg_value);
1355 1355 if (ddi_status != DDI_PROP_SUCCESS)
1356 1356 status |= NXGE_DDI_FAILED;
1357 1357
1358 1358 /* now handle specified cases: */
1359 1359 if (status & NXGE_DDI_FAILED)
1360 1360 status |= NXGE_ERROR;
1361 1361 return (status);
1362 1362 }
1363 1363
1364 1364 /*
1365 1365 * Device properties adv-autoneg-cap etc are defined by FWARC
1366 1366 * http://sac.sfbay/FWARC/2002/345/20020610_asif.haswarey
1367 1367 */
1368 1368 static void
1369 1369 nxge_use_cfg_link_cfg(p_nxge_t nxgep)
1370 1370 {
1371 1371 int *prop_val;
1372 1372 uint_t prop_len;
1373 1373 dev_info_t *dip;
1374 1374 int speed;
1375 1375 int duplex;
1376 1376 int adv_autoneg_cap;
1377 1377 int adv_10gfdx_cap;
1378 1378 int adv_10ghdx_cap;
1379 1379 int adv_1000fdx_cap;
1380 1380 int adv_1000hdx_cap;
1381 1381 int adv_100fdx_cap;
1382 1382 int adv_100hdx_cap;
1383 1383 int adv_10fdx_cap;
1384 1384 int adv_10hdx_cap;
1385 1385 int status = DDI_SUCCESS;
1386 1386
1387 1387 dip = nxgep->dip;
1388 1388
1389 1389 /*
1390 1390 * first find out the card type and the supported link speeds and
1391 1391 * features
1392 1392 */
1393 1393 /* add code for card type */
1394 1394 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, "adv-autoneg-cap",
1395 1395 &prop_val, &prop_len) == DDI_PROP_SUCCESS) {
1396 1396 ddi_prop_free(prop_val);
1397 1397 return;
1398 1398 }
1399 1399
1400 1400 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, "adv-10gfdx-cap",
1401 1401 &prop_val, &prop_len) == DDI_PROP_SUCCESS) {
1402 1402 ddi_prop_free(prop_val);
1403 1403 return;
1404 1404 }
1405 1405
1406 1406 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, "adv-1000hdx-cap",
1407 1407 &prop_val, &prop_len) == DDI_PROP_SUCCESS) {
1408 1408 ddi_prop_free(prop_val);
1409 1409 return;
1410 1410 }
1411 1411
1412 1412 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, "adv-1000fdx-cap",
1413 1413 &prop_val, &prop_len) == DDI_PROP_SUCCESS) {
1414 1414 ddi_prop_free(prop_val);
1415 1415 return;
1416 1416 }
1417 1417
1418 1418 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, "adv-100fdx-cap",
1419 1419 &prop_val, &prop_len) == DDI_PROP_SUCCESS) {
1420 1420 ddi_prop_free(prop_val);
1421 1421 return;
1422 1422 }
1423 1423
1424 1424 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, "adv-100hdx-cap",
1425 1425 &prop_val, &prop_len) == DDI_PROP_SUCCESS) {
1426 1426 ddi_prop_free(prop_val);
1427 1427 return;
1428 1428 }
1429 1429
1430 1430 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, "adv-10fdx-cap",
1431 1431 &prop_val, &prop_len) == DDI_PROP_SUCCESS) {
1432 1432 ddi_prop_free(prop_val);
1433 1433 return;
1434 1434 }
1435 1435
1436 1436 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, "adv-10hdx-cap",
1437 1437 &prop_val, &prop_len) == DDI_PROP_SUCCESS) {
1438 1438 ddi_prop_free(prop_val);
1439 1439 return;
1440 1440 }
1441 1441
1442 1442 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, dip, 0, "speed",
1443 1443 (uchar_t **)&prop_val, &prop_len) == DDI_PROP_SUCCESS) {
1444 1444 if (strncmp("10000", (caddr_t)prop_val,
1445 1445 (size_t)prop_len) == 0) {
1446 1446 speed = 10000;
1447 1447 } else if (strncmp("1000", (caddr_t)prop_val,
1448 1448 (size_t)prop_len) == 0) {
1449 1449 speed = 1000;
1450 1450 } else if (strncmp("100", (caddr_t)prop_val,
1451 1451 (size_t)prop_len) == 0) {
1452 1452 speed = 100;
1453 1453 } else if (strncmp("10", (caddr_t)prop_val,
1454 1454 (size_t)prop_len) == 0) {
1455 1455 speed = 10;
1456 1456 } else if (strncmp("auto", (caddr_t)prop_val,
1457 1457 (size_t)prop_len) == 0) {
1458 1458 speed = 0;
1459 1459 } else {
1460 1460 NXGE_ERROR_MSG((nxgep, NXGE_NOTE,
1461 1461 "speed property is invalid reverting to auto"));
1462 1462 speed = 0;
1463 1463 }
1464 1464 ddi_prop_free(prop_val);
1465 1465 } else
1466 1466 speed = 0;
1467 1467
1468 1468 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, dip, 0, "duplex",
1469 1469 (uchar_t **)&prop_val, &prop_len) == DDI_PROP_SUCCESS) {
1470 1470 if (strncmp("full", (caddr_t)prop_val,
1471 1471 (size_t)prop_len) == 0) {
1472 1472 duplex = 2;
1473 1473 } else if (strncmp("half", (caddr_t)prop_val,
1474 1474 (size_t)prop_len) == 0) {
1475 1475 duplex = 1;
1476 1476 } else if (strncmp("auto", (caddr_t)prop_val,
1477 1477 (size_t)prop_len) == 0) {
1478 1478 duplex = 0;
1479 1479 } else {
1480 1480 NXGE_ERROR_MSG((nxgep, NXGE_NOTE,
1481 1481 "duplex property is invalid"
1482 1482 " reverting to auto"));
1483 1483 duplex = 0;
1484 1484 }
1485 1485 ddi_prop_free(prop_val);
1486 1486 } else
1487 1487 duplex = 0;
1488 1488
1489 1489 /* speed == 0 or duplex == 0 means auto negotiation. */
1490 1490 adv_autoneg_cap = (speed == 0) || (duplex == 0);
1491 1491 if (adv_autoneg_cap == 0) {
1492 1492 adv_10gfdx_cap = ((speed == 10000) && (duplex == 2));
1493 1493 adv_10ghdx_cap = adv_10gfdx_cap;
1494 1494 adv_10ghdx_cap |= ((speed == 10000) && (duplex == 1));
1495 1495 adv_1000fdx_cap = adv_10ghdx_cap;
1496 1496 adv_1000fdx_cap |= ((speed == 1000) && (duplex == 2));
1497 1497 adv_1000hdx_cap = adv_1000fdx_cap;
1498 1498 adv_1000hdx_cap |= ((speed == 1000) && (duplex == 1));
1499 1499 adv_100fdx_cap = adv_1000hdx_cap;
1500 1500 adv_100fdx_cap |= ((speed == 100) && (duplex == 2));
1501 1501 adv_100hdx_cap = adv_100fdx_cap;
1502 1502 adv_100hdx_cap |= ((speed == 100) && (duplex == 1));
1503 1503 adv_10fdx_cap = adv_100hdx_cap;
1504 1504 adv_10fdx_cap |= ((speed == 10) && (duplex == 2));
1505 1505 adv_10hdx_cap = adv_10fdx_cap;
1506 1506 adv_10hdx_cap |= ((speed == 10) && (duplex == 1));
1507 1507 } else if (speed == 0) {
1508 1508 adv_10gfdx_cap = (duplex == 2);
1509 1509 adv_10ghdx_cap = (duplex == 1);
1510 1510 adv_1000fdx_cap = (duplex == 2);
1511 1511 adv_1000hdx_cap = (duplex == 1);
1512 1512 adv_100fdx_cap = (duplex == 2);
1513 1513 adv_100hdx_cap = (duplex == 1);
1514 1514 adv_10fdx_cap = (duplex == 2);
1515 1515 adv_10hdx_cap = (duplex == 1);
1516 1516 }
1517 1517 if (duplex == 0) {
1518 1518 adv_10gfdx_cap = (speed == 0);
1519 1519 adv_10gfdx_cap |= (speed == 10000);
1520 1520 adv_10ghdx_cap = adv_10gfdx_cap;
1521 1521 adv_10ghdx_cap |= (speed == 10000);
1522 1522 adv_1000fdx_cap = adv_10ghdx_cap;
1523 1523 adv_1000fdx_cap |= (speed == 1000);
1524 1524 adv_1000hdx_cap = adv_1000fdx_cap;
1525 1525 adv_1000hdx_cap |= (speed == 1000);
1526 1526 adv_100fdx_cap = adv_1000hdx_cap;
1527 1527 adv_100fdx_cap |= (speed == 100);
1528 1528 adv_100hdx_cap = adv_100fdx_cap;
1529 1529 adv_100hdx_cap |= (speed == 100);
1530 1530 adv_10fdx_cap = adv_100hdx_cap;
1531 1531 adv_10fdx_cap |= (speed == 10);
1532 1532 adv_10hdx_cap = adv_10fdx_cap;
1533 1533 adv_10hdx_cap |= (speed == 10);
1534 1534 }
1535 1535 status = ddi_prop_update_int_array(DDI_DEV_T_NONE, dip,
1536 1536 "adv-autoneg-cap", &adv_autoneg_cap, 1);
1537 1537 if (status)
1538 1538 return;
1539 1539
1540 1540 status = ddi_prop_update_int_array(DDI_DEV_T_NONE, dip,
1541 1541 "adv-10gfdx-cap", &adv_10gfdx_cap, 1);
1542 1542 if (status)
1543 1543 goto nxge_map_myargs_to_gmii_fail1;
1544 1544
1545 1545 status = ddi_prop_update_int_array(DDI_DEV_T_NONE, dip,
1546 1546 "adv-10ghdx-cap", &adv_10ghdx_cap, 1);
1547 1547 if (status)
1548 1548 goto nxge_map_myargs_to_gmii_fail2;
1549 1549
1550 1550 status = ddi_prop_update_int_array(DDI_DEV_T_NONE, dip,
1551 1551 "adv-1000fdx-cap", &adv_1000fdx_cap, 1);
1552 1552 if (status)
1553 1553 goto nxge_map_myargs_to_gmii_fail3;
1554 1554
1555 1555 status = ddi_prop_update_int_array(DDI_DEV_T_NONE, dip,
1556 1556 "adv-1000hdx-cap", &adv_1000hdx_cap, 1);
1557 1557 if (status)
1558 1558 goto nxge_map_myargs_to_gmii_fail4;
1559 1559
1560 1560 status = ddi_prop_update_int_array(DDI_DEV_T_NONE, dip,
1561 1561 "adv-100fdx-cap", &adv_100fdx_cap, 1);
1562 1562 if (status)
1563 1563 goto nxge_map_myargs_to_gmii_fail5;
1564 1564
1565 1565 status = ddi_prop_update_int_array(DDI_DEV_T_NONE, dip,
1566 1566 "adv-100hdx-cap", &adv_100hdx_cap, 1);
1567 1567 if (status)
1568 1568 goto nxge_map_myargs_to_gmii_fail6;
1569 1569
1570 1570 status = ddi_prop_update_int_array(DDI_DEV_T_NONE, dip,
1571 1571 "adv-10fdx-cap", &adv_10fdx_cap, 1);
1572 1572 if (status)
1573 1573 goto nxge_map_myargs_to_gmii_fail7;
1574 1574
1575 1575 status = ddi_prop_update_int_array(DDI_DEV_T_NONE, dip,
1576 1576 "adv-10hdx-cap", &adv_10hdx_cap, 1);
1577 1577 if (status)
1578 1578 goto nxge_map_myargs_to_gmii_fail8;
1579 1579
1580 1580 return;
1581 1581
1582 1582 nxge_map_myargs_to_gmii_fail9:
1583 1583 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "adv-10hdx-cap");
1584 1584
1585 1585 nxge_map_myargs_to_gmii_fail8:
1586 1586 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "adv-10fdx-cap");
1587 1587
1588 1588 nxge_map_myargs_to_gmii_fail7:
1589 1589 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "adv-100hdx-cap");
1590 1590
1591 1591 nxge_map_myargs_to_gmii_fail6:
1592 1592 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "adv-100fdx-cap");
1593 1593
1594 1594 nxge_map_myargs_to_gmii_fail5:
1595 1595 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "adv-1000hdx-cap");
1596 1596
1597 1597 nxge_map_myargs_to_gmii_fail4:
1598 1598 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "adv-1000fdx-cap");
1599 1599
1600 1600 nxge_map_myargs_to_gmii_fail3:
1601 1601 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "adv-10ghdx-cap");
1602 1602
1603 1603 nxge_map_myargs_to_gmii_fail2:
1604 1604 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "adv-10gfdx-cap");
1605 1605
1606 1606 nxge_map_myargs_to_gmii_fail1:
1607 1607 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "adv-autoneg-cap");
1608 1608 }
1609 1609
1610 1610 nxge_status_t
1611 1611 nxge_get_config_properties(p_nxge_t nxgep)
1612 1612 {
1613 1613 nxge_status_t status = NXGE_OK;
1614 1614 p_nxge_hw_list_t hw_p;
1615 1615 char **prop_val;
1616 1616 uint_t prop_len;
1617 1617 uint_t i;
1618 1618
1619 1619 NXGE_DEBUG_MSG((nxgep, VPD_CTL, " ==> nxge_get_config_properties"));
1620 1620
1621 1621 if ((hw_p = nxgep->nxge_hw_p) == NULL) {
1622 1622 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1623 1623 " nxge_get_config_properties:"
1624 1624 " common hardware not set", nxgep->niu_type));
1625 1625 return (NXGE_ERROR);
1626 1626 }
1627 1627
1628 1628 /*
1629 1629 * Get info on how many ports Neptune card has.
1630 1630 */
1631 1631 nxgep->nports = nxge_get_nports(nxgep);
1632 1632 if (nxgep->nports <= 0) {
1633 1633 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1634 1634 "<==nxge_get_config_properties: Invalid Neptune type 0x%x",
1635 1635 nxgep->niu_type));
1636 1636 return (NXGE_ERROR);
1637 1637 }
1638 1638 nxgep->classifier.tcam_size = TCAM_NIU_TCAM_MAX_ENTRY;
1639 1639 if (NXGE_IS_VALID_NEPTUNE_TYPE(nxgep)) {
1640 1640 nxgep->classifier.tcam_size = TCAM_NXGE_TCAM_MAX_ENTRY;
1641 1641 }
1642 1642 if (nxgep->function_num >= nxgep->nports) {
1643 1643 return (NXGE_ERROR);
1644 1644 }
1645 1645
1646 1646 status = nxge_get_mac_addr_properties(nxgep);
1647 1647 if (status != NXGE_OK)
1648 1648 return (NXGE_ERROR);
1649 1649
1650 1650 /*
1651 1651 * read the configuration type. If none is specified, used default.
1652 1652 * Config types: equal: (default) DMA channels, RDC groups, TCAM, FCRAM
1653 1653 * are shared equally across all the ports.
1654 1654 *
1655 1655 * Fair: DMA channels, RDC groups, TCAM, FCRAM are shared proportional
1656 1656 * to the port speed.
1657 1657 *
1658 1658 *
1659 1659 * custom: DMA channels, RDC groups, TCAM, FCRAM partition is
1660 1660 * specified in nxge.conf. Need to read each parameter and set
1661 1661 * up the parameters in nxge structures.
1662 1662 *
1663 1663 */
1664 1664 switch (nxgep->niu_type) {
1665 1665 case N2_NIU:
1666 1666 NXGE_DEBUG_MSG((nxgep, VPD_CTL,
1667 1667 " ==> nxge_get_config_properties: N2"));
1668 1668 MUTEX_ENTER(&hw_p->nxge_cfg_lock);
1669 1669 if ((hw_p->flags & COMMON_CFG_VALID) !=
1670 1670 COMMON_CFG_VALID) {
1671 1671 status = nxge_cfg_verify_set(nxgep,
1672 1672 COMMON_RXDMA_GRP_CFG);
1673 1673 status = nxge_cfg_verify_set(nxgep,
1674 1674 COMMON_CLASS_CFG);
1675 1675 hw_p->flags |= COMMON_CFG_VALID;
1676 1676 }
1677 1677 MUTEX_EXIT(&hw_p->nxge_cfg_lock);
1678 1678 status = nxge_use_cfg_n2niu_properties(nxgep);
1679 1679 break;
1680 1680 default:
1681 1681 if (!NXGE_IS_VALID_NEPTUNE_TYPE(nxgep)) {
1682 1682 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1683 1683 " nxge_get_config_properties:"
1684 1684 " unknown NIU type 0x%x", nxgep->niu_type));
1685 1685 return (NXGE_ERROR);
1686 1686 }
1687 1687
1688 1688 NXGE_DEBUG_MSG((nxgep, VPD_CTL,
1689 1689 " ==> nxge_get_config_properties: Neptune"));
1690 1690 status = nxge_cfg_verify_set_quick_config(nxgep);
1691 1691 MUTEX_ENTER(&hw_p->nxge_cfg_lock);
1692 1692 if ((hw_p->flags & COMMON_CFG_VALID) !=
1693 1693 COMMON_CFG_VALID) {
1694 1694 status = nxge_cfg_verify_set(nxgep,
1695 1695 COMMON_TXDMA_CFG);
1696 1696 status = nxge_cfg_verify_set(nxgep,
1697 1697 COMMON_RXDMA_CFG);
1698 1698 status = nxge_cfg_verify_set(nxgep,
1699 1699 COMMON_RXDMA_GRP_CFG);
1700 1700 status = nxge_cfg_verify_set(nxgep,
1701 1701 COMMON_CLASS_CFG);
1702 1702 hw_p->flags |= COMMON_CFG_VALID;
1703 1703 }
1704 1704 MUTEX_EXIT(&hw_p->nxge_cfg_lock);
1705 1705 nxge_use_cfg_neptune_properties(nxgep);
1706 1706 status = NXGE_OK;
1707 1707 break;
1708 1708 }
1709 1709
1710 1710 /*
1711 1711 * Get the software LSO enable flag property from the
1712 1712 * driver configuration file (nxge.conf).
1713 1713 * This flag will be set to disable (0) if this property
1714 1714 * does not exist.
1715 1715 */
1716 1716 nxgep->soft_lso_enable = ddi_prop_get_int(DDI_DEV_T_ANY, nxgep->dip,
1717 1717 DDI_PROP_DONTPASS | DDI_PROP_NOTPROM, "soft-lso-enable", 0);
1718 1718 NXGE_DEBUG_MSG((nxgep, VPD_CTL,
1719 1719 "nxge_get_config_properties: software lso %d\n",
1720 1720 nxgep->soft_lso_enable));
1721 1721
1722 1722 nxgep->niu_hw_type = NIU_HW_TYPE_DEFAULT;
1723 1723 if (nxgep->niu_type == N2_NIU) {
1724 1724
1725 1725 uchar_t *s_prop_val;
1726 1726
1727 1727 /*
1728 1728 * For NIU, the next generation KT has
1729 1729 * a few differences in features that the
1730 1730 * driver needs to handle them
1731 1731 * accordingly.
1732 1732 */
1733 1733 if (ddi_prop_lookup_string_array(DDI_DEV_T_ANY, nxgep->dip, 0,
1734 1734 "compatible", &prop_val, &prop_len) == DDI_PROP_SUCCESS) {
1735 1735 for (i = 0; i < prop_len; i++) {
1736 1736 if ((strcmp((caddr_t)prop_val[i],
1737 1737 KT_NIU_COMPATIBLE) == 0)) {
1738 1738 nxgep->niu_hw_type = NIU_HW_TYPE_RF;
1739 1739 NXGE_DEBUG_MSG((nxgep, VPD_CTL,
1740 1740 "NIU type %d", nxgep->niu_hw_type));
1741 1741 break;
1742 1742 }
1743 1743 }
1744 1744 }
1745 1745
1746 1746 ddi_prop_free(prop_val);
1747 1747 /*
1748 1748 * Some Serdes and PHY properties may also be provided as OBP
1749 1749 * properties
1750 1750 */
1751 1751 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, nxgep->dip, 0,
1752 1752 "tx-cfg-l", &s_prop_val, &prop_len) == DDI_PROP_SUCCESS) {
1753 1753 nxgep->srds_prop.tx_cfg_l =
1754 1754 (uint16_t)(*(uint32_t *)s_prop_val);
1755 1755 NXGE_DEBUG_MSG((nxgep, VPD_CTL,
1756 1756 "nxge_get_config_properties: "
1757 1757 "tx_cfg_l 0x%x, Read from OBP",
1758 1758 nxgep->srds_prop.tx_cfg_l));
1759 1759 nxgep->srds_prop.prop_set |= NXGE_SRDS_TXCFGL;
1760 1760 ddi_prop_free(s_prop_val);
1761 1761 }
1762 1762 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, nxgep->dip, 0,
1763 1763 "tx-cfg-h", &s_prop_val, &prop_len) == DDI_PROP_SUCCESS) {
1764 1764 nxgep->srds_prop.tx_cfg_h =
1765 1765 (uint16_t)(*(uint32_t *)s_prop_val);
1766 1766 NXGE_DEBUG_MSG((nxgep, VPD_CTL,
1767 1767 "nxge_get_config_properties: "
1768 1768 "tx_cfg_h 0x%x, Read from OBP",
1769 1769 nxgep->srds_prop.tx_cfg_h));
1770 1770 nxgep->srds_prop.prop_set |= NXGE_SRDS_TXCFGH;
1771 1771 ddi_prop_free(s_prop_val);
1772 1772 }
1773 1773 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, nxgep->dip, 0,
1774 1774 "rx-cfg-l", &s_prop_val, &prop_len) == DDI_PROP_SUCCESS) {
1775 1775 nxgep->srds_prop.rx_cfg_l =
1776 1776 (uint16_t)(*(uint32_t *)s_prop_val);
1777 1777 NXGE_DEBUG_MSG((nxgep, VPD_CTL,
1778 1778 "nxge_get_config_properties: "
1779 1779 "rx_cfg_l 0x%x, Read from OBP",
1780 1780 nxgep->srds_prop.rx_cfg_l));
1781 1781 nxgep->srds_prop.prop_set |= NXGE_SRDS_RXCFGL;
1782 1782 ddi_prop_free(s_prop_val);
1783 1783 }
1784 1784 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, nxgep->dip, 0,
1785 1785 "rx-cfg-h", &s_prop_val, &prop_len) == DDI_PROP_SUCCESS) {
1786 1786 nxgep->srds_prop.rx_cfg_h =
1787 1787 (uint16_t)(*(uint32_t *)s_prop_val);
1788 1788 NXGE_DEBUG_MSG((nxgep, VPD_CTL,
1789 1789 "nxge_get_config_properties: "
1790 1790 "rx_cfg_h 0x%x, Read from OBP",
1791 1791 nxgep->srds_prop.rx_cfg_h));
1792 1792 nxgep->srds_prop.prop_set |= NXGE_SRDS_RXCFGH;
1793 1793 ddi_prop_free(s_prop_val);
1794 1794 }
1795 1795 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, nxgep->dip, 0,
1796 1796 "pll-cfg", &s_prop_val, &prop_len) == DDI_PROP_SUCCESS) {
1797 1797 nxgep->srds_prop.pll_cfg_l =
1798 1798 (uint16_t)(*(uint32_t *)s_prop_val);
1799 1799 NXGE_DEBUG_MSG((nxgep, VPD_CTL,
1800 1800 "nxge_get_config_properties: "
1801 1801 "pll_cfg_l 0x%x, Read from OBP",
1802 1802 nxgep->srds_prop.pll_cfg_l));
1803 1803 nxgep->srds_prop.prop_set |= NXGE_SRDS_PLLCFGL;
1804 1804 ddi_prop_free(s_prop_val);
1805 1805 }
1806 1806 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, nxgep->dip, 0,
1807 1807 "phy-reg-values", &s_prop_val, &prop_len) ==
1808 1808 DDI_PROP_SUCCESS) {
1809 1809
1810 1810 int tun_cnt, i;
1811 1811 uchar_t *arr = s_prop_val;
1812 1812
1813 1813 tun_cnt = prop_len / 6; /* 3 values, 2 bytes each */
1814 1814 nxgep->phy_prop.arr =
1815 1815 KMEM_ZALLOC(sizeof (nxge_phy_mdio_val_t) * tun_cnt,
1816 1816 KM_SLEEP);
1817 1817 nxgep->phy_prop.cnt = tun_cnt;
1818 1818 for (i = 0; i < tun_cnt; i++) {
1819 1819 nxgep->phy_prop.arr[i].dev = *(uint16_t *)arr;
1820 1820 arr += 2;
1821 1821 nxgep->phy_prop.arr[i].reg = *(uint16_t *)arr;
1822 1822 arr += 2;
1823 1823 nxgep->phy_prop.arr[i].val = *(uint16_t *)arr;
1824 1824 arr += 2;
1825 1825 NXGE_DEBUG_MSG((nxgep, VPD_CTL,
1826 1826 "nxge_get_config_properties: From OBP, "
1827 1827 "read PHY <dev.reg.val> = "
1828 1828 "<0x%x.0x%x.0x%x>",
1829 1829 nxgep->phy_prop.arr[i].dev,
1830 1830 nxgep->phy_prop.arr[i].reg,
1831 1831 nxgep->phy_prop.arr[i].val));
1832 1832 }
1833 1833 ddi_prop_free(s_prop_val);
1834 1834 }
1835 1835 }
1836 1836
1837 1837 NXGE_DEBUG_MSG((nxgep, VPD_CTL, " <== nxge_get_config_properties"));
1838 1838 return (status);
1839 1839 }
1840 1840
1841 1841 static nxge_status_t
1842 1842 nxge_use_cfg_n2niu_properties(p_nxge_t nxgep)
1843 1843 {
1844 1844 nxge_status_t status = NXGE_OK;
1845 1845
1846 1846 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " ==> nxge_use_cfg_n2niu_properties"));
1847 1847
1848 1848 status = nxge_use_default_dma_config_n2(nxgep);
1849 1849 if (status != NXGE_OK) {
1850 1850 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1851 1851 " ==> nxge_use_cfg_n2niu_properties (err 0x%x)",
1852 1852 status));
1853 1853 return (status | NXGE_ERROR);
1854 1854 }
1855 1855
1856 1856 (void) nxge_use_cfg_vlan_class_config(nxgep);
1857 1857 (void) nxge_use_cfg_mac_class_config(nxgep);
1858 1858 (void) nxge_use_cfg_class_config(nxgep);
1859 1859 (void) nxge_use_cfg_link_cfg(nxgep);
1860 1860
1861 1861 /*
1862 1862 * Read in the hardware (fcode) properties. Use the ndd array to read
1863 1863 * each property.
1864 1864 */
1865 1865 (void) nxge_get_param_soft_properties(nxgep);
1866 1866 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " <== nxge_use_cfg_n2niu_properties"));
1867 1867
1868 1868 return (status);
1869 1869 }
1870 1870
1871 1871 static void
1872 1872 nxge_use_cfg_neptune_properties(p_nxge_t nxgep)
1873 1873 {
1874 1874 NXGE_DEBUG_MSG((nxgep, CFG_CTL, "==> nxge_use_cfg_neptune_properties"));
1875 1875
1876 1876 (void) nxge_use_cfg_dma_config(nxgep);
1877 1877 (void) nxge_use_cfg_vlan_class_config(nxgep);
1878 1878 (void) nxge_use_cfg_mac_class_config(nxgep);
1879 1879 (void) nxge_use_cfg_class_config(nxgep);
1880 1880 (void) nxge_use_cfg_link_cfg(nxgep);
1881 1881
1882 1882 /*
1883 1883 * Read in the hardware (fcode) properties. Use the ndd array to read
1884 1884 * each property.
1885 1885 */
1886 1886 (void) nxge_get_param_soft_properties(nxgep);
1887 1887 NXGE_DEBUG_MSG((nxgep, CFG_CTL, "<== nxge_use_cfg_neptune_properties"));
1888 1888 }
1889 1889
1890 1890 /*
1891 1891 * FWARC 2006/556 for N2 NIU. Get the properties
1892 1892 * from the prom.
1893 1893 */
1894 1894 static nxge_status_t
1895 1895 nxge_use_default_dma_config_n2(p_nxge_t nxgep)
1896 1896 {
1897 1897 int ndmas;
1898 1898 uint8_t func;
1899 1899 p_nxge_dma_pt_cfg_t p_dma_cfgp;
1900 1900 p_nxge_hw_pt_cfg_t p_cfgp;
1901 1901 int *prop_val;
1902 1902 uint_t prop_len;
1903 1903 int i;
1904 1904 nxge_status_t status = NXGE_OK;
1905 1905
1906 1906 NXGE_DEBUG_MSG((nxgep, OBP_CTL, "==> nxge_use_default_dma_config_n2"));
1907 1907
1908 1908 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
1909 1909 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config;
1910 1910
1911 1911 func = nxgep->function_num;
1912 1912 p_cfgp->function_number = func;
1913 1913 ndmas = NXGE_TDMA_PER_NIU_PORT;
1914 1914 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0,
1915 1915 "tx-dma-channels", (int **)&prop_val,
1916 1916 &prop_len) == DDI_PROP_SUCCESS) {
1917 1917 if (prop_len != NXGE_NIU_TDMA_PROP_LEN) {
1918 1918 ddi_prop_free(prop_val);
1919 1919 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1920 1920 "==> nxge_use_default_dma_config_n2: "
1921 1921 "invalid tx-dma-channels property for the NIU, "
1922 1922 "using defaults"));
1923 1923 /*
1924 1924 * Just failover to defaults
1925 1925 */
1926 1926 p_cfgp->tdc.start = (func * NXGE_TDMA_PER_NIU_PORT);
1927 1927 ndmas = NXGE_TDMA_PER_NIU_PORT;
1928 1928 } else {
1929 1929 p_cfgp->tdc.start = prop_val[0];
1930 1930 NXGE_DEBUG_MSG((nxgep, OBP_CTL,
1931 1931 "==> nxge_use_default_dma_config_n2: tdc starts %d "
1932 1932 "(#%d)", p_cfgp->tdc.start, prop_len));
1933 1933
1934 1934 ndmas = prop_val[1];
1935 1935 NXGE_DEBUG_MSG((nxgep, OBP_CTL,
1936 1936 "==> nxge_use_default_dma_config_n2: #tdc %d (#%d)",
1937 1937 ndmas, prop_len));
1938 1938 ddi_prop_free(prop_val);
1939 1939 }
1940 1940 } else {
1941 1941 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1942 1942 "==> nxge_use_default_dma_config_n2: "
1943 1943 "get tx-dma-channels failed"));
1944 1944 return (NXGE_DDI_FAILED);
1945 1945 }
1946 1946
1947 1947 p_cfgp->tdc.count = ndmas;
1948 1948 p_cfgp->tdc.owned = p_cfgp->tdc.count;
1949 1949
1950 1950 NXGE_DEBUG_MSG((nxgep, OBP_CTL, "==> nxge_use_default_dma_config_n2: "
1951 1951 "p_cfgp 0x%llx max_tdcs %d start %d",
1952 1952 p_cfgp, p_cfgp->tdc.count, p_cfgp->tdc.start));
1953 1953
1954 1954 /* Receive DMA */
1955 1955 ndmas = NXGE_RDMA_PER_NIU_PORT;
1956 1956 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0,
1957 1957 "rx-dma-channels", (int **)&prop_val,
1958 1958 &prop_len) == DDI_PROP_SUCCESS) {
1959 1959 if (prop_len != NXGE_NIU_RDMA_PROP_LEN) {
1960 1960 ddi_prop_free(prop_val);
1961 1961 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1962 1962 "==> nxge_use_default_dma_config_n2: "
1963 1963 "invalid rx-dma-channels property for the NIU, "
1964 1964 "using defaults"));
1965 1965 /*
1966 1966 * Just failover to defaults
1967 1967 */
1968 1968 p_cfgp->start_rdc = (func * NXGE_RDMA_PER_NIU_PORT);
1969 1969 ndmas = NXGE_RDMA_PER_NIU_PORT;
1970 1970 } else {
1971 1971 p_cfgp->start_rdc = prop_val[0];
1972 1972 NXGE_DEBUG_MSG((nxgep, OBP_CTL,
1973 1973 "==> nxge_use_default_dma_config_n2(obp):"
1974 1974 " rdc start %d (#%d)",
1975 1975 p_cfgp->start_rdc, prop_len));
1976 1976 ndmas = prop_val[1];
1977 1977 NXGE_DEBUG_MSG((nxgep, OBP_CTL,
1978 1978 "==> nxge_use_default_dma_config_n2(obp): "
1979 1979 "#rdc %d (#%d)", ndmas, prop_len));
1980 1980 ddi_prop_free(prop_val);
1981 1981 }
1982 1982 } else {
1983 1983 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
1984 1984 "==> nxge_use_default_dma_config_n2: "
1985 1985 "get rx-dma-channel failed"));
1986 1986 return (NXGE_DDI_FAILED);
1987 1987 }
1988 1988
1989 1989 p_cfgp->max_rdcs = ndmas;
1990 1990 nxgep->rdc_mask = (ndmas - 1);
1991 1991
1992 1992 /* Hypervisor: rdc # and group # use the same # !! */
1993 1993 p_cfgp->max_grpids = p_cfgp->max_rdcs + p_cfgp->tdc.owned;
1994 1994 p_cfgp->mif_ldvid = p_cfgp->mac_ldvid = p_cfgp->ser_ldvid = 0;
1995 1995
1996 1996 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0,
1997 1997 "interrupts", (int **)&prop_val,
1998 1998 &prop_len) == DDI_PROP_SUCCESS) {
1999 1999 if ((prop_len != NXGE_NIU_0_INTR_PROP_LEN) &&
2000 2000 (prop_len != NXGE_NIU_1_INTR_PROP_LEN)) {
2001 2001 ddi_prop_free(prop_val);
2002 2002 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
2003 2003 "==> nxge_use_default_dma_config_n2: "
2004 2004 "get interrupts failed"));
2005 2005 return (NXGE_DDI_FAILED);
2006 2006 }
2007 2007
2008 2008 /*
2009 2009 * For each device assigned, the content of each interrupts
2010 2010 * property is its logical device group.
2011 2011 *
2012 2012 * Assignment of interrupts property is in the the following
2013 2013 * order:
2014 2014 *
2015 2015 * MAC MIF (if configured) SYSTEM ERROR (if configured) first
2016 2016 * receive channel next channel...... last receive channel
2017 2017 * first transmit channel next channel...... last transmit
2018 2018 * channel
2019 2019 *
2020 2020 * prop_len should be at least for one mac and total # of rx and
2021 2021 * tx channels. Function 0 owns MIF and ERROR
2022 2022 */
2023 2023 NXGE_DEBUG_MSG((nxgep, OBP_CTL,
2024 2024 "==> nxge_use_default_dma_config_n2(obp): "
2025 2025 "# interrupts %d", prop_len));
2026 2026
2027 2027 switch (func) {
2028 2028 case 0:
2029 2029 p_cfgp->ldg_chn_start = 3;
2030 2030 p_cfgp->mac_ldvid = NXGE_MAC_LD_PORT0;
2031 2031 p_cfgp->mif_ldvid = NXGE_MIF_LD;
2032 2032 p_cfgp->ser_ldvid = NXGE_SYS_ERROR_LD;
2033 2033
2034 2034 break;
2035 2035 case 1:
2036 2036 p_cfgp->ldg_chn_start = 1;
2037 2037 p_cfgp->mac_ldvid = NXGE_MAC_LD_PORT1;
2038 2038
2039 2039 break;
2040 2040 default:
2041 2041 status = NXGE_DDI_FAILED;
2042 2042 break;
2043 2043 }
2044 2044
2045 2045 if (status != NXGE_OK)
2046 2046 return (status);
2047 2047
2048 2048 for (i = 0; i < prop_len; i++) {
2049 2049 p_cfgp->ldg[i] = prop_val[i];
2050 2050 NXGE_DEBUG_MSG((nxgep, OBP_CTL,
2051 2051 "==> nxge_use_default_dma_config_n2(obp): "
2052 2052 "F%d: interrupt #%d, ldg %d",
2053 2053 nxgep->function_num, i, p_cfgp->ldg[i]));
2054 2054 }
2055 2055
2056 2056 p_cfgp->max_grpids = prop_len;
2057 2057 NXGE_DEBUG_MSG((nxgep, OBP_CTL,
2058 2058 "==> nxge_use_default_dma_config_n2(obp): %d "
2059 2059 "(#%d) maxgrpids %d channel starts %d",
2060 2060 p_cfgp->mac_ldvid, i, p_cfgp->max_grpids,
2061 2061 p_cfgp->ldg_chn_start));
2062 2062 ddi_prop_free(prop_val);
2063 2063 } else {
2064 2064 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
2065 2065 "==> nxge_use_default_dma_config_n2: "
2066 2066 "get interrupts failed"));
2067 2067 return (NXGE_DDI_FAILED);
2068 2068 }
2069 2069
2070 2070 p_cfgp->max_ldgs = p_cfgp->max_grpids;
2071 2071 NXGE_DEBUG_MSG((nxgep, OBP_CTL,
2072 2072 "==> nxge_use_default_dma_config_n2: p_cfgp 0x%llx max_rdcs %d "
2073 2073 "max_grpids %d macid %d mifid %d serrid %d",
2074 2074 p_cfgp, p_cfgp->max_rdcs, p_cfgp->max_grpids,
2075 2075 p_cfgp->mac_ldvid, p_cfgp->mif_ldvid, p_cfgp->ser_ldvid));
2076 2076
2077 2077
2078 2078 NXGE_DEBUG_MSG((nxgep, OBP_CTL, "==> nxge_use_default_dma_config_n2: "
2079 2079 "p_cfgp p%p start_ldg %d nxgep->max_ldgs %d",
2080 2080 p_cfgp, p_cfgp->start_ldg, p_cfgp->max_ldgs));
2081 2081
2082 2082 /*
2083 2083 * RDC groups and the beginning RDC group assigned to this function.
2084 2084 */
2085 2085 p_cfgp->max_rdc_grpids = NXGE_MAX_RDC_GROUPS / nxgep->nports;
2086 2086 p_cfgp->def_mac_rxdma_grpid =
2087 2087 nxgep->function_num * NXGE_MAX_RDC_GROUPS / nxgep->nports;
2088 2088 p_cfgp->def_mac_txdma_grpid =
2089 2089 nxgep->function_num * NXGE_MAX_TDC_GROUPS / nxgep->nports;
2090 2090
2091 2091 if ((p_cfgp->def_mac_rxdma_grpid = nxge_fzc_rdc_tbl_bind(nxgep,
2092 2092 p_cfgp->def_mac_rxdma_grpid, B_TRUE)) >= NXGE_MAX_RDC_GRPS) {
2093 2093 NXGE_ERROR_MSG((nxgep, CFG_CTL,
2094 2094 "nxge_use_default_dma_config_n2(): "
2095 2095 "nxge_fzc_rdc_tbl_bind failed"));
2096 2096 return (NXGE_DDI_FAILED);
2097 2097 }
2098 2098
2099 2099 status = ddi_prop_update_int(DDI_DEV_T_NONE, nxgep->dip,
2100 2100 "rx-rdc-grps", p_cfgp->max_rdc_grpids);
2101 2101 if (status) {
2102 2102 return (NXGE_DDI_FAILED);
2103 2103 }
2104 2104 status = ddi_prop_update_int(DDI_DEV_T_NONE, nxgep->dip,
2105 2105 "rx-rdc-grps-begin", p_cfgp->def_mac_rxdma_grpid);
2106 2106 if (status) {
2107 2107 (void) ddi_prop_remove(DDI_DEV_T_NONE, nxgep->dip,
2108 2108 "rx-rdc-grps");
2109 2109 return (NXGE_DDI_FAILED);
2110 2110 }
2111 2111 NXGE_DEBUG_MSG((nxgep, OBP_CTL, "==> nxge_use_default_dma_config_n2: "
2112 2112 "p_cfgp $%p # rdc groups %d start rdc group id %d",
2113 2113 p_cfgp, p_cfgp->max_rdc_grpids,
2114 2114 p_cfgp->def_mac_rxdma_grpid));
2115 2115
2116 2116 nxgep->intr_timeout = NXGE_RDC_RCR_TIMEOUT;
2117 2117 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0,
2118 2118 "rxdma-intr-time", (int **)&prop_val, &prop_len) ==
2119 2119 DDI_PROP_SUCCESS) {
2120 2120 if ((prop_len > 0) && (prop_len <= p_cfgp->max_rdcs)) {
2121 2121 nxgep->intr_timeout = prop_val[0];
2122 2122 (void) ddi_prop_update_int_array(DDI_DEV_T_NONE,
2123 2123 nxgep->dip, "rxdma-intr-time", prop_val, prop_len);
2124 2124 }
2125 2125 ddi_prop_free(prop_val);
2126 2126 }
2127 2127
2128 2128 nxgep->intr_threshold = NXGE_RDC_RCR_THRESHOLD;
2129 2129 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0,
2130 2130 "rxdma-intr-pkts", (int **)&prop_val, &prop_len) ==
2131 2131 DDI_PROP_SUCCESS) {
2132 2132 if ((prop_len > 0) && (prop_len <= p_cfgp->max_rdcs)) {
2133 2133 nxgep->intr_threshold = prop_val[0];
2134 2134 (void) ddi_prop_update_int_array(DDI_DEV_T_NONE,
2135 2135 nxgep->dip, "rxdma-intr-pkts", prop_val, prop_len);
2136 2136 }
2137 2137 ddi_prop_free(prop_val);
2138 2138 }
2139 2139
2140 2140 nxge_set_hw_dma_config(nxgep);
2141 2141 NXGE_DEBUG_MSG((nxgep, OBP_CTL, "<== nxge_use_default_dma_config_n2"));
2142 2142 return (status);
2143 2143 }
2144 2144
2145 2145 static void
2146 2146 nxge_use_cfg_dma_config(p_nxge_t nxgep)
2147 2147 {
2148 2148 int tx_ndmas, rx_ndmas, nrxgp, st_txdma, st_rxdma;
2149 2149 p_nxge_dma_pt_cfg_t p_dma_cfgp;
2150 2150 p_nxge_hw_pt_cfg_t p_cfgp;
2151 2151 dev_info_t *dip;
2152 2152 p_nxge_param_t param_arr;
2153 2153 char *prop;
2154 2154 int *prop_val;
2155 2155 uint_t prop_len;
2156 2156 int i;
2157 2157 uint8_t *ch_arr_p;
2158 2158
2159 2159 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " ==> nxge_use_cfg_dma_config"));
2160 2160 param_arr = nxgep->param_arr;
2161 2161
2162 2162 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
2163 2163 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config;
2164 2164 dip = nxgep->dip;
2165 2165 p_cfgp->function_number = nxgep->function_num;
2166 2166 prop = param_arr[param_txdma_channels_begin].fcode_name;
2167 2167
2168 2168 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, prop,
2169 2169 &prop_val, &prop_len) == DDI_PROP_SUCCESS) {
2170 2170 p_cfgp->tdc.start = *prop_val;
2171 2171 ddi_prop_free(prop_val);
2172 2172 } else {
2173 2173 switch (nxgep->niu_type) {
2174 2174 case NEPTUNE_4_1GC:
2175 2175 ch_arr_p = &tx_4_1G[0];
2176 2176 break;
2177 2177 case NEPTUNE_2_10GF:
2178 2178 ch_arr_p = &tx_2_10G[0];
2179 2179 break;
2180 2180 case NEPTUNE_2_10GF_2_1GC:
2181 2181 case NEPTUNE_2_10GF_2_1GRF:
2182 2182 ch_arr_p = &tx_2_10G_2_1G[0];
2183 2183 break;
2184 2184 case NEPTUNE_1_10GF_3_1GC:
2185 2185 ch_arr_p = &tx_1_10G_3_1G[0];
2186 2186 break;
2187 2187 case NEPTUNE_1_1GC_1_10GF_2_1GC:
2188 2188 ch_arr_p = &tx_1_1G_1_10G_2_1G[0];
2189 2189 break;
2190 2190 default:
2191 2191 switch (nxgep->platform_type) {
2192 2192 case P_NEPTUNE_ALONSO:
2193 2193 ch_arr_p = &tx_2_10G_2_1G[0];
2194 2194 break;
2195 2195 default:
2196 2196 ch_arr_p = &p4_tx_equal[0];
2197 2197 break;
2198 2198 }
2199 2199 break;
2200 2200 }
2201 2201 st_txdma = 0;
2202 2202 for (i = 0; i < nxgep->function_num; i++, ch_arr_p++)
2203 2203 st_txdma += *ch_arr_p;
2204 2204
2205 2205 (void) ddi_prop_update_int(DDI_DEV_T_NONE, nxgep->dip,
2206 2206 prop, st_txdma);
2207 2207 p_cfgp->tdc.start = st_txdma;
2208 2208 }
2209 2209
2210 2210 prop = param_arr[param_txdma_channels].fcode_name;
2211 2211 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, prop,
2212 2212 &prop_val, &prop_len) == DDI_PROP_SUCCESS) {
2213 2213 tx_ndmas = *prop_val;
2214 2214 ddi_prop_free(prop_val);
2215 2215 } else {
2216 2216 switch (nxgep->niu_type) {
2217 2217 case NEPTUNE_4_1GC:
2218 2218 tx_ndmas = tx_4_1G[nxgep->function_num];
2219 2219 break;
2220 2220 case NEPTUNE_2_10GF:
2221 2221 tx_ndmas = tx_2_10G[nxgep->function_num];
2222 2222 break;
2223 2223 case NEPTUNE_2_10GF_2_1GC:
2224 2224 case NEPTUNE_2_10GF_2_1GRF:
2225 2225 tx_ndmas = tx_2_10G_2_1G[nxgep->function_num];
2226 2226 break;
2227 2227 case NEPTUNE_1_10GF_3_1GC:
2228 2228 tx_ndmas = tx_1_10G_3_1G[nxgep->function_num];
2229 2229 break;
2230 2230 case NEPTUNE_1_1GC_1_10GF_2_1GC:
2231 2231 tx_ndmas = tx_1_1G_1_10G_2_1G[nxgep->function_num];
2232 2232 break;
2233 2233 default:
2234 2234 switch (nxgep->platform_type) {
2235 2235 case P_NEPTUNE_ALONSO:
2236 2236 tx_ndmas = tx_2_10G_2_1G[nxgep->function_num];
2237 2237 break;
2238 2238 default:
2239 2239 tx_ndmas = p4_tx_equal[nxgep->function_num];
2240 2240 break;
2241 2241 }
2242 2242 break;
2243 2243 }
2244 2244 (void) ddi_prop_update_int(DDI_DEV_T_NONE, nxgep->dip,
2245 2245 prop, tx_ndmas);
2246 2246 }
2247 2247
2248 2248 p_cfgp->tdc.count = tx_ndmas;
2249 2249 p_cfgp->tdc.owned = p_cfgp->tdc.count;
2250 2250 NXGE_DEBUG_MSG((nxgep, CFG_CTL, "==> nxge_use_cfg_dma_config: "
2251 2251 "p_cfgp 0x%llx max_tdcs %d", p_cfgp, p_cfgp->tdc.count));
2252 2252
2253 2253 prop = param_arr[param_rxdma_channels_begin].fcode_name;
2254 2254
2255 2255 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, prop,
2256 2256 &prop_val, &prop_len) == DDI_PROP_SUCCESS) {
2257 2257 p_cfgp->start_rdc = *prop_val;
2258 2258 ddi_prop_free(prop_val);
2259 2259 } else {
2260 2260 switch (nxgep->niu_type) {
2261 2261 case NEPTUNE_4_1GC:
2262 2262 ch_arr_p = &rx_4_1G[0];
2263 2263 break;
2264 2264 case NEPTUNE_2_10GF:
2265 2265 ch_arr_p = &rx_2_10G[0];
2266 2266 break;
2267 2267 case NEPTUNE_2_10GF_2_1GC:
2268 2268 case NEPTUNE_2_10GF_2_1GRF:
2269 2269 ch_arr_p = &rx_2_10G_2_1G[0];
2270 2270 break;
2271 2271 case NEPTUNE_1_10GF_3_1GC:
2272 2272 ch_arr_p = &rx_1_10G_3_1G[0];
2273 2273 break;
2274 2274 case NEPTUNE_1_1GC_1_10GF_2_1GC:
2275 2275 ch_arr_p = &rx_1_1G_1_10G_2_1G[0];
2276 2276 break;
2277 2277 default:
2278 2278 switch (nxgep->platform_type) {
2279 2279 case P_NEPTUNE_ALONSO:
2280 2280 ch_arr_p = &rx_2_10G_2_1G[0];
2281 2281 break;
2282 2282 default:
2283 2283 ch_arr_p = &p4_rx_equal[0];
2284 2284 break;
2285 2285 }
2286 2286 break;
2287 2287 }
2288 2288 st_rxdma = 0;
2289 2289 for (i = 0; i < nxgep->function_num; i++, ch_arr_p++)
2290 2290 st_rxdma += *ch_arr_p;
2291 2291
2292 2292 (void) ddi_prop_update_int(DDI_DEV_T_NONE, nxgep->dip,
2293 2293 prop, st_rxdma);
2294 2294 p_cfgp->start_rdc = st_rxdma;
2295 2295 }
2296 2296
2297 2297 prop = param_arr[param_rxdma_channels].fcode_name;
2298 2298
2299 2299 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, prop,
2300 2300 &prop_val, &prop_len) == DDI_PROP_SUCCESS) {
2301 2301 rx_ndmas = *prop_val;
2302 2302 ddi_prop_free(prop_val);
2303 2303 } else {
2304 2304 switch (nxgep->niu_type) {
2305 2305 case NEPTUNE_4_1GC:
2306 2306 rx_ndmas = rx_4_1G[nxgep->function_num];
2307 2307 break;
2308 2308 case NEPTUNE_2_10GF:
2309 2309 rx_ndmas = rx_2_10G[nxgep->function_num];
2310 2310 break;
2311 2311 case NEPTUNE_2_10GF_2_1GC:
2312 2312 case NEPTUNE_2_10GF_2_1GRF:
2313 2313 rx_ndmas = rx_2_10G_2_1G[nxgep->function_num];
2314 2314 break;
2315 2315 case NEPTUNE_1_10GF_3_1GC:
2316 2316 rx_ndmas = rx_1_10G_3_1G[nxgep->function_num];
2317 2317 break;
2318 2318 case NEPTUNE_1_1GC_1_10GF_2_1GC:
2319 2319 rx_ndmas = rx_1_1G_1_10G_2_1G[nxgep->function_num];
2320 2320 break;
2321 2321 default:
2322 2322 switch (nxgep->platform_type) {
2323 2323 case P_NEPTUNE_ALONSO:
2324 2324 rx_ndmas = rx_2_10G_2_1G[nxgep->function_num];
2325 2325 break;
2326 2326 default:
2327 2327 rx_ndmas = p4_rx_equal[nxgep->function_num];
2328 2328 break;
2329 2329 }
2330 2330 break;
2331 2331 }
2332 2332 (void) ddi_prop_update_int(DDI_DEV_T_NONE, nxgep->dip,
2333 2333 prop, rx_ndmas);
2334 2334 }
2335 2335
2336 2336 p_cfgp->max_rdcs = rx_ndmas;
2337 2337
2338 2338 /*
2339 2339 * RDC groups and the beginning RDC group assigned to this function.
2340 2340 * XXX: this may be wrong if prop value is used.
2341 2341 */
2342 2342 p_cfgp->def_mac_rxdma_grpid =
2343 2343 nxgep->function_num * NXGE_MAX_RDC_GROUPS / nxgep->nports;
2344 2344 p_cfgp->def_mac_txdma_grpid =
2345 2345 nxgep->function_num * NXGE_MAX_TDC_GROUPS / nxgep->nports;
2346 2346
2347 2347 if ((p_cfgp->def_mac_rxdma_grpid = nxge_fzc_rdc_tbl_bind(nxgep,
2348 2348 p_cfgp->def_mac_rxdma_grpid, B_TRUE)) >= NXGE_MAX_RDC_GRPS) {
2349 2349 NXGE_ERROR_MSG((nxgep, CFG_CTL,
2350 2350 "nxge_use_default_dma_config2(): "
2351 2351 "nxge_fzc_rdc_tbl_bind failed"));
2352 2352 goto nxge_use_cfg_dma_config_exit;
2353 2353 }
2354 2354
2355 2355 prop = param_arr[param_rx_rdc_grps].fcode_name;
2356 2356 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, prop,
2357 2357 &prop_val, &prop_len) == DDI_PROP_SUCCESS) {
2358 2358 nrxgp = *prop_val;
2359 2359 ddi_prop_free(prop_val);
2360 2360 } else {
2361 2361 nrxgp = NXGE_MAX_RDC_GRPS / nxgep->nports;
2362 2362 (void) ddi_prop_update_int(DDI_DEV_T_NONE, nxgep->dip,
2363 2363 prop, nrxgp);
2364 2364 NXGE_DEBUG_MSG((nxgep, CFG_CTL,
2365 2365 "==> nxge_use_default_dma_config: "
2366 2366 "num_rdc_grpid not found: use def:# of "
2367 2367 "rdc groups %d\n", nrxgp));
2368 2368 }
2369 2369 p_cfgp->max_rdc_grpids = nrxgp;
2370 2370
2371 2371 /*
2372 2372 * 2/4 ports have the same hard-wired logical groups assigned.
2373 2373 */
2374 2374 p_cfgp->start_ldg = nxgep->function_num * NXGE_LDGRP_PER_4PORTS;
2375 2375 p_cfgp->max_ldgs = NXGE_LDGRP_PER_4PORTS;
2376 2376
2377 2377 NXGE_DEBUG_MSG((nxgep, CFG_CTL, "==> nxge_use_default_dma_config: "
2378 2378 "p_cfgp 0x%llx max_rdcs %d max_grpids %d default_grpid %d",
2379 2379 p_cfgp, p_cfgp->max_rdcs, p_cfgp->max_grpids,
2380 2380 p_cfgp->def_mac_rxdma_grpid));
2381 2381
2382 2382 NXGE_DEBUG_MSG((nxgep, CFG_CTL, "==> nxge_use_cfg_dma_config: "
2383 2383 "p_cfgp 0x%016llx start_ldg %d nxgep->max_ldgs %d "
2384 2384 "def_mac_rxdma_grpid %d",
2385 2385 p_cfgp, p_cfgp->start_ldg, p_cfgp->max_ldgs,
2386 2386 p_cfgp->def_mac_rxdma_grpid));
2387 2387
2388 2388 nxgep->intr_timeout = NXGE_RDC_RCR_TIMEOUT;
2389 2389 prop = param_arr[param_rxdma_intr_time].fcode_name;
2390 2390
2391 2391 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, prop,
2392 2392 &prop_val, &prop_len) == DDI_PROP_SUCCESS) {
2393 2393 if ((prop_len > 0) && (prop_len <= p_cfgp->max_rdcs)) {
2394 2394 nxgep->intr_timeout = prop_val[0];
2395 2395 (void) ddi_prop_update_int_array(DDI_DEV_T_NONE,
2396 2396 nxgep->dip, prop, prop_val, prop_len);
2397 2397 }
2398 2398 ddi_prop_free(prop_val);
2399 2399 }
2400 2400
2401 2401 nxgep->intr_threshold = NXGE_RDC_RCR_THRESHOLD;
2402 2402 prop = param_arr[param_rxdma_intr_pkts].fcode_name;
2403 2403
2404 2404 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, prop,
2405 2405 &prop_val, &prop_len) == DDI_PROP_SUCCESS) {
2406 2406 if ((prop_len > 0) && (prop_len <= p_cfgp->max_rdcs)) {
2407 2407 nxgep->intr_threshold = prop_val[0];
2408 2408 (void) ddi_prop_update_int_array(DDI_DEV_T_NONE,
2409 2409 nxgep->dip, prop, prop_val, prop_len);
2410 2410 }
2411 2411 ddi_prop_free(prop_val);
2412 2412 }
2413 2413 nxge_set_hw_dma_config(nxgep);
2414 2414
2415 2415 NXGE_DEBUG_MSG((nxgep, CFG_CTL, "<== nxge_use_cfg_dma_config: "
2416 2416 "sTDC[%d] nTDC[%d] sRDC[%d] nRDC[%d]",
2417 2417 p_cfgp->tdc.start, p_cfgp->tdc.count,
2418 2418 p_cfgp->start_rdc, p_cfgp->max_rdcs));
2419 2419
2420 2420 nxge_use_cfg_dma_config_exit:
2421 2421 NXGE_DEBUG_MSG((nxgep, CFG_CTL, "<== nxge_use_cfg_dma_config"));
2422 2422 }
2423 2423
2424 2424 void
2425 2425 nxge_get_logical_props(p_nxge_t nxgep)
2426 2426 {
2427 2427 nxge_dma_pt_cfg_t *port = &nxgep->pt_config;
2428 2428 nxge_hw_pt_cfg_t *hardware;
2429 2429 nxge_rdc_grp_t *group;
2430 2430
2431 2431 (void) memset(port, 0, sizeof (*port));
2432 2432
2433 2433 port->mac_port = nxgep->function_num; /* := function number */
2434 2434
2435 2435 /*
2436 2436 * alloc_buf_size:
2437 2437 * dead variables.
2438 2438 */
2439 2439 port->rbr_size = nxge_rbr_size;
2440 2440 port->rcr_size = nxge_rcr_size;
2441 2441
2442 2442 port->tx_dma_map = 0; /* Transmit DMA channel bit map */
2443 2443
2444 2444 nxge_set_rdc_intr_property(nxgep);
2445 2445
2446 2446 port->rcr_full_header = NXGE_RCR_FULL_HEADER;
2447 2447 port->rx_drr_weight = PT_DRR_WT_DEFAULT_10G;
2448 2448
2449 2449 /* ----------------------------------------------------- */
2450 2450 hardware = &port->hw_config;
2451 2451
2452 2452 (void) memset(hardware, 0, sizeof (*hardware));
2453 2453
2454 2454 /*
2455 2455 * partition_id, read_write_mode:
2456 2456 * dead variables.
2457 2457 */
2458 2458
2459 2459 /*
2460 2460 * drr_wt, rx_full_header, *_ldg?, start_mac_entry,
2461 2461 * mac_pref, def_mac_rxdma_grpid, start_vlan, max_vlans,
2462 2462 * start_ldgs, max_ldgs, max_ldvs,
2463 2463 * vlan_pref, def_vlan_rxdma_grpid are meaningful only
2464 2464 * in the service domain.
2465 2465 */
2466 2466
2467 2467 group = &port->rdc_grps[0];
2468 2468
2469 2469 group->flag = B_TRUE; /* configured */
2470 2470 group->config_method = RDC_TABLE_ENTRY_METHOD_REP;
2471 2471 group->port = NXGE_GET_PORT_NUM(nxgep->function_num);
2472 2472
2473 2473 /* HIO futures: this is still an open question. */
2474 2474 hardware->max_macs = 1;
2475 2475 }
2476 2476
2477 2477 static void
2478 2478 nxge_use_cfg_vlan_class_config(p_nxge_t nxgep)
2479 2479 {
2480 2480 uint_t vlan_cnt;
2481 2481 int *vlan_cfg_val;
2482 2482 int status;
2483 2483 p_nxge_param_t param_arr;
2484 2484 char *prop;
2485 2485
2486 2486 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " ==> nxge_use_cfg_vlan_config"));
2487 2487 param_arr = nxgep->param_arr;
2488 2488 prop = param_arr[param_vlan_2rdc_grp].fcode_name;
2489 2489
2490 2490 status = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, prop,
2491 2491 &vlan_cfg_val, &vlan_cnt);
2492 2492 if (status == DDI_PROP_SUCCESS) {
2493 2493 status = ddi_prop_update_int_array(DDI_DEV_T_NONE,
2494 2494 nxgep->dip, prop, vlan_cfg_val, vlan_cnt);
2495 2495 ddi_prop_free(vlan_cfg_val);
2496 2496 }
2497 2497 nxge_set_hw_vlan_class_config(nxgep);
2498 2498 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " <== nxge_use_cfg_vlan_config"));
2499 2499 }
2500 2500
2501 2501 static void
2502 2502 nxge_use_cfg_mac_class_config(p_nxge_t nxgep)
2503 2503 {
2504 2504 p_nxge_dma_pt_cfg_t p_dma_cfgp;
2505 2505 p_nxge_hw_pt_cfg_t p_cfgp;
2506 2506 uint_t mac_cnt;
2507 2507 int *mac_cfg_val;
2508 2508 int status;
2509 2509 p_nxge_param_t param_arr;
2510 2510 char *prop;
2511 2511
2512 2512 NXGE_DEBUG_MSG((nxgep, CFG_CTL, "==> nxge_use_cfg_mac_class_config"));
2513 2513 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
2514 2514 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config;
2515 2515 p_cfgp->start_mac_entry = 0;
2516 2516 param_arr = nxgep->param_arr;
2517 2517 prop = param_arr[param_mac_2rdc_grp].fcode_name;
2518 2518
2519 2519 switch (nxgep->function_num) {
2520 2520 case 0:
2521 2521 case 1:
2522 2522 /* 10G ports */
2523 2523 p_cfgp->max_macs = NXGE_MAX_MACS_XMACS;
2524 2524 break;
2525 2525 case 2:
2526 2526 case 3:
2527 2527 /* 1G ports */
2528 2528 default:
2529 2529 p_cfgp->max_macs = NXGE_MAX_MACS_BMACS;
2530 2530 break;
2531 2531 }
2532 2532
2533 2533 p_cfgp->mac_pref = 1;
2534 2534 NXGE_DEBUG_MSG((nxgep, OBP_CTL,
2535 2535 "== nxge_use_cfg_mac_class_config: "
2536 2536 " mac_pref bit set def_mac_rxdma_grpid %d",
2537 2537 p_cfgp->def_mac_rxdma_grpid));
2538 2538
2539 2539 status = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, prop,
2540 2540 &mac_cfg_val, &mac_cnt);
2541 2541 if (status == DDI_PROP_SUCCESS) {
2542 2542 if (mac_cnt <= p_cfgp->max_macs)
2543 2543 status = ddi_prop_update_int_array(DDI_DEV_T_NONE,
2544 2544 nxgep->dip, prop, mac_cfg_val, mac_cnt);
2545 2545 ddi_prop_free(mac_cfg_val);
2546 2546 }
2547 2547 nxge_set_hw_mac_class_config(nxgep);
2548 2548 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " <== nxge_use_cfg_mac_class_config"));
2549 2549 }
2550 2550
2551 2551 static void
2552 2552 nxge_use_cfg_class_config(p_nxge_t nxgep)
2553 2553 {
2554 2554 nxge_set_hw_class_config(nxgep);
2555 2555 }
2556 2556
2557 2557 static void
2558 2558 nxge_set_rdc_intr_property(p_nxge_t nxgep)
2559 2559 {
2560 2560 int i;
2561 2561 p_nxge_dma_pt_cfg_t p_dma_cfgp;
2562 2562
2563 2563 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " ==> nxge_set_rdc_intr_property"));
2564 2564 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
2565 2565
2566 2566 for (i = 0; i < NXGE_MAX_RDCS; i++) {
2567 2567 p_dma_cfgp->rcr_timeout[i] = nxgep->intr_timeout;
2568 2568 p_dma_cfgp->rcr_threshold[i] = nxgep->intr_threshold;
2569 2569 }
2570 2570
2571 2571 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " <== nxge_set_rdc_intr_property"));
2572 2572 }
2573 2573
2574 2574 static void
2575 2575 nxge_set_hw_dma_config(p_nxge_t nxgep)
2576 2576 {
2577 2577 int i, j, ngrps, bitmap, end, st_rdc;
2578 2578 p_nxge_dma_pt_cfg_t p_dma_cfgp;
2579 2579 p_nxge_hw_pt_cfg_t p_cfgp;
2580 2580 p_nxge_rdc_grp_t rdc_grp_p;
2581 2581 p_nxge_tdc_grp_t tdc_grp_p;
2582 2582 nxge_grp_t *group;
2583 2583 uint8_t nrdcs;
2584 2584 dc_map_t map = 0;
2585 2585
2586 2586 NXGE_DEBUG_MSG((nxgep, CFG_CTL, "==> nxge_set_hw_dma_config"));
2587 2587
2588 2588 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
2589 2589 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config;
2590 2590
2591 2591 switch (nxgep->niu_type) {
2592 2592 case NEPTUNE_4_1GC:
2593 2593 case NEPTUNE_2_10GF_2_1GC:
2594 2594 case NEPTUNE_1_10GF_3_1GC:
2595 2595 case NEPTUNE_1_1GC_1_10GF_2_1GC:
2596 2596 case NEPTUNE_2_10GF_2_1GRF:
2597 2597 default:
2598 2598 ngrps = 2;
2599 2599 break;
2600 2600 case NEPTUNE_2_10GF:
2601 2601 case NEPTUNE_2_1GRF:
2602 2602 case N2_NIU:
2603 2603 ngrps = 4;
2604 2604 break;
2605 2605 }
2606 2606
2607 2607 /*
2608 2608 * Setup TDC groups
2609 2609 */
2610 2610 bitmap = 0;
2611 2611 end = p_cfgp->tdc.start + p_cfgp->tdc.owned;
2612 2612 for (i = p_cfgp->tdc.start; i < end; i++) {
2613 2613 bitmap |= (1 << i);
2614 2614 }
2615 2615
2616 2616 nxgep->tx_set.owned.map |= bitmap; /* Owned, & not shared. */
2617 2617 nxgep->tx_set.owned.count = p_cfgp->tdc.owned;
2618 2618 p_dma_cfgp->tx_dma_map = bitmap;
2619 2619
2620 2620 for (i = 0; i < ngrps; i++) {
2621 2621 group = (nxge_grp_t *)nxge_grp_add(nxgep,
2622 2622 NXGE_TRANSMIT_GROUP);
2623 2623 tdc_grp_p = &p_dma_cfgp->tdc_grps[
2624 2624 p_cfgp->def_mac_txdma_grpid + i];
2625 2625 if (i == 0)
2626 2626 tdc_grp_p->map = bitmap;
2627 2627 else
2628 2628 tdc_grp_p->map = 0;
2629 2629 /* no ring is associated with a group initially */
2630 2630 tdc_grp_p->start_tdc = 0;
2631 2631 tdc_grp_p->max_tdcs = 0;
2632 2632 tdc_grp_p->grp_index = group->index;
2633 2633 }
2634 2634
2635 2635 /*
2636 2636 * Setup RDC groups
2637 2637 */
2638 2638 st_rdc = p_cfgp->start_rdc;
2639 2639 for (i = 0; i < ngrps; i++) {
2640 2640 /*
2641 2641 * All rings are associated with the default group initially
2642 2642 */
2643 2643 if (i == 0) {
2644 2644 /* default group */
2645 2645 switch (nxgep->niu_type) {
2646 2646 case NEPTUNE_4_1GC:
2647 2647 nrdcs = rx_4_1G[nxgep->function_num];
2648 2648 break;
2649 2649 case N2_NIU:
2650 2650 case NEPTUNE_2_10GF:
2651 2651 nrdcs = rx_2_10G[nxgep->function_num];
2652 2652 break;
2653 2653 case NEPTUNE_2_10GF_2_1GC:
2654 2654 nrdcs = rx_2_10G_2_1G[nxgep->function_num];
2655 2655 break;
2656 2656 case NEPTUNE_1_10GF_3_1GC:
2657 2657 nrdcs = rx_1_10G_3_1G[nxgep->function_num];
2658 2658 break;
2659 2659 case NEPTUNE_1_1GC_1_10GF_2_1GC:
2660 2660 nrdcs = rx_1_1G_1_10G_2_1G[nxgep->function_num];
2661 2661 break;
2662 2662 default:
2663 2663 switch (nxgep->platform_type) {
2664 2664 case P_NEPTUNE_ALONSO:
2665 2665 nrdcs =
2666 2666 rx_2_10G_2_1G[nxgep->function_num];
2667 2667 break;
2668 2668 default:
2669 2669 nrdcs = rx_4_1G[nxgep->function_num];
2670 2670 break;
2671 2671 }
2672 2672 break;
2673 2673 }
2674 2674
2675 2675 if (p_cfgp->max_rdcs < nrdcs)
2676 2676 nrdcs = p_cfgp->max_rdcs;
2677 2677 } else {
2678 2678 nrdcs = 0;
2679 2679 }
2680 2680
2681 2681 rdc_grp_p = &p_dma_cfgp->rdc_grps[
2682 2682 p_cfgp->def_mac_rxdma_grpid + i];
2683 2683 rdc_grp_p->start_rdc = st_rdc;
2684 2684 rdc_grp_p->max_rdcs = nrdcs;
2685 2685 rdc_grp_p->def_rdc = rdc_grp_p->start_rdc;
2686 2686
2687 2687 /* default to: 0, 1, 2, 3, ...., 0, 1, 2, 3.... */
2688 2688 if (nrdcs != 0) {
2689 2689 for (j = 0; j < nrdcs; j++) {
2690 2690 map |= (1 << j);
2691 2691 }
2692 2692 map <<= rdc_grp_p->start_rdc;
2693 2693 } else
2694 2694 map = 0;
2695 2695 rdc_grp_p->map = map;
2696 2696
2697 2697 nxgep->rx_set.owned.map |= map; /* Owned, & not shared. */
2698 2698 nxgep->rx_set.owned.count = nrdcs;
2699 2699
2700 2700 group = (nxge_grp_t *)nxge_grp_add(nxgep, NXGE_RECEIVE_GROUP);
2701 2701
2702 2702 rdc_grp_p->config_method = RDC_TABLE_ENTRY_METHOD_SEQ;
2703 2703 rdc_grp_p->flag = B_TRUE; /* This group has been configured. */
2704 2704 rdc_grp_p->grp_index = group->index;
2705 2705 rdc_grp_p->port = NXGE_GET_PORT_NUM(nxgep->function_num);
2706 2706
2707 2707 map = 0;
2708 2708 }
2709 2709
2710 2710
2711 2711 /* default RDC */
2712 2712 p_cfgp->def_rdc = p_cfgp->start_rdc;
2713 2713 nxgep->def_rdc = p_cfgp->start_rdc;
2714 2714
2715 2715 /* full 18 byte header ? */
2716 2716 p_dma_cfgp->rcr_full_header = NXGE_RCR_FULL_HEADER;
2717 2717 p_dma_cfgp->rx_drr_weight = PT_DRR_WT_DEFAULT_10G;
2718 2718 if (nxgep->function_num > 1)
2719 2719 p_dma_cfgp->rx_drr_weight = PT_DRR_WT_DEFAULT_1G;
2720 2720 p_dma_cfgp->rbr_size = nxge_rbr_size;
2721 2721 p_dma_cfgp->rcr_size = nxge_rcr_size;
2722 2722
2723 2723 nxge_set_rdc_intr_property(nxgep);
2724 2724 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " <== nxge_set_hw_dma_config"));
2725 2725 }
2726 2726
2727 2727 boolean_t
2728 2728 nxge_check_rxdma_port_member(p_nxge_t nxgep, uint8_t rdc)
2729 2729 {
2730 2730 p_nxge_dma_pt_cfg_t p_dma_cfgp;
2731 2731 p_nxge_hw_pt_cfg_t p_cfgp;
2732 2732 int status = B_TRUE;
2733 2733
2734 2734 NXGE_DEBUG_MSG((nxgep, CFG2_CTL, "==> nxge_check_rxdma_port_member"));
2735 2735
2736 2736 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
2737 2737 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config;
2738 2738
2739 2739 /* Receive DMA Channels */
2740 2740 if (rdc < p_cfgp->max_rdcs)
2741 2741 status = B_TRUE;
2742 2742 NXGE_DEBUG_MSG((nxgep, CFG2_CTL, " <== nxge_check_rxdma_port_member"));
2743 2743 return (status);
2744 2744 }
2745 2745
2746 2746 boolean_t
2747 2747 nxge_check_txdma_port_member(p_nxge_t nxgep, uint8_t tdc)
2748 2748 {
2749 2749 int status = B_FALSE;
2750 2750
2751 2751 NXGE_DEBUG_MSG((nxgep, CFG2_CTL, "==> nxge_check_txdma_port_member"));
2752 2752
2753 2753 if (tdc >= nxgep->pt_config.hw_config.tdc.start &&
2754 2754 tdc < nxgep->pt_config.hw_config.tdc.count)
2755 2755 status = B_TRUE;
2756 2756
2757 2757 NXGE_DEBUG_MSG((nxgep, CFG2_CTL, " <== nxge_check_txdma_port_member"));
2758 2758 return (status);
2759 2759 }
2760 2760
2761 2761 boolean_t
2762 2762 nxge_check_rxdma_rdcgrp_member(p_nxge_t nxgep, uint8_t rdc_grp, uint8_t rdc)
2763 2763 {
2764 2764 p_nxge_dma_pt_cfg_t p_dma_cfgp;
2765 2765 int status = B_TRUE;
2766 2766 p_nxge_rdc_grp_t rdc_grp_p;
2767 2767
2768 2768 NXGE_DEBUG_MSG((nxgep, CFG2_CTL,
2769 2769 " ==> nxge_check_rxdma_rdcgrp_member"));
2770 2770 NXGE_DEBUG_MSG((nxgep, CFG2_CTL, " nxge_check_rxdma_rdcgrp_member"
2771 2771 " rdc %d group %d", rdc, rdc_grp));
2772 2772 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
2773 2773
2774 2774 rdc_grp_p = &p_dma_cfgp->rdc_grps[rdc_grp];
2775 2775 NXGE_DEBUG_MSG((nxgep, CFG2_CTL, " max %d ", rdc_grp_p->max_rdcs));
2776 2776 if (rdc >= rdc_grp_p->max_rdcs) {
2777 2777 status = B_FALSE;
2778 2778 }
2779 2779 NXGE_DEBUG_MSG((nxgep, CFG2_CTL,
2780 2780 " <== nxge_check_rxdma_rdcgrp_member"));
2781 2781 return (status);
2782 2782 }
2783 2783
2784 2784 boolean_t
2785 2785 nxge_check_rdcgrp_port_member(p_nxge_t nxgep, uint8_t rdc_grp)
2786 2786 {
2787 2787 p_nxge_dma_pt_cfg_t p_dma_cfgp;
2788 2788 p_nxge_hw_pt_cfg_t p_cfgp;
2789 2789 int status = B_TRUE;
2790 2790
2791 2791 NXGE_DEBUG_MSG((nxgep, CFG2_CTL, "==> nxge_check_rdcgrp_port_member"));
2792 2792
2793 2793 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
2794 2794 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config;
2795 2795
2796 2796 if (rdc_grp >= p_cfgp->max_rdc_grpids)
2797 2797 status = B_FALSE;
2798 2798 NXGE_DEBUG_MSG((nxgep, CFG2_CTL, " <== nxge_check_rdcgrp_port_member"));
2799 2799 return (status);
2800 2800 }
2801 2801
2802 2802 static void
2803 2803 nxge_set_hw_vlan_class_config(p_nxge_t nxgep)
2804 2804 {
2805 2805 int i;
2806 2806 p_nxge_dma_pt_cfg_t p_dma_cfgp;
2807 2807 p_nxge_hw_pt_cfg_t p_cfgp;
2808 2808 p_nxge_param_t param_arr;
2809 2809 uint_t vlan_cnt;
2810 2810 int *vlan_cfg_val;
2811 2811 nxge_param_map_t *vmap;
2812 2812 char *prop;
2813 2813 p_nxge_class_pt_cfg_t p_class_cfgp;
2814 2814 uint32_t good_cfg[32];
2815 2815 int good_count = 0;
2816 2816 nxge_mv_cfg_t *vlan_tbl;
2817 2817
2818 2818 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " ==> nxge_set_hw_vlan_config"));
2819 2819 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
2820 2820 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config;
2821 2821 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config;
2822 2822
2823 2823 param_arr = nxgep->param_arr;
2824 2824 prop = param_arr[param_vlan_2rdc_grp].fcode_name;
2825 2825
2826 2826 /*
2827 2827 * By default, VLAN to RDC group mapping is disabled Need to read HW or
2828 2828 * .conf properties to find out if mapping is required
2829 2829 *
2830 2830 * Format
2831 2831 *
2832 2832 * uint32_t array, each array entry specifying the VLAN id and the
2833 2833 * mapping
2834 2834 *
2835 2835 * bit[30] = add bit[29] = remove bit[28] = preference bits[23-16] =
2836 2836 * rdcgrp bits[15-0] = VLAN ID ( )
2837 2837 */
2838 2838
2839 2839 for (i = 0; i < NXGE_MAX_VLANS; i++) {
2840 2840 p_class_cfgp->vlan_tbl[i].flag = 0;
2841 2841 }
2842 2842
2843 2843 vlan_tbl = (nxge_mv_cfg_t *)&p_class_cfgp->vlan_tbl[0];
2844 2844 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, prop,
2845 2845 &vlan_cfg_val, &vlan_cnt) == DDI_PROP_SUCCESS) {
2846 2846 for (i = 0; i < vlan_cnt; i++) {
2847 2847 vmap = (nxge_param_map_t *)&vlan_cfg_val[i];
2848 2848 if ((vmap->param_id) &&
2849 2849 (vmap->param_id < NXGE_MAX_VLANS) &&
2850 2850 (vmap->map_to <
2851 2851 p_cfgp->max_rdc_grpids) &&
2852 2852 (vmap->map_to >= (uint8_t)0)) {
2853 2853 NXGE_DEBUG_MSG((nxgep, CFG2_CTL,
2854 2854 " nxge_vlan_config mapping"
2855 2855 " id %d grp %d",
2856 2856 vmap->param_id, vmap->map_to));
2857 2857 good_cfg[good_count] = vlan_cfg_val[i];
2858 2858 if (vlan_tbl[vmap->param_id].flag == 0)
2859 2859 good_count++;
2860 2860 vlan_tbl[vmap->param_id].flag = 1;
2861 2861 vlan_tbl[vmap->param_id].rdctbl =
2862 2862 vmap->map_to + p_cfgp->def_mac_rxdma_grpid;
2863 2863 vlan_tbl[vmap->param_id].mpr_npr = vmap->pref;
2864 2864 }
2865 2865 }
2866 2866 ddi_prop_free(vlan_cfg_val);
2867 2867 if (good_count != vlan_cnt) {
2868 2868 (void) ddi_prop_update_int_array(DDI_DEV_T_NONE,
2869 2869 nxgep->dip, prop, (int *)good_cfg, good_count);
2870 2870 }
2871 2871 }
2872 2872 NXGE_DEBUG_MSG((nxgep, CFG_CTL, "<== nxge_set_hw_vlan_config"));
2873 2873 }
2874 2874
2875 2875 static void
2876 2876 nxge_set_hw_mac_class_config(p_nxge_t nxgep)
2877 2877 {
2878 2878 int i;
2879 2879 p_nxge_dma_pt_cfg_t p_dma_cfgp;
2880 2880 p_nxge_hw_pt_cfg_t p_cfgp;
2881 2881 p_nxge_param_t param_arr;
2882 2882 uint_t mac_cnt;
2883 2883 int *mac_cfg_val;
2884 2884 nxge_param_map_t *mac_map;
2885 2885 char *prop;
2886 2886 p_nxge_class_pt_cfg_t p_class_cfgp;
2887 2887 int good_count = 0;
2888 2888 int good_cfg[NXGE_MAX_MACS];
2889 2889 nxge_mv_cfg_t *mac_host_info;
2890 2890
2891 2891 NXGE_DEBUG_MSG((nxgep, CFG_CTL, "==> nxge_set_hw_mac_config"));
2892 2892
2893 2893 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
2894 2894 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config;
2895 2895 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config;
2896 2896 mac_host_info = (nxge_mv_cfg_t *)&p_class_cfgp->mac_host_info[0];
2897 2897
2898 2898 param_arr = nxgep->param_arr;
2899 2899 prop = param_arr[param_mac_2rdc_grp].fcode_name;
2900 2900
2901 2901 for (i = 0; i < NXGE_MAX_MACS; i++) {
2902 2902 p_class_cfgp->mac_host_info[i].flag = 0;
2903 2903 p_class_cfgp->mac_host_info[i].rdctbl =
2904 2904 p_cfgp->def_mac_rxdma_grpid;
2905 2905 }
2906 2906
2907 2907 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, prop,
2908 2908 &mac_cfg_val, &mac_cnt) == DDI_PROP_SUCCESS) {
2909 2909 for (i = 0; i < mac_cnt; i++) {
2910 2910 mac_map = (nxge_param_map_t *)&mac_cfg_val[i];
2911 2911 if ((mac_map->param_id < p_cfgp->max_macs) &&
2912 2912 (mac_map->map_to <
2913 2913 p_cfgp->max_rdc_grpids) &&
2914 2914 (mac_map->map_to >= (uint8_t)0)) {
2915 2915 NXGE_DEBUG_MSG((nxgep, CFG2_CTL,
2916 2916 " nxge_mac_config mapping"
2917 2917 " id %d grp %d",
2918 2918 mac_map->param_id, mac_map->map_to));
2919 2919 mac_host_info[mac_map->param_id].mpr_npr =
2920 2920 p_cfgp->mac_pref;
2921 2921 mac_host_info[mac_map->param_id].rdctbl =
2922 2922 mac_map->map_to +
2923 2923 p_cfgp->def_mac_rxdma_grpid;
2924 2924 good_cfg[good_count] = mac_cfg_val[i];
2925 2925 if (mac_host_info[mac_map->param_id].flag == 0)
2926 2926 good_count++;
2927 2927 mac_host_info[mac_map->param_id].flag = 1;
2928 2928 }
2929 2929 }
2930 2930 ddi_prop_free(mac_cfg_val);
2931 2931 if (good_count != mac_cnt) {
2932 2932 (void) ddi_prop_update_int_array(DDI_DEV_T_NONE,
2933 2933 nxgep->dip, prop, good_cfg, good_count);
2934 2934 }
2935 2935 }
2936 2936 NXGE_DEBUG_MSG((nxgep, CFG_CTL, "<== nxge_set_hw_mac_config"));
2937 2937 }
2938 2938
2939 2939 static void
2940 2940 nxge_set_hw_class_config(p_nxge_t nxgep)
2941 2941 {
2942 2942 int i;
2943 2943 p_nxge_param_t param_arr;
2944 2944 int *int_prop_val;
2945 2945 uint32_t cfg_value;
2946 2946 char *prop;
2947 2947 p_nxge_class_pt_cfg_t p_class_cfgp;
2948 2948 int start_prop, end_prop;
2949 2949 uint_t prop_cnt;
2950 2950 int start_class, j = 0;
2951 2951
2952 2952 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " ==> nxge_set_hw_class_config"));
2953 2953
2954 2954 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config;
2955 2955 param_arr = nxgep->param_arr;
2956 2956 start_prop = param_class_opt_ipv4_tcp;
2957 2957 end_prop = param_class_opt_ipv6_sctp;
2958 2958 start_class = TCAM_CLASS_TCP_IPV4;
2959 2959
2960 2960 for (i = start_prop, j = 0; i <= end_prop; i++, j++) {
2961 2961 prop = param_arr[i].fcode_name;
2962 2962 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip,
2963 2963 0, prop, &int_prop_val,
2964 2964 &prop_cnt) == DDI_PROP_SUCCESS) {
2965 2965 cfg_value = (uint32_t)*int_prop_val;
2966 2966 ddi_prop_free(int_prop_val);
2967 2967 } else {
2968 2968 cfg_value = (uint32_t)param_arr[i].value;
2969 2969 }
2970 2970 p_class_cfgp->class_cfg[start_class + j] = cfg_value;
2971 2971 }
2972 2972
2973 2973 prop = param_arr[param_h1_init_value].fcode_name;
2974 2974
2975 2975 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, prop,
2976 2976 &int_prop_val, &prop_cnt) == DDI_PROP_SUCCESS) {
2977 2977 cfg_value = (uint32_t)*int_prop_val;
2978 2978 ddi_prop_free(int_prop_val);
2979 2979 } else {
2980 2980 cfg_value = (uint32_t)param_arr[param_h1_init_value].value;
2981 2981 }
2982 2982
2983 2983 p_class_cfgp->init_h1 = (uint32_t)cfg_value;
2984 2984 prop = param_arr[param_h2_init_value].fcode_name;
2985 2985
2986 2986 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, prop,
2987 2987 &int_prop_val, &prop_cnt) == DDI_PROP_SUCCESS) {
2988 2988 cfg_value = (uint32_t)*int_prop_val;
2989 2989 ddi_prop_free(int_prop_val);
2990 2990 } else {
2991 2991 cfg_value = (uint32_t)param_arr[param_h2_init_value].value;
2992 2992 }
2993 2993
2994 2994 p_class_cfgp->init_h2 = (uint16_t)cfg_value;
2995 2995 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " <== nxge_set_hw_class_config"));
2996 2996 }
2997 2997
2998 2998 nxge_status_t
2999 2999 nxge_ldgv_init_n2(p_nxge_t nxgep, int *navail_p, int *nrequired_p)
3000 3000 {
3001 3001 int i, maxldvs, maxldgs, nldvs;
3002 3002 int ldv, endldg;
3003 3003 uint8_t func;
3004 3004 uint8_t channel;
3005 3005 uint8_t chn_start;
3006 3006 boolean_t own_sys_err = B_FALSE, own_fzc = B_FALSE;
3007 3007 p_nxge_dma_pt_cfg_t p_dma_cfgp;
3008 3008 p_nxge_hw_pt_cfg_t p_cfgp;
3009 3009 p_nxge_ldgv_t ldgvp;
3010 3010 p_nxge_ldg_t ldgp, ptr;
3011 3011 p_nxge_ldv_t ldvp, sysldvp;
3012 3012 nxge_status_t status = NXGE_OK;
3013 3013 nxge_grp_set_t *set;
3014 3014
3015 3015 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_ldgv_init_n2"));
3016 3016 if (!*navail_p) {
3017 3017 *nrequired_p = 0;
3018 3018 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
3019 3019 "<== nxge_ldgv_init:no avail"));
3020 3020 return (NXGE_ERROR);
3021 3021 }
3022 3022 /*
3023 3023 * N2/NIU: one logical device owns one logical group. and each
3024 3024 * device/group will be assigned one vector by Hypervisor.
3025 3025 */
3026 3026 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
3027 3027 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config;
3028 3028 maxldgs = p_cfgp->max_ldgs;
3029 3029 if (!maxldgs) {
3030 3030 /* No devices configured. */
3031 3031 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "<== nxge_ldgv_init_n2: "
3032 3032 "no logical groups configured."));
3033 3033 return (NXGE_ERROR);
3034 3034 } else {
3035 3035 maxldvs = maxldgs + 1;
3036 3036 }
3037 3037
3038 3038 /*
3039 3039 * If function zero instance, it needs to handle the system and MIF
3040 3040 * error interrupts. MIF interrupt may not be needed for N2/NIU.
3041 3041 */
3042 3042 func = nxgep->function_num;
3043 3043 if (func == 0) {
3044 3044 own_sys_err = B_TRUE;
3045 3045 if (!p_cfgp->ser_ldvid) {
3046 3046 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
3047 3047 "nxge_ldgv_init_n2: func 0, ERR ID not set!"));
3048 3048 }
3049 3049 /* MIF interrupt */
3050 3050 if (!p_cfgp->mif_ldvid) {
3051 3051 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
3052 3052 "nxge_ldgv_init_n2: func 0, MIF ID not set!"));
3053 3053 }
3054 3054 }
3055 3055
3056 3056 /*
3057 3057 * Assume single partition, each function owns mac.
3058 3058 */
3059 3059 if (!nxge_use_partition)
3060 3060 own_fzc = B_TRUE;
3061 3061
3062 3062 ldgvp = nxgep->ldgvp;
3063 3063 if (ldgvp == NULL) {
3064 3064 ldgvp = KMEM_ZALLOC(sizeof (nxge_ldgv_t), KM_SLEEP);
3065 3065 nxgep->ldgvp = ldgvp;
3066 3066 ldgvp->maxldgs = (uint8_t)maxldgs;
3067 3067 ldgvp->maxldvs = (uint8_t)maxldvs;
3068 3068 ldgp = ldgvp->ldgp = KMEM_ZALLOC(
3069 3069 sizeof (nxge_ldg_t) * maxldgs, KM_SLEEP);
3070 3070 ldvp = ldgvp->ldvp = KMEM_ZALLOC(
3071 3071 sizeof (nxge_ldv_t) * maxldvs, KM_SLEEP);
3072 3072 } else {
3073 3073 ldgp = ldgvp->ldgp;
3074 3074 ldvp = ldgvp->ldvp;
3075 3075 }
3076 3076
3077 3077 ldgvp->ndma_ldvs = p_cfgp->tdc.owned + p_cfgp->max_rdcs;
3078 3078 ldgvp->tmres = NXGE_TIMER_RESO;
3079 3079
3080 3080 NXGE_DEBUG_MSG((nxgep, INT_CTL,
3081 3081 "==> nxge_ldgv_init_n2: maxldvs %d maxldgs %d",
3082 3082 maxldvs, maxldgs));
3083 3083
3084 3084 /* logical start_ldg is ldv */
3085 3085 ptr = ldgp;
3086 3086 for (i = 0; i < maxldgs; i++) {
3087 3087 ptr->func = func;
3088 3088 ptr->arm = B_TRUE;
3089 3089 ptr->vldg_index = (uint8_t)i;
3090 3090 ptr->ldg_timer = NXGE_TIMER_LDG;
3091 3091 ptr->ldg = p_cfgp->ldg[i];
3092 3092 ptr->sys_intr_handler = nxge_intr;
3093 3093 ptr->nldvs = 0;
3094 3094 ptr->ldvp = NULL;
3095 3095 ptr->nxgep = nxgep;
3096 3096 NXGE_DEBUG_MSG((nxgep, INT_CTL,
3097 3097 "==> nxge_ldgv_init_n2: maxldvs %d maxldgs %d "
3098 3098 "ldg %d ldgptr $%p",
3099 3099 maxldvs, maxldgs, ptr->ldg, ptr));
3100 3100 ptr++;
3101 3101 }
3102 3102
3103 3103 endldg = NXGE_INT_MAX_LDG;
3104 3104 nldvs = 0;
3105 3105 ldgvp->nldvs = 0;
3106 3106 ldgp->ldvp = NULL;
3107 3107 *nrequired_p = 0;
3108 3108
3109 3109 /*
3110 3110 * logical device group table is organized in the following order (same
3111 3111 * as what interrupt property has). function 0: owns MAC, MIF, error,
3112 3112 * rx, tx. function 1: owns MAC, rx, tx.
3113 3113 */
3114 3114
3115 3115 if (own_fzc && p_cfgp->mac_ldvid) {
3116 3116 /* Each function should own MAC interrupt */
3117 3117 ldv = p_cfgp->mac_ldvid;
3118 3118 ldvp->ldv = (uint8_t)ldv;
3119 3119 ldvp->is_mac = B_TRUE;
3120 3120 ldvp->ldv_intr_handler = nxge_mac_intr;
3121 3121 ldvp->ldv_ldf_masks = 0;
3122 3122 ldvp->nxgep = nxgep;
3123 3123 NXGE_DEBUG_MSG((nxgep, INT_CTL,
3124 3124 "==> nxge_ldgv_init_n2(mac): maxldvs %d ldv %d "
3125 3125 "ldg %d ldgptr $%p ldvptr $%p",
3126 3126 maxldvs, ldv, ldgp->ldg, ldgp, ldvp));
3127 3127 nxge_ldgv_setup(&ldgp, &ldvp, ldv, endldg, nrequired_p);
3128 3128 nldvs++;
3129 3129 }
3130 3130
3131 3131 if (own_fzc && p_cfgp->mif_ldvid) {
3132 3132 ldv = p_cfgp->mif_ldvid;
3133 3133 ldvp->ldv = (uint8_t)ldv;
3134 3134 ldvp->is_mif = B_TRUE;
3135 3135 ldvp->ldv_intr_handler = nxge_mif_intr;
3136 3136 ldvp->ldv_ldf_masks = 0;
3137 3137 ldvp->nxgep = nxgep;
3138 3138 NXGE_DEBUG_MSG((nxgep, INT_CTL,
3139 3139 "==> nxge_ldgv_init_n2(mif): maxldvs %d ldv %d "
3140 3140 "ldg %d ldgptr $%p ldvptr $%p",
3141 3141 maxldvs, ldv, ldgp->ldg, ldgp, ldvp));
3142 3142 nxge_ldgv_setup(&ldgp, &ldvp, ldv, endldg, nrequired_p);
3143 3143 nldvs++;
3144 3144 }
3145 3145
3146 3146 /*
3147 3147 * HW based syserr interrupt for port0, and SW based syserr interrupt
3148 3148 * for port1
3149 3149 */
3150 3150 if (own_sys_err && p_cfgp->ser_ldvid) {
3151 3151 ldv = p_cfgp->ser_ldvid;
3152 3152 /*
3153 3153 * Unmask the system interrupt states.
3154 3154 */
3155 3155 (void) nxge_fzc_sys_err_mask_set(nxgep, SYS_ERR_SMX_MASK |
3156 3156 SYS_ERR_IPP_MASK | SYS_ERR_TXC_MASK |
3157 3157 SYS_ERR_ZCP_MASK);
3158 3158
3159 3159 ldvp->use_timer = B_TRUE;
3160 3160 ldvp->ldv = (uint8_t)ldv;
3161 3161 ldvp->is_syserr = B_TRUE;
3162 3162 ldvp->ldv_intr_handler = nxge_syserr_intr;
3163 3163 ldvp->ldv_ldf_masks = 0;
3164 3164 ldvp->nxgep = nxgep;
3165 3165 ldgvp->ldvp_syserr = ldvp;
3166 3166
3167 3167 NXGE_DEBUG_MSG((nxgep, INT_CTL,
3168 3168 "==> nxge_ldgv_init_n2(syserr): maxldvs %d ldv %d "
3169 3169 "ldg %d ldgptr $%p ldvptr p%p",
3170 3170 maxldvs, ldv, ldgp->ldg, ldgp, ldvp));
3171 3171 nxge_ldgv_setup(&ldgp, &ldvp, ldv, endldg, nrequired_p);
3172 3172 nldvs++;
3173 3173 } else {
3174 3174 /*
3175 3175 * SW based: allocate the ldv for the syserr since the vector
3176 3176 * should not be consumed for port1
3177 3177 */
3178 3178 sysldvp = KMEM_ZALLOC(sizeof (nxge_ldv_t), KM_SLEEP);
3179 3179 sysldvp->use_timer = B_TRUE;
3180 3180 sysldvp->ldv = NXGE_SYS_ERROR_LD;
3181 3181 sysldvp->is_syserr = B_TRUE;
3182 3182 sysldvp->ldv_intr_handler = nxge_syserr_intr;
3183 3183 sysldvp->ldv_ldf_masks = 0;
3184 3184 sysldvp->nxgep = nxgep;
3185 3185 ldgvp->ldvp_syserr = sysldvp;
3186 3186 ldgvp->ldvp_syserr_alloced = B_TRUE;
3187 3187 }
3188 3188
3189 3189
3190 3190 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_ldgv_init_n2: "
3191 3191 "(before rx) func %d nldvs %d navail %d nrequired %d",
3192 3192 func, nldvs, *navail_p, *nrequired_p));
3193 3193
3194 3194 /*
3195 3195 * Start with RDC to configure logical devices for each group.
3196 3196 */
3197 3197 chn_start = p_cfgp->ldg_chn_start;
3198 3198 set = &nxgep->rx_set;
3199 3199 for (channel = 0; channel < NXGE_MAX_RDCS; channel++) {
3200 3200 if ((1 << channel) & set->owned.map) {
3201 3201 ldvp->is_rxdma = B_TRUE;
3202 3202 ldvp->ldv = (uint8_t)channel + NXGE_RDMA_LD_START;
3203 3203 ldvp->channel = channel;
3204 3204 ldvp->vdma_index = (uint8_t)channel;
3205 3205 ldvp->ldv_intr_handler = nxge_rx_intr;
3206 3206 ldvp->ldv_ldf_masks = 0;
3207 3207 ldvp->nxgep = nxgep;
3208 3208 ldgp->ldg = p_cfgp->ldg[chn_start];
3209 3209
3210 3210 NXGE_DEBUG_MSG((nxgep, INT_CTL,
3211 3211 "==> nxge_ldgv_init_n2(rx%d): maxldvs %d ldv %d "
3212 3212 "ldg %d ldgptr 0x%016llx ldvptr 0x%016llx",
3213 3213 i, maxldvs, ldv, ldgp->ldg, ldgp, ldvp));
3214 3214 nxge_ldgv_setup(&ldgp, &ldvp, ldvp->ldv,
3215 3215 endldg, nrequired_p);
3216 3216 nldvs++;
3217 3217 chn_start++;
3218 3218 }
3219 3219 }
3220 3220
3221 3221 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_ldgv_init_n2: "
3222 3222 "func %d nldvs %d navail %d nrequired %d",
3223 3223 func, nldvs, *navail_p, *nrequired_p));
3224 3224
3225 3225 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_ldgv_init_n2: "
3226 3226 "func %d nldvs %d navail %d nrequired %d ldgp 0x%llx "
3227 3227 "ldvp 0x%llx",
3228 3228 func, nldvs, *navail_p, *nrequired_p, ldgp, ldvp));
3229 3229 /*
3230 3230 * Transmit DMA channels.
3231 3231 */
3232 3232 chn_start = p_cfgp->ldg_chn_start + 8;
3233 3233 set = &nxgep->tx_set;
3234 3234 for (channel = 0; channel < NXGE_MAX_TDCS; channel++) {
3235 3235 if ((1 << channel) & set->owned.map) {
3236 3236 ldvp->is_txdma = B_TRUE;
3237 3237 ldvp->ldv = (uint8_t)channel + NXGE_TDMA_LD_START;
3238 3238 ldvp->channel = channel;
3239 3239 ldvp->vdma_index = (uint8_t)channel;
3240 3240 ldvp->ldv_intr_handler = nxge_tx_intr;
3241 3241 ldvp->ldv_ldf_masks = 0;
3242 3242 ldgp->ldg = p_cfgp->ldg[chn_start];
3243 3243 ldvp->nxgep = nxgep;
3244 3244 NXGE_DEBUG_MSG((nxgep, INT_CTL,
3245 3245 "==> nxge_ldgv_init_n2(tx%d): maxldvs %d ldv %d "
3246 3246 "ldg %d ldgptr %p ldvptr %p",
3247 3247 channel, maxldvs, ldv, ldgp->ldg, ldgp, ldvp));
3248 3248 nxge_ldgv_setup(&ldgp, &ldvp, ldvp->ldv,
3249 3249 endldg, nrequired_p);
3250 3250 nldvs++;
3251 3251 chn_start++;
3252 3252 }
3253 3253 }
3254 3254
3255 3255 ldgvp->ldg_intrs = *nrequired_p;
3256 3256 ldgvp->nldvs = (uint8_t)nldvs;
3257 3257
3258 3258 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_ldgv_init_n2: "
3259 3259 "func %d nldvs %d maxgrps %d navail %d nrequired %d",
3260 3260 func, nldvs, maxldgs, *navail_p, *nrequired_p));
3261 3261
3262 3262 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_ldgv_init_n2"));
3263 3263 return (status);
3264 3264 }
3265 3265
3266 3266 /*
3267 3267 * Interrupts related interface functions.
3268 3268 */
3269 3269
3270 3270 nxge_status_t
3271 3271 nxge_ldgv_init(p_nxge_t nxgep, int *navail_p, int *nrequired_p)
3272 3272 {
3273 3273 int i, maxldvs, maxldgs, nldvs;
3274 3274 int ldv, ldg, endldg, ngrps;
3275 3275 uint8_t func;
3276 3276 uint8_t channel;
3277 3277 boolean_t own_sys_err = B_FALSE, own_fzc = B_FALSE;
3278 3278 p_nxge_dma_pt_cfg_t p_dma_cfgp;
3279 3279 p_nxge_hw_pt_cfg_t p_cfgp;
3280 3280 p_nxge_ldgv_t ldgvp;
3281 3281 p_nxge_ldg_t ldgp, ptr;
3282 3282 p_nxge_ldv_t ldvp;
3283 3283 nxge_grp_set_t *set;
3284 3284
3285 3285 nxge_status_t status = NXGE_OK;
3286 3286
3287 3287 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_ldgv_init"));
3288 3288 if (!*navail_p) {
3289 3289 *nrequired_p = 0;
3290 3290 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
3291 3291 "<== nxge_ldgv_init:no avail"));
3292 3292 return (NXGE_ERROR);
3293 3293 }
3294 3294 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config;
3295 3295 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config;
3296 3296
3297 3297 nldvs = p_cfgp->tdc.owned + p_cfgp->max_rdcs;
3298 3298
3299 3299 /*
3300 3300 * If function zero instance, it needs to handle the system error
3301 3301 * interrupts.
3302 3302 */
3303 3303 func = nxgep->function_num;
3304 3304 if (func == 0) {
3305 3305 nldvs++;
3306 3306 own_sys_err = B_TRUE;
3307 3307 } else {
3308 3308 /* use timer */
3309 3309 nldvs++;
3310 3310 }
3311 3311
3312 3312 /*
3313 3313 * Assume single partition, each function owns mac.
3314 3314 */
3315 3315 if (!nxge_use_partition) {
3316 3316 /* mac */
3317 3317 nldvs++;
3318 3318 /* MIF */
3319 3319 nldvs++;
3320 3320 own_fzc = B_TRUE;
3321 3321 }
3322 3322 maxldvs = nldvs;
3323 3323 maxldgs = p_cfgp->max_ldgs;
3324 3324 if (!maxldvs || !maxldgs) {
3325 3325 /* No devices configured. */
3326 3326 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "<== nxge_ldgv_init: "
3327 3327 "no logical devices or groups configured."));
3328 3328 return (NXGE_ERROR);
3329 3329 }
3330 3330 ldgvp = nxgep->ldgvp;
3331 3331 if (ldgvp == NULL) {
3332 3332 ldgvp = KMEM_ZALLOC(sizeof (nxge_ldgv_t), KM_SLEEP);
3333 3333 nxgep->ldgvp = ldgvp;
3334 3334 ldgvp->maxldgs = (uint8_t)maxldgs;
3335 3335 ldgvp->maxldvs = (uint8_t)maxldvs;
3336 3336 ldgp = ldgvp->ldgp = KMEM_ZALLOC(sizeof (nxge_ldg_t) * maxldgs,
3337 3337 KM_SLEEP);
3338 3338 ldvp = ldgvp->ldvp = KMEM_ZALLOC(sizeof (nxge_ldv_t) * maxldvs,
3339 3339 KM_SLEEP);
3340 3340 }
3341 3341 ldgvp->ndma_ldvs = p_cfgp->tdc.owned + p_cfgp->max_rdcs;
3342 3342 ldgvp->tmres = NXGE_TIMER_RESO;
3343 3343
3344 3344 NXGE_DEBUG_MSG((nxgep, INT_CTL,
3345 3345 "==> nxge_ldgv_init: maxldvs %d maxldgs %d nldvs %d",
3346 3346 maxldvs, maxldgs, nldvs));
3347 3347 ldg = p_cfgp->start_ldg;
3348 3348 ptr = ldgp;
3349 3349 for (i = 0; i < maxldgs; i++) {
3350 3350 ptr->func = func;
3351 3351 ptr->arm = B_TRUE;
3352 3352 ptr->vldg_index = (uint8_t)i;
3353 3353 ptr->ldg_timer = NXGE_TIMER_LDG;
3354 3354 ptr->ldg = ldg++;
3355 3355 ptr->sys_intr_handler = nxge_intr;
3356 3356 ptr->nldvs = 0;
3357 3357 ptr->nxgep = nxgep;
3358 3358 NXGE_DEBUG_MSG((nxgep, INT_CTL,
3359 3359 "==> nxge_ldgv_init: maxldvs %d maxldgs %d ldg %d",
3360 3360 maxldvs, maxldgs, ptr->ldg));
3361 3361 ptr++;
3362 3362 }
3363 3363
3364 3364 ldg = p_cfgp->start_ldg;
3365 3365 if (maxldgs > *navail_p) {
3366 3366 ngrps = *navail_p;
3367 3367 } else {
3368 3368 ngrps = maxldgs;
3369 3369 }
3370 3370 endldg = ldg + ngrps;
3371 3371
3372 3372 /*
3373 3373 * Receive DMA channels.
3374 3374 */
3375 3375 nldvs = 0;
3376 3376 ldgvp->nldvs = 0;
3377 3377 ldgp->ldvp = NULL;
3378 3378 *nrequired_p = 0;
3379 3379
3380 3380 /*
3381 3381 * Start with RDC to configure logical devices for each group.
3382 3382 */
3383 3383 set = &nxgep->rx_set;
3384 3384 for (channel = 0; channel < NXGE_MAX_RDCS; channel++) {
3385 3385 if ((1 << channel) & set->owned.map) {
3386 3386 /* For now, <channel & <vdma_index> are the same. */
3387 3387 ldvp->is_rxdma = B_TRUE;
3388 3388 ldvp->ldv = (uint8_t)channel + NXGE_RDMA_LD_START;
3389 3389 ldvp->channel = channel;
3390 3390 ldvp->vdma_index = (uint8_t)channel;
3391 3391 ldvp->ldv_intr_handler = nxge_rx_intr;
3392 3392 ldvp->ldv_ldf_masks = 0;
3393 3393 ldvp->use_timer = B_FALSE;
3394 3394 ldvp->nxgep = nxgep;
3395 3395 nxge_ldgv_setup(&ldgp, &ldvp, ldvp->ldv,
3396 3396 endldg, nrequired_p);
3397 3397 nldvs++;
3398 3398 }
3399 3399 }
3400 3400
3401 3401 /*
3402 3402 * Transmit DMA channels.
3403 3403 */
3404 3404 set = &nxgep->tx_set;
3405 3405 for (channel = 0; channel < NXGE_MAX_TDCS; channel++) {
3406 3406 if ((1 << channel) & set->owned.map) {
3407 3407 /* For now, <channel & <vdma_index> are the same. */
3408 3408 ldvp->is_txdma = B_TRUE;
3409 3409 ldvp->ldv = (uint8_t)channel + NXGE_TDMA_LD_START;
3410 3410 ldvp->channel = channel;
3411 3411 ldvp->vdma_index = (uint8_t)channel;
3412 3412 ldvp->ldv_intr_handler = nxge_tx_intr;
3413 3413 ldvp->ldv_ldf_masks = 0;
3414 3414 ldvp->use_timer = B_FALSE;
3415 3415 ldvp->nxgep = nxgep;
3416 3416 nxge_ldgv_setup(&ldgp, &ldvp, ldvp->ldv,
3417 3417 endldg, nrequired_p);
3418 3418 nldvs++;
3419 3419 }
3420 3420 }
3421 3421
3422 3422 if (own_fzc) {
3423 3423 ldv = NXGE_MIF_LD;
3424 3424 ldvp->ldv = (uint8_t)ldv;
3425 3425 ldvp->is_mif = B_TRUE;
3426 3426 ldvp->ldv_intr_handler = nxge_mif_intr;
3427 3427 ldvp->ldv_ldf_masks = 0;
3428 3428 ldvp->use_timer = B_FALSE;
3429 3429 ldvp->nxgep = nxgep;
3430 3430 nxge_ldgv_setup(&ldgp, &ldvp, ldv, endldg, nrequired_p);
3431 3431 nldvs++;
3432 3432 }
3433 3433 /*
3434 3434 * MAC port (function zero control)
3435 3435 */
3436 3436 if (own_fzc) {
3437 3437 ldvp->is_mac = B_TRUE;
3438 3438 ldvp->ldv_intr_handler = nxge_mac_intr;
3439 3439 ldvp->ldv_ldf_masks = 0;
3440 3440 ldv = func + NXGE_MAC_LD_START;
3441 3441 ldvp->ldv = (uint8_t)ldv;
3442 3442 ldvp->use_timer = B_FALSE;
3443 3443 ldvp->nxgep = nxgep;
3444 3444 nxge_ldgv_setup(&ldgp, &ldvp, ldv, endldg, nrequired_p);
3445 3445 nldvs++;
3446 3446 }
3447 3447 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_ldgv_init: "
3448 3448 "func %d nldvs %d navail %d nrequired %d",
3449 3449 func, nldvs, *navail_p, *nrequired_p));
3450 3450 /*
3451 3451 * Function 0 owns system error interrupts.
3452 3452 */
3453 3453 ldvp->use_timer = B_TRUE;
3454 3454 if (own_sys_err) {
3455 3455 ldv = NXGE_SYS_ERROR_LD;
3456 3456 ldvp->ldv = (uint8_t)ldv;
3457 3457 ldvp->is_syserr = B_TRUE;
3458 3458 ldvp->ldv_intr_handler = nxge_syserr_intr;
3459 3459 ldvp->ldv_ldf_masks = 0;
3460 3460 ldvp->nxgep = nxgep;
3461 3461 ldgvp->ldvp_syserr = ldvp;
3462 3462 /*
3463 3463 * Unmask the system interrupt states.
3464 3464 */
3465 3465 (void) nxge_fzc_sys_err_mask_set(nxgep, SYS_ERR_SMX_MASK |
3466 3466 SYS_ERR_IPP_MASK | SYS_ERR_TXC_MASK |
3467 3467 SYS_ERR_ZCP_MASK);
3468 3468
3469 3469 (void) nxge_ldgv_setup(&ldgp, &ldvp, ldv, endldg, nrequired_p);
3470 3470 nldvs++;
3471 3471 } else {
3472 3472 ldv = NXGE_SYS_ERROR_LD;
3473 3473 ldvp->ldv = (uint8_t)ldv;
3474 3474 ldvp->is_syserr = B_TRUE;
3475 3475 ldvp->ldv_intr_handler = nxge_syserr_intr;
3476 3476 ldvp->nxgep = nxgep;
3477 3477 ldvp->ldv_ldf_masks = 0;
3478 3478 ldgvp->ldvp_syserr = ldvp;
3479 3479 }
3480 3480
3481 3481 ldgvp->ldg_intrs = *nrequired_p;
3482 3482
3483 3483 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_ldgv_init: "
3484 3484 "func %d nldvs %d navail %d nrequired %d",
3485 3485 func, nldvs, *navail_p, *nrequired_p));
3486 3486
3487 3487 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_ldgv_init"));
3488 3488 return (status);
3489 3489 }
3490 3490
3491 3491 nxge_status_t
3492 3492 nxge_ldgv_uninit(p_nxge_t nxgep)
3493 3493 {
3494 3494 p_nxge_ldgv_t ldgvp;
3495 3495
3496 3496 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_ldgv_uninit"));
3497 3497 ldgvp = nxgep->ldgvp;
3498 3498 if (ldgvp == NULL) {
3499 3499 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "<== nxge_ldgv_uninit: "
3500 3500 "no logical group configured."));
3501 3501 return (NXGE_OK);
3502 3502 }
3503 3503 if (ldgvp->ldvp_syserr_alloced == B_TRUE) {
3504 3504 KMEM_FREE(ldgvp->ldvp_syserr, sizeof (nxge_ldv_t));
3505 3505 }
3506 3506 if (ldgvp->ldgp) {
3507 3507 KMEM_FREE(ldgvp->ldgp, sizeof (nxge_ldg_t) * ldgvp->maxldgs);
3508 3508 }
3509 3509 if (ldgvp->ldvp) {
3510 3510 KMEM_FREE(ldgvp->ldvp, sizeof (nxge_ldv_t) * ldgvp->maxldvs);
3511 3511 }
3512 3512 KMEM_FREE(ldgvp, sizeof (nxge_ldgv_t));
3513 3513 nxgep->ldgvp = NULL;
3514 3514
3515 3515 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_ldgv_uninit"));
3516 3516 return (NXGE_OK);
3517 3517 }
3518 3518
3519 3519 nxge_status_t
3520 3520 nxge_intr_ldgv_init(p_nxge_t nxgep)
3521 3521 {
3522 3522 nxge_status_t status = NXGE_OK;
3523 3523
3524 3524 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr_ldgv_init"));
3525 3525 /*
3526 3526 * Configure the logical device group numbers, state vectors and
3527 3527 * interrupt masks for each logical device.
3528 3528 */
3529 3529 status = nxge_fzc_intr_init(nxgep);
3530 3530
3531 3531 /*
3532 3532 * Configure logical device masks and timers.
3533 3533 */
3534 3534 status = nxge_intr_mask_mgmt(nxgep);
3535 3535
3536 3536 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_intr_ldgv_init"));
3537 3537 return (status);
3538 3538 }
3539 3539
3540 3540 nxge_status_t
3541 3541 nxge_intr_mask_mgmt(p_nxge_t nxgep)
3542 3542 {
3543 3543 p_nxge_ldgv_t ldgvp;
3544 3544 p_nxge_ldg_t ldgp;
3545 3545 p_nxge_ldv_t ldvp;
3546 3546 npi_handle_t handle;
3547 3547 int i, j;
3548 3548 npi_status_t rs = NPI_SUCCESS;
3549 3549
3550 3550 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr_mask_mgmt"));
3551 3551
3552 3552 if ((ldgvp = nxgep->ldgvp) == NULL) {
3553 3553 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
3554 3554 "<== nxge_intr_mask_mgmt: Null ldgvp"));
3555 3555 return (NXGE_ERROR);
3556 3556 }
3557 3557 handle = NXGE_DEV_NPI_HANDLE(nxgep);
3558 3558 ldgp = ldgvp->ldgp;
3559 3559 ldvp = ldgvp->ldvp;
3560 3560 if (ldgp == NULL || ldvp == NULL) {
3561 3561 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
3562 3562 "<== nxge_intr_mask_mgmt: Null ldgp or ldvp"));
3563 3563 return (NXGE_ERROR);
3564 3564 }
3565 3565 NXGE_DEBUG_MSG((nxgep, INT_CTL,
3566 3566 "==> nxge_intr_mask_mgmt: # of intrs %d ", ldgvp->ldg_intrs));
3567 3567 /* Initialize masks. */
3568 3568 if (nxgep->niu_type != N2_NIU) {
3569 3569 NXGE_DEBUG_MSG((nxgep, INT_CTL,
3570 3570 "==> nxge_intr_mask_mgmt(Neptune): # intrs %d ",
3571 3571 ldgvp->ldg_intrs));
3572 3572 for (i = 0; i < ldgvp->ldg_intrs; i++, ldgp++) {
3573 3573 NXGE_DEBUG_MSG((nxgep, INT_CTL,
3574 3574 "==> nxge_intr_mask_mgmt(Neptune): # ldv %d "
3575 3575 "in group %d", ldgp->nldvs, ldgp->ldg));
3576 3576 for (j = 0; j < ldgp->nldvs; j++, ldvp++) {
3577 3577 NXGE_DEBUG_MSG((nxgep, INT_CTL,
3578 3578 "==> nxge_intr_mask_mgmt: set ldv # %d "
3579 3579 "for ldg %d", ldvp->ldv, ldgp->ldg));
3580 3580 rs = npi_intr_mask_set(handle, ldvp->ldv,
3581 3581 ldvp->ldv_ldf_masks);
3582 3582 if (rs != NPI_SUCCESS) {
3583 3583 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
3584 3584 "<== nxge_intr_mask_mgmt: "
3585 3585 "set mask failed "
3586 3586 " rs 0x%x ldv %d mask 0x%x",
3587 3587 rs, ldvp->ldv,
3588 3588 ldvp->ldv_ldf_masks));
3589 3589 return (NXGE_ERROR | rs);
3590 3590 }
3591 3591 NXGE_DEBUG_MSG((nxgep, INT_CTL,
3592 3592 "==> nxge_intr_mask_mgmt: "
3593 3593 "set mask OK "
3594 3594 " rs 0x%x ldv %d mask 0x%x",
3595 3595 rs, ldvp->ldv,
3596 3596 ldvp->ldv_ldf_masks));
3597 3597 }
3598 3598 }
3599 3599 }
3600 3600 ldgp = ldgvp->ldgp;
3601 3601 /* Configure timer and arm bit */
3602 3602 for (i = 0; i < nxgep->ldgvp->ldg_intrs; i++, ldgp++) {
3603 3603 rs = npi_intr_ldg_mgmt_set(handle, ldgp->ldg,
3604 3604 ldgp->arm, ldgp->ldg_timer);
3605 3605 if (rs != NPI_SUCCESS) {
3606 3606 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
3607 3607 "<== nxge_intr_mask_mgmt: "
3608 3608 "set timer failed "
3609 3609 " rs 0x%x dg %d timer 0x%x",
3610 3610 rs, ldgp->ldg, ldgp->ldg_timer));
3611 3611 return (NXGE_ERROR | rs);
3612 3612 }
3613 3613 NXGE_DEBUG_MSG((nxgep, INT_CTL,
3614 3614 "==> nxge_intr_mask_mgmt: "
3615 3615 "set timer OK "
3616 3616 " rs 0x%x ldg %d timer 0x%x",
3617 3617 rs, ldgp->ldg, ldgp->ldg_timer));
3618 3618 }
3619 3619
3620 3620 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_fzc_intr_mask_mgmt"));
3621 3621 return (NXGE_OK);
3622 3622 }
3623 3623
3624 3624 nxge_status_t
3625 3625 nxge_intr_mask_mgmt_set(p_nxge_t nxgep, boolean_t on)
3626 3626 {
3627 3627 p_nxge_ldgv_t ldgvp;
3628 3628 p_nxge_ldg_t ldgp;
3629 3629 p_nxge_ldv_t ldvp;
3630 3630 npi_handle_t handle;
3631 3631 int i, j;
3632 3632 npi_status_t rs = NPI_SUCCESS;
3633 3633
3634 3634 NXGE_DEBUG_MSG((nxgep, INT_CTL,
3635 3635 "==> nxge_intr_mask_mgmt_set (%d)", on));
3636 3636
3637 3637 if (nxgep->niu_type == N2_NIU) {
3638 3638 NXGE_DEBUG_MSG((nxgep, INT_CTL,
3639 3639 "<== nxge_intr_mask_mgmt_set (%d) not set (N2/NIU)",
3640 3640 on));
3641 3641 return (NXGE_ERROR);
3642 3642 }
3643 3643
3644 3644 if ((ldgvp = nxgep->ldgvp) == NULL) {
3645 3645 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
3646 3646 "==> nxge_intr_mask_mgmt_set: Null ldgvp"));
3647 3647 return (NXGE_ERROR);
3648 3648 }
3649 3649
3650 3650 handle = NXGE_DEV_NPI_HANDLE(nxgep);
3651 3651 ldgp = ldgvp->ldgp;
3652 3652 ldvp = ldgvp->ldvp;
3653 3653 if (ldgp == NULL || ldvp == NULL) {
3654 3654 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
3655 3655 "<== nxge_intr_mask_mgmt_set: Null ldgp or ldvp"));
3656 3656 return (NXGE_ERROR);
3657 3657 }
3658 3658 /* set masks. */
3659 3659 for (i = 0; i < ldgvp->ldg_intrs; i++, ldgp++) {
3660 3660 NXGE_DEBUG_MSG((nxgep, INT_CTL,
3661 3661 "==> nxge_intr_mask_mgmt_set: flag %d ldg %d"
3662 3662 "set mask nldvs %d", on, ldgp->ldg, ldgp->nldvs));
3663 3663 for (j = 0; j < ldgp->nldvs; j++, ldvp++) {
3664 3664 NXGE_DEBUG_MSG((nxgep, INT_CTL,
3665 3665 "==> nxge_intr_mask_mgmt_set: "
3666 3666 "for %d %d flag %d", i, j, on));
3667 3667 if (on) {
3668 3668 ldvp->ldv_ldf_masks = 0;
3669 3669 NXGE_DEBUG_MSG((nxgep, INT_CTL,
3670 3670 "==> nxge_intr_mask_mgmt_set: "
3671 3671 "ON mask off"));
3672 3672 } else if (!on) {
3673 3673 ldvp->ldv_ldf_masks = (uint8_t)LD_IM1_MASK;
3674 3674 NXGE_DEBUG_MSG((nxgep, INT_CTL,
3675 3675 "==> nxge_intr_mask_mgmt_set:mask on"));
3676 3676 }
3677 3677 rs = npi_intr_mask_set(handle, ldvp->ldv,
3678 3678 ldvp->ldv_ldf_masks);
3679 3679 if (rs != NPI_SUCCESS) {
3680 3680 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
3681 3681 "==> nxge_intr_mask_mgmt_set: "
3682 3682 "set mask failed "
3683 3683 " rs 0x%x ldv %d mask 0x%x",
3684 3684 rs, ldvp->ldv, ldvp->ldv_ldf_masks));
3685 3685 return (NXGE_ERROR | rs);
3686 3686 }
3687 3687 NXGE_DEBUG_MSG((nxgep, INT_CTL,
3688 3688 "==> nxge_intr_mask_mgmt_set: flag %d"
3689 3689 "set mask OK "
3690 3690 " ldv %d mask 0x%x",
3691 3691 on, ldvp->ldv, ldvp->ldv_ldf_masks));
3692 3692 }
3693 3693 }
3694 3694
3695 3695 ldgp = ldgvp->ldgp;
3696 3696 /* set the arm bit */
3697 3697 for (i = 0; i < nxgep->ldgvp->ldg_intrs; i++, ldgp++) {
3698 3698 if (on && !ldgp->arm) {
3699 3699 ldgp->arm = B_TRUE;
3700 3700 } else if (!on && ldgp->arm) {
3701 3701 ldgp->arm = B_FALSE;
3702 3702 }
3703 3703 rs = npi_intr_ldg_mgmt_set(handle, ldgp->ldg,
3704 3704 ldgp->arm, ldgp->ldg_timer);
3705 3705 if (rs != NPI_SUCCESS) {
3706 3706 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
3707 3707 "<== nxge_intr_mask_mgmt_set: "
3708 3708 "set timer failed "
3709 3709 " rs 0x%x ldg %d timer 0x%x",
3710 3710 rs, ldgp->ldg, ldgp->ldg_timer));
3711 3711 return (NXGE_ERROR | rs);
3712 3712 }
3713 3713 NXGE_DEBUG_MSG((nxgep, INT_CTL,
3714 3714 "==> nxge_intr_mask_mgmt_set: OK (flag %d) "
3715 3715 "set timer "
3716 3716 " ldg %d timer 0x%x",
3717 3717 on, ldgp->ldg, ldgp->ldg_timer));
3718 3718 }
3719 3719
3720 3720 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_intr_mask_mgmt_set"));
3721 3721 return (NXGE_OK);
3722 3722 }
3723 3723
3724 3724 static nxge_status_t
3725 3725 nxge_get_mac_addr_properties(p_nxge_t nxgep)
3726 3726 {
3727 3727 #if defined(_BIG_ENDIAN)
3728 3728 uchar_t *prop_val;
3729 3729 uint_t prop_len;
3730 3730 uint_t j;
3731 3731 #endif
3732 3732 uint_t i;
3733 3733 uint8_t func_num;
3734 3734 boolean_t compute_macs = B_TRUE;
3735 3735
3736 3736 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_get_mac_addr_properties "));
3737 3737
3738 3738 #if defined(_BIG_ENDIAN)
3739 3739 /*
3740 3740 * Get the ethernet address.
3741 3741 */
3742 3742 (void) localetheraddr((struct ether_addr *)NULL, &nxgep->ouraddr);
3743 3743
3744 3744 /*
3745 3745 * Check if it is an adapter with its own local mac address If it is
3746 3746 * present, override the system mac address.
3747 3747 */
3748 3748 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, nxgep->dip, 0,
3749 3749 "local-mac-address", &prop_val,
3750 3750 &prop_len) == DDI_PROP_SUCCESS) {
3751 3751 if (prop_len == ETHERADDRL) {
3752 3752 nxgep->factaddr = *(p_ether_addr_t)prop_val;
3753 3753 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "Local mac address = "
3754 3754 "%02x:%02x:%02x:%02x:%02x:%02x",
3755 3755 prop_val[0], prop_val[1], prop_val[2],
3756 3756 prop_val[3], prop_val[4], prop_val[5]));
3757 3757 }
3758 3758 ddi_prop_free(prop_val);
3759 3759 }
3760 3760 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, nxgep->dip, 0,
3761 3761 "local-mac-address?", &prop_val,
3762 3762 &prop_len) == DDI_PROP_SUCCESS) {
3763 3763 if (strncmp("true", (caddr_t)prop_val, (size_t)prop_len) == 0) {
3764 3764 nxgep->ouraddr = nxgep->factaddr;
3765 3765 NXGE_DEBUG_MSG((nxgep, DDI_CTL,
3766 3766 "Using local MAC address"));
3767 3767 }
3768 3768 ddi_prop_free(prop_val);
3769 3769 } else {
3770 3770 nxgep->ouraddr = nxgep->factaddr;
3771 3771 }
3772 3772
3773 3773 if ((!nxgep->vpd_info.present) ||
3774 3774 (nxge_is_valid_local_mac(nxgep->factaddr)))
3775 3775 goto got_mac_addr;
3776 3776
3777 3777 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "nxge_get_mac_addr_properties: "
3778 3778 "MAC address from properties is not valid...reading from PROM"));
3779 3779
3780 3780 #endif
3781 3781 if (!nxgep->vpd_info.ver_valid) {
3782 3782 (void) nxge_espc_mac_addrs_get(nxgep);
3783 3783 if (!nxge_is_valid_local_mac(nxgep->factaddr)) {
3784 3784 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "Failed to get "
3785 3785 "MAC address"));
3786 3786 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "EEPROM version "
3787 3787 "[%s] invalid...please update",
3788 3788 nxgep->vpd_info.ver));
3789 3789 return (NXGE_ERROR);
3790 3790 }
3791 3791 nxgep->ouraddr = nxgep->factaddr;
3792 3792 goto got_mac_addr;
3793 3793 }
3794 3794 /*
3795 3795 * First get the MAC address from the info in the VPD data read
3796 3796 * from the EEPROM.
3797 3797 */
3798 3798 nxge_espc_get_next_mac_addr(nxgep->vpd_info.mac_addr,
3799 3799 nxgep->function_num, &nxgep->factaddr);
3800 3800
3801 3801 if (!nxge_is_valid_local_mac(nxgep->factaddr)) {
3802 3802 NXGE_DEBUG_MSG((nxgep, DDI_CTL,
3803 3803 "nxge_get_mac_addr_properties: "
3804 3804 "MAC address in EEPROM VPD data not valid"
3805 3805 "...reading from NCR registers"));
3806 3806 (void) nxge_espc_mac_addrs_get(nxgep);
3807 3807 if (!nxge_is_valid_local_mac(nxgep->factaddr)) {
3808 3808 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "Failed to get "
3809 3809 "MAC address"));
3810 3810 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "EEPROM version "
3811 3811 "[%s] invalid...please update",
3812 3812 nxgep->vpd_info.ver));
3813 3813 return (NXGE_ERROR);
3814 3814 }
3815 3815 }
3816 3816
3817 3817 nxgep->ouraddr = nxgep->factaddr;
3818 3818
3819 3819 got_mac_addr:
3820 3820 func_num = nxgep->function_num;
3821 3821
3822 3822 /*
3823 3823 * Note: mac-addresses property is the list of mac addresses for a
3824 3824 * port. NXGE_MAX_MMAC_ADDRS is the total number of MAC addresses
3825 3825 * allocated for a board.
3826 3826 */
3827 3827 nxgep->nxge_mmac_info.total_factory_macs = NXGE_MAX_MMAC_ADDRS;
3828 3828
3829 3829 #if defined(_BIG_ENDIAN)
3830 3830 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, nxgep->dip, 0,
3831 3831 "mac-addresses", &prop_val, &prop_len) == DDI_PROP_SUCCESS) {
3832 3832 /*
3833 3833 * XAUI may have up to 18 MACs, more than the XMAC can
3834 3834 * use (1 unique MAC plus 16 alternate MACs)
3835 3835 */
3836 3836 nxgep->nxge_mmac_info.num_factory_mmac =
3837 3837 prop_len / ETHERADDRL - 1;
3838 3838 if (nxgep->nxge_mmac_info.num_factory_mmac >
3839 3839 XMAC_MAX_ALT_ADDR_ENTRY) {
3840 3840 nxgep->nxge_mmac_info.num_factory_mmac =
3841 3841 XMAC_MAX_ALT_ADDR_ENTRY;
3842 3842 }
3843 3843
3844 3844 for (i = 1; i <= nxgep->nxge_mmac_info.num_factory_mmac; i++) {
3845 3845 for (j = 0; j < ETHERADDRL; j++) {
3846 3846 nxgep->nxge_mmac_info.factory_mac_pool[i][j] =
3847 3847 *(prop_val + (i * ETHERADDRL) + j);
3848 3848 }
3849 3849 NXGE_DEBUG_MSG((nxgep, DDI_CTL,
3850 3850 "nxge_get_mac_addr_properties: Alt mac[%d] from "
3851 3851 "mac-addresses property[%2x:%2x:%2x:%2x:%2x:%2x]",
3852 3852 i, nxgep->nxge_mmac_info.factory_mac_pool[i][0],
3853 3853 nxgep->nxge_mmac_info.factory_mac_pool[i][1],
3854 3854 nxgep->nxge_mmac_info.factory_mac_pool[i][2],
3855 3855 nxgep->nxge_mmac_info.factory_mac_pool[i][3],
3856 3856 nxgep->nxge_mmac_info.factory_mac_pool[i][4],
3857 3857 nxgep->nxge_mmac_info.factory_mac_pool[i][5]));
3858 3858 }
3859 3859
3860 3860 compute_macs = B_FALSE;
3861 3861 ddi_prop_free(prop_val);
3862 3862 goto got_mmac_info;
3863 3863 }
3864 3864 #endif
3865 3865 /*
3866 3866 * total_factory_macs = 32
3867 3867 * num_factory_mmac = (32 >> (nports/2)) - 1
3868 3868 * So if nports = 4, then num_factory_mmac = 7
3869 3869 * if nports = 2, then num_factory_mmac = 15
3870 3870 */
3871 3871 nxgep->nxge_mmac_info.num_factory_mmac =
3872 3872 ((nxgep->nxge_mmac_info.total_factory_macs >>
3873 3873 (nxgep->nports >> 1))) - 1;
3874 3874
3875 3875 got_mmac_info:
3876 3876
3877 3877 if ((nxgep->function_num < 2) &&
3878 3878 (nxgep->nxge_mmac_info.num_factory_mmac >
3879 3879 XMAC_MAX_ALT_ADDR_ENTRY)) {
3880 3880 nxgep->nxge_mmac_info.num_factory_mmac =
3881 3881 XMAC_MAX_ALT_ADDR_ENTRY;
3882 3882 } else if ((nxgep->function_num > 1) &&
3883 3883 (nxgep->nxge_mmac_info.num_factory_mmac >
3884 3884 BMAC_MAX_ALT_ADDR_ENTRY)) {
3885 3885 nxgep->nxge_mmac_info.num_factory_mmac =
3886 3886 BMAC_MAX_ALT_ADDR_ENTRY;
3887 3887 }
3888 3888
3889 3889 for (i = 0; i <= nxgep->nxge_mmac_info.num_mmac; i++) {
3890 3890 (void) npi_mac_altaddr_disable(nxgep->npi_handle,
3891 3891 NXGE_GET_PORT_NUM(func_num), i);
3892 3892 }
3893 3893
3894 3894 (void) nxge_init_mmac(nxgep, compute_macs);
3895 3895 return (NXGE_OK);
3896 3896 }
3897 3897
3898 3898 void
3899 3899 nxge_get_xcvr_properties(p_nxge_t nxgep)
3900 3900 {
3901 3901 uchar_t *prop_val;
3902 3902 uint_t prop_len;
3903 3903
3904 3904 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_get_xcvr_properties"));
3905 3905
3906 3906 /*
3907 3907 * Read the type of physical layer interface being used.
3908 3908 */
3909 3909 nxgep->statsp->mac_stats.xcvr_inuse = INT_MII_XCVR;
3910 3910 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, nxgep->dip, 0,
3911 3911 "phy-type", &prop_val, &prop_len) == DDI_PROP_SUCCESS) {
3912 3912 if (strncmp("pcs", (caddr_t)prop_val,
3913 3913 (size_t)prop_len) == 0) {
3914 3914 nxgep->statsp->mac_stats.xcvr_inuse = PCS_XCVR;
3915 3915 } else {
3916 3916 nxgep->statsp->mac_stats.xcvr_inuse = INT_MII_XCVR;
3917 3917 }
3918 3918 ddi_prop_free(prop_val);
3919 3919 } else if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, nxgep->dip, 0,
3920 3920 "phy-interface", &prop_val,
3921 3921 &prop_len) == DDI_PROP_SUCCESS) {
3922 3922 if (strncmp("pcs", (caddr_t)prop_val, (size_t)prop_len) == 0) {
3923 3923 nxgep->statsp->mac_stats.xcvr_inuse = PCS_XCVR;
3924 3924 } else {
3925 3925 nxgep->statsp->mac_stats.xcvr_inuse = INT_MII_XCVR;
3926 3926 }
3927 3927 ddi_prop_free(prop_val);
3928 3928 }
3929 3929 }
3930 3930
3931 3931 /*
3932 3932 * Static functions start here.
3933 3933 */
3934 3934
3935 3935 static void
3936 3936 nxge_ldgv_setup(p_nxge_ldg_t *ldgp, p_nxge_ldv_t *ldvp, uint8_t ldv,
3937 3937 uint8_t endldg, int *ngrps)
3938 3938 {
3939 3939 NXGE_DEBUG_MSG((NULL, INT_CTL, "==> nxge_ldgv_setup"));
3940 3940 /* Assign the group number for each device. */
3941 3941 (*ldvp)->ldg_assigned = (*ldgp)->ldg;
3942 3942 (*ldvp)->ldgp = *ldgp;
3943 3943 (*ldvp)->ldv = ldv;
3944 3944
3945 3945 NXGE_DEBUG_MSG((NULL, INT_CTL, "==> nxge_ldgv_setup: "
3946 3946 "ldv %d endldg %d ldg %d, ldvp $%p",
3947 3947 ldv, endldg, (*ldgp)->ldg, (*ldgp)->ldvp));
3948 3948
3949 3949 (*ldgp)->nldvs++;
3950 3950 if ((*ldgp)->ldg == (endldg - 1)) {
3951 3951 if ((*ldgp)->ldvp == NULL) {
3952 3952 (*ldgp)->ldvp = *ldvp;
3953 3953 *ngrps += 1;
3954 3954 NXGE_DEBUG_MSG((NULL, INT_CTL,
3955 3955 "==> nxge_ldgv_setup: ngrps %d", *ngrps));
3956 3956 }
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3957 3957 NXGE_DEBUG_MSG((NULL, INT_CTL,
3958 3958 "==> nxge_ldgv_setup: ldvp $%p ngrps %d",
3959 3959 *ldvp, *ngrps));
3960 3960 ++*ldvp;
3961 3961 } else {
3962 3962 (*ldgp)->ldvp = *ldvp;
3963 3963 *ngrps += 1;
3964 3964 NXGE_DEBUG_MSG((NULL, INT_CTL, "==> nxge_ldgv_setup(done): "
3965 3965 "ldv %d endldg %d ldg %d, ldvp $%p",
3966 3966 ldv, endldg, (*ldgp)->ldg, (*ldgp)->ldvp));
3967 - (*ldvp) = ++*ldvp;
3968 - (*ldgp) = ++*ldgp;
3967 + ++*ldvp;
3968 + ++*ldgp;
3969 3969 NXGE_DEBUG_MSG((NULL, INT_CTL,
3970 3970 "==> nxge_ldgv_setup: new ngrps %d", *ngrps));
3971 3971 }
3972 3972
3973 3973 NXGE_DEBUG_MSG((NULL, INT_CTL, "==> nxge_ldgv_setup: "
3974 3974 "ldv %d ldvp $%p endldg %d ngrps %d",
3975 3975 ldv, ldvp, endldg, *ngrps));
3976 3976
3977 3977 NXGE_DEBUG_MSG((NULL, INT_CTL, "<== nxge_ldgv_setup"));
3978 3978 }
3979 3979
3980 3980 /*
3981 3981 * Note: This function assumes the following distribution of mac
3982 3982 * addresses among 4 ports in neptune:
3983 3983 *
3984 3984 * -------------
3985 3985 * 0| |0 - local-mac-address for fn 0
3986 3986 * -------------
3987 3987 * 1| |1 - local-mac-address for fn 1
3988 3988 * -------------
3989 3989 * 2| |2 - local-mac-address for fn 2
3990 3990 * -------------
3991 3991 * 3| |3 - local-mac-address for fn 3
3992 3992 * -------------
3993 3993 * | |4 - Start of alt. mac addr. for fn 0
3994 3994 * | |
3995 3995 * | |
3996 3996 * | |10
3997 3997 * --------------
3998 3998 * | |11 - Start of alt. mac addr. for fn 1
3999 3999 * | |
4000 4000 * | |
4001 4001 * | |17
4002 4002 * --------------
4003 4003 * | |18 - Start of alt. mac addr. for fn 2
4004 4004 * | |
4005 4005 * | |
4006 4006 * | |24
4007 4007 * --------------
4008 4008 * | |25 - Start of alt. mac addr. for fn 3
4009 4009 * | |
4010 4010 * | |
4011 4011 * | |31
4012 4012 * --------------
4013 4013 *
4014 4014 * For N2/NIU the mac addresses is from XAUI card.
4015 4015 *
4016 4016 * When 'compute_addrs' is true, the alternate mac addresses are computed
4017 4017 * using the unique mac address as base. Otherwise the alternate addresses
4018 4018 * are assigned from the list read off the 'mac-addresses' property.
4019 4019 */
4020 4020
4021 4021 static void
4022 4022 nxge_init_mmac(p_nxge_t nxgep, boolean_t compute_addrs)
4023 4023 {
4024 4024 int slot;
4025 4025 uint8_t func_num;
4026 4026 uint16_t *base_mmac_addr;
4027 4027 uint32_t alt_mac_ls4b;
4028 4028 uint16_t *mmac_addr;
4029 4029 uint32_t base_mac_ls4b; /* least significant 4 bytes */
4030 4030 nxge_mmac_t *mmac_info;
4031 4031 npi_mac_addr_t mac_addr;
4032 4032
4033 4033 func_num = nxgep->function_num;
4034 4034 base_mmac_addr = (uint16_t *)&nxgep->factaddr;
4035 4035 mmac_info = (nxge_mmac_t *)&nxgep->nxge_mmac_info;
4036 4036
4037 4037 if (compute_addrs) {
4038 4038 base_mac_ls4b = ((uint32_t)base_mmac_addr[1]) << 16 |
4039 4039 base_mmac_addr[2];
4040 4040
4041 4041 if (nxgep->niu_type == N2_NIU) {
4042 4042 /* ls4b of 1st altmac */
4043 4043 alt_mac_ls4b = base_mac_ls4b + 1;
4044 4044 } else { /* Neptune */
4045 4045 alt_mac_ls4b = base_mac_ls4b +
4046 4046 (nxgep->nports - func_num) +
4047 4047 (func_num * (mmac_info->num_factory_mmac));
4048 4048 }
4049 4049 }
4050 4050
4051 4051 /* Set flags for unique MAC */
4052 4052 mmac_info->mac_pool[0].flags |= MMAC_SLOT_USED | MMAC_VENDOR_ADDR;
4053 4053
4054 4054 /* Clear flags of all alternate MAC slots */
4055 4055 for (slot = 1; slot <= mmac_info->num_mmac; slot++) {
4056 4056 if (slot <= mmac_info->num_factory_mmac)
4057 4057 mmac_info->mac_pool[slot].flags = MMAC_VENDOR_ADDR;
4058 4058 else
4059 4059 mmac_info->mac_pool[slot].flags = 0;
4060 4060 }
4061 4061
4062 4062 /* Generate and store factory alternate MACs */
4063 4063 for (slot = 1; slot <= mmac_info->num_factory_mmac; slot++) {
4064 4064 mmac_addr = (uint16_t *)&mmac_info->factory_mac_pool[slot];
4065 4065 if (compute_addrs) {
4066 4066 mmac_addr[0] = base_mmac_addr[0];
4067 4067 mac_addr.w2 = mmac_addr[0];
4068 4068
4069 4069 mmac_addr[1] = (alt_mac_ls4b >> 16) & 0x0FFFF;
4070 4070 mac_addr.w1 = mmac_addr[1];
4071 4071
4072 4072 mmac_addr[2] = alt_mac_ls4b & 0x0FFFF;
4073 4073 mac_addr.w0 = mmac_addr[2];
4074 4074
4075 4075 alt_mac_ls4b++;
4076 4076 } else {
4077 4077 mac_addr.w2 = mmac_addr[0];
4078 4078 mac_addr.w1 = mmac_addr[1];
4079 4079 mac_addr.w0 = mmac_addr[2];
4080 4080 }
4081 4081
4082 4082 NXGE_DEBUG_MSG((nxgep, DDI_CTL,
4083 4083 "mac_pool_addr[%2x:%2x:%2x:%2x:%2x:%2x] npi_addr[%x%x%x]",
4084 4084 mmac_info->factory_mac_pool[slot][0],
4085 4085 mmac_info->factory_mac_pool[slot][1],
4086 4086 mmac_info->factory_mac_pool[slot][2],
4087 4087 mmac_info->factory_mac_pool[slot][3],
4088 4088 mmac_info->factory_mac_pool[slot][4],
4089 4089 mmac_info->factory_mac_pool[slot][5],
4090 4090 mac_addr.w0, mac_addr.w1, mac_addr.w2));
4091 4091 /*
4092 4092 * slot minus 1 because npi_mac_altaddr_entry expects 0
4093 4093 * for the first alternate mac address.
4094 4094 */
4095 4095 (void) npi_mac_altaddr_entry(nxgep->npi_handle, OP_SET,
4096 4096 NXGE_GET_PORT_NUM(func_num), slot - 1, &mac_addr);
4097 4097 }
4098 4098 /* Initialize the first two parameters for mmac kstat */
4099 4099 nxgep->statsp->mmac_stats.mmac_max_cnt = mmac_info->num_mmac;
4100 4100 nxgep->statsp->mmac_stats.mmac_avail_cnt = mmac_info->num_mmac;
4101 4101 }
4102 4102
4103 4103 /*
4104 4104 * Convert an RDC group index into a port ring index. That is, map
4105 4105 * <groupid> to an index into nxgep->rx_ring_handles.
4106 4106 * (group ring index -> port ring index)
4107 4107 */
4108 4108 int
4109 4109 nxge_get_rxring_index(p_nxge_t nxgep, int groupid, int ringidx)
4110 4110 {
4111 4111 int i;
4112 4112 int index = 0;
4113 4113 p_nxge_rdc_grp_t rdc_grp_p;
4114 4114 p_nxge_dma_pt_cfg_t p_dma_cfgp;
4115 4115 p_nxge_hw_pt_cfg_t p_cfgp;
4116 4116
4117 4117 p_dma_cfgp = &nxgep->pt_config;
4118 4118 p_cfgp = &p_dma_cfgp->hw_config;
4119 4119
4120 4120 if (isLDOMguest(nxgep))
4121 4121 return (ringidx);
4122 4122
4123 4123 for (i = 0; i < groupid; i++) {
4124 4124 rdc_grp_p =
4125 4125 &p_dma_cfgp->rdc_grps[p_cfgp->def_mac_rxdma_grpid + i];
4126 4126 index += rdc_grp_p->max_rdcs;
4127 4127 }
4128 4128
4129 4129 return (index + ringidx);
4130 4130 }
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