Print this page
libdtrace: attempt to resolve FORWARD types to concrete types
| Split |
Close |
| Expand all |
| Collapse all |
--- old/usr/src/lib/libdtrace/common/dt_cg.c
+++ new/usr/src/lib/libdtrace/common/dt_cg.c
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License, Version 1.0 only
6 6 * (the "License"). You may not use this file except in compliance
7 7 * with the License.
8 8 *
9 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
10 10 * or http://www.opensolaris.org/os/licensing.
11 11 * See the License for the specific language governing permissions
12 12 * and limitations under the License.
13 13 *
14 14 * When distributing Covered Code, include this CDDL HEADER in each
15 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
16 16 * If applicable, add the following below this CDDL HEADER, with the
17 17 * fields enclosed by brackets "[]" replaced with your own identifying
18 18 * information: Portions Copyright [yyyy] [name of copyright owner]
19 19 *
20 20 * CDDL HEADER END
21 21 */
22 22
23 23 /*
24 24 * Copyright 2005 Sun Microsystems, Inc. All rights reserved.
25 25 * Use is subject to license terms.
26 26 */
27 27
28 28 /*
29 29 * Copyright (c) 2012 by Delphix. All rights reserved.
30 30 */
31 31
32 32 #include <sys/types.h>
33 33 #include <sys/sysmacros.h>
|
↓ open down ↓ |
33 lines elided |
↑ open up ↑ |
34 34 #include <sys/isa_defs.h>
35 35
36 36 #include <strings.h>
37 37 #include <stdlib.h>
38 38 #include <setjmp.h>
39 39 #include <assert.h>
40 40 #include <errno.h>
41 41
42 42 #include <dt_impl.h>
43 43 #include <dt_grammar.h>
44 +#include <dt_module.h>
44 45 #include <dt_parser.h>
45 46 #include <dt_provider.h>
46 47
47 48 static void dt_cg_node(dt_node_t *, dt_irlist_t *, dt_regset_t *);
48 49
49 50 static dt_irnode_t *
50 51 dt_cg_node_alloc(uint_t label, dif_instr_t instr)
51 52 {
52 53 dt_irnode_t *dip = malloc(sizeof (dt_irnode_t));
53 54
54 55 if (dip == NULL)
55 56 longjmp(yypcb->pcb_jmpbuf, EDT_NOMEM);
56 57
57 58 dip->di_label = label;
58 59 dip->di_instr = instr;
59 60 dip->di_extern = NULL;
60 61 dip->di_next = NULL;
61 62
62 63 return (dip);
|
↓ open down ↓ |
9 lines elided |
↑ open up ↑ |
63 64 }
64 65
65 66 /*
66 67 * Code generator wrapper function for ctf_member_info. If we are given a
67 68 * reference to a forward declaration tag, search the entire type space for
68 69 * the actual definition and then call ctf_member_info on the result.
69 70 */
70 71 static ctf_file_t *
71 72 dt_cg_membinfo(ctf_file_t *fp, ctf_id_t type, const char *s, ctf_membinfo_t *mp)
72 73 {
73 - while (ctf_type_kind(fp, type) == CTF_K_FORWARD) {
74 - char n[DT_TYPE_NAMELEN];
75 - dtrace_typeinfo_t dtt;
76 -
77 - if (ctf_type_name(fp, type, n, sizeof (n)) == NULL ||
78 - dt_type_lookup(n, &dtt) == -1 || (
79 - dtt.dtt_ctfp == fp && dtt.dtt_type == type))
80 - break; /* unable to improve our position */
81 -
82 - fp = dtt.dtt_ctfp;
83 - type = ctf_type_resolve(fp, dtt.dtt_type);
84 - }
74 + dt_resolve_forward_decl(&fp, &type);
85 75
86 76 if (ctf_member_info(fp, type, s, mp) == CTF_ERR)
87 77 return (NULL); /* ctf_errno is set for us */
88 78
89 79 return (fp);
90 80 }
91 81
92 82 static void
93 83 dt_cg_xsetx(dt_irlist_t *dlp, dt_ident_t *idp, uint_t lbl, int reg, uint64_t x)
94 84 {
95 85 int flag = idp != NULL ? DT_INT_PRIVATE : DT_INT_SHARED;
96 86 int intoff = dt_inttab_insert(yypcb->pcb_inttab, x, flag);
97 87 dif_instr_t instr = DIF_INSTR_SETX((uint_t)intoff, reg);
98 88
99 89 if (intoff == -1)
100 90 longjmp(yypcb->pcb_jmpbuf, EDT_NOMEM);
101 91
102 92 if (intoff > DIF_INTOFF_MAX)
103 93 longjmp(yypcb->pcb_jmpbuf, EDT_INT2BIG);
104 94
105 95 dt_irlist_append(dlp, dt_cg_node_alloc(lbl, instr));
106 96
107 97 if (idp != NULL)
108 98 dlp->dl_last->di_extern = idp;
109 99 }
110 100
111 101 static void
112 102 dt_cg_setx(dt_irlist_t *dlp, int reg, uint64_t x)
113 103 {
114 104 dt_cg_xsetx(dlp, NULL, DT_LBL_NONE, reg, x);
115 105 }
116 106
117 107 /*
118 108 * When loading bit-fields, we want to convert a byte count in the range
119 109 * 1-8 to the closest power of 2 (e.g. 3->4, 5->8, etc). The clp2() function
120 110 * is a clever implementation from "Hacker's Delight" by Henry Warren, Jr.
121 111 */
122 112 static size_t
123 113 clp2(size_t x)
124 114 {
125 115 x--;
126 116
127 117 x |= (x >> 1);
128 118 x |= (x >> 2);
129 119 x |= (x >> 4);
130 120 x |= (x >> 8);
131 121 x |= (x >> 16);
132 122
133 123 return (x + 1);
134 124 }
135 125
136 126 /*
137 127 * Lookup the correct load opcode to use for the specified node and CTF type.
138 128 * We determine the size and convert it to a 3-bit index. Our lookup table
139 129 * is constructed to use a 5-bit index, consisting of the 3-bit size 0-7, a
140 130 * bit for the sign, and a bit for userland address. For example, a 4-byte
141 131 * signed load from userland would be at the following table index:
142 132 * user=1 sign=1 size=4 => binary index 11011 = decimal index 27
143 133 */
144 134 static uint_t
145 135 dt_cg_load(dt_node_t *dnp, ctf_file_t *ctfp, ctf_id_t type)
146 136 {
147 137 static const uint_t ops[] = {
148 138 DIF_OP_LDUB, DIF_OP_LDUH, 0, DIF_OP_LDUW,
149 139 0, 0, 0, DIF_OP_LDX,
150 140 DIF_OP_LDSB, DIF_OP_LDSH, 0, DIF_OP_LDSW,
151 141 0, 0, 0, DIF_OP_LDX,
152 142 DIF_OP_ULDUB, DIF_OP_ULDUH, 0, DIF_OP_ULDUW,
153 143 0, 0, 0, DIF_OP_ULDX,
154 144 DIF_OP_ULDSB, DIF_OP_ULDSH, 0, DIF_OP_ULDSW,
155 145 0, 0, 0, DIF_OP_ULDX,
156 146 };
157 147
158 148 ctf_encoding_t e;
159 149 ssize_t size;
160 150
161 151 /*
162 152 * If we're loading a bit-field, the size of our load is found by
163 153 * rounding cte_bits up to a byte boundary and then finding the
164 154 * nearest power of two to this value (see clp2(), above).
165 155 */
166 156 if ((dnp->dn_flags & DT_NF_BITFIELD) &&
167 157 ctf_type_encoding(ctfp, type, &e) != CTF_ERR)
168 158 size = clp2(P2ROUNDUP(e.cte_bits, NBBY) / NBBY);
169 159 else
170 160 size = ctf_type_size(ctfp, type);
171 161
172 162 if (size < 1 || size > 8 || (size & (size - 1)) != 0) {
173 163 xyerror(D_UNKNOWN, "internal error -- cg cannot load "
174 164 "size %ld when passed by value\n", (long)size);
175 165 }
176 166
177 167 size--; /* convert size to 3-bit index */
178 168
179 169 if (dnp->dn_flags & DT_NF_SIGNED)
180 170 size |= 0x08;
181 171 if (dnp->dn_flags & DT_NF_USERLAND)
182 172 size |= 0x10;
183 173
184 174 return (ops[size]);
185 175 }
186 176
187 177 static void
188 178 dt_cg_ptrsize(dt_node_t *dnp, dt_irlist_t *dlp, dt_regset_t *drp,
189 179 uint_t op, int dreg)
190 180 {
191 181 ctf_file_t *ctfp = dnp->dn_ctfp;
192 182 ctf_arinfo_t r;
193 183 dif_instr_t instr;
194 184 ctf_id_t type;
195 185 uint_t kind;
196 186 ssize_t size;
197 187 int sreg;
198 188
199 189 type = ctf_type_resolve(ctfp, dnp->dn_type);
200 190 kind = ctf_type_kind(ctfp, type);
201 191 assert(kind == CTF_K_POINTER || kind == CTF_K_ARRAY);
202 192
203 193 if (kind == CTF_K_ARRAY) {
204 194 if (ctf_array_info(ctfp, type, &r) != 0) {
205 195 yypcb->pcb_hdl->dt_ctferr = ctf_errno(ctfp);
206 196 longjmp(yypcb->pcb_jmpbuf, EDT_CTF);
207 197 }
208 198 type = r.ctr_contents;
209 199 } else
210 200 type = ctf_type_reference(ctfp, type);
211 201
212 202 if ((size = ctf_type_size(ctfp, type)) == 1)
213 203 return; /* multiply or divide by one can be omitted */
214 204
215 205 sreg = dt_regset_alloc(drp);
216 206 dt_cg_setx(dlp, sreg, size);
217 207 instr = DIF_INSTR_FMT(op, dreg, sreg, dreg);
218 208 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
219 209 dt_regset_free(drp, sreg);
220 210 }
221 211
222 212 /*
223 213 * If the result of a "." or "->" operation is a bit-field, we use this routine
224 214 * to generate an epilogue to the load instruction that extracts the value. In
225 215 * the diagrams below the "ld??" is the load instruction that is generated to
226 216 * load the containing word that is generating prior to calling this function.
227 217 *
228 218 * Epilogue for unsigned fields: Epilogue for signed fields:
229 219 *
230 220 * ldu? [r1], r1 lds? [r1], r1
231 221 * setx USHIFT, r2 setx 64 - SSHIFT, r2
232 222 * srl r1, r2, r1 sll r1, r2, r1
233 223 * setx (1 << bits) - 1, r2 setx 64 - bits, r2
234 224 * and r1, r2, r1 sra r1, r2, r1
235 225 *
236 226 * The *SHIFT constants above changes value depending on the endian-ness of our
237 227 * target architecture. Refer to the comments below for more details.
238 228 */
239 229 static void
240 230 dt_cg_field_get(dt_node_t *dnp, dt_irlist_t *dlp, dt_regset_t *drp,
241 231 ctf_file_t *fp, const ctf_membinfo_t *mp)
242 232 {
243 233 ctf_encoding_t e;
244 234 dif_instr_t instr;
245 235 uint64_t shift;
246 236 int r1, r2;
247 237
248 238 if (ctf_type_encoding(fp, mp->ctm_type, &e) != 0 || e.cte_bits > 64) {
249 239 xyerror(D_UNKNOWN, "cg: bad field: off %lu type <%ld> "
250 240 "bits %u\n", mp->ctm_offset, mp->ctm_type, e.cte_bits);
251 241 }
252 242
253 243 assert(dnp->dn_op == DT_TOK_PTR || dnp->dn_op == DT_TOK_DOT);
254 244 r1 = dnp->dn_left->dn_reg;
255 245 r2 = dt_regset_alloc(drp);
256 246
257 247 /*
258 248 * On little-endian architectures, ctm_offset counts from the right so
259 249 * ctm_offset % NBBY itself is the amount we want to shift right to
260 250 * move the value bits to the little end of the register to mask them.
261 251 * On big-endian architectures, ctm_offset counts from the left so we
262 252 * must subtract (ctm_offset % NBBY + cte_bits) from the size in bits
263 253 * we used for the load. The size of our load in turn is found by
264 254 * rounding cte_bits up to a byte boundary and then finding the
265 255 * nearest power of two to this value (see clp2(), above). These
266 256 * properties are used to compute shift as USHIFT or SSHIFT, below.
267 257 */
268 258 if (dnp->dn_flags & DT_NF_SIGNED) {
269 259 #ifdef _BIG_ENDIAN
270 260 shift = clp2(P2ROUNDUP(e.cte_bits, NBBY) / NBBY) * NBBY -
271 261 mp->ctm_offset % NBBY;
272 262 #else
273 263 shift = mp->ctm_offset % NBBY + e.cte_bits;
274 264 #endif
275 265 dt_cg_setx(dlp, r2, 64 - shift);
276 266 instr = DIF_INSTR_FMT(DIF_OP_SLL, r1, r2, r1);
277 267 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
278 268
279 269 dt_cg_setx(dlp, r2, 64 - e.cte_bits);
280 270 instr = DIF_INSTR_FMT(DIF_OP_SRA, r1, r2, r1);
281 271 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
282 272 } else {
283 273 #ifdef _BIG_ENDIAN
284 274 shift = clp2(P2ROUNDUP(e.cte_bits, NBBY) / NBBY) * NBBY -
285 275 (mp->ctm_offset % NBBY + e.cte_bits);
286 276 #else
287 277 shift = mp->ctm_offset % NBBY;
288 278 #endif
289 279 dt_cg_setx(dlp, r2, shift);
290 280 instr = DIF_INSTR_FMT(DIF_OP_SRL, r1, r2, r1);
291 281 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
292 282
293 283 dt_cg_setx(dlp, r2, (1ULL << e.cte_bits) - 1);
294 284 instr = DIF_INSTR_FMT(DIF_OP_AND, r1, r2, r1);
295 285 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
296 286 }
297 287
298 288 dt_regset_free(drp, r2);
299 289 }
300 290
301 291 /*
302 292 * If the destination of a store operation is a bit-field, we use this routine
303 293 * to generate a prologue to the store instruction that loads the surrounding
304 294 * bits, clears the destination field, and ORs in the new value of the field.
305 295 * In the diagram below the "st?" is the store instruction that is generated to
306 296 * store the containing word that is generating after calling this function.
307 297 *
308 298 * ld [dst->dn_reg], r1
309 299 * setx ~(((1 << cte_bits) - 1) << (ctm_offset % NBBY)), r2
310 300 * and r1, r2, r1
311 301 *
312 302 * setx (1 << cte_bits) - 1, r2
313 303 * and src->dn_reg, r2, r2
314 304 * setx ctm_offset % NBBY, r3
315 305 * sll r2, r3, r2
316 306 *
317 307 * or r1, r2, r1
318 308 * st? r1, [dst->dn_reg]
319 309 *
320 310 * This routine allocates a new register to hold the value to be stored and
321 311 * returns it. The caller is responsible for freeing this register later.
322 312 */
323 313 static int
324 314 dt_cg_field_set(dt_node_t *src, dt_irlist_t *dlp,
325 315 dt_regset_t *drp, dt_node_t *dst)
326 316 {
327 317 uint64_t cmask, fmask, shift;
328 318 dif_instr_t instr;
329 319 int r1, r2, r3;
330 320
331 321 ctf_membinfo_t m;
332 322 ctf_encoding_t e;
333 323 ctf_file_t *fp, *ofp;
334 324 ctf_id_t type;
335 325
336 326 assert(dst->dn_op == DT_TOK_PTR || dst->dn_op == DT_TOK_DOT);
337 327 assert(dst->dn_right->dn_kind == DT_NODE_IDENT);
338 328
339 329 fp = dst->dn_left->dn_ctfp;
340 330 type = ctf_type_resolve(fp, dst->dn_left->dn_type);
341 331
342 332 if (dst->dn_op == DT_TOK_PTR) {
343 333 type = ctf_type_reference(fp, type);
344 334 type = ctf_type_resolve(fp, type);
345 335 }
346 336
347 337 if ((fp = dt_cg_membinfo(ofp = fp, type,
348 338 dst->dn_right->dn_string, &m)) == NULL) {
349 339 yypcb->pcb_hdl->dt_ctferr = ctf_errno(ofp);
350 340 longjmp(yypcb->pcb_jmpbuf, EDT_CTF);
351 341 }
352 342
353 343 if (ctf_type_encoding(fp, m.ctm_type, &e) != 0 || e.cte_bits > 64) {
354 344 xyerror(D_UNKNOWN, "cg: bad field: off %lu type <%ld> "
355 345 "bits %u\n", m.ctm_offset, m.ctm_type, e.cte_bits);
356 346 }
357 347
358 348 r1 = dt_regset_alloc(drp);
359 349 r2 = dt_regset_alloc(drp);
360 350 r3 = dt_regset_alloc(drp);
361 351
362 352 /*
363 353 * Compute shifts and masks. We need to compute "shift" as the amount
364 354 * we need to shift left to position our field in the containing word.
365 355 * Refer to the comments in dt_cg_field_get(), above, for more info.
366 356 * We then compute fmask as the mask that truncates the value in the
367 357 * input register to width cte_bits, and cmask as the mask used to
368 358 * pass through the containing bits and zero the field bits.
369 359 */
370 360 #ifdef _BIG_ENDIAN
371 361 shift = clp2(P2ROUNDUP(e.cte_bits, NBBY) / NBBY) * NBBY -
372 362 (m.ctm_offset % NBBY + e.cte_bits);
373 363 #else
374 364 shift = m.ctm_offset % NBBY;
375 365 #endif
376 366 fmask = (1ULL << e.cte_bits) - 1;
377 367 cmask = ~(fmask << shift);
378 368
379 369 instr = DIF_INSTR_LOAD(
380 370 dt_cg_load(dst, fp, m.ctm_type), dst->dn_reg, r1);
381 371 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
382 372
383 373 dt_cg_setx(dlp, r2, cmask);
384 374 instr = DIF_INSTR_FMT(DIF_OP_AND, r1, r2, r1);
385 375 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
386 376
387 377 dt_cg_setx(dlp, r2, fmask);
388 378 instr = DIF_INSTR_FMT(DIF_OP_AND, src->dn_reg, r2, r2);
389 379 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
390 380
391 381 dt_cg_setx(dlp, r3, shift);
392 382 instr = DIF_INSTR_FMT(DIF_OP_SLL, r2, r3, r2);
393 383 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
394 384
395 385 instr = DIF_INSTR_FMT(DIF_OP_OR, r1, r2, r1);
396 386 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
397 387
398 388 dt_regset_free(drp, r3);
399 389 dt_regset_free(drp, r2);
400 390
401 391 return (r1);
402 392 }
403 393
404 394 static void
405 395 dt_cg_store(dt_node_t *src, dt_irlist_t *dlp, dt_regset_t *drp, dt_node_t *dst)
406 396 {
407 397 ctf_encoding_t e;
408 398 dif_instr_t instr;
409 399 size_t size;
410 400 int reg;
411 401
412 402 /*
413 403 * If we're loading a bit-field, the size of our store is found by
414 404 * rounding dst's cte_bits up to a byte boundary and then finding the
415 405 * nearest power of two to this value (see clp2(), above).
416 406 */
417 407 if ((dst->dn_flags & DT_NF_BITFIELD) &&
418 408 ctf_type_encoding(dst->dn_ctfp, dst->dn_type, &e) != CTF_ERR)
419 409 size = clp2(P2ROUNDUP(e.cte_bits, NBBY) / NBBY);
420 410 else
421 411 size = dt_node_type_size(src);
422 412
423 413 if (src->dn_flags & DT_NF_REF) {
424 414 reg = dt_regset_alloc(drp);
425 415 dt_cg_setx(dlp, reg, size);
426 416 instr = DIF_INSTR_COPYS(src->dn_reg, reg, dst->dn_reg);
427 417 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
428 418 dt_regset_free(drp, reg);
429 419 } else {
430 420 if (dst->dn_flags & DT_NF_BITFIELD)
431 421 reg = dt_cg_field_set(src, dlp, drp, dst);
432 422 else
433 423 reg = src->dn_reg;
434 424
435 425 switch (size) {
436 426 case 1:
437 427 instr = DIF_INSTR_STORE(DIF_OP_STB, reg, dst->dn_reg);
438 428 break;
439 429 case 2:
440 430 instr = DIF_INSTR_STORE(DIF_OP_STH, reg, dst->dn_reg);
441 431 break;
442 432 case 4:
443 433 instr = DIF_INSTR_STORE(DIF_OP_STW, reg, dst->dn_reg);
444 434 break;
445 435 case 8:
446 436 instr = DIF_INSTR_STORE(DIF_OP_STX, reg, dst->dn_reg);
447 437 break;
448 438 default:
449 439 xyerror(D_UNKNOWN, "internal error -- cg cannot store "
450 440 "size %lu when passed by value\n", (ulong_t)size);
451 441 }
452 442 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
453 443
454 444 if (dst->dn_flags & DT_NF_BITFIELD)
455 445 dt_regset_free(drp, reg);
456 446 }
457 447 }
458 448
459 449 /*
460 450 * Generate code for a typecast or for argument promotion from the type of the
461 451 * actual to the type of the formal. We need to generate code for casts when
462 452 * a scalar type is being narrowed or changing signed-ness. We first shift the
463 453 * desired bits high (losing excess bits if narrowing) and then shift them down
464 454 * using logical shift (unsigned result) or arithmetic shift (signed result).
465 455 */
466 456 static void
467 457 dt_cg_typecast(const dt_node_t *src, const dt_node_t *dst,
468 458 dt_irlist_t *dlp, dt_regset_t *drp)
469 459 {
470 460 size_t srcsize = dt_node_type_size(src);
471 461 size_t dstsize = dt_node_type_size(dst);
472 462
473 463 dif_instr_t instr;
474 464 int rg;
475 465
476 466 if (!dt_node_is_scalar(dst))
477 467 return; /* not a scalar */
478 468 if (dstsize == srcsize &&
479 469 ((src->dn_flags ^ dst->dn_flags) & DT_NF_SIGNED) == 0)
480 470 return; /* not narrowing or changing signed-ness */
481 471 if (dstsize > srcsize && (src->dn_flags & DT_NF_SIGNED) == 0)
482 472 return; /* nothing to do in this case */
483 473
484 474 rg = dt_regset_alloc(drp);
485 475
486 476 if (dstsize > srcsize) {
487 477 int n = sizeof (uint64_t) * NBBY - srcsize * NBBY;
488 478 int s = (dstsize - srcsize) * NBBY;
489 479
490 480 dt_cg_setx(dlp, rg, n);
491 481
492 482 instr = DIF_INSTR_FMT(DIF_OP_SLL, src->dn_reg, rg, dst->dn_reg);
493 483 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
494 484
495 485 if ((dst->dn_flags & DT_NF_SIGNED) || n == s) {
496 486 instr = DIF_INSTR_FMT(DIF_OP_SRA,
497 487 dst->dn_reg, rg, dst->dn_reg);
498 488 dt_irlist_append(dlp,
499 489 dt_cg_node_alloc(DT_LBL_NONE, instr));
500 490 } else {
501 491 dt_cg_setx(dlp, rg, s);
502 492 instr = DIF_INSTR_FMT(DIF_OP_SRA,
503 493 dst->dn_reg, rg, dst->dn_reg);
504 494 dt_irlist_append(dlp,
505 495 dt_cg_node_alloc(DT_LBL_NONE, instr));
506 496 dt_cg_setx(dlp, rg, n - s);
507 497 instr = DIF_INSTR_FMT(DIF_OP_SRL,
508 498 dst->dn_reg, rg, dst->dn_reg);
509 499 dt_irlist_append(dlp,
510 500 dt_cg_node_alloc(DT_LBL_NONE, instr));
511 501 }
512 502 } else if (dstsize != sizeof (uint64_t)) {
513 503 int n = sizeof (uint64_t) * NBBY - dstsize * NBBY;
514 504
515 505 dt_cg_setx(dlp, rg, n);
516 506
517 507 instr = DIF_INSTR_FMT(DIF_OP_SLL, src->dn_reg, rg, dst->dn_reg);
518 508 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
519 509
520 510 instr = DIF_INSTR_FMT((dst->dn_flags & DT_NF_SIGNED) ?
521 511 DIF_OP_SRA : DIF_OP_SRL, dst->dn_reg, rg, dst->dn_reg);
522 512 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
523 513 }
524 514
525 515 dt_regset_free(drp, rg);
526 516 }
527 517
528 518 /*
529 519 * Generate code to push the specified argument list on to the tuple stack.
530 520 * We use this routine for handling subroutine calls and associative arrays.
531 521 * We must first generate code for all subexpressions before loading the stack
532 522 * because any subexpression could itself require the use of the tuple stack.
533 523 * This holds a number of registers equal to the number of arguments, but this
534 524 * is not a huge problem because the number of arguments can't exceed the
535 525 * number of tuple register stack elements anyway. At most one extra register
536 526 * is required (either by dt_cg_typecast() or for dtdt_size, below). This
537 527 * implies that a DIF implementation should offer a number of general purpose
538 528 * registers at least one greater than the number of tuple registers.
539 529 */
540 530 static void
541 531 dt_cg_arglist(dt_ident_t *idp, dt_node_t *args,
542 532 dt_irlist_t *dlp, dt_regset_t *drp)
543 533 {
544 534 const dt_idsig_t *isp = idp->di_data;
545 535 dt_node_t *dnp;
546 536 int i = 0;
547 537
548 538 for (dnp = args; dnp != NULL; dnp = dnp->dn_list)
549 539 dt_cg_node(dnp, dlp, drp);
550 540
551 541 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, DIF_INSTR_FLUSHTS));
552 542
553 543 for (dnp = args; dnp != NULL; dnp = dnp->dn_list, i++) {
554 544 dtrace_diftype_t t;
555 545 dif_instr_t instr;
556 546 uint_t op;
557 547 int reg;
558 548
559 549 dt_node_diftype(yypcb->pcb_hdl, dnp, &t);
560 550
561 551 isp->dis_args[i].dn_reg = dnp->dn_reg; /* re-use register */
562 552 dt_cg_typecast(dnp, &isp->dis_args[i], dlp, drp);
563 553 isp->dis_args[i].dn_reg = -1;
564 554
565 555 if (t.dtdt_flags & DIF_TF_BYREF) {
566 556 op = DIF_OP_PUSHTR;
567 557 if (t.dtdt_size != 0) {
568 558 reg = dt_regset_alloc(drp);
569 559 dt_cg_setx(dlp, reg, t.dtdt_size);
570 560 } else {
571 561 reg = DIF_REG_R0;
572 562 }
573 563 } else {
574 564 op = DIF_OP_PUSHTV;
575 565 reg = DIF_REG_R0;
576 566 }
577 567
578 568 instr = DIF_INSTR_PUSHTS(op, t.dtdt_kind, reg, dnp->dn_reg);
579 569 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
580 570 dt_regset_free(drp, dnp->dn_reg);
581 571
582 572 if (reg != DIF_REG_R0)
583 573 dt_regset_free(drp, reg);
584 574 }
585 575
586 576 if (i > yypcb->pcb_hdl->dt_conf.dtc_diftupregs)
587 577 longjmp(yypcb->pcb_jmpbuf, EDT_NOTUPREG);
588 578 }
589 579
590 580 static void
591 581 dt_cg_arithmetic_op(dt_node_t *dnp, dt_irlist_t *dlp,
592 582 dt_regset_t *drp, uint_t op)
593 583 {
594 584 int is_ptr_op = (dnp->dn_op == DT_TOK_ADD || dnp->dn_op == DT_TOK_SUB ||
595 585 dnp->dn_op == DT_TOK_ADD_EQ || dnp->dn_op == DT_TOK_SUB_EQ);
596 586
597 587 int lp_is_ptr = dt_node_is_pointer(dnp->dn_left);
598 588 int rp_is_ptr = dt_node_is_pointer(dnp->dn_right);
599 589
600 590 dif_instr_t instr;
601 591
602 592 if (lp_is_ptr && rp_is_ptr) {
603 593 assert(dnp->dn_op == DT_TOK_SUB);
604 594 is_ptr_op = 0;
605 595 }
606 596
607 597 dt_cg_node(dnp->dn_left, dlp, drp);
608 598 if (is_ptr_op && rp_is_ptr)
609 599 dt_cg_ptrsize(dnp, dlp, drp, DIF_OP_MUL, dnp->dn_left->dn_reg);
610 600
611 601 dt_cg_node(dnp->dn_right, dlp, drp);
612 602 if (is_ptr_op && lp_is_ptr)
613 603 dt_cg_ptrsize(dnp, dlp, drp, DIF_OP_MUL, dnp->dn_right->dn_reg);
614 604
615 605 instr = DIF_INSTR_FMT(op, dnp->dn_left->dn_reg,
616 606 dnp->dn_right->dn_reg, dnp->dn_left->dn_reg);
617 607
618 608 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
619 609 dt_regset_free(drp, dnp->dn_right->dn_reg);
620 610 dnp->dn_reg = dnp->dn_left->dn_reg;
621 611
622 612 if (lp_is_ptr && rp_is_ptr)
623 613 dt_cg_ptrsize(dnp->dn_right,
624 614 dlp, drp, DIF_OP_UDIV, dnp->dn_reg);
625 615 }
626 616
627 617 static uint_t
628 618 dt_cg_stvar(const dt_ident_t *idp)
629 619 {
630 620 static const uint_t aops[] = { DIF_OP_STGAA, DIF_OP_STTAA, DIF_OP_NOP };
631 621 static const uint_t sops[] = { DIF_OP_STGS, DIF_OP_STTS, DIF_OP_STLS };
632 622
633 623 uint_t i = (((idp->di_flags & DT_IDFLG_LOCAL) != 0) << 1) |
634 624 ((idp->di_flags & DT_IDFLG_TLS) != 0);
635 625
636 626 return (idp->di_kind == DT_IDENT_ARRAY ? aops[i] : sops[i]);
637 627 }
638 628
639 629 static void
640 630 dt_cg_prearith_op(dt_node_t *dnp, dt_irlist_t *dlp, dt_regset_t *drp, uint_t op)
641 631 {
642 632 ctf_file_t *ctfp = dnp->dn_ctfp;
643 633 dif_instr_t instr;
644 634 ctf_id_t type;
645 635 ssize_t size = 1;
646 636 int reg;
647 637
648 638 if (dt_node_is_pointer(dnp)) {
649 639 type = ctf_type_resolve(ctfp, dnp->dn_type);
650 640 assert(ctf_type_kind(ctfp, type) == CTF_K_POINTER);
651 641 size = ctf_type_size(ctfp, ctf_type_reference(ctfp, type));
652 642 }
653 643
654 644 dt_cg_node(dnp->dn_child, dlp, drp);
655 645 dnp->dn_reg = dnp->dn_child->dn_reg;
656 646
657 647 reg = dt_regset_alloc(drp);
658 648 dt_cg_setx(dlp, reg, size);
659 649
660 650 instr = DIF_INSTR_FMT(op, dnp->dn_reg, reg, dnp->dn_reg);
661 651 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
662 652 dt_regset_free(drp, reg);
663 653
664 654 /*
665 655 * If we are modifying a variable, generate an stv instruction from
666 656 * the variable specified by the identifier. If we are storing to a
667 657 * memory address, generate code again for the left-hand side using
668 658 * DT_NF_REF to get the address, and then generate a store to it.
669 659 * In both paths, we store the value in dnp->dn_reg (the new value).
670 660 */
671 661 if (dnp->dn_child->dn_kind == DT_NODE_VAR) {
672 662 dt_ident_t *idp = dt_ident_resolve(dnp->dn_child->dn_ident);
673 663
674 664 idp->di_flags |= DT_IDFLG_DIFW;
675 665 instr = DIF_INSTR_STV(dt_cg_stvar(idp),
676 666 idp->di_id, dnp->dn_reg);
677 667 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
678 668 } else {
679 669 uint_t rbit = dnp->dn_child->dn_flags & DT_NF_REF;
680 670
681 671 assert(dnp->dn_child->dn_flags & DT_NF_WRITABLE);
682 672 assert(dnp->dn_child->dn_flags & DT_NF_LVALUE);
683 673
684 674 dnp->dn_child->dn_flags |= DT_NF_REF; /* force pass-by-ref */
685 675 dt_cg_node(dnp->dn_child, dlp, drp);
686 676
687 677 dt_cg_store(dnp, dlp, drp, dnp->dn_child);
688 678 dt_regset_free(drp, dnp->dn_child->dn_reg);
689 679
690 680 dnp->dn_left->dn_flags &= ~DT_NF_REF;
691 681 dnp->dn_left->dn_flags |= rbit;
692 682 }
693 683 }
694 684
695 685 static void
696 686 dt_cg_postarith_op(dt_node_t *dnp, dt_irlist_t *dlp,
697 687 dt_regset_t *drp, uint_t op)
698 688 {
699 689 ctf_file_t *ctfp = dnp->dn_ctfp;
700 690 dif_instr_t instr;
701 691 ctf_id_t type;
702 692 ssize_t size = 1;
703 693 int nreg;
704 694
705 695 if (dt_node_is_pointer(dnp)) {
706 696 type = ctf_type_resolve(ctfp, dnp->dn_type);
707 697 assert(ctf_type_kind(ctfp, type) == CTF_K_POINTER);
708 698 size = ctf_type_size(ctfp, ctf_type_reference(ctfp, type));
709 699 }
710 700
711 701 dt_cg_node(dnp->dn_child, dlp, drp);
712 702 dnp->dn_reg = dnp->dn_child->dn_reg;
713 703
714 704 nreg = dt_regset_alloc(drp);
715 705 dt_cg_setx(dlp, nreg, size);
716 706 instr = DIF_INSTR_FMT(op, dnp->dn_reg, nreg, nreg);
717 707 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
718 708
719 709 /*
720 710 * If we are modifying a variable, generate an stv instruction from
721 711 * the variable specified by the identifier. If we are storing to a
722 712 * memory address, generate code again for the left-hand side using
723 713 * DT_NF_REF to get the address, and then generate a store to it.
724 714 * In both paths, we store the value from 'nreg' (the new value).
725 715 */
726 716 if (dnp->dn_child->dn_kind == DT_NODE_VAR) {
727 717 dt_ident_t *idp = dt_ident_resolve(dnp->dn_child->dn_ident);
728 718
729 719 idp->di_flags |= DT_IDFLG_DIFW;
730 720 instr = DIF_INSTR_STV(dt_cg_stvar(idp), idp->di_id, nreg);
731 721 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
732 722 } else {
733 723 uint_t rbit = dnp->dn_child->dn_flags & DT_NF_REF;
734 724 int oreg = dnp->dn_reg;
735 725
736 726 assert(dnp->dn_child->dn_flags & DT_NF_WRITABLE);
737 727 assert(dnp->dn_child->dn_flags & DT_NF_LVALUE);
738 728
739 729 dnp->dn_child->dn_flags |= DT_NF_REF; /* force pass-by-ref */
740 730 dt_cg_node(dnp->dn_child, dlp, drp);
741 731
742 732 dnp->dn_reg = nreg;
743 733 dt_cg_store(dnp, dlp, drp, dnp->dn_child);
744 734 dnp->dn_reg = oreg;
745 735
746 736 dt_regset_free(drp, dnp->dn_child->dn_reg);
747 737 dnp->dn_left->dn_flags &= ~DT_NF_REF;
748 738 dnp->dn_left->dn_flags |= rbit;
749 739 }
750 740
751 741 dt_regset_free(drp, nreg);
752 742 }
753 743
754 744 /*
755 745 * Determine if we should perform signed or unsigned comparison for an OP2.
756 746 * If both operands are of arithmetic type, perform the usual arithmetic
757 747 * conversions to determine the common real type for comparison [ISOC 6.5.8.3].
758 748 */
759 749 static int
760 750 dt_cg_compare_signed(dt_node_t *dnp)
761 751 {
762 752 dt_node_t dn;
763 753
764 754 if (dt_node_is_string(dnp->dn_left) ||
765 755 dt_node_is_string(dnp->dn_right))
766 756 return (1); /* strings always compare signed */
767 757 else if (!dt_node_is_arith(dnp->dn_left) ||
768 758 !dt_node_is_arith(dnp->dn_right))
769 759 return (0); /* non-arithmetic types always compare unsigned */
770 760
771 761 bzero(&dn, sizeof (dn));
772 762 dt_node_promote(dnp->dn_left, dnp->dn_right, &dn);
773 763 return (dn.dn_flags & DT_NF_SIGNED);
774 764 }
775 765
776 766 static void
777 767 dt_cg_compare_op(dt_node_t *dnp, dt_irlist_t *dlp, dt_regset_t *drp, uint_t op)
778 768 {
779 769 uint_t lbl_true = dt_irlist_label(dlp);
780 770 uint_t lbl_post = dt_irlist_label(dlp);
781 771
782 772 dif_instr_t instr;
783 773 uint_t opc;
784 774
785 775 dt_cg_node(dnp->dn_left, dlp, drp);
786 776 dt_cg_node(dnp->dn_right, dlp, drp);
787 777
788 778 if (dt_node_is_string(dnp->dn_left) || dt_node_is_string(dnp->dn_right))
789 779 opc = DIF_OP_SCMP;
790 780 else
791 781 opc = DIF_OP_CMP;
792 782
793 783 instr = DIF_INSTR_CMP(opc, dnp->dn_left->dn_reg, dnp->dn_right->dn_reg);
794 784 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
795 785 dt_regset_free(drp, dnp->dn_right->dn_reg);
796 786 dnp->dn_reg = dnp->dn_left->dn_reg;
797 787
798 788 instr = DIF_INSTR_BRANCH(op, lbl_true);
799 789 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
800 790
801 791 instr = DIF_INSTR_MOV(DIF_REG_R0, dnp->dn_reg);
802 792 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
803 793
804 794 instr = DIF_INSTR_BRANCH(DIF_OP_BA, lbl_post);
805 795 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
806 796
807 797 dt_cg_xsetx(dlp, NULL, lbl_true, dnp->dn_reg, 1);
808 798 dt_irlist_append(dlp, dt_cg_node_alloc(lbl_post, DIF_INSTR_NOP));
809 799 }
810 800
811 801 /*
812 802 * Code generation for the ternary op requires some trickery with the assembler
813 803 * in order to conserve registers. We generate code for dn_expr and dn_left
814 804 * and free their registers so they do not have be consumed across codegen for
815 805 * dn_right. We insert a dummy MOV at the end of dn_left into the destination
816 806 * register, which is not yet known because we haven't done dn_right yet, and
817 807 * save the pointer to this instruction node. We then generate code for
818 808 * dn_right and use its register as our output. Finally, we reach back and
819 809 * patch the instruction for dn_left to move its output into this register.
820 810 */
821 811 static void
822 812 dt_cg_ternary_op(dt_node_t *dnp, dt_irlist_t *dlp, dt_regset_t *drp)
823 813 {
824 814 uint_t lbl_false = dt_irlist_label(dlp);
825 815 uint_t lbl_post = dt_irlist_label(dlp);
826 816
827 817 dif_instr_t instr;
828 818 dt_irnode_t *dip;
829 819
830 820 dt_cg_node(dnp->dn_expr, dlp, drp);
831 821 instr = DIF_INSTR_TST(dnp->dn_expr->dn_reg);
832 822 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
833 823 dt_regset_free(drp, dnp->dn_expr->dn_reg);
834 824
835 825 instr = DIF_INSTR_BRANCH(DIF_OP_BE, lbl_false);
836 826 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
837 827
838 828 dt_cg_node(dnp->dn_left, dlp, drp);
839 829 instr = DIF_INSTR_MOV(dnp->dn_left->dn_reg, DIF_REG_R0);
840 830 dip = dt_cg_node_alloc(DT_LBL_NONE, instr); /* save dip for below */
841 831 dt_irlist_append(dlp, dip);
842 832 dt_regset_free(drp, dnp->dn_left->dn_reg);
843 833
844 834 instr = DIF_INSTR_BRANCH(DIF_OP_BA, lbl_post);
845 835 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
846 836
847 837 dt_irlist_append(dlp, dt_cg_node_alloc(lbl_false, DIF_INSTR_NOP));
848 838 dt_cg_node(dnp->dn_right, dlp, drp);
849 839 dnp->dn_reg = dnp->dn_right->dn_reg;
850 840
851 841 /*
852 842 * Now that dn_reg is assigned, reach back and patch the correct MOV
853 843 * instruction into the tail of dn_left. We know dn_reg was unused
854 844 * at that point because otherwise dn_right couldn't have allocated it.
855 845 */
856 846 dip->di_instr = DIF_INSTR_MOV(dnp->dn_left->dn_reg, dnp->dn_reg);
857 847 dt_irlist_append(dlp, dt_cg_node_alloc(lbl_post, DIF_INSTR_NOP));
858 848 }
859 849
860 850 static void
861 851 dt_cg_logical_and(dt_node_t *dnp, dt_irlist_t *dlp, dt_regset_t *drp)
862 852 {
863 853 uint_t lbl_false = dt_irlist_label(dlp);
864 854 uint_t lbl_post = dt_irlist_label(dlp);
865 855
866 856 dif_instr_t instr;
867 857
868 858 dt_cg_node(dnp->dn_left, dlp, drp);
869 859 instr = DIF_INSTR_TST(dnp->dn_left->dn_reg);
870 860 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
871 861 dt_regset_free(drp, dnp->dn_left->dn_reg);
872 862
873 863 instr = DIF_INSTR_BRANCH(DIF_OP_BE, lbl_false);
874 864 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
875 865
876 866 dt_cg_node(dnp->dn_right, dlp, drp);
877 867 instr = DIF_INSTR_TST(dnp->dn_right->dn_reg);
878 868 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
879 869 dnp->dn_reg = dnp->dn_right->dn_reg;
880 870
881 871 instr = DIF_INSTR_BRANCH(DIF_OP_BE, lbl_false);
882 872 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
883 873
884 874 dt_cg_setx(dlp, dnp->dn_reg, 1);
885 875
886 876 instr = DIF_INSTR_BRANCH(DIF_OP_BA, lbl_post);
887 877 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
888 878
889 879 instr = DIF_INSTR_MOV(DIF_REG_R0, dnp->dn_reg);
890 880 dt_irlist_append(dlp, dt_cg_node_alloc(lbl_false, instr));
891 881
892 882 dt_irlist_append(dlp, dt_cg_node_alloc(lbl_post, DIF_INSTR_NOP));
893 883 }
894 884
895 885 static void
896 886 dt_cg_logical_xor(dt_node_t *dnp, dt_irlist_t *dlp, dt_regset_t *drp)
897 887 {
898 888 uint_t lbl_next = dt_irlist_label(dlp);
899 889 uint_t lbl_tail = dt_irlist_label(dlp);
900 890
901 891 dif_instr_t instr;
902 892
903 893 dt_cg_node(dnp->dn_left, dlp, drp);
904 894 instr = DIF_INSTR_TST(dnp->dn_left->dn_reg);
905 895 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
906 896
907 897 instr = DIF_INSTR_BRANCH(DIF_OP_BE, lbl_next);
908 898 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
909 899 dt_cg_setx(dlp, dnp->dn_left->dn_reg, 1);
910 900
911 901 dt_irlist_append(dlp, dt_cg_node_alloc(lbl_next, DIF_INSTR_NOP));
912 902 dt_cg_node(dnp->dn_right, dlp, drp);
913 903
914 904 instr = DIF_INSTR_TST(dnp->dn_right->dn_reg);
915 905 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
916 906
917 907 instr = DIF_INSTR_BRANCH(DIF_OP_BE, lbl_tail);
918 908 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
919 909 dt_cg_setx(dlp, dnp->dn_right->dn_reg, 1);
920 910
921 911 instr = DIF_INSTR_FMT(DIF_OP_XOR, dnp->dn_left->dn_reg,
922 912 dnp->dn_right->dn_reg, dnp->dn_left->dn_reg);
923 913
924 914 dt_irlist_append(dlp, dt_cg_node_alloc(lbl_tail, instr));
925 915
926 916 dt_regset_free(drp, dnp->dn_right->dn_reg);
927 917 dnp->dn_reg = dnp->dn_left->dn_reg;
928 918 }
929 919
930 920 static void
931 921 dt_cg_logical_or(dt_node_t *dnp, dt_irlist_t *dlp, dt_regset_t *drp)
932 922 {
933 923 uint_t lbl_true = dt_irlist_label(dlp);
934 924 uint_t lbl_false = dt_irlist_label(dlp);
935 925 uint_t lbl_post = dt_irlist_label(dlp);
936 926
937 927 dif_instr_t instr;
938 928
939 929 dt_cg_node(dnp->dn_left, dlp, drp);
940 930 instr = DIF_INSTR_TST(dnp->dn_left->dn_reg);
941 931 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
942 932 dt_regset_free(drp, dnp->dn_left->dn_reg);
943 933
944 934 instr = DIF_INSTR_BRANCH(DIF_OP_BNE, lbl_true);
945 935 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
946 936
947 937 dt_cg_node(dnp->dn_right, dlp, drp);
948 938 instr = DIF_INSTR_TST(dnp->dn_right->dn_reg);
949 939 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
950 940 dnp->dn_reg = dnp->dn_right->dn_reg;
951 941
952 942 instr = DIF_INSTR_BRANCH(DIF_OP_BE, lbl_false);
953 943 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
954 944
955 945 dt_cg_xsetx(dlp, NULL, lbl_true, dnp->dn_reg, 1);
956 946
957 947 instr = DIF_INSTR_BRANCH(DIF_OP_BA, lbl_post);
958 948 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
959 949
960 950 instr = DIF_INSTR_MOV(DIF_REG_R0, dnp->dn_reg);
961 951 dt_irlist_append(dlp, dt_cg_node_alloc(lbl_false, instr));
962 952
963 953 dt_irlist_append(dlp, dt_cg_node_alloc(lbl_post, DIF_INSTR_NOP));
964 954 }
965 955
966 956 static void
967 957 dt_cg_logical_neg(dt_node_t *dnp, dt_irlist_t *dlp, dt_regset_t *drp)
968 958 {
969 959 uint_t lbl_zero = dt_irlist_label(dlp);
970 960 uint_t lbl_post = dt_irlist_label(dlp);
971 961
972 962 dif_instr_t instr;
973 963
974 964 dt_cg_node(dnp->dn_child, dlp, drp);
975 965 dnp->dn_reg = dnp->dn_child->dn_reg;
976 966
977 967 instr = DIF_INSTR_TST(dnp->dn_reg);
978 968 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
979 969
980 970 instr = DIF_INSTR_BRANCH(DIF_OP_BE, lbl_zero);
981 971 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
982 972
983 973 instr = DIF_INSTR_MOV(DIF_REG_R0, dnp->dn_reg);
984 974 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
985 975
986 976 instr = DIF_INSTR_BRANCH(DIF_OP_BA, lbl_post);
987 977 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
988 978
989 979 dt_cg_xsetx(dlp, NULL, lbl_zero, dnp->dn_reg, 1);
990 980 dt_irlist_append(dlp, dt_cg_node_alloc(lbl_post, DIF_INSTR_NOP));
991 981 }
992 982
993 983 static void
994 984 dt_cg_asgn_op(dt_node_t *dnp, dt_irlist_t *dlp, dt_regset_t *drp)
995 985 {
996 986 dif_instr_t instr;
997 987 dt_ident_t *idp;
998 988
999 989 /*
1000 990 * If we are performing a structure assignment of a translated type,
1001 991 * we must instantiate all members and create a snapshot of the object
1002 992 * in scratch space. We allocs a chunk of memory, generate code for
1003 993 * each member, and then set dnp->dn_reg to the scratch object address.
1004 994 */
1005 995 if ((idp = dt_node_resolve(dnp->dn_right, DT_IDENT_XLSOU)) != NULL) {
1006 996 ctf_membinfo_t ctm;
1007 997 dt_xlator_t *dxp = idp->di_data;
1008 998 dt_node_t *mnp, dn, mn;
1009 999 int r1, r2;
1010 1000
1011 1001 /*
1012 1002 * Create two fake dt_node_t's representing operator "." and a
1013 1003 * right-hand identifier child node. These will be repeatedly
1014 1004 * modified according to each instantiated member so that we
1015 1005 * can pass them to dt_cg_store() and effect a member store.
1016 1006 */
1017 1007 bzero(&dn, sizeof (dt_node_t));
1018 1008 dn.dn_kind = DT_NODE_OP2;
1019 1009 dn.dn_op = DT_TOK_DOT;
1020 1010 dn.dn_left = dnp;
1021 1011 dn.dn_right = &mn;
1022 1012
1023 1013 bzero(&mn, sizeof (dt_node_t));
1024 1014 mn.dn_kind = DT_NODE_IDENT;
1025 1015 mn.dn_op = DT_TOK_IDENT;
1026 1016
1027 1017 /*
1028 1018 * Allocate a register for our scratch data pointer. First we
1029 1019 * set it to the size of our data structure, and then replace
1030 1020 * it with the result of an allocs of the specified size.
1031 1021 */
1032 1022 r1 = dt_regset_alloc(drp);
1033 1023 dt_cg_setx(dlp, r1,
1034 1024 ctf_type_size(dxp->dx_dst_ctfp, dxp->dx_dst_base));
1035 1025
1036 1026 instr = DIF_INSTR_ALLOCS(r1, r1);
1037 1027 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
1038 1028
1039 1029 /*
1040 1030 * When dt_cg_asgn_op() is called, we have already generated
1041 1031 * code for dnp->dn_right, which is the translator input. We
1042 1032 * now associate this register with the translator's input
1043 1033 * identifier so it can be referenced during our member loop.
1044 1034 */
1045 1035 dxp->dx_ident->di_flags |= DT_IDFLG_CGREG;
1046 1036 dxp->dx_ident->di_id = dnp->dn_right->dn_reg;
1047 1037
1048 1038 for (mnp = dxp->dx_members; mnp != NULL; mnp = mnp->dn_list) {
1049 1039 /*
1050 1040 * Generate code for the translator member expression,
1051 1041 * and then cast the result to the member type.
1052 1042 */
1053 1043 dt_cg_node(mnp->dn_membexpr, dlp, drp);
1054 1044 mnp->dn_reg = mnp->dn_membexpr->dn_reg;
1055 1045 dt_cg_typecast(mnp->dn_membexpr, mnp, dlp, drp);
1056 1046
1057 1047 /*
1058 1048 * Ask CTF for the offset of the member so we can store
1059 1049 * to the appropriate offset. This call has already
1060 1050 * been done once by the parser, so it should succeed.
1061 1051 */
1062 1052 if (ctf_member_info(dxp->dx_dst_ctfp, dxp->dx_dst_base,
1063 1053 mnp->dn_membname, &ctm) == CTF_ERR) {
1064 1054 yypcb->pcb_hdl->dt_ctferr =
1065 1055 ctf_errno(dxp->dx_dst_ctfp);
1066 1056 longjmp(yypcb->pcb_jmpbuf, EDT_CTF);
1067 1057 }
1068 1058
1069 1059 /*
1070 1060 * If the destination member is at offset 0, store the
1071 1061 * result directly to r1 (the scratch buffer address).
1072 1062 * Otherwise allocate another temporary for the offset
1073 1063 * and add r1 to it before storing the result.
1074 1064 */
1075 1065 if (ctm.ctm_offset != 0) {
1076 1066 r2 = dt_regset_alloc(drp);
1077 1067
1078 1068 /*
1079 1069 * Add the member offset rounded down to the
1080 1070 * nearest byte. If the offset was not aligned
1081 1071 * on a byte boundary, this member is a bit-
1082 1072 * field and dt_cg_store() will handle masking.
1083 1073 */
1084 1074 dt_cg_setx(dlp, r2, ctm.ctm_offset / NBBY);
1085 1075 instr = DIF_INSTR_FMT(DIF_OP_ADD, r1, r2, r2);
1086 1076 dt_irlist_append(dlp,
1087 1077 dt_cg_node_alloc(DT_LBL_NONE, instr));
1088 1078
1089 1079 dt_node_type_propagate(mnp, &dn);
1090 1080 dn.dn_right->dn_string = mnp->dn_membname;
1091 1081 dn.dn_reg = r2;
1092 1082
1093 1083 dt_cg_store(mnp, dlp, drp, &dn);
1094 1084 dt_regset_free(drp, r2);
1095 1085
1096 1086 } else {
1097 1087 dt_node_type_propagate(mnp, &dn);
1098 1088 dn.dn_right->dn_string = mnp->dn_membname;
1099 1089 dn.dn_reg = r1;
1100 1090
1101 1091 dt_cg_store(mnp, dlp, drp, &dn);
1102 1092 }
1103 1093
1104 1094 dt_regset_free(drp, mnp->dn_reg);
1105 1095 }
1106 1096
1107 1097 dxp->dx_ident->di_flags &= ~DT_IDFLG_CGREG;
1108 1098 dxp->dx_ident->di_id = 0;
1109 1099
1110 1100 if (dnp->dn_right->dn_reg != -1)
1111 1101 dt_regset_free(drp, dnp->dn_right->dn_reg);
1112 1102
1113 1103 assert(dnp->dn_reg == dnp->dn_right->dn_reg);
1114 1104 dnp->dn_reg = r1;
1115 1105 }
1116 1106
1117 1107 /*
1118 1108 * If we are storing to a variable, generate an stv instruction from
1119 1109 * the variable specified by the identifier. If we are storing to a
1120 1110 * memory address, generate code again for the left-hand side using
1121 1111 * DT_NF_REF to get the address, and then generate a store to it.
1122 1112 * In both paths, we assume dnp->dn_reg already has the new value.
1123 1113 */
1124 1114 if (dnp->dn_left->dn_kind == DT_NODE_VAR) {
1125 1115 idp = dt_ident_resolve(dnp->dn_left->dn_ident);
1126 1116
1127 1117 if (idp->di_kind == DT_IDENT_ARRAY)
1128 1118 dt_cg_arglist(idp, dnp->dn_left->dn_args, dlp, drp);
1129 1119
1130 1120 idp->di_flags |= DT_IDFLG_DIFW;
1131 1121 instr = DIF_INSTR_STV(dt_cg_stvar(idp),
1132 1122 idp->di_id, dnp->dn_reg);
1133 1123 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
1134 1124 } else {
1135 1125 uint_t rbit = dnp->dn_left->dn_flags & DT_NF_REF;
1136 1126
1137 1127 assert(dnp->dn_left->dn_flags & DT_NF_WRITABLE);
1138 1128 assert(dnp->dn_left->dn_flags & DT_NF_LVALUE);
1139 1129
1140 1130 dnp->dn_left->dn_flags |= DT_NF_REF; /* force pass-by-ref */
1141 1131
1142 1132 dt_cg_node(dnp->dn_left, dlp, drp);
1143 1133 dt_cg_store(dnp, dlp, drp, dnp->dn_left);
1144 1134 dt_regset_free(drp, dnp->dn_left->dn_reg);
1145 1135
1146 1136 dnp->dn_left->dn_flags &= ~DT_NF_REF;
1147 1137 dnp->dn_left->dn_flags |= rbit;
1148 1138 }
1149 1139 }
1150 1140
1151 1141 static void
1152 1142 dt_cg_assoc_op(dt_node_t *dnp, dt_irlist_t *dlp, dt_regset_t *drp)
1153 1143 {
1154 1144 dif_instr_t instr;
1155 1145 uint_t op;
1156 1146
1157 1147 assert(dnp->dn_kind == DT_NODE_VAR);
1158 1148 assert(!(dnp->dn_ident->di_flags & DT_IDFLG_LOCAL));
1159 1149 assert(dnp->dn_args != NULL);
1160 1150
1161 1151 dt_cg_arglist(dnp->dn_ident, dnp->dn_args, dlp, drp);
1162 1152
1163 1153 dnp->dn_reg = dt_regset_alloc(drp);
1164 1154
1165 1155 if (dnp->dn_ident->di_flags & DT_IDFLG_TLS)
1166 1156 op = DIF_OP_LDTAA;
1167 1157 else
1168 1158 op = DIF_OP_LDGAA;
1169 1159
1170 1160 dnp->dn_ident->di_flags |= DT_IDFLG_DIFR;
1171 1161 instr = DIF_INSTR_LDV(op, dnp->dn_ident->di_id, dnp->dn_reg);
1172 1162 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
1173 1163
1174 1164 /*
1175 1165 * If the associative array is a pass-by-reference type, then we are
1176 1166 * loading its value as a pointer to either load or store through it.
1177 1167 * The array element in question may not have been faulted in yet, in
1178 1168 * which case DIF_OP_LD*AA will return zero. We append an epilogue
1179 1169 * of instructions similar to the following:
1180 1170 *
1181 1171 * ld?aa id, %r1 ! base ld?aa instruction above
1182 1172 * tst %r1 ! start of epilogue
1183 1173 * +--- bne label
1184 1174 * | setx size, %r1
1185 1175 * | allocs %r1, %r1
1186 1176 * | st?aa id, %r1
1187 1177 * | ld?aa id, %r1
1188 1178 * v
1189 1179 * label: < rest of code >
1190 1180 *
1191 1181 * The idea is that we allocs a zero-filled chunk of scratch space and
1192 1182 * do a DIF_OP_ST*AA to fault in and initialize the array element, and
1193 1183 * then reload it to get the faulted-in address of the new variable
1194 1184 * storage. This isn't cheap, but pass-by-ref associative array values
1195 1185 * are (thus far) uncommon and the allocs cost only occurs once. If
1196 1186 * this path becomes important to DTrace users, we can improve things
1197 1187 * by adding a new DIF opcode to fault in associative array elements.
1198 1188 */
1199 1189 if (dnp->dn_flags & DT_NF_REF) {
1200 1190 uint_t stvop = op == DIF_OP_LDTAA ? DIF_OP_STTAA : DIF_OP_STGAA;
1201 1191 uint_t label = dt_irlist_label(dlp);
1202 1192
1203 1193 instr = DIF_INSTR_TST(dnp->dn_reg);
1204 1194 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
1205 1195
1206 1196 instr = DIF_INSTR_BRANCH(DIF_OP_BNE, label);
1207 1197 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
1208 1198
1209 1199 dt_cg_setx(dlp, dnp->dn_reg, dt_node_type_size(dnp));
1210 1200 instr = DIF_INSTR_ALLOCS(dnp->dn_reg, dnp->dn_reg);
1211 1201 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
1212 1202
1213 1203 dnp->dn_ident->di_flags |= DT_IDFLG_DIFW;
1214 1204 instr = DIF_INSTR_STV(stvop, dnp->dn_ident->di_id, dnp->dn_reg);
1215 1205 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
1216 1206
1217 1207 instr = DIF_INSTR_LDV(op, dnp->dn_ident->di_id, dnp->dn_reg);
1218 1208 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
1219 1209
1220 1210 dt_irlist_append(dlp, dt_cg_node_alloc(label, DIF_INSTR_NOP));
1221 1211 }
1222 1212 }
1223 1213
1224 1214 static void
1225 1215 dt_cg_array_op(dt_node_t *dnp, dt_irlist_t *dlp, dt_regset_t *drp)
1226 1216 {
1227 1217 dt_probe_t *prp = yypcb->pcb_probe;
1228 1218 uintmax_t saved = dnp->dn_args->dn_value;
1229 1219 dt_ident_t *idp = dnp->dn_ident;
1230 1220
1231 1221 dif_instr_t instr;
1232 1222 uint_t op;
1233 1223 size_t size;
1234 1224 int reg, n;
1235 1225
1236 1226 assert(dnp->dn_kind == DT_NODE_VAR);
1237 1227 assert(!(idp->di_flags & DT_IDFLG_LOCAL));
1238 1228
1239 1229 assert(dnp->dn_args->dn_kind == DT_NODE_INT);
1240 1230 assert(dnp->dn_args->dn_list == NULL);
1241 1231
1242 1232 /*
1243 1233 * If this is a reference in the args[] array, temporarily modify the
1244 1234 * array index according to the static argument mapping (if any),
1245 1235 * unless the argument reference is provided by a dynamic translator.
1246 1236 * If we're using a dynamic translator for args[], then just set dn_reg
1247 1237 * to an invalid reg and return: DIF_OP_XLARG will fetch the arg later.
1248 1238 */
1249 1239 if (idp->di_id == DIF_VAR_ARGS) {
1250 1240 if ((idp->di_kind == DT_IDENT_XLPTR ||
1251 1241 idp->di_kind == DT_IDENT_XLSOU) &&
1252 1242 dt_xlator_dynamic(idp->di_data)) {
1253 1243 dnp->dn_reg = -1;
1254 1244 return;
1255 1245 }
1256 1246 dnp->dn_args->dn_value = prp->pr_mapping[saved];
1257 1247 }
1258 1248
1259 1249 dt_cg_node(dnp->dn_args, dlp, drp);
1260 1250 dnp->dn_args->dn_value = saved;
1261 1251
1262 1252 dnp->dn_reg = dnp->dn_args->dn_reg;
1263 1253
1264 1254 if (idp->di_flags & DT_IDFLG_TLS)
1265 1255 op = DIF_OP_LDTA;
1266 1256 else
1267 1257 op = DIF_OP_LDGA;
1268 1258
1269 1259 idp->di_flags |= DT_IDFLG_DIFR;
1270 1260
1271 1261 instr = DIF_INSTR_LDA(op, idp->di_id,
1272 1262 dnp->dn_args->dn_reg, dnp->dn_reg);
1273 1263
1274 1264 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
1275 1265
1276 1266 /*
1277 1267 * If this is a reference to the args[] array, we need to take the
1278 1268 * additional step of explicitly eliminating any bits larger than the
1279 1269 * type size: the DIF interpreter in the kernel will always give us
1280 1270 * the raw (64-bit) argument value, and any bits larger than the type
1281 1271 * size may be junk. As a practical matter, this arises only on 64-bit
1282 1272 * architectures and only when the argument index is larger than the
1283 1273 * number of arguments passed directly to DTrace: if a 8-, 16- or
1284 1274 * 32-bit argument must be retrieved from the stack, it is possible
1285 1275 * (and it some cases, likely) that the upper bits will be garbage.
1286 1276 */
1287 1277 if (idp->di_id != DIF_VAR_ARGS || !dt_node_is_scalar(dnp))
1288 1278 return;
1289 1279
1290 1280 if ((size = dt_node_type_size(dnp)) == sizeof (uint64_t))
1291 1281 return;
1292 1282
1293 1283 reg = dt_regset_alloc(drp);
1294 1284 assert(size < sizeof (uint64_t));
1295 1285 n = sizeof (uint64_t) * NBBY - size * NBBY;
1296 1286
1297 1287 dt_cg_setx(dlp, reg, n);
1298 1288
1299 1289 instr = DIF_INSTR_FMT(DIF_OP_SLL, dnp->dn_reg, reg, dnp->dn_reg);
1300 1290 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
1301 1291
1302 1292 instr = DIF_INSTR_FMT((dnp->dn_flags & DT_NF_SIGNED) ?
1303 1293 DIF_OP_SRA : DIF_OP_SRL, dnp->dn_reg, reg, dnp->dn_reg);
1304 1294
1305 1295 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
1306 1296 dt_regset_free(drp, reg);
1307 1297 }
1308 1298
1309 1299 /*
1310 1300 * Generate code for an inlined variable reference. Inlines can be used to
1311 1301 * define either scalar or associative array substitutions. For scalars, we
1312 1302 * simply generate code for the parse tree saved in the identifier's din_root,
1313 1303 * and then cast the resulting expression to the inline's declaration type.
1314 1304 * For arrays, we take the input parameter subtrees from dnp->dn_args and
1315 1305 * temporarily store them in the din_root of each din_argv[i] identifier,
1316 1306 * which are themselves inlines and were set up for us by the parser. The
1317 1307 * result is that any reference to the inlined parameter inside the top-level
1318 1308 * din_root will turn into a recursive call to dt_cg_inline() for a scalar
1319 1309 * inline whose din_root will refer to the subtree pointed to by the argument.
1320 1310 */
1321 1311 static void
1322 1312 dt_cg_inline(dt_node_t *dnp, dt_irlist_t *dlp, dt_regset_t *drp)
1323 1313 {
1324 1314 dt_ident_t *idp = dnp->dn_ident;
1325 1315 dt_idnode_t *inp = idp->di_iarg;
1326 1316
1327 1317 dt_idnode_t *pinp;
1328 1318 dt_node_t *pnp;
1329 1319 int i;
1330 1320
1331 1321 assert(idp->di_flags & DT_IDFLG_INLINE);
1332 1322 assert(idp->di_ops == &dt_idops_inline);
1333 1323
1334 1324 if (idp->di_kind == DT_IDENT_ARRAY) {
1335 1325 for (i = 0, pnp = dnp->dn_args;
1336 1326 pnp != NULL; pnp = pnp->dn_list, i++) {
1337 1327 if (inp->din_argv[i] != NULL) {
1338 1328 pinp = inp->din_argv[i]->di_iarg;
1339 1329 pinp->din_root = pnp;
1340 1330 }
1341 1331 }
1342 1332 }
1343 1333
1344 1334 dt_cg_node(inp->din_root, dlp, drp);
1345 1335 dnp->dn_reg = inp->din_root->dn_reg;
1346 1336 dt_cg_typecast(inp->din_root, dnp, dlp, drp);
1347 1337
1348 1338 if (idp->di_kind == DT_IDENT_ARRAY) {
1349 1339 for (i = 0; i < inp->din_argc; i++) {
1350 1340 pinp = inp->din_argv[i]->di_iarg;
1351 1341 pinp->din_root = NULL;
1352 1342 }
1353 1343 }
1354 1344 }
1355 1345
1356 1346 typedef struct dt_xlmemb {
1357 1347 dt_ident_t *dtxl_idp; /* translated ident */
1358 1348 dt_irlist_t *dtxl_dlp; /* instruction list */
1359 1349 dt_regset_t *dtxl_drp; /* register set */
1360 1350 int dtxl_sreg; /* location of the translation input */
1361 1351 int dtxl_dreg; /* location of our allocated buffer */
1362 1352 } dt_xlmemb_t;
1363 1353
1364 1354 /*ARGSUSED*/
1365 1355 static int
1366 1356 dt_cg_xlate_member(const char *name, ctf_id_t type, ulong_t off, void *arg)
1367 1357 {
1368 1358 dt_xlmemb_t *dx = arg;
1369 1359 dt_ident_t *idp = dx->dtxl_idp;
1370 1360 dt_irlist_t *dlp = dx->dtxl_dlp;
1371 1361 dt_regset_t *drp = dx->dtxl_drp;
1372 1362
1373 1363 dt_node_t *mnp;
1374 1364 dt_xlator_t *dxp;
1375 1365
1376 1366 int reg, treg;
1377 1367 uint32_t instr;
1378 1368 size_t size;
1379 1369
1380 1370 /* Generate code for the translation. */
1381 1371 dxp = idp->di_data;
1382 1372 mnp = dt_xlator_member(dxp, name);
1383 1373
1384 1374 /* If there's no translator for the given member, skip it. */
1385 1375 if (mnp == NULL)
1386 1376 return (0);
1387 1377
1388 1378 dxp->dx_ident->di_flags |= DT_IDFLG_CGREG;
1389 1379 dxp->dx_ident->di_id = dx->dtxl_sreg;
1390 1380
1391 1381 dt_cg_node(mnp->dn_membexpr, dlp, drp);
1392 1382
1393 1383 dxp->dx_ident->di_flags &= ~DT_IDFLG_CGREG;
1394 1384 dxp->dx_ident->di_id = 0;
1395 1385
1396 1386 treg = mnp->dn_membexpr->dn_reg;
1397 1387
1398 1388 /* Compute the offset into our buffer and store the result there. */
1399 1389 reg = dt_regset_alloc(drp);
1400 1390
1401 1391 dt_cg_setx(dlp, reg, off / NBBY);
1402 1392 instr = DIF_INSTR_FMT(DIF_OP_ADD, dx->dtxl_dreg, reg, reg);
1403 1393 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
1404 1394
1405 1395 size = ctf_type_size(mnp->dn_membexpr->dn_ctfp,
1406 1396 mnp->dn_membexpr->dn_type);
1407 1397 if (dt_node_is_scalar(mnp->dn_membexpr)) {
1408 1398 /*
1409 1399 * Copying scalars is simple.
1410 1400 */
1411 1401 switch (size) {
1412 1402 case 1:
1413 1403 instr = DIF_INSTR_STORE(DIF_OP_STB, treg, reg);
1414 1404 break;
1415 1405 case 2:
1416 1406 instr = DIF_INSTR_STORE(DIF_OP_STH, treg, reg);
1417 1407 break;
1418 1408 case 4:
1419 1409 instr = DIF_INSTR_STORE(DIF_OP_STW, treg, reg);
1420 1410 break;
1421 1411 case 8:
1422 1412 instr = DIF_INSTR_STORE(DIF_OP_STX, treg, reg);
1423 1413 break;
1424 1414 default:
1425 1415 xyerror(D_UNKNOWN, "internal error -- unexpected "
1426 1416 "size: %lu\n", (ulong_t)size);
1427 1417 }
1428 1418
1429 1419 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
1430 1420
1431 1421 } else if (dt_node_is_string(mnp->dn_membexpr)) {
1432 1422 int szreg;
1433 1423
1434 1424 /*
1435 1425 * Use the copys instruction for strings.
1436 1426 */
1437 1427 szreg = dt_regset_alloc(drp);
1438 1428 dt_cg_setx(dlp, szreg, size);
1439 1429 instr = DIF_INSTR_COPYS(treg, szreg, reg);
1440 1430 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
1441 1431 dt_regset_free(drp, szreg);
1442 1432 } else {
1443 1433 int szreg;
1444 1434
1445 1435 /*
1446 1436 * If it's anything else then we'll just bcopy it.
1447 1437 */
1448 1438 szreg = dt_regset_alloc(drp);
1449 1439 dt_cg_setx(dlp, szreg, size);
1450 1440 dt_irlist_append(dlp,
1451 1441 dt_cg_node_alloc(DT_LBL_NONE, DIF_INSTR_FLUSHTS));
1452 1442 instr = DIF_INSTR_PUSHTS(DIF_OP_PUSHTV, DIF_TYPE_CTF,
1453 1443 DIF_REG_R0, treg);
1454 1444 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
1455 1445 instr = DIF_INSTR_PUSHTS(DIF_OP_PUSHTV, DIF_TYPE_CTF,
1456 1446 DIF_REG_R0, reg);
1457 1447 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
1458 1448 instr = DIF_INSTR_PUSHTS(DIF_OP_PUSHTV, DIF_TYPE_CTF,
1459 1449 DIF_REG_R0, szreg);
1460 1450 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
1461 1451 instr = DIF_INSTR_CALL(DIF_SUBR_BCOPY, szreg);
1462 1452 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
1463 1453 dt_regset_free(drp, szreg);
1464 1454 }
1465 1455
1466 1456 dt_regset_free(drp, reg);
1467 1457 dt_regset_free(drp, treg);
1468 1458
1469 1459 return (0);
1470 1460 }
1471 1461
1472 1462 /*
1473 1463 * If we're expanding a translated type, we create an appropriately sized
1474 1464 * buffer with alloca() and then translate each member into it.
1475 1465 */
1476 1466 static int
1477 1467 dt_cg_xlate_expand(dt_node_t *dnp, dt_ident_t *idp, dt_irlist_t *dlp,
1478 1468 dt_regset_t *drp)
1479 1469 {
1480 1470 dt_xlmemb_t dlm;
1481 1471 uint32_t instr;
1482 1472 int dreg;
1483 1473 size_t size;
1484 1474
1485 1475 dreg = dt_regset_alloc(drp);
1486 1476 size = ctf_type_size(dnp->dn_ident->di_ctfp, dnp->dn_ident->di_type);
1487 1477
1488 1478 /* Call alloca() to create the buffer. */
1489 1479 dt_cg_setx(dlp, dreg, size);
1490 1480
1491 1481 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, DIF_INSTR_FLUSHTS));
1492 1482
1493 1483 instr = DIF_INSTR_PUSHTS(DIF_OP_PUSHTV, DIF_TYPE_CTF, DIF_REG_R0, dreg);
1494 1484 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
1495 1485
1496 1486 instr = DIF_INSTR_CALL(DIF_SUBR_ALLOCA, dreg);
1497 1487 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
1498 1488
1499 1489 /* Generate the translation for each member. */
1500 1490 dlm.dtxl_idp = idp;
1501 1491 dlm.dtxl_dlp = dlp;
1502 1492 dlm.dtxl_drp = drp;
1503 1493 dlm.dtxl_sreg = dnp->dn_reg;
1504 1494 dlm.dtxl_dreg = dreg;
1505 1495 (void) ctf_member_iter(dnp->dn_ident->di_ctfp,
1506 1496 dnp->dn_ident->di_type, dt_cg_xlate_member,
1507 1497 &dlm);
1508 1498
1509 1499 return (dreg);
1510 1500 }
1511 1501
1512 1502 static void
1513 1503 dt_cg_node(dt_node_t *dnp, dt_irlist_t *dlp, dt_regset_t *drp)
1514 1504 {
1515 1505 ctf_file_t *ctfp = dnp->dn_ctfp;
1516 1506 ctf_file_t *octfp;
1517 1507 ctf_membinfo_t m;
1518 1508 ctf_id_t type;
1519 1509
1520 1510 dif_instr_t instr;
1521 1511 dt_ident_t *idp;
1522 1512 ssize_t stroff;
1523 1513 uint_t op;
1524 1514
1525 1515 switch (dnp->dn_op) {
1526 1516 case DT_TOK_COMMA:
1527 1517 dt_cg_node(dnp->dn_left, dlp, drp);
1528 1518 dt_regset_free(drp, dnp->dn_left->dn_reg);
1529 1519 dt_cg_node(dnp->dn_right, dlp, drp);
1530 1520 dnp->dn_reg = dnp->dn_right->dn_reg;
1531 1521 break;
1532 1522
1533 1523 case DT_TOK_ASGN:
1534 1524 dt_cg_node(dnp->dn_right, dlp, drp);
1535 1525 dnp->dn_reg = dnp->dn_right->dn_reg;
1536 1526 dt_cg_asgn_op(dnp, dlp, drp);
1537 1527 break;
1538 1528
1539 1529 case DT_TOK_ADD_EQ:
1540 1530 dt_cg_arithmetic_op(dnp, dlp, drp, DIF_OP_ADD);
1541 1531 dt_cg_asgn_op(dnp, dlp, drp);
1542 1532 break;
1543 1533
1544 1534 case DT_TOK_SUB_EQ:
1545 1535 dt_cg_arithmetic_op(dnp, dlp, drp, DIF_OP_SUB);
1546 1536 dt_cg_asgn_op(dnp, dlp, drp);
1547 1537 break;
1548 1538
1549 1539 case DT_TOK_MUL_EQ:
1550 1540 dt_cg_arithmetic_op(dnp, dlp, drp, DIF_OP_MUL);
1551 1541 dt_cg_asgn_op(dnp, dlp, drp);
1552 1542 break;
1553 1543
1554 1544 case DT_TOK_DIV_EQ:
1555 1545 dt_cg_arithmetic_op(dnp, dlp, drp,
1556 1546 (dnp->dn_flags & DT_NF_SIGNED) ? DIF_OP_SDIV : DIF_OP_UDIV);
1557 1547 dt_cg_asgn_op(dnp, dlp, drp);
1558 1548 break;
1559 1549
1560 1550 case DT_TOK_MOD_EQ:
1561 1551 dt_cg_arithmetic_op(dnp, dlp, drp,
1562 1552 (dnp->dn_flags & DT_NF_SIGNED) ? DIF_OP_SREM : DIF_OP_UREM);
1563 1553 dt_cg_asgn_op(dnp, dlp, drp);
1564 1554 break;
1565 1555
1566 1556 case DT_TOK_AND_EQ:
1567 1557 dt_cg_arithmetic_op(dnp, dlp, drp, DIF_OP_AND);
1568 1558 dt_cg_asgn_op(dnp, dlp, drp);
1569 1559 break;
1570 1560
1571 1561 case DT_TOK_XOR_EQ:
1572 1562 dt_cg_arithmetic_op(dnp, dlp, drp, DIF_OP_XOR);
1573 1563 dt_cg_asgn_op(dnp, dlp, drp);
1574 1564 break;
1575 1565
1576 1566 case DT_TOK_OR_EQ:
1577 1567 dt_cg_arithmetic_op(dnp, dlp, drp, DIF_OP_OR);
1578 1568 dt_cg_asgn_op(dnp, dlp, drp);
1579 1569 break;
1580 1570
1581 1571 case DT_TOK_LSH_EQ:
1582 1572 dt_cg_arithmetic_op(dnp, dlp, drp, DIF_OP_SLL);
1583 1573 dt_cg_asgn_op(dnp, dlp, drp);
1584 1574 break;
1585 1575
1586 1576 case DT_TOK_RSH_EQ:
1587 1577 dt_cg_arithmetic_op(dnp, dlp, drp,
1588 1578 (dnp->dn_flags & DT_NF_SIGNED) ? DIF_OP_SRA : DIF_OP_SRL);
1589 1579 dt_cg_asgn_op(dnp, dlp, drp);
1590 1580 break;
1591 1581
1592 1582 case DT_TOK_QUESTION:
1593 1583 dt_cg_ternary_op(dnp, dlp, drp);
1594 1584 break;
1595 1585
1596 1586 case DT_TOK_LOR:
1597 1587 dt_cg_logical_or(dnp, dlp, drp);
1598 1588 break;
1599 1589
1600 1590 case DT_TOK_LXOR:
1601 1591 dt_cg_logical_xor(dnp, dlp, drp);
1602 1592 break;
1603 1593
1604 1594 case DT_TOK_LAND:
1605 1595 dt_cg_logical_and(dnp, dlp, drp);
1606 1596 break;
1607 1597
1608 1598 case DT_TOK_BOR:
1609 1599 dt_cg_arithmetic_op(dnp, dlp, drp, DIF_OP_OR);
1610 1600 break;
1611 1601
1612 1602 case DT_TOK_XOR:
1613 1603 dt_cg_arithmetic_op(dnp, dlp, drp, DIF_OP_XOR);
1614 1604 break;
1615 1605
1616 1606 case DT_TOK_BAND:
1617 1607 dt_cg_arithmetic_op(dnp, dlp, drp, DIF_OP_AND);
1618 1608 break;
1619 1609
1620 1610 case DT_TOK_EQU:
1621 1611 dt_cg_compare_op(dnp, dlp, drp, DIF_OP_BE);
1622 1612 break;
1623 1613
1624 1614 case DT_TOK_NEQ:
1625 1615 dt_cg_compare_op(dnp, dlp, drp, DIF_OP_BNE);
1626 1616 break;
1627 1617
1628 1618 case DT_TOK_LT:
1629 1619 dt_cg_compare_op(dnp, dlp, drp,
1630 1620 dt_cg_compare_signed(dnp) ? DIF_OP_BL : DIF_OP_BLU);
1631 1621 break;
1632 1622
1633 1623 case DT_TOK_LE:
1634 1624 dt_cg_compare_op(dnp, dlp, drp,
1635 1625 dt_cg_compare_signed(dnp) ? DIF_OP_BLE : DIF_OP_BLEU);
1636 1626 break;
1637 1627
1638 1628 case DT_TOK_GT:
1639 1629 dt_cg_compare_op(dnp, dlp, drp,
1640 1630 dt_cg_compare_signed(dnp) ? DIF_OP_BG : DIF_OP_BGU);
1641 1631 break;
1642 1632
1643 1633 case DT_TOK_GE:
1644 1634 dt_cg_compare_op(dnp, dlp, drp,
1645 1635 dt_cg_compare_signed(dnp) ? DIF_OP_BGE : DIF_OP_BGEU);
1646 1636 break;
1647 1637
1648 1638 case DT_TOK_LSH:
1649 1639 dt_cg_arithmetic_op(dnp, dlp, drp, DIF_OP_SLL);
1650 1640 break;
1651 1641
1652 1642 case DT_TOK_RSH:
1653 1643 dt_cg_arithmetic_op(dnp, dlp, drp,
1654 1644 (dnp->dn_flags & DT_NF_SIGNED) ? DIF_OP_SRA : DIF_OP_SRL);
1655 1645 break;
1656 1646
1657 1647 case DT_TOK_ADD:
1658 1648 dt_cg_arithmetic_op(dnp, dlp, drp, DIF_OP_ADD);
1659 1649 break;
1660 1650
1661 1651 case DT_TOK_SUB:
1662 1652 dt_cg_arithmetic_op(dnp, dlp, drp, DIF_OP_SUB);
1663 1653 break;
1664 1654
1665 1655 case DT_TOK_MUL:
1666 1656 dt_cg_arithmetic_op(dnp, dlp, drp, DIF_OP_MUL);
1667 1657 break;
1668 1658
1669 1659 case DT_TOK_DIV:
1670 1660 dt_cg_arithmetic_op(dnp, dlp, drp,
1671 1661 (dnp->dn_flags & DT_NF_SIGNED) ? DIF_OP_SDIV : DIF_OP_UDIV);
1672 1662 break;
1673 1663
1674 1664 case DT_TOK_MOD:
1675 1665 dt_cg_arithmetic_op(dnp, dlp, drp,
1676 1666 (dnp->dn_flags & DT_NF_SIGNED) ? DIF_OP_SREM : DIF_OP_UREM);
1677 1667 break;
1678 1668
1679 1669 case DT_TOK_LNEG:
1680 1670 dt_cg_logical_neg(dnp, dlp, drp);
1681 1671 break;
1682 1672
1683 1673 case DT_TOK_BNEG:
1684 1674 dt_cg_node(dnp->dn_child, dlp, drp);
1685 1675 dnp->dn_reg = dnp->dn_child->dn_reg;
1686 1676 instr = DIF_INSTR_NOT(dnp->dn_reg, dnp->dn_reg);
1687 1677 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
1688 1678 break;
1689 1679
1690 1680 case DT_TOK_PREINC:
1691 1681 dt_cg_prearith_op(dnp, dlp, drp, DIF_OP_ADD);
1692 1682 break;
1693 1683
1694 1684 case DT_TOK_POSTINC:
1695 1685 dt_cg_postarith_op(dnp, dlp, drp, DIF_OP_ADD);
1696 1686 break;
1697 1687
1698 1688 case DT_TOK_PREDEC:
1699 1689 dt_cg_prearith_op(dnp, dlp, drp, DIF_OP_SUB);
1700 1690 break;
1701 1691
1702 1692 case DT_TOK_POSTDEC:
1703 1693 dt_cg_postarith_op(dnp, dlp, drp, DIF_OP_SUB);
1704 1694 break;
1705 1695
1706 1696 case DT_TOK_IPOS:
1707 1697 dt_cg_node(dnp->dn_child, dlp, drp);
1708 1698 dnp->dn_reg = dnp->dn_child->dn_reg;
1709 1699 break;
1710 1700
1711 1701 case DT_TOK_INEG:
1712 1702 dt_cg_node(dnp->dn_child, dlp, drp);
1713 1703 dnp->dn_reg = dnp->dn_child->dn_reg;
1714 1704
1715 1705 instr = DIF_INSTR_FMT(DIF_OP_SUB, DIF_REG_R0,
1716 1706 dnp->dn_reg, dnp->dn_reg);
1717 1707
1718 1708 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
1719 1709 break;
1720 1710
1721 1711 case DT_TOK_DEREF:
1722 1712 dt_cg_node(dnp->dn_child, dlp, drp);
1723 1713 dnp->dn_reg = dnp->dn_child->dn_reg;
1724 1714
1725 1715 if (dt_node_is_dynamic(dnp->dn_child)) {
1726 1716 int reg;
1727 1717 idp = dt_node_resolve(dnp->dn_child, DT_IDENT_XLPTR);
1728 1718 assert(idp != NULL);
1729 1719 reg = dt_cg_xlate_expand(dnp, idp, dlp, drp);
1730 1720
1731 1721 dt_regset_free(drp, dnp->dn_child->dn_reg);
1732 1722 dnp->dn_reg = reg;
1733 1723
1734 1724 } else if (!(dnp->dn_flags & DT_NF_REF)) {
1735 1725 uint_t ubit = dnp->dn_flags & DT_NF_USERLAND;
1736 1726
1737 1727 /*
1738 1728 * Save and restore DT_NF_USERLAND across dt_cg_load():
1739 1729 * we need the sign bit from dnp and the user bit from
1740 1730 * dnp->dn_child in order to get the proper opcode.
1741 1731 */
1742 1732 dnp->dn_flags |=
1743 1733 (dnp->dn_child->dn_flags & DT_NF_USERLAND);
1744 1734
1745 1735 instr = DIF_INSTR_LOAD(dt_cg_load(dnp, ctfp,
1746 1736 dnp->dn_type), dnp->dn_reg, dnp->dn_reg);
1747 1737
1748 1738 dnp->dn_flags &= ~DT_NF_USERLAND;
1749 1739 dnp->dn_flags |= ubit;
1750 1740
1751 1741 dt_irlist_append(dlp,
1752 1742 dt_cg_node_alloc(DT_LBL_NONE, instr));
1753 1743 }
1754 1744 break;
1755 1745
1756 1746 case DT_TOK_ADDROF: {
1757 1747 uint_t rbit = dnp->dn_child->dn_flags & DT_NF_REF;
1758 1748
1759 1749 dnp->dn_child->dn_flags |= DT_NF_REF; /* force pass-by-ref */
1760 1750 dt_cg_node(dnp->dn_child, dlp, drp);
1761 1751 dnp->dn_reg = dnp->dn_child->dn_reg;
1762 1752
1763 1753 dnp->dn_child->dn_flags &= ~DT_NF_REF;
1764 1754 dnp->dn_child->dn_flags |= rbit;
1765 1755 break;
1766 1756 }
1767 1757
1768 1758 case DT_TOK_SIZEOF: {
1769 1759 size_t size = dt_node_sizeof(dnp->dn_child);
1770 1760 dnp->dn_reg = dt_regset_alloc(drp);
1771 1761 assert(size != 0);
1772 1762 dt_cg_setx(dlp, dnp->dn_reg, size);
1773 1763 break;
1774 1764 }
1775 1765
1776 1766 case DT_TOK_STRINGOF:
1777 1767 dt_cg_node(dnp->dn_child, dlp, drp);
1778 1768 dnp->dn_reg = dnp->dn_child->dn_reg;
1779 1769 break;
1780 1770
1781 1771 case DT_TOK_XLATE:
1782 1772 /*
1783 1773 * An xlate operator appears in either an XLATOR, indicating a
1784 1774 * reference to a dynamic translator, or an OP2, indicating
1785 1775 * use of the xlate operator in the user's program. For the
1786 1776 * dynamic case, generate an xlate opcode with a reference to
1787 1777 * the corresponding member, pre-computed for us in dn_members.
1788 1778 */
1789 1779 if (dnp->dn_kind == DT_NODE_XLATOR) {
1790 1780 dt_xlator_t *dxp = dnp->dn_xlator;
1791 1781
1792 1782 assert(dxp->dx_ident->di_flags & DT_IDFLG_CGREG);
1793 1783 assert(dxp->dx_ident->di_id != 0);
1794 1784
1795 1785 dnp->dn_reg = dt_regset_alloc(drp);
1796 1786
1797 1787 if (dxp->dx_arg == -1) {
1798 1788 instr = DIF_INSTR_MOV(
1799 1789 dxp->dx_ident->di_id, dnp->dn_reg);
1800 1790 dt_irlist_append(dlp,
1801 1791 dt_cg_node_alloc(DT_LBL_NONE, instr));
1802 1792 op = DIF_OP_XLATE;
1803 1793 } else
1804 1794 op = DIF_OP_XLARG;
1805 1795
1806 1796 instr = DIF_INSTR_XLATE(op, 0, dnp->dn_reg);
1807 1797 dt_irlist_append(dlp,
1808 1798 dt_cg_node_alloc(DT_LBL_NONE, instr));
1809 1799
1810 1800 dlp->dl_last->di_extern = dnp->dn_xmember;
1811 1801 break;
1812 1802 }
1813 1803
1814 1804 assert(dnp->dn_kind == DT_NODE_OP2);
1815 1805 dt_cg_node(dnp->dn_right, dlp, drp);
1816 1806 dnp->dn_reg = dnp->dn_right->dn_reg;
1817 1807 break;
1818 1808
1819 1809 case DT_TOK_LPAR:
1820 1810 dt_cg_node(dnp->dn_right, dlp, drp);
1821 1811 dnp->dn_reg = dnp->dn_right->dn_reg;
1822 1812 dt_cg_typecast(dnp->dn_right, dnp, dlp, drp);
1823 1813 break;
1824 1814
1825 1815 case DT_TOK_PTR:
1826 1816 case DT_TOK_DOT:
1827 1817 assert(dnp->dn_right->dn_kind == DT_NODE_IDENT);
1828 1818 dt_cg_node(dnp->dn_left, dlp, drp);
1829 1819
1830 1820 /*
1831 1821 * If the left-hand side of PTR or DOT is a dynamic variable,
1832 1822 * we expect it to be the output of a D translator. In this
1833 1823 * case, we look up the parse tree corresponding to the member
1834 1824 * that is being accessed and run the code generator over it.
1835 1825 * We then cast the result as if by the assignment operator.
1836 1826 */
1837 1827 if ((idp = dt_node_resolve(
1838 1828 dnp->dn_left, DT_IDENT_XLSOU)) != NULL ||
1839 1829 (idp = dt_node_resolve(
1840 1830 dnp->dn_left, DT_IDENT_XLPTR)) != NULL) {
1841 1831
1842 1832 dt_xlator_t *dxp;
1843 1833 dt_node_t *mnp;
1844 1834
1845 1835 dxp = idp->di_data;
1846 1836 mnp = dt_xlator_member(dxp, dnp->dn_right->dn_string);
1847 1837 assert(mnp != NULL);
1848 1838
1849 1839 dxp->dx_ident->di_flags |= DT_IDFLG_CGREG;
1850 1840 dxp->dx_ident->di_id = dnp->dn_left->dn_reg;
1851 1841
1852 1842 dt_cg_node(mnp->dn_membexpr, dlp, drp);
1853 1843 dnp->dn_reg = mnp->dn_membexpr->dn_reg;
1854 1844 dt_cg_typecast(mnp->dn_membexpr, dnp, dlp, drp);
1855 1845
1856 1846 dxp->dx_ident->di_flags &= ~DT_IDFLG_CGREG;
1857 1847 dxp->dx_ident->di_id = 0;
1858 1848
1859 1849 if (dnp->dn_left->dn_reg != -1)
1860 1850 dt_regset_free(drp, dnp->dn_left->dn_reg);
1861 1851 break;
1862 1852 }
1863 1853
1864 1854 ctfp = dnp->dn_left->dn_ctfp;
1865 1855 type = ctf_type_resolve(ctfp, dnp->dn_left->dn_type);
1866 1856
1867 1857 if (dnp->dn_op == DT_TOK_PTR) {
1868 1858 type = ctf_type_reference(ctfp, type);
1869 1859 type = ctf_type_resolve(ctfp, type);
1870 1860 }
1871 1861
1872 1862 if ((ctfp = dt_cg_membinfo(octfp = ctfp, type,
1873 1863 dnp->dn_right->dn_string, &m)) == NULL) {
1874 1864 yypcb->pcb_hdl->dt_ctferr = ctf_errno(octfp);
1875 1865 longjmp(yypcb->pcb_jmpbuf, EDT_CTF);
1876 1866 }
1877 1867
1878 1868 if (m.ctm_offset != 0) {
1879 1869 int reg;
1880 1870
1881 1871 reg = dt_regset_alloc(drp);
1882 1872
1883 1873 /*
1884 1874 * If the offset is not aligned on a byte boundary, it
1885 1875 * is a bit-field member and we will extract the value
1886 1876 * bits below after we generate the appropriate load.
1887 1877 */
1888 1878 dt_cg_setx(dlp, reg, m.ctm_offset / NBBY);
1889 1879
1890 1880 instr = DIF_INSTR_FMT(DIF_OP_ADD,
1891 1881 dnp->dn_left->dn_reg, reg, dnp->dn_left->dn_reg);
1892 1882
1893 1883 dt_irlist_append(dlp,
1894 1884 dt_cg_node_alloc(DT_LBL_NONE, instr));
1895 1885 dt_regset_free(drp, reg);
1896 1886 }
1897 1887
1898 1888 if (!(dnp->dn_flags & DT_NF_REF)) {
1899 1889 uint_t ubit = dnp->dn_flags & DT_NF_USERLAND;
1900 1890
1901 1891 /*
1902 1892 * Save and restore DT_NF_USERLAND across dt_cg_load():
1903 1893 * we need the sign bit from dnp and the user bit from
1904 1894 * dnp->dn_left in order to get the proper opcode.
1905 1895 */
1906 1896 dnp->dn_flags |=
1907 1897 (dnp->dn_left->dn_flags & DT_NF_USERLAND);
1908 1898
1909 1899 instr = DIF_INSTR_LOAD(dt_cg_load(dnp,
1910 1900 ctfp, m.ctm_type), dnp->dn_left->dn_reg,
1911 1901 dnp->dn_left->dn_reg);
1912 1902
1913 1903 dnp->dn_flags &= ~DT_NF_USERLAND;
1914 1904 dnp->dn_flags |= ubit;
1915 1905
1916 1906 dt_irlist_append(dlp,
1917 1907 dt_cg_node_alloc(DT_LBL_NONE, instr));
1918 1908
1919 1909 if (dnp->dn_flags & DT_NF_BITFIELD)
1920 1910 dt_cg_field_get(dnp, dlp, drp, ctfp, &m);
1921 1911 }
1922 1912
1923 1913 dnp->dn_reg = dnp->dn_left->dn_reg;
1924 1914 break;
1925 1915
1926 1916 case DT_TOK_STRING:
1927 1917 dnp->dn_reg = dt_regset_alloc(drp);
1928 1918
1929 1919 assert(dnp->dn_kind == DT_NODE_STRING);
1930 1920 stroff = dt_strtab_insert(yypcb->pcb_strtab, dnp->dn_string);
1931 1921
1932 1922 if (stroff == -1L)
1933 1923 longjmp(yypcb->pcb_jmpbuf, EDT_NOMEM);
1934 1924 if (stroff > DIF_STROFF_MAX)
1935 1925 longjmp(yypcb->pcb_jmpbuf, EDT_STR2BIG);
1936 1926
1937 1927 instr = DIF_INSTR_SETS((ulong_t)stroff, dnp->dn_reg);
1938 1928 dt_irlist_append(dlp, dt_cg_node_alloc(DT_LBL_NONE, instr));
1939 1929 break;
1940 1930
1941 1931 case DT_TOK_IDENT:
1942 1932 /*
1943 1933 * If the specified identifier is a variable on which we have
1944 1934 * set the code generator register flag, then this variable
1945 1935 * has already had code generated for it and saved in di_id.
1946 1936 * Allocate a new register and copy the existing value to it.
1947 1937 */
1948 1938 if (dnp->dn_kind == DT_NODE_VAR &&
1949 1939 (dnp->dn_ident->di_flags & DT_IDFLG_CGREG)) {
1950 1940 dnp->dn_reg = dt_regset_alloc(drp);
1951 1941 instr = DIF_INSTR_MOV(dnp->dn_ident->di_id,
1952 1942 dnp->dn_reg);
1953 1943 dt_irlist_append(dlp,
1954 1944 dt_cg_node_alloc(DT_LBL_NONE, instr));
1955 1945 break;
1956 1946 }
1957 1947
1958 1948 /*
1959 1949 * Identifiers can represent function calls, variable refs, or
1960 1950 * symbols. First we check for inlined variables, and handle
1961 1951 * them by generating code for the inline parse tree.
1962 1952 */
1963 1953 if (dnp->dn_kind == DT_NODE_VAR &&
1964 1954 (dnp->dn_ident->di_flags & DT_IDFLG_INLINE)) {
1965 1955 dt_cg_inline(dnp, dlp, drp);
1966 1956 break;
1967 1957 }
1968 1958
1969 1959 switch (dnp->dn_kind) {
1970 1960 case DT_NODE_FUNC:
1971 1961 if ((idp = dnp->dn_ident)->di_kind != DT_IDENT_FUNC) {
1972 1962 dnerror(dnp, D_CG_EXPR, "%s %s( ) may not be "
1973 1963 "called from a D expression (D program "
1974 1964 "context required)\n",
1975 1965 dt_idkind_name(idp->di_kind), idp->di_name);
1976 1966 }
1977 1967
1978 1968 dt_cg_arglist(dnp->dn_ident, dnp->dn_args, dlp, drp);
1979 1969
1980 1970 dnp->dn_reg = dt_regset_alloc(drp);
1981 1971 instr = DIF_INSTR_CALL(dnp->dn_ident->di_id,
1982 1972 dnp->dn_reg);
1983 1973
1984 1974 dt_irlist_append(dlp,
1985 1975 dt_cg_node_alloc(DT_LBL_NONE, instr));
1986 1976
1987 1977 break;
1988 1978
1989 1979 case DT_NODE_VAR:
1990 1980 if (dnp->dn_ident->di_kind == DT_IDENT_XLSOU ||
1991 1981 dnp->dn_ident->di_kind == DT_IDENT_XLPTR) {
1992 1982 /*
1993 1983 * This can only happen if we have translated
1994 1984 * args[]. See dt_idcook_args() for details.
1995 1985 */
1996 1986 assert(dnp->dn_ident->di_id == DIF_VAR_ARGS);
1997 1987 dt_cg_array_op(dnp, dlp, drp);
1998 1988 break;
1999 1989 }
2000 1990
2001 1991 if (dnp->dn_ident->di_kind == DT_IDENT_ARRAY) {
2002 1992 if (dnp->dn_ident->di_id > DIF_VAR_ARRAY_MAX)
2003 1993 dt_cg_assoc_op(dnp, dlp, drp);
2004 1994 else
2005 1995 dt_cg_array_op(dnp, dlp, drp);
2006 1996 break;
2007 1997 }
2008 1998
2009 1999 dnp->dn_reg = dt_regset_alloc(drp);
2010 2000
2011 2001 if (dnp->dn_ident->di_flags & DT_IDFLG_LOCAL)
2012 2002 op = DIF_OP_LDLS;
2013 2003 else if (dnp->dn_ident->di_flags & DT_IDFLG_TLS)
2014 2004 op = DIF_OP_LDTS;
2015 2005 else
2016 2006 op = DIF_OP_LDGS;
2017 2007
2018 2008 dnp->dn_ident->di_flags |= DT_IDFLG_DIFR;
2019 2009
2020 2010 instr = DIF_INSTR_LDV(op,
2021 2011 dnp->dn_ident->di_id, dnp->dn_reg);
2022 2012
2023 2013 dt_irlist_append(dlp,
2024 2014 dt_cg_node_alloc(DT_LBL_NONE, instr));
2025 2015 break;
2026 2016
2027 2017 case DT_NODE_SYM: {
2028 2018 dtrace_hdl_t *dtp = yypcb->pcb_hdl;
2029 2019 dtrace_syminfo_t *sip = dnp->dn_ident->di_data;
2030 2020 GElf_Sym sym;
2031 2021
2032 2022 if (dtrace_lookup_by_name(dtp,
2033 2023 sip->dts_object, sip->dts_name, &sym, NULL) == -1) {
2034 2024 xyerror(D_UNKNOWN, "cg failed for symbol %s`%s:"
2035 2025 " %s\n", sip->dts_object, sip->dts_name,
2036 2026 dtrace_errmsg(dtp, dtrace_errno(dtp)));
2037 2027 }
2038 2028
2039 2029 dnp->dn_reg = dt_regset_alloc(drp);
2040 2030 dt_cg_xsetx(dlp, dnp->dn_ident,
2041 2031 DT_LBL_NONE, dnp->dn_reg, sym.st_value);
2042 2032
2043 2033 if (!(dnp->dn_flags & DT_NF_REF)) {
2044 2034 instr = DIF_INSTR_LOAD(dt_cg_load(dnp, ctfp,
2045 2035 dnp->dn_type), dnp->dn_reg, dnp->dn_reg);
2046 2036 dt_irlist_append(dlp,
2047 2037 dt_cg_node_alloc(DT_LBL_NONE, instr));
2048 2038 }
2049 2039 break;
2050 2040 }
2051 2041
2052 2042 default:
2053 2043 xyerror(D_UNKNOWN, "internal error -- node type %u is "
2054 2044 "not valid for an identifier\n", dnp->dn_kind);
2055 2045 }
2056 2046 break;
2057 2047
2058 2048 case DT_TOK_INT:
2059 2049 dnp->dn_reg = dt_regset_alloc(drp);
2060 2050 dt_cg_setx(dlp, dnp->dn_reg, dnp->dn_value);
2061 2051 break;
2062 2052
2063 2053 default:
2064 2054 xyerror(D_UNKNOWN, "internal error -- token type %u is not a "
2065 2055 "valid D compilation token\n", dnp->dn_op);
2066 2056 }
2067 2057 }
2068 2058
2069 2059 void
2070 2060 dt_cg(dt_pcb_t *pcb, dt_node_t *dnp)
2071 2061 {
2072 2062 dif_instr_t instr;
2073 2063 dt_xlator_t *dxp;
2074 2064 dt_ident_t *idp;
2075 2065
2076 2066 if (pcb->pcb_regs == NULL && (pcb->pcb_regs =
2077 2067 dt_regset_create(pcb->pcb_hdl->dt_conf.dtc_difintregs)) == NULL)
2078 2068 longjmp(pcb->pcb_jmpbuf, EDT_NOMEM);
2079 2069
2080 2070 dt_regset_reset(pcb->pcb_regs);
2081 2071 (void) dt_regset_alloc(pcb->pcb_regs); /* allocate %r0 */
2082 2072
2083 2073 if (pcb->pcb_inttab != NULL)
2084 2074 dt_inttab_destroy(pcb->pcb_inttab);
2085 2075
2086 2076 if ((pcb->pcb_inttab = dt_inttab_create(yypcb->pcb_hdl)) == NULL)
2087 2077 longjmp(pcb->pcb_jmpbuf, EDT_NOMEM);
2088 2078
2089 2079 if (pcb->pcb_strtab != NULL)
2090 2080 dt_strtab_destroy(pcb->pcb_strtab);
2091 2081
2092 2082 if ((pcb->pcb_strtab = dt_strtab_create(BUFSIZ)) == NULL)
2093 2083 longjmp(pcb->pcb_jmpbuf, EDT_NOMEM);
2094 2084
2095 2085 dt_irlist_destroy(&pcb->pcb_ir);
2096 2086 dt_irlist_create(&pcb->pcb_ir);
2097 2087
2098 2088 assert(pcb->pcb_dret == NULL);
2099 2089 pcb->pcb_dret = dnp;
2100 2090
2101 2091 if (dt_node_resolve(dnp, DT_IDENT_XLPTR) != NULL) {
2102 2092 dnerror(dnp, D_CG_DYN, "expression cannot evaluate to result "
2103 2093 "of a translated pointer\n");
2104 2094 }
2105 2095
2106 2096 /*
2107 2097 * If we're generating code for a translator body, assign the input
2108 2098 * parameter to the first available register (i.e. caller passes %r1).
2109 2099 */
2110 2100 if (dnp->dn_kind == DT_NODE_MEMBER) {
2111 2101 dxp = dnp->dn_membxlator;
2112 2102 dnp = dnp->dn_membexpr;
2113 2103
2114 2104 dxp->dx_ident->di_flags |= DT_IDFLG_CGREG;
2115 2105 dxp->dx_ident->di_id = dt_regset_alloc(pcb->pcb_regs);
2116 2106 }
2117 2107
2118 2108 dt_cg_node(dnp, &pcb->pcb_ir, pcb->pcb_regs);
2119 2109
2120 2110 if ((idp = dt_node_resolve(dnp, DT_IDENT_XLSOU)) != NULL) {
2121 2111 int reg = dt_cg_xlate_expand(dnp, idp,
2122 2112 &pcb->pcb_ir, pcb->pcb_regs);
2123 2113 dt_regset_free(pcb->pcb_regs, dnp->dn_reg);
2124 2114 dnp->dn_reg = reg;
2125 2115 }
2126 2116
2127 2117 instr = DIF_INSTR_RET(dnp->dn_reg);
2128 2118 dt_regset_free(pcb->pcb_regs, dnp->dn_reg);
2129 2119 dt_irlist_append(&pcb->pcb_ir, dt_cg_node_alloc(DT_LBL_NONE, instr));
2130 2120
2131 2121 if (dnp->dn_kind == DT_NODE_MEMBER) {
2132 2122 dt_regset_free(pcb->pcb_regs, dxp->dx_ident->di_id);
2133 2123 dxp->dx_ident->di_id = 0;
2134 2124 dxp->dx_ident->di_flags &= ~DT_IDFLG_CGREG;
2135 2125 }
2136 2126
2137 2127 dt_regset_free(pcb->pcb_regs, 0);
2138 2128 dt_regset_assert_free(pcb->pcb_regs);
2139 2129 }
|
↓ open down ↓ |
2045 lines elided |
↑ open up ↑ |
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX