1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright 2001 Sun Microsystems, Inc. All rights reserved.
24 * Use is subject to license terms.
25 */
26
27 #ifndef _MONTECARLO_SYS_SCSB_H
28 #define _MONTECARLO_SYS_SCSB_H
29
30 #pragma ident "%Z%%M% %I% %E% SMI"
31
32 #ifdef __cplusplus
33 extern "C" {
34 #endif
35
36 #ifdef _KERNEL
37 #include <sys/inttypes.h>
38 #include <sys/i2c/misc/i2c_svc.h>
39 #include <sys/ksynch.h>
40 #endif /* _KERNEL */
41
42 /*
43 * CPU and AlarmCard slots
44 * MonteCarlo: CPU = SLOT1, AC = SLOT8
45 * Tonga: CPU = SLOT3, AC = SLOT1
46 */
47 #define SC_MC_CPU_SLOT 1
48 #define SC_TG_CPU_SLOT 3
49 #define SC_MC_AC_SLOT 8
50 #define SC_TG_AC_SLOT 1
51 #define SC_MC_CTC_SLOT 2
52
53 #define SCSB_MC_ALARM_SLOT SC_MC_AC_SLOT
54 #define SCSB_TONGA_ALARM_SLOT SC_TG_AC_SLOT
55
56 #define SCTRL_PROM_P06 0x00
57 #define SCTRL_PROM_P10 0x01
58 #define SCTRL_PROM_P15 0x02
59 #define SCTRL_PROM_P20 0x03
60
61 #define SCSB_RESET_SLOT 1
62 #define SCSB_UNRESET_SLOT 2
63 #define SCSB_GET_SLOT_RESET_STATUS 3
64
65 #define SCTRL_CFG_SLOT16 SCTRL_SYSCFG_5_READ-SCTRL_SYSCFG_BASE
66 #define SCTRL_CFG_SLOT710 SCTRL_SYSCFG_6_READ-SCTRL_SYSCFG_BASE
67 #define SCTRL_CFG_SLOTAC SCTRL_SYSCFG_4_READ-SCTRL_SYSCFG_BASE
68
69 /*
70 * SCSB operations between scsb and the hotswap controller module
71 */
72 #define SCSB_HSC_AC_BUSY 1
73 #define SCSB_HSC_AC_CONFIGURED 2
74 #define SCSB_HSC_AC_UNCONFIGURED 3
75 #define SCSB_HSC_AC_UNCONFIGURE 4
76 #define SCSB_HSC_AC_CONFIGURE 5
77 #define SCSB_HSC_AC_SET_BUSY 6
78 #define SCSB_HSC_AC_REMOVAL_ALERT 7
79 /*
80 * SCSB_HSC_AC_GET_SLOT_INFO for hsc_ac_op()
81 * to return hsc_slot_t pointer (for debugging)
82 */
83 #define SCSB_HSC_AC_GET_SLOT_INFO 11
84
85 /*
86 * The register set starting address, and macro for translating
87 * the index to 0 base.
88 */
89 #define SCSB_REG_ADDR_START 0xC0
90 #define SCSB_REG_INDEX(raddr) ((raddr) % SCSB_REG_ADDR_START)
91
92 /*
93 * ----------------------
94 * P1.0
95 * ----------------------
96 * The following three register offset groups are defined for P1.0 where
97 * FRUs might have three different bit offset values,
98 * Group 1: LEDs, Slot Reset, and BrdHlthy,
99 * Group 2: Config/Status registers
100 * Group 3: Interrupt Pointer/Mask registers
101 */
102 #define REG_GROUP1 0
103 #define REG_GROUP2 1
104 #define REG_GROUP3 2
105 #define REG_GROUPS_NUM 3
106 #define IS_GROUP1(rx) (rx < SCTRL_SYSCFG_5)
107 #define IS_GROUP3(rx) (rx > SCTRL_SYSCFG_4)
108 #define IS_GROUP2(rx) (rx > (SCTRL_SYSCFG_5 - 1) && \
109 (rx < (SCTRL_SYSCFG_4 + 1)))
110 #define IS_SCB_P10 (scsb->scsb_state & \
111 (SCSB_P06_PROM | SCSB_P10_PROM))
112 /*
113 * ----------------------
114 * P1.5
115 * ----------------------
116 * The table access macros use BASE register plus register offset to get the
117 * correct register index or address.
118 * The SCB FRU type has two register offsets, LED reg and INT reg offsets.
119 * The one in fru_offsets[] is for the NOK, OK, and BLINK LED data.
120 * To get the register offset for the INTSRC and INTMASK registers, the
121 * following constant must be added to the table value returned by
122 * FRU_REG_INDEX(SCTRL_EVENT_SCB, SCTRL_INTMSK_BASE), NOT SCTRL_INTMASK_BASE.
123 * Given enough time, this too should be handled via macro access to tables.
124 */
125 #define SCB_INT_OFFSET 2
126
127 /*
128 * ----------------------------------
129 * P0.6, P1.0, P1.5, P2.0 DEFINITIONS
130 * ----------------------------------
131 */
132
133 #define SCTRL_PROM_VERSION 0xCF /* same Addr for P06 thru P20 */
134 #define IS_SCB_P15 (scsb->scsb_state & \
135 (SCSB_P15_PROM | SCSB_P20_PROM))
136
137 /*
138 * SCB Register Indicies to scb_reg_index[] table
139 */
140 #define SCTRL_SYS_CMD_BASE 0
141 #define SCTRL_SYS_CMD1 SCTRL_SYS_CMD_BASE
142 #define SCTRL_SYS_CMD2 1
143 #define SCTRL_LED_NOK_BASE 2
144 #define SCTRL_LED_SLOT_16_NOK SCTRL_LED_NOK_BASE
145 #define SCTRL_LED_SLOT_712_NOK 3
146 #define SCTRL_LED_DPP_NOK 4
147 #define SCTRL_LED_FAN_NOK 5
148 #define SCTRL_LED_OK_BASE 6
149 #define SCTRL_LED_SLOT_16_OK SCTRL_LED_OK_BASE
150 #define SCTRL_LED_SLOT_712_OK 7
151 #define SCTRL_LED_DPP_OK 8
152 #define SCTRL_LED_FAN_OK 9
153 #define SCTRL_RESET_BASE 10
154 #define SCTRL_RESET_SLOT_16 SCTRL_RESET_BASE
155 #define SCTRL_RESET_SLOT_710A 11
156 #define SCTRL_RESET_ALARM 11
157 #define SCTRL_BLINK_OK_BASE 12
158 #define SCTRL_BLINK_OK_1 SCTRL_BLINK_OK_BASE
159 #define SCTRL_BLINK_OK_2 13
160 #define SCTRL_BLINK_GR_3 14 /* 0xCE */
161 #define SCTRL_SCBID_BASE 15
162 #define SCTRL_BHLTHY_BASE 16
163 #define SCTRL_BHLTHY_SLOT_16 SCTRL_BHLTHY_BASE
164 #define SCTRL_BHLTHY_SLOT_710 17
165 #define SCTRL_SYSCFG_BASE 18
166 #define SCTRL_SYSCFG_5 SCTRL_SYSCFG_BASE
167 #define SCTRL_SYSCFG_6 19
168 #define SCTRL_SYSCFG_1 20
169 #define SCTRL_SYSCFG_2 21
170 #define SCTRL_SYSCFG_3 22
171 #define SCTRL_SYSCFG_4 23
172 #define SCTRL_INTSRC_BASE 24
173 #define SCTRL_INTSRC_HLTHY_BASE SCTRL_INTSRC_BASE
174 #define SCTRL_INTSRC_1 SCTRL_INTSRC_BASE
175 #define SCTRL_INTSRC_2 25
176 #define SCTRL_INTSRC_3 26
177 #define SCTRL_INTSRC_4 27
178 #define SCTRL_INTSRC_5 28
179 #define SCTRL_INTSRC_6 29
180 #define SCTRL_INTSRC_SCB_P15 SCTRL_INTSRC_6
181 #define SCTRL_INTMASK_BASE 30
182 #define SCTRL_INTMASK_HLTHY_BASE SCTRL_INTMASK_BASE
183 #define SCTRL_INTMASK_1 SCTRL_INTMASK_BASE
184 #define SCTRL_INTMASK_2 31
185 #define SCTRL_INTMASK_3 32
186 #define SCTRL_INTMASK_4 33
187 #define SCTRL_INTMASK_5 34
188 #define SCTRL_INTMASK_6 35
189
190 #define SCTRL_INTPTR_BASE SCTRL_INTSRC_3
191 #define SCTRL_INTMSK_BASE SCTRL_INTMASK_3
192 /*
193 * The last two definitions are for register offset compatibility.
194 * These will be used with FRU_REG_INDEX macros, for P1.0 and P1.5, so 1.5
195 * register offsets in upper nibble of fru_offset[] tables will be consistent.
196 * This happens because the HLTHY INTs and INT masks come before the slots and
197 * FRUs. That's what changes the register offsets.
198 * The only EXCEPTION is the ALARM RESET register, which for P1.5 is not
199 * BASE + 3 as in all other cases, but BASE + 1. FRU_REG_INDEX(code,base) does
200 * NOT work for ALARM RESET. Use ALARM_RESET_REG_INDEX() instead.
201 * FRU_REG_INDEX() works differently for P1.0, using offset groups to calculate
202 * the index to the fru_offset[] table.
203 */
204
205 /*
206 * REGISTER BIT OFFSETS
207 * For the bit definitions, the SCB register sets are divided into two tables,
208 * 1. scb_1x_fru_offset[] bit-offsets for all FRUs and
209 * Interrupt events
210 * 2. scb_1x_sys_offset[] for system command/control registers
211 * and any remaining bits, like MPID.
212 *
213 * This is a bit historic from P0.6,P1.0 days.
214 * The fru_offset table is indexed using the SCTRL_EVENT_ codes defined in
215 * mct_topology.h. Almost all of these describe interrupt generated events.
216 * Ths sys_offset table contains anything else, mostly the System Control
217 * registers and some bit definitions form the config/status registers.
218 */
219
220 /*
221 * scb_1x_sys_offset[] table indicies
222 *
223 * SCB System Command/Control Registers from 1.0 and 1.5
224 */
225 #define SCTRL_SYS_PS1_OFF 0
226 #define SCTRL_SYS_PS2_OFF 1
227 #define SCTRL_SYS_PS_OFF_BASE SCTRL_SYS_PS1_OFF
228 #define SCTRL_SYS_PS1_ON 2
229 #define SCTRL_SYS_PS2_ON 3
230 #define SCTRL_SYS_PS_ON_BASE SCTRL_SYS_PS1_ON
231 #define SCTRL_SYS_SCB_CTL0 4
232 #define SCTRL_SYS_SCB_CTL1 5
233 #define SCTRL_SYS_SCB_CTL2 6
234 #define SCTRL_SYS_SCB_CTL3 7
235 #define SCTRL_SYS_PSM_INT_ENABLE 8
236 #define SCTRL_SYS_SCB_INIT 9
237 #define SCTRL_SYS_TEST_MODE 10
238 #define SCTRL_SYS_SCBLED 11
239 #define SCTRL_SYS_SPA0 12
240 #define SCTRL_SYS_SPA1 13
241 #define SCTRL_SYS_SPA2 14
242 #define SCTRL_SYS_RSVD 15
243 /*
244 * SCB Config/Status register leftovers
245 */
246 #define SCTRL_CFG_MPID0 16
247 #define SCTRL_CFG_MPID1 17
248 #define SCTRL_CFG_MPID2 18
249 #define SCTRL_CFG_MPID3 19
250 #define SCTRL_CFG_SCB_STAT0 20
251 #define SCTRL_CFG_SCB_STAT2 21
252 /*
253 * SCB Identity register offsets
254 */
255 #define SCTRL_SCBID0 22
256 #define SCTRL_SCBID_SIZE 4
257 #define SCTRL_SCB_TEST 23
258
259 /* numregs table order and indicies */
260 #define SCTRL_SYS_CMD_NUM 0
261 #define SCTRL_LED_NOK_NUM 1
262 #define SCTRL_LED_OK_NUM 2
263 #define SCTRL_LED_NUM 3
264 #define SCTRL_RESET_NUM 4
265 #define SCTRL_BLINK_NUM 5
266 #define SCTRL_SCBID_NUM 6
267 #define SCTRL_BHLTHY_NUM 7
268 #define SCTRL_SYSCFG_NUM 8
269 #define SCTRL_INTSRC_NUM 9
270 #define SCTRL_INTMSK_NUM 10
271 #define SCTRL_TOTAL_NUM 11
272
273
274 /*
275 * Macro Definitions for register and bit offset values
276 */
277 /* macros names for scb_numregs[] access */
278 #define SCTRL_SYSCMD_NUMREGS (scb_numregs[SCTRL_SYS_CMD_NUM])
279 #define SCTRL_LED_NOK_NUMREGS (scb_numregs[SCTRL_LED_NOK_NUM])
280 #define SCTRL_LED_OK_NUMREGS (scb_numregs[SCTRL_LED_OK_NUM])
281 #define SCTRL_LED_NUMREGS (scb_numregs[SCTRL_LED_NUM])
282 #define SCTRL_RESET_NUMREGS (scb_numregs[SCTRL_RESET_NUM])
283 #define SCTRL_BLINK_NUMREGS (scb_numregs[SCTRL_BLINK_NUM])
284 #define SCTRL_SCBID_NUMREGS (scb_numregs[SCTRL_SCBID_NUM])
285 #define SCTRL_BHLTHY_NUMREGS (scb_numregs[SCTRL_BHLTHY_NUM])
286 #define SCTRL_CFG_NUMREGS (scb_numregs[SCTRL_SYSCFG_NUM])
287 #define SCTRL_INTR_NUMREGS (scb_numregs[SCTRL_INTSRC_NUM])
288 #define SCTRL_MASK_NUMREGS (scb_numregs[SCTRL_INTMSK_NUM])
289 #define SCTRL_TOTAL_NUMREGS (scb_numregs[SCTRL_TOTAL_NUM])
290
291 /*
292 * Maximum number of registers in a register group
293 * Needed for above register groups array sizing
294 */
295 #define SCTRL_MAX_GROUP_NUMREGS 16
296
297 #define SCSB_REG_ADDR(rx) (scb_reg_index[rx])
298 #define FRU_INDEX(code) (event_to_index(code))
299 #define FRU_OFFSET_BASE(rx) (MCT_MAX_FRUS * (IS_SCB_P15 ? 0 : \
300 (IS_GROUP1(rx) ? REG_GROUP1 : \
301 (IS_GROUP3(rx) ? REG_GROUP3 : \
302 REG_GROUP2))))
303 #define FRU_OFFSET_VAL(code, rx) (scb_fru_offset[FRU_OFFSET_BASE(rx) + \
304 FRU_INDEX(code)])
305
306 #define FRU_OFFSET(code, rx) (FRU_OFFSET_VAL(code, rx) & 0xf)
307 #define FRU_REG_INDEX(code, rx) (((FRU_OFFSET_VAL(code, rx) >> 4) \
308 & 0xf) + rx)
309 #define FRU_REG_ADDR(code, rx) (SCSB_REG_ADDR(FRU_REG_INDEX(code, rx)))
310 #define SYS_OFFSET_VAL(idx) (scb_sys_offset[idx])
311 #define SYS_OFFSET(idx) (SYS_OFFSET_VAL(idx) & 0xf)
312 #define SYS_REG_INDEX(idx, rx) (((SYS_OFFSET_VAL(idx) >> 4) \
313 & 0xf) + rx)
314
315 #define ALARM_RESET_REG_INDEX(code, rx) ((IS_SCB_P15 ? 1 : \
316 ((FRU_OFFSET_VAL(code, rx) >> 4) \
317 & 0xf)) + rx)
318 #define FRU_UNIT_TO_EVCODE(type, unit) (type_to_code1[type] << (unit - 1))
319
320 /*LINTED table used in scsb.o and system utilities*/
321 static uchar_t *scb_reg_index;
322 /*LINTED table used in scsb.o and system utilities*/
323 static uchar_t *scb_numregs;
324 /*LINTED table used in scsb.o and system utilities*/
325 static uchar_t *scb_fru_offset;
326 /*LINTED table used in scsb.o and system utilities*/
327 static uchar_t *scb_sys_offset;
328
329 /*
330 * --------------------
331 * Common TABLES
332 * --------------------
333 */
334
335 /*
336 * FRU type to unit 1 event_code, see FRU_UNIT_TO_EVCODE() macro above.
337 * Table order is dependent on scsb_utype_t definition in mct_topology.h
338 */
339 /*LINTED table used in scsb.o and system utilities*/
340 static uint32_t type_to_code1[] = {
341 SCTRL_EVENT_SLOT1,
342 SCTRL_EVENT_PDU1,
343 SCTRL_EVENT_PS1,
344 SCTRL_EVENT_DISK1,
345 SCTRL_EVENT_FAN1,
346 SCTRL_EVENT_ALARM,
347 SCTRL_EVENT_SCB,
348 SCTRL_EVENT_SSB,
349 SCTRL_EVENT_CFTM,
350 SCTRL_EVENT_CRTM,
351 SCTRL_EVENT_PRTM
352 };
353
354 /*
355 * --------------------
356 * P0.6 and P1.0 TABLES
357 * --------------------
358 */
359
360 /*
361 * MonteCarlo: Programming Inteface Specifications Version 0.9
362 * 10/27/99
363 * NOTE: P0.6 FANs and PDUs were different
364 */
365 /*LINTED table used in scsb.o and system utilities*/
366 static uchar_t scb_10_reg_index[] = {
367 0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, /* 00 - 07 */
368 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, /* 08 - 15 */
369 0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, /* 16 - 23 */
370 0xD8, 0xD9, 0xDA, 0xDB, 0x00, 0x00, 0xDC, 0x00, /* 24 - 31 */
371 0xDC, 0xDD, 0xDE, 0xDF, 0xD8, 0xDC, 0x00, 0x00, /* 32 - 39 */
372 };
373
374 /*LINTED table used in scsb.o and system utilities*/
375 static uchar_t scb_10_numregs[] = {
376 2, 4, 4, 8, 2, 2, 1, 2, 6, 4, 4, 32
377 };
378
379
380 /*
381 * MCT_MAX_FRUS * REG_GROUPS_NUM
382 *
383 * FRU order:
384 * 0 - 9: Slots 1 - 10
385 * 10 - 11: PDU 1 - 2
386 * 12 - 13: PS 1 - 2
387 * 14 - 16: Disk 1 - 3
388 * 17 - 19: Fan 1 - 3
389 * 20: Alarm Card
390 * 21: SCB
391 * 22: SSB
392 * 23: CRTM
393 * 24: CFTM
394 * 25: PRTM
395 * 26: PWRDWN
396 * 27: REPLACE
397 * 28: ALARM_INT
398 * 29 - 31: Unused
399 *
400 * A register base group offset is added to the register base value to
401 * find the index into the reg_index table.
402 * Example: LED_NOK_BASE + '1' = register for slots 7-10 NOK LEDs
403 * This offset is encoded in the upper nibble in the following table
404 * of register offsets per FRU/EVENT.
405 * The register base group definitions are:
406 * base group offset group
407 * ---------------------- ------------
408 * SCTRL_LED_NOK_BASE G1
409 * SCTRL_LED_OK_BASE G1
410 * SCTRL_RESET_BASE G1
411 * SCTRL_BLINK_OK_BASE G1
412 * SCTRL_BHLTHY_BASE G1
413 * SCTRL_SYSCFG_BASE G2
414 * SCTRL_INTSRC_BASE G3
415 * SCTRL_INTMASK_BASE G3
416 * SCTRL_SYS_CMD_BASE G4
417 *
418 * See FRU_OFFSET() macro
419 */
420 /*LINTED table used in scsb.o and system utilities*/
421 static uchar_t scb_10_fru_offset[] = {
422 /* Register Group 1 */
423 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, /* SLOT 1-6 */
424 0x10, 0x11, 0x12, 0x13, /* SLOT 7-10 */
425 0x35, 0x15, 0x21, 0x22, /* PDU/PS 1-2 */
426 0x23, 0x24, 0x25, /* Disks 1-3 */
427 0x33, 0x34, 0x35, /* Fans 1-3 */
428 0xFF, 0x20, 0xFF, /* Alarm Card, SCB, SSB */
429 0xFF, 0xFF, 0xFF, /* CRTM, CFTM, PRTM */
430 0xFF, 0xFF, 0xFF, /* PWRDWN, SCBRR, ACINT */
431 0xFF, 0xFF, 0xFF, /* Unused */
432 /* Register Group 2 */
433 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, /* SLOT 1-6 */
434 0x10, 0x11, 0x12, 0x13, /* SLOT 7-10 */
435 0x25, 0x27, 0x30, 0x31, /* PDU/PS 1-2 */
436 0x40, 0x41, 0x42, /* Disks 1-3 */
437 0x32, 0x33, 0x34, /* Fans 1-3 */
438 0x50, 0xFF, 0x35, /* Alarm Card, SCB, SSB */
439 0x43, 0x44, 0x45, /* CRTM, CFTM, PRTM */
440 0xFF, 0xFF, 0xFF, /* PWRDWN, SCBRR, ACINT */
441 0x24, 0x26, 0x20, /* STAT0, STAT1, MPID0 */
442 /* Register Group 3 */
443 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, /* SLOT 1-6 */
444 0x37, 0x26, 0x27, 0x16, /* SLOT 7-10 */
445 0xFF, 0xFF, 0x10, 0x11, /* PDU/PS 1-2 */
446 0x20, 0x21, 0x22, /* Disks 1-3 */
447 0x12, 0x13, 0x14, /* Fans 1-3 */
448 0x30, 0x04, 0x15, /* Alarm Card, SCB, SSB */
449 0x23, 0x24, 0x25, /* CRTM, CFTM, PRTM */
450 0x00, 0x02, 0x03, /* PWRDWN, SCBRR, ACINT */
451 0xFF, 0xFF, 0xFF, /* Unused */
452 };
453
454 /*LINTED table used in scsb.o and system utilities*/
455 static uchar_t scb_10_sys_offset[] = {
456 0x00, 0x01, 0x06, 0x07, 0x10, 0x11, 0x12, 0x13,
457 0x15, 0x16, 0xFF, 0x02, 0x03, 0x04, 0x05, 0x14,
458 0x20, 0x21, 0x22, 0x23, 0x24, 0x26, 0x00, 0x07,
459 };
460
461 /*LINTED table used in scsb.o and system utilities*/
462 static uchar_t scb_10_int_masks[] = {
463 0x11, 0x2F, 0x3F, 0xFF, 0x00, 0x00,
464 };
465
466
467 /*
468 * --------------------
469 * P1.5 and P2.0 TABLES
470 * --------------------
471 */
472
473 /*
474 * MonteCarlo: Programming Inteface Specifications
475 * Chapter 12 from the MonteCarlo System Specification
476 * 02/08/00: Chapter update from Carl Meert
477 */
478 /*LINTED table used in scsb.o and system utilities*/
479 static uchar_t scb_15_reg_index[] = {
480 0xE0, 0xE1, 0xC0, 0xC1, 0xC2, 0xC2, 0xC3, 0xC4, /* 00 - 07 */
481 0xC5, 0xC5, 0xE2, 0xE3, 0xC6, 0xC7, 0xC8, 0xCF, /* 08 - 15 */
482 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0x00, 0x00, /* 16 - 23 */
483 0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, /* 24 - 31 */
484 0xD8, 0xD9, 0xDA, 0xDB, 0xD2, 0xD8, 0x00, 0x00, /* 32 - 39 */
485 };
486
487 /*LINTED table used in scsb.o and system utilities*/
488 static uchar_t scb_15_numregs[] = {
489 2, 3, 3, 6, 2, 3, 1, 2, 4, 6, 6, 48
490 };
491
492 /*LINTED table used in scsb.o and system utilities*/
493 static uchar_t scb_15_fru_offset[] = {
494 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, /* SLOT 1-6 */
495 0x06, 0x07, 0x16, 0x17, /* SLOT 7-10 */
496 0x11, 0x13, 0x26, 0x27, /* PDU/PS 1-2 */
497 0x23, 0x24, 0x25, /* Disks 1-3 */
498 0x20, 0x21, 0xFF, /* Fans 1-3 */
499 0x30, 0x15, 0x33, /* Alarm Card, SCB, SSB */
500 0x31, 0x14, 0x32, /* CRTM, CFTM, PRTM */
501 0x34, 0xFF, 0x36, /* PWRDWN, SCBRR, ACINT */
502 0xFF, 0xFF, 0xFF, /* Unused */
503 };
504
505 /*LINTED table used in scsb.o and system utilities*/
506 static uchar_t scb_15_sys_offset[] = {
507 0x00, 0x01, 0x02, 0x03, 0x10, 0x11, 0x12, 0x13,
508 0x14, 0x15, 0x16, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
509 0x34, 0x35, 0x36, 0x37, 0x10, 0x12, 0x00, 0x07
510 };
511
512 /*LINTED table used in scsb.o and system utilities*/
513 static uchar_t scb_15_int_masks[] = {
514 0xFF, 0x00, 0xFF, 0x1A, 0xFB, 0x7F,
515 };
516
517 #define SCSB_NO_OF_BOARDS 1
518
519 /*
520 * scsb_state values
521 * outside _KERNEL for smctrl test utility
522 */
523 #define SCSB_DOWN 0x0000 /* never really used */
524 #define SCSB_UP 0x0001
525 #define SCSB_OPEN 0x0002
526 #define SCSB_EXCL 0x0004
527 #define SCSB_APP_SLOTLED_CTRL 0x0008
528 #define SCSB_KS_UPDATE 0x0010
529 #define SCSB_FROZEN 0x0020
530 #define SCSB_DEBUG_MODE 0x0040
531 #define SCSB_DIAGS_MODE 0x0080
532 #define SCSB_UNUSED_08 0x0100
533 #define SCSB_PSM_INT_ENABLED 0x0200
534 #define SCSB_UMUTEX 0x0400
535 #define SCSB_CONDVAR 0x0800
536 #define SCSB_SCB_PRESENT 0x1000
537 #define SCSB_SSB_PRESENT 0x2000
538 #define SCSB_UNUSED_14 0x4000
539 #define SCSB_UNUSED_15 0x8000
540 #define SCSB_MINOR_NODE 0x00010000
541 #define SCSB_PROP_CREATE 0x00020000
542 #define SCSB_IMUTEX 0x00040000
543 #define SCSB_I2C_PHANDLE 0x00080000
544 #define SCSB_I2C_TRANSFER 0x00100000
545 #define SCSB_TOPOLOGY 0x00200000
546 #define SCSB_KSTATS 0x00400000
547 #define SCSB_IS_TONGA 0x00800000
548 #define SCSB_P10_PROM 0x01000000
549 #define SCSB_P15_PROM 0x02000000
550 #define SCSB_P20_PROM 0x04000000
551 #define SCSB_P2X_PROM 0x08000000
552 #define SCSB_P06_PROM 0x10000000
553 #define SCSB_P06_INTR_ON 0x20000000
554 #define SCSB_P06_NOINT_KLUGE 0x40000000
555 #define SCSB_IN_INTR 0x80000000
556 #define SCSB_HSC_INIT 0x0001
557 #define SCSB_ENUM_ENABLED 0x0002
558 #define SCSB_ALARM_CARD_PRES 0x0004
559 #define SCSB_ALARM_CARD_IN_USE 0x0008
560 #define SCSB_AC_SLOT_INTR_DONE 0x0010
561 #define SCSB_HSC_CTC_PRES 0x0020
562 #define SCSB_HSC_UNUSED_06 0x0040
563 #define SCSB_HSC_UNUSED_07 0x0080
564 #define SCSB_HSC_UNUSED_08 0x0100
565 #define SCSB_HSC_UNUSED_09 0x0200
566 #define SCSB_HSC_UNUSED_10 0x0400
567 #define SCSB_HSC_UNUSED_11 0x0800
568 #define SCSB_HSC_UNUSED_12 0x1000
569 #define SCSB_HSC_UNUSED_13 0x2000
570 #define SCSB_HSC_UNUSED_14 0x4000
571 #define SCSB_HSC_UNUSED_15 0x8000
572
573 #ifdef _KERNEL
574
575 /*
576 * The System Controller Board uses the Xilinx to control the I2C bus.
577 * The address should really go to scsb.conf file.
578 * The I2C address of the System Controller Board
579 */
580 #define SCSB_I2C_ADDR 0x80
581 #define SCSB_I2C_ADDR_MASK 0xFF
582
583 #define SCSB_DEVICE_NAME "scsb"
584 #define SCSB_INTR_PIL 4
585
586 /*
587 * definitions for Interrupt Event Code handling
588 */
589 #define EVC_FIFO_SIZE 8
590 #define EVC_PROCS_MAX 16
591 /*
592 * return values for check_event_procs()
593 */
594 #define EVC_NO_EVENT_CODE 1
595 #define EVC_NO_CURR_PROC 2
596 #define EVC_NEW_EVENT_CODE 3
597 #define EVC_OR_EVENT_CODE 4
598 #define EVC_FAILURE 5
599 /*
600 * scsb_queue_ops() definitions
601 * Operations:
602 */
603 #define QPROCSOFF 1
604 #define QPUT_INT32 2
605 #define QFIRST_AVAILABLE 3
606 #define QFIRST_OPEN 4
607 #define QFIND_QUEUE 5
608 /*
609 * Return values:
610 * 0 - 15 are valid clone numbers used as index to clone_devs[]
611 * and returned for some operations instead of QOP_OK.
612 */
613 #define QOP_OK 16
614 #define QOP_FAILED -1
615
616 /*
617 * minor_t definitions
618 * bits 2-0 SCB instance 0-7
619 * bit 3 Clone device for sm_open()
620 * bits 7-4 Cloned device numbers for a total of 15: 0x1# - 0xf#
621 * Must start with '1' to avoid conflict with:
622 * 0x00 non-clone device node for instance 0
623 * 0x08 the clone device node for instance 0
624 * the new minor_t for the clone is all of the above.
625 */
626 #define SCSB_INSTANCE_MASK 0x07
627 #define SCSB_CLONE 0x08
628 #define SCSB_CLONES_MASK 0xf0
629 #define SCSB_CLONES_SHIFT 4
630 #define SCSB_CLONES_FIRST 1
631 #define SCSB_CLONES_MAX 16
632 #define SCSB_GET_CLONE(minor) ((minor&SCSB_CLONES_MASK)>>SCSB_CLONES_SHIFT)
633 #define SCSB_GET_INSTANCE(minor) \
634 (minor&SCSB_INSTANCE_MASK)
635 #define SCSB_MAKE_MINOR(inst, clnum) \
636 (inst|(clnum<<SCSB_CLONES_SHIFT)|SCSB_CLONE)
637
638 typedef struct clone_dev {
639 queue_t *cl_rq;
640 minor_t cl_minor;
641 uint32_t cl_flags;
642 } clone_dev_t;
643
644 typedef struct {
645 uint32_t scsb_instance;
646 uint32_t scsb_state;
647 uint32_t scsb_hsc_state;
648 int ac_slotnum; /* Alarm Card Slot Number */
649 kmutex_t scsb_mutex;
650 kcondvar_t scsb_cv;
651 uint32_t scsb_opens;
652 dev_info_t *scsb_dev;
653 i2c_client_hdl_t scsb_phandle; /* i2c private handle from i2c nexus */
654 mblk_t *scsb_mp; /* reserved for interrupt processing */
655 i2c_transfer_t *scsb_i2ctp; /* pointer to read/write structure */
656 uchar_t scsb_data_reg[SCSB_DATA_REGISTERS];
657 int scsb_i2c_addr; /* i2c addr. */
658 queue_t *scsb_rq; /* read q for scsb_instance */
659 timeout_id_t scsb_btid; /* qbufcall, or qtimeout id */
660 kmutex_t scsb_imutex;
661 ddi_iblock_cookie_t scsb_iblock;
662 kstat_t *ks_leddata;
663 kstat_t *ks_state;
664 kstat_t *ks_topology;
665 kstat_t *ks_evcreg;
666 uint32_t scsb_i2c_errcnt;
667 boolean_t scsb_err_flag; /* latch err until kstat read */
668 boolean_t scsb_kstat_flag; /* do i2c trans for kstat */
669 uint32_t scsb_clopens;
670 clone_dev_t clone_devs[SCSB_CLONES_MAX];
671 } scsb_state_t;
672
673 int scsb_led_get(scsb_state_t *, scsb_uinfo_t *, scsb_led_t led_type);
674 int scsb_led_set(scsb_state_t *, scsb_uinfo_t *, scsb_led_t led_type);
675 int scsb_reset_unit(scsb_state_t *, scsb_uinfo_t *);
676 int scsb_bhealthy_slot(scsb_state_t *, scsb_uinfo_t *);
677 int scsb_slot_occupancy(scsb_state_t *, scsb_uinfo_t *);
678
679 #if defined(DEBUG)
680 extern void prom_printf(const char *, ...);
681 void scsb_debug_prnt(char *, uintptr_t, uintptr_t,
682 uintptr_t, uintptr_t, uintptr_t);
683
684 #define DEBUG0(fmt)\
685 scsb_debug_prnt(fmt, 0, 0, 0, 0, 0);
686 #define DEBUG1(fmt, a1)\
687 scsb_debug_prnt(fmt, (uintptr_t)(a1), 0, 0, 0, 0);
688 #define DEBUG2(fmt, a1, a2)\
689 scsb_debug_prnt(fmt, (uintptr_t)(a1), (uintptr_t)(a2), 0, 0, 0);
690 #define DEBUG3(fmt, a1, a2, a3)\
691 scsb_debug_prnt(fmt, (uintptr_t)(a1), (uintptr_t)(a2),\
692 (uintptr_t)(a3), 0, 0);
693 #define DEBUG4(fmt, a1, a2, a3, a4)\
694 scsb_debug_prnt(fmt, (uintptr_t)(a1), (uintptr_t)(a2),\
695 (uintptr_t)(a3), (uintptr_t)(a4), 0);
696 #else
697 #define DEBUG0(fmt)
698 #define DEBUG1(fmt, a1)
699 #define DEBUG2(fmt, a1, a2)
700 #define DEBUG3(fmt, a1, a2, a3)
701 #define DEBUG4(fmt, a1, a2, a3, a4)
702 #endif
703
704
705 #endif /* _KERNEL */
706
707 #ifdef __cplusplus
708 }
709 #endif
710
711 #endif /* _MONTECARLO_SYS_SCSB_H */