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7813 mpt_sas does not like concurrent HBA resets
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--- old/usr/src/uts/common/sys/scsi/adapters/mpt_sas/mptsas_var.h
+++ new/usr/src/uts/common/sys/scsi/adapters/mpt_sas/mptsas_var.h
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21
22 22 /*
23 23 * Copyright (c) 2009, 2010, Oracle and/or its affiliates. All rights reserved.
24 24 * Copyright 2015 Nexenta Systems, Inc. All rights reserved.
25 25 * Copyright (c) 2013, Joyent, Inc. All rights reserved.
26 26 * Copyright (c) 2014, Tegile Systems Inc. All rights reserved.
27 27 */
28 28
29 29 /*
30 30 * Copyright (c) 2000 to 2010, LSI Corporation.
31 31 * All rights reserved.
32 32 *
33 33 * Redistribution and use in source and binary forms of all code within
34 34 * this file that is exclusively owned by LSI, with or without
35 35 * modification, is permitted provided that, in addition to the CDDL 1.0
36 36 * License requirements, the following conditions are met:
37 37 *
38 38 * Neither the name of the author nor the names of its contributors may be
39 39 * used to endorse or promote products derived from this software without
40 40 * specific prior written permission.
41 41 *
42 42 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
43 43 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
44 44 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
45 45 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
46 46 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
47 47 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
48 48 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
49 49 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
50 50 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
51 51 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
52 52 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
53 53 * DAMAGE.
54 54 */
55 55
56 56 #ifndef _SYS_SCSI_ADAPTERS_MPTVAR_H
57 57 #define _SYS_SCSI_ADAPTERS_MPTVAR_H
58 58
59 59 #include <sys/byteorder.h>
60 60 #include <sys/queue.h>
61 61 #include <sys/isa_defs.h>
62 62 #include <sys/sunmdi.h>
63 63 #include <sys/mdi_impldefs.h>
64 64 #include <sys/scsi/adapters/mpt_sas/mptsas_hash.h>
65 65 #include <sys/scsi/adapters/mpt_sas/mptsas_ioctl.h>
66 66 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_tool.h>
67 67 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_cnfg.h>
68 68
69 69 #ifdef __cplusplus
70 70 extern "C" {
71 71 #endif
72 72
73 73 /*
74 74 * Compile options
75 75 */
76 76 #ifdef DEBUG
77 77 #define MPTSAS_DEBUG /* turn on debugging code */
78 78 #endif /* DEBUG */
79 79
80 80 #define MPTSAS_INITIAL_SOFT_SPACE 4
81 81
82 82 #define MAX_MPI_PORTS 16
83 83
84 84 /*
85 85 * Note below macro definition and data type definition
86 86 * are used for phy mask handling, it should be changed
87 87 * simultaneously.
88 88 */
89 89 #define MPTSAS_MAX_PHYS 16
90 90 typedef uint16_t mptsas_phymask_t;
91 91
92 92 #define MPTSAS_INVALID_DEVHDL 0xffff
93 93 #define MPTSAS_SATA_GUID "sata-guid"
94 94
95 95 /*
96 96 * Hash table sizes for SMP targets (i.e., expanders) and ordinary SSP/STP
97 97 * targets. There's no need to go overboard here, as the ordinary paths for
98 98 * I/O do not normally require hashed target lookups. These should be good
99 99 * enough and then some for any fabric within the hardware's capabilities.
100 100 */
101 101 #define MPTSAS_SMP_BUCKET_COUNT 23
102 102 #define MPTSAS_TARGET_BUCKET_COUNT 97
103 103 #define MPTSAS_TMP_TARGET_BUCKET_COUNT 13
104 104
105 105 /*
106 106 * MPT HW defines
107 107 */
108 108 #define MPTSAS_MAX_DISKS_IN_CONFIG 14
109 109 #define MPTSAS_MAX_DISKS_IN_VOL 10
110 110 #define MPTSAS_MAX_HOTSPARES 2
111 111 #define MPTSAS_MAX_RAIDVOLS 2
112 112 #define MPTSAS_MAX_RAIDCONFIGS 5
113 113
114 114 /*
115 115 * 64-bit SAS WWN is displayed as 16 characters as HEX characters,
116 116 * plus two means the prefix 'w' and end of the string '\0'.
117 117 */
118 118 #define MPTSAS_WWN_STRLEN (16 + 2)
119 119 #define MPTSAS_MAX_GUID_LEN 64
120 120
121 121 /*
122 122 * DMA routine flags
123 123 */
124 124 #define MPTSAS_DMA_HANDLE_ALLOCD 0x2
125 125 #define MPTSAS_DMA_MEMORY_ALLOCD 0x4
126 126 #define MPTSAS_DMA_HANDLE_BOUND 0x8
127 127
128 128 /*
129 129 * If the HBA supports DMA or bus-mastering, you may have your own
130 130 * scatter-gather list for physically non-contiguous memory in one
131 131 * I/O operation; if so, there's probably a size for that list.
132 132 * It must be placed in the ddi_dma_lim_t structure, so that the system
133 133 * DMA-support routines can use it to break up the I/O request, so we
134 134 * define it here.
135 135 */
136 136 #if defined(__sparc)
137 137 #define MPTSAS_MAX_DMA_SEGS 1
138 138 #define MPTSAS_MAX_CMD_SEGS 1
139 139 #else
140 140 #define MPTSAS_MAX_DMA_SEGS 256
141 141 #define MPTSAS_MAX_CMD_SEGS 257
142 142 #endif
143 143 #define MPTSAS_MAX_FRAME_SGES(mpt) \
144 144 (((mpt->m_req_frame_size - (sizeof (MPI2_SCSI_IO_REQUEST))) / 8) + 1)
145 145
146 146 #define MPTSAS_SGE_SIZE(mpt) \
147 147 ((mpt)->m_MPI25 ? sizeof (MPI2_IEEE_SGE_SIMPLE64) : \
148 148 sizeof (MPI2_SGE_SIMPLE64))
149 149
150 150 /*
151 151 * Calculating how many 64-bit DMA simple elements can be stored in the first
152 152 * frame. Note that msg_scsi_io_request contains 2 double-words (8 bytes) for
153 153 * element storage. And 64-bit dma element is 3 double-words (12 bytes) in
154 154 * size. IEEE 64-bit dma element used for SAS3 controllers is 4 double-words
155 155 * (16 bytes).
156 156 */
157 157 #define MPTSAS_MAX_FRAME_SGES64(mpt) \
158 158 ((mpt->m_req_frame_size - \
159 159 sizeof (MPI2_SCSI_IO_REQUEST) + sizeof (MPI2_SGE_IO_UNION)) / \
160 160 MPTSAS_SGE_SIZE(mpt))
161 161
162 162 /*
163 163 * Scatter-gather list structure defined by HBA hardware
164 164 */
165 165 typedef struct NcrTableIndirect { /* Table Indirect entries */
166 166 uint32_t count; /* 24 bit count */
167 167 union {
168 168 uint32_t address32; /* 32 bit address */
169 169 struct {
170 170 uint32_t Low;
171 171 uint32_t High;
172 172 } address64; /* 64 bit address */
173 173 } addr;
174 174 } mptti_t;
175 175
176 176 /*
177 177 * preferred pkt_private length in 64-bit quantities
178 178 */
179 179 #ifdef _LP64
180 180 #define PKT_PRIV_SIZE 2
181 181 #define PKT_PRIV_LEN 16 /* in bytes */
182 182 #else /* _ILP32 */
183 183 #define PKT_PRIV_SIZE 1
184 184 #define PKT_PRIV_LEN 8 /* in bytes */
185 185 #endif
186 186
187 187 #define PKT2CMD(pkt) ((struct mptsas_cmd *)((pkt)->pkt_ha_private))
188 188 #define CMD2PKT(cmdp) ((struct scsi_pkt *)((cmdp)->cmd_pkt))
189 189 #define EXTCMDS_STATUS_SIZE (sizeof (struct scsi_arq_status))
190 190
191 191 /*
192 192 * get offset of item in structure
193 193 */
194 194 #define MPTSAS_GET_ITEM_OFF(type, member) ((size_t)(&((type *)0)->member))
195 195
196 196 /*
197 197 * WWID provided by LSI firmware is generated by firmware but the WWID is not
198 198 * IEEE NAA standard format, OBP has no chance to distinguish format of unit
199 199 * address. According LSI's confirmation, the top nibble of RAID WWID is
200 200 * meanless, so the consensus between Solaris and OBP is to replace top nibble
201 201 * of WWID provided by LSI to "3" always to hint OBP that this is a RAID WWID
202 202 * format unit address.
203 203 */
204 204 #define MPTSAS_RAID_WWID(wwid) \
205 205 ((wwid & 0x0FFFFFFFFFFFFFFF) | 0x3000000000000000)
206 206
207 207 typedef struct mptsas_target_addr {
208 208 uint64_t mta_wwn;
209 209 mptsas_phymask_t mta_phymask;
210 210 } mptsas_target_addr_t;
211 211
212 212 TAILQ_HEAD(mptsas_active_cmdq, mptsas_cmd);
213 213 typedef struct mptsas_active_cmdq mptsas_active_cmdq_t;
214 214
215 215 typedef struct mptsas_target {
216 216 mptsas_target_addr_t m_addr;
217 217 refhash_link_t m_link;
218 218 uint8_t m_dr_flag;
219 219 uint16_t m_devhdl;
220 220 uint32_t m_deviceinfo;
221 221 uint8_t m_phynum;
222 222 uint32_t m_dups;
223 223 mptsas_active_cmdq_t m_active_cmdq;
224 224 int32_t m_t_throttle;
225 225 int32_t m_t_ncmds;
226 226 int32_t m_reset_delay;
227 227 int32_t m_t_nwait;
228 228
229 229 uint16_t m_qfull_retry_interval;
230 230 uint8_t m_qfull_retries;
231 231 uint16_t m_io_flags;
232 232 uint16_t m_enclosure;
233 233 uint16_t m_slot_num;
234 234 uint32_t m_tgt_unconfigured;
235 235 uint8_t m_led_status;
236 236 uint8_t m_scsi_req_desc_type;
237 237
238 238 } mptsas_target_t;
239 239
240 240 /*
241 241 * If you change this structure, be sure that mptsas_smp_target_copy()
242 242 * does the right thing.
243 243 */
244 244 typedef struct mptsas_smp {
245 245 mptsas_target_addr_t m_addr;
246 246 refhash_link_t m_link;
247 247 uint16_t m_devhdl;
248 248 uint32_t m_deviceinfo;
249 249 uint16_t m_pdevhdl;
250 250 uint32_t m_pdevinfo;
251 251 } mptsas_smp_t;
252 252
253 253 typedef struct mptsas_cache_frames {
254 254 ddi_dma_handle_t m_dma_hdl;
255 255 ddi_acc_handle_t m_acc_hdl;
256 256 caddr_t m_frames_addr;
257 257 uint64_t m_phys_addr;
258 258 } mptsas_cache_frames_t;
259 259
260 260 typedef struct mptsas_cmd {
261 261 uint_t cmd_flags; /* flags from scsi_init_pkt */
262 262 ddi_dma_handle_t cmd_dmahandle; /* dma handle */
263 263 ddi_dma_cookie_t cmd_cookie;
264 264 uint_t cmd_cookiec;
265 265 uint_t cmd_winindex;
266 266 uint_t cmd_nwin;
267 267 uint_t cmd_cur_cookie;
268 268 off_t cmd_dma_offset;
269 269 size_t cmd_dma_len;
270 270 uint32_t cmd_totaldmacount;
271 271 caddr_t cmd_arq_buf;
272 272
273 273 int cmd_pkt_flags;
274 274
275 275 /* pending expiration time for command in active slot */
276 276 hrtime_t cmd_active_expiration;
277 277 TAILQ_ENTRY(mptsas_cmd) cmd_active_link;
278 278
279 279 struct scsi_pkt *cmd_pkt;
280 280 struct scsi_arq_status cmd_scb;
281 281 uchar_t cmd_cdblen; /* length of cdb */
282 282 uchar_t cmd_rqslen; /* len of requested rqsense */
283 283 uchar_t cmd_privlen;
284 284 uint16_t cmd_extrqslen; /* len of extended rqsense */
285 285 uint16_t cmd_extrqschunks; /* len in map chunks */
286 286 uint16_t cmd_extrqsidx; /* Index into map */
287 287 uint_t cmd_scblen;
288 288 uint32_t cmd_dmacount;
289 289 uint64_t cmd_dma_addr;
290 290 uchar_t cmd_age;
291 291 ushort_t cmd_qfull_retries;
292 292 uchar_t cmd_queued; /* true if queued */
293 293 struct mptsas_cmd *cmd_linkp;
294 294 mptti_t *cmd_sg; /* Scatter/Gather structure */
295 295 uchar_t cmd_cdb[SCSI_CDB_SIZE];
296 296 uint64_t cmd_pkt_private[PKT_PRIV_LEN];
297 297 uint32_t cmd_slot;
298 298 uint32_t ioc_cmd_slot;
299 299
300 300 mptsas_cache_frames_t *cmd_extra_frames;
301 301
302 302 uint32_t cmd_rfm;
303 303 mptsas_target_t *cmd_tgt_addr;
304 304 } mptsas_cmd_t;
305 305
306 306 /*
307 307 * These are the defined cmd_flags for this structure.
308 308 */
309 309 #define CFLAG_CMDDISC 0x000001 /* cmd currently disconnected */
310 310 #define CFLAG_WATCH 0x000002 /* watchdog time for this command */
311 311 #define CFLAG_FINISHED 0x000004 /* command completed */
312 312 #define CFLAG_CHKSEG 0x000008 /* check cmd_data within seg */
313 313 #define CFLAG_COMPLETED 0x000010 /* completion routine called */
314 314 #define CFLAG_PREPARED 0x000020 /* pkt has been init'ed */
315 315 #define CFLAG_IN_TRANSPORT 0x000040 /* in use by host adapter driver */
316 316 #define CFLAG_RESTORE_PTRS 0x000080 /* implicit restore ptr on reconnect */
317 317 #define CFLAG_ARQ_IN_PROGRESS 0x000100 /* auto request sense in progress */
318 318 #define CFLAG_TRANFLAG 0x0001ff /* covers transport part of flags */
319 319 #define CFLAG_TM_CMD 0x000200 /* cmd is a task management command */
320 320 #define CFLAG_CMDARQ 0x000400 /* cmd is a 'rqsense' command */
321 321 #define CFLAG_DMAVALID 0x000800 /* dma mapping valid */
322 322 #define CFLAG_DMASEND 0x001000 /* data is going 'out' */
323 323 #define CFLAG_CMDIOPB 0x002000 /* this is an 'iopb' packet */
324 324 #define CFLAG_CDBEXTERN 0x004000 /* cdb kmem_alloc'd */
325 325 #define CFLAG_SCBEXTERN 0x008000 /* scb kmem_alloc'd */
326 326 #define CFLAG_FREE 0x010000 /* packet is on free list */
327 327 #define CFLAG_PRIVEXTERN 0x020000 /* target private kmem_alloc'd */
328 328 #define CFLAG_DMA_PARTIAL 0x040000 /* partial xfer OK */
329 329 #define CFLAG_QFULL_STATUS 0x080000 /* pkt got qfull status */
330 330 #define CFLAG_TIMEOUT 0x100000 /* passthru/config command timeout */
331 331 #define CFLAG_PMM_RECEIVED 0x200000 /* use cmd_pmm* for saving pointers */
332 332 #define CFLAG_RETRY 0x400000 /* cmd has been retried */
333 333 #define CFLAG_CMDIOC 0x800000 /* cmd is just for for ioc, no io */
334 334 #define CFLAG_PASSTHRU 0x2000000 /* cmd is a passthrough command */
335 335 #define CFLAG_XARQ 0x4000000 /* cmd requests for extra sense */
336 336 #define CFLAG_CMDACK 0x8000000 /* cmd for event ack */
337 337 #define CFLAG_TXQ 0x10000000 /* cmd queued in the tx_waitq */
338 338 #define CFLAG_FW_CMD 0x20000000 /* cmd is a fw up/down command */
339 339 #define CFLAG_CONFIG 0x40000000 /* cmd is for config header/page */
340 340 #define CFLAG_FW_DIAG 0x80000000 /* cmd is for FW diag buffers */
341 341
342 342 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_SIZE 8
343 343 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_MASK 0xC0
344 344 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_PERIPHERAL 0x00
345 345 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_FLAT_SPACE 0x40
346 346 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT 0x80
347 347 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_EXTENDED_UNIT 0xC0
348 348 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_2B 0x00
349 349 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_4B 0x01
350 350 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_6B 0x10
351 351 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_8B 0x20
352 352 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_SIZE 0x30
353 353
354 354 #define MPTSAS_HASH_ARRAY_SIZE 16
355 355 /*
356 356 * hash table definition
357 357 */
358 358
359 359 #define MPTSAS_HASH_FIRST 0xffff
360 360 #define MPTSAS_HASH_NEXT 0x0000
361 361
362 362 typedef struct mptsas_dma_alloc_state
363 363 {
364 364 ddi_dma_handle_t handle;
365 365 caddr_t memp;
366 366 size_t size;
367 367 ddi_acc_handle_t accessp;
368 368 ddi_dma_cookie_t cookie;
369 369 } mptsas_dma_alloc_state_t;
370 370
371 371 /*
372 372 * passthrough request structure
373 373 */
374 374 typedef struct mptsas_pt_request {
375 375 uint8_t *request;
376 376 uint32_t request_size;
377 377 uint32_t data_size;
378 378 uint32_t dataout_size;
379 379 uint32_t direction;
380 380 uint8_t simple;
381 381 uint16_t sgl_offset;
382 382 ddi_dma_cookie_t data_cookie;
383 383 ddi_dma_cookie_t dataout_cookie;
384 384 } mptsas_pt_request_t;
385 385
386 386 /*
387 387 * config page request structure
388 388 */
389 389 typedef struct mptsas_config_request {
390 390 uint32_t page_address;
391 391 uint8_t action;
392 392 uint8_t page_type;
393 393 uint8_t page_number;
394 394 uint8_t page_length;
395 395 uint8_t page_version;
396 396 uint8_t ext_page_type;
397 397 uint16_t ext_page_length;
398 398 } mptsas_config_request_t;
399 399
400 400 typedef struct mptsas_fw_diagnostic_buffer {
401 401 mptsas_dma_alloc_state_t buffer_data;
402 402 uint8_t extended_type;
403 403 uint8_t buffer_type;
404 404 uint8_t force_release;
405 405 uint32_t product_specific[23];
406 406 uint8_t immediate;
407 407 uint8_t enabled;
408 408 uint8_t valid_data;
409 409 uint8_t owned_by_firmware;
410 410 uint32_t unique_id;
411 411 } mptsas_fw_diagnostic_buffer_t;
412 412
413 413 /*
414 414 * FW diag request structure
415 415 */
416 416 typedef struct mptsas_diag_request {
417 417 mptsas_fw_diagnostic_buffer_t *pBuffer;
418 418 uint8_t function;
419 419 } mptsas_diag_request_t;
420 420
421 421 typedef struct mptsas_hash_node {
422 422 void *data;
423 423 struct mptsas_hash_node *next;
424 424 } mptsas_hash_node_t;
425 425
426 426 typedef struct mptsas_hash_table {
427 427 struct mptsas_hash_node *head[MPTSAS_HASH_ARRAY_SIZE];
428 428 /*
429 429 * last position in traverse
430 430 */
431 431 struct mptsas_hash_node *cur;
432 432 uint16_t line;
433 433
434 434 } mptsas_hash_table_t;
435 435
436 436 /*
437 437 * RAID volume information
438 438 */
439 439 typedef struct mptsas_raidvol {
440 440 ushort_t m_israid;
441 441 uint16_t m_raidhandle;
442 442 uint64_t m_raidwwid;
443 443 uint8_t m_state;
444 444 uint32_t m_statusflags;
445 445 uint32_t m_settings;
446 446 uint16_t m_devhdl[MPTSAS_MAX_DISKS_IN_VOL];
447 447 uint8_t m_disknum[MPTSAS_MAX_DISKS_IN_VOL];
448 448 ushort_t m_diskstatus[MPTSAS_MAX_DISKS_IN_VOL];
449 449 uint64_t m_raidsize;
450 450 int m_raidlevel;
451 451 int m_ndisks;
452 452 mptsas_target_t *m_raidtgt;
453 453 } mptsas_raidvol_t;
454 454
455 455 /*
456 456 * RAID configurations
457 457 */
458 458 typedef struct mptsas_raidconfig {
459 459 mptsas_raidvol_t m_raidvol[MPTSAS_MAX_RAIDVOLS];
460 460 uint16_t m_physdisk_devhdl[
461 461 MPTSAS_MAX_DISKS_IN_CONFIG];
462 462 uint8_t m_native;
463 463 } m_raidconfig_t;
464 464
465 465 /*
466 466 * Track outstanding commands. The index into the m_slot array is the SMID
467 467 * (system message ID) of the outstanding command. SMID 0 is reserved by the
468 468 * software/firmware protocol and is never used for any command we generate;
469 469 * as such, the assertion m_slot[0] == NULL is universally true. The last
470 470 * entry in the array is slot number MPTSAS_TM_SLOT(mpt) and is used ONLY for
471 471 * task management commands. No normal SCSI or ATA command will ever occupy
472 472 * that slot. Finally, the relationship m_slot[X]->cmd_slot == X holds at any
473 473 * time that a consistent view of the target array is obtainable.
474 474 *
475 475 * As such, m_n_normal is the maximum number of slots available to ordinary
476 476 * commands, and the relationship:
477 477 * mpt->m_active->m_n_normal == mpt->m_max_requests - 2
478 478 * always holds after initialisation.
479 479 */
480 480 typedef struct mptsas_slots {
481 481 size_t m_size; /* size of struct, bytes */
482 482 uint_t m_n_normal; /* see above */
483 483 uint_t m_rotor; /* next slot idx to consider */
484 484 mptsas_cmd_t *m_slot[1];
485 485 } mptsas_slots_t;
486 486
487 487 /*
488 488 * Structure to hold command and packets for event ack
489 489 * and task management commands.
490 490 */
491 491 typedef struct m_event_struct {
492 492 struct mptsas_cmd m_event_cmd;
493 493 struct m_event_struct *m_event_linkp;
494 494 /*
495 495 * event member record the failure event and eventcntx
496 496 * event member would be used in send ack pending process
497 497 */
498 498 uint32_t m_event;
499 499 uint32_t m_eventcntx;
500 500 uint_t in_use;
501 501 struct scsi_pkt m_event_pkt; /* must be last */
502 502 /* ... scsi_pkt_size() */
503 503 } m_event_struct_t;
504 504 #define M_EVENT_STRUCT_SIZE (sizeof (m_event_struct_t) - \
505 505 sizeof (struct scsi_pkt) + scsi_pkt_size())
506 506
507 507 #define MAX_IOC_COMMANDS 8
508 508
509 509 /*
510 510 * A pool of MAX_IOC_COMMANDS is maintained for event ack commands.
511 511 * A new event ack command requests mptsas_cmd and scsi_pkt structures
512 512 * from this pool, and returns it back when done.
513 513 */
514 514
515 515 typedef struct m_replyh_arg {
516 516 void *mpt;
517 517 uint32_t rfm;
518 518 } m_replyh_arg_t;
519 519 _NOTE(DATA_READABLE_WITHOUT_LOCK(m_replyh_arg_t::mpt))
520 520 _NOTE(DATA_READABLE_WITHOUT_LOCK(m_replyh_arg_t::rfm))
521 521
522 522 /*
523 523 * Flags for DR handler topology change
524 524 */
525 525 #define MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE 0x0
526 526 #define MPTSAS_TOPO_FLAG_EXPANDER_ASSOCIATED 0x1
527 527 #define MPTSAS_TOPO_FLAG_LUN_ASSOCIATED 0x2
528 528 #define MPTSAS_TOPO_FLAG_RAID_ASSOCIATED 0x4
529 529 #define MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED 0x8
530 530 #define MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE 0x10
531 531
532 532 typedef struct mptsas_topo_change_list {
533 533 void *mpt;
534 534 uint_t event;
535 535 union {
536 536 uint8_t physport;
537 537 mptsas_phymask_t phymask;
538 538 } un;
539 539 uint16_t devhdl;
540 540 void *object;
541 541 uint8_t flags;
542 542 struct mptsas_topo_change_list *next;
543 543 } mptsas_topo_change_list_t;
544 544
545 545
546 546 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::mpt))
547 547 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::event))
548 548 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::physport))
549 549 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::devhdl))
550 550 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::object))
551 551 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::flags))
552 552
553 553 /*
554 554 * Status types when calling mptsas_get_target_device_info
555 555 */
556 556 #define DEV_INFO_SUCCESS 0x0
557 557 #define DEV_INFO_FAIL_PAGE0 0x1
558 558 #define DEV_INFO_WRONG_DEVICE_TYPE 0x2
559 559 #define DEV_INFO_PHYS_DISK 0x3
560 560 #define DEV_INFO_FAIL_ALLOC 0x4
561 561 #define DEV_INFO_FAIL_GUID 0x5
562 562
563 563 /*
564 564 * mpt hotplug event defines
565 565 */
566 566 #define MPTSAS_DR_EVENT_RECONFIG_TARGET 0x01
567 567 #define MPTSAS_DR_EVENT_OFFLINE_TARGET 0x02
568 568 #define MPTSAS_TOPO_FLAG_REMOVE_HANDLE 0x04
569 569
570 570 /*
571 571 * SMP target hotplug events
572 572 */
573 573 #define MPTSAS_DR_EVENT_RECONFIG_SMP 0x10
574 574 #define MPTSAS_DR_EVENT_OFFLINE_SMP 0x20
575 575 #define MPTSAS_DR_EVENT_MASK 0x3F
576 576
577 577 /*
578 578 * mpt hotplug status definition for m_dr_flag
579 579 */
580 580
581 581 /*
582 582 * MPTSAS_DR_INACTIVE
583 583 *
584 584 * The target is in a normal operating state.
585 585 * No dynamic reconfiguration operation is in progress.
586 586 */
587 587 #define MPTSAS_DR_INACTIVE 0x0
588 588 /*
589 589 * MPTSAS_DR_INTRANSITION
590 590 *
591 591 * The target is in a transition mode since
592 592 * hotplug event happens and offline procedure has not
593 593 * been finished
594 594 */
595 595 #define MPTSAS_DR_INTRANSITION 0x1
596 596
597 597 typedef struct mptsas_tgt_private {
598 598 int t_lun;
599 599 struct mptsas_target *t_private;
600 600 } mptsas_tgt_private_t;
601 601
602 602 /*
603 603 * The following defines are used in mptsas_set_init_mode to track the current
604 604 * state as we progress through reprogramming the HBA from target mode into
605 605 * initiator mode.
606 606 */
607 607
608 608 #define IOUC_READ_PAGE0 0x00000100
609 609 #define IOUC_READ_PAGE1 0x00000200
610 610 #define IOUC_WRITE_PAGE1 0x00000400
611 611 #define IOUC_DONE 0x00000800
612 612 #define DISCOVERY_IN_PROGRESS MPI2_SASIOUNIT0_PORTFLAGS_DISCOVERY_IN_PROGRESS
613 613 #define AUTO_PORT_CONFIGURATION MPI2_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG
614 614
615 615 /*
616 616 * Last allocated slot is used for TM requests. Since only m_max_requests
617 617 * frames are allocated, the last SMID will be m_max_requests - 1.
618 618 */
619 619 #define MPTSAS_SLOTS_SIZE(mpt) \
620 620 (sizeof (struct mptsas_slots) + (sizeof (struct mptsas_cmd *) * \
621 621 mpt->m_max_requests))
622 622 #define MPTSAS_TM_SLOT(mpt) (mpt->m_max_requests - 1)
623 623
624 624 /*
625 625 * Macro for phy_flags
626 626 */
627 627
628 628 typedef struct smhba_info {
629 629 kmutex_t phy_mutex;
630 630 uint8_t phy_id;
631 631 uint64_t sas_addr;
632 632 char path[8];
633 633 uint16_t owner_devhdl;
634 634 uint16_t attached_devhdl;
635 635 uint8_t attached_phy_identify;
636 636 uint32_t attached_phy_info;
637 637 uint8_t programmed_link_rate;
638 638 uint8_t hw_link_rate;
639 639 uint8_t change_count;
640 640 uint32_t phy_info;
641 641 uint8_t negotiated_link_rate;
642 642 uint8_t port_num;
643 643 kstat_t *phy_stats;
644 644 uint32_t invalid_dword_count;
645 645 uint32_t running_disparity_error_count;
646 646 uint32_t loss_of_dword_sync_count;
647 647 uint32_t phy_reset_problem_count;
648 648 void *mpt;
649 649 } smhba_info_t;
650 650
651 651 typedef struct mptsas_phy_info {
652 652 uint8_t port_num;
653 653 uint8_t port_flags;
654 654 uint16_t ctrl_devhdl;
655 655 uint32_t phy_device_type;
656 656 uint16_t attached_devhdl;
657 657 mptsas_phymask_t phy_mask;
658 658 smhba_info_t smhba_info;
659 659 } mptsas_phy_info_t;
660 660
661 661
662 662 typedef struct mptsas_doneq_thread_arg {
663 663 void *mpt;
664 664 uint64_t t;
665 665 } mptsas_doneq_thread_arg_t;
666 666
667 667 #define MPTSAS_DONEQ_THREAD_ACTIVE 0x1
668 668 typedef struct mptsas_doneq_thread_list {
669 669 mptsas_cmd_t *doneq;
670 670 mptsas_cmd_t **donetail;
671 671 kthread_t *threadp;
672 672 kcondvar_t cv;
673 673 ushort_t reserv1;
674 674 uint32_t reserv2;
675 675 kmutex_t mutex;
676 676 uint32_t flag;
677 677 uint32_t len;
678 678 mptsas_doneq_thread_arg_t arg;
679 679 } mptsas_doneq_thread_list_t;
680 680
681 681 typedef struct mptsas {
682 682 int m_instance;
683 683
684 684 struct mptsas *m_next;
685 685
686 686 scsi_hba_tran_t *m_tran;
687 687 smp_hba_tran_t *m_smptran;
688 688 kmutex_t m_mutex;
689 689 kmutex_t m_passthru_mutex;
690 690 kcondvar_t m_cv;
691 691 kcondvar_t m_passthru_cv;
692 692 kcondvar_t m_fw_cv;
693 693 kcondvar_t m_config_cv;
694 694 kcondvar_t m_fw_diag_cv;
695 695 dev_info_t *m_dip;
696 696
697 697 /*
698 698 * soft state flags
699 699 */
700 700 uint_t m_softstate;
701 701
702 702 refhash_t *m_targets;
703 703 refhash_t *m_smp_targets;
704 704 refhash_t *m_tmp_targets;
705 705
706 706 m_raidconfig_t m_raidconfig[MPTSAS_MAX_RAIDCONFIGS];
707 707 uint8_t m_num_raid_configs;
708 708
709 709 struct mptsas_slots *m_active; /* outstanding cmds */
710 710
711 711 mptsas_cmd_t *m_waitq; /* cmd queue for active request */
712 712 mptsas_cmd_t **m_waitqtail; /* wait queue tail ptr */
713 713
714 714 kmutex_t m_tx_waitq_mutex;
715 715 mptsas_cmd_t *m_tx_waitq; /* TX cmd queue for active request */
716 716 mptsas_cmd_t **m_tx_waitqtail; /* tx_wait queue tail ptr */
717 717 int m_tx_draining; /* TX queue draining flag */
718 718
719 719 mptsas_cmd_t *m_doneq; /* queue of completed commands */
720 720 mptsas_cmd_t **m_donetail; /* queue tail ptr */
721 721
722 722 /*
723 723 * variables for helper threads (fan-out interrupts)
724 724 */
725 725 mptsas_doneq_thread_list_t *m_doneq_thread_id;
726 726 uint32_t m_doneq_thread_n;
727 727 uint32_t m_doneq_thread_threshold;
728 728 uint32_t m_doneq_length_threshold;
729 729 uint32_t m_doneq_len;
730 730 kcondvar_t m_doneq_thread_cv;
731 731 kmutex_t m_doneq_mutex;
732 732
733 733 int m_ncmds; /* number of outstanding commands */
734 734 m_event_struct_t *m_ioc_event_cmdq; /* cmd queue for ioc event */
735 735 m_event_struct_t **m_ioc_event_cmdtail; /* ioc cmd queue tail */
736 736
737 737 ddi_acc_handle_t m_datap; /* operating regs data access handle */
738 738
739 739 struct _MPI2_SYSTEM_INTERFACE_REGS *m_reg;
740 740
741 741 ushort_t m_devid; /* device id of chip. */
742 742 uchar_t m_revid; /* revision of chip. */
743 743 uint16_t m_svid; /* subsystem Vendor ID of chip */
744 744 uint16_t m_ssid; /* subsystem Device ID of chip */
745 745
746 746 uchar_t m_sync_offset; /* default offset for this chip. */
747 747
748 748 timeout_id_t m_quiesce_timeid;
749 749
750 750 ddi_dma_handle_t m_dma_req_frame_hdl;
751 751 ddi_acc_handle_t m_acc_req_frame_hdl;
752 752 ddi_dma_handle_t m_dma_req_sense_hdl;
753 753 ddi_acc_handle_t m_acc_req_sense_hdl;
754 754 ddi_dma_handle_t m_dma_reply_frame_hdl;
755 755 ddi_acc_handle_t m_acc_reply_frame_hdl;
756 756 ddi_dma_handle_t m_dma_free_queue_hdl;
757 757 ddi_acc_handle_t m_acc_free_queue_hdl;
758 758 ddi_dma_handle_t m_dma_post_queue_hdl;
759 759 ddi_acc_handle_t m_acc_post_queue_hdl;
760 760
761 761 /*
762 762 * list of reset notification requests
763 763 */
764 764 struct scsi_reset_notify_entry *m_reset_notify_listf;
765 765
766 766 /*
767 767 * qfull handling
768 768 */
769 769 timeout_id_t m_restart_cmd_timeid;
770 770
771 771 /*
772 772 * scsi reset delay per bus
773 773 */
774 774 uint_t m_scsi_reset_delay;
775 775
776 776 int m_pm_idle_delay;
777 777
778 778 uchar_t m_polled_intr; /* intr was polled. */
779 779 uchar_t m_suspended; /* true if driver is suspended */
780 780
781 781 struct kmem_cache *m_kmem_cache;
782 782 struct kmem_cache *m_cache_frames;
783 783
784 784 /*
785 785 * hba options.
786 786 */
787 787 uint_t m_options;
788 788
789 789 int m_in_callback;
790 790
791 791 int m_power_level; /* current power level */
792 792
793 793 int m_busy; /* power management busy state */
794 794
795 795 off_t m_pmcsr_offset; /* PMCSR offset */
796 796
797 797 ddi_acc_handle_t m_config_handle;
798 798
799 799 ddi_dma_attr_t m_io_dma_attr; /* Used for data I/O */
800 800 ddi_dma_attr_t m_msg_dma_attr; /* Used for message frames */
801 801 ddi_device_acc_attr_t m_dev_acc_attr;
802 802 ddi_device_acc_attr_t m_reg_acc_attr;
803 803
804 804 /*
805 805 * request/reply variables
806 806 */
807 807 caddr_t m_req_frame;
808 808 uint64_t m_req_frame_dma_addr;
809 809 caddr_t m_req_sense;
810 810 caddr_t m_extreq_sense;
811 811 uint_t m_extreq_sense_refcount;
812 812 kcondvar_t m_extreq_sense_refcount_cv;
813 813 uint64_t m_req_sense_dma_addr;
814 814 caddr_t m_reply_frame;
815 815 uint64_t m_reply_frame_dma_addr;
816 816 caddr_t m_free_queue;
817 817 uint64_t m_free_queue_dma_addr;
818 818 caddr_t m_post_queue;
819 819 uint64_t m_post_queue_dma_addr;
820 820 struct map *m_erqsense_map;
821 821
822 822 m_replyh_arg_t *m_replyh_args;
823 823
824 824 uint16_t m_max_requests;
825 825 uint16_t m_req_frame_size;
826 826 uint16_t m_req_sense_size;
827 827
828 828 /*
829 829 * Max frames per request reprted in IOC Facts
830 830 */
831 831 uint8_t m_max_chain_depth;
832 832 /*
833 833 * Max frames per request which is used in reality. It's adjusted
834 834 * according DMA SG length attribute, and shall not exceed the
835 835 * m_max_chain_depth.
836 836 */
837 837 uint8_t m_max_request_frames;
838 838
839 839 uint16_t m_free_queue_depth;
840 840 uint16_t m_post_queue_depth;
841 841 uint16_t m_max_replies;
842 842 uint32_t m_free_index;
843 843 uint32_t m_post_index;
844 844 uint8_t m_reply_frame_size;
845 845 uint32_t m_ioc_capabilities;
846 846
847 847 /*
848 848 * indicates if the firmware was upload by the driver
849 849 * at boot time
850 850 */
851 851 ushort_t m_fwupload;
852 852
853 853 uint16_t m_productid;
854 854
855 855 /*
856 856 * per instance data structures for dma memory resources for
857 857 * MPI handshake protocol. only one handshake cmd can run at a time.
858 858 */
859 859 ddi_dma_handle_t m_hshk_dma_hdl;
860 860 ddi_acc_handle_t m_hshk_acc_hdl;
861 861 caddr_t m_hshk_memp;
862 862 size_t m_hshk_dma_size;
863 863
864 864 /* Firmware version on the card at boot time */
865 865 uint32_t m_fwversion;
866 866
867 867 /* MSI specific fields */
868 868 ddi_intr_handle_t *m_htable; /* For array of interrupts */
869 869 int m_intr_type; /* What type of interrupt */
870 870 int m_intr_cnt; /* # of intrs count returned */
871 871 size_t m_intr_size; /* Size of intr array */
872 872 uint_t m_intr_pri; /* Interrupt priority */
873 873 int m_intr_cap; /* Interrupt capabilities */
874 874 ddi_taskq_t *m_event_taskq;
875 875
876 876 /* SAS specific information */
877 877
878 878 union {
879 879 uint64_t m_base_wwid; /* Base WWID */
880 880 struct {
881 881 #ifdef _BIG_ENDIAN
882 882 uint32_t m_base_wwid_hi;
883 883 uint32_t m_base_wwid_lo;
884 884 #else
885 885 uint32_t m_base_wwid_lo;
886 886 uint32_t m_base_wwid_hi;
887 887 #endif
888 888 } sasaddr;
889 889 } un;
890 890
891 891 uint8_t m_num_phys; /* # of PHYs */
892 892 mptsas_phy_info_t m_phy_info[MPTSAS_MAX_PHYS];
893 893 uint8_t m_port_chng; /* initiator port changes */
894 894 MPI2_CONFIG_PAGE_MAN_0 m_MANU_page0; /* Manufactor page 0 info */
895 895 MPI2_CONFIG_PAGE_MAN_1 m_MANU_page1; /* Manufactor page 1 info */
896 896
897 897 /* FMA Capabilities */
898 898 int m_fm_capabilities;
899 899 ddi_taskq_t *m_dr_taskq;
900 900 int m_mpxio_enable;
901 901 uint8_t m_done_traverse_dev;
902 902 uint8_t m_done_traverse_smp;
903 903 int m_diag_action_in_progress;
904 904 uint16_t m_dev_handle;
905 905 uint16_t m_smp_devhdl;
906 906
907 907 /*
908 908 * Event recording
909 909 */
910 910 uint8_t m_event_index;
911 911 uint32_t m_event_number;
912 912 uint32_t m_event_mask[4];
913 913 mptsas_event_entry_t m_events[MPTSAS_EVENT_QUEUE_SIZE];
914 914
915 915 /*
916 916 * FW diag Buffer List
917 917 */
918 918 mptsas_fw_diagnostic_buffer_t
919 919 m_fw_diag_buffer_list[MPI2_DIAG_BUF_TYPE_COUNT];
920 920
921 921 /* GEN3 support */
922 922 uint8_t m_MPI25;
923 923
924 924 /*
925 925 * Event Replay flag (MUR support)
926 926 */
927 927 uint8_t m_event_replay;
928 928
929 929 /*
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929 lines elided |
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930 930 * IR Capable flag
931 931 */
932 932 uint8_t m_ir_capable;
933 933
934 934 /*
935 935 * Is HBA processing a diag reset?
936 936 */
937 937 uint8_t m_in_reset;
938 938
939 939 /*
940 + * Task management protection
941 + */
942 + kmutex_t m_taskmgmt_mutex;
943 +
944 + /*
940 945 * per instance cmd data structures for task management cmds
941 946 */
942 947 m_event_struct_t m_event_task_mgmt; /* must be last */
943 948 /* ... scsi_pkt_size */
944 949 } mptsas_t;
945 950 #define MPTSAS_SIZE (sizeof (struct mptsas) - \
946 951 sizeof (struct scsi_pkt) + scsi_pkt_size())
947 952 /*
948 953 * Only one of below two conditions is satisfied, we
949 954 * think the target is associated to the iport and
950 955 * allow call into mptsas_probe_lun().
951 956 * 1. physicalsport == physport
952 957 * 2. (phymask & (1 << physport)) == 0
953 958 * The condition #2 is because LSI uses lowest PHY
954 959 * number as the value of physical port when auto port
955 960 * configuration.
956 961 */
957 962 #define IS_SAME_PORT(physicalport, physport, phymask, dynamicport) \
958 963 ((physicalport == physport) || (dynamicport && (phymask & \
959 964 (1 << physport))))
960 965
961 966 _NOTE(MUTEX_PROTECTS_DATA(mptsas::m_mutex, mptsas))
962 967 _NOTE(SCHEME_PROTECTS_DATA("safe sharing", mptsas::m_next))
963 968 _NOTE(SCHEME_PROTECTS_DATA("stable data", mptsas::m_dip mptsas::m_tran))
964 969 _NOTE(SCHEME_PROTECTS_DATA("stable data", mptsas::m_kmem_cache))
965 970 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_io_dma_attr.dma_attr_sgllen))
966 971 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_devid))
967 972 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_productid))
968 973 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_mpxio_enable))
969 974 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_instance))
970 975
971 976 /*
972 977 * These should eventually migrate into the mpt header files
973 978 * that may become the /kernel/misc/mpt module...
974 979 */
975 980 #define mptsas_init_std_hdr(hdl, mp, DevHandle, Lun, ChainOffset, Function) \
976 981 mptsas_put_msg_DevHandle(hdl, mp, DevHandle); \
977 982 mptsas_put_msg_ChainOffset(hdl, mp, ChainOffset); \
978 983 mptsas_put_msg_Function(hdl, mp, Function); \
979 984 mptsas_put_msg_Lun(hdl, mp, Lun)
980 985
981 986 #define mptsas_put_msg_DevHandle(hdl, mp, val) \
982 987 ddi_put16(hdl, &(mp)->DevHandle, (val))
983 988 #define mptsas_put_msg_ChainOffset(hdl, mp, val) \
984 989 ddi_put8(hdl, &(mp)->ChainOffset, (val))
985 990 #define mptsas_put_msg_Function(hdl, mp, val) \
986 991 ddi_put8(hdl, &(mp)->Function, (val))
987 992 #define mptsas_put_msg_Lun(hdl, mp, val) \
988 993 ddi_put8(hdl, &(mp)->LUN[1], (val))
989 994
990 995 #define mptsas_get_msg_Function(hdl, mp) \
991 996 ddi_get8(hdl, &(mp)->Function)
992 997
993 998 #define mptsas_get_msg_MsgFlags(hdl, mp) \
994 999 ddi_get8(hdl, &(mp)->MsgFlags)
995 1000
996 1001 #define MPTSAS_ENABLE_DRWE(hdl) \
997 1002 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \
998 1003 MPI2_WRSEQ_FLUSH_KEY_VALUE); \
999 1004 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \
1000 1005 MPI2_WRSEQ_1ST_KEY_VALUE); \
1001 1006 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \
1002 1007 MPI2_WRSEQ_2ND_KEY_VALUE); \
1003 1008 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \
1004 1009 MPI2_WRSEQ_3RD_KEY_VALUE); \
1005 1010 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \
1006 1011 MPI2_WRSEQ_4TH_KEY_VALUE); \
1007 1012 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \
1008 1013 MPI2_WRSEQ_5TH_KEY_VALUE); \
1009 1014 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \
1010 1015 MPI2_WRSEQ_6TH_KEY_VALUE);
1011 1016
1012 1017 /*
1013 1018 * m_options flags
1014 1019 */
1015 1020 #define MPTSAS_OPT_PM 0x01 /* Power Management */
1016 1021
1017 1022 /*
1018 1023 * m_softstate flags
1019 1024 */
1020 1025 #define MPTSAS_SS_DRAINING 0x02
1021 1026 #define MPTSAS_SS_QUIESCED 0x04
1022 1027 #define MPTSAS_SS_MSG_UNIT_RESET 0x08
1023 1028 #define MPTSAS_DID_MSG_UNIT_RESET 0x10
1024 1029
1025 1030 /*
1026 1031 * regspec defines.
1027 1032 */
1028 1033 #define CONFIG_SPACE 0 /* regset[0] - configuration space */
1029 1034 #define IO_SPACE 1 /* regset[1] - used for i/o mapped device */
1030 1035 #define MEM_SPACE 2 /* regset[2] - used for memory mapped device */
1031 1036 #define BASE_REG2 3 /* regset[3] - used for 875 scripts ram */
1032 1037
1033 1038 /*
1034 1039 * Handy constants
1035 1040 */
1036 1041 #define FALSE 0
1037 1042 #define TRUE 1
1038 1043 #define UNDEFINED -1
1039 1044 #define FAILED -2
1040 1045
1041 1046 /*
1042 1047 * power management.
1043 1048 */
1044 1049 #define MPTSAS_POWER_ON(mpt) { \
1045 1050 pci_config_put16(mpt->m_config_handle, mpt->m_pmcsr_offset, \
1046 1051 PCI_PMCSR_D0); \
1047 1052 delay(drv_usectohz(10000)); \
1048 1053 (void) pci_restore_config_regs(mpt->m_dip); \
1049 1054 mptsas_setup_cmd_reg(mpt); \
1050 1055 }
1051 1056
1052 1057 #define MPTSAS_POWER_OFF(mpt) { \
1053 1058 (void) pci_save_config_regs(mpt->m_dip); \
1054 1059 pci_config_put16(mpt->m_config_handle, mpt->m_pmcsr_offset, \
1055 1060 PCI_PMCSR_D3HOT); \
1056 1061 mpt->m_power_level = PM_LEVEL_D3; \
1057 1062 }
1058 1063
1059 1064 /*
1060 1065 * inq_dtype:
1061 1066 * Bits 5 through 7 are the Peripheral Device Qualifier
1062 1067 * 001b: device not connected to the LUN
1063 1068 * Bits 0 through 4 are the Peripheral Device Type
1064 1069 * 1fh: Unknown or no device type
1065 1070 *
1066 1071 * Although the inquiry may return success, the following value
1067 1072 * means no valid LUN connected.
1068 1073 */
1069 1074 #define MPTSAS_VALID_LUN(sd_inq) \
1070 1075 (((sd_inq->inq_dtype & 0xe0) != 0x20) && \
1071 1076 ((sd_inq->inq_dtype & 0x1f) != 0x1f))
1072 1077
1073 1078 /*
1074 1079 * Default is to have 10 retries on receiving QFULL status and
1075 1080 * each retry to be after 100 ms.
1076 1081 */
1077 1082 #define QFULL_RETRIES 10
1078 1083 #define QFULL_RETRY_INTERVAL 100
1079 1084
1080 1085 /*
1081 1086 * Handy macros
1082 1087 */
1083 1088 #define Tgt(sp) ((sp)->cmd_pkt->pkt_address.a_target)
1084 1089 #define Lun(sp) ((sp)->cmd_pkt->pkt_address.a_lun)
1085 1090
1086 1091 #define IS_HEX_DIGIT(n) (((n) >= '0' && (n) <= '9') || \
1087 1092 ((n) >= 'a' && (n) <= 'f') || ((n) >= 'A' && (n) <= 'F'))
1088 1093
1089 1094 /*
1090 1095 * poll time for mptsas_pollret() and mptsas_wait_intr()
1091 1096 */
1092 1097 #define MPTSAS_POLL_TIME 30000 /* 30 seconds */
1093 1098
1094 1099 /*
1095 1100 * default time for mptsas_do_passthru
1096 1101 */
1097 1102 #define MPTSAS_PASS_THRU_TIME_DEFAULT 60 /* 60 seconds */
1098 1103
1099 1104 /*
1100 1105 * macro to return the effective address of a given per-target field
1101 1106 */
1102 1107 #define EFF_ADDR(start, offset) ((start) + (offset))
1103 1108
1104 1109 #define SDEV2ADDR(devp) (&((devp)->sd_address))
1105 1110 #define SDEV2TRAN(devp) ((devp)->sd_address.a_hba_tran)
1106 1111 #define PKT2TRAN(pkt) ((pkt)->pkt_address.a_hba_tran)
1107 1112 #define ADDR2TRAN(ap) ((ap)->a_hba_tran)
1108 1113 #define DIP2TRAN(dip) (ddi_get_driver_private(dip))
1109 1114
1110 1115
1111 1116 #define TRAN2MPT(hba) ((mptsas_t *)(hba)->tran_hba_private)
1112 1117 #define DIP2MPT(dip) (TRAN2MPT((scsi_hba_tran_t *)DIP2TRAN(dip)))
1113 1118 #define SDEV2MPT(sd) (TRAN2MPT(SDEV2TRAN(sd)))
1114 1119 #define PKT2MPT(pkt) (TRAN2MPT(PKT2TRAN(pkt)))
1115 1120
1116 1121 #define ADDR2MPT(ap) (TRAN2MPT(ADDR2TRAN(ap)))
1117 1122
1118 1123 #define POLL_TIMEOUT (2 * SCSI_POLL_TIMEOUT * 1000000)
1119 1124 #define SHORT_POLL_TIMEOUT (1000000) /* in usec, about 1 secs */
1120 1125 #define MPTSAS_QUIESCE_TIMEOUT 1 /* 1 sec */
1121 1126 #define MPTSAS_PM_IDLE_TIMEOUT 60 /* 60 seconds */
1122 1127
1123 1128 #define MPTSAS_GET_ISTAT(mpt) (ddi_get32((mpt)->m_datap, \
1124 1129 &(mpt)->m_reg->HostInterruptStatus))
1125 1130
1126 1131 #define MPTSAS_SET_SIGP(P) \
1127 1132 ClrSetBits(mpt->m_devaddr + NREG_ISTAT, 0, NB_ISTAT_SIGP)
1128 1133
1129 1134 #define MPTSAS_RESET_SIGP(P) (void) ddi_get8(mpt->m_datap, \
1130 1135 (uint8_t *)(mpt->m_devaddr + NREG_CTEST2))
1131 1136
1132 1137 #define MPTSAS_GET_INTCODE(P) (ddi_get32(mpt->m_datap, \
1133 1138 (uint32_t *)(mpt->m_devaddr + NREG_DSPS)))
1134 1139
1135 1140
1136 1141 #define MPTSAS_START_CMD(mpt, req_desc) \
1137 1142 ddi_put32(mpt->m_datap, &mpt->m_reg->RequestDescriptorPostLow, \
1138 1143 req_desc & 0xffffffffu); \
1139 1144 ddi_put32(mpt->m_datap, &mpt->m_reg->RequestDescriptorPostHigh, \
1140 1145 (req_desc >> 32) & 0xffffffffu);
1141 1146
1142 1147 #define INTPENDING(mpt) \
1143 1148 (MPTSAS_GET_ISTAT(mpt) & MPI2_HIS_REPLY_DESCRIPTOR_INTERRUPT)
1144 1149
1145 1150 /*
1146 1151 * Mask all interrupts to disable
1147 1152 */
1148 1153 #define MPTSAS_DISABLE_INTR(mpt) \
1149 1154 ddi_put32((mpt)->m_datap, &(mpt)->m_reg->HostInterruptMask, \
1150 1155 (MPI2_HIM_RIM | MPI2_HIM_DIM | MPI2_HIM_RESET_IRQ_MASK))
1151 1156
1152 1157 /*
1153 1158 * Mask Doorbell and Reset interrupts to enable reply desc int.
1154 1159 */
1155 1160 #define MPTSAS_ENABLE_INTR(mpt) \
1156 1161 ddi_put32(mpt->m_datap, &mpt->m_reg->HostInterruptMask, \
1157 1162 (MPI2_HIM_DIM | MPI2_HIM_RESET_IRQ_MASK))
1158 1163
1159 1164 #define MPTSAS_GET_NEXT_REPLY(mpt, index) \
1160 1165 &((uint64_t *)(void *)mpt->m_post_queue)[index]
1161 1166
1162 1167 #define MPTSAS_GET_NEXT_FRAME(mpt, SMID) \
1163 1168 (mpt->m_req_frame + (mpt->m_req_frame_size * SMID))
1164 1169
1165 1170 #define ClrSetBits32(hdl, reg, clr, set) \
1166 1171 ddi_put32(hdl, (reg), \
1167 1172 ((ddi_get32(mpt->m_datap, (reg)) & ~(clr)) | (set)))
1168 1173
1169 1174 #define ClrSetBits(reg, clr, set) \
1170 1175 ddi_put8(mpt->m_datap, (uint8_t *)(reg), \
1171 1176 ((ddi_get8(mpt->m_datap, (uint8_t *)(reg)) & ~(clr)) | (set)))
1172 1177
1173 1178 #define MPTSAS_WAITQ_RM(mpt, cmdp) \
1174 1179 if ((cmdp = mpt->m_waitq) != NULL) { \
1175 1180 /* If the queue is now empty fix the tail pointer */ \
1176 1181 if ((mpt->m_waitq = cmdp->cmd_linkp) == NULL) \
1177 1182 mpt->m_waitqtail = &mpt->m_waitq; \
1178 1183 cmdp->cmd_linkp = NULL; \
1179 1184 cmdp->cmd_queued = FALSE; \
1180 1185 }
1181 1186
1182 1187 #define MPTSAS_TX_WAITQ_RM(mpt, cmdp) \
1183 1188 if ((cmdp = mpt->m_tx_waitq) != NULL) { \
1184 1189 /* If the queue is now empty fix the tail pointer */ \
1185 1190 if ((mpt->m_tx_waitq = cmdp->cmd_linkp) == NULL) \
1186 1191 mpt->m_tx_waitqtail = &mpt->m_tx_waitq; \
1187 1192 cmdp->cmd_linkp = NULL; \
1188 1193 cmdp->cmd_queued = FALSE; \
1189 1194 }
1190 1195
1191 1196 /*
1192 1197 * defaults for the global properties
1193 1198 */
1194 1199 #define DEFAULT_SCSI_OPTIONS SCSI_OPTIONS_DR
1195 1200 #define DEFAULT_TAG_AGE_LIMIT 2
1196 1201 #define DEFAULT_WD_TICK 1
1197 1202
1198 1203 /*
1199 1204 * invalid hostid.
1200 1205 */
1201 1206 #define MPTSAS_INVALID_HOSTID -1
1202 1207
1203 1208 /*
1204 1209 * Get/Set hostid from SCSI port configuration page
1205 1210 */
1206 1211 #define MPTSAS_GET_HOST_ID(configuration) (configuration & 0xFF)
1207 1212 #define MPTSAS_SET_HOST_ID(hostid) (hostid | ((1 << hostid) << 16))
1208 1213
1209 1214 /*
1210 1215 * Config space.
1211 1216 */
1212 1217 #define MPTSAS_LATENCY_TIMER 0x40
1213 1218
1214 1219 /*
1215 1220 * Offset to firmware version
1216 1221 */
1217 1222 #define MPTSAS_FW_VERSION_OFFSET 9
1218 1223
1219 1224 /*
1220 1225 * Offset and masks to get at the ProductId field
1221 1226 */
1222 1227 #define MPTSAS_FW_PRODUCTID_OFFSET 8
1223 1228 #define MPTSAS_FW_PRODUCTID_MASK 0xFFFF0000
1224 1229 #define MPTSAS_FW_PRODUCTID_SHIFT 16
1225 1230
1226 1231 /*
1227 1232 * Subsystem ID for HBAs.
1228 1233 */
1229 1234 #define MPTSAS_HBA_SUBSYSTEM_ID 0x10C0
1230 1235 #define MPTSAS_RHEA_SUBSYSTEM_ID 0x10B0
1231 1236
1232 1237 /*
1233 1238 * reset delay tick
1234 1239 */
1235 1240 #define MPTSAS_WATCH_RESET_DELAY_TICK 50 /* specified in milli seconds */
1236 1241
1237 1242 /*
1238 1243 * Ioc reset return values
1239 1244 */
1240 1245 #define MPTSAS_RESET_FAIL -1
1241 1246 #define MPTSAS_NO_RESET 0
1242 1247 #define MPTSAS_SUCCESS_HARDRESET 1
1243 1248 #define MPTSAS_SUCCESS_MUR 2
1244 1249
1245 1250 /*
1246 1251 * throttle support.
1247 1252 */
1248 1253 #define MAX_THROTTLE 32
1249 1254 #define HOLD_THROTTLE 0
1250 1255 #define DRAIN_THROTTLE -1
1251 1256 #define QFULL_THROTTLE -2
1252 1257
1253 1258 /*
1254 1259 * Passthrough/config request flags
1255 1260 */
1256 1261 #define MPTSAS_DATA_ALLOCATED 0x0001
1257 1262 #define MPTSAS_DATAOUT_ALLOCATED 0x0002
1258 1263 #define MPTSAS_REQUEST_POOL_CMD 0x0004
1259 1264 #define MPTSAS_ADDRESS_REPLY 0x0008
1260 1265 #define MPTSAS_CMD_TIMEOUT 0x0010
1261 1266
1262 1267 /*
1263 1268 * response code tlr flag
1264 1269 */
1265 1270 #define MPTSAS_SCSI_RESPONSE_CODE_TLR_OFF 0x02
1266 1271
1267 1272 /*
1268 1273 * System Events
1269 1274 */
1270 1275 #ifndef DDI_VENDOR_LSI
1271 1276 #define DDI_VENDOR_LSI "LSI"
1272 1277 #endif /* DDI_VENDOR_LSI */
1273 1278
1274 1279 /*
1275 1280 * Shared functions
1276 1281 */
1277 1282 int mptsas_save_cmd(struct mptsas *mpt, struct mptsas_cmd *cmd);
1278 1283 void mptsas_remove_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd);
1279 1284 void mptsas_waitq_add(mptsas_t *mpt, mptsas_cmd_t *cmd);
1280 1285 void mptsas_log(struct mptsas *mpt, int level, char *fmt, ...);
1281 1286 int mptsas_poll(mptsas_t *mpt, mptsas_cmd_t *poll_cmd, int polltime);
1282 1287 int mptsas_do_dma(mptsas_t *mpt, uint32_t size, int var, int (*callback)());
1283 1288 int mptsas_update_flash(mptsas_t *mpt, caddr_t ptrbuffer, uint32_t size,
1284 1289 uint8_t type, int mode);
1285 1290 int mptsas_check_flash(mptsas_t *mpt, caddr_t origfile, uint32_t size,
1286 1291 uint8_t type, int mode);
1287 1292 int mptsas_download_firmware();
1288 1293 int mptsas_can_download_firmware();
1289 1294 int mptsas_dma_alloc(mptsas_t *mpt, mptsas_dma_alloc_state_t *dma_statep);
1290 1295 void mptsas_dma_free(mptsas_dma_alloc_state_t *dma_statep);
1291 1296 mptsas_phymask_t mptsas_physport_to_phymask(mptsas_t *mpt, uint8_t physport);
1292 1297 void mptsas_fma_check(mptsas_t *mpt, mptsas_cmd_t *cmd);
1293 1298 int mptsas_check_acc_handle(ddi_acc_handle_t handle);
1294 1299 int mptsas_check_dma_handle(ddi_dma_handle_t handle);
1295 1300 void mptsas_fm_ereport(mptsas_t *mpt, char *detail);
1296 1301 int mptsas_dma_addr_create(mptsas_t *mpt, ddi_dma_attr_t dma_attr,
1297 1302 ddi_dma_handle_t *dma_hdp, ddi_acc_handle_t *acc_hdp, caddr_t *dma_memp,
1298 1303 uint32_t alloc_size, ddi_dma_cookie_t *cookiep);
1299 1304 void mptsas_dma_addr_destroy(ddi_dma_handle_t *, ddi_acc_handle_t *);
1300 1305
1301 1306 /*
1302 1307 * impl functions
1303 1308 */
1304 1309 int mptsas_ioc_wait_for_response(mptsas_t *mpt);
1305 1310 int mptsas_ioc_wait_for_doorbell(mptsas_t *mpt);
1306 1311 int mptsas_ioc_reset(mptsas_t *mpt, int);
1307 1312 int mptsas_send_handshake_msg(mptsas_t *mpt, caddr_t memp, int numbytes,
1308 1313 ddi_acc_handle_t accessp);
1309 1314 int mptsas_get_handshake_msg(mptsas_t *mpt, caddr_t memp, int numbytes,
1310 1315 ddi_acc_handle_t accessp);
1311 1316 int mptsas_send_config_request_msg(mptsas_t *mpt, uint8_t action,
1312 1317 uint8_t pagetype, uint32_t pageaddress, uint8_t pagenumber,
1313 1318 uint8_t pageversion, uint8_t pagelength, uint32_t SGEflagslength,
1314 1319 uint64_t SGEaddress);
1315 1320 int mptsas_send_extended_config_request_msg(mptsas_t *mpt, uint8_t action,
1316 1321 uint8_t extpagetype, uint32_t pageaddress, uint8_t pagenumber,
1317 1322 uint8_t pageversion, uint16_t extpagelength,
1318 1323 uint32_t SGEflagslength, uint64_t SGEaddress);
1319 1324
1320 1325 int mptsas_request_from_pool(mptsas_t *mpt, mptsas_cmd_t **cmd,
1321 1326 struct scsi_pkt **pkt);
1322 1327 void mptsas_return_to_pool(mptsas_t *mpt, mptsas_cmd_t *cmd);
1323 1328 void mptsas_destroy_ioc_event_cmd(mptsas_t *mpt);
1324 1329 void mptsas_start_config_page_access(mptsas_t *mpt, mptsas_cmd_t *cmd);
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1325 1330 int mptsas_access_config_page(mptsas_t *mpt, uint8_t action, uint8_t page_type,
1326 1331 uint8_t page_number, uint32_t page_address, int (*callback) (mptsas_t *,
1327 1332 caddr_t, ddi_acc_handle_t, uint16_t, uint32_t, va_list), ...);
1328 1333
1329 1334 int mptsas_ioc_task_management(mptsas_t *mpt, int task_type,
1330 1335 uint16_t dev_handle, int lun, uint8_t *reply, uint32_t reply_size,
1331 1336 int mode);
1332 1337 int mptsas_send_event_ack(mptsas_t *mpt, uint32_t event, uint32_t eventcntx);
1333 1338 void mptsas_send_pending_event_ack(mptsas_t *mpt);
1334 1339 void mptsas_set_throttle(struct mptsas *mpt, mptsas_target_t *ptgt, int what);
1335 -int mptsas_restart_ioc(mptsas_t *mpt);
1340 +int mptsas_reset_handler(mptsas_t *mpt);
1336 1341 void mptsas_update_driver_data(struct mptsas *mpt);
1337 1342 uint64_t mptsas_get_sata_guid(mptsas_t *mpt, mptsas_target_t *ptgt, int lun);
1338 1343
1339 1344 /*
1340 1345 * init functions
1341 1346 */
1342 1347 int mptsas_ioc_get_facts(mptsas_t *mpt);
1343 1348 int mptsas_ioc_get_port_facts(mptsas_t *mpt, int port);
1344 1349 int mptsas_ioc_enable_port(mptsas_t *mpt);
1345 1350 int mptsas_ioc_enable_event_notification(mptsas_t *mpt);
1346 1351 int mptsas_ioc_init(mptsas_t *mpt);
1347 1352
1348 1353 /*
1349 1354 * configuration pages operation
1350 1355 */
1351 1356 int mptsas_get_sas_device_page0(mptsas_t *mpt, uint32_t page_address,
1352 1357 uint16_t *dev_handle, uint64_t *sas_wwn, uint32_t *dev_info,
1353 1358 uint8_t *physport, uint8_t *phynum, uint16_t *pdevhandle,
1354 1359 uint16_t *slot_num, uint16_t *enclosure, uint16_t *io_flags);
1355 1360 int mptsas_get_sas_io_unit_page(mptsas_t *mpt);
1356 1361 int mptsas_get_sas_io_unit_page_hndshk(mptsas_t *mpt);
1357 1362 int mptsas_get_sas_expander_page0(mptsas_t *mpt, uint32_t page_address,
1358 1363 mptsas_smp_t *info);
1359 1364 int mptsas_set_ioc_params(mptsas_t *mpt);
1360 1365 int mptsas_get_manufacture_page5(mptsas_t *mpt);
1361 1366 int mptsas_get_sas_port_page0(mptsas_t *mpt, uint32_t page_address,
1362 1367 uint64_t *sas_wwn, uint8_t *portwidth);
1363 1368 int mptsas_get_bios_page3(mptsas_t *mpt, uint32_t *bios_version);
1364 1369 int
1365 1370 mptsas_get_sas_phy_page0(mptsas_t *mpt, uint32_t page_address,
1366 1371 smhba_info_t *info);
1367 1372 int
1368 1373 mptsas_get_sas_phy_page1(mptsas_t *mpt, uint32_t page_address,
1369 1374 smhba_info_t *info);
1370 1375 int
1371 1376 mptsas_get_manufacture_page0(mptsas_t *mpt);
1372 1377 void
1373 1378 mptsas_create_phy_stats(mptsas_t *mpt, char *iport, dev_info_t *dip);
1374 1379 void mptsas_destroy_phy_stats(mptsas_t *mpt);
1375 1380 int mptsas_smhba_phy_init(mptsas_t *mpt);
1376 1381 /*
1377 1382 * RAID functions
1378 1383 */
1379 1384 int mptsas_get_raid_settings(mptsas_t *mpt, mptsas_raidvol_t *raidvol);
1380 1385 int mptsas_get_raid_info(mptsas_t *mpt);
1381 1386 int mptsas_get_physdisk_settings(mptsas_t *mpt, mptsas_raidvol_t *raidvol,
1382 1387 uint8_t physdisknum);
1383 1388 int mptsas_delete_volume(mptsas_t *mpt, uint16_t volid);
1384 1389 void mptsas_raid_action_system_shutdown(mptsas_t *mpt);
1385 1390
1386 1391 #define MPTSAS_IOCSTATUS(status) (status & MPI2_IOCSTATUS_MASK)
1387 1392 /*
1388 1393 * debugging.
1389 1394 * MPTSAS_DBGLOG_LINECNT must be a power of 2.
1390 1395 */
1391 1396 #define MPTSAS_DBGLOG_LINECNT 128
1392 1397 #define MPTSAS_DBGLOG_LINELEN 256
1393 1398 #define MPTSAS_DBGLOG_BUFSIZE (MPTSAS_DBGLOG_LINECNT * MPTSAS_DBGLOG_LINELEN)
1394 1399
1395 1400 #if defined(MPTSAS_DEBUG)
1396 1401
1397 1402 extern uint32_t mptsas_debugprt_flags;
1398 1403 extern uint32_t mptsas_debuglog_flags;
1399 1404
1400 1405 void mptsas_printf(char *fmt, ...);
1401 1406 void mptsas_debug_log(char *fmt, ...);
1402 1407
1403 1408 #define MPTSAS_DBGPR(m, args) \
1404 1409 if (mptsas_debugprt_flags & (m)) \
1405 1410 mptsas_printf args; \
1406 1411 if (mptsas_debuglog_flags & (m)) \
1407 1412 mptsas_debug_log args
1408 1413 #else /* ! defined(MPTSAS_DEBUG) */
1409 1414 #define MPTSAS_DBGPR(m, args)
1410 1415 #endif /* defined(MPTSAS_DEBUG) */
1411 1416
1412 1417 #define NDBG0(args) MPTSAS_DBGPR(0x01, args) /* init */
1413 1418 #define NDBG1(args) MPTSAS_DBGPR(0x02, args) /* normal running */
1414 1419 #define NDBG2(args) MPTSAS_DBGPR(0x04, args) /* property handling */
1415 1420 #define NDBG3(args) MPTSAS_DBGPR(0x08, args) /* pkt handling */
1416 1421
1417 1422 #define NDBG4(args) MPTSAS_DBGPR(0x10, args) /* kmem alloc/free */
1418 1423 #define NDBG5(args) MPTSAS_DBGPR(0x20, args) /* polled cmds */
1419 1424 #define NDBG6(args) MPTSAS_DBGPR(0x40, args) /* interrupts */
1420 1425 #define NDBG7(args) MPTSAS_DBGPR(0x80, args) /* queue handling */
1421 1426
1422 1427 #define NDBG8(args) MPTSAS_DBGPR(0x0100, args) /* arq */
1423 1428 #define NDBG9(args) MPTSAS_DBGPR(0x0200, args) /* Tagged Q'ing */
1424 1429 #define NDBG10(args) MPTSAS_DBGPR(0x0400, args) /* halting chip */
1425 1430 #define NDBG11(args) MPTSAS_DBGPR(0x0800, args) /* power management */
1426 1431
1427 1432 #define NDBG12(args) MPTSAS_DBGPR(0x1000, args) /* enumeration */
1428 1433 #define NDBG13(args) MPTSAS_DBGPR(0x2000, args) /* configuration page */
1429 1434 #define NDBG14(args) MPTSAS_DBGPR(0x4000, args) /* LED control */
1430 1435 #define NDBG15(args) MPTSAS_DBGPR(0x8000, args) /* Passthrough */
1431 1436
1432 1437 #define NDBG16(args) MPTSAS_DBGPR(0x010000, args) /* SAS Broadcasts */
1433 1438 #define NDBG17(args) MPTSAS_DBGPR(0x020000, args) /* scatter/gather */
1434 1439 #define NDBG18(args) MPTSAS_DBGPR(0x040000, args)
1435 1440 #define NDBG19(args) MPTSAS_DBGPR(0x080000, args) /* handshaking */
1436 1441
1437 1442 #define NDBG20(args) MPTSAS_DBGPR(0x100000, args) /* events */
1438 1443 #define NDBG21(args) MPTSAS_DBGPR(0x200000, args) /* dma */
1439 1444 #define NDBG22(args) MPTSAS_DBGPR(0x400000, args) /* reset */
1440 1445 #define NDBG23(args) MPTSAS_DBGPR(0x800000, args) /* abort */
1441 1446
1442 1447 #define NDBG24(args) MPTSAS_DBGPR(0x1000000, args) /* capabilities */
1443 1448 #define NDBG25(args) MPTSAS_DBGPR(0x2000000, args) /* flushing */
1444 1449 #define NDBG26(args) MPTSAS_DBGPR(0x4000000, args)
1445 1450 #define NDBG27(args) MPTSAS_DBGPR(0x8000000, args) /* passthrough */
1446 1451
1447 1452 #define NDBG28(args) MPTSAS_DBGPR(0x10000000, args) /* hotplug */
1448 1453 #define NDBG29(args) MPTSAS_DBGPR(0x20000000, args) /* timeouts */
1449 1454 #define NDBG30(args) MPTSAS_DBGPR(0x40000000, args) /* mptsas_watch */
1450 1455 #define NDBG31(args) MPTSAS_DBGPR(0x80000000, args) /* negotations */
1451 1456
1452 1457 /*
1453 1458 * auto request sense
1454 1459 */
1455 1460 #define RQ_MAKECOM_COMMON(pkt, flag, cmd) \
1456 1461 (pkt)->pkt_flags = (flag), \
1457 1462 ((union scsi_cdb *)(pkt)->pkt_cdbp)->scc_cmd = (cmd), \
1458 1463 ((union scsi_cdb *)(pkt)->pkt_cdbp)->scc_lun = \
1459 1464 (pkt)->pkt_address.a_lun
1460 1465
1461 1466 #define RQ_MAKECOM_G0(pkt, flag, cmd, addr, cnt) \
1462 1467 RQ_MAKECOM_COMMON((pkt), (flag), (cmd)), \
1463 1468 FORMG0ADDR(((union scsi_cdb *)(pkt)->pkt_cdbp), (addr)), \
1464 1469 FORMG0COUNT(((union scsi_cdb *)(pkt)->pkt_cdbp), (cnt))
1465 1470
1466 1471
1467 1472 #ifdef __cplusplus
1468 1473 }
1469 1474 #endif
1470 1475
1471 1476 #endif /* _SYS_SCSI_ADAPTERS_MPTVAR_H */
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