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7813 mpt_sas does not like concurrent HBA resets
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--- old/usr/src/uts/common/io/scsi/adapters/mpt_sas/mptsas.c
+++ new/usr/src/uts/common/io/scsi/adapters/mpt_sas/mptsas.c
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21
22 22 /*
23 23 * Copyright (c) 2009, 2010, Oracle and/or its affiliates. All rights reserved.
24 24 * Copyright 2016 Nexenta Systems, Inc. All rights reserved.
25 25 * Copyright (c) 2014, Joyent, Inc. All rights reserved.
26 26 * Copyright 2014 OmniTI Computer Consulting, Inc. All rights reserved.
27 27 * Copyright (c) 2014, Tegile Systems Inc. All rights reserved.
28 28 */
29 29
30 30 /*
31 31 * Copyright (c) 2000 to 2010, LSI Corporation.
32 32 * All rights reserved.
33 33 *
34 34 * Redistribution and use in source and binary forms of all code within
35 35 * this file that is exclusively owned by LSI, with or without
36 36 * modification, is permitted provided that, in addition to the CDDL 1.0
37 37 * License requirements, the following conditions are met:
38 38 *
39 39 * Neither the name of the author nor the names of its contributors may be
40 40 * used to endorse or promote products derived from this software without
41 41 * specific prior written permission.
42 42 *
43 43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
44 44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
45 45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
46 46 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
47 47 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
48 48 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
49 49 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
50 50 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
51 51 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
52 52 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
53 53 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
54 54 * DAMAGE.
55 55 */
56 56
57 57 /*
58 58 * mptsas - This is a driver based on LSI Logic's MPT2.0/2.5 interface.
59 59 *
60 60 */
61 61
62 62 #if defined(lint) || defined(DEBUG)
63 63 #define MPTSAS_DEBUG
64 64 #endif
65 65
66 66 /*
67 67 * standard header files.
68 68 */
69 69 #include <sys/note.h>
70 70 #include <sys/scsi/scsi.h>
71 71 #include <sys/pci.h>
72 72 #include <sys/file.h>
73 73 #include <sys/policy.h>
74 74 #include <sys/model.h>
75 75 #include <sys/sysevent.h>
76 76 #include <sys/sysevent/eventdefs.h>
77 77 #include <sys/sysevent/dr.h>
78 78 #include <sys/sata/sata_defs.h>
79 79 #include <sys/sata/sata_hba.h>
80 80 #include <sys/scsi/generic/sas.h>
81 81 #include <sys/scsi/impl/scsi_sas.h>
82 82
83 83 #pragma pack(1)
84 84 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_type.h>
85 85 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2.h>
86 86 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_cnfg.h>
87 87 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_init.h>
88 88 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_ioc.h>
89 89 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_sas.h>
90 90 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_tool.h>
91 91 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_raid.h>
92 92 #pragma pack()
93 93
94 94 /*
95 95 * private header files.
96 96 *
97 97 */
98 98 #include <sys/scsi/impl/scsi_reset_notify.h>
99 99 #include <sys/scsi/adapters/mpt_sas/mptsas_var.h>
100 100 #include <sys/scsi/adapters/mpt_sas/mptsas_ioctl.h>
101 101 #include <sys/scsi/adapters/mpt_sas/mptsas_smhba.h>
102 102 #include <sys/scsi/adapters/mpt_sas/mptsas_hash.h>
103 103 #include <sys/raidioctl.h>
104 104
105 105 #include <sys/fs/dv_node.h> /* devfs_clean */
106 106
107 107 /*
108 108 * FMA header files
109 109 */
110 110 #include <sys/ddifm.h>
111 111 #include <sys/fm/protocol.h>
112 112 #include <sys/fm/util.h>
113 113 #include <sys/fm/io/ddi.h>
114 114
115 115 /*
116 116 * autoconfiguration data and routines.
117 117 */
118 118 static int mptsas_attach(dev_info_t *dip, ddi_attach_cmd_t cmd);
119 119 static int mptsas_detach(dev_info_t *devi, ddi_detach_cmd_t cmd);
120 120 static int mptsas_power(dev_info_t *dip, int component, int level);
121 121
122 122 /*
123 123 * cb_ops function
124 124 */
125 125 static int mptsas_ioctl(dev_t dev, int cmd, intptr_t data, int mode,
126 126 cred_t *credp, int *rval);
127 127 #ifdef __sparc
128 128 static int mptsas_reset(dev_info_t *devi, ddi_reset_cmd_t cmd);
129 129 #else /* __sparc */
130 130 static int mptsas_quiesce(dev_info_t *devi);
131 131 #endif /* __sparc */
132 132
133 133 /*
134 134 * Resource initilaization for hardware
135 135 */
136 136 static void mptsas_setup_cmd_reg(mptsas_t *mpt);
137 137 static void mptsas_disable_bus_master(mptsas_t *mpt);
138 138 static void mptsas_hba_fini(mptsas_t *mpt);
139 139 static void mptsas_cfg_fini(mptsas_t *mptsas_blkp);
140 140 static int mptsas_hba_setup(mptsas_t *mpt);
141 141 static void mptsas_hba_teardown(mptsas_t *mpt);
142 142 static int mptsas_config_space_init(mptsas_t *mpt);
143 143 static void mptsas_config_space_fini(mptsas_t *mpt);
144 144 static void mptsas_iport_register(mptsas_t *mpt);
145 145 static int mptsas_smp_setup(mptsas_t *mpt);
146 146 static void mptsas_smp_teardown(mptsas_t *mpt);
147 147 static int mptsas_cache_create(mptsas_t *mpt);
148 148 static void mptsas_cache_destroy(mptsas_t *mpt);
149 149 static int mptsas_alloc_request_frames(mptsas_t *mpt);
150 150 static int mptsas_alloc_sense_bufs(mptsas_t *mpt);
151 151 static int mptsas_alloc_reply_frames(mptsas_t *mpt);
152 152 static int mptsas_alloc_free_queue(mptsas_t *mpt);
153 153 static int mptsas_alloc_post_queue(mptsas_t *mpt);
154 154 static void mptsas_alloc_reply_args(mptsas_t *mpt);
155 155 static int mptsas_alloc_extra_sgl_frame(mptsas_t *mpt, mptsas_cmd_t *cmd);
156 156 static void mptsas_free_extra_sgl_frame(mptsas_t *mpt, mptsas_cmd_t *cmd);
157 157 static int mptsas_init_chip(mptsas_t *mpt, int first_time);
158 158
159 159 /*
160 160 * SCSA function prototypes
161 161 */
162 162 static int mptsas_scsi_start(struct scsi_address *ap, struct scsi_pkt *pkt);
163 163 static int mptsas_scsi_reset(struct scsi_address *ap, int level);
164 164 static int mptsas_scsi_abort(struct scsi_address *ap, struct scsi_pkt *pkt);
165 165 static int mptsas_scsi_getcap(struct scsi_address *ap, char *cap, int tgtonly);
166 166 static int mptsas_scsi_setcap(struct scsi_address *ap, char *cap, int value,
167 167 int tgtonly);
168 168 static void mptsas_scsi_dmafree(struct scsi_address *ap, struct scsi_pkt *pkt);
169 169 static struct scsi_pkt *mptsas_scsi_init_pkt(struct scsi_address *ap,
170 170 struct scsi_pkt *pkt, struct buf *bp, int cmdlen, int statuslen,
171 171 int tgtlen, int flags, int (*callback)(), caddr_t arg);
172 172 static void mptsas_scsi_sync_pkt(struct scsi_address *ap, struct scsi_pkt *pkt);
173 173 static void mptsas_scsi_destroy_pkt(struct scsi_address *ap,
174 174 struct scsi_pkt *pkt);
175 175 static int mptsas_scsi_tgt_init(dev_info_t *hba_dip, dev_info_t *tgt_dip,
176 176 scsi_hba_tran_t *hba_tran, struct scsi_device *sd);
177 177 static void mptsas_scsi_tgt_free(dev_info_t *hba_dip, dev_info_t *tgt_dip,
178 178 scsi_hba_tran_t *hba_tran, struct scsi_device *sd);
179 179 static int mptsas_scsi_reset_notify(struct scsi_address *ap, int flag,
180 180 void (*callback)(caddr_t), caddr_t arg);
181 181 static int mptsas_get_name(struct scsi_device *sd, char *name, int len);
182 182 static int mptsas_get_bus_addr(struct scsi_device *sd, char *name, int len);
183 183 static int mptsas_scsi_quiesce(dev_info_t *dip);
184 184 static int mptsas_scsi_unquiesce(dev_info_t *dip);
185 185 static int mptsas_bus_config(dev_info_t *pdip, uint_t flags,
186 186 ddi_bus_config_op_t op, void *arg, dev_info_t **childp);
187 187
188 188 /*
189 189 * SMP functions
190 190 */
191 191 static int mptsas_smp_start(struct smp_pkt *smp_pkt);
192 192
193 193 /*
194 194 * internal function prototypes.
195 195 */
196 196 static void mptsas_list_add(mptsas_t *mpt);
197 197 static void mptsas_list_del(mptsas_t *mpt);
198 198
199 199 static int mptsas_quiesce_bus(mptsas_t *mpt);
200 200 static int mptsas_unquiesce_bus(mptsas_t *mpt);
201 201
202 202 static int mptsas_alloc_handshake_msg(mptsas_t *mpt, size_t alloc_size);
203 203 static void mptsas_free_handshake_msg(mptsas_t *mpt);
204 204
205 205 static void mptsas_ncmds_checkdrain(void *arg);
206 206
207 207 static int mptsas_prepare_pkt(mptsas_cmd_t *cmd);
208 208 static int mptsas_accept_pkt(mptsas_t *mpt, mptsas_cmd_t *sp);
209 209 static int mptsas_accept_txwq_and_pkt(mptsas_t *mpt, mptsas_cmd_t *sp);
210 210 static void mptsas_accept_tx_waitq(mptsas_t *mpt);
211 211
212 212 static int mptsas_do_detach(dev_info_t *dev);
213 213 static int mptsas_do_scsi_reset(mptsas_t *mpt, uint16_t devhdl);
214 214 static int mptsas_do_scsi_abort(mptsas_t *mpt, int target, int lun,
215 215 struct scsi_pkt *pkt);
216 216 static int mptsas_scsi_capchk(char *cap, int tgtonly, int *cidxp);
217 217
218 218 static void mptsas_handle_qfull(mptsas_t *mpt, mptsas_cmd_t *cmd);
219 219 static void mptsas_handle_event(void *args);
220 220 static int mptsas_handle_event_sync(void *args);
221 221 static void mptsas_handle_dr(void *args);
222 222 static void mptsas_handle_topo_change(mptsas_topo_change_list_t *topo_node,
223 223 dev_info_t *pdip);
224 224
225 225 static void mptsas_restart_cmd(void *);
226 226
227 227 static void mptsas_flush_hba(mptsas_t *mpt);
228 228 static void mptsas_flush_target(mptsas_t *mpt, ushort_t target, int lun,
229 229 uint8_t tasktype);
230 230 static void mptsas_set_pkt_reason(mptsas_t *mpt, mptsas_cmd_t *cmd,
231 231 uchar_t reason, uint_t stat);
232 232
233 233 static uint_t mptsas_intr(caddr_t arg1, caddr_t arg2);
234 234 static void mptsas_process_intr(mptsas_t *mpt,
235 235 pMpi2ReplyDescriptorsUnion_t reply_desc_union);
236 236 static void mptsas_handle_scsi_io_success(mptsas_t *mpt,
237 237 pMpi2ReplyDescriptorsUnion_t reply_desc);
238 238 static void mptsas_handle_address_reply(mptsas_t *mpt,
239 239 pMpi2ReplyDescriptorsUnion_t reply_desc);
240 240 static int mptsas_wait_intr(mptsas_t *mpt, int polltime);
241 241 static void mptsas_sge_setup(mptsas_t *mpt, mptsas_cmd_t *cmd,
242 242 uint32_t *control, pMpi2SCSIIORequest_t frame, ddi_acc_handle_t acc_hdl);
243 243
244 244 static void mptsas_watch(void *arg);
245 245 static void mptsas_watchsubr(mptsas_t *mpt);
246 246 static void mptsas_cmd_timeout(mptsas_t *mpt, mptsas_target_t *ptgt);
247 247
248 248 static void mptsas_start_passthru(mptsas_t *mpt, mptsas_cmd_t *cmd);
249 249 static int mptsas_do_passthru(mptsas_t *mpt, uint8_t *request, uint8_t *reply,
250 250 uint8_t *data, uint32_t request_size, uint32_t reply_size,
251 251 uint32_t data_size, uint32_t direction, uint8_t *dataout,
252 252 uint32_t dataout_size, short timeout, int mode);
253 253 static int mptsas_free_devhdl(mptsas_t *mpt, uint16_t devhdl);
254 254
255 255 static uint8_t mptsas_get_fw_diag_buffer_number(mptsas_t *mpt,
256 256 uint32_t unique_id);
257 257 static void mptsas_start_diag(mptsas_t *mpt, mptsas_cmd_t *cmd);
258 258 static int mptsas_post_fw_diag_buffer(mptsas_t *mpt,
259 259 mptsas_fw_diagnostic_buffer_t *pBuffer, uint32_t *return_code);
260 260 static int mptsas_release_fw_diag_buffer(mptsas_t *mpt,
261 261 mptsas_fw_diagnostic_buffer_t *pBuffer, uint32_t *return_code,
262 262 uint32_t diag_type);
263 263 static int mptsas_diag_register(mptsas_t *mpt,
264 264 mptsas_fw_diag_register_t *diag_register, uint32_t *return_code);
265 265 static int mptsas_diag_unregister(mptsas_t *mpt,
266 266 mptsas_fw_diag_unregister_t *diag_unregister, uint32_t *return_code);
267 267 static int mptsas_diag_query(mptsas_t *mpt, mptsas_fw_diag_query_t *diag_query,
268 268 uint32_t *return_code);
269 269 static int mptsas_diag_read_buffer(mptsas_t *mpt,
270 270 mptsas_diag_read_buffer_t *diag_read_buffer, uint8_t *ioctl_buf,
271 271 uint32_t *return_code, int ioctl_mode);
272 272 static int mptsas_diag_release(mptsas_t *mpt,
273 273 mptsas_fw_diag_release_t *diag_release, uint32_t *return_code);
274 274 static int mptsas_do_diag_action(mptsas_t *mpt, uint32_t action,
275 275 uint8_t *diag_action, uint32_t length, uint32_t *return_code,
276 276 int ioctl_mode);
277 277 static int mptsas_diag_action(mptsas_t *mpt, mptsas_diag_action_t *data,
278 278 int mode);
279 279
280 280 static int mptsas_pkt_alloc_extern(mptsas_t *mpt, mptsas_cmd_t *cmd,
281 281 int cmdlen, int tgtlen, int statuslen, int kf);
282 282 static void mptsas_pkt_destroy_extern(mptsas_t *mpt, mptsas_cmd_t *cmd);
283 283
284 284 static int mptsas_kmem_cache_constructor(void *buf, void *cdrarg, int kmflags);
285 285 static void mptsas_kmem_cache_destructor(void *buf, void *cdrarg);
286 286
287 287 static int mptsas_cache_frames_constructor(void *buf, void *cdrarg,
288 288 int kmflags);
289 289 static void mptsas_cache_frames_destructor(void *buf, void *cdrarg);
290 290
291 291 static void mptsas_check_scsi_io_error(mptsas_t *mpt, pMpi2SCSIIOReply_t reply,
292 292 mptsas_cmd_t *cmd);
293 293 static void mptsas_check_task_mgt(mptsas_t *mpt,
294 294 pMpi2SCSIManagementReply_t reply, mptsas_cmd_t *cmd);
295 295 static int mptsas_send_scsi_cmd(mptsas_t *mpt, struct scsi_address *ap,
296 296 mptsas_target_t *ptgt, uchar_t *cdb, int cdblen, struct buf *data_bp,
297 297 int *resid);
298 298
299 299 static int mptsas_alloc_active_slots(mptsas_t *mpt, int flag);
300 300 static void mptsas_free_active_slots(mptsas_t *mpt);
301 301 static int mptsas_start_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd);
302 302
303 303 static void mptsas_restart_hba(mptsas_t *mpt);
304 304 static void mptsas_restart_waitq(mptsas_t *mpt);
305 305
306 306 static void mptsas_deliver_doneq_thread(mptsas_t *mpt);
307 307 static void mptsas_doneq_add(mptsas_t *mpt, mptsas_cmd_t *cmd);
308 308 static void mptsas_doneq_mv(mptsas_t *mpt, uint64_t t);
309 309
310 310 static mptsas_cmd_t *mptsas_doneq_thread_rm(mptsas_t *mpt, uint64_t t);
311 311 static void mptsas_doneq_empty(mptsas_t *mpt);
312 312 static void mptsas_doneq_thread(mptsas_doneq_thread_arg_t *arg);
313 313
314 314 static mptsas_cmd_t *mptsas_waitq_rm(mptsas_t *mpt);
315 315 static void mptsas_waitq_delete(mptsas_t *mpt, mptsas_cmd_t *cmd);
316 316 static mptsas_cmd_t *mptsas_tx_waitq_rm(mptsas_t *mpt);
317 317 static void mptsas_tx_waitq_delete(mptsas_t *mpt, mptsas_cmd_t *cmd);
318 318
319 319
320 320 static void mptsas_start_watch_reset_delay();
321 321 static void mptsas_setup_bus_reset_delay(mptsas_t *mpt);
322 322 static void mptsas_watch_reset_delay(void *arg);
323 323 static int mptsas_watch_reset_delay_subr(mptsas_t *mpt);
324 324
325 325 /*
326 326 * helper functions
327 327 */
328 328 static void mptsas_dump_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd);
329 329
330 330 static dev_info_t *mptsas_find_child(dev_info_t *pdip, char *name);
331 331 static dev_info_t *mptsas_find_child_phy(dev_info_t *pdip, uint8_t phy);
332 332 static dev_info_t *mptsas_find_child_addr(dev_info_t *pdip, uint64_t sasaddr,
333 333 int lun);
334 334 static mdi_pathinfo_t *mptsas_find_path_addr(dev_info_t *pdip, uint64_t sasaddr,
335 335 int lun);
336 336 static mdi_pathinfo_t *mptsas_find_path_phy(dev_info_t *pdip, uint8_t phy);
337 337 static dev_info_t *mptsas_find_smp_child(dev_info_t *pdip, char *str_wwn);
338 338
339 339 static int mptsas_parse_address(char *name, uint64_t *wwid, uint8_t *phy,
340 340 int *lun);
341 341 static int mptsas_parse_smp_name(char *name, uint64_t *wwn);
342 342
343 343 static mptsas_target_t *mptsas_phy_to_tgt(mptsas_t *mpt,
344 344 mptsas_phymask_t phymask, uint8_t phy);
345 345 static mptsas_target_t *mptsas_wwid_to_ptgt(mptsas_t *mpt,
346 346 mptsas_phymask_t phymask, uint64_t wwid);
347 347 static mptsas_smp_t *mptsas_wwid_to_psmp(mptsas_t *mpt,
348 348 mptsas_phymask_t phymask, uint64_t wwid);
349 349
350 350 static int mptsas_inquiry(mptsas_t *mpt, mptsas_target_t *ptgt, int lun,
351 351 uchar_t page, unsigned char *buf, int len, int *rlen, uchar_t evpd);
352 352
353 353 static int mptsas_get_target_device_info(mptsas_t *mpt, uint32_t page_address,
354 354 uint16_t *handle, mptsas_target_t **pptgt);
355 355 static void mptsas_update_phymask(mptsas_t *mpt);
356 356
357 357 static int mptsas_send_sep(mptsas_t *mpt, mptsas_target_t *ptgt,
358 358 uint32_t *status, uint8_t cmd);
359 359 static dev_info_t *mptsas_get_dip_from_dev(dev_t dev,
360 360 mptsas_phymask_t *phymask);
361 361 static mptsas_target_t *mptsas_addr_to_ptgt(mptsas_t *mpt, char *addr,
362 362 mptsas_phymask_t phymask);
363 363 static int mptsas_flush_led_status(mptsas_t *mpt, mptsas_target_t *ptgt);
364 364
365 365
366 366 /*
367 367 * Enumeration / DR functions
368 368 */
369 369 static void mptsas_config_all(dev_info_t *pdip);
370 370 static int mptsas_config_one_addr(dev_info_t *pdip, uint64_t sasaddr, int lun,
371 371 dev_info_t **lundip);
372 372 static int mptsas_config_one_phy(dev_info_t *pdip, uint8_t phy, int lun,
373 373 dev_info_t **lundip);
374 374
375 375 static int mptsas_config_target(dev_info_t *pdip, mptsas_target_t *ptgt);
376 376 static int mptsas_offline_target(dev_info_t *pdip, char *name);
377 377
378 378 static int mptsas_config_raid(dev_info_t *pdip, uint16_t target,
379 379 dev_info_t **dip);
380 380
381 381 static int mptsas_config_luns(dev_info_t *pdip, mptsas_target_t *ptgt);
382 382 static int mptsas_probe_lun(dev_info_t *pdip, int lun,
383 383 dev_info_t **dip, mptsas_target_t *ptgt);
384 384
385 385 static int mptsas_create_lun(dev_info_t *pdip, struct scsi_inquiry *sd_inq,
386 386 dev_info_t **dip, mptsas_target_t *ptgt, int lun);
387 387
388 388 static int mptsas_create_phys_lun(dev_info_t *pdip, struct scsi_inquiry *sd,
389 389 char *guid, dev_info_t **dip, mptsas_target_t *ptgt, int lun);
390 390 static int mptsas_create_virt_lun(dev_info_t *pdip, struct scsi_inquiry *sd,
391 391 char *guid, dev_info_t **dip, mdi_pathinfo_t **pip, mptsas_target_t *ptgt,
392 392 int lun);
393 393
394 394 static void mptsas_offline_missed_luns(dev_info_t *pdip,
395 395 uint16_t *repluns, int lun_cnt, mptsas_target_t *ptgt);
396 396 static int mptsas_offline_lun(dev_info_t *pdip, dev_info_t *rdip,
397 397 mdi_pathinfo_t *rpip, uint_t flags);
398 398
399 399 static int mptsas_config_smp(dev_info_t *pdip, uint64_t sas_wwn,
400 400 dev_info_t **smp_dip);
401 401 static int mptsas_offline_smp(dev_info_t *pdip, mptsas_smp_t *smp_node,
402 402 uint_t flags);
403 403
404 404 static int mptsas_event_query(mptsas_t *mpt, mptsas_event_query_t *data,
405 405 int mode, int *rval);
406 406 static int mptsas_event_enable(mptsas_t *mpt, mptsas_event_enable_t *data,
407 407 int mode, int *rval);
408 408 static int mptsas_event_report(mptsas_t *mpt, mptsas_event_report_t *data,
409 409 int mode, int *rval);
410 410 static void mptsas_record_event(void *args);
411 411 static int mptsas_reg_access(mptsas_t *mpt, mptsas_reg_access_t *data,
412 412 int mode);
413 413
414 414 mptsas_target_t *mptsas_tgt_alloc(refhash_t *, uint16_t, uint64_t,
415 415 uint32_t, mptsas_phymask_t, uint8_t);
416 416 static mptsas_smp_t *mptsas_smp_alloc(mptsas_t *, mptsas_smp_t *);
417 417 static int mptsas_online_smp(dev_info_t *pdip, mptsas_smp_t *smp_node,
418 418 dev_info_t **smp_dip);
419 419
420 420 /*
421 421 * Power management functions
422 422 */
423 423 static int mptsas_get_pci_cap(mptsas_t *mpt);
424 424 static int mptsas_init_pm(mptsas_t *mpt);
425 425
426 426 /*
427 427 * MPT MSI tunable:
428 428 *
429 429 * By default MSI is enabled on all supported platforms.
430 430 */
431 431 boolean_t mptsas_enable_msi = B_TRUE;
432 432 boolean_t mptsas_physical_bind_failed_page_83 = B_FALSE;
433 433
434 434 /*
435 435 * Global switch for use of MPI2.5 FAST PATH.
436 436 * We don't really know what FAST PATH actually does, so if it is suspected
437 437 * to cause problems it can be turned off by setting this variable to B_FALSE.
438 438 */
439 439 boolean_t mptsas_use_fastpath = B_TRUE;
440 440
441 441 static int mptsas_register_intrs(mptsas_t *);
442 442 static void mptsas_unregister_intrs(mptsas_t *);
443 443 static int mptsas_add_intrs(mptsas_t *, int);
444 444 static void mptsas_rem_intrs(mptsas_t *);
445 445
446 446 /*
447 447 * FMA Prototypes
448 448 */
449 449 static void mptsas_fm_init(mptsas_t *mpt);
450 450 static void mptsas_fm_fini(mptsas_t *mpt);
451 451 static int mptsas_fm_error_cb(dev_info_t *, ddi_fm_error_t *, const void *);
452 452
453 453 extern pri_t minclsyspri, maxclsyspri;
454 454
455 455 /*
456 456 * This device is created by the SCSI pseudo nexus driver (SCSI vHCI). It is
457 457 * under this device that the paths to a physical device are created when
458 458 * MPxIO is used.
459 459 */
460 460 extern dev_info_t *scsi_vhci_dip;
461 461
462 462 /*
463 463 * Tunable timeout value for Inquiry VPD page 0x83
464 464 * By default the value is 30 seconds.
465 465 */
466 466 int mptsas_inq83_retry_timeout = 30;
467 467
468 468 /*
469 469 * This is used to allocate memory for message frame storage, not for
470 470 * data I/O DMA. All message frames must be stored in the first 4G of
471 471 * physical memory.
472 472 */
473 473 ddi_dma_attr_t mptsas_dma_attrs = {
474 474 DMA_ATTR_V0, /* attribute layout version */
475 475 0x0ull, /* address low - should be 0 (longlong) */
476 476 0xffffffffull, /* address high - 32-bit max range */
477 477 0x00ffffffull, /* count max - max DMA object size */
478 478 4, /* allocation alignment requirements */
479 479 0x78, /* burstsizes - binary encoded values */
480 480 1, /* minxfer - gran. of DMA engine */
481 481 0x00ffffffull, /* maxxfer - gran. of DMA engine */
482 482 0xffffffffull, /* max segment size (DMA boundary) */
483 483 MPTSAS_MAX_DMA_SEGS, /* scatter/gather list length */
484 484 512, /* granularity - device transfer size */
485 485 0 /* flags, set to 0 */
486 486 };
487 487
488 488 /*
489 489 * This is used for data I/O DMA memory allocation. (full 64-bit DMA
490 490 * physical addresses are supported.)
491 491 */
492 492 ddi_dma_attr_t mptsas_dma_attrs64 = {
493 493 DMA_ATTR_V0, /* attribute layout version */
494 494 0x0ull, /* address low - should be 0 (longlong) */
495 495 0xffffffffffffffffull, /* address high - 64-bit max */
496 496 0x00ffffffull, /* count max - max DMA object size */
497 497 4, /* allocation alignment requirements */
498 498 0x78, /* burstsizes - binary encoded values */
499 499 1, /* minxfer - gran. of DMA engine */
500 500 0x00ffffffull, /* maxxfer - gran. of DMA engine */
501 501 0xffffffffull, /* max segment size (DMA boundary) */
502 502 MPTSAS_MAX_DMA_SEGS, /* scatter/gather list length */
503 503 512, /* granularity - device transfer size */
504 504 0 /* flags, set to 0 */
505 505 };
506 506
507 507 ddi_device_acc_attr_t mptsas_dev_attr = {
508 508 DDI_DEVICE_ATTR_V1,
509 509 DDI_STRUCTURE_LE_ACC,
510 510 DDI_STRICTORDER_ACC,
511 511 DDI_DEFAULT_ACC
512 512 };
513 513
514 514 static struct cb_ops mptsas_cb_ops = {
515 515 scsi_hba_open, /* open */
516 516 scsi_hba_close, /* close */
517 517 nodev, /* strategy */
518 518 nodev, /* print */
519 519 nodev, /* dump */
520 520 nodev, /* read */
521 521 nodev, /* write */
522 522 mptsas_ioctl, /* ioctl */
523 523 nodev, /* devmap */
524 524 nodev, /* mmap */
525 525 nodev, /* segmap */
526 526 nochpoll, /* chpoll */
527 527 ddi_prop_op, /* cb_prop_op */
528 528 NULL, /* streamtab */
529 529 D_MP, /* cb_flag */
530 530 CB_REV, /* rev */
531 531 nodev, /* aread */
532 532 nodev /* awrite */
533 533 };
534 534
535 535 static struct dev_ops mptsas_ops = {
536 536 DEVO_REV, /* devo_rev, */
537 537 0, /* refcnt */
538 538 ddi_no_info, /* info */
539 539 nulldev, /* identify */
540 540 nulldev, /* probe */
541 541 mptsas_attach, /* attach */
542 542 mptsas_detach, /* detach */
543 543 #ifdef __sparc
544 544 mptsas_reset,
545 545 #else
546 546 nodev, /* reset */
547 547 #endif /* __sparc */
548 548 &mptsas_cb_ops, /* driver operations */
↓ open down ↓ |
548 lines elided |
↑ open up ↑ |
549 549 NULL, /* bus operations */
550 550 mptsas_power, /* power management */
551 551 #ifdef __sparc
552 552 ddi_quiesce_not_needed
553 553 #else
554 554 mptsas_quiesce /* quiesce */
555 555 #endif /* __sparc */
556 556 };
557 557
558 558
559 -#define MPTSAS_MOD_STRING "MPTSAS HBA Driver 00.00.00.24"
559 +#define MPTSAS_MOD_STRING "MPTSAS HBA Driver 00.00.00.24X"
560 560
561 561 static struct modldrv modldrv = {
562 562 &mod_driverops, /* Type of module. This one is a driver */
563 563 MPTSAS_MOD_STRING, /* Name of the module. */
564 564 &mptsas_ops, /* driver ops */
565 565 };
566 566
567 567 static struct modlinkage modlinkage = {
568 568 MODREV_1, &modldrv, NULL
569 569 };
570 570 #define TARGET_PROP "target"
571 571 #define LUN_PROP "lun"
572 572 #define LUN64_PROP "lun64"
573 573 #define SAS_PROP "sas-mpt"
574 574 #define MDI_GUID "wwn"
575 575 #define NDI_GUID "guid"
576 576 #define MPTSAS_DEV_GONE "mptsas_dev_gone"
577 577
578 578 /*
579 579 * Local static data
580 580 */
581 581 #if defined(MPTSAS_DEBUG)
582 582 /*
583 583 * Flags to indicate which debug messages are to be printed and which go to the
584 584 * debug log ring buffer. Default is to not print anything, and to log
585 585 * everything except the watchsubr() output which normally happens every second.
586 586 */
587 587 uint32_t mptsas_debugprt_flags = 0x0;
588 588 uint32_t mptsas_debuglog_flags = ~(1U << 30);
589 589 #endif /* defined(MPTSAS_DEBUG) */
590 590 uint32_t mptsas_debug_resets = 0;
591 591
592 592 static kmutex_t mptsas_global_mutex;
593 593 static void *mptsas_state; /* soft state ptr */
594 594 static krwlock_t mptsas_global_rwlock;
595 595
596 596 static kmutex_t mptsas_log_mutex;
597 597 static char mptsas_log_buf[256];
598 598 _NOTE(MUTEX_PROTECTS_DATA(mptsas_log_mutex, mptsas_log_buf))
599 599
600 600 static mptsas_t *mptsas_head, *mptsas_tail;
601 601 static clock_t mptsas_scsi_watchdog_tick;
602 602 static clock_t mptsas_tick;
603 603 static timeout_id_t mptsas_reset_watch;
604 604 static timeout_id_t mptsas_timeout_id;
605 605 static int mptsas_timeouts_enabled = 0;
606 606
607 607 /*
608 608 * Default length for extended auto request sense buffers.
609 609 * All sense buffers need to be under the same alloc because there
610 610 * is only one common top 32bits (of 64bits) address register.
611 611 * Most requests only require 32 bytes, but some request >256.
612 612 * We use rmalloc()/rmfree() on this additional memory to manage the
613 613 * "extended" requests.
614 614 */
615 615 int mptsas_extreq_sense_bufsize = 256*64;
616 616
617 617 /*
618 618 * We believe that all software resrictions of having to run with DMA
619 619 * attributes to limit allocation to the first 4G are removed.
620 620 * However, this flag remains to enable quick switchback should suspicious
621 621 * problems emerge.
622 622 * Note that scsi_alloc_consistent_buf() does still adhere to allocating
623 623 * 32 bit addressable memory, but we can cope if that is changed now.
624 624 */
625 625 int mptsas_use_64bit_msgaddr = 1;
626 626
627 627 /*
628 628 * warlock directives
629 629 */
630 630 _NOTE(SCHEME_PROTECTS_DATA("unique per pkt", scsi_pkt \
631 631 mptsas_cmd NcrTableIndirect buf scsi_cdb scsi_status))
632 632 _NOTE(SCHEME_PROTECTS_DATA("unique per pkt", smp_pkt))
633 633 _NOTE(SCHEME_PROTECTS_DATA("stable data", scsi_device scsi_address))
634 634 _NOTE(SCHEME_PROTECTS_DATA("No Mutex Needed", mptsas_tgt_private))
635 635 _NOTE(SCHEME_PROTECTS_DATA("No Mutex Needed", scsi_hba_tran::tran_tgt_private))
636 636
637 637 /*
638 638 * SM - HBA statics
639 639 */
640 640 char *mptsas_driver_rev = MPTSAS_MOD_STRING;
641 641
642 642 #ifdef MPTSAS_DEBUG
643 643 void debug_enter(char *);
644 644 #endif
645 645
646 646 /*
647 647 * Notes:
648 648 * - scsi_hba_init(9F) initializes SCSI HBA modules
649 649 * - must call scsi_hba_fini(9F) if modload() fails
650 650 */
651 651 int
652 652 _init(void)
653 653 {
654 654 int status;
655 655 /* CONSTCOND */
656 656 ASSERT(NO_COMPETING_THREADS);
657 657
658 658 NDBG0(("_init"));
659 659
660 660 status = ddi_soft_state_init(&mptsas_state, MPTSAS_SIZE,
661 661 MPTSAS_INITIAL_SOFT_SPACE);
662 662 if (status != 0) {
663 663 return (status);
664 664 }
665 665
666 666 if ((status = scsi_hba_init(&modlinkage)) != 0) {
667 667 ddi_soft_state_fini(&mptsas_state);
668 668 return (status);
669 669 }
670 670
671 671 mutex_init(&mptsas_global_mutex, NULL, MUTEX_DRIVER, NULL);
672 672 rw_init(&mptsas_global_rwlock, NULL, RW_DRIVER, NULL);
673 673 mutex_init(&mptsas_log_mutex, NULL, MUTEX_DRIVER, NULL);
674 674
675 675 if ((status = mod_install(&modlinkage)) != 0) {
676 676 mutex_destroy(&mptsas_log_mutex);
677 677 rw_destroy(&mptsas_global_rwlock);
678 678 mutex_destroy(&mptsas_global_mutex);
679 679 ddi_soft_state_fini(&mptsas_state);
680 680 scsi_hba_fini(&modlinkage);
681 681 }
682 682
683 683 return (status);
684 684 }
685 685
686 686 /*
687 687 * Notes:
688 688 * - scsi_hba_fini(9F) uninitializes SCSI HBA modules
689 689 */
690 690 int
691 691 _fini(void)
692 692 {
693 693 int status;
694 694 /* CONSTCOND */
695 695 ASSERT(NO_COMPETING_THREADS);
696 696
697 697 NDBG0(("_fini"));
698 698
699 699 if ((status = mod_remove(&modlinkage)) == 0) {
700 700 ddi_soft_state_fini(&mptsas_state);
701 701 scsi_hba_fini(&modlinkage);
702 702 mutex_destroy(&mptsas_global_mutex);
703 703 rw_destroy(&mptsas_global_rwlock);
704 704 mutex_destroy(&mptsas_log_mutex);
705 705 }
706 706 return (status);
707 707 }
708 708
709 709 /*
710 710 * The loadable-module _info(9E) entry point
711 711 */
712 712 int
713 713 _info(struct modinfo *modinfop)
714 714 {
715 715 /* CONSTCOND */
716 716 ASSERT(NO_COMPETING_THREADS);
717 717 NDBG0(("mptsas _info"));
718 718
719 719 return (mod_info(&modlinkage, modinfop));
720 720 }
721 721
722 722 static int
723 723 mptsas_target_eval_devhdl(const void *op, void *arg)
724 724 {
725 725 uint16_t dh = *(uint16_t *)arg;
726 726 const mptsas_target_t *tp = op;
727 727
728 728 return ((int)tp->m_devhdl - (int)dh);
729 729 }
730 730
731 731 static int
732 732 mptsas_target_eval_slot(const void *op, void *arg)
733 733 {
734 734 mptsas_led_control_t *lcp = arg;
735 735 const mptsas_target_t *tp = op;
736 736
737 737 if (tp->m_enclosure != lcp->Enclosure)
738 738 return ((int)tp->m_enclosure - (int)lcp->Enclosure);
739 739
740 740 return ((int)tp->m_slot_num - (int)lcp->Slot);
741 741 }
742 742
743 743 static int
744 744 mptsas_target_eval_nowwn(const void *op, void *arg)
745 745 {
746 746 uint8_t phy = *(uint8_t *)arg;
747 747 const mptsas_target_t *tp = op;
748 748
749 749 if (tp->m_addr.mta_wwn != 0)
750 750 return (-1);
751 751
752 752 return ((int)tp->m_phynum - (int)phy);
753 753 }
754 754
755 755 static int
756 756 mptsas_smp_eval_devhdl(const void *op, void *arg)
757 757 {
758 758 uint16_t dh = *(uint16_t *)arg;
759 759 const mptsas_smp_t *sp = op;
760 760
761 761 return ((int)sp->m_devhdl - (int)dh);
762 762 }
763 763
764 764 static uint64_t
765 765 mptsas_target_addr_hash(const void *tp)
766 766 {
767 767 const mptsas_target_addr_t *tap = tp;
768 768
769 769 return ((tap->mta_wwn & 0xffffffffffffULL) |
770 770 ((uint64_t)tap->mta_phymask << 48));
771 771 }
772 772
773 773 static int
774 774 mptsas_target_addr_cmp(const void *a, const void *b)
775 775 {
776 776 const mptsas_target_addr_t *aap = a;
777 777 const mptsas_target_addr_t *bap = b;
778 778
779 779 if (aap->mta_wwn < bap->mta_wwn)
780 780 return (-1);
781 781 if (aap->mta_wwn > bap->mta_wwn)
782 782 return (1);
783 783 return ((int)bap->mta_phymask - (int)aap->mta_phymask);
784 784 }
785 785
786 786 static uint64_t
787 787 mptsas_tmp_target_hash(const void *tp)
788 788 {
789 789 return ((uint64_t)(uintptr_t)tp);
790 790 }
791 791
792 792 static int
793 793 mptsas_tmp_target_cmp(const void *a, const void *b)
794 794 {
795 795 if (a > b)
796 796 return (1);
797 797 if (b < a)
798 798 return (-1);
799 799
800 800 return (0);
801 801 }
802 802
803 803 static void
804 804 mptsas_target_free(void *op)
805 805 {
806 806 kmem_free(op, sizeof (mptsas_target_t));
807 807 }
808 808
809 809 static void
810 810 mptsas_smp_free(void *op)
811 811 {
812 812 kmem_free(op, sizeof (mptsas_smp_t));
813 813 }
814 814
815 815 static void
816 816 mptsas_destroy_hashes(mptsas_t *mpt)
817 817 {
818 818 mptsas_target_t *tp;
819 819 mptsas_smp_t *sp;
820 820
821 821 for (tp = refhash_first(mpt->m_targets); tp != NULL;
822 822 tp = refhash_next(mpt->m_targets, tp)) {
823 823 refhash_remove(mpt->m_targets, tp);
824 824 }
825 825 for (sp = refhash_first(mpt->m_smp_targets); sp != NULL;
826 826 sp = refhash_next(mpt->m_smp_targets, sp)) {
827 827 refhash_remove(mpt->m_smp_targets, sp);
828 828 }
829 829 refhash_destroy(mpt->m_tmp_targets);
830 830 refhash_destroy(mpt->m_targets);
831 831 refhash_destroy(mpt->m_smp_targets);
832 832 mpt->m_targets = NULL;
833 833 mpt->m_smp_targets = NULL;
834 834 }
835 835
836 836 static int
837 837 mptsas_iport_attach(dev_info_t *dip, ddi_attach_cmd_t cmd)
838 838 {
839 839 dev_info_t *pdip;
840 840 mptsas_t *mpt;
841 841 scsi_hba_tran_t *hba_tran;
842 842 char *iport = NULL;
843 843 char phymask[MPTSAS_MAX_PHYS];
844 844 mptsas_phymask_t phy_mask = 0;
845 845 int dynamic_port = 0;
846 846 uint32_t page_address;
847 847 char initiator_wwnstr[MPTSAS_WWN_STRLEN];
848 848 int rval = DDI_FAILURE;
849 849 int i = 0;
850 850 uint8_t numphys = 0;
851 851 uint8_t phy_id;
852 852 uint8_t phy_port = 0;
853 853 uint16_t attached_devhdl = 0;
854 854 uint32_t dev_info;
855 855 uint64_t attached_sas_wwn;
856 856 uint16_t dev_hdl;
857 857 uint16_t pdev_hdl;
858 858 uint16_t bay_num, enclosure, io_flags;
859 859 char attached_wwnstr[MPTSAS_WWN_STRLEN];
860 860
861 861 /* CONSTCOND */
862 862 ASSERT(NO_COMPETING_THREADS);
863 863
864 864 switch (cmd) {
865 865 case DDI_ATTACH:
866 866 break;
867 867
868 868 case DDI_RESUME:
869 869 /*
870 870 * If this a scsi-iport node, nothing to do here.
871 871 */
872 872 return (DDI_SUCCESS);
873 873
874 874 default:
875 875 return (DDI_FAILURE);
876 876 }
877 877
878 878 pdip = ddi_get_parent(dip);
879 879
880 880 if ((hba_tran = ndi_flavorv_get(pdip, SCSA_FLAVOR_SCSI_DEVICE)) ==
881 881 NULL) {
882 882 cmn_err(CE_WARN, "Failed attach iport because fail to "
883 883 "get tran vector for the HBA node");
884 884 return (DDI_FAILURE);
885 885 }
886 886
887 887 mpt = TRAN2MPT(hba_tran);
888 888 ASSERT(mpt != NULL);
889 889 if (mpt == NULL)
890 890 return (DDI_FAILURE);
891 891
892 892 if ((hba_tran = ndi_flavorv_get(dip, SCSA_FLAVOR_SCSI_DEVICE)) ==
893 893 NULL) {
894 894 mptsas_log(mpt, CE_WARN, "Failed attach iport because fail to "
895 895 "get tran vector for the iport node");
896 896 return (DDI_FAILURE);
897 897 }
898 898
899 899 /*
900 900 * Overwrite parent's tran_hba_private to iport's tran vector
901 901 */
902 902 hba_tran->tran_hba_private = mpt;
903 903
904 904 ddi_report_dev(dip);
905 905
906 906 /*
907 907 * Get SAS address for initiator port according dev_handle
908 908 */
909 909 iport = ddi_get_name_addr(dip);
910 910 if (iport && strncmp(iport, "v0", 2) == 0) {
911 911 if (ddi_prop_update_int(DDI_DEV_T_NONE, dip,
912 912 MPTSAS_VIRTUAL_PORT, 1) !=
913 913 DDI_PROP_SUCCESS) {
914 914 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip,
915 915 MPTSAS_VIRTUAL_PORT);
916 916 mptsas_log(mpt, CE_WARN, "mptsas virtual port "
917 917 "prop update failed");
918 918 return (DDI_FAILURE);
919 919 }
920 920 return (DDI_SUCCESS);
921 921 }
922 922
923 923 mutex_enter(&mpt->m_mutex);
924 924 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
925 925 bzero(phymask, sizeof (phymask));
926 926 (void) sprintf(phymask,
927 927 "%x", mpt->m_phy_info[i].phy_mask);
928 928 if (strcmp(phymask, iport) == 0) {
929 929 break;
930 930 }
931 931 }
932 932
933 933 if (i == MPTSAS_MAX_PHYS) {
934 934 mptsas_log(mpt, CE_WARN, "Failed attach port %s because port"
935 935 "seems not exist", iport);
936 936 mutex_exit(&mpt->m_mutex);
937 937 return (DDI_FAILURE);
938 938 }
939 939
940 940 phy_mask = mpt->m_phy_info[i].phy_mask;
941 941
942 942 if (mpt->m_phy_info[i].port_flags & AUTO_PORT_CONFIGURATION)
943 943 dynamic_port = 1;
944 944 else
945 945 dynamic_port = 0;
946 946
947 947 /*
948 948 * Update PHY info for smhba
949 949 */
950 950 if (mptsas_smhba_phy_init(mpt)) {
951 951 mutex_exit(&mpt->m_mutex);
952 952 mptsas_log(mpt, CE_WARN, "mptsas phy update "
953 953 "failed");
954 954 return (DDI_FAILURE);
955 955 }
956 956
957 957 mutex_exit(&mpt->m_mutex);
958 958
959 959 numphys = 0;
960 960 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
961 961 if ((phy_mask >> i) & 0x01) {
962 962 numphys++;
963 963 }
964 964 }
965 965
966 966 bzero(initiator_wwnstr, sizeof (initiator_wwnstr));
967 967 (void) sprintf(initiator_wwnstr, "w%016"PRIx64,
968 968 mpt->un.m_base_wwid);
969 969
970 970 if (ddi_prop_update_string(DDI_DEV_T_NONE, dip,
971 971 SCSI_ADDR_PROP_INITIATOR_PORT, initiator_wwnstr) !=
972 972 DDI_PROP_SUCCESS) {
973 973 (void) ddi_prop_remove(DDI_DEV_T_NONE,
974 974 dip, SCSI_ADDR_PROP_INITIATOR_PORT);
975 975 mptsas_log(mpt, CE_WARN, "mptsas Initiator port "
976 976 "prop update failed");
977 977 return (DDI_FAILURE);
978 978 }
979 979 if (ddi_prop_update_int(DDI_DEV_T_NONE, dip,
980 980 MPTSAS_NUM_PHYS, numphys) !=
981 981 DDI_PROP_SUCCESS) {
982 982 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, MPTSAS_NUM_PHYS);
983 983 return (DDI_FAILURE);
984 984 }
985 985
986 986 if (ddi_prop_update_int(DDI_DEV_T_NONE, dip,
987 987 "phymask", phy_mask) !=
988 988 DDI_PROP_SUCCESS) {
989 989 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "phymask");
990 990 mptsas_log(mpt, CE_WARN, "mptsas phy mask "
991 991 "prop update failed");
992 992 return (DDI_FAILURE);
993 993 }
994 994
995 995 if (ddi_prop_update_int(DDI_DEV_T_NONE, dip,
996 996 "dynamic-port", dynamic_port) !=
997 997 DDI_PROP_SUCCESS) {
998 998 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "dynamic-port");
999 999 mptsas_log(mpt, CE_WARN, "mptsas dynamic port "
1000 1000 "prop update failed");
1001 1001 return (DDI_FAILURE);
1002 1002 }
1003 1003 if (ddi_prop_update_int(DDI_DEV_T_NONE, dip,
1004 1004 MPTSAS_VIRTUAL_PORT, 0) !=
1005 1005 DDI_PROP_SUCCESS) {
1006 1006 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip,
1007 1007 MPTSAS_VIRTUAL_PORT);
1008 1008 mptsas_log(mpt, CE_WARN, "mptsas virtual port "
1009 1009 "prop update failed");
1010 1010 return (DDI_FAILURE);
1011 1011 }
1012 1012 mptsas_smhba_set_all_phy_props(mpt, dip, numphys, phy_mask,
1013 1013 &attached_devhdl);
1014 1014
1015 1015 mutex_enter(&mpt->m_mutex);
1016 1016 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE &
1017 1017 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | (uint32_t)attached_devhdl;
1018 1018 rval = mptsas_get_sas_device_page0(mpt, page_address, &dev_hdl,
1019 1019 &attached_sas_wwn, &dev_info, &phy_port, &phy_id,
1020 1020 &pdev_hdl, &bay_num, &enclosure, &io_flags);
1021 1021 if (rval != DDI_SUCCESS) {
1022 1022 mptsas_log(mpt, CE_WARN,
1023 1023 "Failed to get device page0 for handle:%d",
1024 1024 attached_devhdl);
1025 1025 mutex_exit(&mpt->m_mutex);
1026 1026 return (DDI_FAILURE);
1027 1027 }
1028 1028
1029 1029 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
1030 1030 bzero(phymask, sizeof (phymask));
1031 1031 (void) sprintf(phymask, "%x", mpt->m_phy_info[i].phy_mask);
1032 1032 if (strcmp(phymask, iport) == 0) {
1033 1033 (void) sprintf(&mpt->m_phy_info[i].smhba_info.path[0],
1034 1034 "%x",
1035 1035 mpt->m_phy_info[i].phy_mask);
1036 1036 }
1037 1037 }
1038 1038 mutex_exit(&mpt->m_mutex);
1039 1039
1040 1040 bzero(attached_wwnstr, sizeof (attached_wwnstr));
1041 1041 (void) sprintf(attached_wwnstr, "w%016"PRIx64,
1042 1042 attached_sas_wwn);
1043 1043 if (ddi_prop_update_string(DDI_DEV_T_NONE, dip,
1044 1044 SCSI_ADDR_PROP_ATTACHED_PORT, attached_wwnstr) !=
1045 1045 DDI_PROP_SUCCESS) {
1046 1046 (void) ddi_prop_remove(DDI_DEV_T_NONE,
1047 1047 dip, SCSI_ADDR_PROP_ATTACHED_PORT);
1048 1048 return (DDI_FAILURE);
1049 1049 }
1050 1050
1051 1051 /* Create kstats for each phy on this iport */
1052 1052
1053 1053 mptsas_create_phy_stats(mpt, iport, dip);
1054 1054
1055 1055 /*
1056 1056 * register sas hba iport with mdi (MPxIO/vhci)
1057 1057 */
1058 1058 if (mdi_phci_register(MDI_HCI_CLASS_SCSI,
1059 1059 dip, 0) == MDI_SUCCESS) {
1060 1060 mpt->m_mpxio_enable = TRUE;
1061 1061 }
1062 1062 return (DDI_SUCCESS);
1063 1063 }
1064 1064
1065 1065 /*
1066 1066 * Notes:
1067 1067 * Set up all device state and allocate data structures,
1068 1068 * mutexes, condition variables, etc. for device operation.
1069 1069 * Add interrupts needed.
1070 1070 * Return DDI_SUCCESS if device is ready, else return DDI_FAILURE.
1071 1071 */
1072 1072 static int
1073 1073 mptsas_attach(dev_info_t *dip, ddi_attach_cmd_t cmd)
1074 1074 {
1075 1075 mptsas_t *mpt = NULL;
1076 1076 int instance, i, j;
1077 1077 int doneq_thread_num;
1078 1078 char intr_added = 0;
1079 1079 char map_setup = 0;
1080 1080 char config_setup = 0;
1081 1081 char hba_attach_setup = 0;
1082 1082 char smp_attach_setup = 0;
1083 1083 char mutex_init_done = 0;
1084 1084 char event_taskq_create = 0;
1085 1085 char dr_taskq_create = 0;
1086 1086 char doneq_thread_create = 0;
1087 1087 char added_watchdog = 0;
1088 1088 scsi_hba_tran_t *hba_tran;
1089 1089 uint_t mem_bar = MEM_SPACE;
1090 1090 int rval = DDI_FAILURE;
1091 1091
1092 1092 /* CONSTCOND */
1093 1093 ASSERT(NO_COMPETING_THREADS);
1094 1094
1095 1095 if (scsi_hba_iport_unit_address(dip)) {
1096 1096 return (mptsas_iport_attach(dip, cmd));
1097 1097 }
1098 1098
1099 1099 switch (cmd) {
1100 1100 case DDI_ATTACH:
1101 1101 break;
1102 1102
1103 1103 case DDI_RESUME:
1104 1104 if ((hba_tran = ddi_get_driver_private(dip)) == NULL)
1105 1105 return (DDI_FAILURE);
1106 1106
1107 1107 mpt = TRAN2MPT(hba_tran);
1108 1108
1109 1109 if (!mpt) {
1110 1110 return (DDI_FAILURE);
1111 1111 }
1112 1112
1113 1113 /*
1114 1114 * Reset hardware and softc to "no outstanding commands"
1115 1115 * Note that a check condition can result on first command
1116 1116 * to a target.
1117 1117 */
1118 1118 mutex_enter(&mpt->m_mutex);
1119 1119
1120 1120 /*
1121 1121 * raise power.
1122 1122 */
1123 1123 if (mpt->m_options & MPTSAS_OPT_PM) {
1124 1124 mutex_exit(&mpt->m_mutex);
1125 1125 (void) pm_busy_component(dip, 0);
1126 1126 rval = pm_power_has_changed(dip, 0, PM_LEVEL_D0);
1127 1127 if (rval == DDI_SUCCESS) {
1128 1128 mutex_enter(&mpt->m_mutex);
1129 1129 } else {
1130 1130 /*
1131 1131 * The pm_raise_power() call above failed,
1132 1132 * and that can only occur if we were unable
1133 1133 * to reset the hardware. This is probably
1134 1134 * due to unhealty hardware, and because
1135 1135 * important filesystems(such as the root
1136 1136 * filesystem) could be on the attached disks,
1137 1137 * it would not be a good idea to continue,
1138 1138 * as we won't be entirely certain we are
1139 1139 * writing correct data. So we panic() here
1140 1140 * to not only prevent possible data corruption,
1141 1141 * but to give developers or end users a hope
1142 1142 * of identifying and correcting any problems.
1143 1143 */
1144 1144 fm_panic("mptsas could not reset hardware "
1145 1145 "during resume");
1146 1146 }
1147 1147 }
1148 1148
1149 1149 mpt->m_suspended = 0;
1150 1150
1151 1151 /*
1152 1152 * Reinitialize ioc
1153 1153 */
1154 1154 mpt->m_softstate |= MPTSAS_SS_MSG_UNIT_RESET;
1155 1155 if (mptsas_init_chip(mpt, FALSE) == DDI_FAILURE) {
1156 1156 mutex_exit(&mpt->m_mutex);
1157 1157 if (mpt->m_options & MPTSAS_OPT_PM) {
1158 1158 (void) pm_idle_component(dip, 0);
1159 1159 }
1160 1160 fm_panic("mptsas init chip fail during resume");
1161 1161 }
1162 1162 /*
1163 1163 * mptsas_update_driver_data needs interrupts so enable them
1164 1164 * first.
1165 1165 */
1166 1166 MPTSAS_ENABLE_INTR(mpt);
1167 1167 mptsas_update_driver_data(mpt);
1168 1168
1169 1169 /* start requests, if possible */
1170 1170 mptsas_restart_hba(mpt);
1171 1171
1172 1172 mutex_exit(&mpt->m_mutex);
1173 1173
1174 1174 /*
1175 1175 * Restart watch thread
1176 1176 */
1177 1177 mutex_enter(&mptsas_global_mutex);
1178 1178 if (mptsas_timeout_id == 0) {
1179 1179 mptsas_timeout_id = timeout(mptsas_watch, NULL,
1180 1180 mptsas_tick);
1181 1181 mptsas_timeouts_enabled = 1;
1182 1182 }
1183 1183 mutex_exit(&mptsas_global_mutex);
1184 1184
1185 1185 /* report idle status to pm framework */
1186 1186 if (mpt->m_options & MPTSAS_OPT_PM) {
1187 1187 (void) pm_idle_component(dip, 0);
1188 1188 }
1189 1189
1190 1190 return (DDI_SUCCESS);
1191 1191
1192 1192 default:
1193 1193 return (DDI_FAILURE);
1194 1194
1195 1195 }
1196 1196
1197 1197 instance = ddi_get_instance(dip);
1198 1198
1199 1199 /*
1200 1200 * Allocate softc information.
1201 1201 */
1202 1202 if (ddi_soft_state_zalloc(mptsas_state, instance) != DDI_SUCCESS) {
1203 1203 mptsas_log(NULL, CE_WARN,
1204 1204 "mptsas%d: cannot allocate soft state", instance);
1205 1205 goto fail;
1206 1206 }
1207 1207
1208 1208 mpt = ddi_get_soft_state(mptsas_state, instance);
1209 1209
1210 1210 if (mpt == NULL) {
1211 1211 mptsas_log(NULL, CE_WARN,
1212 1212 "mptsas%d: cannot get soft state", instance);
1213 1213 goto fail;
1214 1214 }
1215 1215
1216 1216 /* Indicate that we are 'sizeof (scsi_*(9S))' clean. */
1217 1217 scsi_size_clean(dip);
1218 1218
1219 1219 mpt->m_dip = dip;
1220 1220 mpt->m_instance = instance;
1221 1221
1222 1222 /* Make a per-instance copy of the structures */
1223 1223 mpt->m_io_dma_attr = mptsas_dma_attrs64;
1224 1224 if (mptsas_use_64bit_msgaddr) {
1225 1225 mpt->m_msg_dma_attr = mptsas_dma_attrs64;
1226 1226 } else {
1227 1227 mpt->m_msg_dma_attr = mptsas_dma_attrs;
1228 1228 }
1229 1229 mpt->m_reg_acc_attr = mptsas_dev_attr;
1230 1230 mpt->m_dev_acc_attr = mptsas_dev_attr;
1231 1231
1232 1232 /*
1233 1233 * Size of individual request sense buffer
1234 1234 */
1235 1235 mpt->m_req_sense_size = EXTCMDS_STATUS_SIZE;
1236 1236
1237 1237 /*
1238 1238 * Initialize FMA
1239 1239 */
1240 1240 mpt->m_fm_capabilities = ddi_getprop(DDI_DEV_T_ANY, mpt->m_dip,
1241 1241 DDI_PROP_CANSLEEP | DDI_PROP_DONTPASS, "fm-capable",
1242 1242 DDI_FM_EREPORT_CAPABLE | DDI_FM_ACCCHK_CAPABLE |
1243 1243 DDI_FM_DMACHK_CAPABLE | DDI_FM_ERRCB_CAPABLE);
1244 1244
1245 1245 mptsas_fm_init(mpt);
1246 1246
1247 1247 if (mptsas_alloc_handshake_msg(mpt,
1248 1248 sizeof (Mpi2SCSITaskManagementRequest_t)) == DDI_FAILURE) {
1249 1249 mptsas_log(mpt, CE_WARN, "cannot initialize handshake msg.");
1250 1250 goto fail;
1251 1251 }
1252 1252
1253 1253 /*
1254 1254 * Setup configuration space
1255 1255 */
1256 1256 if (mptsas_config_space_init(mpt) == FALSE) {
1257 1257 mptsas_log(mpt, CE_WARN, "mptsas_config_space_init failed");
1258 1258 goto fail;
1259 1259 }
1260 1260 config_setup++;
1261 1261
1262 1262 if (ddi_regs_map_setup(dip, mem_bar, (caddr_t *)&mpt->m_reg,
1263 1263 0, 0, &mpt->m_reg_acc_attr, &mpt->m_datap) != DDI_SUCCESS) {
1264 1264 mptsas_log(mpt, CE_WARN, "map setup failed");
1265 1265 goto fail;
1266 1266 }
1267 1267 map_setup++;
1268 1268
1269 1269 /*
1270 1270 * A taskq is created for dealing with the event handler
1271 1271 */
1272 1272 if ((mpt->m_event_taskq = ddi_taskq_create(dip, "mptsas_event_taskq",
1273 1273 1, TASKQ_DEFAULTPRI, 0)) == NULL) {
1274 1274 mptsas_log(mpt, CE_NOTE, "ddi_taskq_create failed");
1275 1275 goto fail;
1276 1276 }
1277 1277 event_taskq_create++;
1278 1278
1279 1279 /*
1280 1280 * A taskq is created for dealing with dr events
1281 1281 */
1282 1282 if ((mpt->m_dr_taskq = ddi_taskq_create(dip,
1283 1283 "mptsas_dr_taskq",
1284 1284 1, TASKQ_DEFAULTPRI, 0)) == NULL) {
1285 1285 mptsas_log(mpt, CE_NOTE, "ddi_taskq_create for discovery "
1286 1286 "failed");
1287 1287 goto fail;
1288 1288 }
1289 1289 dr_taskq_create++;
1290 1290
1291 1291 mpt->m_doneq_thread_threshold = ddi_prop_get_int(DDI_DEV_T_ANY, dip,
1292 1292 0, "mptsas_doneq_thread_threshold_prop", 10);
1293 1293 mpt->m_doneq_length_threshold = ddi_prop_get_int(DDI_DEV_T_ANY, dip,
1294 1294 0, "mptsas_doneq_length_threshold_prop", 8);
1295 1295 mpt->m_doneq_thread_n = ddi_prop_get_int(DDI_DEV_T_ANY, dip,
1296 1296 0, "mptsas_doneq_thread_n_prop", 8);
1297 1297
1298 1298 if (mpt->m_doneq_thread_n) {
1299 1299 cv_init(&mpt->m_doneq_thread_cv, NULL, CV_DRIVER, NULL);
1300 1300 mutex_init(&mpt->m_doneq_mutex, NULL, MUTEX_DRIVER, NULL);
1301 1301
1302 1302 mutex_enter(&mpt->m_doneq_mutex);
1303 1303 mpt->m_doneq_thread_id =
1304 1304 kmem_zalloc(sizeof (mptsas_doneq_thread_list_t)
1305 1305 * mpt->m_doneq_thread_n, KM_SLEEP);
1306 1306
1307 1307 for (j = 0; j < mpt->m_doneq_thread_n; j++) {
1308 1308 cv_init(&mpt->m_doneq_thread_id[j].cv, NULL,
1309 1309 CV_DRIVER, NULL);
1310 1310 mutex_init(&mpt->m_doneq_thread_id[j].mutex, NULL,
1311 1311 MUTEX_DRIVER, NULL);
1312 1312 mutex_enter(&mpt->m_doneq_thread_id[j].mutex);
1313 1313 mpt->m_doneq_thread_id[j].flag |=
1314 1314 MPTSAS_DONEQ_THREAD_ACTIVE;
1315 1315 mpt->m_doneq_thread_id[j].arg.mpt = mpt;
1316 1316 mpt->m_doneq_thread_id[j].arg.t = j;
1317 1317 mpt->m_doneq_thread_id[j].threadp =
1318 1318 thread_create(NULL, 0, mptsas_doneq_thread,
1319 1319 &mpt->m_doneq_thread_id[j].arg,
1320 1320 0, &p0, TS_RUN, minclsyspri);
1321 1321 mpt->m_doneq_thread_id[j].donetail =
1322 1322 &mpt->m_doneq_thread_id[j].doneq;
1323 1323 mutex_exit(&mpt->m_doneq_thread_id[j].mutex);
1324 1324 }
1325 1325 mutex_exit(&mpt->m_doneq_mutex);
1326 1326 doneq_thread_create++;
1327 1327 }
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1328 1328
1329 1329 /*
1330 1330 * Disable hardware interrupt since we're not ready to
1331 1331 * handle it yet.
1332 1332 */
1333 1333 MPTSAS_DISABLE_INTR(mpt);
1334 1334 if (mptsas_register_intrs(mpt) == FALSE)
1335 1335 goto fail;
1336 1336 intr_added++;
1337 1337
1338 + /*
1339 + * The mutex to protect task management during reset
1340 + */
1341 + mutex_init(&mpt->m_taskmgmt_mutex, NULL, MUTEX_SPIN,
1342 + DDI_INTR_PRI(mpt->m_intr_pri));
1343 +
1338 1344 /* Initialize mutex used in interrupt handler */
1339 1345 mutex_init(&mpt->m_mutex, NULL, MUTEX_DRIVER,
1340 1346 DDI_INTR_PRI(mpt->m_intr_pri));
1341 1347 mutex_init(&mpt->m_passthru_mutex, NULL, MUTEX_DRIVER, NULL);
1342 1348 mutex_init(&mpt->m_tx_waitq_mutex, NULL, MUTEX_DRIVER,
1343 1349 DDI_INTR_PRI(mpt->m_intr_pri));
1344 1350 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
1345 1351 mutex_init(&mpt->m_phy_info[i].smhba_info.phy_mutex,
1346 1352 NULL, MUTEX_DRIVER,
1347 1353 DDI_INTR_PRI(mpt->m_intr_pri));
1348 1354 }
1349 1355
1350 1356 cv_init(&mpt->m_cv, NULL, CV_DRIVER, NULL);
1351 1357 cv_init(&mpt->m_passthru_cv, NULL, CV_DRIVER, NULL);
1352 1358 cv_init(&mpt->m_fw_cv, NULL, CV_DRIVER, NULL);
1353 1359 cv_init(&mpt->m_config_cv, NULL, CV_DRIVER, NULL);
1354 1360 cv_init(&mpt->m_fw_diag_cv, NULL, CV_DRIVER, NULL);
1355 1361 cv_init(&mpt->m_extreq_sense_refcount_cv, NULL, CV_DRIVER, NULL);
1356 1362 mutex_init_done++;
1357 1363
1358 1364 mutex_enter(&mpt->m_mutex);
1359 1365 /*
1360 1366 * Initialize power management component
1361 1367 */
1362 1368 if (mpt->m_options & MPTSAS_OPT_PM) {
1363 1369 if (mptsas_init_pm(mpt)) {
1364 1370 mutex_exit(&mpt->m_mutex);
1365 1371 mptsas_log(mpt, CE_WARN, "mptsas pm initialization "
1366 1372 "failed");
1367 1373 goto fail;
1368 1374 }
1369 1375 }
1370 1376
1371 1377 /*
1372 1378 * Initialize chip using Message Unit Reset, if allowed
1373 1379 */
1374 1380 mpt->m_softstate |= MPTSAS_SS_MSG_UNIT_RESET;
1375 1381 if (mptsas_init_chip(mpt, TRUE) == DDI_FAILURE) {
1376 1382 mutex_exit(&mpt->m_mutex);
1377 1383 mptsas_log(mpt, CE_WARN, "mptsas chip initialization failed");
1378 1384 goto fail;
1379 1385 }
1380 1386
1381 1387 mpt->m_targets = refhash_create(MPTSAS_TARGET_BUCKET_COUNT,
1382 1388 mptsas_target_addr_hash, mptsas_target_addr_cmp,
1383 1389 mptsas_target_free, sizeof (mptsas_target_t),
1384 1390 offsetof(mptsas_target_t, m_link),
1385 1391 offsetof(mptsas_target_t, m_addr), KM_SLEEP);
1386 1392
1387 1393 /*
1388 1394 * The refhash for temporary targets uses the address of the target
1389 1395 * struct itself as tag, so the tag offset is 0. See the implementation
1390 1396 * of mptsas_tmp_target_hash() and mptsas_tmp_target_cmp().
1391 1397 */
1392 1398 mpt->m_tmp_targets = refhash_create(MPTSAS_TMP_TARGET_BUCKET_COUNT,
1393 1399 mptsas_tmp_target_hash, mptsas_tmp_target_cmp,
1394 1400 mptsas_target_free, sizeof (mptsas_target_t),
1395 1401 offsetof(mptsas_target_t, m_link), 0, KM_SLEEP);
1396 1402
1397 1403 /*
1398 1404 * Fill in the phy_info structure and get the base WWID
1399 1405 */
1400 1406 if (mptsas_get_manufacture_page5(mpt) == DDI_FAILURE) {
1401 1407 mptsas_log(mpt, CE_WARN,
1402 1408 "mptsas_get_manufacture_page5 failed!");
1403 1409 goto fail;
1404 1410 }
1405 1411
1406 1412 if (mptsas_get_sas_io_unit_page_hndshk(mpt)) {
1407 1413 mptsas_log(mpt, CE_WARN,
1408 1414 "mptsas_get_sas_io_unit_page_hndshk failed!");
1409 1415 goto fail;
1410 1416 }
1411 1417
1412 1418 if (mptsas_get_manufacture_page0(mpt) == DDI_FAILURE) {
1413 1419 mptsas_log(mpt, CE_WARN,
1414 1420 "mptsas_get_manufacture_page0 failed!");
1415 1421 goto fail;
1416 1422 }
1417 1423
1418 1424 mutex_exit(&mpt->m_mutex);
1419 1425
1420 1426 /*
1421 1427 * Register the iport for multiple port HBA
1422 1428 */
1423 1429 mptsas_iport_register(mpt);
1424 1430
1425 1431 /*
1426 1432 * initialize SCSI HBA transport structure
1427 1433 */
1428 1434 if (mptsas_hba_setup(mpt) == FALSE)
1429 1435 goto fail;
1430 1436 hba_attach_setup++;
1431 1437
1432 1438 if (mptsas_smp_setup(mpt) == FALSE)
1433 1439 goto fail;
1434 1440 smp_attach_setup++;
1435 1441
1436 1442 if (mptsas_cache_create(mpt) == FALSE)
1437 1443 goto fail;
1438 1444
1439 1445 mpt->m_scsi_reset_delay = ddi_prop_get_int(DDI_DEV_T_ANY,
1440 1446 dip, 0, "scsi-reset-delay", SCSI_DEFAULT_RESET_DELAY);
1441 1447 if (mpt->m_scsi_reset_delay == 0) {
1442 1448 mptsas_log(mpt, CE_NOTE,
1443 1449 "scsi_reset_delay of 0 is not recommended,"
1444 1450 " resetting to SCSI_DEFAULT_RESET_DELAY\n");
1445 1451 mpt->m_scsi_reset_delay = SCSI_DEFAULT_RESET_DELAY;
1446 1452 }
1447 1453
1448 1454 /*
1449 1455 * Initialize the wait and done FIFO queue
1450 1456 */
1451 1457 mpt->m_donetail = &mpt->m_doneq;
1452 1458 mpt->m_waitqtail = &mpt->m_waitq;
1453 1459 mpt->m_tx_waitqtail = &mpt->m_tx_waitq;
1454 1460 mpt->m_tx_draining = 0;
1455 1461
1456 1462 /*
1457 1463 * ioc cmd queue initialize
1458 1464 */
1459 1465 mpt->m_ioc_event_cmdtail = &mpt->m_ioc_event_cmdq;
1460 1466 mpt->m_dev_handle = 0xFFFF;
1461 1467
1462 1468 MPTSAS_ENABLE_INTR(mpt);
1463 1469
1464 1470 /*
1465 1471 * enable event notification
1466 1472 */
1467 1473 mutex_enter(&mpt->m_mutex);
1468 1474 if (mptsas_ioc_enable_event_notification(mpt)) {
1469 1475 mutex_exit(&mpt->m_mutex);
1470 1476 goto fail;
1471 1477 }
1472 1478 mutex_exit(&mpt->m_mutex);
1473 1479
1474 1480 /*
1475 1481 * used for mptsas_watch
1476 1482 */
1477 1483 mptsas_list_add(mpt);
1478 1484
1479 1485 mutex_enter(&mptsas_global_mutex);
1480 1486 if (mptsas_timeouts_enabled == 0) {
1481 1487 mptsas_scsi_watchdog_tick = ddi_prop_get_int(DDI_DEV_T_ANY,
1482 1488 dip, 0, "scsi-watchdog-tick", DEFAULT_WD_TICK);
1483 1489
1484 1490 mptsas_tick = mptsas_scsi_watchdog_tick *
1485 1491 drv_usectohz((clock_t)1000000);
1486 1492
1487 1493 mptsas_timeout_id = timeout(mptsas_watch, NULL, mptsas_tick);
1488 1494 mptsas_timeouts_enabled = 1;
1489 1495 }
1490 1496 mutex_exit(&mptsas_global_mutex);
1491 1497 added_watchdog++;
1492 1498
1493 1499 /*
1494 1500 * Initialize PHY info for smhba.
1495 1501 * This requires watchdog to be enabled otherwise if interrupts
1496 1502 * don't work the system will hang.
1497 1503 */
1498 1504 if (mptsas_smhba_setup(mpt)) {
1499 1505 mptsas_log(mpt, CE_WARN, "mptsas phy initialization "
1500 1506 "failed");
1501 1507 goto fail;
1502 1508 }
1503 1509
1504 1510 /* Check all dma handles allocated in attach */
1505 1511 if ((mptsas_check_dma_handle(mpt->m_dma_req_frame_hdl)
1506 1512 != DDI_SUCCESS) ||
1507 1513 (mptsas_check_dma_handle(mpt->m_dma_req_sense_hdl)
1508 1514 != DDI_SUCCESS) ||
1509 1515 (mptsas_check_dma_handle(mpt->m_dma_reply_frame_hdl)
1510 1516 != DDI_SUCCESS) ||
1511 1517 (mptsas_check_dma_handle(mpt->m_dma_free_queue_hdl)
1512 1518 != DDI_SUCCESS) ||
1513 1519 (mptsas_check_dma_handle(mpt->m_dma_post_queue_hdl)
1514 1520 != DDI_SUCCESS) ||
1515 1521 (mptsas_check_dma_handle(mpt->m_hshk_dma_hdl)
1516 1522 != DDI_SUCCESS)) {
1517 1523 goto fail;
1518 1524 }
1519 1525
1520 1526 /* Check all acc handles allocated in attach */
1521 1527 if ((mptsas_check_acc_handle(mpt->m_datap) != DDI_SUCCESS) ||
1522 1528 (mptsas_check_acc_handle(mpt->m_acc_req_frame_hdl)
1523 1529 != DDI_SUCCESS) ||
1524 1530 (mptsas_check_acc_handle(mpt->m_acc_req_sense_hdl)
1525 1531 != DDI_SUCCESS) ||
1526 1532 (mptsas_check_acc_handle(mpt->m_acc_reply_frame_hdl)
1527 1533 != DDI_SUCCESS) ||
1528 1534 (mptsas_check_acc_handle(mpt->m_acc_free_queue_hdl)
1529 1535 != DDI_SUCCESS) ||
1530 1536 (mptsas_check_acc_handle(mpt->m_acc_post_queue_hdl)
1531 1537 != DDI_SUCCESS) ||
1532 1538 (mptsas_check_acc_handle(mpt->m_hshk_acc_hdl)
1533 1539 != DDI_SUCCESS) ||
1534 1540 (mptsas_check_acc_handle(mpt->m_config_handle)
1535 1541 != DDI_SUCCESS)) {
1536 1542 goto fail;
1537 1543 }
1538 1544
1539 1545 /*
1540 1546 * After this point, we are not going to fail the attach.
1541 1547 */
1542 1548
1543 1549 /* Print message of HBA present */
1544 1550 ddi_report_dev(dip);
1545 1551
1546 1552 /* report idle status to pm framework */
1547 1553 if (mpt->m_options & MPTSAS_OPT_PM) {
1548 1554 (void) pm_idle_component(dip, 0);
1549 1555 }
1550 1556
1551 1557 return (DDI_SUCCESS);
1552 1558
1553 1559 fail:
1554 1560 mptsas_log(mpt, CE_WARN, "attach failed");
1555 1561 mptsas_fm_ereport(mpt, DDI_FM_DEVICE_NO_RESPONSE);
1556 1562 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_LOST);
1557 1563 if (mpt) {
1558 1564 /* deallocate in reverse order */
1559 1565 if (added_watchdog) {
1560 1566 mptsas_list_del(mpt);
1561 1567 mutex_enter(&mptsas_global_mutex);
1562 1568
1563 1569 if (mptsas_timeout_id && (mptsas_head == NULL)) {
1564 1570 timeout_id_t tid = mptsas_timeout_id;
1565 1571 mptsas_timeouts_enabled = 0;
1566 1572 mptsas_timeout_id = 0;
1567 1573 mutex_exit(&mptsas_global_mutex);
1568 1574 (void) untimeout(tid);
1569 1575 mutex_enter(&mptsas_global_mutex);
1570 1576 }
1571 1577 mutex_exit(&mptsas_global_mutex);
1572 1578 }
1573 1579
1574 1580 mptsas_cache_destroy(mpt);
1575 1581
1576 1582 if (smp_attach_setup) {
1577 1583 mptsas_smp_teardown(mpt);
1578 1584 }
1579 1585 if (hba_attach_setup) {
1580 1586 mptsas_hba_teardown(mpt);
1581 1587 }
1582 1588
1583 1589 if (mpt->m_tmp_targets)
1584 1590 refhash_destroy(mpt->m_tmp_targets);
1585 1591 if (mpt->m_targets)
1586 1592 refhash_destroy(mpt->m_targets);
1587 1593 if (mpt->m_smp_targets)
1588 1594 refhash_destroy(mpt->m_smp_targets);
1589 1595
1590 1596 if (mpt->m_active) {
1591 1597 mptsas_free_active_slots(mpt);
1592 1598 }
1593 1599 if (intr_added) {
1594 1600 mptsas_unregister_intrs(mpt);
1595 1601 }
1596 1602
1597 1603 if (doneq_thread_create) {
1598 1604 mutex_enter(&mpt->m_doneq_mutex);
1599 1605 doneq_thread_num = mpt->m_doneq_thread_n;
1600 1606 for (j = 0; j < mpt->m_doneq_thread_n; j++) {
1601 1607 mutex_enter(&mpt->m_doneq_thread_id[j].mutex);
1602 1608 mpt->m_doneq_thread_id[j].flag &=
1603 1609 (~MPTSAS_DONEQ_THREAD_ACTIVE);
1604 1610 cv_signal(&mpt->m_doneq_thread_id[j].cv);
1605 1611 mutex_exit(&mpt->m_doneq_thread_id[j].mutex);
1606 1612 }
1607 1613 while (mpt->m_doneq_thread_n) {
1608 1614 cv_wait(&mpt->m_doneq_thread_cv,
1609 1615 &mpt->m_doneq_mutex);
1610 1616 }
1611 1617 for (j = 0; j < doneq_thread_num; j++) {
1612 1618 cv_destroy(&mpt->m_doneq_thread_id[j].cv);
1613 1619 mutex_destroy(&mpt->m_doneq_thread_id[j].mutex);
1614 1620 }
1615 1621 kmem_free(mpt->m_doneq_thread_id,
1616 1622 sizeof (mptsas_doneq_thread_list_t)
1617 1623 * doneq_thread_num);
1618 1624 mutex_exit(&mpt->m_doneq_mutex);
1619 1625 cv_destroy(&mpt->m_doneq_thread_cv);
1620 1626 mutex_destroy(&mpt->m_doneq_mutex);
1621 1627 }
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1622 1628 if (event_taskq_create) {
1623 1629 ddi_taskq_destroy(mpt->m_event_taskq);
1624 1630 }
1625 1631 if (dr_taskq_create) {
1626 1632 ddi_taskq_destroy(mpt->m_dr_taskq);
1627 1633 }
1628 1634 if (mutex_init_done) {
1629 1635 mutex_destroy(&mpt->m_tx_waitq_mutex);
1630 1636 mutex_destroy(&mpt->m_passthru_mutex);
1631 1637 mutex_destroy(&mpt->m_mutex);
1638 + mutex_destroy(&mpt->m_taskmgmt_mutex);
1632 1639 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
1633 1640 mutex_destroy(
1634 1641 &mpt->m_phy_info[i].smhba_info.phy_mutex);
1635 1642 }
1636 1643 cv_destroy(&mpt->m_cv);
1637 1644 cv_destroy(&mpt->m_passthru_cv);
1638 1645 cv_destroy(&mpt->m_fw_cv);
1639 1646 cv_destroy(&mpt->m_config_cv);
1640 1647 cv_destroy(&mpt->m_fw_diag_cv);
1641 1648 cv_destroy(&mpt->m_extreq_sense_refcount_cv);
1642 1649 }
1643 1650
1644 1651 if (map_setup) {
1645 1652 mptsas_cfg_fini(mpt);
1646 1653 }
1647 1654 if (config_setup) {
1648 1655 mptsas_config_space_fini(mpt);
1649 1656 }
1650 1657 mptsas_free_handshake_msg(mpt);
1651 1658 mptsas_hba_fini(mpt);
1652 1659
1653 1660 mptsas_fm_fini(mpt);
1654 1661 ddi_soft_state_free(mptsas_state, instance);
1655 1662 ddi_prop_remove_all(dip);
1656 1663 }
1657 1664 return (DDI_FAILURE);
1658 1665 }
1659 1666
1660 1667 static int
1661 1668 mptsas_suspend(dev_info_t *devi)
1662 1669 {
1663 1670 mptsas_t *mpt, *g;
1664 1671 scsi_hba_tran_t *tran;
1665 1672
1666 1673 if (scsi_hba_iport_unit_address(devi)) {
1667 1674 return (DDI_SUCCESS);
1668 1675 }
1669 1676
1670 1677 if ((tran = ddi_get_driver_private(devi)) == NULL)
1671 1678 return (DDI_SUCCESS);
1672 1679
1673 1680 mpt = TRAN2MPT(tran);
1674 1681 if (!mpt) {
1675 1682 return (DDI_SUCCESS);
1676 1683 }
1677 1684
1678 1685 mutex_enter(&mpt->m_mutex);
1679 1686
1680 1687 if (mpt->m_suspended++) {
1681 1688 mutex_exit(&mpt->m_mutex);
1682 1689 return (DDI_SUCCESS);
1683 1690 }
1684 1691
1685 1692 /*
1686 1693 * Cancel timeout threads for this mpt
1687 1694 */
1688 1695 if (mpt->m_quiesce_timeid) {
1689 1696 timeout_id_t tid = mpt->m_quiesce_timeid;
1690 1697 mpt->m_quiesce_timeid = 0;
1691 1698 mutex_exit(&mpt->m_mutex);
1692 1699 (void) untimeout(tid);
1693 1700 mutex_enter(&mpt->m_mutex);
1694 1701 }
1695 1702
1696 1703 if (mpt->m_restart_cmd_timeid) {
1697 1704 timeout_id_t tid = mpt->m_restart_cmd_timeid;
1698 1705 mpt->m_restart_cmd_timeid = 0;
1699 1706 mutex_exit(&mpt->m_mutex);
1700 1707 (void) untimeout(tid);
1701 1708 mutex_enter(&mpt->m_mutex);
1702 1709 }
1703 1710
1704 1711 mutex_exit(&mpt->m_mutex);
1705 1712
1706 1713 (void) pm_idle_component(mpt->m_dip, 0);
1707 1714
1708 1715 /*
1709 1716 * Cancel watch threads if all mpts suspended
1710 1717 */
1711 1718 rw_enter(&mptsas_global_rwlock, RW_WRITER);
1712 1719 for (g = mptsas_head; g != NULL; g = g->m_next) {
1713 1720 if (!g->m_suspended)
1714 1721 break;
1715 1722 }
1716 1723 rw_exit(&mptsas_global_rwlock);
1717 1724
1718 1725 mutex_enter(&mptsas_global_mutex);
1719 1726 if (g == NULL) {
1720 1727 timeout_id_t tid;
1721 1728
1722 1729 mptsas_timeouts_enabled = 0;
1723 1730 if (mptsas_timeout_id) {
1724 1731 tid = mptsas_timeout_id;
1725 1732 mptsas_timeout_id = 0;
1726 1733 mutex_exit(&mptsas_global_mutex);
1727 1734 (void) untimeout(tid);
1728 1735 mutex_enter(&mptsas_global_mutex);
1729 1736 }
1730 1737 if (mptsas_reset_watch) {
1731 1738 tid = mptsas_reset_watch;
1732 1739 mptsas_reset_watch = 0;
1733 1740 mutex_exit(&mptsas_global_mutex);
1734 1741 (void) untimeout(tid);
1735 1742 mutex_enter(&mptsas_global_mutex);
1736 1743 }
1737 1744 }
1738 1745 mutex_exit(&mptsas_global_mutex);
1739 1746
1740 1747 mutex_enter(&mpt->m_mutex);
1741 1748
1742 1749 /*
1743 1750 * If this mpt is not in full power(PM_LEVEL_D0), just return.
1744 1751 */
1745 1752 if ((mpt->m_options & MPTSAS_OPT_PM) &&
1746 1753 (mpt->m_power_level != PM_LEVEL_D0)) {
1747 1754 mutex_exit(&mpt->m_mutex);
1748 1755 return (DDI_SUCCESS);
1749 1756 }
1750 1757
1751 1758 /* Disable HBA interrupts in hardware */
1752 1759 MPTSAS_DISABLE_INTR(mpt);
1753 1760 /*
1754 1761 * Send RAID action system shutdown to sync IR
1755 1762 */
1756 1763 mptsas_raid_action_system_shutdown(mpt);
1757 1764
1758 1765 mutex_exit(&mpt->m_mutex);
1759 1766
1760 1767 /* drain the taskq */
1761 1768 ddi_taskq_wait(mpt->m_event_taskq);
1762 1769 ddi_taskq_wait(mpt->m_dr_taskq);
1763 1770
1764 1771 return (DDI_SUCCESS);
1765 1772 }
1766 1773
1767 1774 #ifdef __sparc
1768 1775 /*ARGSUSED*/
1769 1776 static int
1770 1777 mptsas_reset(dev_info_t *devi, ddi_reset_cmd_t cmd)
1771 1778 {
1772 1779 mptsas_t *mpt;
1773 1780 scsi_hba_tran_t *tran;
1774 1781
1775 1782 /*
1776 1783 * If this call is for iport, just return.
1777 1784 */
1778 1785 if (scsi_hba_iport_unit_address(devi))
1779 1786 return (DDI_SUCCESS);
1780 1787
1781 1788 if ((tran = ddi_get_driver_private(devi)) == NULL)
1782 1789 return (DDI_SUCCESS);
1783 1790
1784 1791 if ((mpt = TRAN2MPT(tran)) == NULL)
1785 1792 return (DDI_SUCCESS);
1786 1793
1787 1794 /*
1788 1795 * Send RAID action system shutdown to sync IR. Disable HBA
1789 1796 * interrupts in hardware first.
1790 1797 */
1791 1798 MPTSAS_DISABLE_INTR(mpt);
1792 1799 mptsas_raid_action_system_shutdown(mpt);
1793 1800
1794 1801 return (DDI_SUCCESS);
1795 1802 }
1796 1803 #else /* __sparc */
1797 1804 /*
1798 1805 * quiesce(9E) entry point.
1799 1806 *
1800 1807 * This function is called when the system is single-threaded at high
1801 1808 * PIL with preemption disabled. Therefore, this function must not be
1802 1809 * blocked.
1803 1810 *
1804 1811 * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure.
1805 1812 * DDI_FAILURE indicates an error condition and should almost never happen.
1806 1813 */
1807 1814 static int
1808 1815 mptsas_quiesce(dev_info_t *devi)
1809 1816 {
1810 1817 mptsas_t *mpt;
1811 1818 scsi_hba_tran_t *tran;
1812 1819
1813 1820 /*
1814 1821 * If this call is for iport, just return.
1815 1822 */
1816 1823 if (scsi_hba_iport_unit_address(devi))
1817 1824 return (DDI_SUCCESS);
1818 1825
1819 1826 if ((tran = ddi_get_driver_private(devi)) == NULL)
1820 1827 return (DDI_SUCCESS);
1821 1828
1822 1829 if ((mpt = TRAN2MPT(tran)) == NULL)
1823 1830 return (DDI_SUCCESS);
1824 1831
1825 1832 /* Disable HBA interrupts in hardware */
1826 1833 MPTSAS_DISABLE_INTR(mpt);
1827 1834 /* Send RAID action system shutdonw to sync IR */
1828 1835 mptsas_raid_action_system_shutdown(mpt);
1829 1836
1830 1837 return (DDI_SUCCESS);
1831 1838 }
1832 1839 #endif /* __sparc */
1833 1840
1834 1841 /*
1835 1842 * detach(9E). Remove all device allocations and system resources;
1836 1843 * disable device interrupts.
1837 1844 * Return DDI_SUCCESS if done; DDI_FAILURE if there's a problem.
1838 1845 */
1839 1846 static int
1840 1847 mptsas_detach(dev_info_t *devi, ddi_detach_cmd_t cmd)
1841 1848 {
1842 1849 /* CONSTCOND */
1843 1850 ASSERT(NO_COMPETING_THREADS);
1844 1851 NDBG0(("mptsas_detach: dip=0x%p cmd=0x%p", (void *)devi, (void *)cmd));
1845 1852
1846 1853 switch (cmd) {
1847 1854 case DDI_DETACH:
1848 1855 return (mptsas_do_detach(devi));
1849 1856
1850 1857 case DDI_SUSPEND:
1851 1858 return (mptsas_suspend(devi));
1852 1859
1853 1860 default:
1854 1861 return (DDI_FAILURE);
1855 1862 }
1856 1863 /* NOTREACHED */
1857 1864 }
1858 1865
1859 1866 static int
1860 1867 mptsas_do_detach(dev_info_t *dip)
1861 1868 {
1862 1869 mptsas_t *mpt;
1863 1870 scsi_hba_tran_t *tran;
1864 1871 int circ = 0;
1865 1872 int circ1 = 0;
1866 1873 mdi_pathinfo_t *pip = NULL;
1867 1874 int i;
1868 1875 int doneq_thread_num = 0;
1869 1876
1870 1877 NDBG0(("mptsas_do_detach: dip=0x%p", (void *)dip));
1871 1878
1872 1879 if ((tran = ndi_flavorv_get(dip, SCSA_FLAVOR_SCSI_DEVICE)) == NULL)
1873 1880 return (DDI_FAILURE);
1874 1881
1875 1882 mpt = TRAN2MPT(tran);
1876 1883 if (!mpt) {
1877 1884 return (DDI_FAILURE);
1878 1885 }
1879 1886 /*
1880 1887 * Still have pathinfo child, should not detach mpt driver
1881 1888 */
1882 1889 if (scsi_hba_iport_unit_address(dip)) {
1883 1890 if (mpt->m_mpxio_enable) {
1884 1891 /*
1885 1892 * MPxIO enabled for the iport
1886 1893 */
1887 1894 ndi_devi_enter(scsi_vhci_dip, &circ1);
1888 1895 ndi_devi_enter(dip, &circ);
1889 1896 while (pip = mdi_get_next_client_path(dip, NULL)) {
1890 1897 if (mdi_pi_free(pip, 0) == MDI_SUCCESS) {
1891 1898 continue;
1892 1899 }
1893 1900 ndi_devi_exit(dip, circ);
1894 1901 ndi_devi_exit(scsi_vhci_dip, circ1);
1895 1902 NDBG12(("detach failed because of "
1896 1903 "outstanding path info"));
1897 1904 return (DDI_FAILURE);
1898 1905 }
1899 1906 ndi_devi_exit(dip, circ);
1900 1907 ndi_devi_exit(scsi_vhci_dip, circ1);
1901 1908 (void) mdi_phci_unregister(dip, 0);
1902 1909 }
1903 1910
1904 1911 ddi_prop_remove_all(dip);
1905 1912
1906 1913 return (DDI_SUCCESS);
1907 1914 }
1908 1915
1909 1916 /* Make sure power level is D0 before accessing registers */
1910 1917 if (mpt->m_options & MPTSAS_OPT_PM) {
1911 1918 (void) pm_busy_component(dip, 0);
1912 1919 if (mpt->m_power_level != PM_LEVEL_D0) {
1913 1920 if (pm_raise_power(dip, 0, PM_LEVEL_D0) !=
1914 1921 DDI_SUCCESS) {
1915 1922 mptsas_log(mpt, CE_WARN,
1916 1923 "mptsas%d: Raise power request failed.",
1917 1924 mpt->m_instance);
1918 1925 (void) pm_idle_component(dip, 0);
1919 1926 return (DDI_FAILURE);
1920 1927 }
1921 1928 }
1922 1929 }
1923 1930
1924 1931 /*
1925 1932 * Send RAID action system shutdown to sync IR. After action, send a
1926 1933 * Message Unit Reset. Since after that DMA resource will be freed,
1927 1934 * set ioc to READY state will avoid HBA initiated DMA operation.
1928 1935 */
1929 1936 mutex_enter(&mpt->m_mutex);
1930 1937 MPTSAS_DISABLE_INTR(mpt);
1931 1938 mptsas_raid_action_system_shutdown(mpt);
1932 1939 mpt->m_softstate |= MPTSAS_SS_MSG_UNIT_RESET;
1933 1940 (void) mptsas_ioc_reset(mpt, FALSE);
1934 1941 mutex_exit(&mpt->m_mutex);
1935 1942 mptsas_rem_intrs(mpt);
1936 1943 ddi_taskq_destroy(mpt->m_event_taskq);
1937 1944 ddi_taskq_destroy(mpt->m_dr_taskq);
1938 1945
1939 1946 if (mpt->m_doneq_thread_n) {
1940 1947 mutex_enter(&mpt->m_doneq_mutex);
1941 1948 doneq_thread_num = mpt->m_doneq_thread_n;
1942 1949 for (i = 0; i < mpt->m_doneq_thread_n; i++) {
1943 1950 mutex_enter(&mpt->m_doneq_thread_id[i].mutex);
1944 1951 mpt->m_doneq_thread_id[i].flag &=
1945 1952 (~MPTSAS_DONEQ_THREAD_ACTIVE);
1946 1953 cv_signal(&mpt->m_doneq_thread_id[i].cv);
1947 1954 mutex_exit(&mpt->m_doneq_thread_id[i].mutex);
1948 1955 }
1949 1956 while (mpt->m_doneq_thread_n) {
1950 1957 cv_wait(&mpt->m_doneq_thread_cv,
1951 1958 &mpt->m_doneq_mutex);
1952 1959 }
1953 1960 for (i = 0; i < doneq_thread_num; i++) {
1954 1961 cv_destroy(&mpt->m_doneq_thread_id[i].cv);
1955 1962 mutex_destroy(&mpt->m_doneq_thread_id[i].mutex);
1956 1963 }
1957 1964 kmem_free(mpt->m_doneq_thread_id,
1958 1965 sizeof (mptsas_doneq_thread_list_t)
1959 1966 * doneq_thread_num);
1960 1967 mutex_exit(&mpt->m_doneq_mutex);
1961 1968 cv_destroy(&mpt->m_doneq_thread_cv);
1962 1969 mutex_destroy(&mpt->m_doneq_mutex);
1963 1970 }
1964 1971
1965 1972 scsi_hba_reset_notify_tear_down(mpt->m_reset_notify_listf);
1966 1973
1967 1974 mptsas_list_del(mpt);
1968 1975
1969 1976 /*
1970 1977 * Cancel timeout threads for this mpt
1971 1978 */
1972 1979 mutex_enter(&mpt->m_mutex);
1973 1980 if (mpt->m_quiesce_timeid) {
1974 1981 timeout_id_t tid = mpt->m_quiesce_timeid;
1975 1982 mpt->m_quiesce_timeid = 0;
1976 1983 mutex_exit(&mpt->m_mutex);
1977 1984 (void) untimeout(tid);
1978 1985 mutex_enter(&mpt->m_mutex);
1979 1986 }
1980 1987
1981 1988 if (mpt->m_restart_cmd_timeid) {
1982 1989 timeout_id_t tid = mpt->m_restart_cmd_timeid;
1983 1990 mpt->m_restart_cmd_timeid = 0;
1984 1991 mutex_exit(&mpt->m_mutex);
1985 1992 (void) untimeout(tid);
1986 1993 mutex_enter(&mpt->m_mutex);
1987 1994 }
1988 1995
1989 1996 mutex_exit(&mpt->m_mutex);
1990 1997
1991 1998 /*
1992 1999 * last mpt? ... if active, CANCEL watch threads.
1993 2000 */
1994 2001 mutex_enter(&mptsas_global_mutex);
1995 2002 if (mptsas_head == NULL) {
1996 2003 timeout_id_t tid;
1997 2004 /*
1998 2005 * Clear mptsas_timeouts_enable so that the watch thread
1999 2006 * gets restarted on DDI_ATTACH
2000 2007 */
2001 2008 mptsas_timeouts_enabled = 0;
2002 2009 if (mptsas_timeout_id) {
2003 2010 tid = mptsas_timeout_id;
2004 2011 mptsas_timeout_id = 0;
2005 2012 mutex_exit(&mptsas_global_mutex);
2006 2013 (void) untimeout(tid);
2007 2014 mutex_enter(&mptsas_global_mutex);
2008 2015 }
2009 2016 if (mptsas_reset_watch) {
2010 2017 tid = mptsas_reset_watch;
2011 2018 mptsas_reset_watch = 0;
2012 2019 mutex_exit(&mptsas_global_mutex);
2013 2020 (void) untimeout(tid);
2014 2021 mutex_enter(&mptsas_global_mutex);
2015 2022 }
2016 2023 }
2017 2024 mutex_exit(&mptsas_global_mutex);
2018 2025
2019 2026 /*
2020 2027 * Delete Phy stats
2021 2028 */
2022 2029 mptsas_destroy_phy_stats(mpt);
2023 2030
2024 2031 mptsas_destroy_hashes(mpt);
2025 2032
2026 2033 /*
2027 2034 * Delete nt_active.
2028 2035 */
2029 2036 mutex_enter(&mpt->m_mutex);
2030 2037 mptsas_free_active_slots(mpt);
2031 2038 mutex_exit(&mpt->m_mutex);
2032 2039
2033 2040 /* deallocate everything that was allocated in mptsas_attach */
2034 2041 mptsas_cache_destroy(mpt);
2035 2042
2036 2043 mptsas_hba_fini(mpt);
2037 2044 mptsas_cfg_fini(mpt);
2038 2045
2039 2046 /* Lower the power informing PM Framework */
2040 2047 if (mpt->m_options & MPTSAS_OPT_PM) {
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2041 2048 if (pm_lower_power(dip, 0, PM_LEVEL_D3) != DDI_SUCCESS)
2042 2049 mptsas_log(mpt, CE_WARN,
2043 2050 "!mptsas%d: Lower power request failed "
2044 2051 "during detach, ignoring.",
2045 2052 mpt->m_instance);
2046 2053 }
2047 2054
2048 2055 mutex_destroy(&mpt->m_tx_waitq_mutex);
2049 2056 mutex_destroy(&mpt->m_passthru_mutex);
2050 2057 mutex_destroy(&mpt->m_mutex);
2058 + mutex_destroy(&mpt->m_taskmgmt_mutex);
2051 2059 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
2052 2060 mutex_destroy(&mpt->m_phy_info[i].smhba_info.phy_mutex);
2053 2061 }
2054 2062 cv_destroy(&mpt->m_cv);
2055 2063 cv_destroy(&mpt->m_passthru_cv);
2056 2064 cv_destroy(&mpt->m_fw_cv);
2057 2065 cv_destroy(&mpt->m_config_cv);
2058 2066 cv_destroy(&mpt->m_fw_diag_cv);
2059 2067 cv_destroy(&mpt->m_extreq_sense_refcount_cv);
2060 2068
2061 2069 mptsas_smp_teardown(mpt);
2062 2070 mptsas_hba_teardown(mpt);
2063 2071
2064 2072 mptsas_config_space_fini(mpt);
2065 2073
2066 2074 mptsas_free_handshake_msg(mpt);
2067 2075
2068 2076 mptsas_fm_fini(mpt);
2069 2077 ddi_soft_state_free(mptsas_state, ddi_get_instance(dip));
2070 2078 ddi_prop_remove_all(dip);
2071 2079
2072 2080 return (DDI_SUCCESS);
2073 2081 }
2074 2082
2075 2083 static void
2076 2084 mptsas_list_add(mptsas_t *mpt)
2077 2085 {
2078 2086 rw_enter(&mptsas_global_rwlock, RW_WRITER);
2079 2087
2080 2088 if (mptsas_head == NULL) {
2081 2089 mptsas_head = mpt;
2082 2090 } else {
2083 2091 mptsas_tail->m_next = mpt;
2084 2092 }
2085 2093 mptsas_tail = mpt;
2086 2094 rw_exit(&mptsas_global_rwlock);
2087 2095 }
2088 2096
2089 2097 static void
2090 2098 mptsas_list_del(mptsas_t *mpt)
2091 2099 {
2092 2100 mptsas_t *m;
2093 2101 /*
2094 2102 * Remove device instance from the global linked list
2095 2103 */
2096 2104 rw_enter(&mptsas_global_rwlock, RW_WRITER);
2097 2105 if (mptsas_head == mpt) {
2098 2106 m = mptsas_head = mpt->m_next;
2099 2107 } else {
2100 2108 for (m = mptsas_head; m != NULL; m = m->m_next) {
2101 2109 if (m->m_next == mpt) {
2102 2110 m->m_next = mpt->m_next;
2103 2111 break;
2104 2112 }
2105 2113 }
2106 2114 if (m == NULL) {
2107 2115 mptsas_log(mpt, CE_PANIC, "Not in softc list!");
2108 2116 }
2109 2117 }
2110 2118
2111 2119 if (mptsas_tail == mpt) {
2112 2120 mptsas_tail = m;
2113 2121 }
2114 2122 rw_exit(&mptsas_global_rwlock);
2115 2123 }
2116 2124
2117 2125 static int
2118 2126 mptsas_alloc_handshake_msg(mptsas_t *mpt, size_t alloc_size)
2119 2127 {
2120 2128 ddi_dma_attr_t task_dma_attrs;
2121 2129
2122 2130 mpt->m_hshk_dma_size = 0;
2123 2131 task_dma_attrs = mpt->m_msg_dma_attr;
2124 2132 task_dma_attrs.dma_attr_sgllen = 1;
2125 2133 task_dma_attrs.dma_attr_granular = (uint32_t)(alloc_size);
2126 2134
2127 2135 /* allocate Task Management ddi_dma resources */
2128 2136 if (mptsas_dma_addr_create(mpt, task_dma_attrs,
2129 2137 &mpt->m_hshk_dma_hdl, &mpt->m_hshk_acc_hdl, &mpt->m_hshk_memp,
2130 2138 alloc_size, NULL) == FALSE) {
2131 2139 return (DDI_FAILURE);
2132 2140 }
2133 2141 mpt->m_hshk_dma_size = alloc_size;
2134 2142
2135 2143 return (DDI_SUCCESS);
2136 2144 }
2137 2145
2138 2146 static void
2139 2147 mptsas_free_handshake_msg(mptsas_t *mpt)
2140 2148 {
2141 2149 if (mpt->m_hshk_dma_size == 0)
2142 2150 return;
2143 2151 mptsas_dma_addr_destroy(&mpt->m_hshk_dma_hdl, &mpt->m_hshk_acc_hdl);
2144 2152 mpt->m_hshk_dma_size = 0;
2145 2153 }
2146 2154
2147 2155 static int
2148 2156 mptsas_hba_setup(mptsas_t *mpt)
2149 2157 {
2150 2158 scsi_hba_tran_t *hba_tran;
2151 2159 int tran_flags;
2152 2160
2153 2161 /* Allocate a transport structure */
2154 2162 hba_tran = mpt->m_tran = scsi_hba_tran_alloc(mpt->m_dip,
2155 2163 SCSI_HBA_CANSLEEP);
2156 2164 ASSERT(mpt->m_tran != NULL);
2157 2165
2158 2166 hba_tran->tran_hba_private = mpt;
2159 2167 hba_tran->tran_tgt_private = NULL;
2160 2168
2161 2169 hba_tran->tran_tgt_init = mptsas_scsi_tgt_init;
2162 2170 hba_tran->tran_tgt_free = mptsas_scsi_tgt_free;
2163 2171
2164 2172 hba_tran->tran_start = mptsas_scsi_start;
2165 2173 hba_tran->tran_reset = mptsas_scsi_reset;
2166 2174 hba_tran->tran_abort = mptsas_scsi_abort;
2167 2175 hba_tran->tran_getcap = mptsas_scsi_getcap;
2168 2176 hba_tran->tran_setcap = mptsas_scsi_setcap;
2169 2177 hba_tran->tran_init_pkt = mptsas_scsi_init_pkt;
2170 2178 hba_tran->tran_destroy_pkt = mptsas_scsi_destroy_pkt;
2171 2179
2172 2180 hba_tran->tran_dmafree = mptsas_scsi_dmafree;
2173 2181 hba_tran->tran_sync_pkt = mptsas_scsi_sync_pkt;
2174 2182 hba_tran->tran_reset_notify = mptsas_scsi_reset_notify;
2175 2183
2176 2184 hba_tran->tran_get_bus_addr = mptsas_get_bus_addr;
2177 2185 hba_tran->tran_get_name = mptsas_get_name;
2178 2186
2179 2187 hba_tran->tran_quiesce = mptsas_scsi_quiesce;
2180 2188 hba_tran->tran_unquiesce = mptsas_scsi_unquiesce;
2181 2189 hba_tran->tran_bus_reset = NULL;
2182 2190
2183 2191 hba_tran->tran_add_eventcall = NULL;
2184 2192 hba_tran->tran_get_eventcookie = NULL;
2185 2193 hba_tran->tran_post_event = NULL;
2186 2194 hba_tran->tran_remove_eventcall = NULL;
2187 2195
2188 2196 hba_tran->tran_bus_config = mptsas_bus_config;
2189 2197
2190 2198 hba_tran->tran_interconnect_type = INTERCONNECT_SAS;
2191 2199
2192 2200 /*
2193 2201 * All children of the HBA are iports. We need tran was cloned.
2194 2202 * So we pass the flags to SCSA. SCSI_HBA_TRAN_CLONE will be
2195 2203 * inherited to iport's tran vector.
2196 2204 */
2197 2205 tran_flags = (SCSI_HBA_HBA | SCSI_HBA_TRAN_CLONE);
2198 2206
2199 2207 if (scsi_hba_attach_setup(mpt->m_dip, &mpt->m_msg_dma_attr,
2200 2208 hba_tran, tran_flags) != DDI_SUCCESS) {
2201 2209 mptsas_log(mpt, CE_WARN, "hba attach setup failed");
2202 2210 scsi_hba_tran_free(hba_tran);
2203 2211 mpt->m_tran = NULL;
2204 2212 return (FALSE);
2205 2213 }
2206 2214 return (TRUE);
2207 2215 }
2208 2216
2209 2217 static void
2210 2218 mptsas_hba_teardown(mptsas_t *mpt)
2211 2219 {
2212 2220 (void) scsi_hba_detach(mpt->m_dip);
2213 2221 if (mpt->m_tran != NULL) {
2214 2222 scsi_hba_tran_free(mpt->m_tran);
2215 2223 mpt->m_tran = NULL;
2216 2224 }
2217 2225 }
2218 2226
2219 2227 static void
2220 2228 mptsas_iport_register(mptsas_t *mpt)
2221 2229 {
2222 2230 int i, j;
2223 2231 mptsas_phymask_t mask = 0x0;
2224 2232 /*
2225 2233 * initial value of mask is 0
2226 2234 */
2227 2235 mutex_enter(&mpt->m_mutex);
2228 2236 for (i = 0; i < mpt->m_num_phys; i++) {
2229 2237 mptsas_phymask_t phy_mask = 0x0;
2230 2238 char phy_mask_name[MPTSAS_MAX_PHYS];
2231 2239 uint8_t current_port;
2232 2240
2233 2241 if (mpt->m_phy_info[i].attached_devhdl == 0)
2234 2242 continue;
2235 2243
2236 2244 bzero(phy_mask_name, sizeof (phy_mask_name));
2237 2245
2238 2246 current_port = mpt->m_phy_info[i].port_num;
2239 2247
2240 2248 if ((mask & (1 << i)) != 0)
2241 2249 continue;
2242 2250
2243 2251 for (j = 0; j < mpt->m_num_phys; j++) {
2244 2252 if (mpt->m_phy_info[j].attached_devhdl &&
2245 2253 (mpt->m_phy_info[j].port_num == current_port)) {
2246 2254 phy_mask |= (1 << j);
2247 2255 }
2248 2256 }
2249 2257 mask = mask | phy_mask;
2250 2258
2251 2259 for (j = 0; j < mpt->m_num_phys; j++) {
2252 2260 if ((phy_mask >> j) & 0x01) {
2253 2261 mpt->m_phy_info[j].phy_mask = phy_mask;
2254 2262 }
2255 2263 }
2256 2264
2257 2265 (void) sprintf(phy_mask_name, "%x", phy_mask);
2258 2266
2259 2267 mutex_exit(&mpt->m_mutex);
2260 2268 /*
2261 2269 * register a iport
2262 2270 */
2263 2271 (void) scsi_hba_iport_register(mpt->m_dip, phy_mask_name);
2264 2272 mutex_enter(&mpt->m_mutex);
2265 2273 }
2266 2274 mutex_exit(&mpt->m_mutex);
2267 2275 /*
2268 2276 * register a virtual port for RAID volume always
2269 2277 */
2270 2278 (void) scsi_hba_iport_register(mpt->m_dip, "v0");
2271 2279
2272 2280 }
2273 2281
2274 2282 static int
2275 2283 mptsas_smp_setup(mptsas_t *mpt)
2276 2284 {
2277 2285 mpt->m_smptran = smp_hba_tran_alloc(mpt->m_dip);
2278 2286 ASSERT(mpt->m_smptran != NULL);
2279 2287 mpt->m_smptran->smp_tran_hba_private = mpt;
2280 2288 mpt->m_smptran->smp_tran_start = mptsas_smp_start;
2281 2289 if (smp_hba_attach_setup(mpt->m_dip, mpt->m_smptran) != DDI_SUCCESS) {
2282 2290 mptsas_log(mpt, CE_WARN, "smp attach setup failed");
2283 2291 smp_hba_tran_free(mpt->m_smptran);
2284 2292 mpt->m_smptran = NULL;
2285 2293 return (FALSE);
2286 2294 }
2287 2295 /*
2288 2296 * Initialize smp hash table
2289 2297 */
2290 2298 mpt->m_smp_targets = refhash_create(MPTSAS_SMP_BUCKET_COUNT,
2291 2299 mptsas_target_addr_hash, mptsas_target_addr_cmp,
2292 2300 mptsas_smp_free, sizeof (mptsas_smp_t),
2293 2301 offsetof(mptsas_smp_t, m_link), offsetof(mptsas_smp_t, m_addr),
2294 2302 KM_SLEEP);
2295 2303 mpt->m_smp_devhdl = 0xFFFF;
2296 2304
2297 2305 return (TRUE);
2298 2306 }
2299 2307
2300 2308 static void
2301 2309 mptsas_smp_teardown(mptsas_t *mpt)
2302 2310 {
2303 2311 (void) smp_hba_detach(mpt->m_dip);
2304 2312 if (mpt->m_smptran != NULL) {
2305 2313 smp_hba_tran_free(mpt->m_smptran);
2306 2314 mpt->m_smptran = NULL;
2307 2315 }
2308 2316 mpt->m_smp_devhdl = 0;
2309 2317 }
2310 2318
2311 2319 static int
2312 2320 mptsas_cache_create(mptsas_t *mpt)
2313 2321 {
2314 2322 int instance = mpt->m_instance;
2315 2323 char buf[64];
2316 2324
2317 2325 /*
2318 2326 * create kmem cache for packets
2319 2327 */
2320 2328 (void) sprintf(buf, "mptsas%d_cache", instance);
2321 2329 mpt->m_kmem_cache = kmem_cache_create(buf,
2322 2330 sizeof (struct mptsas_cmd) + scsi_pkt_size(), 8,
2323 2331 mptsas_kmem_cache_constructor, mptsas_kmem_cache_destructor,
2324 2332 NULL, (void *)mpt, NULL, 0);
2325 2333
2326 2334 if (mpt->m_kmem_cache == NULL) {
2327 2335 mptsas_log(mpt, CE_WARN, "creating kmem cache failed");
2328 2336 return (FALSE);
2329 2337 }
2330 2338
2331 2339 /*
2332 2340 * create kmem cache for extra SGL frames if SGL cannot
2333 2341 * be accomodated into main request frame.
2334 2342 */
2335 2343 (void) sprintf(buf, "mptsas%d_cache_frames", instance);
2336 2344 mpt->m_cache_frames = kmem_cache_create(buf,
2337 2345 sizeof (mptsas_cache_frames_t), 8,
2338 2346 mptsas_cache_frames_constructor, mptsas_cache_frames_destructor,
2339 2347 NULL, (void *)mpt, NULL, 0);
2340 2348
2341 2349 if (mpt->m_cache_frames == NULL) {
2342 2350 mptsas_log(mpt, CE_WARN, "creating cache for frames failed");
2343 2351 return (FALSE);
2344 2352 }
2345 2353
2346 2354 return (TRUE);
2347 2355 }
2348 2356
2349 2357 static void
2350 2358 mptsas_cache_destroy(mptsas_t *mpt)
2351 2359 {
2352 2360 /* deallocate in reverse order */
2353 2361 if (mpt->m_cache_frames) {
2354 2362 kmem_cache_destroy(mpt->m_cache_frames);
2355 2363 mpt->m_cache_frames = NULL;
2356 2364 }
2357 2365 if (mpt->m_kmem_cache) {
2358 2366 kmem_cache_destroy(mpt->m_kmem_cache);
2359 2367 mpt->m_kmem_cache = NULL;
2360 2368 }
2361 2369 }
2362 2370
2363 2371 static int
2364 2372 mptsas_power(dev_info_t *dip, int component, int level)
2365 2373 {
2366 2374 #ifndef __lock_lint
2367 2375 _NOTE(ARGUNUSED(component))
2368 2376 #endif
2369 2377 mptsas_t *mpt;
2370 2378 int rval = DDI_SUCCESS;
2371 2379 int polls = 0;
2372 2380 uint32_t ioc_status;
2373 2381
2374 2382 if (scsi_hba_iport_unit_address(dip) != 0)
2375 2383 return (DDI_SUCCESS);
2376 2384
2377 2385 mpt = ddi_get_soft_state(mptsas_state, ddi_get_instance(dip));
2378 2386 if (mpt == NULL) {
2379 2387 return (DDI_FAILURE);
2380 2388 }
2381 2389
2382 2390 mutex_enter(&mpt->m_mutex);
2383 2391
2384 2392 /*
2385 2393 * If the device is busy, don't lower its power level
2386 2394 */
2387 2395 if (mpt->m_busy && (mpt->m_power_level > level)) {
2388 2396 mutex_exit(&mpt->m_mutex);
2389 2397 return (DDI_FAILURE);
2390 2398 }
2391 2399 switch (level) {
2392 2400 case PM_LEVEL_D0:
2393 2401 NDBG11(("mptsas%d: turning power ON.", mpt->m_instance));
2394 2402 MPTSAS_POWER_ON(mpt);
2395 2403 /*
2396 2404 * Wait up to 30 seconds for IOC to come out of reset.
2397 2405 */
2398 2406 while (((ioc_status = ddi_get32(mpt->m_datap,
2399 2407 &mpt->m_reg->Doorbell)) &
2400 2408 MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_RESET) {
2401 2409 if (polls++ > 3000) {
↓ open down ↓ |
341 lines elided |
↑ open up ↑ |
2402 2410 break;
2403 2411 }
2404 2412 delay(drv_usectohz(10000));
2405 2413 }
2406 2414 /*
2407 2415 * If IOC is not in operational state, try to hard reset it.
2408 2416 */
2409 2417 if ((ioc_status & MPI2_IOC_STATE_MASK) !=
2410 2418 MPI2_IOC_STATE_OPERATIONAL) {
2411 2419 mpt->m_softstate &= ~MPTSAS_SS_MSG_UNIT_RESET;
2412 - if (mptsas_restart_ioc(mpt) == DDI_FAILURE) {
2420 + if (mptsas_reset_handler(mpt) == DDI_FAILURE) {
2413 2421 mptsas_log(mpt, CE_WARN,
2414 2422 "mptsas_power: hard reset failed");
2415 2423 mutex_exit(&mpt->m_mutex);
2416 2424 return (DDI_FAILURE);
2417 2425 }
2418 2426 }
2419 2427 mpt->m_power_level = PM_LEVEL_D0;
2420 2428 break;
2421 2429 case PM_LEVEL_D3:
2422 2430 NDBG11(("mptsas%d: turning power OFF.", mpt->m_instance));
2423 2431 MPTSAS_POWER_OFF(mpt);
2424 2432 break;
2425 2433 default:
2426 2434 mptsas_log(mpt, CE_WARN, "mptsas%d: unknown power level <%x>.",
2427 2435 mpt->m_instance, level);
2428 2436 rval = DDI_FAILURE;
2429 2437 break;
2430 2438 }
2431 2439 mutex_exit(&mpt->m_mutex);
2432 2440 return (rval);
2433 2441 }
2434 2442
2435 2443 /*
2436 2444 * Initialize configuration space and figure out which
2437 2445 * chip and revison of the chip the mpt driver is using.
2438 2446 */
2439 2447 static int
2440 2448 mptsas_config_space_init(mptsas_t *mpt)
2441 2449 {
2442 2450 NDBG0(("mptsas_config_space_init"));
2443 2451
2444 2452 if (mpt->m_config_handle != NULL)
2445 2453 return (TRUE);
2446 2454
2447 2455 if (pci_config_setup(mpt->m_dip,
2448 2456 &mpt->m_config_handle) != DDI_SUCCESS) {
2449 2457 mptsas_log(mpt, CE_WARN, "cannot map configuration space.");
2450 2458 return (FALSE);
2451 2459 }
2452 2460
2453 2461 /*
2454 2462 * This is a workaround for a XMITS ASIC bug which does not
2455 2463 * drive the CBE upper bits.
2456 2464 */
2457 2465 if (pci_config_get16(mpt->m_config_handle, PCI_CONF_STAT) &
2458 2466 PCI_STAT_PERROR) {
2459 2467 pci_config_put16(mpt->m_config_handle, PCI_CONF_STAT,
2460 2468 PCI_STAT_PERROR);
2461 2469 }
2462 2470
2463 2471 mptsas_setup_cmd_reg(mpt);
2464 2472
2465 2473 /*
2466 2474 * Get the chip device id:
2467 2475 */
2468 2476 mpt->m_devid = pci_config_get16(mpt->m_config_handle, PCI_CONF_DEVID);
2469 2477
2470 2478 /*
2471 2479 * Save the revision.
2472 2480 */
2473 2481 mpt->m_revid = pci_config_get8(mpt->m_config_handle, PCI_CONF_REVID);
2474 2482
2475 2483 /*
2476 2484 * Save the SubSystem Vendor and Device IDs
2477 2485 */
2478 2486 mpt->m_svid = pci_config_get16(mpt->m_config_handle, PCI_CONF_SUBVENID);
2479 2487 mpt->m_ssid = pci_config_get16(mpt->m_config_handle, PCI_CONF_SUBSYSID);
2480 2488
2481 2489 /*
2482 2490 * Set the latency timer to 0x40 as specified by the upa -> pci
2483 2491 * bridge chip design team. This may be done by the sparc pci
2484 2492 * bus nexus driver, but the driver should make sure the latency
2485 2493 * timer is correct for performance reasons.
2486 2494 */
2487 2495 pci_config_put8(mpt->m_config_handle, PCI_CONF_LATENCY_TIMER,
2488 2496 MPTSAS_LATENCY_TIMER);
2489 2497
2490 2498 (void) mptsas_get_pci_cap(mpt);
2491 2499 return (TRUE);
2492 2500 }
2493 2501
2494 2502 static void
2495 2503 mptsas_config_space_fini(mptsas_t *mpt)
2496 2504 {
2497 2505 if (mpt->m_config_handle != NULL) {
2498 2506 mptsas_disable_bus_master(mpt);
2499 2507 pci_config_teardown(&mpt->m_config_handle);
2500 2508 mpt->m_config_handle = NULL;
2501 2509 }
2502 2510 }
2503 2511
2504 2512 static void
2505 2513 mptsas_setup_cmd_reg(mptsas_t *mpt)
2506 2514 {
2507 2515 ushort_t cmdreg;
2508 2516
2509 2517 /*
2510 2518 * Set the command register to the needed values.
2511 2519 */
2512 2520 cmdreg = pci_config_get16(mpt->m_config_handle, PCI_CONF_COMM);
2513 2521 cmdreg |= (PCI_COMM_ME | PCI_COMM_SERR_ENABLE |
2514 2522 PCI_COMM_PARITY_DETECT | PCI_COMM_MAE);
2515 2523 cmdreg &= ~PCI_COMM_IO;
2516 2524 pci_config_put16(mpt->m_config_handle, PCI_CONF_COMM, cmdreg);
2517 2525 }
2518 2526
2519 2527 static void
2520 2528 mptsas_disable_bus_master(mptsas_t *mpt)
2521 2529 {
2522 2530 ushort_t cmdreg;
2523 2531
2524 2532 /*
2525 2533 * Clear the master enable bit in the PCI command register.
2526 2534 * This prevents any bus mastering activity like DMA.
2527 2535 */
2528 2536 cmdreg = pci_config_get16(mpt->m_config_handle, PCI_CONF_COMM);
2529 2537 cmdreg &= ~PCI_COMM_ME;
2530 2538 pci_config_put16(mpt->m_config_handle, PCI_CONF_COMM, cmdreg);
2531 2539 }
2532 2540
2533 2541 int
2534 2542 mptsas_dma_alloc(mptsas_t *mpt, mptsas_dma_alloc_state_t *dma_statep)
2535 2543 {
2536 2544 ddi_dma_attr_t attrs;
2537 2545
2538 2546 attrs = mpt->m_io_dma_attr;
2539 2547 attrs.dma_attr_sgllen = 1;
2540 2548
2541 2549 ASSERT(dma_statep != NULL);
2542 2550
2543 2551 if (mptsas_dma_addr_create(mpt, attrs, &dma_statep->handle,
2544 2552 &dma_statep->accessp, &dma_statep->memp, dma_statep->size,
2545 2553 &dma_statep->cookie) == FALSE) {
2546 2554 return (DDI_FAILURE);
2547 2555 }
2548 2556
2549 2557 return (DDI_SUCCESS);
2550 2558 }
2551 2559
2552 2560 void
2553 2561 mptsas_dma_free(mptsas_dma_alloc_state_t *dma_statep)
2554 2562 {
2555 2563 ASSERT(dma_statep != NULL);
2556 2564 mptsas_dma_addr_destroy(&dma_statep->handle, &dma_statep->accessp);
2557 2565 dma_statep->size = 0;
2558 2566 }
2559 2567
2560 2568 int
2561 2569 mptsas_do_dma(mptsas_t *mpt, uint32_t size, int var, int (*callback)())
2562 2570 {
2563 2571 ddi_dma_attr_t attrs;
2564 2572 ddi_dma_handle_t dma_handle;
2565 2573 caddr_t memp;
2566 2574 ddi_acc_handle_t accessp;
2567 2575 int rval;
2568 2576
2569 2577 ASSERT(mutex_owned(&mpt->m_mutex));
2570 2578
2571 2579 attrs = mpt->m_msg_dma_attr;
2572 2580 attrs.dma_attr_sgllen = 1;
2573 2581 attrs.dma_attr_granular = size;
2574 2582
2575 2583 if (mptsas_dma_addr_create(mpt, attrs, &dma_handle,
2576 2584 &accessp, &memp, size, NULL) == FALSE) {
2577 2585 return (DDI_FAILURE);
2578 2586 }
2579 2587
2580 2588 rval = (*callback) (mpt, memp, var, accessp);
2581 2589
2582 2590 if ((mptsas_check_dma_handle(dma_handle) != DDI_SUCCESS) ||
2583 2591 (mptsas_check_acc_handle(accessp) != DDI_SUCCESS)) {
2584 2592 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
2585 2593 rval = DDI_FAILURE;
2586 2594 }
2587 2595
2588 2596 mptsas_dma_addr_destroy(&dma_handle, &accessp);
2589 2597 return (rval);
2590 2598
2591 2599 }
2592 2600
2593 2601 static int
2594 2602 mptsas_alloc_request_frames(mptsas_t *mpt)
2595 2603 {
2596 2604 ddi_dma_attr_t frame_dma_attrs;
2597 2605 caddr_t memp;
2598 2606 ddi_dma_cookie_t cookie;
2599 2607 size_t mem_size;
2600 2608
2601 2609 /*
2602 2610 * re-alloc when it has already alloced
2603 2611 */
2604 2612 if (mpt->m_dma_req_frame_hdl)
2605 2613 mptsas_dma_addr_destroy(&mpt->m_dma_req_frame_hdl,
2606 2614 &mpt->m_acc_req_frame_hdl);
2607 2615
2608 2616 /*
2609 2617 * The size of the request frame pool is:
2610 2618 * Number of Request Frames * Request Frame Size
2611 2619 */
2612 2620 mem_size = mpt->m_max_requests * mpt->m_req_frame_size;
2613 2621
2614 2622 /*
2615 2623 * set the DMA attributes. System Request Message Frames must be
2616 2624 * aligned on a 16-byte boundry.
2617 2625 */
2618 2626 frame_dma_attrs = mpt->m_msg_dma_attr;
2619 2627 frame_dma_attrs.dma_attr_align = 16;
2620 2628 frame_dma_attrs.dma_attr_sgllen = 1;
2621 2629
2622 2630 /*
2623 2631 * allocate the request frame pool.
2624 2632 */
2625 2633 if (mptsas_dma_addr_create(mpt, frame_dma_attrs,
2626 2634 &mpt->m_dma_req_frame_hdl, &mpt->m_acc_req_frame_hdl, &memp,
2627 2635 mem_size, &cookie) == FALSE) {
2628 2636 return (DDI_FAILURE);
2629 2637 }
2630 2638
2631 2639 /*
2632 2640 * Store the request frame memory address. This chip uses this
2633 2641 * address to dma to and from the driver's frame. The second
2634 2642 * address is the address mpt uses to fill in the frame.
2635 2643 */
2636 2644 mpt->m_req_frame_dma_addr = cookie.dmac_laddress;
2637 2645 mpt->m_req_frame = memp;
2638 2646
2639 2647 /*
2640 2648 * Clear the request frame pool.
2641 2649 */
2642 2650 bzero(mpt->m_req_frame, mem_size);
2643 2651
2644 2652 return (DDI_SUCCESS);
2645 2653 }
2646 2654
2647 2655 static int
2648 2656 mptsas_alloc_sense_bufs(mptsas_t *mpt)
2649 2657 {
2650 2658 ddi_dma_attr_t sense_dma_attrs;
2651 2659 caddr_t memp;
2652 2660 ddi_dma_cookie_t cookie;
2653 2661 size_t mem_size;
2654 2662 int num_extrqsense_bufs;
2655 2663
2656 2664 ASSERT(mpt->m_extreq_sense_refcount == 0);
2657 2665
2658 2666 /*
2659 2667 * re-alloc when it has already alloced
2660 2668 */
2661 2669 if (mpt->m_dma_req_sense_hdl) {
2662 2670 rmfreemap(mpt->m_erqsense_map);
2663 2671 mptsas_dma_addr_destroy(&mpt->m_dma_req_sense_hdl,
2664 2672 &mpt->m_acc_req_sense_hdl);
2665 2673 }
2666 2674
2667 2675 /*
2668 2676 * The size of the request sense pool is:
2669 2677 * (Number of Request Frames - 2 ) * Request Sense Size +
2670 2678 * extra memory for extended sense requests.
2671 2679 */
2672 2680 mem_size = ((mpt->m_max_requests - 2) * mpt->m_req_sense_size) +
2673 2681 mptsas_extreq_sense_bufsize;
2674 2682
2675 2683 /*
2676 2684 * set the DMA attributes. ARQ buffers
2677 2685 * aligned on a 16-byte boundry.
2678 2686 */
2679 2687 sense_dma_attrs = mpt->m_msg_dma_attr;
2680 2688 sense_dma_attrs.dma_attr_align = 16;
2681 2689 sense_dma_attrs.dma_attr_sgllen = 1;
2682 2690
2683 2691 /*
2684 2692 * allocate the request sense buffer pool.
2685 2693 */
2686 2694 if (mptsas_dma_addr_create(mpt, sense_dma_attrs,
2687 2695 &mpt->m_dma_req_sense_hdl, &mpt->m_acc_req_sense_hdl, &memp,
2688 2696 mem_size, &cookie) == FALSE) {
2689 2697 return (DDI_FAILURE);
2690 2698 }
2691 2699
2692 2700 /*
2693 2701 * Store the request sense base memory address. This chip uses this
2694 2702 * address to dma the request sense data. The second
2695 2703 * address is the address mpt uses to access the data.
2696 2704 * The third is the base for the extended rqsense buffers.
2697 2705 */
2698 2706 mpt->m_req_sense_dma_addr = cookie.dmac_laddress;
2699 2707 mpt->m_req_sense = memp;
2700 2708 memp += (mpt->m_max_requests - 2) * mpt->m_req_sense_size;
2701 2709 mpt->m_extreq_sense = memp;
2702 2710
2703 2711 /*
2704 2712 * The extra memory is divided up into multiples of the base
2705 2713 * buffer size in order to allocate via rmalloc().
2706 2714 * Note that the rmallocmap cannot start at zero!
2707 2715 */
2708 2716 num_extrqsense_bufs = mptsas_extreq_sense_bufsize /
2709 2717 mpt->m_req_sense_size;
2710 2718 mpt->m_erqsense_map = rmallocmap_wait(num_extrqsense_bufs);
2711 2719 rmfree(mpt->m_erqsense_map, num_extrqsense_bufs, 1);
2712 2720
2713 2721 /*
2714 2722 * Clear the pool.
2715 2723 */
2716 2724 bzero(mpt->m_req_sense, mem_size);
2717 2725
2718 2726 return (DDI_SUCCESS);
2719 2727 }
2720 2728
2721 2729 static int
2722 2730 mptsas_alloc_reply_frames(mptsas_t *mpt)
2723 2731 {
2724 2732 ddi_dma_attr_t frame_dma_attrs;
2725 2733 caddr_t memp;
2726 2734 ddi_dma_cookie_t cookie;
2727 2735 size_t mem_size;
2728 2736
2729 2737 /*
2730 2738 * re-alloc when it has already alloced
2731 2739 */
2732 2740 if (mpt->m_dma_reply_frame_hdl) {
2733 2741 mptsas_dma_addr_destroy(&mpt->m_dma_reply_frame_hdl,
2734 2742 &mpt->m_acc_reply_frame_hdl);
2735 2743 }
2736 2744
2737 2745 /*
2738 2746 * The size of the reply frame pool is:
2739 2747 * Number of Reply Frames * Reply Frame Size
2740 2748 */
2741 2749 mem_size = mpt->m_max_replies * mpt->m_reply_frame_size;
2742 2750
2743 2751 /*
2744 2752 * set the DMA attributes. System Reply Message Frames must be
2745 2753 * aligned on a 4-byte boundry. This is the default.
2746 2754 */
2747 2755 frame_dma_attrs = mpt->m_msg_dma_attr;
2748 2756 frame_dma_attrs.dma_attr_sgllen = 1;
2749 2757
2750 2758 /*
2751 2759 * allocate the reply frame pool
2752 2760 */
2753 2761 if (mptsas_dma_addr_create(mpt, frame_dma_attrs,
2754 2762 &mpt->m_dma_reply_frame_hdl, &mpt->m_acc_reply_frame_hdl, &memp,
2755 2763 mem_size, &cookie) == FALSE) {
2756 2764 return (DDI_FAILURE);
2757 2765 }
2758 2766
2759 2767 /*
2760 2768 * Store the reply frame memory address. This chip uses this
2761 2769 * address to dma to and from the driver's frame. The second
2762 2770 * address is the address mpt uses to process the frame.
2763 2771 */
2764 2772 mpt->m_reply_frame_dma_addr = cookie.dmac_laddress;
2765 2773 mpt->m_reply_frame = memp;
2766 2774
2767 2775 /*
2768 2776 * Clear the reply frame pool.
2769 2777 */
2770 2778 bzero(mpt->m_reply_frame, mem_size);
2771 2779
2772 2780 return (DDI_SUCCESS);
2773 2781 }
2774 2782
2775 2783 static int
2776 2784 mptsas_alloc_free_queue(mptsas_t *mpt)
2777 2785 {
2778 2786 ddi_dma_attr_t frame_dma_attrs;
2779 2787 caddr_t memp;
2780 2788 ddi_dma_cookie_t cookie;
2781 2789 size_t mem_size;
2782 2790
2783 2791 /*
2784 2792 * re-alloc when it has already alloced
2785 2793 */
2786 2794 if (mpt->m_dma_free_queue_hdl) {
2787 2795 mptsas_dma_addr_destroy(&mpt->m_dma_free_queue_hdl,
2788 2796 &mpt->m_acc_free_queue_hdl);
2789 2797 }
2790 2798
2791 2799 /*
2792 2800 * The reply free queue size is:
2793 2801 * Reply Free Queue Depth * 4
2794 2802 * The "4" is the size of one 32 bit address (low part of 64-bit
2795 2803 * address)
2796 2804 */
2797 2805 mem_size = mpt->m_free_queue_depth * 4;
2798 2806
2799 2807 /*
2800 2808 * set the DMA attributes The Reply Free Queue must be aligned on a
2801 2809 * 16-byte boundry.
2802 2810 */
2803 2811 frame_dma_attrs = mpt->m_msg_dma_attr;
2804 2812 frame_dma_attrs.dma_attr_align = 16;
2805 2813 frame_dma_attrs.dma_attr_sgllen = 1;
2806 2814
2807 2815 /*
2808 2816 * allocate the reply free queue
2809 2817 */
2810 2818 if (mptsas_dma_addr_create(mpt, frame_dma_attrs,
2811 2819 &mpt->m_dma_free_queue_hdl, &mpt->m_acc_free_queue_hdl, &memp,
2812 2820 mem_size, &cookie) == FALSE) {
2813 2821 return (DDI_FAILURE);
2814 2822 }
2815 2823
2816 2824 /*
2817 2825 * Store the reply free queue memory address. This chip uses this
2818 2826 * address to read from the reply free queue. The second address
2819 2827 * is the address mpt uses to manage the queue.
2820 2828 */
2821 2829 mpt->m_free_queue_dma_addr = cookie.dmac_laddress;
2822 2830 mpt->m_free_queue = memp;
2823 2831
2824 2832 /*
2825 2833 * Clear the reply free queue memory.
2826 2834 */
2827 2835 bzero(mpt->m_free_queue, mem_size);
2828 2836
2829 2837 return (DDI_SUCCESS);
2830 2838 }
2831 2839
2832 2840 static int
2833 2841 mptsas_alloc_post_queue(mptsas_t *mpt)
2834 2842 {
2835 2843 ddi_dma_attr_t frame_dma_attrs;
2836 2844 caddr_t memp;
2837 2845 ddi_dma_cookie_t cookie;
2838 2846 size_t mem_size;
2839 2847
2840 2848 /*
2841 2849 * re-alloc when it has already alloced
2842 2850 */
2843 2851 if (mpt->m_dma_post_queue_hdl) {
2844 2852 mptsas_dma_addr_destroy(&mpt->m_dma_post_queue_hdl,
2845 2853 &mpt->m_acc_post_queue_hdl);
2846 2854 }
2847 2855
2848 2856 /*
2849 2857 * The reply descriptor post queue size is:
2850 2858 * Reply Descriptor Post Queue Depth * 8
2851 2859 * The "8" is the size of each descriptor (8 bytes or 64 bits).
2852 2860 */
2853 2861 mem_size = mpt->m_post_queue_depth * 8;
2854 2862
2855 2863 /*
2856 2864 * set the DMA attributes. The Reply Descriptor Post Queue must be
2857 2865 * aligned on a 16-byte boundry.
2858 2866 */
2859 2867 frame_dma_attrs = mpt->m_msg_dma_attr;
2860 2868 frame_dma_attrs.dma_attr_align = 16;
2861 2869 frame_dma_attrs.dma_attr_sgllen = 1;
2862 2870
2863 2871 /*
2864 2872 * allocate the reply post queue
2865 2873 */
2866 2874 if (mptsas_dma_addr_create(mpt, frame_dma_attrs,
2867 2875 &mpt->m_dma_post_queue_hdl, &mpt->m_acc_post_queue_hdl, &memp,
2868 2876 mem_size, &cookie) == FALSE) {
2869 2877 return (DDI_FAILURE);
2870 2878 }
2871 2879
2872 2880 /*
2873 2881 * Store the reply descriptor post queue memory address. This chip
2874 2882 * uses this address to write to the reply descriptor post queue. The
2875 2883 * second address is the address mpt uses to manage the queue.
2876 2884 */
2877 2885 mpt->m_post_queue_dma_addr = cookie.dmac_laddress;
2878 2886 mpt->m_post_queue = memp;
2879 2887
2880 2888 /*
2881 2889 * Clear the reply post queue memory.
2882 2890 */
2883 2891 bzero(mpt->m_post_queue, mem_size);
2884 2892
2885 2893 return (DDI_SUCCESS);
2886 2894 }
2887 2895
2888 2896 static void
2889 2897 mptsas_alloc_reply_args(mptsas_t *mpt)
2890 2898 {
2891 2899 if (mpt->m_replyh_args == NULL) {
2892 2900 mpt->m_replyh_args = kmem_zalloc(sizeof (m_replyh_arg_t) *
2893 2901 mpt->m_max_replies, KM_SLEEP);
2894 2902 }
2895 2903 }
2896 2904
2897 2905 static int
2898 2906 mptsas_alloc_extra_sgl_frame(mptsas_t *mpt, mptsas_cmd_t *cmd)
2899 2907 {
2900 2908 mptsas_cache_frames_t *frames = NULL;
2901 2909 if (cmd->cmd_extra_frames == NULL) {
2902 2910 frames = kmem_cache_alloc(mpt->m_cache_frames, KM_NOSLEEP);
2903 2911 if (frames == NULL) {
2904 2912 return (DDI_FAILURE);
2905 2913 }
2906 2914 cmd->cmd_extra_frames = frames;
2907 2915 }
2908 2916 return (DDI_SUCCESS);
2909 2917 }
2910 2918
2911 2919 static void
2912 2920 mptsas_free_extra_sgl_frame(mptsas_t *mpt, mptsas_cmd_t *cmd)
2913 2921 {
2914 2922 if (cmd->cmd_extra_frames) {
2915 2923 kmem_cache_free(mpt->m_cache_frames,
2916 2924 (void *)cmd->cmd_extra_frames);
2917 2925 cmd->cmd_extra_frames = NULL;
2918 2926 }
2919 2927 }
2920 2928
2921 2929 static void
2922 2930 mptsas_cfg_fini(mptsas_t *mpt)
2923 2931 {
2924 2932 NDBG0(("mptsas_cfg_fini"));
2925 2933 ddi_regs_map_free(&mpt->m_datap);
2926 2934 }
2927 2935
2928 2936 static void
2929 2937 mptsas_hba_fini(mptsas_t *mpt)
2930 2938 {
2931 2939 NDBG0(("mptsas_hba_fini"));
2932 2940
2933 2941 /*
2934 2942 * Free up any allocated memory
2935 2943 */
2936 2944 if (mpt->m_dma_req_frame_hdl) {
2937 2945 mptsas_dma_addr_destroy(&mpt->m_dma_req_frame_hdl,
2938 2946 &mpt->m_acc_req_frame_hdl);
2939 2947 }
2940 2948
2941 2949 if (mpt->m_dma_req_sense_hdl) {
2942 2950 rmfreemap(mpt->m_erqsense_map);
2943 2951 mptsas_dma_addr_destroy(&mpt->m_dma_req_sense_hdl,
2944 2952 &mpt->m_acc_req_sense_hdl);
2945 2953 }
2946 2954
2947 2955 if (mpt->m_dma_reply_frame_hdl) {
2948 2956 mptsas_dma_addr_destroy(&mpt->m_dma_reply_frame_hdl,
2949 2957 &mpt->m_acc_reply_frame_hdl);
2950 2958 }
2951 2959
2952 2960 if (mpt->m_dma_free_queue_hdl) {
2953 2961 mptsas_dma_addr_destroy(&mpt->m_dma_free_queue_hdl,
2954 2962 &mpt->m_acc_free_queue_hdl);
2955 2963 }
2956 2964
2957 2965 if (mpt->m_dma_post_queue_hdl) {
2958 2966 mptsas_dma_addr_destroy(&mpt->m_dma_post_queue_hdl,
2959 2967 &mpt->m_acc_post_queue_hdl);
2960 2968 }
2961 2969
2962 2970 if (mpt->m_replyh_args != NULL) {
2963 2971 kmem_free(mpt->m_replyh_args, sizeof (m_replyh_arg_t)
2964 2972 * mpt->m_max_replies);
2965 2973 }
2966 2974 }
2967 2975
2968 2976 static int
2969 2977 mptsas_name_child(dev_info_t *lun_dip, char *name, int len)
2970 2978 {
2971 2979 int lun = 0;
2972 2980 char *sas_wwn = NULL;
2973 2981 int phynum = -1;
2974 2982 int reallen = 0;
2975 2983
2976 2984 /* Get the target num */
2977 2985 lun = ddi_prop_get_int(DDI_DEV_T_ANY, lun_dip, DDI_PROP_DONTPASS,
2978 2986 LUN_PROP, 0);
2979 2987
2980 2988 if ((phynum = ddi_prop_get_int(DDI_DEV_T_ANY, lun_dip,
2981 2989 DDI_PROP_DONTPASS, "sata-phy", -1)) != -1) {
2982 2990 /*
2983 2991 * Stick in the address of form "pPHY,LUN"
2984 2992 */
2985 2993 reallen = snprintf(name, len, "p%x,%x", phynum, lun);
2986 2994 } else if (ddi_prop_lookup_string(DDI_DEV_T_ANY, lun_dip,
2987 2995 DDI_PROP_DONTPASS, SCSI_ADDR_PROP_TARGET_PORT, &sas_wwn)
2988 2996 == DDI_PROP_SUCCESS) {
2989 2997 /*
2990 2998 * Stick in the address of the form "wWWN,LUN"
2991 2999 */
2992 3000 reallen = snprintf(name, len, "%s,%x", sas_wwn, lun);
2993 3001 ddi_prop_free(sas_wwn);
2994 3002 } else {
2995 3003 return (DDI_FAILURE);
2996 3004 }
2997 3005
2998 3006 ASSERT(reallen < len);
2999 3007 if (reallen >= len) {
3000 3008 mptsas_log(0, CE_WARN, "!mptsas_get_name: name parameter "
3001 3009 "length too small, it needs to be %d bytes", reallen + 1);
3002 3010 }
3003 3011 return (DDI_SUCCESS);
3004 3012 }
3005 3013
3006 3014 /*
3007 3015 * tran_tgt_init(9E) - target device instance initialization
3008 3016 */
3009 3017 static int
3010 3018 mptsas_scsi_tgt_init(dev_info_t *hba_dip, dev_info_t *tgt_dip,
3011 3019 scsi_hba_tran_t *hba_tran, struct scsi_device *sd)
3012 3020 {
3013 3021 #ifndef __lock_lint
3014 3022 _NOTE(ARGUNUSED(hba_tran))
3015 3023 #endif
3016 3024
3017 3025 /*
3018 3026 * At this point, the scsi_device structure already exists
3019 3027 * and has been initialized.
3020 3028 *
3021 3029 * Use this function to allocate target-private data structures,
3022 3030 * if needed by this HBA. Add revised flow-control and queue
3023 3031 * properties for child here, if desired and if you can tell they
3024 3032 * support tagged queueing by now.
3025 3033 */
3026 3034 mptsas_t *mpt;
3027 3035 int lun = sd->sd_address.a_lun;
3028 3036 mdi_pathinfo_t *pip = NULL;
3029 3037 mptsas_tgt_private_t *tgt_private = NULL;
3030 3038 mptsas_target_t *ptgt = NULL;
3031 3039 char *psas_wwn = NULL;
3032 3040 mptsas_phymask_t phymask = 0;
3033 3041 uint64_t sas_wwn = 0;
3034 3042 mptsas_target_addr_t addr;
3035 3043 mpt = SDEV2MPT(sd);
3036 3044
3037 3045 ASSERT(scsi_hba_iport_unit_address(hba_dip) != 0);
3038 3046
3039 3047 NDBG0(("mptsas_scsi_tgt_init: hbadip=0x%p tgtdip=0x%p lun=%d",
3040 3048 (void *)hba_dip, (void *)tgt_dip, lun));
3041 3049
3042 3050 if (ndi_dev_is_persistent_node(tgt_dip) == 0) {
3043 3051 (void) ndi_merge_node(tgt_dip, mptsas_name_child);
3044 3052 ddi_set_name_addr(tgt_dip, NULL);
3045 3053 return (DDI_FAILURE);
3046 3054 }
3047 3055 /*
3048 3056 * phymask is 0 means the virtual port for RAID
3049 3057 */
3050 3058 phymask = (mptsas_phymask_t)ddi_prop_get_int(DDI_DEV_T_ANY, hba_dip, 0,
3051 3059 "phymask", 0);
3052 3060 if (mdi_component_is_client(tgt_dip, NULL) == MDI_SUCCESS) {
3053 3061 if ((pip = (void *)(sd->sd_private)) == NULL) {
3054 3062 /*
3055 3063 * Very bad news if this occurs. Somehow scsi_vhci has
3056 3064 * lost the pathinfo node for this target.
3057 3065 */
3058 3066 return (DDI_NOT_WELL_FORMED);
3059 3067 }
3060 3068
3061 3069 if (mdi_prop_lookup_int(pip, LUN_PROP, &lun) !=
3062 3070 DDI_PROP_SUCCESS) {
3063 3071 mptsas_log(mpt, CE_WARN, "Get lun property failed\n");
3064 3072 return (DDI_FAILURE);
3065 3073 }
3066 3074
3067 3075 if (mdi_prop_lookup_string(pip, SCSI_ADDR_PROP_TARGET_PORT,
3068 3076 &psas_wwn) == MDI_SUCCESS) {
3069 3077 if (scsi_wwnstr_to_wwn(psas_wwn, &sas_wwn)) {
3070 3078 sas_wwn = 0;
3071 3079 }
3072 3080 (void) mdi_prop_free(psas_wwn);
3073 3081 }
3074 3082 } else {
3075 3083 lun = ddi_prop_get_int(DDI_DEV_T_ANY, tgt_dip,
3076 3084 DDI_PROP_DONTPASS, LUN_PROP, 0);
3077 3085 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, tgt_dip,
3078 3086 DDI_PROP_DONTPASS, SCSI_ADDR_PROP_TARGET_PORT, &psas_wwn) ==
3079 3087 DDI_PROP_SUCCESS) {
3080 3088 if (scsi_wwnstr_to_wwn(psas_wwn, &sas_wwn)) {
3081 3089 sas_wwn = 0;
3082 3090 }
3083 3091 ddi_prop_free(psas_wwn);
3084 3092 } else {
3085 3093 sas_wwn = 0;
3086 3094 }
3087 3095 }
3088 3096
3089 3097 ASSERT((sas_wwn != 0) || (phymask != 0));
3090 3098 addr.mta_wwn = sas_wwn;
3091 3099 addr.mta_phymask = phymask;
3092 3100 mutex_enter(&mpt->m_mutex);
3093 3101 ptgt = refhash_lookup(mpt->m_targets, &addr);
3094 3102 mutex_exit(&mpt->m_mutex);
3095 3103 if (ptgt == NULL) {
3096 3104 mptsas_log(mpt, CE_WARN, "!tgt_init: target doesn't exist or "
3097 3105 "gone already! phymask:%x, saswwn %"PRIx64, phymask,
3098 3106 sas_wwn);
3099 3107 return (DDI_FAILURE);
3100 3108 }
3101 3109 if (hba_tran->tran_tgt_private == NULL) {
3102 3110 tgt_private = kmem_zalloc(sizeof (mptsas_tgt_private_t),
3103 3111 KM_SLEEP);
3104 3112 tgt_private->t_lun = lun;
3105 3113 tgt_private->t_private = ptgt;
3106 3114 hba_tran->tran_tgt_private = tgt_private;
3107 3115 }
3108 3116
3109 3117 if (mdi_component_is_client(tgt_dip, NULL) == MDI_SUCCESS) {
3110 3118 return (DDI_SUCCESS);
3111 3119 }
3112 3120 mutex_enter(&mpt->m_mutex);
3113 3121
3114 3122 if (ptgt->m_deviceinfo &
3115 3123 (MPI2_SAS_DEVICE_INFO_SATA_DEVICE |
3116 3124 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) {
3117 3125 uchar_t *inq89 = NULL;
3118 3126 int inq89_len = 0x238;
3119 3127 int reallen = 0;
3120 3128 int rval = 0;
3121 3129 struct sata_id *sid = NULL;
3122 3130 char model[SATA_ID_MODEL_LEN + 1];
3123 3131 char fw[SATA_ID_FW_LEN + 1];
3124 3132 char *vid, *pid;
3125 3133
3126 3134 mutex_exit(&mpt->m_mutex);
3127 3135 /*
3128 3136 * According SCSI/ATA Translation -2 (SAT-2) revision 01a
3129 3137 * chapter 12.4.2 VPD page 89h includes 512 bytes ATA IDENTIFY
3130 3138 * DEVICE data or ATA IDENTIFY PACKET DEVICE data.
3131 3139 */
3132 3140 inq89 = kmem_zalloc(inq89_len, KM_SLEEP);
3133 3141 rval = mptsas_inquiry(mpt, ptgt, 0, 0x89,
3134 3142 inq89, inq89_len, &reallen, 1);
3135 3143
3136 3144 if (rval != 0) {
3137 3145 if (inq89 != NULL) {
3138 3146 kmem_free(inq89, inq89_len);
3139 3147 }
3140 3148
3141 3149 mptsas_log(mpt, CE_WARN, "!mptsas request inquiry page "
3142 3150 "0x89 for SATA target:%x failed!", ptgt->m_devhdl);
3143 3151 return (DDI_SUCCESS);
3144 3152 }
3145 3153 sid = (void *)(&inq89[60]);
3146 3154
3147 3155 swab(sid->ai_model, model, SATA_ID_MODEL_LEN);
3148 3156 swab(sid->ai_fw, fw, SATA_ID_FW_LEN);
3149 3157
3150 3158 model[SATA_ID_MODEL_LEN] = 0;
3151 3159 fw[SATA_ID_FW_LEN] = 0;
3152 3160
3153 3161 sata_split_model(model, &vid, &pid);
3154 3162
3155 3163 /*
3156 3164 * override SCSA "inquiry-*" properties
3157 3165 */
3158 3166 if (vid)
3159 3167 (void) scsi_device_prop_update_inqstring(sd,
3160 3168 INQUIRY_VENDOR_ID, vid, strlen(vid));
3161 3169 if (pid)
3162 3170 (void) scsi_device_prop_update_inqstring(sd,
3163 3171 INQUIRY_PRODUCT_ID, pid, strlen(pid));
3164 3172 (void) scsi_device_prop_update_inqstring(sd,
3165 3173 INQUIRY_REVISION_ID, fw, strlen(fw));
3166 3174
3167 3175 if (inq89 != NULL) {
3168 3176 kmem_free(inq89, inq89_len);
3169 3177 }
3170 3178 } else {
3171 3179 mutex_exit(&mpt->m_mutex);
3172 3180 }
3173 3181
3174 3182 return (DDI_SUCCESS);
3175 3183 }
3176 3184 /*
3177 3185 * tran_tgt_free(9E) - target device instance deallocation
3178 3186 */
3179 3187 static void
3180 3188 mptsas_scsi_tgt_free(dev_info_t *hba_dip, dev_info_t *tgt_dip,
3181 3189 scsi_hba_tran_t *hba_tran, struct scsi_device *sd)
3182 3190 {
3183 3191 #ifndef __lock_lint
3184 3192 _NOTE(ARGUNUSED(hba_dip, tgt_dip, hba_tran, sd))
3185 3193 #endif
3186 3194
3187 3195 mptsas_tgt_private_t *tgt_private = hba_tran->tran_tgt_private;
3188 3196
3189 3197 if (tgt_private != NULL) {
3190 3198 kmem_free(tgt_private, sizeof (mptsas_tgt_private_t));
3191 3199 hba_tran->tran_tgt_private = NULL;
3192 3200 }
3193 3201 }
3194 3202
3195 3203 /*
3196 3204 * scsi_pkt handling
3197 3205 *
3198 3206 * Visible to the external world via the transport structure.
3199 3207 */
3200 3208
3201 3209 /*
3202 3210 * Notes:
3203 3211 * - transport the command to the addressed SCSI target/lun device
3204 3212 * - normal operation is to schedule the command to be transported,
3205 3213 * and return TRAN_ACCEPT if this is successful.
3206 3214 * - if NO_INTR, tran_start must poll device for command completion
3207 3215 */
3208 3216 static int
3209 3217 mptsas_scsi_start(struct scsi_address *ap, struct scsi_pkt *pkt)
3210 3218 {
3211 3219 #ifndef __lock_lint
3212 3220 _NOTE(ARGUNUSED(ap))
3213 3221 #endif
3214 3222 mptsas_t *mpt = PKT2MPT(pkt);
3215 3223 mptsas_cmd_t *cmd = PKT2CMD(pkt);
3216 3224 int rval;
3217 3225 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
3218 3226
3219 3227 NDBG1(("mptsas_scsi_start: pkt=0x%p", (void *)pkt));
3220 3228 ASSERT(ptgt);
3221 3229 if (ptgt == NULL)
3222 3230 return (TRAN_FATAL_ERROR);
3223 3231
3224 3232 /*
3225 3233 * prepare the pkt before taking mutex.
3226 3234 */
3227 3235 rval = mptsas_prepare_pkt(cmd);
3228 3236 if (rval != TRAN_ACCEPT) {
3229 3237 return (rval);
3230 3238 }
3231 3239
3232 3240 /*
3233 3241 * Send the command to target/lun, however your HBA requires it.
3234 3242 * If busy, return TRAN_BUSY; if there's some other formatting error
3235 3243 * in the packet, return TRAN_BADPKT; otherwise, fall through to the
3236 3244 * return of TRAN_ACCEPT.
3237 3245 *
3238 3246 * Remember that access to shared resources, including the mptsas_t
3239 3247 * data structure and the HBA hardware registers, must be protected
3240 3248 * with mutexes, here and everywhere.
3241 3249 *
3242 3250 * Also remember that at interrupt time, you'll get an argument
3243 3251 * to the interrupt handler which is a pointer to your mptsas_t
3244 3252 * structure; you'll have to remember which commands are outstanding
3245 3253 * and which scsi_pkt is the currently-running command so the
3246 3254 * interrupt handler can refer to the pkt to set completion
3247 3255 * status, call the target driver back through pkt_comp, etc.
3248 3256 *
3249 3257 * If the instance lock is held by other thread, don't spin to wait
3250 3258 * for it. Instead, queue the cmd and next time when the instance lock
3251 3259 * is not held, accept all the queued cmd. A extra tx_waitq is
3252 3260 * introduced to protect the queue.
3253 3261 *
3254 3262 * The polled cmd will not be queud and accepted as usual.
3255 3263 *
3256 3264 * Under the tx_waitq mutex, record whether a thread is draining
3257 3265 * the tx_waitq. An IO requesting thread that finds the instance
3258 3266 * mutex contended appends to the tx_waitq and while holding the
3259 3267 * tx_wait mutex, if the draining flag is not set, sets it and then
3260 3268 * proceeds to spin for the instance mutex. This scheme ensures that
3261 3269 * the last cmd in a burst be processed.
3262 3270 *
3263 3271 * we enable this feature only when the helper threads are enabled,
3264 3272 * at which we think the loads are heavy.
3265 3273 *
3266 3274 * per instance mutex m_tx_waitq_mutex is introduced to protect the
3267 3275 * m_tx_waitqtail, m_tx_waitq, m_tx_draining.
3268 3276 */
3269 3277
3270 3278 if (mpt->m_doneq_thread_n) {
3271 3279 if (mutex_tryenter(&mpt->m_mutex) != 0) {
3272 3280 rval = mptsas_accept_txwq_and_pkt(mpt, cmd);
3273 3281 mutex_exit(&mpt->m_mutex);
3274 3282 } else if (cmd->cmd_pkt_flags & FLAG_NOINTR) {
3275 3283 mutex_enter(&mpt->m_mutex);
3276 3284 rval = mptsas_accept_txwq_and_pkt(mpt, cmd);
3277 3285 mutex_exit(&mpt->m_mutex);
3278 3286 } else {
3279 3287 mutex_enter(&mpt->m_tx_waitq_mutex);
3280 3288 /*
3281 3289 * ptgt->m_dr_flag is protected by m_mutex or
3282 3290 * m_tx_waitq_mutex. In this case, m_tx_waitq_mutex
3283 3291 * is acquired.
3284 3292 */
3285 3293 if (ptgt->m_dr_flag == MPTSAS_DR_INTRANSITION) {
3286 3294 if (cmd->cmd_pkt_flags & FLAG_NOQUEUE) {
3287 3295 /*
3288 3296 * The command should be allowed to
3289 3297 * retry by returning TRAN_BUSY to
3290 3298 * to stall the I/O's which come from
3291 3299 * scsi_vhci since the device/path is
3292 3300 * in unstable state now.
3293 3301 */
3294 3302 mutex_exit(&mpt->m_tx_waitq_mutex);
3295 3303 return (TRAN_BUSY);
3296 3304 } else {
3297 3305 /*
3298 3306 * The device is offline, just fail the
3299 3307 * command by returning
3300 3308 * TRAN_FATAL_ERROR.
3301 3309 */
3302 3310 mutex_exit(&mpt->m_tx_waitq_mutex);
3303 3311 return (TRAN_FATAL_ERROR);
3304 3312 }
3305 3313 }
3306 3314 if (mpt->m_tx_draining) {
3307 3315 cmd->cmd_flags |= CFLAG_TXQ;
3308 3316 *mpt->m_tx_waitqtail = cmd;
3309 3317 mpt->m_tx_waitqtail = &cmd->cmd_linkp;
3310 3318 mutex_exit(&mpt->m_tx_waitq_mutex);
3311 3319 } else { /* drain the queue */
3312 3320 mpt->m_tx_draining = 1;
3313 3321 mutex_exit(&mpt->m_tx_waitq_mutex);
3314 3322 mutex_enter(&mpt->m_mutex);
3315 3323 rval = mptsas_accept_txwq_and_pkt(mpt, cmd);
3316 3324 mutex_exit(&mpt->m_mutex);
3317 3325 }
3318 3326 }
3319 3327 } else {
3320 3328 mutex_enter(&mpt->m_mutex);
3321 3329 /*
3322 3330 * ptgt->m_dr_flag is protected by m_mutex or m_tx_waitq_mutex
3323 3331 * in this case, m_mutex is acquired.
3324 3332 */
3325 3333 if (ptgt->m_dr_flag == MPTSAS_DR_INTRANSITION) {
3326 3334 if (cmd->cmd_pkt_flags & FLAG_NOQUEUE) {
3327 3335 /*
3328 3336 * commands should be allowed to retry by
3329 3337 * returning TRAN_BUSY to stall the I/O's
3330 3338 * which come from scsi_vhci since the device/
3331 3339 * path is in unstable state now.
3332 3340 */
3333 3341 mutex_exit(&mpt->m_mutex);
3334 3342 return (TRAN_BUSY);
3335 3343 } else {
3336 3344 /*
3337 3345 * The device is offline, just fail the
3338 3346 * command by returning TRAN_FATAL_ERROR.
3339 3347 */
3340 3348 mutex_exit(&mpt->m_mutex);
3341 3349 return (TRAN_FATAL_ERROR);
3342 3350 }
3343 3351 }
3344 3352 rval = mptsas_accept_pkt(mpt, cmd);
3345 3353 mutex_exit(&mpt->m_mutex);
3346 3354 }
3347 3355
3348 3356 return (rval);
3349 3357 }
3350 3358
3351 3359 /*
3352 3360 * Accept all the queued cmds(if any) before accept the current one.
3353 3361 */
3354 3362 static int
3355 3363 mptsas_accept_txwq_and_pkt(mptsas_t *mpt, mptsas_cmd_t *cmd)
3356 3364 {
3357 3365 int rval;
3358 3366 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
3359 3367
3360 3368 ASSERT(mutex_owned(&mpt->m_mutex));
3361 3369 /*
3362 3370 * The call to mptsas_accept_tx_waitq() must always be performed
3363 3371 * because that is where mpt->m_tx_draining is cleared.
3364 3372 */
3365 3373 mutex_enter(&mpt->m_tx_waitq_mutex);
3366 3374 mptsas_accept_tx_waitq(mpt);
3367 3375 mutex_exit(&mpt->m_tx_waitq_mutex);
3368 3376 /*
3369 3377 * ptgt->m_dr_flag is protected by m_mutex or m_tx_waitq_mutex
3370 3378 * in this case, m_mutex is acquired.
3371 3379 */
3372 3380 if (ptgt->m_dr_flag == MPTSAS_DR_INTRANSITION) {
3373 3381 if (cmd->cmd_pkt_flags & FLAG_NOQUEUE) {
3374 3382 /*
3375 3383 * The command should be allowed to retry by returning
3376 3384 * TRAN_BUSY to stall the I/O's which come from
3377 3385 * scsi_vhci since the device/path is in unstable state
3378 3386 * now.
3379 3387 */
3380 3388 return (TRAN_BUSY);
3381 3389 } else {
3382 3390 /*
3383 3391 * The device is offline, just fail the command by
3384 3392 * return TRAN_FATAL_ERROR.
3385 3393 */
3386 3394 return (TRAN_FATAL_ERROR);
3387 3395 }
3388 3396 }
3389 3397 rval = mptsas_accept_pkt(mpt, cmd);
3390 3398
3391 3399 return (rval);
3392 3400 }
3393 3401
3394 3402 static int
3395 3403 mptsas_accept_pkt(mptsas_t *mpt, mptsas_cmd_t *cmd)
3396 3404 {
3397 3405 int rval = TRAN_ACCEPT;
3398 3406 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
3399 3407
3400 3408 NDBG1(("mptsas_accept_pkt: cmd=0x%p", (void *)cmd));
3401 3409
3402 3410 ASSERT(mutex_owned(&mpt->m_mutex));
3403 3411
3404 3412 if ((cmd->cmd_flags & CFLAG_PREPARED) == 0) {
3405 3413 rval = mptsas_prepare_pkt(cmd);
3406 3414 if (rval != TRAN_ACCEPT) {
3407 3415 cmd->cmd_flags &= ~CFLAG_TRANFLAG;
3408 3416 return (rval);
3409 3417 }
3410 3418 }
3411 3419
3412 3420 /*
3413 3421 * reset the throttle if we were draining
3414 3422 */
3415 3423 if ((ptgt->m_t_ncmds == 0) &&
3416 3424 (ptgt->m_t_throttle == DRAIN_THROTTLE)) {
3417 3425 NDBG23(("reset throttle"));
3418 3426 ASSERT(ptgt->m_reset_delay == 0);
↓ open down ↓ |
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3419 3427 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE);
3420 3428 }
3421 3429
3422 3430 /*
3423 3431 * If HBA is being reset, the DevHandles are being re-initialized,
3424 3432 * which means that they could be invalid even if the target is still
3425 3433 * attached. Check if being reset and if DevHandle is being
3426 3434 * re-initialized. If this is the case, return BUSY so the I/O can be
3427 3435 * retried later.
3428 3436 */
3437 + mutex_enter(&mpt->m_taskmgmt_mutex);
3429 3438 if ((ptgt->m_devhdl == MPTSAS_INVALID_DEVHDL) && mpt->m_in_reset) {
3430 3439 mptsas_set_pkt_reason(mpt, cmd, CMD_RESET, STAT_BUS_RESET);
3431 3440 if (cmd->cmd_flags & CFLAG_TXQ) {
3432 3441 mptsas_doneq_add(mpt, cmd);
3433 3442 mptsas_doneq_empty(mpt);
3443 + mutex_exit(&mpt->m_taskmgmt_mutex);
3434 3444 return (rval);
3435 3445 } else {
3446 + mutex_exit(&mpt->m_taskmgmt_mutex);
3436 3447 return (TRAN_BUSY);
3437 3448 }
3438 3449 }
3450 + mutex_exit(&mpt->m_taskmgmt_mutex);
3439 3451
3440 3452 /*
3441 3453 * If device handle has already been invalidated, just
3442 3454 * fail the command. In theory, command from scsi_vhci
3443 3455 * client is impossible send down command with invalid
3444 3456 * devhdl since devhdl is set after path offline, target
3445 3457 * driver is not suppose to select a offlined path.
3446 3458 */
3447 3459 if (ptgt->m_devhdl == MPTSAS_INVALID_DEVHDL) {
3448 3460 NDBG3(("rejecting command, it might because invalid devhdl "
3449 3461 "request."));
3450 3462 mptsas_set_pkt_reason(mpt, cmd, CMD_DEV_GONE, STAT_TERMINATED);
3451 3463 if (cmd->cmd_flags & CFLAG_TXQ) {
3452 3464 mptsas_doneq_add(mpt, cmd);
3453 3465 mptsas_doneq_empty(mpt);
3454 3466 return (rval);
3455 3467 } else {
3456 3468 return (TRAN_FATAL_ERROR);
3457 3469 }
3458 3470 }
3459 3471 /*
3460 3472 * The first case is the normal case. mpt gets a command from the
3461 3473 * target driver and starts it.
3462 3474 * Since SMID 0 is reserved and the TM slot is reserved, the actual max
3463 3475 * commands is m_max_requests - 2.
3464 3476 */
3465 3477 if ((mpt->m_ncmds <= (mpt->m_max_requests - 2)) &&
3466 3478 (ptgt->m_t_throttle > HOLD_THROTTLE) &&
3467 3479 (ptgt->m_t_ncmds < ptgt->m_t_throttle) &&
3468 3480 (ptgt->m_reset_delay == 0) &&
3469 3481 (ptgt->m_t_nwait == 0) &&
3470 3482 ((cmd->cmd_pkt_flags & FLAG_NOINTR) == 0)) {
3471 3483 if (mptsas_save_cmd(mpt, cmd) == TRUE) {
3472 3484 (void) mptsas_start_cmd(mpt, cmd);
3473 3485 } else {
3474 3486 mptsas_waitq_add(mpt, cmd);
3475 3487 }
3476 3488 } else {
3477 3489 /*
3478 3490 * Add this pkt to the work queue
3479 3491 */
3480 3492 mptsas_waitq_add(mpt, cmd);
3481 3493
3482 3494 if (cmd->cmd_pkt_flags & FLAG_NOINTR) {
3483 3495 (void) mptsas_poll(mpt, cmd, MPTSAS_POLL_TIME);
3484 3496
3485 3497 /*
3486 3498 * Only flush the doneq if this is not a TM
3487 3499 * cmd. For TM cmds the flushing of the
3488 3500 * doneq will be done in those routines.
3489 3501 */
3490 3502 if ((cmd->cmd_flags & CFLAG_TM_CMD) == 0) {
3491 3503 mptsas_doneq_empty(mpt);
3492 3504 }
3493 3505 }
3494 3506 }
3495 3507 return (rval);
3496 3508 }
3497 3509
3498 3510 int
3499 3511 mptsas_save_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd)
3500 3512 {
3501 3513 mptsas_slots_t *slots = mpt->m_active;
3502 3514 uint_t slot, start_rotor;
3503 3515 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
3504 3516
3505 3517 ASSERT(MUTEX_HELD(&mpt->m_mutex));
3506 3518
3507 3519 /*
3508 3520 * Account for reserved TM request slot and reserved SMID of 0.
3509 3521 */
3510 3522 ASSERT(slots->m_n_normal == (mpt->m_max_requests - 2));
3511 3523
3512 3524 /*
3513 3525 * Find the next available slot, beginning at m_rotor. If no slot is
3514 3526 * available, we'll return FALSE to indicate that. This mechanism
3515 3527 * considers only the normal slots, not the reserved slot 0 nor the
3516 3528 * task management slot m_n_normal + 1. The rotor is left to point to
3517 3529 * the normal slot after the one we select, unless we select the last
3518 3530 * normal slot in which case it returns to slot 1.
3519 3531 */
3520 3532 start_rotor = slots->m_rotor;
3521 3533 do {
3522 3534 slot = slots->m_rotor++;
3523 3535 if (slots->m_rotor > slots->m_n_normal)
3524 3536 slots->m_rotor = 1;
3525 3537
3526 3538 if (slots->m_rotor == start_rotor)
3527 3539 break;
3528 3540 } while (slots->m_slot[slot] != NULL);
3529 3541
3530 3542 if (slots->m_slot[slot] != NULL)
3531 3543 return (FALSE);
3532 3544
3533 3545 ASSERT(slot != 0 && slot <= slots->m_n_normal);
3534 3546
3535 3547 cmd->cmd_slot = slot;
3536 3548 slots->m_slot[slot] = cmd;
3537 3549 mpt->m_ncmds++;
3538 3550
3539 3551 /*
3540 3552 * only increment per target ncmds if this is not a
3541 3553 * command that has no target associated with it (i.e. a
3542 3554 * event acknoledgment)
3543 3555 */
3544 3556 if ((cmd->cmd_flags & CFLAG_CMDIOC) == 0) {
3545 3557 /*
3546 3558 * Expiration time is set in mptsas_start_cmd
3547 3559 */
3548 3560 ptgt->m_t_ncmds++;
3549 3561 cmd->cmd_active_expiration = 0;
3550 3562 } else {
3551 3563 /*
3552 3564 * Initialize expiration time for passthrough commands,
3553 3565 */
3554 3566 cmd->cmd_active_expiration = gethrtime() +
3555 3567 (hrtime_t)cmd->cmd_pkt->pkt_time * NANOSEC;
3556 3568 }
3557 3569 return (TRUE);
3558 3570 }
3559 3571
3560 3572 /*
3561 3573 * prepare the pkt:
3562 3574 * the pkt may have been resubmitted or just reused so
3563 3575 * initialize some fields and do some checks.
3564 3576 */
3565 3577 static int
3566 3578 mptsas_prepare_pkt(mptsas_cmd_t *cmd)
3567 3579 {
3568 3580 struct scsi_pkt *pkt = CMD2PKT(cmd);
3569 3581
3570 3582 NDBG1(("mptsas_prepare_pkt: cmd=0x%p", (void *)cmd));
3571 3583
3572 3584 /*
3573 3585 * Reinitialize some fields that need it; the packet may
3574 3586 * have been resubmitted
3575 3587 */
3576 3588 pkt->pkt_reason = CMD_CMPLT;
3577 3589 pkt->pkt_state = 0;
3578 3590 pkt->pkt_statistics = 0;
3579 3591 pkt->pkt_resid = 0;
3580 3592 cmd->cmd_age = 0;
3581 3593 cmd->cmd_pkt_flags = pkt->pkt_flags;
3582 3594
3583 3595 /*
3584 3596 * zero status byte.
3585 3597 */
3586 3598 *(pkt->pkt_scbp) = 0;
3587 3599
3588 3600 if (cmd->cmd_flags & CFLAG_DMAVALID) {
3589 3601 pkt->pkt_resid = cmd->cmd_dmacount;
3590 3602
3591 3603 /*
3592 3604 * consistent packets need to be sync'ed first
3593 3605 * (only for data going out)
3594 3606 */
3595 3607 if ((cmd->cmd_flags & CFLAG_CMDIOPB) &&
3596 3608 (cmd->cmd_flags & CFLAG_DMASEND)) {
3597 3609 (void) ddi_dma_sync(cmd->cmd_dmahandle, 0, 0,
3598 3610 DDI_DMA_SYNC_FORDEV);
3599 3611 }
3600 3612 }
3601 3613
3602 3614 cmd->cmd_flags =
3603 3615 (cmd->cmd_flags & ~(CFLAG_TRANFLAG)) |
3604 3616 CFLAG_PREPARED | CFLAG_IN_TRANSPORT;
3605 3617
3606 3618 return (TRAN_ACCEPT);
3607 3619 }
3608 3620
3609 3621 /*
3610 3622 * tran_init_pkt(9E) - allocate scsi_pkt(9S) for command
3611 3623 *
3612 3624 * One of three possibilities:
3613 3625 * - allocate scsi_pkt
3614 3626 * - allocate scsi_pkt and DMA resources
3615 3627 * - allocate DMA resources to an already-allocated pkt
3616 3628 */
3617 3629 static struct scsi_pkt *
3618 3630 mptsas_scsi_init_pkt(struct scsi_address *ap, struct scsi_pkt *pkt,
3619 3631 struct buf *bp, int cmdlen, int statuslen, int tgtlen, int flags,
3620 3632 int (*callback)(), caddr_t arg)
3621 3633 {
3622 3634 mptsas_cmd_t *cmd, *new_cmd;
3623 3635 mptsas_t *mpt = ADDR2MPT(ap);
3624 3636 uint_t oldcookiec;
3625 3637 mptsas_target_t *ptgt = NULL;
3626 3638 int rval;
3627 3639 mptsas_tgt_private_t *tgt_private;
3628 3640 int kf;
3629 3641
3630 3642 kf = (callback == SLEEP_FUNC)? KM_SLEEP: KM_NOSLEEP;
3631 3643
3632 3644 tgt_private = (mptsas_tgt_private_t *)ap->a_hba_tran->
3633 3645 tran_tgt_private;
3634 3646 ASSERT(tgt_private != NULL);
3635 3647 if (tgt_private == NULL) {
3636 3648 return (NULL);
3637 3649 }
3638 3650 ptgt = tgt_private->t_private;
3639 3651 ASSERT(ptgt != NULL);
3640 3652 if (ptgt == NULL)
3641 3653 return (NULL);
3642 3654 ap->a_target = ptgt->m_devhdl;
3643 3655 ap->a_lun = tgt_private->t_lun;
3644 3656
3645 3657 ASSERT(callback == NULL_FUNC || callback == SLEEP_FUNC);
3646 3658 #ifdef MPTSAS_TEST_EXTRN_ALLOC
3647 3659 statuslen *= 100; tgtlen *= 4;
3648 3660 #endif
3649 3661 NDBG3(("mptsas_scsi_init_pkt:\n"
3650 3662 "\ttgt=%d in=0x%p bp=0x%p clen=%d slen=%d tlen=%d flags=%x",
3651 3663 ap->a_target, (void *)pkt, (void *)bp,
3652 3664 cmdlen, statuslen, tgtlen, flags));
3653 3665
3654 3666 /*
3655 3667 * Allocate the new packet.
3656 3668 */
3657 3669 if (pkt == NULL) {
3658 3670 ddi_dma_handle_t save_dma_handle;
3659 3671
3660 3672 cmd = kmem_cache_alloc(mpt->m_kmem_cache, kf);
3661 3673 if (cmd == NULL)
3662 3674 return (NULL);
3663 3675
3664 3676 save_dma_handle = cmd->cmd_dmahandle;
3665 3677 bzero(cmd, sizeof (*cmd) + scsi_pkt_size());
3666 3678 cmd->cmd_dmahandle = save_dma_handle;
3667 3679
3668 3680 pkt = (void *)((uchar_t *)cmd +
3669 3681 sizeof (struct mptsas_cmd));
3670 3682 pkt->pkt_ha_private = (opaque_t)cmd;
3671 3683 pkt->pkt_address = *ap;
3672 3684 pkt->pkt_private = (opaque_t)cmd->cmd_pkt_private;
3673 3685 pkt->pkt_scbp = (opaque_t)&cmd->cmd_scb;
3674 3686 pkt->pkt_cdbp = (opaque_t)&cmd->cmd_cdb;
3675 3687 cmd->cmd_pkt = (struct scsi_pkt *)pkt;
3676 3688 cmd->cmd_cdblen = (uchar_t)cmdlen;
3677 3689 cmd->cmd_scblen = statuslen;
3678 3690 cmd->cmd_rqslen = SENSE_LENGTH;
3679 3691 cmd->cmd_tgt_addr = ptgt;
3680 3692
3681 3693 if ((cmdlen > sizeof (cmd->cmd_cdb)) ||
3682 3694 (tgtlen > PKT_PRIV_LEN) ||
3683 3695 (statuslen > EXTCMDS_STATUS_SIZE)) {
↓ open down ↓ |
235 lines elided |
↑ open up ↑ |
3684 3696 int failure;
3685 3697
3686 3698 /*
3687 3699 * We are going to allocate external packet space which
3688 3700 * might include the sense data buffer for DMA so we
3689 3701 * need to increase the reference counter here. In a
3690 3702 * case the HBA is in reset we just simply free the
3691 3703 * allocated packet and bail out.
3692 3704 */
3693 3705 mutex_enter(&mpt->m_mutex);
3694 - if (mpt->m_in_reset) {
3706 + mutex_enter(&mpt->m_taskmgmt_mutex);
3707 + if (mpt->m_in_reset == TRUE) {
3708 + mutex_exit(&mpt->m_taskmgmt_mutex);
3695 3709 mutex_exit(&mpt->m_mutex);
3696 3710
3697 3711 cmd->cmd_flags = CFLAG_FREE;
3698 3712 kmem_cache_free(mpt->m_kmem_cache, cmd);
3699 3713 return (NULL);
3700 3714 }
3715 + mutex_exit(&mpt->m_taskmgmt_mutex);
3701 3716 mpt->m_extreq_sense_refcount++;
3702 3717 ASSERT(mpt->m_extreq_sense_refcount > 0);
3703 3718 mutex_exit(&mpt->m_mutex);
3704 3719
3705 3720 /*
3706 3721 * if extern alloc fails, all will be
3707 3722 * deallocated, including cmd
3708 3723 */
3709 3724 failure = mptsas_pkt_alloc_extern(mpt, cmd,
3710 3725 cmdlen, tgtlen, statuslen, kf);
3711 3726
3712 3727 if (failure != 0 || cmd->cmd_extrqslen == 0) {
3713 3728 /*
3714 3729 * If the external packet space allocation
3715 3730 * failed, or we didn't allocated the sense
3716 3731 * data buffer for DMA we need to decrease the
3717 3732 * reference counter.
3718 3733 */
3719 3734 mutex_enter(&mpt->m_mutex);
3720 3735 ASSERT(mpt->m_extreq_sense_refcount > 0);
3721 3736 mpt->m_extreq_sense_refcount--;
3722 3737 if (mpt->m_extreq_sense_refcount == 0)
3723 3738 cv_broadcast(
3724 3739 &mpt->m_extreq_sense_refcount_cv);
3725 3740 mutex_exit(&mpt->m_mutex);
3726 3741
3727 3742 if (failure != 0) {
3728 3743 /*
3729 3744 * if extern allocation fails, it will
3730 3745 * deallocate the new pkt as well
3731 3746 */
3732 3747 return (NULL);
3733 3748 }
3734 3749 }
3735 3750 }
3736 3751 new_cmd = cmd;
3737 3752
3738 3753 } else {
3739 3754 cmd = PKT2CMD(pkt);
3740 3755 new_cmd = NULL;
3741 3756 }
3742 3757
3743 3758
3744 3759 /* grab cmd->cmd_cookiec here as oldcookiec */
3745 3760
3746 3761 oldcookiec = cmd->cmd_cookiec;
3747 3762
3748 3763 /*
3749 3764 * If the dma was broken up into PARTIAL transfers cmd_nwin will be
3750 3765 * greater than 0 and we'll need to grab the next dma window
3751 3766 */
3752 3767 /*
3753 3768 * SLM-not doing extra command frame right now; may add later
3754 3769 */
3755 3770
3756 3771 if (cmd->cmd_nwin > 0) {
3757 3772
3758 3773 /*
3759 3774 * Make sure we havn't gone past the the total number
3760 3775 * of windows
3761 3776 */
3762 3777 if (++cmd->cmd_winindex >= cmd->cmd_nwin) {
3763 3778 return (NULL);
3764 3779 }
3765 3780 if (ddi_dma_getwin(cmd->cmd_dmahandle, cmd->cmd_winindex,
3766 3781 &cmd->cmd_dma_offset, &cmd->cmd_dma_len,
3767 3782 &cmd->cmd_cookie, &cmd->cmd_cookiec) == DDI_FAILURE) {
3768 3783 return (NULL);
3769 3784 }
3770 3785 goto get_dma_cookies;
3771 3786 }
3772 3787
3773 3788
3774 3789 if (flags & PKT_XARQ) {
3775 3790 cmd->cmd_flags |= CFLAG_XARQ;
3776 3791 }
3777 3792
3778 3793 /*
3779 3794 * DMA resource allocation. This version assumes your
3780 3795 * HBA has some sort of bus-mastering or onboard DMA capability, with a
3781 3796 * scatter-gather list of length MPTSAS_MAX_DMA_SEGS, as given in the
3782 3797 * ddi_dma_attr_t structure and passed to scsi_impl_dmaget.
3783 3798 */
3784 3799 if (bp && (bp->b_bcount != 0) &&
3785 3800 (cmd->cmd_flags & CFLAG_DMAVALID) == 0) {
3786 3801
3787 3802 int cnt, dma_flags;
3788 3803 mptti_t *dmap; /* ptr to the S/G list */
3789 3804
3790 3805 /*
3791 3806 * Set up DMA memory and position to the next DMA segment.
3792 3807 */
3793 3808 ASSERT(cmd->cmd_dmahandle != NULL);
3794 3809
3795 3810 if (bp->b_flags & B_READ) {
3796 3811 dma_flags = DDI_DMA_READ;
3797 3812 cmd->cmd_flags &= ~CFLAG_DMASEND;
3798 3813 } else {
3799 3814 dma_flags = DDI_DMA_WRITE;
3800 3815 cmd->cmd_flags |= CFLAG_DMASEND;
3801 3816 }
3802 3817 if (flags & PKT_CONSISTENT) {
3803 3818 cmd->cmd_flags |= CFLAG_CMDIOPB;
3804 3819 dma_flags |= DDI_DMA_CONSISTENT;
3805 3820 }
3806 3821
3807 3822 if (flags & PKT_DMA_PARTIAL) {
3808 3823 dma_flags |= DDI_DMA_PARTIAL;
3809 3824 }
3810 3825
3811 3826 /*
3812 3827 * workaround for byte hole issue on psycho and
3813 3828 * schizo pre 2.1
3814 3829 */
3815 3830 if ((bp->b_flags & B_READ) && ((bp->b_flags &
3816 3831 (B_PAGEIO|B_REMAPPED)) != B_PAGEIO) &&
3817 3832 ((uintptr_t)bp->b_un.b_addr & 0x7)) {
3818 3833 dma_flags |= DDI_DMA_CONSISTENT;
3819 3834 }
3820 3835
3821 3836 rval = ddi_dma_buf_bind_handle(cmd->cmd_dmahandle, bp,
3822 3837 dma_flags, callback, arg,
3823 3838 &cmd->cmd_cookie, &cmd->cmd_cookiec);
3824 3839 if (rval == DDI_DMA_PARTIAL_MAP) {
3825 3840 (void) ddi_dma_numwin(cmd->cmd_dmahandle,
3826 3841 &cmd->cmd_nwin);
3827 3842 cmd->cmd_winindex = 0;
3828 3843 (void) ddi_dma_getwin(cmd->cmd_dmahandle,
3829 3844 cmd->cmd_winindex, &cmd->cmd_dma_offset,
3830 3845 &cmd->cmd_dma_len, &cmd->cmd_cookie,
3831 3846 &cmd->cmd_cookiec);
3832 3847 } else if (rval && (rval != DDI_DMA_MAPPED)) {
3833 3848 switch (rval) {
3834 3849 case DDI_DMA_NORESOURCES:
3835 3850 bioerror(bp, 0);
3836 3851 break;
3837 3852 case DDI_DMA_BADATTR:
3838 3853 case DDI_DMA_NOMAPPING:
3839 3854 bioerror(bp, EFAULT);
3840 3855 break;
3841 3856 case DDI_DMA_TOOBIG:
3842 3857 default:
3843 3858 bioerror(bp, EINVAL);
3844 3859 break;
3845 3860 }
3846 3861 cmd->cmd_flags &= ~CFLAG_DMAVALID;
3847 3862 if (new_cmd) {
3848 3863 mptsas_scsi_destroy_pkt(ap, pkt);
3849 3864 }
3850 3865 return ((struct scsi_pkt *)NULL);
3851 3866 }
3852 3867
3853 3868 get_dma_cookies:
3854 3869 cmd->cmd_flags |= CFLAG_DMAVALID;
3855 3870 ASSERT(cmd->cmd_cookiec > 0);
3856 3871
3857 3872 if (cmd->cmd_cookiec > MPTSAS_MAX_CMD_SEGS) {
3858 3873 mptsas_log(mpt, CE_NOTE, "large cookiec received %d\n",
3859 3874 cmd->cmd_cookiec);
3860 3875 bioerror(bp, EINVAL);
3861 3876 if (new_cmd) {
3862 3877 mptsas_scsi_destroy_pkt(ap, pkt);
3863 3878 }
3864 3879 return ((struct scsi_pkt *)NULL);
3865 3880 }
3866 3881
3867 3882 /*
3868 3883 * Allocate extra SGL buffer if needed.
3869 3884 */
3870 3885 if ((cmd->cmd_cookiec > MPTSAS_MAX_FRAME_SGES64(mpt)) &&
3871 3886 (cmd->cmd_extra_frames == NULL)) {
3872 3887 if (mptsas_alloc_extra_sgl_frame(mpt, cmd) ==
3873 3888 DDI_FAILURE) {
3874 3889 mptsas_log(mpt, CE_WARN, "MPT SGL mem alloc "
3875 3890 "failed");
3876 3891 bioerror(bp, ENOMEM);
3877 3892 if (new_cmd) {
3878 3893 mptsas_scsi_destroy_pkt(ap, pkt);
3879 3894 }
3880 3895 return ((struct scsi_pkt *)NULL);
3881 3896 }
3882 3897 }
3883 3898
3884 3899 /*
3885 3900 * Always use scatter-gather transfer
3886 3901 * Use the loop below to store physical addresses of
3887 3902 * DMA segments, from the DMA cookies, into your HBA's
3888 3903 * scatter-gather list.
3889 3904 * We need to ensure we have enough kmem alloc'd
3890 3905 * for the sg entries since we are no longer using an
3891 3906 * array inside mptsas_cmd_t.
3892 3907 *
3893 3908 * We check cmd->cmd_cookiec against oldcookiec so
3894 3909 * the scatter-gather list is correctly allocated
3895 3910 */
3896 3911
3897 3912 if (oldcookiec != cmd->cmd_cookiec) {
3898 3913 if (cmd->cmd_sg != (mptti_t *)NULL) {
3899 3914 kmem_free(cmd->cmd_sg, sizeof (mptti_t) *
3900 3915 oldcookiec);
3901 3916 cmd->cmd_sg = NULL;
3902 3917 }
3903 3918 }
3904 3919
3905 3920 if (cmd->cmd_sg == (mptti_t *)NULL) {
3906 3921 cmd->cmd_sg = kmem_alloc((size_t)(sizeof (mptti_t)*
3907 3922 cmd->cmd_cookiec), kf);
3908 3923
3909 3924 if (cmd->cmd_sg == (mptti_t *)NULL) {
3910 3925 mptsas_log(mpt, CE_WARN,
3911 3926 "unable to kmem_alloc enough memory "
3912 3927 "for scatter/gather list");
3913 3928 /*
3914 3929 * if we have an ENOMEM condition we need to behave
3915 3930 * the same way as the rest of this routine
3916 3931 */
3917 3932
3918 3933 bioerror(bp, ENOMEM);
3919 3934 if (new_cmd) {
3920 3935 mptsas_scsi_destroy_pkt(ap, pkt);
3921 3936 }
3922 3937 return ((struct scsi_pkt *)NULL);
3923 3938 }
3924 3939 }
3925 3940
3926 3941 dmap = cmd->cmd_sg;
3927 3942
3928 3943 ASSERT(cmd->cmd_cookie.dmac_size != 0);
3929 3944
3930 3945 /*
3931 3946 * store the first segment into the S/G list
3932 3947 */
3933 3948 dmap->count = cmd->cmd_cookie.dmac_size;
3934 3949 dmap->addr.address64.Low = (uint32_t)
3935 3950 (cmd->cmd_cookie.dmac_laddress & 0xffffffffull);
3936 3951 dmap->addr.address64.High = (uint32_t)
3937 3952 (cmd->cmd_cookie.dmac_laddress >> 32);
3938 3953
3939 3954 /*
3940 3955 * dmacount counts the size of the dma for this window
3941 3956 * (if partial dma is being used). totaldmacount
3942 3957 * keeps track of the total amount of dma we have
3943 3958 * transferred for all the windows (needed to calculate
3944 3959 * the resid value below).
3945 3960 */
3946 3961 cmd->cmd_dmacount = cmd->cmd_cookie.dmac_size;
3947 3962 cmd->cmd_totaldmacount += cmd->cmd_cookie.dmac_size;
3948 3963
3949 3964 /*
3950 3965 * We already stored the first DMA scatter gather segment,
3951 3966 * start at 1 if we need to store more.
3952 3967 */
3953 3968 for (cnt = 1; cnt < cmd->cmd_cookiec; cnt++) {
3954 3969 /*
3955 3970 * Get next DMA cookie
3956 3971 */
3957 3972 ddi_dma_nextcookie(cmd->cmd_dmahandle,
3958 3973 &cmd->cmd_cookie);
3959 3974 dmap++;
3960 3975
3961 3976 cmd->cmd_dmacount += cmd->cmd_cookie.dmac_size;
3962 3977 cmd->cmd_totaldmacount += cmd->cmd_cookie.dmac_size;
3963 3978
3964 3979 /*
3965 3980 * store the segment parms into the S/G list
3966 3981 */
3967 3982 dmap->count = cmd->cmd_cookie.dmac_size;
3968 3983 dmap->addr.address64.Low = (uint32_t)
3969 3984 (cmd->cmd_cookie.dmac_laddress & 0xffffffffull);
3970 3985 dmap->addr.address64.High = (uint32_t)
3971 3986 (cmd->cmd_cookie.dmac_laddress >> 32);
3972 3987 }
3973 3988
3974 3989 /*
3975 3990 * If this was partially allocated we set the resid
3976 3991 * the amount of data NOT transferred in this window
3977 3992 * If there is only one window, the resid will be 0
3978 3993 */
3979 3994 pkt->pkt_resid = (bp->b_bcount - cmd->cmd_totaldmacount);
3980 3995 NDBG3(("mptsas_scsi_init_pkt: cmd_dmacount=%d.",
3981 3996 cmd->cmd_dmacount));
3982 3997 }
3983 3998 return (pkt);
3984 3999 }
3985 4000
3986 4001 /*
3987 4002 * tran_destroy_pkt(9E) - scsi_pkt(9s) deallocation
3988 4003 *
3989 4004 * Notes:
3990 4005 * - also frees DMA resources if allocated
3991 4006 * - implicit DMA synchonization
3992 4007 */
3993 4008 static void
3994 4009 mptsas_scsi_destroy_pkt(struct scsi_address *ap, struct scsi_pkt *pkt)
3995 4010 {
3996 4011 mptsas_cmd_t *cmd = PKT2CMD(pkt);
3997 4012 mptsas_t *mpt = ADDR2MPT(ap);
3998 4013
3999 4014 NDBG3(("mptsas_scsi_destroy_pkt: target=%d pkt=0x%p",
4000 4015 ap->a_target, (void *)pkt));
4001 4016
4002 4017 if (cmd->cmd_flags & CFLAG_DMAVALID) {
4003 4018 (void) ddi_dma_unbind_handle(cmd->cmd_dmahandle);
4004 4019 cmd->cmd_flags &= ~CFLAG_DMAVALID;
4005 4020 }
4006 4021
4007 4022 if (cmd->cmd_sg) {
4008 4023 kmem_free(cmd->cmd_sg, sizeof (mptti_t) * cmd->cmd_cookiec);
4009 4024 cmd->cmd_sg = NULL;
4010 4025 }
4011 4026
4012 4027 mptsas_free_extra_sgl_frame(mpt, cmd);
4013 4028
4014 4029 if ((cmd->cmd_flags &
4015 4030 (CFLAG_FREE | CFLAG_CDBEXTERN | CFLAG_PRIVEXTERN |
4016 4031 CFLAG_SCBEXTERN)) == 0) {
4017 4032 cmd->cmd_flags = CFLAG_FREE;
4018 4033 kmem_cache_free(mpt->m_kmem_cache, (void *)cmd);
4019 4034 } else {
4020 4035 boolean_t extrqslen = cmd->cmd_extrqslen != 0;
4021 4036
4022 4037 mptsas_pkt_destroy_extern(mpt, cmd);
4023 4038
4024 4039 /*
4025 4040 * If the packet had the sense data buffer for DMA allocated we
4026 4041 * need to decrease the reference counter.
4027 4042 */
4028 4043 if (extrqslen) {
4029 4044 mutex_enter(&mpt->m_mutex);
4030 4045 ASSERT(mpt->m_extreq_sense_refcount > 0);
4031 4046 mpt->m_extreq_sense_refcount--;
4032 4047 if (mpt->m_extreq_sense_refcount == 0)
4033 4048 cv_broadcast(&mpt->m_extreq_sense_refcount_cv);
4034 4049 mutex_exit(&mpt->m_mutex);
4035 4050 }
4036 4051 }
4037 4052 }
4038 4053
4039 4054 /*
4040 4055 * kmem cache constructor and destructor:
4041 4056 * When constructing, we bzero the cmd and allocate the dma handle
4042 4057 * When destructing, just free the dma handle
4043 4058 */
4044 4059 static int
4045 4060 mptsas_kmem_cache_constructor(void *buf, void *cdrarg, int kmflags)
4046 4061 {
4047 4062 mptsas_cmd_t *cmd = buf;
4048 4063 mptsas_t *mpt = cdrarg;
4049 4064 int (*callback)(caddr_t);
4050 4065
4051 4066 callback = (kmflags == KM_SLEEP)? DDI_DMA_SLEEP: DDI_DMA_DONTWAIT;
4052 4067
4053 4068 NDBG4(("mptsas_kmem_cache_constructor"));
4054 4069
4055 4070 /*
4056 4071 * allocate a dma handle
4057 4072 */
4058 4073 if ((ddi_dma_alloc_handle(mpt->m_dip, &mpt->m_io_dma_attr, callback,
4059 4074 NULL, &cmd->cmd_dmahandle)) != DDI_SUCCESS) {
4060 4075 cmd->cmd_dmahandle = NULL;
4061 4076 return (-1);
4062 4077 }
4063 4078 return (0);
4064 4079 }
4065 4080
4066 4081 static void
4067 4082 mptsas_kmem_cache_destructor(void *buf, void *cdrarg)
4068 4083 {
4069 4084 #ifndef __lock_lint
4070 4085 _NOTE(ARGUNUSED(cdrarg))
4071 4086 #endif
4072 4087 mptsas_cmd_t *cmd = buf;
4073 4088
4074 4089 NDBG4(("mptsas_kmem_cache_destructor"));
4075 4090
4076 4091 if (cmd->cmd_dmahandle) {
4077 4092 ddi_dma_free_handle(&cmd->cmd_dmahandle);
4078 4093 cmd->cmd_dmahandle = NULL;
4079 4094 }
4080 4095 }
4081 4096
4082 4097 static int
4083 4098 mptsas_cache_frames_constructor(void *buf, void *cdrarg, int kmflags)
4084 4099 {
4085 4100 mptsas_cache_frames_t *p = buf;
4086 4101 mptsas_t *mpt = cdrarg;
4087 4102 ddi_dma_attr_t frame_dma_attr;
4088 4103 size_t mem_size, alloc_len;
4089 4104 ddi_dma_cookie_t cookie;
4090 4105 uint_t ncookie;
4091 4106 int (*callback)(caddr_t) = (kmflags == KM_SLEEP)
4092 4107 ? DDI_DMA_SLEEP: DDI_DMA_DONTWAIT;
4093 4108
4094 4109 frame_dma_attr = mpt->m_msg_dma_attr;
4095 4110 frame_dma_attr.dma_attr_align = 0x10;
4096 4111 frame_dma_attr.dma_attr_sgllen = 1;
4097 4112
4098 4113 if (ddi_dma_alloc_handle(mpt->m_dip, &frame_dma_attr, callback, NULL,
4099 4114 &p->m_dma_hdl) != DDI_SUCCESS) {
4100 4115 mptsas_log(mpt, CE_WARN, "Unable to allocate dma handle for"
4101 4116 " extra SGL.");
4102 4117 return (DDI_FAILURE);
4103 4118 }
4104 4119
4105 4120 mem_size = (mpt->m_max_request_frames - 1) * mpt->m_req_frame_size;
4106 4121
4107 4122 if (ddi_dma_mem_alloc(p->m_dma_hdl, mem_size, &mpt->m_dev_acc_attr,
4108 4123 DDI_DMA_CONSISTENT, callback, NULL, (caddr_t *)&p->m_frames_addr,
4109 4124 &alloc_len, &p->m_acc_hdl) != DDI_SUCCESS) {
4110 4125 ddi_dma_free_handle(&p->m_dma_hdl);
4111 4126 p->m_dma_hdl = NULL;
4112 4127 mptsas_log(mpt, CE_WARN, "Unable to allocate dma memory for"
4113 4128 " extra SGL.");
4114 4129 return (DDI_FAILURE);
4115 4130 }
4116 4131
4117 4132 if (ddi_dma_addr_bind_handle(p->m_dma_hdl, NULL, p->m_frames_addr,
4118 4133 alloc_len, DDI_DMA_RDWR | DDI_DMA_CONSISTENT, callback, NULL,
4119 4134 &cookie, &ncookie) != DDI_DMA_MAPPED) {
4120 4135 (void) ddi_dma_mem_free(&p->m_acc_hdl);
4121 4136 ddi_dma_free_handle(&p->m_dma_hdl);
4122 4137 p->m_dma_hdl = NULL;
4123 4138 mptsas_log(mpt, CE_WARN, "Unable to bind DMA resources for"
4124 4139 " extra SGL");
4125 4140 return (DDI_FAILURE);
4126 4141 }
4127 4142
4128 4143 /*
4129 4144 * Store the SGL memory address. This chip uses this
4130 4145 * address to dma to and from the driver. The second
4131 4146 * address is the address mpt uses to fill in the SGL.
4132 4147 */
4133 4148 p->m_phys_addr = cookie.dmac_laddress;
4134 4149
4135 4150 return (DDI_SUCCESS);
4136 4151 }
4137 4152
4138 4153 static void
4139 4154 mptsas_cache_frames_destructor(void *buf, void *cdrarg)
4140 4155 {
4141 4156 #ifndef __lock_lint
4142 4157 _NOTE(ARGUNUSED(cdrarg))
4143 4158 #endif
4144 4159 mptsas_cache_frames_t *p = buf;
4145 4160 if (p->m_dma_hdl != NULL) {
4146 4161 (void) ddi_dma_unbind_handle(p->m_dma_hdl);
4147 4162 (void) ddi_dma_mem_free(&p->m_acc_hdl);
4148 4163 ddi_dma_free_handle(&p->m_dma_hdl);
4149 4164 p->m_phys_addr = NULL;
4150 4165 p->m_frames_addr = NULL;
4151 4166 p->m_dma_hdl = NULL;
4152 4167 p->m_acc_hdl = NULL;
4153 4168 }
4154 4169
4155 4170 }
4156 4171
4157 4172 /*
4158 4173 * Figure out if we need to use a different method for the request
4159 4174 * sense buffer and allocate from the map if necessary.
4160 4175 */
4161 4176 static boolean_t
4162 4177 mptsas_cmdarqsize(mptsas_t *mpt, mptsas_cmd_t *cmd, size_t senselength, int kf)
4163 4178 {
4164 4179 if (senselength > mpt->m_req_sense_size) {
4165 4180 unsigned long i;
4166 4181
4167 4182 /* Sense length is limited to an 8 bit value in MPI Spec. */
4168 4183 if (senselength > 255)
4169 4184 senselength = 255;
4170 4185 cmd->cmd_extrqschunks = (senselength +
4171 4186 (mpt->m_req_sense_size - 1))/mpt->m_req_sense_size;
4172 4187 i = (kf == KM_SLEEP ? rmalloc_wait : rmalloc)
4173 4188 (mpt->m_erqsense_map, cmd->cmd_extrqschunks);
4174 4189
4175 4190 if (i == 0)
4176 4191 return (B_FALSE);
4177 4192
4178 4193 cmd->cmd_extrqslen = (uint16_t)senselength;
4179 4194 cmd->cmd_extrqsidx = i - 1;
4180 4195 cmd->cmd_arq_buf = mpt->m_extreq_sense +
4181 4196 (cmd->cmd_extrqsidx * mpt->m_req_sense_size);
4182 4197 } else {
4183 4198 cmd->cmd_rqslen = (uchar_t)senselength;
4184 4199 }
4185 4200
4186 4201 return (B_TRUE);
4187 4202 }
4188 4203
4189 4204 /*
4190 4205 * allocate and deallocate external pkt space (ie. not part of mptsas_cmd)
4191 4206 * for non-standard length cdb, pkt_private, status areas
4192 4207 * if allocation fails, then deallocate all external space and the pkt
4193 4208 */
4194 4209 /* ARGSUSED */
4195 4210 static int
4196 4211 mptsas_pkt_alloc_extern(mptsas_t *mpt, mptsas_cmd_t *cmd,
4197 4212 int cmdlen, int tgtlen, int statuslen, int kf)
4198 4213 {
4199 4214 caddr_t cdbp, scbp, tgt;
4200 4215
4201 4216 NDBG3(("mptsas_pkt_alloc_extern: "
4202 4217 "cmd=0x%p cmdlen=%d tgtlen=%d statuslen=%d kf=%x",
4203 4218 (void *)cmd, cmdlen, tgtlen, statuslen, kf));
4204 4219
4205 4220 tgt = cdbp = scbp = NULL;
4206 4221 cmd->cmd_scblen = statuslen;
4207 4222 cmd->cmd_privlen = (uchar_t)tgtlen;
4208 4223
4209 4224 if (cmdlen > sizeof (cmd->cmd_cdb)) {
4210 4225 if ((cdbp = kmem_zalloc((size_t)cmdlen, kf)) == NULL) {
4211 4226 goto fail;
4212 4227 }
4213 4228 cmd->cmd_pkt->pkt_cdbp = (opaque_t)cdbp;
4214 4229 cmd->cmd_flags |= CFLAG_CDBEXTERN;
4215 4230 }
4216 4231 if (tgtlen > PKT_PRIV_LEN) {
4217 4232 if ((tgt = kmem_zalloc((size_t)tgtlen, kf)) == NULL) {
4218 4233 goto fail;
4219 4234 }
4220 4235 cmd->cmd_flags |= CFLAG_PRIVEXTERN;
4221 4236 cmd->cmd_pkt->pkt_private = tgt;
4222 4237 }
4223 4238 if (statuslen > EXTCMDS_STATUS_SIZE) {
4224 4239 if ((scbp = kmem_zalloc((size_t)statuslen, kf)) == NULL) {
4225 4240 goto fail;
4226 4241 }
4227 4242 cmd->cmd_flags |= CFLAG_SCBEXTERN;
4228 4243 cmd->cmd_pkt->pkt_scbp = (opaque_t)scbp;
4229 4244
4230 4245 /* allocate sense data buf for DMA */
4231 4246 if (mptsas_cmdarqsize(mpt, cmd, statuslen -
4232 4247 MPTSAS_GET_ITEM_OFF(struct scsi_arq_status, sts_sensedata),
4233 4248 kf) == B_FALSE)
4234 4249 goto fail;
4235 4250 }
4236 4251 return (0);
4237 4252 fail:
4238 4253 mptsas_pkt_destroy_extern(mpt, cmd);
4239 4254 return (1);
4240 4255 }
4241 4256
4242 4257 /*
4243 4258 * deallocate external pkt space and deallocate the pkt
4244 4259 */
4245 4260 static void
4246 4261 mptsas_pkt_destroy_extern(mptsas_t *mpt, mptsas_cmd_t *cmd)
4247 4262 {
4248 4263 NDBG3(("mptsas_pkt_destroy_extern: cmd=0x%p", (void *)cmd));
4249 4264
4250 4265 if (cmd->cmd_flags & CFLAG_FREE) {
4251 4266 mptsas_log(mpt, CE_PANIC,
4252 4267 "mptsas_pkt_destroy_extern: freeing free packet");
4253 4268 _NOTE(NOT_REACHED)
4254 4269 /* NOTREACHED */
4255 4270 }
4256 4271 if (cmd->cmd_extrqslen != 0) {
4257 4272 rmfree(mpt->m_erqsense_map, cmd->cmd_extrqschunks,
4258 4273 cmd->cmd_extrqsidx + 1);
4259 4274 }
4260 4275 if (cmd->cmd_flags & CFLAG_CDBEXTERN) {
4261 4276 kmem_free(cmd->cmd_pkt->pkt_cdbp, (size_t)cmd->cmd_cdblen);
4262 4277 }
4263 4278 if (cmd->cmd_flags & CFLAG_SCBEXTERN) {
4264 4279 kmem_free(cmd->cmd_pkt->pkt_scbp, (size_t)cmd->cmd_scblen);
4265 4280 }
4266 4281 if (cmd->cmd_flags & CFLAG_PRIVEXTERN) {
4267 4282 kmem_free(cmd->cmd_pkt->pkt_private, (size_t)cmd->cmd_privlen);
4268 4283 }
4269 4284 cmd->cmd_flags = CFLAG_FREE;
4270 4285 kmem_cache_free(mpt->m_kmem_cache, (void *)cmd);
4271 4286 }
4272 4287
4273 4288 /*
4274 4289 * tran_sync_pkt(9E) - explicit DMA synchronization
4275 4290 */
4276 4291 /*ARGSUSED*/
4277 4292 static void
4278 4293 mptsas_scsi_sync_pkt(struct scsi_address *ap, struct scsi_pkt *pkt)
4279 4294 {
4280 4295 mptsas_cmd_t *cmd = PKT2CMD(pkt);
4281 4296
4282 4297 NDBG3(("mptsas_scsi_sync_pkt: target=%d, pkt=0x%p",
4283 4298 ap->a_target, (void *)pkt));
4284 4299
4285 4300 if (cmd->cmd_dmahandle) {
4286 4301 (void) ddi_dma_sync(cmd->cmd_dmahandle, 0, 0,
4287 4302 (cmd->cmd_flags & CFLAG_DMASEND) ?
4288 4303 DDI_DMA_SYNC_FORDEV : DDI_DMA_SYNC_FORCPU);
4289 4304 }
4290 4305 }
4291 4306
4292 4307 /*
4293 4308 * tran_dmafree(9E) - deallocate DMA resources allocated for command
4294 4309 */
4295 4310 /*ARGSUSED*/
4296 4311 static void
4297 4312 mptsas_scsi_dmafree(struct scsi_address *ap, struct scsi_pkt *pkt)
4298 4313 {
4299 4314 mptsas_cmd_t *cmd = PKT2CMD(pkt);
4300 4315 mptsas_t *mpt = ADDR2MPT(ap);
4301 4316
4302 4317 NDBG3(("mptsas_scsi_dmafree: target=%d pkt=0x%p",
4303 4318 ap->a_target, (void *)pkt));
4304 4319
4305 4320 if (cmd->cmd_flags & CFLAG_DMAVALID) {
4306 4321 (void) ddi_dma_unbind_handle(cmd->cmd_dmahandle);
4307 4322 cmd->cmd_flags &= ~CFLAG_DMAVALID;
4308 4323 }
4309 4324
4310 4325 mptsas_free_extra_sgl_frame(mpt, cmd);
4311 4326 }
4312 4327
4313 4328 static void
4314 4329 mptsas_pkt_comp(struct scsi_pkt *pkt, mptsas_cmd_t *cmd)
4315 4330 {
4316 4331 if ((cmd->cmd_flags & CFLAG_CMDIOPB) &&
4317 4332 (!(cmd->cmd_flags & CFLAG_DMASEND))) {
4318 4333 (void) ddi_dma_sync(cmd->cmd_dmahandle, 0, 0,
4319 4334 DDI_DMA_SYNC_FORCPU);
4320 4335 }
4321 4336 (*pkt->pkt_comp)(pkt);
4322 4337 }
4323 4338
4324 4339 static void
4325 4340 mptsas_sge_mainframe(mptsas_cmd_t *cmd, pMpi2SCSIIORequest_t frame,
4326 4341 ddi_acc_handle_t acc_hdl, uint_t cookiec, uint32_t end_flags)
4327 4342 {
4328 4343 pMpi2SGESimple64_t sge;
4329 4344 mptti_t *dmap;
4330 4345 uint32_t flags;
4331 4346
4332 4347 dmap = cmd->cmd_sg;
4333 4348
4334 4349 sge = (pMpi2SGESimple64_t)(&frame->SGL);
4335 4350 while (cookiec--) {
4336 4351 ddi_put32(acc_hdl,
4337 4352 &sge->Address.Low, dmap->addr.address64.Low);
4338 4353 ddi_put32(acc_hdl,
4339 4354 &sge->Address.High, dmap->addr.address64.High);
4340 4355 ddi_put32(acc_hdl, &sge->FlagsLength,
4341 4356 dmap->count);
4342 4357 flags = ddi_get32(acc_hdl, &sge->FlagsLength);
4343 4358 flags |= ((uint32_t)
4344 4359 (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
4345 4360 MPI2_SGE_FLAGS_SYSTEM_ADDRESS |
4346 4361 MPI2_SGE_FLAGS_64_BIT_ADDRESSING) <<
4347 4362 MPI2_SGE_FLAGS_SHIFT);
4348 4363
4349 4364 /*
4350 4365 * If this is the last cookie, we set the flags
4351 4366 * to indicate so
4352 4367 */
4353 4368 if (cookiec == 0) {
4354 4369 flags |= end_flags;
4355 4370 }
4356 4371 if (cmd->cmd_flags & CFLAG_DMASEND) {
4357 4372 flags |= (MPI2_SGE_FLAGS_HOST_TO_IOC <<
4358 4373 MPI2_SGE_FLAGS_SHIFT);
4359 4374 } else {
4360 4375 flags |= (MPI2_SGE_FLAGS_IOC_TO_HOST <<
4361 4376 MPI2_SGE_FLAGS_SHIFT);
4362 4377 }
4363 4378 ddi_put32(acc_hdl, &sge->FlagsLength, flags);
4364 4379 dmap++;
4365 4380 sge++;
4366 4381 }
4367 4382 }
4368 4383
4369 4384 static void
4370 4385 mptsas_sge_chain(mptsas_t *mpt, mptsas_cmd_t *cmd,
4371 4386 pMpi2SCSIIORequest_t frame, ddi_acc_handle_t acc_hdl)
4372 4387 {
4373 4388 pMpi2SGESimple64_t sge;
4374 4389 pMpi2SGEChain64_t sgechain;
4375 4390 uint64_t nframe_phys_addr;
4376 4391 uint_t cookiec;
4377 4392 mptti_t *dmap;
4378 4393 uint32_t flags;
4379 4394
4380 4395 /*
4381 4396 * Save the number of entries in the DMA
4382 4397 * Scatter/Gather list
4383 4398 */
4384 4399 cookiec = cmd->cmd_cookiec;
4385 4400
4386 4401 /*
4387 4402 * Hereby we start to deal with multiple frames.
4388 4403 * The process is as follows:
4389 4404 * 1. Determine how many frames are needed for SGL element
4390 4405 * storage; Note that all frames are stored in contiguous
4391 4406 * memory space and in 64-bit DMA mode each element is
4392 4407 * 3 double-words (12 bytes) long.
4393 4408 * 2. Fill up the main frame. We need to do this separately
4394 4409 * since it contains the SCSI IO request header and needs
4395 4410 * dedicated processing. Note that the last 4 double-words
4396 4411 * of the SCSI IO header is for SGL element storage
4397 4412 * (MPI2_SGE_IO_UNION).
4398 4413 * 3. Fill the chain element in the main frame, so the DMA
4399 4414 * engine can use the following frames.
4400 4415 * 4. Enter a loop to fill the remaining frames. Note that the
4401 4416 * last frame contains no chain element. The remaining
4402 4417 * frames go into the mpt SGL buffer allocated on the fly,
4403 4418 * not immediately following the main message frame, as in
4404 4419 * Gen1.
4405 4420 * Some restrictions:
4406 4421 * 1. For 64-bit DMA, the simple element and chain element
4407 4422 * are both of 3 double-words (12 bytes) in size, even
4408 4423 * though all frames are stored in the first 4G of mem
4409 4424 * range and the higher 32-bits of the address are always 0.
4410 4425 * 2. On some controllers (like the 1064/1068), a frame can
4411 4426 * hold SGL elements with the last 1 or 2 double-words
4412 4427 * (4 or 8 bytes) un-used. On these controllers, we should
4413 4428 * recognize that there's not enough room for another SGL
4414 4429 * element and move the sge pointer to the next frame.
4415 4430 */
4416 4431 int i, j, k, l, frames, sgemax;
4417 4432 int temp;
4418 4433 uint8_t chainflags;
4419 4434 uint16_t chainlength;
4420 4435 mptsas_cache_frames_t *p;
4421 4436
4422 4437 /*
4423 4438 * Sgemax is the number of SGE's that will fit
4424 4439 * each extra frame and frames is total
4425 4440 * number of frames we'll need. 1 sge entry per
4426 4441 * frame is reseverd for the chain element thus the -1 below.
4427 4442 */
4428 4443 sgemax = ((mpt->m_req_frame_size / sizeof (MPI2_SGE_SIMPLE64))
4429 4444 - 1);
4430 4445 temp = (cookiec - (MPTSAS_MAX_FRAME_SGES64(mpt) - 1)) / sgemax;
4431 4446
4432 4447 /*
4433 4448 * A little check to see if we need to round up the number
4434 4449 * of frames we need
4435 4450 */
4436 4451 if ((cookiec - (MPTSAS_MAX_FRAME_SGES64(mpt) - 1)) - (temp *
4437 4452 sgemax) > 1) {
4438 4453 frames = (temp + 1);
4439 4454 } else {
4440 4455 frames = temp;
4441 4456 }
4442 4457 dmap = cmd->cmd_sg;
4443 4458 sge = (pMpi2SGESimple64_t)(&frame->SGL);
4444 4459
4445 4460 /*
4446 4461 * First fill in the main frame
4447 4462 */
4448 4463 j = MPTSAS_MAX_FRAME_SGES64(mpt) - 1;
4449 4464 mptsas_sge_mainframe(cmd, frame, acc_hdl, j,
4450 4465 ((uint32_t)(MPI2_SGE_FLAGS_LAST_ELEMENT) <<
4451 4466 MPI2_SGE_FLAGS_SHIFT));
4452 4467 dmap += j;
4453 4468 sge += j;
4454 4469 j++;
4455 4470
4456 4471 /*
4457 4472 * Fill in the chain element in the main frame.
4458 4473 * About calculation on ChainOffset:
4459 4474 * 1. Struct msg_scsi_io_request has 4 double-words (16 bytes)
4460 4475 * in the end reserved for SGL element storage
4461 4476 * (MPI2_SGE_IO_UNION); we should count it in our
4462 4477 * calculation. See its definition in the header file.
4463 4478 * 2. Constant j is the counter of the current SGL element
4464 4479 * that will be processed, and (j - 1) is the number of
4465 4480 * SGL elements that have been processed (stored in the
4466 4481 * main frame).
4467 4482 * 3. ChainOffset value should be in units of double-words (4
4468 4483 * bytes) so the last value should be divided by 4.
4469 4484 */
4470 4485 ddi_put8(acc_hdl, &frame->ChainOffset,
4471 4486 (sizeof (MPI2_SCSI_IO_REQUEST) -
4472 4487 sizeof (MPI2_SGE_IO_UNION) +
4473 4488 (j - 1) * sizeof (MPI2_SGE_SIMPLE64)) >> 2);
4474 4489 sgechain = (pMpi2SGEChain64_t)sge;
4475 4490 chainflags = (MPI2_SGE_FLAGS_CHAIN_ELEMENT |
4476 4491 MPI2_SGE_FLAGS_SYSTEM_ADDRESS |
4477 4492 MPI2_SGE_FLAGS_64_BIT_ADDRESSING);
4478 4493 ddi_put8(acc_hdl, &sgechain->Flags, chainflags);
4479 4494
4480 4495 /*
4481 4496 * The size of the next frame is the accurate size of space
4482 4497 * (in bytes) used to store the SGL elements. j is the counter
4483 4498 * of SGL elements. (j - 1) is the number of SGL elements that
4484 4499 * have been processed (stored in frames).
4485 4500 */
4486 4501 if (frames >= 2) {
4487 4502 ASSERT(mpt->m_req_frame_size >= sizeof (MPI2_SGE_SIMPLE64));
4488 4503 chainlength = mpt->m_req_frame_size /
4489 4504 sizeof (MPI2_SGE_SIMPLE64) *
4490 4505 sizeof (MPI2_SGE_SIMPLE64);
4491 4506 } else {
4492 4507 chainlength = ((cookiec - (j - 1)) *
4493 4508 sizeof (MPI2_SGE_SIMPLE64));
4494 4509 }
4495 4510
4496 4511 p = cmd->cmd_extra_frames;
4497 4512
4498 4513 ddi_put16(acc_hdl, &sgechain->Length, chainlength);
4499 4514 ddi_put32(acc_hdl, &sgechain->Address.Low, p->m_phys_addr);
4500 4515 ddi_put32(acc_hdl, &sgechain->Address.High, p->m_phys_addr >> 32);
4501 4516
4502 4517 /*
4503 4518 * If there are more than 2 frames left we have to
4504 4519 * fill in the next chain offset to the location of
4505 4520 * the chain element in the next frame.
4506 4521 * sgemax is the number of simple elements in an extra
4507 4522 * frame. Note that the value NextChainOffset should be
4508 4523 * in double-words (4 bytes).
4509 4524 */
4510 4525 if (frames >= 2) {
4511 4526 ddi_put8(acc_hdl, &sgechain->NextChainOffset,
4512 4527 (sgemax * sizeof (MPI2_SGE_SIMPLE64)) >> 2);
4513 4528 } else {
4514 4529 ddi_put8(acc_hdl, &sgechain->NextChainOffset, 0);
4515 4530 }
4516 4531
4517 4532 /*
4518 4533 * Jump to next frame;
4519 4534 * Starting here, chain buffers go into the per command SGL.
4520 4535 * This buffer is allocated when chain buffers are needed.
4521 4536 */
4522 4537 sge = (pMpi2SGESimple64_t)p->m_frames_addr;
4523 4538 i = cookiec;
4524 4539
4525 4540 /*
4526 4541 * Start filling in frames with SGE's. If we
4527 4542 * reach the end of frame and still have SGE's
4528 4543 * to fill we need to add a chain element and
4529 4544 * use another frame. j will be our counter
4530 4545 * for what cookie we are at and i will be
4531 4546 * the total cookiec. k is the current frame
4532 4547 */
4533 4548 for (k = 1; k <= frames; k++) {
4534 4549 for (l = 1; (l <= (sgemax + 1)) && (j <= i); j++, l++) {
4535 4550
4536 4551 /*
4537 4552 * If we have reached the end of frame
4538 4553 * and we have more SGE's to fill in
4539 4554 * we have to fill the final entry
4540 4555 * with a chain element and then
4541 4556 * continue to the next frame
4542 4557 */
4543 4558 if ((l == (sgemax + 1)) && (k != frames)) {
4544 4559 sgechain = (pMpi2SGEChain64_t)sge;
4545 4560 j--;
4546 4561 chainflags = (
4547 4562 MPI2_SGE_FLAGS_CHAIN_ELEMENT |
4548 4563 MPI2_SGE_FLAGS_SYSTEM_ADDRESS |
4549 4564 MPI2_SGE_FLAGS_64_BIT_ADDRESSING);
4550 4565 ddi_put8(p->m_acc_hdl,
4551 4566 &sgechain->Flags, chainflags);
4552 4567 /*
4553 4568 * k is the frame counter and (k + 1)
4554 4569 * is the number of the next frame.
4555 4570 * Note that frames are in contiguous
4556 4571 * memory space.
4557 4572 */
4558 4573 nframe_phys_addr = p->m_phys_addr +
4559 4574 (mpt->m_req_frame_size * k);
4560 4575 ddi_put32(p->m_acc_hdl,
4561 4576 &sgechain->Address.Low,
4562 4577 nframe_phys_addr);
4563 4578 ddi_put32(p->m_acc_hdl,
4564 4579 &sgechain->Address.High,
4565 4580 nframe_phys_addr >> 32);
4566 4581
4567 4582 /*
4568 4583 * If there are more than 2 frames left
4569 4584 * we have to next chain offset to
4570 4585 * the location of the chain element
4571 4586 * in the next frame and fill in the
4572 4587 * length of the next chain
4573 4588 */
4574 4589 if ((frames - k) >= 2) {
4575 4590 ddi_put8(p->m_acc_hdl,
4576 4591 &sgechain->NextChainOffset,
4577 4592 (sgemax *
4578 4593 sizeof (MPI2_SGE_SIMPLE64))
4579 4594 >> 2);
4580 4595 ddi_put16(p->m_acc_hdl,
4581 4596 &sgechain->Length,
4582 4597 mpt->m_req_frame_size /
4583 4598 sizeof (MPI2_SGE_SIMPLE64) *
4584 4599 sizeof (MPI2_SGE_SIMPLE64));
4585 4600 } else {
4586 4601 /*
4587 4602 * This is the last frame. Set
4588 4603 * the NextChainOffset to 0 and
4589 4604 * Length is the total size of
4590 4605 * all remaining simple elements
4591 4606 */
4592 4607 ddi_put8(p->m_acc_hdl,
4593 4608 &sgechain->NextChainOffset,
4594 4609 0);
4595 4610 ddi_put16(p->m_acc_hdl,
4596 4611 &sgechain->Length,
4597 4612 (cookiec - j) *
4598 4613 sizeof (MPI2_SGE_SIMPLE64));
4599 4614 }
4600 4615
4601 4616 /* Jump to the next frame */
4602 4617 sge = (pMpi2SGESimple64_t)
4603 4618 ((char *)p->m_frames_addr +
4604 4619 (int)mpt->m_req_frame_size * k);
4605 4620
4606 4621 continue;
4607 4622 }
4608 4623
4609 4624 ddi_put32(p->m_acc_hdl,
4610 4625 &sge->Address.Low,
4611 4626 dmap->addr.address64.Low);
4612 4627 ddi_put32(p->m_acc_hdl,
4613 4628 &sge->Address.High,
4614 4629 dmap->addr.address64.High);
4615 4630 ddi_put32(p->m_acc_hdl,
4616 4631 &sge->FlagsLength, dmap->count);
4617 4632 flags = ddi_get32(p->m_acc_hdl,
4618 4633 &sge->FlagsLength);
4619 4634 flags |= ((uint32_t)(
4620 4635 MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
4621 4636 MPI2_SGE_FLAGS_SYSTEM_ADDRESS |
4622 4637 MPI2_SGE_FLAGS_64_BIT_ADDRESSING) <<
4623 4638 MPI2_SGE_FLAGS_SHIFT);
4624 4639
4625 4640 /*
4626 4641 * If we are at the end of the frame and
4627 4642 * there is another frame to fill in
4628 4643 * we set the last simple element as last
4629 4644 * element
4630 4645 */
4631 4646 if ((l == sgemax) && (k != frames)) {
4632 4647 flags |= ((uint32_t)
4633 4648 (MPI2_SGE_FLAGS_LAST_ELEMENT) <<
4634 4649 MPI2_SGE_FLAGS_SHIFT);
4635 4650 }
4636 4651
4637 4652 /*
4638 4653 * If this is the final cookie we
4639 4654 * indicate it by setting the flags
4640 4655 */
4641 4656 if (j == i) {
4642 4657 flags |= ((uint32_t)
4643 4658 (MPI2_SGE_FLAGS_LAST_ELEMENT |
4644 4659 MPI2_SGE_FLAGS_END_OF_BUFFER |
4645 4660 MPI2_SGE_FLAGS_END_OF_LIST) <<
4646 4661 MPI2_SGE_FLAGS_SHIFT);
4647 4662 }
4648 4663 if (cmd->cmd_flags & CFLAG_DMASEND) {
4649 4664 flags |=
4650 4665 (MPI2_SGE_FLAGS_HOST_TO_IOC <<
4651 4666 MPI2_SGE_FLAGS_SHIFT);
4652 4667 } else {
4653 4668 flags |=
4654 4669 (MPI2_SGE_FLAGS_IOC_TO_HOST <<
4655 4670 MPI2_SGE_FLAGS_SHIFT);
4656 4671 }
4657 4672 ddi_put32(p->m_acc_hdl,
4658 4673 &sge->FlagsLength, flags);
4659 4674 dmap++;
4660 4675 sge++;
4661 4676 }
4662 4677 }
4663 4678
4664 4679 /*
4665 4680 * Sync DMA with the chain buffers that were just created
4666 4681 */
4667 4682 (void) ddi_dma_sync(p->m_dma_hdl, 0, 0, DDI_DMA_SYNC_FORDEV);
4668 4683 }
4669 4684
4670 4685 static void
4671 4686 mptsas_ieee_sge_mainframe(mptsas_cmd_t *cmd, pMpi2SCSIIORequest_t frame,
4672 4687 ddi_acc_handle_t acc_hdl, uint_t cookiec, uint8_t end_flag)
4673 4688 {
4674 4689 pMpi2IeeeSgeSimple64_t ieeesge;
4675 4690 mptti_t *dmap;
4676 4691 uint8_t flags;
4677 4692
4678 4693 dmap = cmd->cmd_sg;
4679 4694
4680 4695 NDBG1(("mptsas_ieee_sge_mainframe: cookiec=%d, %s", cookiec,
4681 4696 cmd->cmd_flags & CFLAG_DMASEND?"Out":"In"));
4682 4697
4683 4698 ieeesge = (pMpi2IeeeSgeSimple64_t)(&frame->SGL);
4684 4699 while (cookiec--) {
4685 4700 ddi_put32(acc_hdl,
4686 4701 &ieeesge->Address.Low, dmap->addr.address64.Low);
4687 4702 ddi_put32(acc_hdl,
4688 4703 &ieeesge->Address.High, dmap->addr.address64.High);
4689 4704 ddi_put32(acc_hdl, &ieeesge->Length,
4690 4705 dmap->count);
4691 4706 NDBG1(("mptsas_ieee_sge_mainframe: len=%d", dmap->count));
4692 4707 flags = (MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
4693 4708 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR);
4694 4709
4695 4710 /*
4696 4711 * If this is the last cookie, we set the flags
4697 4712 * to indicate so
4698 4713 */
4699 4714 if (cookiec == 0) {
4700 4715 flags |= end_flag;
4701 4716 }
4702 4717
4703 4718 ddi_put8(acc_hdl, &ieeesge->Flags, flags);
4704 4719 dmap++;
4705 4720 ieeesge++;
4706 4721 }
4707 4722 }
4708 4723
4709 4724 static void
4710 4725 mptsas_ieee_sge_chain(mptsas_t *mpt, mptsas_cmd_t *cmd,
4711 4726 pMpi2SCSIIORequest_t frame, ddi_acc_handle_t acc_hdl)
4712 4727 {
4713 4728 pMpi2IeeeSgeSimple64_t ieeesge;
4714 4729 pMpi25IeeeSgeChain64_t ieeesgechain;
4715 4730 uint64_t nframe_phys_addr;
4716 4731 uint_t cookiec;
4717 4732 mptti_t *dmap;
4718 4733 uint8_t flags;
4719 4734
4720 4735 /*
4721 4736 * Save the number of entries in the DMA
4722 4737 * Scatter/Gather list
4723 4738 */
4724 4739 cookiec = cmd->cmd_cookiec;
4725 4740
4726 4741 NDBG1(("mptsas_ieee_sge_chain: cookiec=%d", cookiec));
4727 4742
4728 4743 /*
4729 4744 * Hereby we start to deal with multiple frames.
4730 4745 * The process is as follows:
4731 4746 * 1. Determine how many frames are needed for SGL element
4732 4747 * storage; Note that all frames are stored in contiguous
4733 4748 * memory space and in 64-bit DMA mode each element is
4734 4749 * 4 double-words (16 bytes) long.
4735 4750 * 2. Fill up the main frame. We need to do this separately
4736 4751 * since it contains the SCSI IO request header and needs
4737 4752 * dedicated processing. Note that the last 4 double-words
4738 4753 * of the SCSI IO header is for SGL element storage
4739 4754 * (MPI2_SGE_IO_UNION).
4740 4755 * 3. Fill the chain element in the main frame, so the DMA
4741 4756 * engine can use the following frames.
4742 4757 * 4. Enter a loop to fill the remaining frames. Note that the
4743 4758 * last frame contains no chain element. The remaining
4744 4759 * frames go into the mpt SGL buffer allocated on the fly,
4745 4760 * not immediately following the main message frame, as in
4746 4761 * Gen1.
4747 4762 * Restrictions:
4748 4763 * For 64-bit DMA, the simple element and chain element
4749 4764 * are both of 4 double-words (16 bytes) in size, even
4750 4765 * though all frames are stored in the first 4G of mem
4751 4766 * range and the higher 32-bits of the address are always 0.
4752 4767 */
4753 4768 int i, j, k, l, frames, sgemax;
4754 4769 int temp;
4755 4770 uint8_t chainflags;
4756 4771 uint32_t chainlength;
4757 4772 mptsas_cache_frames_t *p;
4758 4773
4759 4774 /*
4760 4775 * Sgemax is the number of SGE's that will fit
4761 4776 * each extra frame and frames is total
4762 4777 * number of frames we'll need. 1 sge entry per
4763 4778 * frame is reseverd for the chain element thus the -1 below.
4764 4779 */
4765 4780 sgemax = ((mpt->m_req_frame_size / sizeof (MPI2_IEEE_SGE_SIMPLE64))
4766 4781 - 1);
4767 4782 temp = (cookiec - (MPTSAS_MAX_FRAME_SGES64(mpt) - 1)) / sgemax;
4768 4783
4769 4784 /*
4770 4785 * A little check to see if we need to round up the number
4771 4786 * of frames we need
4772 4787 */
4773 4788 if ((cookiec - (MPTSAS_MAX_FRAME_SGES64(mpt) - 1)) - (temp *
4774 4789 sgemax) > 1) {
4775 4790 frames = (temp + 1);
4776 4791 } else {
4777 4792 frames = temp;
4778 4793 }
4779 4794 NDBG1(("mptsas_ieee_sge_chain: temp=%d, frames=%d", temp, frames));
4780 4795 dmap = cmd->cmd_sg;
4781 4796 ieeesge = (pMpi2IeeeSgeSimple64_t)(&frame->SGL);
4782 4797
4783 4798 /*
4784 4799 * First fill in the main frame
4785 4800 */
4786 4801 j = MPTSAS_MAX_FRAME_SGES64(mpt) - 1;
4787 4802 mptsas_ieee_sge_mainframe(cmd, frame, acc_hdl, j, 0);
4788 4803 dmap += j;
4789 4804 ieeesge += j;
4790 4805 j++;
4791 4806
4792 4807 /*
4793 4808 * Fill in the chain element in the main frame.
4794 4809 * About calculation on ChainOffset:
4795 4810 * 1. Struct msg_scsi_io_request has 4 double-words (16 bytes)
4796 4811 * in the end reserved for SGL element storage
4797 4812 * (MPI2_SGE_IO_UNION); we should count it in our
4798 4813 * calculation. See its definition in the header file.
4799 4814 * 2. Constant j is the counter of the current SGL element
4800 4815 * that will be processed, and (j - 1) is the number of
4801 4816 * SGL elements that have been processed (stored in the
4802 4817 * main frame).
4803 4818 * 3. ChainOffset value should be in units of quad-words (16
4804 4819 * bytes) so the last value should be divided by 16.
4805 4820 */
4806 4821 ddi_put8(acc_hdl, &frame->ChainOffset,
4807 4822 (sizeof (MPI2_SCSI_IO_REQUEST) -
4808 4823 sizeof (MPI2_SGE_IO_UNION) +
4809 4824 (j - 1) * sizeof (MPI2_IEEE_SGE_SIMPLE64)) >> 4);
4810 4825 ieeesgechain = (pMpi25IeeeSgeChain64_t)ieeesge;
4811 4826 chainflags = (MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT |
4812 4827 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR);
4813 4828 ddi_put8(acc_hdl, &ieeesgechain->Flags, chainflags);
4814 4829
4815 4830 /*
4816 4831 * The size of the next frame is the accurate size of space
4817 4832 * (in bytes) used to store the SGL elements. j is the counter
4818 4833 * of SGL elements. (j - 1) is the number of SGL elements that
4819 4834 * have been processed (stored in frames).
4820 4835 */
4821 4836 if (frames >= 2) {
4822 4837 ASSERT(mpt->m_req_frame_size >=
4823 4838 sizeof (MPI2_IEEE_SGE_SIMPLE64));
4824 4839 chainlength = mpt->m_req_frame_size /
4825 4840 sizeof (MPI2_IEEE_SGE_SIMPLE64) *
4826 4841 sizeof (MPI2_IEEE_SGE_SIMPLE64);
4827 4842 } else {
4828 4843 chainlength = ((cookiec - (j - 1)) *
4829 4844 sizeof (MPI2_IEEE_SGE_SIMPLE64));
4830 4845 }
4831 4846
4832 4847 p = cmd->cmd_extra_frames;
4833 4848
4834 4849 ddi_put32(acc_hdl, &ieeesgechain->Length, chainlength);
4835 4850 ddi_put32(acc_hdl, &ieeesgechain->Address.Low, p->m_phys_addr);
4836 4851 ddi_put32(acc_hdl, &ieeesgechain->Address.High, p->m_phys_addr >> 32);
4837 4852
4838 4853 /*
4839 4854 * If there are more than 2 frames left we have to
4840 4855 * fill in the next chain offset to the location of
4841 4856 * the chain element in the next frame.
4842 4857 * sgemax is the number of simple elements in an extra
4843 4858 * frame. Note that the value NextChainOffset should be
4844 4859 * in double-words (4 bytes).
4845 4860 */
4846 4861 if (frames >= 2) {
4847 4862 ddi_put8(acc_hdl, &ieeesgechain->NextChainOffset,
4848 4863 (sgemax * sizeof (MPI2_IEEE_SGE_SIMPLE64)) >> 4);
4849 4864 } else {
4850 4865 ddi_put8(acc_hdl, &ieeesgechain->NextChainOffset, 0);
4851 4866 }
4852 4867
4853 4868 /*
4854 4869 * Jump to next frame;
4855 4870 * Starting here, chain buffers go into the per command SGL.
4856 4871 * This buffer is allocated when chain buffers are needed.
4857 4872 */
4858 4873 ieeesge = (pMpi2IeeeSgeSimple64_t)p->m_frames_addr;
4859 4874 i = cookiec;
4860 4875
4861 4876 /*
4862 4877 * Start filling in frames with SGE's. If we
4863 4878 * reach the end of frame and still have SGE's
4864 4879 * to fill we need to add a chain element and
4865 4880 * use another frame. j will be our counter
4866 4881 * for what cookie we are at and i will be
4867 4882 * the total cookiec. k is the current frame
4868 4883 */
4869 4884 for (k = 1; k <= frames; k++) {
4870 4885 for (l = 1; (l <= (sgemax + 1)) && (j <= i); j++, l++) {
4871 4886
4872 4887 /*
4873 4888 * If we have reached the end of frame
4874 4889 * and we have more SGE's to fill in
4875 4890 * we have to fill the final entry
4876 4891 * with a chain element and then
4877 4892 * continue to the next frame
4878 4893 */
4879 4894 if ((l == (sgemax + 1)) && (k != frames)) {
4880 4895 ieeesgechain = (pMpi25IeeeSgeChain64_t)ieeesge;
4881 4896 j--;
4882 4897 chainflags =
4883 4898 MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT |
4884 4899 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
4885 4900 ddi_put8(p->m_acc_hdl,
4886 4901 &ieeesgechain->Flags, chainflags);
4887 4902 /*
4888 4903 * k is the frame counter and (k + 1)
4889 4904 * is the number of the next frame.
4890 4905 * Note that frames are in contiguous
4891 4906 * memory space.
4892 4907 */
4893 4908 nframe_phys_addr = p->m_phys_addr +
4894 4909 (mpt->m_req_frame_size * k);
4895 4910 ddi_put32(p->m_acc_hdl,
4896 4911 &ieeesgechain->Address.Low,
4897 4912 nframe_phys_addr);
4898 4913 ddi_put32(p->m_acc_hdl,
4899 4914 &ieeesgechain->Address.High,
4900 4915 nframe_phys_addr >> 32);
4901 4916
4902 4917 /*
4903 4918 * If there are more than 2 frames left
4904 4919 * we have to next chain offset to
4905 4920 * the location of the chain element
4906 4921 * in the next frame and fill in the
4907 4922 * length of the next chain
4908 4923 */
4909 4924 if ((frames - k) >= 2) {
4910 4925 ddi_put8(p->m_acc_hdl,
4911 4926 &ieeesgechain->NextChainOffset,
4912 4927 (sgemax *
4913 4928 sizeof (MPI2_IEEE_SGE_SIMPLE64))
4914 4929 >> 4);
4915 4930 ASSERT(mpt->m_req_frame_size >=
4916 4931 sizeof (MPI2_IEEE_SGE_SIMPLE64));
4917 4932 ddi_put32(p->m_acc_hdl,
4918 4933 &ieeesgechain->Length,
4919 4934 mpt->m_req_frame_size /
4920 4935 sizeof (MPI2_IEEE_SGE_SIMPLE64) *
4921 4936 sizeof (MPI2_IEEE_SGE_SIMPLE64));
4922 4937 } else {
4923 4938 /*
4924 4939 * This is the last frame. Set
4925 4940 * the NextChainOffset to 0 and
4926 4941 * Length is the total size of
4927 4942 * all remaining simple elements
4928 4943 */
4929 4944 ddi_put8(p->m_acc_hdl,
4930 4945 &ieeesgechain->NextChainOffset,
4931 4946 0);
4932 4947 ddi_put32(p->m_acc_hdl,
4933 4948 &ieeesgechain->Length,
4934 4949 (cookiec - j) *
4935 4950 sizeof (MPI2_IEEE_SGE_SIMPLE64));
4936 4951 }
4937 4952
4938 4953 /* Jump to the next frame */
4939 4954 ieeesge = (pMpi2IeeeSgeSimple64_t)
4940 4955 ((char *)p->m_frames_addr +
4941 4956 (int)mpt->m_req_frame_size * k);
4942 4957
4943 4958 continue;
4944 4959 }
4945 4960
4946 4961 ddi_put32(p->m_acc_hdl,
4947 4962 &ieeesge->Address.Low,
4948 4963 dmap->addr.address64.Low);
4949 4964 ddi_put32(p->m_acc_hdl,
4950 4965 &ieeesge->Address.High,
4951 4966 dmap->addr.address64.High);
4952 4967 ddi_put32(p->m_acc_hdl,
4953 4968 &ieeesge->Length, dmap->count);
4954 4969 flags = (MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
4955 4970 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR);
4956 4971
4957 4972 /*
4958 4973 * If we are at the end of the frame and
4959 4974 * there is another frame to fill in
4960 4975 * do we need to do anything?
4961 4976 * if ((l == sgemax) && (k != frames)) {
4962 4977 * }
4963 4978 */
4964 4979
4965 4980 /*
4966 4981 * If this is the final cookie set end of list.
4967 4982 */
4968 4983 if (j == i) {
4969 4984 flags |= MPI25_IEEE_SGE_FLAGS_END_OF_LIST;
4970 4985 }
4971 4986
4972 4987 ddi_put8(p->m_acc_hdl, &ieeesge->Flags, flags);
4973 4988 dmap++;
4974 4989 ieeesge++;
4975 4990 }
4976 4991 }
4977 4992
4978 4993 /*
4979 4994 * Sync DMA with the chain buffers that were just created
4980 4995 */
4981 4996 (void) ddi_dma_sync(p->m_dma_hdl, 0, 0, DDI_DMA_SYNC_FORDEV);
4982 4997 }
4983 4998
4984 4999 static void
4985 5000 mptsas_sge_setup(mptsas_t *mpt, mptsas_cmd_t *cmd, uint32_t *control,
4986 5001 pMpi2SCSIIORequest_t frame, ddi_acc_handle_t acc_hdl)
4987 5002 {
4988 5003 ASSERT(cmd->cmd_flags & CFLAG_DMAVALID);
4989 5004
4990 5005 NDBG1(("mptsas_sge_setup: cookiec=%d", cmd->cmd_cookiec));
4991 5006
4992 5007 /*
4993 5008 * Set read/write bit in control.
4994 5009 */
4995 5010 if (cmd->cmd_flags & CFLAG_DMASEND) {
4996 5011 *control |= MPI2_SCSIIO_CONTROL_WRITE;
4997 5012 } else {
4998 5013 *control |= MPI2_SCSIIO_CONTROL_READ;
4999 5014 }
5000 5015
5001 5016 ddi_put32(acc_hdl, &frame->DataLength, cmd->cmd_dmacount);
5002 5017
5003 5018 /*
5004 5019 * We have 4 cases here. First where we can fit all the
5005 5020 * SG elements into the main frame, and the case
5006 5021 * where we can't. The SG element is also different when using
5007 5022 * MPI2.5 interface.
5008 5023 * If we have more cookies than we can attach to a frame
5009 5024 * we will need to use a chain element to point
5010 5025 * a location of memory where the rest of the S/G
5011 5026 * elements reside.
5012 5027 */
5013 5028 if (cmd->cmd_cookiec <= MPTSAS_MAX_FRAME_SGES64(mpt)) {
5014 5029 if (mpt->m_MPI25) {
5015 5030 mptsas_ieee_sge_mainframe(cmd, frame, acc_hdl,
5016 5031 cmd->cmd_cookiec,
5017 5032 MPI25_IEEE_SGE_FLAGS_END_OF_LIST);
5018 5033 } else {
5019 5034 mptsas_sge_mainframe(cmd, frame, acc_hdl,
5020 5035 cmd->cmd_cookiec,
5021 5036 ((uint32_t)(MPI2_SGE_FLAGS_LAST_ELEMENT
5022 5037 | MPI2_SGE_FLAGS_END_OF_BUFFER
5023 5038 | MPI2_SGE_FLAGS_END_OF_LIST) <<
5024 5039 MPI2_SGE_FLAGS_SHIFT));
5025 5040 }
5026 5041 } else {
5027 5042 if (mpt->m_MPI25) {
5028 5043 mptsas_ieee_sge_chain(mpt, cmd, frame, acc_hdl);
5029 5044 } else {
5030 5045 mptsas_sge_chain(mpt, cmd, frame, acc_hdl);
5031 5046 }
5032 5047 }
5033 5048 }
5034 5049
5035 5050 /*
5036 5051 * Interrupt handling
5037 5052 * Utility routine. Poll for status of a command sent to HBA
5038 5053 * without interrupts (a FLAG_NOINTR command).
5039 5054 */
5040 5055 int
5041 5056 mptsas_poll(mptsas_t *mpt, mptsas_cmd_t *poll_cmd, int polltime)
5042 5057 {
5043 5058 int rval = TRUE;
5044 5059
5045 5060 NDBG5(("mptsas_poll: cmd=0x%p", (void *)poll_cmd));
5046 5061
5047 5062 if ((poll_cmd->cmd_flags & CFLAG_TM_CMD) == 0) {
5048 5063 mptsas_restart_hba(mpt);
5049 5064 }
5050 5065
5051 5066 /*
5052 5067 * Wait, using drv_usecwait(), long enough for the command to
5053 5068 * reasonably return from the target if the target isn't
5054 5069 * "dead". A polled command may well be sent from scsi_poll, and
5055 5070 * there are retries built in to scsi_poll if the transport
5056 5071 * accepted the packet (TRAN_ACCEPT). scsi_poll waits 1 second
5057 5072 * and retries the transport up to scsi_poll_busycnt times
5058 5073 * (currently 60) if
5059 5074 * 1. pkt_reason is CMD_INCOMPLETE and pkt_state is 0, or
5060 5075 * 2. pkt_reason is CMD_CMPLT and *pkt_scbp has STATUS_BUSY
5061 5076 *
5062 5077 * limit the waiting to avoid a hang in the event that the
5063 5078 * cmd never gets started but we are still receiving interrupts
5064 5079 */
5065 5080 while (!(poll_cmd->cmd_flags & CFLAG_FINISHED)) {
5066 5081 if (mptsas_wait_intr(mpt, polltime) == FALSE) {
5067 5082 NDBG5(("mptsas_poll: command incomplete"));
5068 5083 rval = FALSE;
5069 5084 break;
5070 5085 }
5071 5086 }
5072 5087
5073 5088 if (rval == FALSE) {
5074 5089
5075 5090 /*
5076 5091 * this isn't supposed to happen, the hba must be wedged
5077 5092 * Mark this cmd as a timeout.
5078 5093 */
5079 5094 mptsas_set_pkt_reason(mpt, poll_cmd, CMD_TIMEOUT,
5080 5095 (STAT_TIMEOUT|STAT_ABORTED));
5081 5096
5082 5097 if (poll_cmd->cmd_queued == FALSE) {
5083 5098
5084 5099 NDBG5(("mptsas_poll: not on waitq"));
5085 5100
5086 5101 poll_cmd->cmd_pkt->pkt_state |=
5087 5102 (STATE_GOT_BUS|STATE_GOT_TARGET|STATE_SENT_CMD);
5088 5103 } else {
5089 5104
5090 5105 /* find and remove it from the waitq */
5091 5106 NDBG5(("mptsas_poll: delete from waitq"));
5092 5107 mptsas_waitq_delete(mpt, poll_cmd);
5093 5108 }
5094 5109
5095 5110 }
5096 5111 mptsas_fma_check(mpt, poll_cmd);
5097 5112 NDBG5(("mptsas_poll: done"));
5098 5113 return (rval);
5099 5114 }
5100 5115
5101 5116 /*
5102 5117 * Used for polling cmds and TM function
5103 5118 */
5104 5119 static int
5105 5120 mptsas_wait_intr(mptsas_t *mpt, int polltime)
5106 5121 {
5107 5122 int cnt;
5108 5123 pMpi2ReplyDescriptorsUnion_t reply_desc_union;
5109 5124 uint32_t int_mask;
5110 5125
5111 5126 NDBG5(("mptsas_wait_intr"));
5112 5127
5113 5128 mpt->m_polled_intr = 1;
5114 5129
5115 5130 /*
5116 5131 * Get the current interrupt mask and disable interrupts. When
5117 5132 * re-enabling ints, set mask to saved value.
5118 5133 */
5119 5134 int_mask = ddi_get32(mpt->m_datap, &mpt->m_reg->HostInterruptMask);
5120 5135 MPTSAS_DISABLE_INTR(mpt);
5121 5136
5122 5137 /*
5123 5138 * Keep polling for at least (polltime * 1000) seconds
5124 5139 */
5125 5140 for (cnt = 0; cnt < polltime; cnt++) {
5126 5141 (void) ddi_dma_sync(mpt->m_dma_post_queue_hdl, 0, 0,
5127 5142 DDI_DMA_SYNC_FORCPU);
5128 5143
5129 5144 reply_desc_union = (pMpi2ReplyDescriptorsUnion_t)
5130 5145 MPTSAS_GET_NEXT_REPLY(mpt, mpt->m_post_index);
5131 5146
5132 5147 if (ddi_get32(mpt->m_acc_post_queue_hdl,
5133 5148 &reply_desc_union->Words.Low) == 0xFFFFFFFF ||
5134 5149 ddi_get32(mpt->m_acc_post_queue_hdl,
5135 5150 &reply_desc_union->Words.High) == 0xFFFFFFFF) {
5136 5151 drv_usecwait(1000);
5137 5152 continue;
5138 5153 }
5139 5154
5140 5155 /*
5141 5156 * The reply is valid, process it according to its
5142 5157 * type.
5143 5158 */
5144 5159 mptsas_process_intr(mpt, reply_desc_union);
5145 5160
5146 5161 if (++mpt->m_post_index == mpt->m_post_queue_depth) {
5147 5162 mpt->m_post_index = 0;
5148 5163 }
5149 5164
5150 5165 /*
5151 5166 * Update the global reply index
5152 5167 */
5153 5168 ddi_put32(mpt->m_datap,
5154 5169 &mpt->m_reg->ReplyPostHostIndex, mpt->m_post_index);
5155 5170 mpt->m_polled_intr = 0;
5156 5171
5157 5172 /*
5158 5173 * Re-enable interrupts and quit.
5159 5174 */
5160 5175 ddi_put32(mpt->m_datap, &mpt->m_reg->HostInterruptMask,
5161 5176 int_mask);
5162 5177 return (TRUE);
5163 5178
5164 5179 }
5165 5180
5166 5181 /*
5167 5182 * Clear polling flag, re-enable interrupts and quit.
5168 5183 */
5169 5184 mpt->m_polled_intr = 0;
5170 5185 ddi_put32(mpt->m_datap, &mpt->m_reg->HostInterruptMask, int_mask);
5171 5186 return (FALSE);
5172 5187 }
5173 5188
5174 5189 static void
5175 5190 mptsas_handle_scsi_io_success(mptsas_t *mpt,
5176 5191 pMpi2ReplyDescriptorsUnion_t reply_desc)
5177 5192 {
5178 5193 pMpi2SCSIIOSuccessReplyDescriptor_t scsi_io_success;
5179 5194 uint16_t SMID;
5180 5195 mptsas_slots_t *slots = mpt->m_active;
5181 5196 mptsas_cmd_t *cmd = NULL;
5182 5197 struct scsi_pkt *pkt;
5183 5198
5184 5199 ASSERT(mutex_owned(&mpt->m_mutex));
5185 5200
5186 5201 scsi_io_success = (pMpi2SCSIIOSuccessReplyDescriptor_t)reply_desc;
5187 5202 SMID = ddi_get16(mpt->m_acc_post_queue_hdl, &scsi_io_success->SMID);
5188 5203
5189 5204 /*
5190 5205 * This is a success reply so just complete the IO. First, do a sanity
5191 5206 * check on the SMID. The final slot is used for TM requests, which
5192 5207 * would not come into this reply handler.
5193 5208 */
5194 5209 if ((SMID == 0) || (SMID > slots->m_n_normal)) {
5195 5210 mptsas_log(mpt, CE_WARN, "?Received invalid SMID of %d\n",
5196 5211 SMID);
5197 5212 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
5198 5213 return;
5199 5214 }
5200 5215
5201 5216 cmd = slots->m_slot[SMID];
5202 5217
5203 5218 /*
5204 5219 * print warning and return if the slot is empty
5205 5220 */
5206 5221 if (cmd == NULL) {
5207 5222 mptsas_log(mpt, CE_WARN, "?NULL command for successful SCSI IO "
5208 5223 "in slot %d", SMID);
5209 5224 return;
5210 5225 }
5211 5226
5212 5227 pkt = CMD2PKT(cmd);
5213 5228 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET | STATE_SENT_CMD |
5214 5229 STATE_GOT_STATUS);
5215 5230 if (cmd->cmd_flags & CFLAG_DMAVALID) {
5216 5231 pkt->pkt_state |= STATE_XFERRED_DATA;
5217 5232 }
5218 5233 pkt->pkt_resid = 0;
5219 5234
5220 5235 if (cmd->cmd_flags & CFLAG_PASSTHRU) {
5221 5236 cmd->cmd_flags |= CFLAG_FINISHED;
5222 5237 cv_broadcast(&mpt->m_passthru_cv);
5223 5238 return;
5224 5239 } else {
5225 5240 mptsas_remove_cmd(mpt, cmd);
5226 5241 }
5227 5242
5228 5243 if (cmd->cmd_flags & CFLAG_RETRY) {
5229 5244 /*
5230 5245 * The target returned QFULL or busy, do not add tihs
5231 5246 * pkt to the doneq since the hba will retry
5232 5247 * this cmd.
5233 5248 *
5234 5249 * The pkt has already been resubmitted in
5235 5250 * mptsas_handle_qfull() or in mptsas_check_scsi_io_error().
5236 5251 * Remove this cmd_flag here.
5237 5252 */
5238 5253 cmd->cmd_flags &= ~CFLAG_RETRY;
5239 5254 } else {
5240 5255 mptsas_doneq_add(mpt, cmd);
5241 5256 }
5242 5257 }
5243 5258
5244 5259 static void
5245 5260 mptsas_handle_address_reply(mptsas_t *mpt,
5246 5261 pMpi2ReplyDescriptorsUnion_t reply_desc)
5247 5262 {
5248 5263 pMpi2AddressReplyDescriptor_t address_reply;
5249 5264 pMPI2DefaultReply_t reply;
5250 5265 mptsas_fw_diagnostic_buffer_t *pBuffer;
5251 5266 uint32_t reply_addr, reply_frame_dma_baseaddr;
5252 5267 uint16_t SMID, iocstatus;
5253 5268 mptsas_slots_t *slots = mpt->m_active;
5254 5269 mptsas_cmd_t *cmd = NULL;
5255 5270 uint8_t function, buffer_type;
5256 5271 m_replyh_arg_t *args;
5257 5272 int reply_frame_no;
5258 5273
5259 5274 ASSERT(mutex_owned(&mpt->m_mutex));
5260 5275
5261 5276 address_reply = (pMpi2AddressReplyDescriptor_t)reply_desc;
5262 5277 reply_addr = ddi_get32(mpt->m_acc_post_queue_hdl,
5263 5278 &address_reply->ReplyFrameAddress);
5264 5279 SMID = ddi_get16(mpt->m_acc_post_queue_hdl, &address_reply->SMID);
5265 5280
5266 5281 /*
5267 5282 * If reply frame is not in the proper range we should ignore this
5268 5283 * message and exit the interrupt handler.
5269 5284 */
5270 5285 reply_frame_dma_baseaddr = mpt->m_reply_frame_dma_addr & 0xffffffffu;
5271 5286 if ((reply_addr < reply_frame_dma_baseaddr) ||
5272 5287 (reply_addr >= (reply_frame_dma_baseaddr +
5273 5288 (mpt->m_reply_frame_size * mpt->m_max_replies))) ||
5274 5289 ((reply_addr - reply_frame_dma_baseaddr) %
5275 5290 mpt->m_reply_frame_size != 0)) {
5276 5291 mptsas_log(mpt, CE_WARN, "?Received invalid reply frame "
5277 5292 "address 0x%x\n", reply_addr);
5278 5293 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
5279 5294 return;
5280 5295 }
5281 5296
5282 5297 (void) ddi_dma_sync(mpt->m_dma_reply_frame_hdl, 0, 0,
5283 5298 DDI_DMA_SYNC_FORCPU);
5284 5299 reply = (pMPI2DefaultReply_t)(mpt->m_reply_frame + (reply_addr -
5285 5300 reply_frame_dma_baseaddr));
5286 5301 function = ddi_get8(mpt->m_acc_reply_frame_hdl, &reply->Function);
5287 5302
5288 5303 NDBG31(("mptsas_handle_address_reply: function 0x%x, reply_addr=0x%x",
5289 5304 function, reply_addr));
5290 5305
5291 5306 /*
5292 5307 * don't get slot information and command for events since these values
5293 5308 * don't exist
5294 5309 */
5295 5310 if ((function != MPI2_FUNCTION_EVENT_NOTIFICATION) &&
5296 5311 (function != MPI2_FUNCTION_DIAG_BUFFER_POST)) {
5297 5312 /*
5298 5313 * This could be a TM reply, which use the last allocated SMID,
5299 5314 * so allow for that.
5300 5315 */
5301 5316 if ((SMID == 0) || (SMID > (slots->m_n_normal + 1))) {
5302 5317 mptsas_log(mpt, CE_WARN, "?Received invalid SMID of "
5303 5318 "%d\n", SMID);
5304 5319 ddi_fm_service_impact(mpt->m_dip,
5305 5320 DDI_SERVICE_UNAFFECTED);
5306 5321 return;
5307 5322 }
5308 5323
5309 5324 cmd = slots->m_slot[SMID];
5310 5325
5311 5326 /*
5312 5327 * print warning and return if the slot is empty
5313 5328 */
5314 5329 if (cmd == NULL) {
5315 5330 mptsas_log(mpt, CE_WARN, "?NULL command for address "
5316 5331 "reply in slot %d", SMID);
5317 5332 return;
5318 5333 }
5319 5334 if ((cmd->cmd_flags &
5320 5335 (CFLAG_PASSTHRU | CFLAG_CONFIG | CFLAG_FW_DIAG))) {
5321 5336 cmd->cmd_rfm = reply_addr;
5322 5337 cmd->cmd_flags |= CFLAG_FINISHED;
5323 5338 cv_broadcast(&mpt->m_passthru_cv);
5324 5339 cv_broadcast(&mpt->m_config_cv);
5325 5340 cv_broadcast(&mpt->m_fw_diag_cv);
5326 5341 return;
5327 5342 } else if (!(cmd->cmd_flags & CFLAG_FW_CMD)) {
5328 5343 mptsas_remove_cmd(mpt, cmd);
5329 5344 }
5330 5345 NDBG31(("\t\tmptsas_process_intr: slot=%d", SMID));
5331 5346 }
5332 5347 /*
5333 5348 * Depending on the function, we need to handle
5334 5349 * the reply frame (and cmd) differently.
5335 5350 */
5336 5351 switch (function) {
5337 5352 case MPI2_FUNCTION_SCSI_IO_REQUEST:
5338 5353 mptsas_check_scsi_io_error(mpt, (pMpi2SCSIIOReply_t)reply, cmd);
5339 5354 break;
5340 5355 case MPI2_FUNCTION_SCSI_TASK_MGMT:
5341 5356 cmd->cmd_rfm = reply_addr;
5342 5357 mptsas_check_task_mgt(mpt, (pMpi2SCSIManagementReply_t)reply,
5343 5358 cmd);
5344 5359 break;
5345 5360 case MPI2_FUNCTION_FW_DOWNLOAD:
5346 5361 cmd->cmd_flags |= CFLAG_FINISHED;
5347 5362 cv_signal(&mpt->m_fw_cv);
5348 5363 break;
5349 5364 case MPI2_FUNCTION_EVENT_NOTIFICATION:
5350 5365 reply_frame_no = (reply_addr - reply_frame_dma_baseaddr) /
5351 5366 mpt->m_reply_frame_size;
5352 5367 args = &mpt->m_replyh_args[reply_frame_no];
5353 5368 args->mpt = (void *)mpt;
5354 5369 args->rfm = reply_addr;
5355 5370
5356 5371 /*
5357 5372 * Record the event if its type is enabled in
5358 5373 * this mpt instance by ioctl.
5359 5374 */
5360 5375 mptsas_record_event(args);
5361 5376
5362 5377 /*
5363 5378 * Handle time critical events
5364 5379 * NOT_RESPONDING/ADDED only now
↓ open down ↓ |
1654 lines elided |
↑ open up ↑ |
5365 5380 */
5366 5381 if (mptsas_handle_event_sync(args) == DDI_SUCCESS) {
5367 5382 /*
5368 5383 * Would not return main process,
5369 5384 * just let taskq resolve ack action
5370 5385 * and ack would be sent in taskq thread
5371 5386 */
5372 5387 NDBG20(("send mptsas_handle_event_sync success"));
5373 5388 }
5374 5389
5375 - if (mpt->m_in_reset) {
5390 + mutex_enter(&mpt->m_taskmgmt_mutex);
5391 + if (mpt->m_in_reset == TRUE) {
5376 5392 NDBG20(("dropping event received during reset"));
5393 + mutex_exit(&mpt->m_taskmgmt_mutex);
5377 5394 return;
5378 5395 }
5396 + mutex_exit(&mpt->m_taskmgmt_mutex);
5379 5397
5380 5398 if ((ddi_taskq_dispatch(mpt->m_event_taskq, mptsas_handle_event,
5381 5399 (void *)args, DDI_NOSLEEP)) != DDI_SUCCESS) {
5382 5400 mptsas_log(mpt, CE_WARN, "No memory available"
5383 5401 "for dispatch taskq");
5384 5402 /*
5385 5403 * Return the reply frame to the free queue.
5386 5404 */
5387 5405 ddi_put32(mpt->m_acc_free_queue_hdl,
5388 5406 &((uint32_t *)(void *)
5389 5407 mpt->m_free_queue)[mpt->m_free_index], reply_addr);
5390 5408 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0,
5391 5409 DDI_DMA_SYNC_FORDEV);
5392 5410 if (++mpt->m_free_index == mpt->m_free_queue_depth) {
5393 5411 mpt->m_free_index = 0;
5394 5412 }
5395 5413
5396 5414 ddi_put32(mpt->m_datap,
5397 5415 &mpt->m_reg->ReplyFreeHostIndex, mpt->m_free_index);
5398 5416 }
5399 5417 return;
5400 5418 case MPI2_FUNCTION_DIAG_BUFFER_POST:
5401 5419 /*
5402 5420 * If SMID is 0, this implies that the reply is due to a
5403 5421 * release function with a status that the buffer has been
5404 5422 * released. Set the buffer flags accordingly.
5405 5423 */
5406 5424 if (SMID == 0) {
5407 5425 iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl,
5408 5426 &reply->IOCStatus);
5409 5427 buffer_type = ddi_get8(mpt->m_acc_reply_frame_hdl,
5410 5428 &(((pMpi2DiagBufferPostReply_t)reply)->BufferType));
5411 5429 if (iocstatus == MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED) {
5412 5430 pBuffer =
5413 5431 &mpt->m_fw_diag_buffer_list[buffer_type];
5414 5432 pBuffer->valid_data = TRUE;
5415 5433 pBuffer->owned_by_firmware = FALSE;
5416 5434 pBuffer->immediate = FALSE;
5417 5435 }
5418 5436 } else {
5419 5437 /*
5420 5438 * Normal handling of diag post reply with SMID.
5421 5439 */
5422 5440 cmd = slots->m_slot[SMID];
5423 5441
5424 5442 /*
5425 5443 * print warning and return if the slot is empty
5426 5444 */
5427 5445 if (cmd == NULL) {
5428 5446 mptsas_log(mpt, CE_WARN, "?NULL command for "
5429 5447 "address reply in slot %d", SMID);
5430 5448 return;
5431 5449 }
5432 5450 cmd->cmd_rfm = reply_addr;
5433 5451 cmd->cmd_flags |= CFLAG_FINISHED;
5434 5452 cv_broadcast(&mpt->m_fw_diag_cv);
5435 5453 }
5436 5454 return;
5437 5455 default:
5438 5456 mptsas_log(mpt, CE_WARN, "Unknown function 0x%x ", function);
5439 5457 break;
5440 5458 }
5441 5459
5442 5460 /*
5443 5461 * Return the reply frame to the free queue.
5444 5462 */
5445 5463 ddi_put32(mpt->m_acc_free_queue_hdl,
5446 5464 &((uint32_t *)(void *)mpt->m_free_queue)[mpt->m_free_index],
5447 5465 reply_addr);
5448 5466 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0,
5449 5467 DDI_DMA_SYNC_FORDEV);
5450 5468 if (++mpt->m_free_index == mpt->m_free_queue_depth) {
5451 5469 mpt->m_free_index = 0;
5452 5470 }
5453 5471 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex,
5454 5472 mpt->m_free_index);
5455 5473
5456 5474 if (cmd->cmd_flags & CFLAG_FW_CMD)
5457 5475 return;
5458 5476
5459 5477 if (cmd->cmd_flags & CFLAG_RETRY) {
5460 5478 /*
5461 5479 * The target returned QFULL or busy, do not add this
5462 5480 * pkt to the doneq since the hba will retry
5463 5481 * this cmd.
5464 5482 *
5465 5483 * The pkt has already been resubmitted in
5466 5484 * mptsas_handle_qfull() or in mptsas_check_scsi_io_error().
5467 5485 * Remove this cmd_flag here.
5468 5486 */
5469 5487 cmd->cmd_flags &= ~CFLAG_RETRY;
5470 5488 } else {
5471 5489 mptsas_doneq_add(mpt, cmd);
5472 5490 }
5473 5491 }
5474 5492
5475 5493 #ifdef MPTSAS_DEBUG
5476 5494 static uint8_t mptsas_last_sense[256];
5477 5495 #endif
5478 5496
5479 5497 static void
5480 5498 mptsas_check_scsi_io_error(mptsas_t *mpt, pMpi2SCSIIOReply_t reply,
5481 5499 mptsas_cmd_t *cmd)
5482 5500 {
5483 5501 uint8_t scsi_status, scsi_state;
5484 5502 uint16_t ioc_status, cmd_rqs_len;
5485 5503 uint32_t xferred, sensecount, responsedata, loginfo = 0;
5486 5504 struct scsi_pkt *pkt;
5487 5505 struct scsi_arq_status *arqstat;
5488 5506 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
5489 5507 uint8_t *sensedata = NULL;
5490 5508 uint64_t sas_wwn;
5491 5509 uint8_t phy;
5492 5510 char wwn_str[MPTSAS_WWN_STRLEN];
5493 5511
5494 5512 scsi_status = ddi_get8(mpt->m_acc_reply_frame_hdl, &reply->SCSIStatus);
5495 5513 ioc_status = ddi_get16(mpt->m_acc_reply_frame_hdl, &reply->IOCStatus);
5496 5514 scsi_state = ddi_get8(mpt->m_acc_reply_frame_hdl, &reply->SCSIState);
5497 5515 xferred = ddi_get32(mpt->m_acc_reply_frame_hdl, &reply->TransferCount);
5498 5516 sensecount = ddi_get32(mpt->m_acc_reply_frame_hdl, &reply->SenseCount);
5499 5517 responsedata = ddi_get32(mpt->m_acc_reply_frame_hdl,
5500 5518 &reply->ResponseInfo);
5501 5519
5502 5520 if (ioc_status & MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) {
5503 5521 sas_wwn = ptgt->m_addr.mta_wwn;
5504 5522 phy = ptgt->m_phynum;
5505 5523 if (sas_wwn == 0) {
5506 5524 (void) sprintf(wwn_str, "p%x", phy);
5507 5525 } else {
5508 5526 (void) sprintf(wwn_str, "w%016"PRIx64, sas_wwn);
5509 5527 }
5510 5528 loginfo = ddi_get32(mpt->m_acc_reply_frame_hdl,
5511 5529 &reply->IOCLogInfo);
5512 5530 mptsas_log(mpt, CE_NOTE,
5513 5531 "?Log info 0x%x received for target %d %s.\n"
5514 5532 "\tscsi_status=0x%x, ioc_status=0x%x, scsi_state=0x%x",
5515 5533 loginfo, Tgt(cmd), wwn_str, scsi_status, ioc_status,
5516 5534 scsi_state);
5517 5535 }
5518 5536
5519 5537 NDBG31(("\t\tscsi_status=0x%x, ioc_status=0x%x, scsi_state=0x%x",
5520 5538 scsi_status, ioc_status, scsi_state));
5521 5539
5522 5540 pkt = CMD2PKT(cmd);
5523 5541 *(pkt->pkt_scbp) = scsi_status;
5524 5542
5525 5543 if (loginfo == 0x31170000) {
5526 5544 /*
5527 5545 * if loginfo PL_LOGINFO_CODE_IO_DEVICE_MISSING_DELAY_RETRY
5528 5546 * 0x31170000 comes, that means the device missing delay
5529 5547 * is in progressing, the command need retry later.
5530 5548 */
5531 5549 *(pkt->pkt_scbp) = STATUS_BUSY;
5532 5550 return;
5533 5551 }
5534 5552
5535 5553 if ((scsi_state & MPI2_SCSI_STATE_NO_SCSI_STATUS) &&
5536 5554 ((ioc_status & MPI2_IOCSTATUS_MASK) ==
5537 5555 MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE)) {
5538 5556 pkt->pkt_reason = CMD_INCOMPLETE;
5539 5557 pkt->pkt_state |= STATE_GOT_BUS;
5540 5558 if (ptgt->m_reset_delay == 0) {
5541 5559 mptsas_set_throttle(mpt, ptgt,
5542 5560 DRAIN_THROTTLE);
5543 5561 }
5544 5562 return;
5545 5563 }
5546 5564
5547 5565 if (scsi_state & MPI2_SCSI_STATE_RESPONSE_INFO_VALID) {
5548 5566 responsedata &= 0x000000FF;
5549 5567 if (responsedata & MPTSAS_SCSI_RESPONSE_CODE_TLR_OFF) {
5550 5568 mptsas_log(mpt, CE_NOTE, "Do not support the TLR\n");
5551 5569 pkt->pkt_reason = CMD_TLR_OFF;
5552 5570 return;
5553 5571 }
5554 5572 }
5555 5573
5556 5574
5557 5575 switch (scsi_status) {
5558 5576 case MPI2_SCSI_STATUS_CHECK_CONDITION:
5559 5577 pkt->pkt_resid = (cmd->cmd_dmacount - xferred);
5560 5578 arqstat = (void*)(pkt->pkt_scbp);
5561 5579 arqstat->sts_rqpkt_status = *((struct scsi_status *)
5562 5580 (pkt->pkt_scbp));
5563 5581 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET |
5564 5582 STATE_SENT_CMD | STATE_GOT_STATUS | STATE_ARQ_DONE);
5565 5583 if (cmd->cmd_flags & CFLAG_XARQ) {
5566 5584 pkt->pkt_state |= STATE_XARQ_DONE;
5567 5585 }
5568 5586 if (pkt->pkt_resid != cmd->cmd_dmacount) {
5569 5587 pkt->pkt_state |= STATE_XFERRED_DATA;
5570 5588 }
5571 5589 arqstat->sts_rqpkt_reason = pkt->pkt_reason;
5572 5590 arqstat->sts_rqpkt_state = pkt->pkt_state;
5573 5591 arqstat->sts_rqpkt_state |= STATE_XFERRED_DATA;
5574 5592 arqstat->sts_rqpkt_statistics = pkt->pkt_statistics;
5575 5593 sensedata = (uint8_t *)&arqstat->sts_sensedata;
5576 5594 cmd_rqs_len = cmd->cmd_extrqslen ?
5577 5595 cmd->cmd_extrqslen : cmd->cmd_rqslen;
5578 5596 (void) ddi_dma_sync(mpt->m_dma_req_sense_hdl, 0, 0,
5579 5597 DDI_DMA_SYNC_FORKERNEL);
5580 5598 #ifdef MPTSAS_DEBUG
5581 5599 bcopy(cmd->cmd_arq_buf, mptsas_last_sense,
5582 5600 ((cmd_rqs_len >= sizeof (mptsas_last_sense)) ?
5583 5601 sizeof (mptsas_last_sense):cmd_rqs_len));
5584 5602 #endif
5585 5603 bcopy((uchar_t *)cmd->cmd_arq_buf, sensedata,
5586 5604 ((cmd_rqs_len >= sensecount) ? sensecount :
5587 5605 cmd_rqs_len));
5588 5606 arqstat->sts_rqpkt_resid = (cmd_rqs_len - sensecount);
5589 5607 cmd->cmd_flags |= CFLAG_CMDARQ;
5590 5608 /*
5591 5609 * Set proper status for pkt if autosense was valid
5592 5610 */
5593 5611 if (scsi_state & MPI2_SCSI_STATE_AUTOSENSE_VALID) {
5594 5612 struct scsi_status zero_status = { 0 };
5595 5613 arqstat->sts_rqpkt_status = zero_status;
5596 5614 }
5597 5615
5598 5616 /*
5599 5617 * ASC=0x47 is parity error
5600 5618 * ASC=0x48 is initiator detected error received
5601 5619 */
5602 5620 if ((scsi_sense_key(sensedata) == KEY_ABORTED_COMMAND) &&
5603 5621 ((scsi_sense_asc(sensedata) == 0x47) ||
5604 5622 (scsi_sense_asc(sensedata) == 0x48))) {
5605 5623 mptsas_log(mpt, CE_NOTE, "Aborted_command!");
5606 5624 }
5607 5625
5608 5626 /*
5609 5627 * ASC/ASCQ=0x3F/0x0E means report_luns data changed
5610 5628 * ASC/ASCQ=0x25/0x00 means invalid lun
5611 5629 */
5612 5630 if (((scsi_sense_key(sensedata) == KEY_UNIT_ATTENTION) &&
5613 5631 (scsi_sense_asc(sensedata) == 0x3F) &&
5614 5632 (scsi_sense_ascq(sensedata) == 0x0E)) ||
5615 5633 ((scsi_sense_key(sensedata) == KEY_ILLEGAL_REQUEST) &&
5616 5634 (scsi_sense_asc(sensedata) == 0x25) &&
5617 5635 (scsi_sense_ascq(sensedata) == 0x00))) {
5618 5636 mptsas_topo_change_list_t *topo_node = NULL;
5619 5637
5620 5638 topo_node = kmem_zalloc(
5621 5639 sizeof (mptsas_topo_change_list_t),
5622 5640 KM_NOSLEEP);
5623 5641 if (topo_node == NULL) {
5624 5642 mptsas_log(mpt, CE_NOTE, "No memory"
5625 5643 "resource for handle SAS dynamic"
5626 5644 "reconfigure.\n");
5627 5645 break;
5628 5646 }
5629 5647 topo_node->mpt = mpt;
5630 5648 topo_node->event = MPTSAS_DR_EVENT_RECONFIG_TARGET;
5631 5649 topo_node->un.phymask = ptgt->m_addr.mta_phymask;
5632 5650 topo_node->devhdl = ptgt->m_devhdl;
5633 5651 topo_node->object = (void *)ptgt;
5634 5652 topo_node->flags = MPTSAS_TOPO_FLAG_LUN_ASSOCIATED;
5635 5653
5636 5654 if ((ddi_taskq_dispatch(mpt->m_dr_taskq,
5637 5655 mptsas_handle_dr,
5638 5656 (void *)topo_node,
5639 5657 DDI_NOSLEEP)) != DDI_SUCCESS) {
5640 5658 kmem_free(topo_node,
5641 5659 sizeof (mptsas_topo_change_list_t));
5642 5660 mptsas_log(mpt, CE_NOTE, "mptsas start taskq"
5643 5661 "for handle SAS dynamic reconfigure"
5644 5662 "failed. \n");
5645 5663 }
5646 5664 }
5647 5665 break;
5648 5666 case MPI2_SCSI_STATUS_GOOD:
5649 5667 switch (ioc_status & MPI2_IOCSTATUS_MASK) {
5650 5668 case MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE:
5651 5669 pkt->pkt_reason = CMD_DEV_GONE;
5652 5670 pkt->pkt_state |= STATE_GOT_BUS;
5653 5671 if (ptgt->m_reset_delay == 0) {
5654 5672 mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE);
5655 5673 }
5656 5674 NDBG31(("lost disk for target%d, command:%x",
5657 5675 Tgt(cmd), pkt->pkt_cdbp[0]));
5658 5676 break;
5659 5677 case MPI2_IOCSTATUS_SCSI_DATA_OVERRUN:
5660 5678 NDBG31(("data overrun: xferred=%d", xferred));
5661 5679 NDBG31(("dmacount=%d", cmd->cmd_dmacount));
5662 5680 pkt->pkt_reason = CMD_DATA_OVR;
5663 5681 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET
5664 5682 | STATE_SENT_CMD | STATE_GOT_STATUS
5665 5683 | STATE_XFERRED_DATA);
5666 5684 pkt->pkt_resid = 0;
5667 5685 break;
5668 5686 case MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH:
5669 5687 case MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN:
5670 5688 NDBG31(("data underrun: xferred=%d", xferred));
5671 5689 NDBG31(("dmacount=%d", cmd->cmd_dmacount));
5672 5690 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET
5673 5691 | STATE_SENT_CMD | STATE_GOT_STATUS);
5674 5692 pkt->pkt_resid = (cmd->cmd_dmacount - xferred);
5675 5693 if (pkt->pkt_resid != cmd->cmd_dmacount) {
5676 5694 pkt->pkt_state |= STATE_XFERRED_DATA;
5677 5695 }
5678 5696 break;
5679 5697 case MPI2_IOCSTATUS_SCSI_TASK_TERMINATED:
5680 5698 if (cmd->cmd_active_expiration <= gethrtime()) {
5681 5699 /*
5682 5700 * When timeout requested, propagate
5683 5701 * proper reason and statistics to
5684 5702 * target drivers.
5685 5703 */
5686 5704 mptsas_set_pkt_reason(mpt, cmd, CMD_TIMEOUT,
5687 5705 STAT_BUS_RESET | STAT_TIMEOUT);
5688 5706 } else {
5689 5707 mptsas_set_pkt_reason(mpt, cmd, CMD_RESET,
5690 5708 STAT_BUS_RESET);
5691 5709 }
5692 5710 break;
5693 5711 case MPI2_IOCSTATUS_SCSI_IOC_TERMINATED:
5694 5712 case MPI2_IOCSTATUS_SCSI_EXT_TERMINATED:
5695 5713 mptsas_set_pkt_reason(mpt,
5696 5714 cmd, CMD_RESET, STAT_DEV_RESET);
5697 5715 break;
5698 5716 case MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR:
5699 5717 case MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR:
5700 5718 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET);
5701 5719 mptsas_set_pkt_reason(mpt,
5702 5720 cmd, CMD_TERMINATED, STAT_TERMINATED);
5703 5721 break;
5704 5722 case MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES:
5705 5723 case MPI2_IOCSTATUS_BUSY:
5706 5724 /*
5707 5725 * set throttles to drain
5708 5726 */
5709 5727 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL;
5710 5728 ptgt = refhash_next(mpt->m_targets, ptgt)) {
5711 5729 mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE);
5712 5730 }
5713 5731
5714 5732 /*
5715 5733 * retry command
5716 5734 */
5717 5735 cmd->cmd_flags |= CFLAG_RETRY;
5718 5736 cmd->cmd_pkt_flags |= FLAG_HEAD;
5719 5737
5720 5738 (void) mptsas_accept_pkt(mpt, cmd);
5721 5739 break;
5722 5740 default:
5723 5741 mptsas_log(mpt, CE_WARN,
5724 5742 "unknown ioc_status = %x\n", ioc_status);
5725 5743 mptsas_log(mpt, CE_CONT, "scsi_state = %x, transfer "
5726 5744 "count = %x, scsi_status = %x", scsi_state,
5727 5745 xferred, scsi_status);
5728 5746 break;
5729 5747 }
5730 5748 break;
5731 5749 case MPI2_SCSI_STATUS_TASK_SET_FULL:
5732 5750 mptsas_handle_qfull(mpt, cmd);
5733 5751 break;
5734 5752 case MPI2_SCSI_STATUS_BUSY:
5735 5753 NDBG31(("scsi_status busy received"));
5736 5754 break;
5737 5755 case MPI2_SCSI_STATUS_RESERVATION_CONFLICT:
5738 5756 NDBG31(("scsi_status reservation conflict received"));
5739 5757 break;
5740 5758 default:
5741 5759 mptsas_log(mpt, CE_WARN, "scsi_status=%x, ioc_status=%x\n",
5742 5760 scsi_status, ioc_status);
5743 5761 mptsas_log(mpt, CE_WARN,
5744 5762 "mptsas_process_intr: invalid scsi status\n");
5745 5763 break;
5746 5764 }
5747 5765 }
5748 5766
5749 5767 static void
5750 5768 mptsas_check_task_mgt(mptsas_t *mpt, pMpi2SCSIManagementReply_t reply,
5751 5769 mptsas_cmd_t *cmd)
5752 5770 {
5753 5771 uint8_t task_type;
5754 5772 uint16_t ioc_status;
5755 5773 uint32_t log_info;
5756 5774 uint16_t dev_handle;
5757 5775 struct scsi_pkt *pkt = CMD2PKT(cmd);
5758 5776
5759 5777 task_type = ddi_get8(mpt->m_acc_reply_frame_hdl, &reply->TaskType);
5760 5778 ioc_status = ddi_get16(mpt->m_acc_reply_frame_hdl, &reply->IOCStatus);
5761 5779 log_info = ddi_get32(mpt->m_acc_reply_frame_hdl, &reply->IOCLogInfo);
5762 5780 dev_handle = ddi_get16(mpt->m_acc_reply_frame_hdl, &reply->DevHandle);
5763 5781
5764 5782 if (ioc_status != MPI2_IOCSTATUS_SUCCESS) {
5765 5783 mptsas_log(mpt, CE_WARN, "mptsas_check_task_mgt: Task 0x%x "
5766 5784 "failed. IOCStatus=0x%x IOCLogInfo=0x%x target=%d\n",
5767 5785 task_type, ioc_status, log_info, dev_handle);
5768 5786 pkt->pkt_reason = CMD_INCOMPLETE;
5769 5787 return;
5770 5788 }
5771 5789
5772 5790 switch (task_type) {
5773 5791 case MPI2_SCSITASKMGMT_TASKTYPE_ABORT_TASK:
5774 5792 case MPI2_SCSITASKMGMT_TASKTYPE_CLEAR_TASK_SET:
5775 5793 case MPI2_SCSITASKMGMT_TASKTYPE_QUERY_TASK:
5776 5794 case MPI2_SCSITASKMGMT_TASKTYPE_CLR_ACA:
5777 5795 case MPI2_SCSITASKMGMT_TASKTYPE_QRY_TASK_SET:
5778 5796 case MPI2_SCSITASKMGMT_TASKTYPE_QRY_UNIT_ATTENTION:
5779 5797 break;
5780 5798 case MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET:
5781 5799 case MPI2_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET:
5782 5800 case MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET:
5783 5801 /*
5784 5802 * Check for invalid DevHandle of 0 in case application
5785 5803 * sends bad command. DevHandle of 0 could cause problems.
5786 5804 */
5787 5805 if (dev_handle == 0) {
5788 5806 mptsas_log(mpt, CE_WARN, "!Can't flush target with"
5789 5807 " DevHandle of 0.");
5790 5808 } else {
5791 5809 mptsas_flush_target(mpt, dev_handle, Lun(cmd),
5792 5810 task_type);
5793 5811 }
5794 5812 break;
5795 5813 default:
5796 5814 mptsas_log(mpt, CE_WARN, "Unknown task management type %d.",
5797 5815 task_type);
5798 5816 mptsas_log(mpt, CE_WARN, "ioc status = %x", ioc_status);
5799 5817 break;
5800 5818 }
5801 5819 }
5802 5820
5803 5821 static void
5804 5822 mptsas_doneq_thread(mptsas_doneq_thread_arg_t *arg)
5805 5823 {
5806 5824 mptsas_t *mpt = arg->mpt;
5807 5825 uint64_t t = arg->t;
5808 5826 mptsas_cmd_t *cmd;
5809 5827 struct scsi_pkt *pkt;
5810 5828 mptsas_doneq_thread_list_t *item = &mpt->m_doneq_thread_id[t];
5811 5829
5812 5830 mutex_enter(&item->mutex);
5813 5831 while (item->flag & MPTSAS_DONEQ_THREAD_ACTIVE) {
5814 5832 if (!item->doneq) {
5815 5833 cv_wait(&item->cv, &item->mutex);
5816 5834 }
5817 5835 pkt = NULL;
5818 5836 if ((cmd = mptsas_doneq_thread_rm(mpt, t)) != NULL) {
5819 5837 cmd->cmd_flags |= CFLAG_COMPLETED;
5820 5838 pkt = CMD2PKT(cmd);
5821 5839 }
5822 5840 mutex_exit(&item->mutex);
5823 5841 if (pkt) {
5824 5842 mptsas_pkt_comp(pkt, cmd);
5825 5843 }
5826 5844 mutex_enter(&item->mutex);
5827 5845 }
5828 5846 mutex_exit(&item->mutex);
5829 5847 mutex_enter(&mpt->m_doneq_mutex);
5830 5848 mpt->m_doneq_thread_n--;
5831 5849 cv_broadcast(&mpt->m_doneq_thread_cv);
5832 5850 mutex_exit(&mpt->m_doneq_mutex);
5833 5851 }
5834 5852
5835 5853
5836 5854 /*
5837 5855 * mpt interrupt handler.
5838 5856 */
5839 5857 static uint_t
5840 5858 mptsas_intr(caddr_t arg1, caddr_t arg2)
5841 5859 {
5842 5860 mptsas_t *mpt = (void *)arg1;
5843 5861 pMpi2ReplyDescriptorsUnion_t reply_desc_union;
5844 5862 uchar_t did_reply = FALSE;
5845 5863
5846 5864 NDBG1(("mptsas_intr: arg1 0x%p arg2 0x%p", (void *)arg1, (void *)arg2));
5847 5865
5848 5866 mutex_enter(&mpt->m_mutex);
5849 5867
5850 5868 /*
5851 5869 * If interrupts are shared by two channels then check whether this
5852 5870 * interrupt is genuinely for this channel by making sure first the
5853 5871 * chip is in high power state.
5854 5872 */
5855 5873 if ((mpt->m_options & MPTSAS_OPT_PM) &&
5856 5874 (mpt->m_power_level != PM_LEVEL_D0)) {
5857 5875 mutex_exit(&mpt->m_mutex);
5858 5876 return (DDI_INTR_UNCLAIMED);
5859 5877 }
5860 5878
5861 5879 /*
5862 5880 * If polling, interrupt was triggered by some shared interrupt because
5863 5881 * IOC interrupts are disabled during polling, so polling routine will
5864 5882 * handle any replies. Considering this, if polling is happening,
5865 5883 * return with interrupt unclaimed.
5866 5884 */
5867 5885 if (mpt->m_polled_intr) {
5868 5886 mutex_exit(&mpt->m_mutex);
5869 5887 mptsas_log(mpt, CE_WARN, "mpt_sas: Unclaimed interrupt");
5870 5888 return (DDI_INTR_UNCLAIMED);
5871 5889 }
5872 5890
5873 5891 /*
5874 5892 * Read the istat register.
5875 5893 */
5876 5894 if ((INTPENDING(mpt)) != 0) {
5877 5895 /*
5878 5896 * read fifo until empty.
5879 5897 */
5880 5898 #ifndef __lock_lint
5881 5899 _NOTE(CONSTCOND)
5882 5900 #endif
5883 5901 while (TRUE) {
5884 5902 (void) ddi_dma_sync(mpt->m_dma_post_queue_hdl, 0, 0,
5885 5903 DDI_DMA_SYNC_FORCPU);
5886 5904 reply_desc_union = (pMpi2ReplyDescriptorsUnion_t)
5887 5905 MPTSAS_GET_NEXT_REPLY(mpt, mpt->m_post_index);
5888 5906
5889 5907 if (ddi_get32(mpt->m_acc_post_queue_hdl,
5890 5908 &reply_desc_union->Words.Low) == 0xFFFFFFFF ||
5891 5909 ddi_get32(mpt->m_acc_post_queue_hdl,
5892 5910 &reply_desc_union->Words.High) == 0xFFFFFFFF) {
5893 5911 break;
5894 5912 }
5895 5913
5896 5914 /*
5897 5915 * The reply is valid, process it according to its
5898 5916 * type. Also, set a flag for updating the reply index
5899 5917 * after they've all been processed.
5900 5918 */
5901 5919 did_reply = TRUE;
5902 5920
5903 5921 mptsas_process_intr(mpt, reply_desc_union);
5904 5922
5905 5923 /*
5906 5924 * Increment post index and roll over if needed.
5907 5925 */
5908 5926 if (++mpt->m_post_index == mpt->m_post_queue_depth) {
5909 5927 mpt->m_post_index = 0;
5910 5928 }
5911 5929 }
5912 5930
5913 5931 /*
5914 5932 * Update the global reply index if at least one reply was
5915 5933 * processed.
5916 5934 */
5917 5935 if (did_reply) {
5918 5936 ddi_put32(mpt->m_datap,
5919 5937 &mpt->m_reg->ReplyPostHostIndex, mpt->m_post_index);
5920 5938 }
5921 5939 } else {
5922 5940 mutex_exit(&mpt->m_mutex);
5923 5941 return (DDI_INTR_UNCLAIMED);
5924 5942 }
5925 5943 NDBG1(("mptsas_intr complete"));
5926 5944
5927 5945 /*
5928 5946 * If no helper threads are created, process the doneq in ISR. If
5929 5947 * helpers are created, use the doneq length as a metric to measure the
5930 5948 * load on the interrupt CPU. If it is long enough, which indicates the
5931 5949 * load is heavy, then we deliver the IO completions to the helpers.
5932 5950 * This measurement has some limitations, although it is simple and
5933 5951 * straightforward and works well for most of the cases at present.
5934 5952 */
5935 5953 if (!mpt->m_doneq_thread_n ||
5936 5954 (mpt->m_doneq_len <= mpt->m_doneq_length_threshold)) {
5937 5955 mptsas_doneq_empty(mpt);
5938 5956 } else {
5939 5957 mptsas_deliver_doneq_thread(mpt);
5940 5958 }
5941 5959
5942 5960 /*
5943 5961 * If there are queued cmd, start them now.
5944 5962 */
5945 5963 if (mpt->m_waitq != NULL) {
5946 5964 mptsas_restart_waitq(mpt);
5947 5965 }
5948 5966
5949 5967 mutex_exit(&mpt->m_mutex);
5950 5968 return (DDI_INTR_CLAIMED);
5951 5969 }
5952 5970
5953 5971 static void
5954 5972 mptsas_process_intr(mptsas_t *mpt,
5955 5973 pMpi2ReplyDescriptorsUnion_t reply_desc_union)
5956 5974 {
5957 5975 uint8_t reply_type;
5958 5976
5959 5977 ASSERT(mutex_owned(&mpt->m_mutex));
5960 5978
5961 5979 /*
5962 5980 * The reply is valid, process it according to its
5963 5981 * type. Also, set a flag for updated the reply index
5964 5982 * after they've all been processed.
5965 5983 */
5966 5984 reply_type = ddi_get8(mpt->m_acc_post_queue_hdl,
5967 5985 &reply_desc_union->Default.ReplyFlags);
5968 5986 reply_type &= MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK;
5969 5987 if (reply_type == MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS ||
5970 5988 reply_type == MPI25_RPY_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO_SUCCESS) {
5971 5989 mptsas_handle_scsi_io_success(mpt, reply_desc_union);
5972 5990 } else if (reply_type == MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY) {
5973 5991 mptsas_handle_address_reply(mpt, reply_desc_union);
5974 5992 } else {
5975 5993 mptsas_log(mpt, CE_WARN, "?Bad reply type %x", reply_type);
5976 5994 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
5977 5995 }
5978 5996
5979 5997 /*
5980 5998 * Clear the reply descriptor for re-use and increment
5981 5999 * index.
5982 6000 */
5983 6001 ddi_put64(mpt->m_acc_post_queue_hdl,
5984 6002 &((uint64_t *)(void *)mpt->m_post_queue)[mpt->m_post_index],
5985 6003 0xFFFFFFFFFFFFFFFF);
5986 6004 (void) ddi_dma_sync(mpt->m_dma_post_queue_hdl, 0, 0,
5987 6005 DDI_DMA_SYNC_FORDEV);
5988 6006 }
5989 6007
5990 6008 /*
5991 6009 * handle qfull condition
5992 6010 */
5993 6011 static void
5994 6012 mptsas_handle_qfull(mptsas_t *mpt, mptsas_cmd_t *cmd)
5995 6013 {
5996 6014 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
5997 6015
5998 6016 if ((++cmd->cmd_qfull_retries > ptgt->m_qfull_retries) ||
5999 6017 (ptgt->m_qfull_retries == 0)) {
6000 6018 /*
6001 6019 * We have exhausted the retries on QFULL, or,
6002 6020 * the target driver has indicated that it
6003 6021 * wants to handle QFULL itself by setting
6004 6022 * qfull-retries capability to 0. In either case
6005 6023 * we want the target driver's QFULL handling
6006 6024 * to kick in. We do this by having pkt_reason
6007 6025 * as CMD_CMPLT and pkt_scbp as STATUS_QFULL.
6008 6026 */
6009 6027 mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE);
6010 6028 } else {
6011 6029 if (ptgt->m_reset_delay == 0) {
6012 6030 ptgt->m_t_throttle =
6013 6031 max((ptgt->m_t_ncmds - 2), 0);
6014 6032 }
6015 6033
6016 6034 cmd->cmd_pkt_flags |= FLAG_HEAD;
6017 6035 cmd->cmd_flags &= ~(CFLAG_TRANFLAG);
6018 6036 cmd->cmd_flags |= CFLAG_RETRY;
6019 6037
6020 6038 (void) mptsas_accept_pkt(mpt, cmd);
6021 6039
6022 6040 /*
6023 6041 * when target gives queue full status with no commands
6024 6042 * outstanding (m_t_ncmds == 0), throttle is set to 0
6025 6043 * (HOLD_THROTTLE), and the queue full handling start
6026 6044 * (see psarc/1994/313); if there are commands outstanding,
6027 6045 * throttle is set to (m_t_ncmds - 2)
6028 6046 */
6029 6047 if (ptgt->m_t_throttle == HOLD_THROTTLE) {
6030 6048 /*
6031 6049 * By setting throttle to QFULL_THROTTLE, we
6032 6050 * avoid submitting new commands and in
6033 6051 * mptsas_restart_cmd find out slots which need
6034 6052 * their throttles to be cleared.
6035 6053 */
6036 6054 mptsas_set_throttle(mpt, ptgt, QFULL_THROTTLE);
6037 6055 if (mpt->m_restart_cmd_timeid == 0) {
6038 6056 mpt->m_restart_cmd_timeid =
6039 6057 timeout(mptsas_restart_cmd, mpt,
6040 6058 ptgt->m_qfull_retry_interval);
6041 6059 }
6042 6060 }
6043 6061 }
6044 6062 }
6045 6063
6046 6064 mptsas_phymask_t
6047 6065 mptsas_physport_to_phymask(mptsas_t *mpt, uint8_t physport)
6048 6066 {
6049 6067 mptsas_phymask_t phy_mask = 0;
6050 6068 uint8_t i = 0;
6051 6069
6052 6070 NDBG20(("mptsas%d physport_to_phymask enter", mpt->m_instance));
6053 6071
6054 6072 ASSERT(mutex_owned(&mpt->m_mutex));
6055 6073
6056 6074 /*
6057 6075 * If physport is 0xFF, this is a RAID volume. Use phymask of 0.
6058 6076 */
6059 6077 if (physport == 0xFF) {
6060 6078 return (0);
6061 6079 }
6062 6080
6063 6081 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
6064 6082 if (mpt->m_phy_info[i].attached_devhdl &&
6065 6083 (mpt->m_phy_info[i].phy_mask != 0) &&
6066 6084 (mpt->m_phy_info[i].port_num == physport)) {
6067 6085 phy_mask = mpt->m_phy_info[i].phy_mask;
6068 6086 break;
6069 6087 }
6070 6088 }
6071 6089 NDBG20(("mptsas%d physport_to_phymask:physport :%x phymask :%x, ",
6072 6090 mpt->m_instance, physport, phy_mask));
6073 6091 return (phy_mask);
6074 6092 }
6075 6093
6076 6094 /*
6077 6095 * mpt free device handle after device gone, by use of passthrough
6078 6096 */
6079 6097 static int
6080 6098 mptsas_free_devhdl(mptsas_t *mpt, uint16_t devhdl)
6081 6099 {
6082 6100 Mpi2SasIoUnitControlRequest_t req;
6083 6101 Mpi2SasIoUnitControlReply_t rep;
6084 6102 int ret;
6085 6103
6086 6104 ASSERT(mutex_owned(&mpt->m_mutex));
6087 6105
6088 6106 /*
6089 6107 * Need to compose a SAS IO Unit Control request message
6090 6108 * and call mptsas_do_passthru() function
6091 6109 */
6092 6110 bzero(&req, sizeof (req));
6093 6111 bzero(&rep, sizeof (rep));
6094 6112
6095 6113 req.Function = MPI2_FUNCTION_SAS_IO_UNIT_CONTROL;
6096 6114 req.Operation = MPI2_SAS_OP_REMOVE_DEVICE;
6097 6115 req.DevHandle = LE_16(devhdl);
6098 6116
6099 6117 ret = mptsas_do_passthru(mpt, (uint8_t *)&req, (uint8_t *)&rep, NULL,
6100 6118 sizeof (req), sizeof (rep), NULL, 0, NULL, 0, 60, FKIOCTL);
6101 6119 if (ret != 0) {
6102 6120 cmn_err(CE_WARN, "mptsas_free_devhdl: passthru SAS IO Unit "
6103 6121 "Control error %d", ret);
6104 6122 return (DDI_FAILURE);
6105 6123 }
6106 6124
6107 6125 /* do passthrough success, check the ioc status */
6108 6126 if (LE_16(rep.IOCStatus) != MPI2_IOCSTATUS_SUCCESS) {
6109 6127 cmn_err(CE_WARN, "mptsas_free_devhdl: passthru SAS IO Unit "
6110 6128 "Control IOCStatus %d", LE_16(rep.IOCStatus));
6111 6129 return (DDI_FAILURE);
6112 6130 }
6113 6131
6114 6132 return (DDI_SUCCESS);
6115 6133 }
6116 6134
6117 6135 static void
6118 6136 mptsas_update_phymask(mptsas_t *mpt)
6119 6137 {
6120 6138 mptsas_phymask_t mask = 0, phy_mask;
6121 6139 char *phy_mask_name;
6122 6140 uint8_t current_port;
6123 6141 int i, j;
6124 6142
6125 6143 NDBG20(("mptsas%d update phymask ", mpt->m_instance));
6126 6144
6127 6145 ASSERT(mutex_owned(&mpt->m_mutex));
6128 6146
6129 6147 (void) mptsas_get_sas_io_unit_page(mpt);
6130 6148
6131 6149 phy_mask_name = kmem_zalloc(MPTSAS_MAX_PHYS, KM_SLEEP);
6132 6150
6133 6151 for (i = 0; i < mpt->m_num_phys; i++) {
6134 6152 phy_mask = 0x00;
6135 6153
6136 6154 if (mpt->m_phy_info[i].attached_devhdl == 0)
6137 6155 continue;
6138 6156
6139 6157 bzero(phy_mask_name, sizeof (phy_mask_name));
6140 6158
6141 6159 current_port = mpt->m_phy_info[i].port_num;
6142 6160
6143 6161 if ((mask & (1 << i)) != 0)
6144 6162 continue;
6145 6163
6146 6164 for (j = 0; j < mpt->m_num_phys; j++) {
6147 6165 if (mpt->m_phy_info[j].attached_devhdl &&
6148 6166 (mpt->m_phy_info[j].port_num == current_port)) {
6149 6167 phy_mask |= (1 << j);
6150 6168 }
6151 6169 }
6152 6170 mask = mask | phy_mask;
6153 6171
6154 6172 for (j = 0; j < mpt->m_num_phys; j++) {
6155 6173 if ((phy_mask >> j) & 0x01) {
6156 6174 mpt->m_phy_info[j].phy_mask = phy_mask;
6157 6175 }
6158 6176 }
6159 6177
6160 6178 (void) sprintf(phy_mask_name, "%x", phy_mask);
6161 6179
6162 6180 mutex_exit(&mpt->m_mutex);
6163 6181 /*
6164 6182 * register a iport, if the port has already been existed
6165 6183 * SCSA will do nothing and just return.
6166 6184 */
6167 6185 (void) scsi_hba_iport_register(mpt->m_dip, phy_mask_name);
6168 6186 mutex_enter(&mpt->m_mutex);
6169 6187 }
6170 6188 kmem_free(phy_mask_name, MPTSAS_MAX_PHYS);
6171 6189 NDBG20(("mptsas%d update phymask return", mpt->m_instance));
6172 6190 }
6173 6191
6174 6192 /*
6175 6193 * mptsas_handle_dr is a task handler for DR, the DR action includes:
6176 6194 * 1. Directly attched Device Added/Removed.
6177 6195 * 2. Expander Device Added/Removed.
6178 6196 * 3. Indirectly Attached Device Added/Expander.
6179 6197 * 4. LUNs of a existing device status change.
6180 6198 * 5. RAID volume created/deleted.
6181 6199 * 6. Member of RAID volume is released because of RAID deletion.
6182 6200 * 7. Physical disks are removed because of RAID creation.
6183 6201 */
6184 6202 static void
6185 6203 mptsas_handle_dr(void *args)
6186 6204 {
6187 6205 mptsas_topo_change_list_t *topo_node = NULL;
6188 6206 mptsas_topo_change_list_t *save_node = NULL;
6189 6207 mptsas_t *mpt;
6190 6208 dev_info_t *parent = NULL;
6191 6209 mptsas_phymask_t phymask = 0;
6192 6210 char *phy_mask_name;
6193 6211 uint8_t flags = 0, physport = 0xff;
6194 6212 uint8_t port_update = 0;
6195 6213 uint_t event;
6196 6214
6197 6215 topo_node = (mptsas_topo_change_list_t *)args;
6198 6216
6199 6217 mpt = topo_node->mpt;
6200 6218 event = topo_node->event;
6201 6219 flags = topo_node->flags;
6202 6220
6203 6221 phy_mask_name = kmem_zalloc(MPTSAS_MAX_PHYS, KM_SLEEP);
6204 6222
6205 6223 NDBG20(("mptsas%d handle_dr enter", mpt->m_instance));
6206 6224
6207 6225 switch (event) {
6208 6226 case MPTSAS_DR_EVENT_RECONFIG_TARGET:
6209 6227 if ((flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) ||
6210 6228 (flags == MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE) ||
6211 6229 (flags == MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED)) {
6212 6230 /*
6213 6231 * Direct attached or expander attached device added
6214 6232 * into system or a Phys Disk that is being unhidden.
6215 6233 */
6216 6234 port_update = 1;
6217 6235 }
6218 6236 break;
6219 6237 case MPTSAS_DR_EVENT_RECONFIG_SMP:
6220 6238 /*
6221 6239 * New expander added into system, it must be the head
6222 6240 * of topo_change_list_t
6223 6241 */
6224 6242 port_update = 1;
6225 6243 break;
6226 6244 default:
6227 6245 port_update = 0;
6228 6246 break;
6229 6247 }
6230 6248 /*
6231 6249 * All cases port_update == 1 may cause initiator port form change
6232 6250 */
6233 6251 mutex_enter(&mpt->m_mutex);
6234 6252 if (mpt->m_port_chng && port_update) {
6235 6253 /*
6236 6254 * mpt->m_port_chng flag indicates some PHYs of initiator
6237 6255 * port have changed to online. So when expander added or
6238 6256 * directly attached device online event come, we force to
6239 6257 * update port information by issueing SAS IO Unit Page and
6240 6258 * update PHYMASKs.
6241 6259 */
6242 6260 (void) mptsas_update_phymask(mpt);
6243 6261 mpt->m_port_chng = 0;
6244 6262
6245 6263 }
6246 6264 mutex_exit(&mpt->m_mutex);
6247 6265 while (topo_node) {
6248 6266 phymask = 0;
6249 6267 if (parent == NULL) {
6250 6268 physport = topo_node->un.physport;
6251 6269 event = topo_node->event;
6252 6270 flags = topo_node->flags;
6253 6271 if (event & (MPTSAS_DR_EVENT_OFFLINE_TARGET |
6254 6272 MPTSAS_DR_EVENT_OFFLINE_SMP)) {
6255 6273 /*
6256 6274 * For all offline events, phymask is known
6257 6275 */
6258 6276 phymask = topo_node->un.phymask;
6259 6277 goto find_parent;
6260 6278 }
6261 6279 if (event & MPTSAS_TOPO_FLAG_REMOVE_HANDLE) {
6262 6280 goto handle_topo_change;
6263 6281 }
6264 6282 if (flags & MPTSAS_TOPO_FLAG_LUN_ASSOCIATED) {
6265 6283 phymask = topo_node->un.phymask;
6266 6284 goto find_parent;
6267 6285 }
6268 6286
6269 6287 if ((flags ==
6270 6288 MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED) &&
6271 6289 (event == MPTSAS_DR_EVENT_RECONFIG_TARGET)) {
6272 6290 /*
6273 6291 * There is no any field in IR_CONFIG_CHANGE
6274 6292 * event indicate physport/phynum, let's get
6275 6293 * parent after SAS Device Page0 request.
6276 6294 */
6277 6295 goto handle_topo_change;
6278 6296 }
6279 6297
6280 6298 mutex_enter(&mpt->m_mutex);
6281 6299 if (flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) {
6282 6300 /*
6283 6301 * If the direct attached device added or a
6284 6302 * phys disk is being unhidden, argument
6285 6303 * physport actually is PHY#, so we have to get
6286 6304 * phymask according PHY#.
6287 6305 */
6288 6306 physport = mpt->m_phy_info[physport].port_num;
6289 6307 }
6290 6308
6291 6309 /*
6292 6310 * Translate physport to phymask so that we can search
6293 6311 * parent dip.
6294 6312 */
6295 6313 phymask = mptsas_physport_to_phymask(mpt,
6296 6314 physport);
6297 6315 mutex_exit(&mpt->m_mutex);
6298 6316
6299 6317 find_parent:
6300 6318 bzero(phy_mask_name, MPTSAS_MAX_PHYS);
6301 6319 /*
6302 6320 * For RAID topology change node, write the iport name
6303 6321 * as v0.
6304 6322 */
6305 6323 if (flags & MPTSAS_TOPO_FLAG_RAID_ASSOCIATED) {
6306 6324 (void) sprintf(phy_mask_name, "v0");
6307 6325 } else {
6308 6326 /*
6309 6327 * phymask can bo 0 if the drive has been
6310 6328 * pulled by the time an add event is
6311 6329 * processed. If phymask is 0, just skip this
6312 6330 * event and continue.
6313 6331 */
6314 6332 if (phymask == 0) {
6315 6333 mutex_enter(&mpt->m_mutex);
6316 6334 save_node = topo_node;
6317 6335 topo_node = topo_node->next;
6318 6336 ASSERT(save_node);
6319 6337 kmem_free(save_node,
6320 6338 sizeof (mptsas_topo_change_list_t));
6321 6339 mutex_exit(&mpt->m_mutex);
6322 6340
6323 6341 parent = NULL;
6324 6342 continue;
6325 6343 }
6326 6344 (void) sprintf(phy_mask_name, "%x", phymask);
6327 6345 }
6328 6346 parent = scsi_hba_iport_find(mpt->m_dip,
6329 6347 phy_mask_name);
6330 6348 if (parent == NULL) {
6331 6349 mptsas_log(mpt, CE_WARN, "Failed to find an "
6332 6350 "iport, should not happen!");
6333 6351 goto out;
6334 6352 }
↓ open down ↓ |
946 lines elided |
↑ open up ↑ |
6335 6353
6336 6354 }
6337 6355 ASSERT(parent);
6338 6356 handle_topo_change:
6339 6357
6340 6358 mutex_enter(&mpt->m_mutex);
6341 6359 /*
6342 6360 * If HBA is being reset, don't perform operations depending
6343 6361 * on the IOC. We must free the topo list, however.
6344 6362 */
6345 - if (!mpt->m_in_reset)
6363 +
6364 + mutex_enter(&mpt->m_taskmgmt_mutex);
6365 + if (mpt->m_in_reset == FALSE)
6346 6366 mptsas_handle_topo_change(topo_node, parent);
6347 - else
6348 - NDBG20(("skipping topo change received during reset"));
6367 + mutex_exit(&mpt->m_taskmgmt_mutex);
6368 +
6349 6369 save_node = topo_node;
6350 6370 topo_node = topo_node->next;
6351 6371 ASSERT(save_node);
6352 6372 kmem_free(save_node, sizeof (mptsas_topo_change_list_t));
6353 6373 mutex_exit(&mpt->m_mutex);
6354 6374
6355 6375 if ((flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) ||
6356 6376 (flags == MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED) ||
6357 6377 (flags == MPTSAS_TOPO_FLAG_RAID_ASSOCIATED)) {
6358 6378 /*
6359 6379 * If direct attached device associated, make sure
6360 6380 * reset the parent before start the next one. But
6361 6381 * all devices associated with expander shares the
6362 6382 * parent. Also, reset parent if this is for RAID.
6363 6383 */
6364 6384 parent = NULL;
6365 6385 }
6366 6386 }
6367 6387 out:
6368 6388 kmem_free(phy_mask_name, MPTSAS_MAX_PHYS);
6369 6389 }
6370 6390
6371 6391 static void
6372 6392 mptsas_handle_topo_change(mptsas_topo_change_list_t *topo_node,
6373 6393 dev_info_t *parent)
6374 6394 {
6375 6395 mptsas_target_t *ptgt = NULL;
6376 6396 mptsas_smp_t *psmp = NULL;
6377 6397 mptsas_t *mpt = (void *)topo_node->mpt;
6378 6398 uint16_t devhdl;
6379 6399 uint16_t attached_devhdl;
6380 6400 uint64_t sas_wwn = 0;
6381 6401 int rval = 0;
6382 6402 uint32_t page_address;
6383 6403 uint8_t phy, flags;
6384 6404 char *addr = NULL;
6385 6405 dev_info_t *lundip;
6386 6406 int circ = 0, circ1 = 0;
6387 6407 char attached_wwnstr[MPTSAS_WWN_STRLEN];
6388 6408
6389 6409 NDBG20(("mptsas%d handle_topo_change enter, devhdl 0x%x,"
6390 6410 "event 0x%x, flags 0x%x", mpt->m_instance, topo_node->devhdl,
6391 6411 topo_node->event, topo_node->flags));
6392 6412
6393 6413 ASSERT(mutex_owned(&mpt->m_mutex));
6394 6414
6395 6415 switch (topo_node->event) {
6396 6416 case MPTSAS_DR_EVENT_RECONFIG_TARGET:
6397 6417 {
6398 6418 char *phy_mask_name;
6399 6419 mptsas_phymask_t phymask = 0;
6400 6420
6401 6421 if (topo_node->flags == MPTSAS_TOPO_FLAG_RAID_ASSOCIATED) {
6402 6422 /*
6403 6423 * Get latest RAID info.
6404 6424 */
6405 6425 (void) mptsas_get_raid_info(mpt);
6406 6426 ptgt = refhash_linear_search(mpt->m_targets,
6407 6427 mptsas_target_eval_devhdl, &topo_node->devhdl);
6408 6428 if (ptgt == NULL)
6409 6429 break;
6410 6430 } else {
6411 6431 ptgt = (void *)topo_node->object;
6412 6432 }
6413 6433
6414 6434 if (ptgt == NULL) {
6415 6435 /*
6416 6436 * If a Phys Disk was deleted, RAID info needs to be
6417 6437 * updated to reflect the new topology.
6418 6438 */
6419 6439 (void) mptsas_get_raid_info(mpt);
6420 6440
6421 6441 /*
6422 6442 * Get sas device page 0 by DevHandle to make sure if
6423 6443 * SSP/SATA end device exist.
6424 6444 */
6425 6445 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE &
6426 6446 MPI2_SAS_DEVICE_PGAD_FORM_MASK) |
6427 6447 topo_node->devhdl;
6428 6448
6429 6449 rval = mptsas_get_target_device_info(mpt, page_address,
6430 6450 &devhdl, &ptgt);
6431 6451 if (rval == DEV_INFO_WRONG_DEVICE_TYPE) {
6432 6452 mptsas_log(mpt, CE_NOTE,
6433 6453 "mptsas_handle_topo_change: target %d is "
6434 6454 "not a SAS/SATA device. \n",
6435 6455 topo_node->devhdl);
6436 6456 } else if (rval == DEV_INFO_FAIL_ALLOC) {
6437 6457 mptsas_log(mpt, CE_NOTE,
6438 6458 "mptsas_handle_topo_change: could not "
6439 6459 "allocate memory. \n");
6440 6460 } else if (rval == DEV_INFO_FAIL_GUID) {
6441 6461 mptsas_log(mpt, CE_NOTE,
6442 6462 "mptsas_handle_topo_change: could not "
6443 6463 "get SATA GUID for target %d. \n",
6444 6464 topo_node->devhdl);
6445 6465 }
6446 6466 /*
6447 6467 * If rval is DEV_INFO_PHYS_DISK or indicates failure
6448 6468 * then there is nothing else to do, just leave.
6449 6469 */
6450 6470 if (rval != DEV_INFO_SUCCESS) {
6451 6471 return;
6452 6472 }
6453 6473 }
6454 6474
6455 6475 ASSERT(ptgt->m_devhdl == topo_node->devhdl);
6456 6476
6457 6477 mutex_exit(&mpt->m_mutex);
6458 6478 flags = topo_node->flags;
6459 6479
6460 6480 if (flags == MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED) {
6461 6481 phymask = ptgt->m_addr.mta_phymask;
6462 6482 phy_mask_name = kmem_zalloc(MPTSAS_MAX_PHYS, KM_SLEEP);
6463 6483 (void) sprintf(phy_mask_name, "%x", phymask);
6464 6484 parent = scsi_hba_iport_find(mpt->m_dip,
6465 6485 phy_mask_name);
6466 6486 kmem_free(phy_mask_name, MPTSAS_MAX_PHYS);
6467 6487 if (parent == NULL) {
6468 6488 mptsas_log(mpt, CE_WARN, "Failed to find a "
6469 6489 "iport for PD, should not happen!");
6470 6490 mutex_enter(&mpt->m_mutex);
6471 6491 break;
6472 6492 }
6473 6493 }
6474 6494
6475 6495 if (flags == MPTSAS_TOPO_FLAG_RAID_ASSOCIATED) {
6476 6496 ndi_devi_enter(parent, &circ1);
6477 6497 (void) mptsas_config_raid(parent, topo_node->devhdl,
6478 6498 &lundip);
6479 6499 ndi_devi_exit(parent, circ1);
6480 6500 } else {
6481 6501 /*
6482 6502 * hold nexus for bus configure
6483 6503 */
6484 6504 ndi_devi_enter(scsi_vhci_dip, &circ);
6485 6505 ndi_devi_enter(parent, &circ1);
6486 6506 rval = mptsas_config_target(parent, ptgt);
6487 6507 /*
6488 6508 * release nexus for bus configure
6489 6509 */
6490 6510 ndi_devi_exit(parent, circ1);
6491 6511 ndi_devi_exit(scsi_vhci_dip, circ);
6492 6512
6493 6513 /*
6494 6514 * Add parent's props for SMHBA support
6495 6515 */
6496 6516 if (flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) {
6497 6517 bzero(attached_wwnstr,
6498 6518 sizeof (attached_wwnstr));
6499 6519 (void) sprintf(attached_wwnstr, "w%016"PRIx64,
6500 6520 ptgt->m_addr.mta_wwn);
6501 6521 if (ddi_prop_update_string(DDI_DEV_T_NONE,
6502 6522 parent,
6503 6523 SCSI_ADDR_PROP_ATTACHED_PORT,
6504 6524 attached_wwnstr)
6505 6525 != DDI_PROP_SUCCESS) {
6506 6526 (void) ddi_prop_remove(DDI_DEV_T_NONE,
6507 6527 parent,
6508 6528 SCSI_ADDR_PROP_ATTACHED_PORT);
6509 6529 mptsas_log(mpt, CE_WARN, "Failed to"
6510 6530 "attached-port props");
6511 6531 return;
6512 6532 }
6513 6533 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent,
6514 6534 MPTSAS_NUM_PHYS, 1) !=
6515 6535 DDI_PROP_SUCCESS) {
6516 6536 (void) ddi_prop_remove(DDI_DEV_T_NONE,
6517 6537 parent, MPTSAS_NUM_PHYS);
6518 6538 mptsas_log(mpt, CE_WARN, "Failed to"
6519 6539 " create num-phys props");
6520 6540 return;
6521 6541 }
6522 6542
6523 6543 /*
6524 6544 * Update PHY info for smhba
6525 6545 */
6526 6546 mutex_enter(&mpt->m_mutex);
6527 6547 if (mptsas_smhba_phy_init(mpt)) {
6528 6548 mutex_exit(&mpt->m_mutex);
6529 6549 mptsas_log(mpt, CE_WARN, "mptsas phy"
6530 6550 " update failed");
6531 6551 return;
6532 6552 }
6533 6553 mutex_exit(&mpt->m_mutex);
6534 6554
6535 6555 /*
6536 6556 * topo_node->un.physport is really the PHY#
6537 6557 * for direct attached devices
6538 6558 */
6539 6559 mptsas_smhba_set_one_phy_props(mpt, parent,
6540 6560 topo_node->un.physport, &attached_devhdl);
6541 6561
6542 6562 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent,
6543 6563 MPTSAS_VIRTUAL_PORT, 0) !=
6544 6564 DDI_PROP_SUCCESS) {
6545 6565 (void) ddi_prop_remove(DDI_DEV_T_NONE,
6546 6566 parent, MPTSAS_VIRTUAL_PORT);
6547 6567 mptsas_log(mpt, CE_WARN,
6548 6568 "mptsas virtual-port"
6549 6569 "port prop update failed");
6550 6570 return;
6551 6571 }
6552 6572 }
6553 6573 }
6554 6574 mutex_enter(&mpt->m_mutex);
6555 6575
6556 6576 NDBG20(("mptsas%d handle_topo_change to online devhdl:%x, "
6557 6577 "phymask:%x.", mpt->m_instance, ptgt->m_devhdl,
6558 6578 ptgt->m_addr.mta_phymask));
6559 6579 break;
6560 6580 }
6561 6581 case MPTSAS_DR_EVENT_OFFLINE_TARGET:
6562 6582 {
6563 6583 devhdl = topo_node->devhdl;
6564 6584 ptgt = refhash_linear_search(mpt->m_targets,
6565 6585 mptsas_target_eval_devhdl, &devhdl);
6566 6586 if (ptgt == NULL)
6567 6587 break;
6568 6588
6569 6589 sas_wwn = ptgt->m_addr.mta_wwn;
6570 6590 phy = ptgt->m_phynum;
6571 6591
6572 6592 addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
6573 6593
6574 6594 if (sas_wwn) {
6575 6595 (void) sprintf(addr, "w%016"PRIx64, sas_wwn);
6576 6596 } else {
6577 6597 (void) sprintf(addr, "p%x", phy);
6578 6598 }
6579 6599 ASSERT(ptgt->m_devhdl == devhdl);
6580 6600
6581 6601 if ((topo_node->flags == MPTSAS_TOPO_FLAG_RAID_ASSOCIATED) ||
6582 6602 (topo_node->flags ==
6583 6603 MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED)) {
6584 6604 /*
6585 6605 * Get latest RAID info if RAID volume status changes
6586 6606 * or Phys Disk status changes
6587 6607 */
6588 6608 (void) mptsas_get_raid_info(mpt);
6589 6609 }
6590 6610 /*
6591 6611 * Abort all outstanding command on the device
6592 6612 */
6593 6613 rval = mptsas_do_scsi_reset(mpt, devhdl);
6594 6614 if (rval) {
6595 6615 NDBG20(("mptsas%d handle_topo_change to reset target "
6596 6616 "before offline devhdl:%x, phymask:%x, rval:%x",
6597 6617 mpt->m_instance, ptgt->m_devhdl,
6598 6618 ptgt->m_addr.mta_phymask, rval));
6599 6619 }
6600 6620
6601 6621 mutex_exit(&mpt->m_mutex);
6602 6622
6603 6623 ndi_devi_enter(scsi_vhci_dip, &circ);
6604 6624 ndi_devi_enter(parent, &circ1);
6605 6625 rval = mptsas_offline_target(parent, addr);
6606 6626 ndi_devi_exit(parent, circ1);
6607 6627 ndi_devi_exit(scsi_vhci_dip, circ);
6608 6628 NDBG20(("mptsas%d handle_topo_change to offline devhdl:%x, "
6609 6629 "phymask:%x, rval:%x", mpt->m_instance,
6610 6630 ptgt->m_devhdl, ptgt->m_addr.mta_phymask, rval));
6611 6631
6612 6632 kmem_free(addr, SCSI_MAXNAMELEN);
6613 6633
6614 6634 /*
6615 6635 * Clear parent's props for SMHBA support
6616 6636 */
6617 6637 flags = topo_node->flags;
6618 6638 if (flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) {
6619 6639 bzero(attached_wwnstr, sizeof (attached_wwnstr));
6620 6640 if (ddi_prop_update_string(DDI_DEV_T_NONE, parent,
6621 6641 SCSI_ADDR_PROP_ATTACHED_PORT, attached_wwnstr) !=
6622 6642 DDI_PROP_SUCCESS) {
6623 6643 (void) ddi_prop_remove(DDI_DEV_T_NONE, parent,
6624 6644 SCSI_ADDR_PROP_ATTACHED_PORT);
6625 6645 mptsas_log(mpt, CE_WARN, "mptsas attached port "
6626 6646 "prop update failed");
6627 6647 break;
6628 6648 }
6629 6649 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent,
6630 6650 MPTSAS_NUM_PHYS, 0) !=
6631 6651 DDI_PROP_SUCCESS) {
6632 6652 (void) ddi_prop_remove(DDI_DEV_T_NONE, parent,
6633 6653 MPTSAS_NUM_PHYS);
6634 6654 mptsas_log(mpt, CE_WARN, "mptsas num phys "
6635 6655 "prop update failed");
6636 6656 break;
6637 6657 }
6638 6658 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent,
6639 6659 MPTSAS_VIRTUAL_PORT, 1) !=
6640 6660 DDI_PROP_SUCCESS) {
6641 6661 (void) ddi_prop_remove(DDI_DEV_T_NONE, parent,
6642 6662 MPTSAS_VIRTUAL_PORT);
6643 6663 mptsas_log(mpt, CE_WARN, "mptsas virtual port "
6644 6664 "prop update failed");
6645 6665 break;
6646 6666 }
6647 6667 }
6648 6668
6649 6669 mutex_enter(&mpt->m_mutex);
6650 6670 ptgt->m_led_status = 0;
6651 6671 (void) mptsas_flush_led_status(mpt, ptgt);
6652 6672 if (rval == DDI_SUCCESS) {
6653 6673 refhash_remove(mpt->m_targets, ptgt);
6654 6674 ptgt = NULL;
6655 6675 } else {
6656 6676 /*
6657 6677 * clean DR_INTRANSITION flag to allow I/O down to
6658 6678 * PHCI driver since failover finished.
6659 6679 * Invalidate the devhdl
6660 6680 */
6661 6681 ptgt->m_devhdl = MPTSAS_INVALID_DEVHDL;
6662 6682 ptgt->m_tgt_unconfigured = 0;
6663 6683 mutex_enter(&mpt->m_tx_waitq_mutex);
6664 6684 ptgt->m_dr_flag = MPTSAS_DR_INACTIVE;
6665 6685 mutex_exit(&mpt->m_tx_waitq_mutex);
6666 6686 }
6667 6687
6668 6688 /*
6669 6689 * Send SAS IO Unit Control to free the dev handle
6670 6690 */
6671 6691 if ((flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) ||
6672 6692 (flags == MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE)) {
6673 6693 rval = mptsas_free_devhdl(mpt, devhdl);
6674 6694
6675 6695 NDBG20(("mptsas%d handle_topo_change to remove "
6676 6696 "devhdl:%x, rval:%x", mpt->m_instance, devhdl,
6677 6697 rval));
6678 6698 }
6679 6699
6680 6700 break;
6681 6701 }
6682 6702 case MPTSAS_TOPO_FLAG_REMOVE_HANDLE:
6683 6703 {
6684 6704 devhdl = topo_node->devhdl;
6685 6705 /*
6686 6706 * If this is the remove handle event, do a reset first.
6687 6707 */
6688 6708 if (topo_node->event == MPTSAS_TOPO_FLAG_REMOVE_HANDLE) {
6689 6709 rval = mptsas_do_scsi_reset(mpt, devhdl);
6690 6710 if (rval) {
6691 6711 NDBG20(("mpt%d reset target before remove "
6692 6712 "devhdl:%x, rval:%x", mpt->m_instance,
6693 6713 devhdl, rval));
6694 6714 }
6695 6715 }
6696 6716
6697 6717 /*
6698 6718 * Send SAS IO Unit Control to free the dev handle
6699 6719 */
6700 6720 rval = mptsas_free_devhdl(mpt, devhdl);
6701 6721 NDBG20(("mptsas%d handle_topo_change to remove "
6702 6722 "devhdl:%x, rval:%x", mpt->m_instance, devhdl,
6703 6723 rval));
6704 6724 break;
6705 6725 }
6706 6726 case MPTSAS_DR_EVENT_RECONFIG_SMP:
6707 6727 {
6708 6728 mptsas_smp_t smp;
6709 6729 dev_info_t *smpdip;
6710 6730
6711 6731 devhdl = topo_node->devhdl;
6712 6732
6713 6733 page_address = (MPI2_SAS_EXPAND_PGAD_FORM_HNDL &
6714 6734 MPI2_SAS_EXPAND_PGAD_FORM_MASK) | (uint32_t)devhdl;
6715 6735 rval = mptsas_get_sas_expander_page0(mpt, page_address, &smp);
6716 6736 if (rval != DDI_SUCCESS) {
6717 6737 mptsas_log(mpt, CE_WARN, "failed to online smp, "
6718 6738 "handle %x", devhdl);
6719 6739 return;
6720 6740 }
6721 6741
6722 6742 psmp = mptsas_smp_alloc(mpt, &smp);
6723 6743 if (psmp == NULL) {
6724 6744 return;
6725 6745 }
6726 6746
6727 6747 mutex_exit(&mpt->m_mutex);
6728 6748 ndi_devi_enter(parent, &circ1);
6729 6749 (void) mptsas_online_smp(parent, psmp, &smpdip);
6730 6750 ndi_devi_exit(parent, circ1);
6731 6751
6732 6752 mutex_enter(&mpt->m_mutex);
6733 6753 break;
6734 6754 }
6735 6755 case MPTSAS_DR_EVENT_OFFLINE_SMP:
6736 6756 {
6737 6757 devhdl = topo_node->devhdl;
6738 6758 uint32_t dev_info;
6739 6759
6740 6760 psmp = refhash_linear_search(mpt->m_smp_targets,
6741 6761 mptsas_smp_eval_devhdl, &devhdl);
6742 6762 if (psmp == NULL)
6743 6763 break;
6744 6764 /*
6745 6765 * The mptsas_smp_t data is released only if the dip is offlined
6746 6766 * successfully.
6747 6767 */
6748 6768 mutex_exit(&mpt->m_mutex);
6749 6769
6750 6770 ndi_devi_enter(parent, &circ1);
6751 6771 rval = mptsas_offline_smp(parent, psmp, NDI_DEVI_REMOVE);
6752 6772 ndi_devi_exit(parent, circ1);
6753 6773
6754 6774 dev_info = psmp->m_deviceinfo;
6755 6775 if ((dev_info & DEVINFO_DIRECT_ATTACHED) ==
6756 6776 DEVINFO_DIRECT_ATTACHED) {
6757 6777 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent,
6758 6778 MPTSAS_VIRTUAL_PORT, 1) !=
6759 6779 DDI_PROP_SUCCESS) {
6760 6780 (void) ddi_prop_remove(DDI_DEV_T_NONE, parent,
6761 6781 MPTSAS_VIRTUAL_PORT);
6762 6782 mptsas_log(mpt, CE_WARN, "mptsas virtual port "
6763 6783 "prop update failed");
6764 6784 return;
6765 6785 }
6766 6786 /*
6767 6787 * Check whether the smp connected to the iport,
6768 6788 */
6769 6789 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent,
6770 6790 MPTSAS_NUM_PHYS, 0) !=
6771 6791 DDI_PROP_SUCCESS) {
6772 6792 (void) ddi_prop_remove(DDI_DEV_T_NONE, parent,
6773 6793 MPTSAS_NUM_PHYS);
6774 6794 mptsas_log(mpt, CE_WARN, "mptsas num phys"
6775 6795 "prop update failed");
6776 6796 return;
6777 6797 }
6778 6798 /*
6779 6799 * Clear parent's attached-port props
6780 6800 */
6781 6801 bzero(attached_wwnstr, sizeof (attached_wwnstr));
6782 6802 if (ddi_prop_update_string(DDI_DEV_T_NONE, parent,
6783 6803 SCSI_ADDR_PROP_ATTACHED_PORT, attached_wwnstr) !=
6784 6804 DDI_PROP_SUCCESS) {
6785 6805 (void) ddi_prop_remove(DDI_DEV_T_NONE, parent,
6786 6806 SCSI_ADDR_PROP_ATTACHED_PORT);
6787 6807 mptsas_log(mpt, CE_WARN, "mptsas attached port "
6788 6808 "prop update failed");
6789 6809 return;
6790 6810 }
6791 6811 }
6792 6812
6793 6813 mutex_enter(&mpt->m_mutex);
6794 6814 NDBG20(("mptsas%d handle_topo_change to remove devhdl:%x, "
6795 6815 "rval:%x", mpt->m_instance, psmp->m_devhdl, rval));
6796 6816 if (rval == DDI_SUCCESS) {
6797 6817 refhash_remove(mpt->m_smp_targets, psmp);
6798 6818 } else {
6799 6819 psmp->m_devhdl = MPTSAS_INVALID_DEVHDL;
6800 6820 }
6801 6821
6802 6822 bzero(attached_wwnstr, sizeof (attached_wwnstr));
6803 6823
6804 6824 break;
6805 6825 }
6806 6826 default:
6807 6827 return;
6808 6828 }
6809 6829 }
6810 6830
6811 6831 /*
6812 6832 * Record the event if its type is enabled in mpt instance by ioctl.
6813 6833 */
6814 6834 static void
6815 6835 mptsas_record_event(void *args)
6816 6836 {
6817 6837 m_replyh_arg_t *replyh_arg;
6818 6838 pMpi2EventNotificationReply_t eventreply;
6819 6839 uint32_t event, rfm;
6820 6840 mptsas_t *mpt;
6821 6841 int i, j;
6822 6842 uint16_t event_data_len;
6823 6843 boolean_t sendAEN = FALSE;
6824 6844
6825 6845 replyh_arg = (m_replyh_arg_t *)args;
6826 6846 rfm = replyh_arg->rfm;
6827 6847 mpt = replyh_arg->mpt;
6828 6848
6829 6849 eventreply = (pMpi2EventNotificationReply_t)
6830 6850 (mpt->m_reply_frame + (rfm -
6831 6851 (mpt->m_reply_frame_dma_addr & 0xffffffffu)));
6832 6852 event = ddi_get16(mpt->m_acc_reply_frame_hdl, &eventreply->Event);
6833 6853
6834 6854
6835 6855 /*
6836 6856 * Generate a system event to let anyone who cares know that a
6837 6857 * LOG_ENTRY_ADDED event has occurred. This is sent no matter what the
6838 6858 * event mask is set to.
6839 6859 */
6840 6860 if (event == MPI2_EVENT_LOG_ENTRY_ADDED) {
6841 6861 sendAEN = TRUE;
6842 6862 }
6843 6863
6844 6864 /*
6845 6865 * Record the event only if it is not masked. Determine which dword
6846 6866 * and bit of event mask to test.
6847 6867 */
6848 6868 i = (uint8_t)(event / 32);
6849 6869 j = (uint8_t)(event % 32);
6850 6870 if ((i < 4) && ((1 << j) & mpt->m_event_mask[i])) {
6851 6871 i = mpt->m_event_index;
6852 6872 mpt->m_events[i].Type = event;
6853 6873 mpt->m_events[i].Number = ++mpt->m_event_number;
6854 6874 bzero(mpt->m_events[i].Data, MPTSAS_MAX_EVENT_DATA_LENGTH * 4);
6855 6875 event_data_len = ddi_get16(mpt->m_acc_reply_frame_hdl,
6856 6876 &eventreply->EventDataLength);
6857 6877
6858 6878 if (event_data_len > 0) {
6859 6879 /*
6860 6880 * Limit data to size in m_event entry
6861 6881 */
6862 6882 if (event_data_len > MPTSAS_MAX_EVENT_DATA_LENGTH) {
6863 6883 event_data_len = MPTSAS_MAX_EVENT_DATA_LENGTH;
6864 6884 }
6865 6885 for (j = 0; j < event_data_len; j++) {
6866 6886 mpt->m_events[i].Data[j] =
6867 6887 ddi_get32(mpt->m_acc_reply_frame_hdl,
6868 6888 &(eventreply->EventData[j]));
6869 6889 }
6870 6890
6871 6891 /*
6872 6892 * check for index wrap-around
6873 6893 */
6874 6894 if (++i == MPTSAS_EVENT_QUEUE_SIZE) {
6875 6895 i = 0;
6876 6896 }
6877 6897 mpt->m_event_index = (uint8_t)i;
6878 6898
6879 6899 /*
6880 6900 * Set flag to send the event.
6881 6901 */
6882 6902 sendAEN = TRUE;
6883 6903 }
6884 6904 }
6885 6905
6886 6906 /*
6887 6907 * Generate a system event if flag is set to let anyone who cares know
6888 6908 * that an event has occurred.
6889 6909 */
6890 6910 if (sendAEN) {
6891 6911 (void) ddi_log_sysevent(mpt->m_dip, DDI_VENDOR_LSI, "MPT_SAS",
6892 6912 "SAS", NULL, NULL, DDI_NOSLEEP);
6893 6913 }
6894 6914 }
6895 6915
6896 6916 #define SMP_RESET_IN_PROGRESS MPI2_EVENT_SAS_TOPO_LR_SMP_RESET_IN_PROGRESS
6897 6917 /*
6898 6918 * handle sync events from ioc in interrupt
6899 6919 * return value:
6900 6920 * DDI_SUCCESS: The event is handled by this func
6901 6921 * DDI_FAILURE: Event is not handled
6902 6922 */
6903 6923 static int
6904 6924 mptsas_handle_event_sync(void *args)
6905 6925 {
6906 6926 m_replyh_arg_t *replyh_arg;
6907 6927 pMpi2EventNotificationReply_t eventreply;
6908 6928 uint32_t event, rfm;
6909 6929 mptsas_t *mpt;
6910 6930 uint_t iocstatus;
6911 6931
6912 6932 replyh_arg = (m_replyh_arg_t *)args;
6913 6933 rfm = replyh_arg->rfm;
6914 6934 mpt = replyh_arg->mpt;
6915 6935
6916 6936 ASSERT(mutex_owned(&mpt->m_mutex));
6917 6937
6918 6938 eventreply = (pMpi2EventNotificationReply_t)
6919 6939 (mpt->m_reply_frame + (rfm -
6920 6940 (mpt->m_reply_frame_dma_addr & 0xffffffffu)));
6921 6941 event = ddi_get16(mpt->m_acc_reply_frame_hdl, &eventreply->Event);
6922 6942
6923 6943 if (iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl,
6924 6944 &eventreply->IOCStatus)) {
6925 6945 if (iocstatus == MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) {
6926 6946 mptsas_log(mpt, CE_WARN,
6927 6947 "!mptsas_handle_event_sync: event 0x%x, "
6928 6948 "IOCStatus=0x%x, "
6929 6949 "IOCLogInfo=0x%x", event, iocstatus,
6930 6950 ddi_get32(mpt->m_acc_reply_frame_hdl,
6931 6951 &eventreply->IOCLogInfo));
6932 6952 } else {
6933 6953 mptsas_log(mpt, CE_WARN,
6934 6954 "mptsas_handle_event_sync: event 0x%x, "
6935 6955 "IOCStatus=0x%x, "
6936 6956 "(IOCLogInfo=0x%x)", event, iocstatus,
6937 6957 ddi_get32(mpt->m_acc_reply_frame_hdl,
6938 6958 &eventreply->IOCLogInfo));
6939 6959 }
6940 6960 }
6941 6961
6942 6962 /*
6943 6963 * figure out what kind of event we got and handle accordingly
6944 6964 */
6945 6965 switch (event) {
6946 6966 case MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST:
6947 6967 {
6948 6968 pMpi2EventDataSasTopologyChangeList_t sas_topo_change_list;
6949 6969 uint8_t num_entries, expstatus, phy;
6950 6970 uint8_t phystatus, physport, state, i;
6951 6971 uint8_t start_phy_num, link_rate;
6952 6972 uint16_t dev_handle, reason_code;
6953 6973 uint16_t enc_handle, expd_handle;
6954 6974 char string[80], curr[80], prev[80];
6955 6975 mptsas_topo_change_list_t *topo_head = NULL;
6956 6976 mptsas_topo_change_list_t *topo_tail = NULL;
6957 6977 mptsas_topo_change_list_t *topo_node = NULL;
6958 6978 mptsas_target_t *ptgt;
6959 6979 mptsas_smp_t *psmp;
6960 6980 uint8_t flags = 0, exp_flag;
6961 6981 smhba_info_t *pSmhba = NULL;
6962 6982
6963 6983 NDBG20(("mptsas_handle_event_sync: SAS topology change"));
6964 6984
6965 6985 sas_topo_change_list = (pMpi2EventDataSasTopologyChangeList_t)
6966 6986 eventreply->EventData;
6967 6987
6968 6988 enc_handle = ddi_get16(mpt->m_acc_reply_frame_hdl,
6969 6989 &sas_topo_change_list->EnclosureHandle);
6970 6990 expd_handle = ddi_get16(mpt->m_acc_reply_frame_hdl,
6971 6991 &sas_topo_change_list->ExpanderDevHandle);
6972 6992 num_entries = ddi_get8(mpt->m_acc_reply_frame_hdl,
6973 6993 &sas_topo_change_list->NumEntries);
6974 6994 start_phy_num = ddi_get8(mpt->m_acc_reply_frame_hdl,
6975 6995 &sas_topo_change_list->StartPhyNum);
6976 6996 expstatus = ddi_get8(mpt->m_acc_reply_frame_hdl,
6977 6997 &sas_topo_change_list->ExpStatus);
6978 6998 physport = ddi_get8(mpt->m_acc_reply_frame_hdl,
6979 6999 &sas_topo_change_list->PhysicalPort);
6980 7000
6981 7001 string[0] = 0;
6982 7002 if (expd_handle) {
6983 7003 flags = MPTSAS_TOPO_FLAG_EXPANDER_ASSOCIATED;
6984 7004 switch (expstatus) {
6985 7005 case MPI2_EVENT_SAS_TOPO_ES_ADDED:
6986 7006 (void) sprintf(string, " added");
6987 7007 /*
6988 7008 * New expander device added
6989 7009 */
6990 7010 mpt->m_port_chng = 1;
6991 7011 topo_node = kmem_zalloc(
6992 7012 sizeof (mptsas_topo_change_list_t),
6993 7013 KM_SLEEP);
6994 7014 topo_node->mpt = mpt;
6995 7015 topo_node->event = MPTSAS_DR_EVENT_RECONFIG_SMP;
6996 7016 topo_node->un.physport = physport;
6997 7017 topo_node->devhdl = expd_handle;
6998 7018 topo_node->flags = flags;
6999 7019 topo_node->object = NULL;
7000 7020 if (topo_head == NULL) {
7001 7021 topo_head = topo_tail = topo_node;
7002 7022 } else {
7003 7023 topo_tail->next = topo_node;
7004 7024 topo_tail = topo_node;
7005 7025 }
7006 7026 break;
7007 7027 case MPI2_EVENT_SAS_TOPO_ES_NOT_RESPONDING:
7008 7028 (void) sprintf(string, " not responding, "
7009 7029 "removed");
7010 7030 psmp = refhash_linear_search(mpt->m_smp_targets,
7011 7031 mptsas_smp_eval_devhdl, &expd_handle);
7012 7032 if (psmp == NULL)
7013 7033 break;
7014 7034
7015 7035 topo_node = kmem_zalloc(
7016 7036 sizeof (mptsas_topo_change_list_t),
7017 7037 KM_SLEEP);
7018 7038 topo_node->mpt = mpt;
7019 7039 topo_node->un.phymask =
7020 7040 psmp->m_addr.mta_phymask;
7021 7041 topo_node->event = MPTSAS_DR_EVENT_OFFLINE_SMP;
7022 7042 topo_node->devhdl = expd_handle;
7023 7043 topo_node->flags = flags;
7024 7044 topo_node->object = NULL;
7025 7045 if (topo_head == NULL) {
7026 7046 topo_head = topo_tail = topo_node;
7027 7047 } else {
7028 7048 topo_tail->next = topo_node;
7029 7049 topo_tail = topo_node;
7030 7050 }
7031 7051 break;
7032 7052 case MPI2_EVENT_SAS_TOPO_ES_RESPONDING:
7033 7053 break;
7034 7054 case MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING:
7035 7055 (void) sprintf(string, " not responding, "
7036 7056 "delaying removal");
7037 7057 break;
7038 7058 default:
7039 7059 break;
7040 7060 }
7041 7061 } else {
7042 7062 flags = MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE;
7043 7063 }
7044 7064
7045 7065 NDBG20(("SAS TOPOLOGY CHANGE for enclosure %x expander %x%s\n",
7046 7066 enc_handle, expd_handle, string));
7047 7067 for (i = 0; i < num_entries; i++) {
7048 7068 phy = i + start_phy_num;
7049 7069 phystatus = ddi_get8(mpt->m_acc_reply_frame_hdl,
7050 7070 &sas_topo_change_list->PHY[i].PhyStatus);
7051 7071 dev_handle = ddi_get16(mpt->m_acc_reply_frame_hdl,
7052 7072 &sas_topo_change_list->PHY[i].AttachedDevHandle);
7053 7073 reason_code = phystatus & MPI2_EVENT_SAS_TOPO_RC_MASK;
7054 7074 /*
7055 7075 * Filter out processing of Phy Vacant Status unless
7056 7076 * the reason code is "Not Responding". Process all
7057 7077 * other combinations of Phy Status and Reason Codes.
7058 7078 */
7059 7079 if ((phystatus &
7060 7080 MPI2_EVENT_SAS_TOPO_PHYSTATUS_VACANT) &&
7061 7081 (reason_code !=
7062 7082 MPI2_EVENT_SAS_TOPO_RC_TARG_NOT_RESPONDING)) {
7063 7083 continue;
7064 7084 }
7065 7085 curr[0] = 0;
7066 7086 prev[0] = 0;
7067 7087 string[0] = 0;
7068 7088 switch (reason_code) {
7069 7089 case MPI2_EVENT_SAS_TOPO_RC_TARG_ADDED:
7070 7090 {
7071 7091 NDBG20(("mptsas%d phy %d physical_port %d "
7072 7092 "dev_handle %d added", mpt->m_instance, phy,
7073 7093 physport, dev_handle));
7074 7094 link_rate = ddi_get8(mpt->m_acc_reply_frame_hdl,
7075 7095 &sas_topo_change_list->PHY[i].LinkRate);
7076 7096 state = (link_rate &
7077 7097 MPI2_EVENT_SAS_TOPO_LR_CURRENT_MASK) >>
7078 7098 MPI2_EVENT_SAS_TOPO_LR_CURRENT_SHIFT;
7079 7099 switch (state) {
7080 7100 case MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED:
7081 7101 (void) sprintf(curr, "is disabled");
7082 7102 break;
7083 7103 case MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED:
7084 7104 (void) sprintf(curr, "is offline, "
7085 7105 "failed speed negotiation");
7086 7106 break;
7087 7107 case MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE:
7088 7108 (void) sprintf(curr, "SATA OOB "
7089 7109 "complete");
7090 7110 break;
7091 7111 case SMP_RESET_IN_PROGRESS:
7092 7112 (void) sprintf(curr, "SMP reset in "
7093 7113 "progress");
7094 7114 break;
7095 7115 case MPI2_EVENT_SAS_TOPO_LR_RATE_1_5:
7096 7116 (void) sprintf(curr, "is online at "
7097 7117 "1.5 Gbps");
7098 7118 break;
7099 7119 case MPI2_EVENT_SAS_TOPO_LR_RATE_3_0:
7100 7120 (void) sprintf(curr, "is online at 3.0 "
7101 7121 "Gbps");
7102 7122 break;
7103 7123 case MPI2_EVENT_SAS_TOPO_LR_RATE_6_0:
7104 7124 (void) sprintf(curr, "is online at 6.0 "
7105 7125 "Gbps");
7106 7126 break;
7107 7127 case MPI25_EVENT_SAS_TOPO_LR_RATE_12_0:
7108 7128 (void) sprintf(curr,
7109 7129 "is online at 12.0 Gbps");
7110 7130 break;
7111 7131 default:
7112 7132 (void) sprintf(curr, "state is "
7113 7133 "unknown");
7114 7134 break;
7115 7135 }
7116 7136 /*
7117 7137 * New target device added into the system.
7118 7138 * Set association flag according to if an
7119 7139 * expander is used or not.
7120 7140 */
7121 7141 exp_flag =
7122 7142 MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE;
7123 7143 if (flags ==
7124 7144 MPTSAS_TOPO_FLAG_EXPANDER_ASSOCIATED) {
7125 7145 flags = exp_flag;
7126 7146 }
7127 7147 topo_node = kmem_zalloc(
7128 7148 sizeof (mptsas_topo_change_list_t),
7129 7149 KM_SLEEP);
7130 7150 topo_node->mpt = mpt;
7131 7151 topo_node->event =
7132 7152 MPTSAS_DR_EVENT_RECONFIG_TARGET;
7133 7153 if (expd_handle == 0) {
7134 7154 /*
7135 7155 * Per MPI 2, if expander dev handle
7136 7156 * is 0, it's a directly attached
7137 7157 * device. So driver use PHY to decide
7138 7158 * which iport is associated
7139 7159 */
7140 7160 physport = phy;
7141 7161 mpt->m_port_chng = 1;
7142 7162 }
7143 7163 topo_node->un.physport = physport;
7144 7164 topo_node->devhdl = dev_handle;
7145 7165 topo_node->flags = flags;
7146 7166 topo_node->object = NULL;
7147 7167 if (topo_head == NULL) {
7148 7168 topo_head = topo_tail = topo_node;
7149 7169 } else {
7150 7170 topo_tail->next = topo_node;
7151 7171 topo_tail = topo_node;
7152 7172 }
7153 7173 break;
7154 7174 }
7155 7175 case MPI2_EVENT_SAS_TOPO_RC_TARG_NOT_RESPONDING:
7156 7176 {
7157 7177 NDBG20(("mptsas%d phy %d physical_port %d "
7158 7178 "dev_handle %d removed", mpt->m_instance,
7159 7179 phy, physport, dev_handle));
7160 7180 /*
7161 7181 * Set association flag according to if an
7162 7182 * expander is used or not.
7163 7183 */
7164 7184 exp_flag =
7165 7185 MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE;
7166 7186 if (flags ==
7167 7187 MPTSAS_TOPO_FLAG_EXPANDER_ASSOCIATED) {
7168 7188 flags = exp_flag;
7169 7189 }
7170 7190 /*
7171 7191 * Target device is removed from the system
7172 7192 * Before the device is really offline from
7173 7193 * from system.
7174 7194 */
7175 7195 ptgt = refhash_linear_search(mpt->m_targets,
7176 7196 mptsas_target_eval_devhdl, &dev_handle);
7177 7197 /*
7178 7198 * If ptgt is NULL here, it means that the
7179 7199 * DevHandle is not in the hash table. This is
7180 7200 * reasonable sometimes. For example, if a
7181 7201 * disk was pulled, then added, then pulled
7182 7202 * again, the disk will not have been put into
7183 7203 * the hash table because the add event will
7184 7204 * have an invalid phymask. BUT, this does not
7185 7205 * mean that the DevHandle is invalid. The
7186 7206 * controller will still have a valid DevHandle
7187 7207 * that must be removed. To do this, use the
7188 7208 * MPTSAS_TOPO_FLAG_REMOVE_HANDLE event.
7189 7209 */
7190 7210 if (ptgt == NULL) {
7191 7211 topo_node = kmem_zalloc(
7192 7212 sizeof (mptsas_topo_change_list_t),
7193 7213 KM_SLEEP);
7194 7214 topo_node->mpt = mpt;
7195 7215 topo_node->un.phymask = 0;
7196 7216 topo_node->event =
7197 7217 MPTSAS_TOPO_FLAG_REMOVE_HANDLE;
7198 7218 topo_node->devhdl = dev_handle;
7199 7219 topo_node->flags = flags;
7200 7220 topo_node->object = NULL;
7201 7221 if (topo_head == NULL) {
7202 7222 topo_head = topo_tail =
7203 7223 topo_node;
7204 7224 } else {
7205 7225 topo_tail->next = topo_node;
7206 7226 topo_tail = topo_node;
7207 7227 }
7208 7228 break;
7209 7229 }
7210 7230
7211 7231 /*
7212 7232 * Update DR flag immediately avoid I/O failure
7213 7233 * before failover finish. Pay attention to the
7214 7234 * mutex protect, we need grab m_tx_waitq_mutex
7215 7235 * during set m_dr_flag because we won't add
7216 7236 * the following command into waitq, instead,
7217 7237 * we need return TRAN_BUSY in the tran_start
7218 7238 * context.
7219 7239 */
7220 7240 mutex_enter(&mpt->m_tx_waitq_mutex);
7221 7241 ptgt->m_dr_flag = MPTSAS_DR_INTRANSITION;
7222 7242 mutex_exit(&mpt->m_tx_waitq_mutex);
7223 7243
7224 7244 topo_node = kmem_zalloc(
7225 7245 sizeof (mptsas_topo_change_list_t),
7226 7246 KM_SLEEP);
7227 7247 topo_node->mpt = mpt;
7228 7248 topo_node->un.phymask =
7229 7249 ptgt->m_addr.mta_phymask;
7230 7250 topo_node->event =
7231 7251 MPTSAS_DR_EVENT_OFFLINE_TARGET;
7232 7252 topo_node->devhdl = dev_handle;
7233 7253 topo_node->flags = flags;
7234 7254 topo_node->object = NULL;
7235 7255 if (topo_head == NULL) {
7236 7256 topo_head = topo_tail = topo_node;
7237 7257 } else {
7238 7258 topo_tail->next = topo_node;
7239 7259 topo_tail = topo_node;
7240 7260 }
7241 7261 break;
7242 7262 }
7243 7263 case MPI2_EVENT_SAS_TOPO_RC_PHY_CHANGED:
7244 7264 link_rate = ddi_get8(mpt->m_acc_reply_frame_hdl,
7245 7265 &sas_topo_change_list->PHY[i].LinkRate);
7246 7266 state = (link_rate &
7247 7267 MPI2_EVENT_SAS_TOPO_LR_CURRENT_MASK) >>
7248 7268 MPI2_EVENT_SAS_TOPO_LR_CURRENT_SHIFT;
7249 7269 pSmhba = &mpt->m_phy_info[i].smhba_info;
7250 7270 pSmhba->negotiated_link_rate = state;
7251 7271 switch (state) {
7252 7272 case MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED:
7253 7273 (void) sprintf(curr, "is disabled");
7254 7274 mptsas_smhba_log_sysevent(mpt,
7255 7275 ESC_SAS_PHY_EVENT,
7256 7276 SAS_PHY_REMOVE,
7257 7277 &mpt->m_phy_info[i].smhba_info);
7258 7278 mpt->m_phy_info[i].smhba_info.
7259 7279 negotiated_link_rate
7260 7280 = 0x1;
7261 7281 break;
7262 7282 case MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED:
7263 7283 (void) sprintf(curr, "is offline, "
7264 7284 "failed speed negotiation");
7265 7285 mptsas_smhba_log_sysevent(mpt,
7266 7286 ESC_SAS_PHY_EVENT,
7267 7287 SAS_PHY_OFFLINE,
7268 7288 &mpt->m_phy_info[i].smhba_info);
7269 7289 break;
7270 7290 case MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE:
7271 7291 (void) sprintf(curr, "SATA OOB "
7272 7292 "complete");
7273 7293 break;
7274 7294 case SMP_RESET_IN_PROGRESS:
7275 7295 (void) sprintf(curr, "SMP reset in "
7276 7296 "progress");
7277 7297 break;
7278 7298 case MPI2_EVENT_SAS_TOPO_LR_RATE_1_5:
7279 7299 (void) sprintf(curr, "is online at "
7280 7300 "1.5 Gbps");
7281 7301 if ((expd_handle == 0) &&
7282 7302 (enc_handle == 1)) {
7283 7303 mpt->m_port_chng = 1;
7284 7304 }
7285 7305 mptsas_smhba_log_sysevent(mpt,
7286 7306 ESC_SAS_PHY_EVENT,
7287 7307 SAS_PHY_ONLINE,
7288 7308 &mpt->m_phy_info[i].smhba_info);
7289 7309 break;
7290 7310 case MPI2_EVENT_SAS_TOPO_LR_RATE_3_0:
7291 7311 (void) sprintf(curr, "is online at 3.0 "
7292 7312 "Gbps");
7293 7313 if ((expd_handle == 0) &&
7294 7314 (enc_handle == 1)) {
7295 7315 mpt->m_port_chng = 1;
7296 7316 }
7297 7317 mptsas_smhba_log_sysevent(mpt,
7298 7318 ESC_SAS_PHY_EVENT,
7299 7319 SAS_PHY_ONLINE,
7300 7320 &mpt->m_phy_info[i].smhba_info);
7301 7321 break;
7302 7322 case MPI2_EVENT_SAS_TOPO_LR_RATE_6_0:
7303 7323 (void) sprintf(curr, "is online at "
7304 7324 "6.0 Gbps");
7305 7325 if ((expd_handle == 0) &&
7306 7326 (enc_handle == 1)) {
7307 7327 mpt->m_port_chng = 1;
7308 7328 }
7309 7329 mptsas_smhba_log_sysevent(mpt,
7310 7330 ESC_SAS_PHY_EVENT,
7311 7331 SAS_PHY_ONLINE,
7312 7332 &mpt->m_phy_info[i].smhba_info);
7313 7333 break;
7314 7334 case MPI25_EVENT_SAS_TOPO_LR_RATE_12_0:
7315 7335 (void) sprintf(curr, "is online at "
7316 7336 "12.0 Gbps");
7317 7337 if ((expd_handle == 0) &&
7318 7338 (enc_handle == 1)) {
7319 7339 mpt->m_port_chng = 1;
7320 7340 }
7321 7341 mptsas_smhba_log_sysevent(mpt,
7322 7342 ESC_SAS_PHY_EVENT,
7323 7343 SAS_PHY_ONLINE,
7324 7344 &mpt->m_phy_info[i].smhba_info);
7325 7345 break;
7326 7346 default:
7327 7347 (void) sprintf(curr, "state is "
7328 7348 "unknown");
7329 7349 break;
7330 7350 }
7331 7351
7332 7352 state = (link_rate &
7333 7353 MPI2_EVENT_SAS_TOPO_LR_PREV_MASK) >>
7334 7354 MPI2_EVENT_SAS_TOPO_LR_PREV_SHIFT;
7335 7355 switch (state) {
7336 7356 case MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED:
7337 7357 (void) sprintf(prev, ", was disabled");
7338 7358 break;
7339 7359 case MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED:
7340 7360 (void) sprintf(prev, ", was offline, "
7341 7361 "failed speed negotiation");
7342 7362 break;
7343 7363 case MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE:
7344 7364 (void) sprintf(prev, ", was SATA OOB "
7345 7365 "complete");
7346 7366 break;
7347 7367 case SMP_RESET_IN_PROGRESS:
7348 7368 (void) sprintf(prev, ", was SMP reset "
7349 7369 "in progress");
7350 7370 break;
7351 7371 case MPI2_EVENT_SAS_TOPO_LR_RATE_1_5:
7352 7372 (void) sprintf(prev, ", was online at "
7353 7373 "1.5 Gbps");
7354 7374 break;
7355 7375 case MPI2_EVENT_SAS_TOPO_LR_RATE_3_0:
7356 7376 (void) sprintf(prev, ", was online at "
7357 7377 "3.0 Gbps");
7358 7378 break;
7359 7379 case MPI2_EVENT_SAS_TOPO_LR_RATE_6_0:
7360 7380 (void) sprintf(prev, ", was online at "
7361 7381 "6.0 Gbps");
7362 7382 break;
7363 7383 case MPI25_EVENT_SAS_TOPO_LR_RATE_12_0:
7364 7384 (void) sprintf(prev, ", was online at "
7365 7385 "12.0 Gbps");
7366 7386 break;
7367 7387 default:
7368 7388 break;
7369 7389 }
7370 7390 (void) sprintf(&string[strlen(string)], "link "
7371 7391 "changed, ");
7372 7392 break;
7373 7393 case MPI2_EVENT_SAS_TOPO_RC_NO_CHANGE:
7374 7394 continue;
7375 7395 case MPI2_EVENT_SAS_TOPO_RC_DELAY_NOT_RESPONDING:
7376 7396 (void) sprintf(&string[strlen(string)],
7377 7397 "target not responding, delaying "
7378 7398 "removal");
7379 7399 break;
7380 7400 }
7381 7401 NDBG20(("mptsas%d phy %d DevHandle %x, %s%s%s\n",
7382 7402 mpt->m_instance, phy, dev_handle, string, curr,
7383 7403 prev));
7384 7404 }
7385 7405 if (topo_head != NULL) {
7386 7406 /*
7387 7407 * Launch DR taskq to handle topology change
7388 7408 */
7389 7409 if ((ddi_taskq_dispatch(mpt->m_dr_taskq,
7390 7410 mptsas_handle_dr, (void *)topo_head,
7391 7411 DDI_NOSLEEP)) != DDI_SUCCESS) {
7392 7412 while (topo_head != NULL) {
7393 7413 topo_node = topo_head;
7394 7414 topo_head = topo_head->next;
7395 7415 kmem_free(topo_node,
7396 7416 sizeof (mptsas_topo_change_list_t));
7397 7417 }
7398 7418 mptsas_log(mpt, CE_NOTE, "mptsas start taskq "
7399 7419 "for handle SAS DR event failed. \n");
7400 7420 }
7401 7421 }
7402 7422 break;
7403 7423 }
7404 7424 case MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST:
7405 7425 {
7406 7426 Mpi2EventDataIrConfigChangeList_t *irChangeList;
7407 7427 mptsas_topo_change_list_t *topo_head = NULL;
7408 7428 mptsas_topo_change_list_t *topo_tail = NULL;
7409 7429 mptsas_topo_change_list_t *topo_node = NULL;
7410 7430 mptsas_target_t *ptgt;
7411 7431 uint8_t num_entries, i, reason;
7412 7432 uint16_t volhandle, diskhandle;
7413 7433
7414 7434 irChangeList = (pMpi2EventDataIrConfigChangeList_t)
7415 7435 eventreply->EventData;
7416 7436 num_entries = ddi_get8(mpt->m_acc_reply_frame_hdl,
7417 7437 &irChangeList->NumElements);
7418 7438
7419 7439 NDBG20(("mptsas%d IR_CONFIGURATION_CHANGE_LIST event received",
7420 7440 mpt->m_instance));
7421 7441
7422 7442 for (i = 0; i < num_entries; i++) {
7423 7443 reason = ddi_get8(mpt->m_acc_reply_frame_hdl,
7424 7444 &irChangeList->ConfigElement[i].ReasonCode);
7425 7445 volhandle = ddi_get16(mpt->m_acc_reply_frame_hdl,
7426 7446 &irChangeList->ConfigElement[i].VolDevHandle);
7427 7447 diskhandle = ddi_get16(mpt->m_acc_reply_frame_hdl,
7428 7448 &irChangeList->ConfigElement[i].PhysDiskDevHandle);
7429 7449
7430 7450 switch (reason) {
7431 7451 case MPI2_EVENT_IR_CHANGE_RC_ADDED:
7432 7452 case MPI2_EVENT_IR_CHANGE_RC_VOLUME_CREATED:
7433 7453 {
7434 7454 NDBG20(("mptsas %d volume added\n",
7435 7455 mpt->m_instance));
7436 7456
7437 7457 topo_node = kmem_zalloc(
7438 7458 sizeof (mptsas_topo_change_list_t),
7439 7459 KM_SLEEP);
7440 7460
7441 7461 topo_node->mpt = mpt;
7442 7462 topo_node->event =
7443 7463 MPTSAS_DR_EVENT_RECONFIG_TARGET;
7444 7464 topo_node->un.physport = 0xff;
7445 7465 topo_node->devhdl = volhandle;
7446 7466 topo_node->flags =
7447 7467 MPTSAS_TOPO_FLAG_RAID_ASSOCIATED;
7448 7468 topo_node->object = NULL;
7449 7469 if (topo_head == NULL) {
7450 7470 topo_head = topo_tail = topo_node;
7451 7471 } else {
7452 7472 topo_tail->next = topo_node;
7453 7473 topo_tail = topo_node;
7454 7474 }
7455 7475 break;
7456 7476 }
7457 7477 case MPI2_EVENT_IR_CHANGE_RC_REMOVED:
7458 7478 case MPI2_EVENT_IR_CHANGE_RC_VOLUME_DELETED:
7459 7479 {
7460 7480 NDBG20(("mptsas %d volume deleted\n",
7461 7481 mpt->m_instance));
7462 7482 ptgt = refhash_linear_search(mpt->m_targets,
7463 7483 mptsas_target_eval_devhdl, &volhandle);
7464 7484 if (ptgt == NULL)
7465 7485 break;
7466 7486
7467 7487 /*
7468 7488 * Clear any flags related to volume
7469 7489 */
7470 7490 (void) mptsas_delete_volume(mpt, volhandle);
7471 7491
7472 7492 /*
7473 7493 * Update DR flag immediately avoid I/O failure
7474 7494 */
7475 7495 mutex_enter(&mpt->m_tx_waitq_mutex);
7476 7496 ptgt->m_dr_flag = MPTSAS_DR_INTRANSITION;
7477 7497 mutex_exit(&mpt->m_tx_waitq_mutex);
7478 7498
7479 7499 topo_node = kmem_zalloc(
7480 7500 sizeof (mptsas_topo_change_list_t),
7481 7501 KM_SLEEP);
7482 7502 topo_node->mpt = mpt;
7483 7503 topo_node->un.phymask =
7484 7504 ptgt->m_addr.mta_phymask;
7485 7505 topo_node->event =
7486 7506 MPTSAS_DR_EVENT_OFFLINE_TARGET;
7487 7507 topo_node->devhdl = volhandle;
7488 7508 topo_node->flags =
7489 7509 MPTSAS_TOPO_FLAG_RAID_ASSOCIATED;
7490 7510 topo_node->object = (void *)ptgt;
7491 7511 if (topo_head == NULL) {
7492 7512 topo_head = topo_tail = topo_node;
7493 7513 } else {
7494 7514 topo_tail->next = topo_node;
7495 7515 topo_tail = topo_node;
7496 7516 }
7497 7517 break;
7498 7518 }
7499 7519 case MPI2_EVENT_IR_CHANGE_RC_PD_CREATED:
7500 7520 case MPI2_EVENT_IR_CHANGE_RC_HIDE:
7501 7521 {
7502 7522 ptgt = refhash_linear_search(mpt->m_targets,
7503 7523 mptsas_target_eval_devhdl, &diskhandle);
7504 7524 if (ptgt == NULL)
7505 7525 break;
7506 7526
7507 7527 /*
7508 7528 * Update DR flag immediately avoid I/O failure
7509 7529 */
7510 7530 mutex_enter(&mpt->m_tx_waitq_mutex);
7511 7531 ptgt->m_dr_flag = MPTSAS_DR_INTRANSITION;
7512 7532 mutex_exit(&mpt->m_tx_waitq_mutex);
7513 7533
7514 7534 topo_node = kmem_zalloc(
7515 7535 sizeof (mptsas_topo_change_list_t),
7516 7536 KM_SLEEP);
7517 7537 topo_node->mpt = mpt;
7518 7538 topo_node->un.phymask =
7519 7539 ptgt->m_addr.mta_phymask;
7520 7540 topo_node->event =
7521 7541 MPTSAS_DR_EVENT_OFFLINE_TARGET;
7522 7542 topo_node->devhdl = diskhandle;
7523 7543 topo_node->flags =
7524 7544 MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED;
7525 7545 topo_node->object = (void *)ptgt;
7526 7546 if (topo_head == NULL) {
7527 7547 topo_head = topo_tail = topo_node;
7528 7548 } else {
7529 7549 topo_tail->next = topo_node;
7530 7550 topo_tail = topo_node;
7531 7551 }
7532 7552 break;
7533 7553 }
7534 7554 case MPI2_EVENT_IR_CHANGE_RC_UNHIDE:
7535 7555 case MPI2_EVENT_IR_CHANGE_RC_PD_DELETED:
7536 7556 {
7537 7557 /*
7538 7558 * The physical drive is released by a IR
7539 7559 * volume. But we cannot get the the physport
7540 7560 * or phynum from the event data, so we only
7541 7561 * can get the physport/phynum after SAS
7542 7562 * Device Page0 request for the devhdl.
7543 7563 */
7544 7564 topo_node = kmem_zalloc(
7545 7565 sizeof (mptsas_topo_change_list_t),
7546 7566 KM_SLEEP);
7547 7567 topo_node->mpt = mpt;
7548 7568 topo_node->un.phymask = 0;
7549 7569 topo_node->event =
7550 7570 MPTSAS_DR_EVENT_RECONFIG_TARGET;
7551 7571 topo_node->devhdl = diskhandle;
7552 7572 topo_node->flags =
7553 7573 MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED;
7554 7574 topo_node->object = NULL;
7555 7575 mpt->m_port_chng = 1;
7556 7576 if (topo_head == NULL) {
7557 7577 topo_head = topo_tail = topo_node;
7558 7578 } else {
7559 7579 topo_tail->next = topo_node;
7560 7580 topo_tail = topo_node;
7561 7581 }
7562 7582 break;
7563 7583 }
7564 7584 default:
7565 7585 break;
7566 7586 }
7567 7587 }
7568 7588
7569 7589 if (topo_head != NULL) {
7570 7590 /*
7571 7591 * Launch DR taskq to handle topology change
7572 7592 */
7573 7593 if ((ddi_taskq_dispatch(mpt->m_dr_taskq,
7574 7594 mptsas_handle_dr, (void *)topo_head,
7575 7595 DDI_NOSLEEP)) != DDI_SUCCESS) {
7576 7596 while (topo_head != NULL) {
7577 7597 topo_node = topo_head;
7578 7598 topo_head = topo_head->next;
7579 7599 kmem_free(topo_node,
7580 7600 sizeof (mptsas_topo_change_list_t));
7581 7601 }
7582 7602 mptsas_log(mpt, CE_NOTE, "mptsas start taskq "
7583 7603 "for handle SAS DR event failed. \n");
7584 7604 }
7585 7605 }
7586 7606 break;
7587 7607 }
7588 7608 default:
7589 7609 return (DDI_FAILURE);
7590 7610 }
7591 7611
7592 7612 return (DDI_SUCCESS);
7593 7613 }
7594 7614
7595 7615 /*
7596 7616 * handle events from ioc
7597 7617 */
7598 7618 static void
7599 7619 mptsas_handle_event(void *args)
7600 7620 {
7601 7621 m_replyh_arg_t *replyh_arg;
7602 7622 pMpi2EventNotificationReply_t eventreply;
7603 7623 uint32_t event, iocloginfo, rfm;
7604 7624 uint32_t status;
7605 7625 uint8_t port;
7606 7626 mptsas_t *mpt;
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1248 lines elided |
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7607 7627 uint_t iocstatus;
7608 7628
7609 7629 replyh_arg = (m_replyh_arg_t *)args;
7610 7630 rfm = replyh_arg->rfm;
7611 7631 mpt = replyh_arg->mpt;
7612 7632
7613 7633 mutex_enter(&mpt->m_mutex);
7614 7634 /*
7615 7635 * If HBA is being reset, drop incoming event.
7616 7636 */
7617 - if (mpt->m_in_reset) {
7637 + mutex_enter(&mpt->m_taskmgmt_mutex);
7638 + if (mpt->m_in_reset == TRUE) {
7618 7639 NDBG20(("dropping event received prior to reset"));
7640 + mutex_exit(&mpt->m_taskmgmt_mutex);
7619 7641 mutex_exit(&mpt->m_mutex);
7620 7642 return;
7621 7643 }
7644 + mutex_exit(&mpt->m_taskmgmt_mutex);
7622 7645
7623 7646 eventreply = (pMpi2EventNotificationReply_t)
7624 7647 (mpt->m_reply_frame + (rfm -
7625 7648 (mpt->m_reply_frame_dma_addr & 0xffffffffu)));
7626 7649 event = ddi_get16(mpt->m_acc_reply_frame_hdl, &eventreply->Event);
7627 7650
7628 7651 if (iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl,
7629 7652 &eventreply->IOCStatus)) {
7630 7653 if (iocstatus == MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) {
7631 7654 mptsas_log(mpt, CE_WARN,
7632 7655 "!mptsas_handle_event: IOCStatus=0x%x, "
7633 7656 "IOCLogInfo=0x%x", iocstatus,
7634 7657 ddi_get32(mpt->m_acc_reply_frame_hdl,
7635 7658 &eventreply->IOCLogInfo));
7636 7659 } else {
7637 7660 mptsas_log(mpt, CE_WARN,
7638 7661 "mptsas_handle_event: IOCStatus=0x%x, "
7639 7662 "IOCLogInfo=0x%x", iocstatus,
7640 7663 ddi_get32(mpt->m_acc_reply_frame_hdl,
7641 7664 &eventreply->IOCLogInfo));
7642 7665 }
7643 7666 }
7644 7667
7645 7668 /*
7646 7669 * figure out what kind of event we got and handle accordingly
7647 7670 */
7648 7671 switch (event) {
7649 7672 case MPI2_EVENT_LOG_ENTRY_ADDED:
7650 7673 break;
7651 7674 case MPI2_EVENT_LOG_DATA:
7652 7675 iocloginfo = ddi_get32(mpt->m_acc_reply_frame_hdl,
7653 7676 &eventreply->IOCLogInfo);
7654 7677 NDBG20(("mptsas %d log info %x received.\n", mpt->m_instance,
7655 7678 iocloginfo));
7656 7679 break;
7657 7680 case MPI2_EVENT_STATE_CHANGE:
7658 7681 NDBG20(("mptsas%d state change.", mpt->m_instance));
7659 7682 break;
7660 7683 case MPI2_EVENT_HARD_RESET_RECEIVED:
7661 7684 NDBG20(("mptsas%d event change.", mpt->m_instance));
7662 7685 break;
7663 7686 case MPI2_EVENT_SAS_DISCOVERY:
7664 7687 {
7665 7688 MPI2_EVENT_DATA_SAS_DISCOVERY *sasdiscovery;
7666 7689 char string[80];
7667 7690 uint8_t rc;
7668 7691
7669 7692 sasdiscovery =
7670 7693 (pMpi2EventDataSasDiscovery_t)eventreply->EventData;
7671 7694
7672 7695 rc = ddi_get8(mpt->m_acc_reply_frame_hdl,
7673 7696 &sasdiscovery->ReasonCode);
7674 7697 port = ddi_get8(mpt->m_acc_reply_frame_hdl,
7675 7698 &sasdiscovery->PhysicalPort);
7676 7699 status = ddi_get32(mpt->m_acc_reply_frame_hdl,
7677 7700 &sasdiscovery->DiscoveryStatus);
7678 7701
7679 7702 string[0] = 0;
7680 7703 switch (rc) {
7681 7704 case MPI2_EVENT_SAS_DISC_RC_STARTED:
7682 7705 (void) sprintf(string, "STARTING");
7683 7706 break;
7684 7707 case MPI2_EVENT_SAS_DISC_RC_COMPLETED:
7685 7708 (void) sprintf(string, "COMPLETED");
7686 7709 break;
7687 7710 default:
7688 7711 (void) sprintf(string, "UNKNOWN");
7689 7712 break;
7690 7713 }
7691 7714
7692 7715 NDBG20(("SAS DISCOVERY is %s for port %d, status %x", string,
7693 7716 port, status));
7694 7717
7695 7718 break;
7696 7719 }
7697 7720 case MPI2_EVENT_EVENT_CHANGE:
7698 7721 NDBG20(("mptsas%d event change.", mpt->m_instance));
7699 7722 break;
7700 7723 case MPI2_EVENT_TASK_SET_FULL:
7701 7724 {
7702 7725 pMpi2EventDataTaskSetFull_t taskfull;
7703 7726
7704 7727 taskfull = (pMpi2EventDataTaskSetFull_t)eventreply->EventData;
7705 7728
7706 7729 NDBG20(("TASK_SET_FULL received for mptsas%d, depth %d\n",
7707 7730 mpt->m_instance, ddi_get16(mpt->m_acc_reply_frame_hdl,
7708 7731 &taskfull->CurrentDepth)));
7709 7732 break;
7710 7733 }
7711 7734 case MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST:
7712 7735 {
7713 7736 /*
7714 7737 * SAS TOPOLOGY CHANGE LIST Event has already been handled
7715 7738 * in mptsas_handle_event_sync() of interrupt context
7716 7739 */
7717 7740 break;
7718 7741 }
7719 7742 case MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE:
7720 7743 {
7721 7744 pMpi2EventDataSasEnclDevStatusChange_t encstatus;
7722 7745 uint8_t rc;
7723 7746 char string[80];
7724 7747
7725 7748 encstatus = (pMpi2EventDataSasEnclDevStatusChange_t)
7726 7749 eventreply->EventData;
7727 7750
7728 7751 rc = ddi_get8(mpt->m_acc_reply_frame_hdl,
7729 7752 &encstatus->ReasonCode);
7730 7753 switch (rc) {
7731 7754 case MPI2_EVENT_SAS_ENCL_RC_ADDED:
7732 7755 (void) sprintf(string, "added");
7733 7756 break;
7734 7757 case MPI2_EVENT_SAS_ENCL_RC_NOT_RESPONDING:
7735 7758 (void) sprintf(string, ", not responding");
7736 7759 break;
7737 7760 default:
7738 7761 break;
7739 7762 }
7740 7763 NDBG20(("mptsas%d ENCLOSURE STATUS CHANGE for enclosure "
7741 7764 "%x%s\n", mpt->m_instance,
7742 7765 ddi_get16(mpt->m_acc_reply_frame_hdl,
7743 7766 &encstatus->EnclosureHandle), string));
7744 7767 break;
7745 7768 }
7746 7769
7747 7770 /*
7748 7771 * MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE is handled by
7749 7772 * mptsas_handle_event_sync,in here just send ack message.
7750 7773 */
7751 7774 case MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE:
7752 7775 {
7753 7776 pMpi2EventDataSasDeviceStatusChange_t statuschange;
7754 7777 uint8_t rc;
7755 7778 uint16_t devhdl;
7756 7779 uint64_t wwn = 0;
7757 7780 uint32_t wwn_lo, wwn_hi;
7758 7781
7759 7782 statuschange = (pMpi2EventDataSasDeviceStatusChange_t)
7760 7783 eventreply->EventData;
7761 7784 rc = ddi_get8(mpt->m_acc_reply_frame_hdl,
7762 7785 &statuschange->ReasonCode);
7763 7786 wwn_lo = ddi_get32(mpt->m_acc_reply_frame_hdl,
7764 7787 (uint32_t *)(void *)&statuschange->SASAddress);
7765 7788 wwn_hi = ddi_get32(mpt->m_acc_reply_frame_hdl,
7766 7789 (uint32_t *)(void *)&statuschange->SASAddress + 1);
7767 7790 wwn = ((uint64_t)wwn_hi << 32) | wwn_lo;
7768 7791 devhdl = ddi_get16(mpt->m_acc_reply_frame_hdl,
7769 7792 &statuschange->DevHandle);
7770 7793
7771 7794 NDBG13(("MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE wwn is %"PRIx64,
7772 7795 wwn));
7773 7796
7774 7797 switch (rc) {
7775 7798 case MPI2_EVENT_SAS_DEV_STAT_RC_SMART_DATA:
7776 7799 NDBG20(("SMART data received, ASC/ASCQ = %02x/%02x",
7777 7800 ddi_get8(mpt->m_acc_reply_frame_hdl,
7778 7801 &statuschange->ASC),
7779 7802 ddi_get8(mpt->m_acc_reply_frame_hdl,
7780 7803 &statuschange->ASCQ)));
7781 7804 break;
7782 7805
7783 7806 case MPI2_EVENT_SAS_DEV_STAT_RC_UNSUPPORTED:
7784 7807 NDBG20(("Device not supported"));
7785 7808 break;
7786 7809
7787 7810 case MPI2_EVENT_SAS_DEV_STAT_RC_INTERNAL_DEVICE_RESET:
7788 7811 NDBG20(("IOC internally generated the Target Reset "
7789 7812 "for devhdl:%x", devhdl));
7790 7813 break;
7791 7814
7792 7815 case MPI2_EVENT_SAS_DEV_STAT_RC_CMP_INTERNAL_DEV_RESET:
7793 7816 NDBG20(("IOC's internally generated Target Reset "
7794 7817 "completed for devhdl:%x", devhdl));
7795 7818 break;
7796 7819
7797 7820 case MPI2_EVENT_SAS_DEV_STAT_RC_TASK_ABORT_INTERNAL:
7798 7821 NDBG20(("IOC internally generated Abort Task"));
7799 7822 break;
7800 7823
7801 7824 case MPI2_EVENT_SAS_DEV_STAT_RC_CMP_TASK_ABORT_INTERNAL:
7802 7825 NDBG20(("IOC's internally generated Abort Task "
7803 7826 "completed"));
7804 7827 break;
7805 7828
7806 7829 case MPI2_EVENT_SAS_DEV_STAT_RC_ABORT_TASK_SET_INTERNAL:
7807 7830 NDBG20(("IOC internally generated Abort Task Set"));
7808 7831 break;
7809 7832
7810 7833 case MPI2_EVENT_SAS_DEV_STAT_RC_CLEAR_TASK_SET_INTERNAL:
7811 7834 NDBG20(("IOC internally generated Clear Task Set"));
7812 7835 break;
7813 7836
7814 7837 case MPI2_EVENT_SAS_DEV_STAT_RC_QUERY_TASK_INTERNAL:
7815 7838 NDBG20(("IOC internally generated Query Task"));
7816 7839 break;
7817 7840
7818 7841 case MPI2_EVENT_SAS_DEV_STAT_RC_ASYNC_NOTIFICATION:
7819 7842 NDBG20(("Device sent an Asynchronous Notification"));
7820 7843 break;
7821 7844
7822 7845 default:
7823 7846 break;
7824 7847 }
7825 7848 break;
7826 7849 }
7827 7850 case MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST:
7828 7851 {
7829 7852 /*
7830 7853 * IR TOPOLOGY CHANGE LIST Event has already been handled
7831 7854 * in mpt_handle_event_sync() of interrupt context
7832 7855 */
7833 7856 break;
7834 7857 }
7835 7858 case MPI2_EVENT_IR_OPERATION_STATUS:
7836 7859 {
7837 7860 Mpi2EventDataIrOperationStatus_t *irOpStatus;
7838 7861 char reason_str[80];
7839 7862 uint8_t rc, percent;
7840 7863 uint16_t handle;
7841 7864
7842 7865 irOpStatus = (pMpi2EventDataIrOperationStatus_t)
7843 7866 eventreply->EventData;
7844 7867 rc = ddi_get8(mpt->m_acc_reply_frame_hdl,
7845 7868 &irOpStatus->RAIDOperation);
7846 7869 percent = ddi_get8(mpt->m_acc_reply_frame_hdl,
7847 7870 &irOpStatus->PercentComplete);
7848 7871 handle = ddi_get16(mpt->m_acc_reply_frame_hdl,
7849 7872 &irOpStatus->VolDevHandle);
7850 7873
7851 7874 switch (rc) {
7852 7875 case MPI2_EVENT_IR_RAIDOP_RESYNC:
7853 7876 (void) sprintf(reason_str, "resync");
7854 7877 break;
7855 7878 case MPI2_EVENT_IR_RAIDOP_ONLINE_CAP_EXPANSION:
7856 7879 (void) sprintf(reason_str, "online capacity "
7857 7880 "expansion");
7858 7881 break;
7859 7882 case MPI2_EVENT_IR_RAIDOP_CONSISTENCY_CHECK:
7860 7883 (void) sprintf(reason_str, "consistency check");
7861 7884 break;
7862 7885 default:
7863 7886 (void) sprintf(reason_str, "unknown reason %x",
7864 7887 rc);
7865 7888 }
7866 7889
7867 7890 NDBG20(("mptsas%d raid operational status: (%s)"
7868 7891 "\thandle(0x%04x), percent complete(%d)\n",
7869 7892 mpt->m_instance, reason_str, handle, percent));
7870 7893 break;
7871 7894 }
7872 7895 case MPI2_EVENT_SAS_BROADCAST_PRIMITIVE:
7873 7896 {
7874 7897 pMpi2EventDataSasBroadcastPrimitive_t sas_broadcast;
7875 7898 uint8_t phy_num;
7876 7899 uint8_t primitive;
7877 7900
7878 7901 sas_broadcast = (pMpi2EventDataSasBroadcastPrimitive_t)
7879 7902 eventreply->EventData;
7880 7903
7881 7904 phy_num = ddi_get8(mpt->m_acc_reply_frame_hdl,
7882 7905 &sas_broadcast->PhyNum);
7883 7906 primitive = ddi_get8(mpt->m_acc_reply_frame_hdl,
7884 7907 &sas_broadcast->Primitive);
7885 7908
7886 7909 switch (primitive) {
7887 7910 case MPI2_EVENT_PRIMITIVE_CHANGE:
7888 7911 mptsas_smhba_log_sysevent(mpt,
7889 7912 ESC_SAS_HBA_PORT_BROADCAST,
7890 7913 SAS_PORT_BROADCAST_CHANGE,
7891 7914 &mpt->m_phy_info[phy_num].smhba_info);
7892 7915 break;
7893 7916 case MPI2_EVENT_PRIMITIVE_SES:
7894 7917 mptsas_smhba_log_sysevent(mpt,
7895 7918 ESC_SAS_HBA_PORT_BROADCAST,
7896 7919 SAS_PORT_BROADCAST_SES,
7897 7920 &mpt->m_phy_info[phy_num].smhba_info);
7898 7921 break;
7899 7922 case MPI2_EVENT_PRIMITIVE_EXPANDER:
7900 7923 mptsas_smhba_log_sysevent(mpt,
7901 7924 ESC_SAS_HBA_PORT_BROADCAST,
7902 7925 SAS_PORT_BROADCAST_D01_4,
7903 7926 &mpt->m_phy_info[phy_num].smhba_info);
7904 7927 break;
7905 7928 case MPI2_EVENT_PRIMITIVE_ASYNCHRONOUS_EVENT:
7906 7929 mptsas_smhba_log_sysevent(mpt,
7907 7930 ESC_SAS_HBA_PORT_BROADCAST,
7908 7931 SAS_PORT_BROADCAST_D04_7,
7909 7932 &mpt->m_phy_info[phy_num].smhba_info);
7910 7933 break;
7911 7934 case MPI2_EVENT_PRIMITIVE_RESERVED3:
7912 7935 mptsas_smhba_log_sysevent(mpt,
7913 7936 ESC_SAS_HBA_PORT_BROADCAST,
7914 7937 SAS_PORT_BROADCAST_D16_7,
7915 7938 &mpt->m_phy_info[phy_num].smhba_info);
7916 7939 break;
7917 7940 case MPI2_EVENT_PRIMITIVE_RESERVED4:
7918 7941 mptsas_smhba_log_sysevent(mpt,
7919 7942 ESC_SAS_HBA_PORT_BROADCAST,
7920 7943 SAS_PORT_BROADCAST_D29_7,
7921 7944 &mpt->m_phy_info[phy_num].smhba_info);
7922 7945 break;
7923 7946 case MPI2_EVENT_PRIMITIVE_CHANGE0_RESERVED:
7924 7947 mptsas_smhba_log_sysevent(mpt,
7925 7948 ESC_SAS_HBA_PORT_BROADCAST,
7926 7949 SAS_PORT_BROADCAST_D24_0,
7927 7950 &mpt->m_phy_info[phy_num].smhba_info);
7928 7951 break;
7929 7952 case MPI2_EVENT_PRIMITIVE_CHANGE1_RESERVED:
7930 7953 mptsas_smhba_log_sysevent(mpt,
7931 7954 ESC_SAS_HBA_PORT_BROADCAST,
7932 7955 SAS_PORT_BROADCAST_D27_4,
7933 7956 &mpt->m_phy_info[phy_num].smhba_info);
7934 7957 break;
7935 7958 default:
7936 7959 NDBG16(("mptsas%d: unknown BROADCAST PRIMITIVE"
7937 7960 " %x received",
7938 7961 mpt->m_instance, primitive));
7939 7962 break;
7940 7963 }
7941 7964 NDBG16(("mptsas%d sas broadcast primitive: "
7942 7965 "\tprimitive(0x%04x), phy(%d) complete\n",
7943 7966 mpt->m_instance, primitive, phy_num));
7944 7967 break;
7945 7968 }
7946 7969 case MPI2_EVENT_IR_VOLUME:
7947 7970 {
7948 7971 Mpi2EventDataIrVolume_t *irVolume;
7949 7972 uint16_t devhandle;
7950 7973 uint32_t state;
7951 7974 int config, vol;
7952 7975 uint8_t found = FALSE;
7953 7976
7954 7977 irVolume = (pMpi2EventDataIrVolume_t)eventreply->EventData;
7955 7978 state = ddi_get32(mpt->m_acc_reply_frame_hdl,
7956 7979 &irVolume->NewValue);
7957 7980 devhandle = ddi_get16(mpt->m_acc_reply_frame_hdl,
7958 7981 &irVolume->VolDevHandle);
7959 7982
7960 7983 NDBG20(("EVENT_IR_VOLUME event is received"));
7961 7984
7962 7985 /*
7963 7986 * Get latest RAID info and then find the DevHandle for this
7964 7987 * event in the configuration. If the DevHandle is not found
7965 7988 * just exit the event.
7966 7989 */
7967 7990 (void) mptsas_get_raid_info(mpt);
7968 7991 for (config = 0; (config < mpt->m_num_raid_configs) &&
7969 7992 (!found); config++) {
7970 7993 for (vol = 0; vol < MPTSAS_MAX_RAIDVOLS; vol++) {
7971 7994 if (mpt->m_raidconfig[config].m_raidvol[vol].
7972 7995 m_raidhandle == devhandle) {
7973 7996 found = TRUE;
7974 7997 break;
7975 7998 }
7976 7999 }
7977 8000 }
7978 8001 if (!found) {
7979 8002 break;
7980 8003 }
7981 8004
7982 8005 switch (irVolume->ReasonCode) {
7983 8006 case MPI2_EVENT_IR_VOLUME_RC_SETTINGS_CHANGED:
7984 8007 {
7985 8008 uint32_t i;
7986 8009 mpt->m_raidconfig[config].m_raidvol[vol].m_settings =
7987 8010 state;
7988 8011
7989 8012 i = state & MPI2_RAIDVOL0_SETTING_MASK_WRITE_CACHING;
7990 8013 mptsas_log(mpt, CE_NOTE, " Volume %d settings changed"
7991 8014 ", auto-config of hot-swap drives is %s"
7992 8015 ", write caching is %s"
7993 8016 ", hot-spare pool mask is %02x\n",
7994 8017 vol, state &
7995 8018 MPI2_RAIDVOL0_SETTING_AUTO_CONFIG_HSWAP_DISABLE
7996 8019 ? "disabled" : "enabled",
7997 8020 i == MPI2_RAIDVOL0_SETTING_UNCHANGED
7998 8021 ? "controlled by member disks" :
7999 8022 i == MPI2_RAIDVOL0_SETTING_DISABLE_WRITE_CACHING
8000 8023 ? "disabled" :
8001 8024 i == MPI2_RAIDVOL0_SETTING_ENABLE_WRITE_CACHING
8002 8025 ? "enabled" :
8003 8026 "incorrectly set",
8004 8027 (state >> 16) & 0xff);
8005 8028 break;
8006 8029 }
8007 8030 case MPI2_EVENT_IR_VOLUME_RC_STATE_CHANGED:
8008 8031 {
8009 8032 mpt->m_raidconfig[config].m_raidvol[vol].m_state =
8010 8033 (uint8_t)state;
8011 8034
8012 8035 mptsas_log(mpt, CE_NOTE,
8013 8036 "Volume %d is now %s\n", vol,
8014 8037 state == MPI2_RAID_VOL_STATE_OPTIMAL
8015 8038 ? "optimal" :
8016 8039 state == MPI2_RAID_VOL_STATE_DEGRADED
8017 8040 ? "degraded" :
8018 8041 state == MPI2_RAID_VOL_STATE_ONLINE
8019 8042 ? "online" :
8020 8043 state == MPI2_RAID_VOL_STATE_INITIALIZING
8021 8044 ? "initializing" :
8022 8045 state == MPI2_RAID_VOL_STATE_FAILED
8023 8046 ? "failed" :
8024 8047 state == MPI2_RAID_VOL_STATE_MISSING
8025 8048 ? "missing" :
8026 8049 "state unknown");
8027 8050 break;
8028 8051 }
8029 8052 case MPI2_EVENT_IR_VOLUME_RC_STATUS_FLAGS_CHANGED:
8030 8053 {
8031 8054 mpt->m_raidconfig[config].m_raidvol[vol].
8032 8055 m_statusflags = state;
8033 8056
8034 8057 mptsas_log(mpt, CE_NOTE,
8035 8058 " Volume %d is now %s%s%s%s%s%s%s%s%s\n",
8036 8059 vol,
8037 8060 state & MPI2_RAIDVOL0_STATUS_FLAG_ENABLED
8038 8061 ? ", enabled" : ", disabled",
8039 8062 state & MPI2_RAIDVOL0_STATUS_FLAG_QUIESCED
8040 8063 ? ", quiesced" : "",
8041 8064 state & MPI2_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE
8042 8065 ? ", inactive" : ", active",
8043 8066 state &
8044 8067 MPI2_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL
8045 8068 ? ", bad block table is full" : "",
8046 8069 state &
8047 8070 MPI2_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS
8048 8071 ? ", resync in progress" : "",
8049 8072 state & MPI2_RAIDVOL0_STATUS_FLAG_BACKGROUND_INIT
8050 8073 ? ", background initialization in progress" : "",
8051 8074 state &
8052 8075 MPI2_RAIDVOL0_STATUS_FLAG_CAPACITY_EXPANSION
8053 8076 ? ", capacity expansion in progress" : "",
8054 8077 state &
8055 8078 MPI2_RAIDVOL0_STATUS_FLAG_CONSISTENCY_CHECK
8056 8079 ? ", consistency check in progress" : "",
8057 8080 state & MPI2_RAIDVOL0_STATUS_FLAG_DATA_SCRUB
8058 8081 ? ", data scrub in progress" : "");
8059 8082 break;
8060 8083 }
8061 8084 default:
8062 8085 break;
8063 8086 }
8064 8087 break;
8065 8088 }
8066 8089 case MPI2_EVENT_IR_PHYSICAL_DISK:
8067 8090 {
8068 8091 Mpi2EventDataIrPhysicalDisk_t *irPhysDisk;
8069 8092 uint16_t devhandle, enchandle, slot;
8070 8093 uint32_t status, state;
8071 8094 uint8_t physdisknum, reason;
8072 8095
8073 8096 irPhysDisk = (Mpi2EventDataIrPhysicalDisk_t *)
8074 8097 eventreply->EventData;
8075 8098 physdisknum = ddi_get8(mpt->m_acc_reply_frame_hdl,
8076 8099 &irPhysDisk->PhysDiskNum);
8077 8100 devhandle = ddi_get16(mpt->m_acc_reply_frame_hdl,
8078 8101 &irPhysDisk->PhysDiskDevHandle);
8079 8102 enchandle = ddi_get16(mpt->m_acc_reply_frame_hdl,
8080 8103 &irPhysDisk->EnclosureHandle);
8081 8104 slot = ddi_get16(mpt->m_acc_reply_frame_hdl,
8082 8105 &irPhysDisk->Slot);
8083 8106 state = ddi_get32(mpt->m_acc_reply_frame_hdl,
8084 8107 &irPhysDisk->NewValue);
8085 8108 reason = ddi_get8(mpt->m_acc_reply_frame_hdl,
8086 8109 &irPhysDisk->ReasonCode);
8087 8110
8088 8111 NDBG20(("EVENT_IR_PHYSICAL_DISK event is received"));
8089 8112
8090 8113 switch (reason) {
8091 8114 case MPI2_EVENT_IR_PHYSDISK_RC_SETTINGS_CHANGED:
8092 8115 mptsas_log(mpt, CE_NOTE,
8093 8116 " PhysDiskNum %d with DevHandle 0x%x in slot %d "
8094 8117 "for enclosure with handle 0x%x is now in hot "
8095 8118 "spare pool %d",
8096 8119 physdisknum, devhandle, slot, enchandle,
8097 8120 (state >> 16) & 0xff);
8098 8121 break;
8099 8122
8100 8123 case MPI2_EVENT_IR_PHYSDISK_RC_STATUS_FLAGS_CHANGED:
8101 8124 status = state;
8102 8125 mptsas_log(mpt, CE_NOTE,
8103 8126 " PhysDiskNum %d with DevHandle 0x%x in slot %d "
8104 8127 "for enclosure with handle 0x%x is now "
8105 8128 "%s%s%s%s%s\n", physdisknum, devhandle, slot,
8106 8129 enchandle,
8107 8130 status & MPI2_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME
8108 8131 ? ", inactive" : ", active",
8109 8132 status & MPI2_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC
8110 8133 ? ", out of sync" : "",
8111 8134 status & MPI2_PHYSDISK0_STATUS_FLAG_QUIESCED
8112 8135 ? ", quiesced" : "",
8113 8136 status &
8114 8137 MPI2_PHYSDISK0_STATUS_FLAG_WRITE_CACHE_ENABLED
8115 8138 ? ", write cache enabled" : "",
8116 8139 status & MPI2_PHYSDISK0_STATUS_FLAG_OCE_TARGET
8117 8140 ? ", capacity expansion target" : "");
8118 8141 break;
8119 8142
8120 8143 case MPI2_EVENT_IR_PHYSDISK_RC_STATE_CHANGED:
8121 8144 mptsas_log(mpt, CE_NOTE,
8122 8145 " PhysDiskNum %d with DevHandle 0x%x in slot %d "
8123 8146 "for enclosure with handle 0x%x is now %s\n",
8124 8147 physdisknum, devhandle, slot, enchandle,
8125 8148 state == MPI2_RAID_PD_STATE_OPTIMAL
8126 8149 ? "optimal" :
8127 8150 state == MPI2_RAID_PD_STATE_REBUILDING
8128 8151 ? "rebuilding" :
8129 8152 state == MPI2_RAID_PD_STATE_DEGRADED
8130 8153 ? "degraded" :
8131 8154 state == MPI2_RAID_PD_STATE_HOT_SPARE
8132 8155 ? "a hot spare" :
8133 8156 state == MPI2_RAID_PD_STATE_ONLINE
8134 8157 ? "online" :
8135 8158 state == MPI2_RAID_PD_STATE_OFFLINE
8136 8159 ? "offline" :
8137 8160 state == MPI2_RAID_PD_STATE_NOT_COMPATIBLE
8138 8161 ? "not compatible" :
8139 8162 state == MPI2_RAID_PD_STATE_NOT_CONFIGURED
8140 8163 ? "not configured" :
8141 8164 "state unknown");
8142 8165 break;
8143 8166 }
8144 8167 break;
8145 8168 }
8146 8169 default:
8147 8170 NDBG20(("mptsas%d: unknown event %x received",
8148 8171 mpt->m_instance, event));
8149 8172 break;
8150 8173 }
8151 8174
8152 8175 /*
8153 8176 * Return the reply frame to the free queue.
8154 8177 */
8155 8178 ddi_put32(mpt->m_acc_free_queue_hdl,
8156 8179 &((uint32_t *)(void *)mpt->m_free_queue)[mpt->m_free_index], rfm);
8157 8180 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0,
8158 8181 DDI_DMA_SYNC_FORDEV);
8159 8182 if (++mpt->m_free_index == mpt->m_free_queue_depth) {
8160 8183 mpt->m_free_index = 0;
8161 8184 }
8162 8185 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex,
8163 8186 mpt->m_free_index);
8164 8187 mutex_exit(&mpt->m_mutex);
8165 8188 }
8166 8189
8167 8190 /*
8168 8191 * invoked from timeout() to restart qfull cmds with throttle == 0
8169 8192 */
8170 8193 static void
8171 8194 mptsas_restart_cmd(void *arg)
8172 8195 {
8173 8196 mptsas_t *mpt = arg;
8174 8197 mptsas_target_t *ptgt = NULL;
8175 8198
8176 8199 mutex_enter(&mpt->m_mutex);
8177 8200
8178 8201 mpt->m_restart_cmd_timeid = 0;
8179 8202
8180 8203 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL;
8181 8204 ptgt = refhash_next(mpt->m_targets, ptgt)) {
8182 8205 if (ptgt->m_reset_delay == 0) {
8183 8206 if (ptgt->m_t_throttle == QFULL_THROTTLE) {
8184 8207 mptsas_set_throttle(mpt, ptgt,
8185 8208 MAX_THROTTLE);
8186 8209 }
8187 8210 }
8188 8211 }
8189 8212 mptsas_restart_hba(mpt);
8190 8213 mutex_exit(&mpt->m_mutex);
8191 8214 }
8192 8215
8193 8216 void
8194 8217 mptsas_remove_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd)
8195 8218 {
8196 8219 int slot;
8197 8220 mptsas_slots_t *slots = mpt->m_active;
8198 8221 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
8199 8222
8200 8223 ASSERT(cmd != NULL);
8201 8224 ASSERT(cmd->cmd_queued == FALSE);
8202 8225
8203 8226 /*
8204 8227 * Task Management cmds are removed in their own routines. Also,
8205 8228 * we don't want to modify timeout based on TM cmds.
8206 8229 */
8207 8230 if (cmd->cmd_flags & CFLAG_TM_CMD) {
8208 8231 return;
8209 8232 }
8210 8233
8211 8234 slot = cmd->cmd_slot;
8212 8235
8213 8236 /*
8214 8237 * remove the cmd.
8215 8238 */
8216 8239 if (cmd == slots->m_slot[slot]) {
8217 8240 NDBG31(("mptsas_remove_cmd: removing cmd=0x%p, flags "
8218 8241 "0x%x", (void *)cmd, cmd->cmd_flags));
8219 8242 slots->m_slot[slot] = NULL;
8220 8243 mpt->m_ncmds--;
8221 8244
8222 8245 /*
8223 8246 * only decrement per target ncmds if command
8224 8247 * has a target associated with it.
8225 8248 */
8226 8249 if ((cmd->cmd_flags & CFLAG_CMDIOC) == 0) {
8227 8250 ptgt->m_t_ncmds--;
8228 8251 /*
8229 8252 * reset throttle if we just ran an untagged command
8230 8253 * to a tagged target
8231 8254 */
8232 8255 if ((ptgt->m_t_ncmds == 0) &&
8233 8256 ((cmd->cmd_pkt_flags & FLAG_TAGMASK) == 0)) {
8234 8257 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE);
8235 8258 }
8236 8259
8237 8260 /*
8238 8261 * Remove this command from the active queue.
8239 8262 */
8240 8263 if (cmd->cmd_active_expiration != 0) {
8241 8264 TAILQ_REMOVE(&ptgt->m_active_cmdq, cmd,
8242 8265 cmd_active_link);
8243 8266 cmd->cmd_active_expiration = 0;
8244 8267 }
8245 8268 }
8246 8269 }
8247 8270
8248 8271 /*
8249 8272 * This is all we need to do for ioc commands.
8250 8273 */
8251 8274 if (cmd->cmd_flags & CFLAG_CMDIOC) {
8252 8275 mptsas_return_to_pool(mpt, cmd);
8253 8276 return;
8254 8277 }
8255 8278
8256 8279 ASSERT(cmd != slots->m_slot[cmd->cmd_slot]);
8257 8280 }
8258 8281
8259 8282 /*
8260 8283 * accept all cmds on the tx_waitq if any and then
8261 8284 * start a fresh request from the top of the device queue.
8262 8285 *
8263 8286 * since there are always cmds queued on the tx_waitq, and rare cmds on
8264 8287 * the instance waitq, so this function should not be invoked in the ISR,
8265 8288 * the mptsas_restart_waitq() is invoked in the ISR instead. otherwise, the
8266 8289 * burden belongs to the IO dispatch CPUs is moved the interrupt CPU.
8267 8290 */
8268 8291 static void
8269 8292 mptsas_restart_hba(mptsas_t *mpt)
8270 8293 {
8271 8294 ASSERT(mutex_owned(&mpt->m_mutex));
8272 8295
8273 8296 mutex_enter(&mpt->m_tx_waitq_mutex);
8274 8297 if (mpt->m_tx_waitq) {
8275 8298 mptsas_accept_tx_waitq(mpt);
8276 8299 }
8277 8300 mutex_exit(&mpt->m_tx_waitq_mutex);
8278 8301 mptsas_restart_waitq(mpt);
8279 8302 }
8280 8303
8281 8304 /*
8282 8305 * start a fresh request from the top of the device queue
8283 8306 */
8284 8307 static void
8285 8308 mptsas_restart_waitq(mptsas_t *mpt)
8286 8309 {
8287 8310 mptsas_cmd_t *cmd, *next_cmd;
8288 8311 mptsas_target_t *ptgt = NULL;
8289 8312
8290 8313 NDBG1(("mptsas_restart_waitq: mpt=0x%p", (void *)mpt));
8291 8314
8292 8315 ASSERT(mutex_owned(&mpt->m_mutex));
8293 8316
8294 8317 /*
8295 8318 * If there is a reset delay, don't start any cmds. Otherwise, start
8296 8319 * as many cmds as possible.
8297 8320 * Since SMID 0 is reserved and the TM slot is reserved, the actual max
8298 8321 * commands is m_max_requests - 2.
8299 8322 */
8300 8323 cmd = mpt->m_waitq;
8301 8324
8302 8325 while (cmd != NULL) {
8303 8326 next_cmd = cmd->cmd_linkp;
8304 8327 if (cmd->cmd_flags & CFLAG_PASSTHRU) {
8305 8328 if (mptsas_save_cmd(mpt, cmd) == TRUE) {
8306 8329 /*
8307 8330 * passthru command get slot need
8308 8331 * set CFLAG_PREPARED.
8309 8332 */
8310 8333 cmd->cmd_flags |= CFLAG_PREPARED;
8311 8334 mptsas_waitq_delete(mpt, cmd);
8312 8335 mptsas_start_passthru(mpt, cmd);
8313 8336 }
8314 8337 cmd = next_cmd;
8315 8338 continue;
8316 8339 }
8317 8340 if (cmd->cmd_flags & CFLAG_CONFIG) {
8318 8341 if (mptsas_save_cmd(mpt, cmd) == TRUE) {
8319 8342 /*
8320 8343 * Send the config page request and delete it
8321 8344 * from the waitq.
8322 8345 */
8323 8346 cmd->cmd_flags |= CFLAG_PREPARED;
8324 8347 mptsas_waitq_delete(mpt, cmd);
8325 8348 mptsas_start_config_page_access(mpt, cmd);
8326 8349 }
8327 8350 cmd = next_cmd;
8328 8351 continue;
8329 8352 }
8330 8353 if (cmd->cmd_flags & CFLAG_FW_DIAG) {
8331 8354 if (mptsas_save_cmd(mpt, cmd) == TRUE) {
8332 8355 /*
8333 8356 * Send the FW Diag request and delete if from
8334 8357 * the waitq.
8335 8358 */
8336 8359 cmd->cmd_flags |= CFLAG_PREPARED;
8337 8360 mptsas_waitq_delete(mpt, cmd);
8338 8361 mptsas_start_diag(mpt, cmd);
8339 8362 }
8340 8363 cmd = next_cmd;
8341 8364 continue;
8342 8365 }
8343 8366
8344 8367 ptgt = cmd->cmd_tgt_addr;
8345 8368 if (ptgt && (ptgt->m_t_throttle == DRAIN_THROTTLE) &&
8346 8369 (ptgt->m_t_ncmds == 0)) {
8347 8370 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE);
8348 8371 }
8349 8372 if ((mpt->m_ncmds <= (mpt->m_max_requests - 2)) &&
8350 8373 (ptgt && (ptgt->m_reset_delay == 0)) &&
8351 8374 (ptgt && (ptgt->m_t_ncmds <
8352 8375 ptgt->m_t_throttle))) {
8353 8376 if (mptsas_save_cmd(mpt, cmd) == TRUE) {
8354 8377 mptsas_waitq_delete(mpt, cmd);
8355 8378 (void) mptsas_start_cmd(mpt, cmd);
8356 8379 }
8357 8380 }
8358 8381 cmd = next_cmd;
8359 8382 }
8360 8383 }
8361 8384 /*
8362 8385 * Cmds are queued if tran_start() doesn't get the m_mutexlock(no wait).
8363 8386 * Accept all those queued cmds before new cmd is accept so that the
8364 8387 * cmds are sent in order.
8365 8388 */
8366 8389 static void
8367 8390 mptsas_accept_tx_waitq(mptsas_t *mpt)
8368 8391 {
8369 8392 mptsas_cmd_t *cmd;
8370 8393
8371 8394 ASSERT(mutex_owned(&mpt->m_mutex));
8372 8395 ASSERT(mutex_owned(&mpt->m_tx_waitq_mutex));
8373 8396
8374 8397 /*
8375 8398 * A Bus Reset could occur at any time and flush the tx_waitq,
8376 8399 * so we cannot count on the tx_waitq to contain even one cmd.
8377 8400 * And when the m_tx_waitq_mutex is released and run
8378 8401 * mptsas_accept_pkt(), the tx_waitq may be flushed.
8379 8402 */
8380 8403 cmd = mpt->m_tx_waitq;
8381 8404 for (;;) {
8382 8405 if ((cmd = mpt->m_tx_waitq) == NULL) {
8383 8406 mpt->m_tx_draining = 0;
8384 8407 break;
8385 8408 }
8386 8409 if ((mpt->m_tx_waitq = cmd->cmd_linkp) == NULL) {
8387 8410 mpt->m_tx_waitqtail = &mpt->m_tx_waitq;
8388 8411 }
8389 8412 cmd->cmd_linkp = NULL;
8390 8413 mutex_exit(&mpt->m_tx_waitq_mutex);
8391 8414 if (mptsas_accept_pkt(mpt, cmd) != TRAN_ACCEPT)
8392 8415 cmn_err(CE_WARN, "mpt: mptsas_accept_tx_waitq: failed "
8393 8416 "to accept cmd on queue\n");
8394 8417 mutex_enter(&mpt->m_tx_waitq_mutex);
8395 8418 }
8396 8419 }
8397 8420
8398 8421
8399 8422 /*
8400 8423 * mpt tag type lookup
8401 8424 */
8402 8425 static char mptsas_tag_lookup[] =
8403 8426 {0, MSG_HEAD_QTAG, MSG_ORDERED_QTAG, 0, MSG_SIMPLE_QTAG};
8404 8427
8405 8428 static int
8406 8429 mptsas_start_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd)
8407 8430 {
8408 8431 struct scsi_pkt *pkt = CMD2PKT(cmd);
8409 8432 uint32_t control = 0;
8410 8433 caddr_t mem, arsbuf;
8411 8434 pMpi2SCSIIORequest_t io_request;
8412 8435 ddi_dma_handle_t dma_hdl = mpt->m_dma_req_frame_hdl;
8413 8436 ddi_acc_handle_t acc_hdl = mpt->m_acc_req_frame_hdl;
8414 8437 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
8415 8438 uint16_t SMID, io_flags = 0;
8416 8439 uint8_t ars_size;
8417 8440 uint64_t request_desc;
8418 8441 uint32_t ars_dmaaddrlow;
8419 8442 mptsas_cmd_t *c;
8420 8443
8421 8444 NDBG1(("mptsas_start_cmd: cmd=0x%p, flags 0x%x", (void *)cmd,
8422 8445 cmd->cmd_flags));
8423 8446
8424 8447 /*
8425 8448 * Set SMID and increment index. Rollover to 1 instead of 0 if index
8426 8449 * is at the max. 0 is an invalid SMID, so we call the first index 1.
8427 8450 */
8428 8451 SMID = cmd->cmd_slot;
8429 8452
8430 8453 /*
8431 8454 * It is possible for back to back device reset to
8432 8455 * happen before the reset delay has expired. That's
8433 8456 * ok, just let the device reset go out on the bus.
8434 8457 */
8435 8458 if ((cmd->cmd_pkt_flags & FLAG_NOINTR) == 0) {
8436 8459 ASSERT(ptgt->m_reset_delay == 0);
8437 8460 }
8438 8461
8439 8462 /*
8440 8463 * if a non-tagged cmd is submitted to an active tagged target
8441 8464 * then drain before submitting this cmd; SCSI-2 allows RQSENSE
8442 8465 * to be untagged
8443 8466 */
8444 8467 if (((cmd->cmd_pkt_flags & FLAG_TAGMASK) == 0) &&
8445 8468 (ptgt->m_t_ncmds > 1) &&
8446 8469 ((cmd->cmd_flags & CFLAG_TM_CMD) == 0) &&
8447 8470 (*(cmd->cmd_pkt->pkt_cdbp) != SCMD_REQUEST_SENSE)) {
8448 8471 if ((cmd->cmd_pkt_flags & FLAG_NOINTR) == 0) {
8449 8472 NDBG23(("target=%d, untagged cmd, start draining\n",
8450 8473 ptgt->m_devhdl));
8451 8474
8452 8475 if (ptgt->m_reset_delay == 0) {
8453 8476 mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE);
8454 8477 }
8455 8478
8456 8479 mptsas_remove_cmd(mpt, cmd);
8457 8480 cmd->cmd_pkt_flags |= FLAG_HEAD;
8458 8481 mptsas_waitq_add(mpt, cmd);
8459 8482 }
8460 8483 return (DDI_FAILURE);
8461 8484 }
8462 8485
8463 8486 /*
8464 8487 * Set correct tag bits.
8465 8488 */
8466 8489 if (cmd->cmd_pkt_flags & FLAG_TAGMASK) {
8467 8490 switch (mptsas_tag_lookup[((cmd->cmd_pkt_flags &
8468 8491 FLAG_TAGMASK) >> 12)]) {
8469 8492 case MSG_SIMPLE_QTAG:
8470 8493 control |= MPI2_SCSIIO_CONTROL_SIMPLEQ;
8471 8494 break;
8472 8495 case MSG_HEAD_QTAG:
8473 8496 control |= MPI2_SCSIIO_CONTROL_HEADOFQ;
8474 8497 break;
8475 8498 case MSG_ORDERED_QTAG:
8476 8499 control |= MPI2_SCSIIO_CONTROL_ORDEREDQ;
8477 8500 break;
8478 8501 default:
8479 8502 mptsas_log(mpt, CE_WARN, "mpt: Invalid tag type\n");
8480 8503 break;
8481 8504 }
8482 8505 } else {
8483 8506 if (*(cmd->cmd_pkt->pkt_cdbp) != SCMD_REQUEST_SENSE) {
8484 8507 ptgt->m_t_throttle = 1;
8485 8508 }
8486 8509 control |= MPI2_SCSIIO_CONTROL_SIMPLEQ;
8487 8510 }
8488 8511
8489 8512 if (cmd->cmd_pkt_flags & FLAG_TLR) {
8490 8513 control |= MPI2_SCSIIO_CONTROL_TLR_ON;
8491 8514 }
8492 8515
8493 8516 mem = mpt->m_req_frame + (mpt->m_req_frame_size * SMID);
8494 8517 io_request = (pMpi2SCSIIORequest_t)mem;
8495 8518 if (cmd->cmd_extrqslen != 0) {
8496 8519 /*
8497 8520 * Mapping of the buffer was done in mptsas_pkt_alloc_extern().
8498 8521 * Calculate the DMA address with the same offset.
8499 8522 */
8500 8523 arsbuf = cmd->cmd_arq_buf;
8501 8524 ars_size = cmd->cmd_extrqslen;
8502 8525 ars_dmaaddrlow = (mpt->m_req_sense_dma_addr +
8503 8526 ((uintptr_t)arsbuf - (uintptr_t)mpt->m_req_sense)) &
8504 8527 0xffffffffu;
8505 8528 } else {
8506 8529 arsbuf = mpt->m_req_sense + (mpt->m_req_sense_size * (SMID-1));
8507 8530 cmd->cmd_arq_buf = arsbuf;
8508 8531 ars_size = mpt->m_req_sense_size;
8509 8532 ars_dmaaddrlow = (mpt->m_req_sense_dma_addr +
8510 8533 (mpt->m_req_sense_size * (SMID-1))) &
8511 8534 0xffffffffu;
8512 8535 }
8513 8536 bzero(io_request, sizeof (Mpi2SCSIIORequest_t));
8514 8537 bzero(arsbuf, ars_size);
8515 8538
8516 8539 ddi_put8(acc_hdl, &io_request->SGLOffset0, offsetof
8517 8540 (MPI2_SCSI_IO_REQUEST, SGL) / 4);
8518 8541 mptsas_init_std_hdr(acc_hdl, io_request, ptgt->m_devhdl, Lun(cmd), 0,
8519 8542 MPI2_FUNCTION_SCSI_IO_REQUEST);
8520 8543
8521 8544 (void) ddi_rep_put8(acc_hdl, (uint8_t *)pkt->pkt_cdbp,
8522 8545 io_request->CDB.CDB32, cmd->cmd_cdblen, DDI_DEV_AUTOINCR);
8523 8546
8524 8547 io_flags = cmd->cmd_cdblen;
8525 8548 if (mptsas_use_fastpath &&
8526 8549 ptgt->m_io_flags & MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH) {
8527 8550 io_flags |= MPI25_SCSIIO_IOFLAGS_FAST_PATH;
8528 8551 request_desc = MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO;
8529 8552 } else {
8530 8553 request_desc = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO;
8531 8554 }
8532 8555 ddi_put16(acc_hdl, &io_request->IoFlags, io_flags);
8533 8556 /*
8534 8557 * setup the Scatter/Gather DMA list for this request
8535 8558 */
8536 8559 if (cmd->cmd_cookiec > 0) {
8537 8560 mptsas_sge_setup(mpt, cmd, &control, io_request, acc_hdl);
8538 8561 } else {
8539 8562 ddi_put32(acc_hdl, &io_request->SGL.MpiSimple.FlagsLength,
8540 8563 ((uint32_t)MPI2_SGE_FLAGS_LAST_ELEMENT |
8541 8564 MPI2_SGE_FLAGS_END_OF_BUFFER |
8542 8565 MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
8543 8566 MPI2_SGE_FLAGS_END_OF_LIST) << MPI2_SGE_FLAGS_SHIFT);
8544 8567 }
8545 8568
8546 8569 /*
8547 8570 * save ARQ information
8548 8571 */
8549 8572 ddi_put8(acc_hdl, &io_request->SenseBufferLength, ars_size);
8550 8573 ddi_put32(acc_hdl, &io_request->SenseBufferLowAddress, ars_dmaaddrlow);
8551 8574
8552 8575 ddi_put32(acc_hdl, &io_request->Control, control);
8553 8576
8554 8577 NDBG31(("starting message=%d(0x%p), with cmd=0x%p",
8555 8578 SMID, (void *)io_request, (void *)cmd));
8556 8579
8557 8580 (void) ddi_dma_sync(dma_hdl, 0, 0, DDI_DMA_SYNC_FORDEV);
8558 8581 (void) ddi_dma_sync(mpt->m_dma_req_sense_hdl, 0, 0,
8559 8582 DDI_DMA_SYNC_FORDEV);
8560 8583
8561 8584 /*
8562 8585 * Build request descriptor and write it to the request desc post reg.
8563 8586 */
8564 8587 request_desc |= (SMID << 16);
8565 8588 request_desc |= (uint64_t)ptgt->m_devhdl << 48;
8566 8589 MPTSAS_START_CMD(mpt, request_desc);
8567 8590
8568 8591 /*
8569 8592 * Start timeout.
8570 8593 */
8571 8594 cmd->cmd_active_expiration =
8572 8595 gethrtime() + (hrtime_t)pkt->pkt_time * NANOSEC;
8573 8596 #ifdef MPTSAS_TEST
8574 8597 /*
8575 8598 * Force timeouts to happen immediately.
8576 8599 */
8577 8600 if (mptsas_test_timeouts)
8578 8601 cmd->cmd_active_expiration = gethrtime();
8579 8602 #endif
8580 8603 c = TAILQ_FIRST(&ptgt->m_active_cmdq);
8581 8604 if (c == NULL ||
8582 8605 c->cmd_active_expiration < cmd->cmd_active_expiration) {
8583 8606 /*
8584 8607 * Common case is that this is the last pending expiration
8585 8608 * (or queue is empty). Insert at head of the queue.
8586 8609 */
8587 8610 TAILQ_INSERT_HEAD(&ptgt->m_active_cmdq, cmd, cmd_active_link);
8588 8611 } else {
8589 8612 /*
8590 8613 * Queue is not empty and first element expires later than
8591 8614 * this command. Search for element expiring sooner.
8592 8615 */
8593 8616 while ((c = TAILQ_NEXT(c, cmd_active_link)) != NULL) {
8594 8617 if (c->cmd_active_expiration <
8595 8618 cmd->cmd_active_expiration) {
8596 8619 TAILQ_INSERT_BEFORE(c, cmd, cmd_active_link);
8597 8620 break;
8598 8621 }
8599 8622 }
8600 8623 if (c == NULL) {
8601 8624 /*
8602 8625 * No element found expiring sooner, append to
8603 8626 * non-empty queue.
8604 8627 */
8605 8628 TAILQ_INSERT_TAIL(&ptgt->m_active_cmdq, cmd,
8606 8629 cmd_active_link);
8607 8630 }
8608 8631 }
8609 8632
8610 8633 if ((mptsas_check_dma_handle(dma_hdl) != DDI_SUCCESS) ||
8611 8634 (mptsas_check_acc_handle(acc_hdl) != DDI_SUCCESS)) {
8612 8635 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
8613 8636 return (DDI_FAILURE);
8614 8637 }
8615 8638 return (DDI_SUCCESS);
8616 8639 }
8617 8640
8618 8641 /*
8619 8642 * Select a helper thread to handle current doneq
8620 8643 */
8621 8644 static void
8622 8645 mptsas_deliver_doneq_thread(mptsas_t *mpt)
8623 8646 {
8624 8647 uint64_t t, i;
8625 8648 uint32_t min = 0xffffffff;
8626 8649 mptsas_doneq_thread_list_t *item;
8627 8650
8628 8651 for (i = 0; i < mpt->m_doneq_thread_n; i++) {
8629 8652 item = &mpt->m_doneq_thread_id[i];
8630 8653 /*
8631 8654 * If the completed command on help thread[i] less than
8632 8655 * doneq_thread_threshold, then pick the thread[i]. Otherwise
8633 8656 * pick a thread which has least completed command.
8634 8657 */
8635 8658
8636 8659 mutex_enter(&item->mutex);
8637 8660 if (item->len < mpt->m_doneq_thread_threshold) {
8638 8661 t = i;
8639 8662 mutex_exit(&item->mutex);
8640 8663 break;
8641 8664 }
8642 8665 if (item->len < min) {
8643 8666 min = item->len;
8644 8667 t = i;
8645 8668 }
8646 8669 mutex_exit(&item->mutex);
8647 8670 }
8648 8671 mutex_enter(&mpt->m_doneq_thread_id[t].mutex);
8649 8672 mptsas_doneq_mv(mpt, t);
8650 8673 cv_signal(&mpt->m_doneq_thread_id[t].cv);
8651 8674 mutex_exit(&mpt->m_doneq_thread_id[t].mutex);
8652 8675 }
8653 8676
8654 8677 /*
8655 8678 * move the current global doneq to the doneq of thead[t]
8656 8679 */
8657 8680 static void
8658 8681 mptsas_doneq_mv(mptsas_t *mpt, uint64_t t)
8659 8682 {
8660 8683 mptsas_cmd_t *cmd;
8661 8684 mptsas_doneq_thread_list_t *item = &mpt->m_doneq_thread_id[t];
8662 8685
8663 8686 ASSERT(mutex_owned(&item->mutex));
8664 8687 while ((cmd = mpt->m_doneq) != NULL) {
8665 8688 if ((mpt->m_doneq = cmd->cmd_linkp) == NULL) {
8666 8689 mpt->m_donetail = &mpt->m_doneq;
8667 8690 }
8668 8691 cmd->cmd_linkp = NULL;
8669 8692 *item->donetail = cmd;
8670 8693 item->donetail = &cmd->cmd_linkp;
8671 8694 mpt->m_doneq_len--;
8672 8695 item->len++;
8673 8696 }
8674 8697 }
8675 8698
8676 8699 void
8677 8700 mptsas_fma_check(mptsas_t *mpt, mptsas_cmd_t *cmd)
8678 8701 {
8679 8702 struct scsi_pkt *pkt = CMD2PKT(cmd);
8680 8703
8681 8704 /* Check all acc and dma handles */
8682 8705 if ((mptsas_check_acc_handle(mpt->m_datap) !=
8683 8706 DDI_SUCCESS) ||
8684 8707 (mptsas_check_acc_handle(mpt->m_acc_req_frame_hdl) !=
8685 8708 DDI_SUCCESS) ||
8686 8709 (mptsas_check_acc_handle(mpt->m_acc_req_sense_hdl) !=
8687 8710 DDI_SUCCESS) ||
8688 8711 (mptsas_check_acc_handle(mpt->m_acc_reply_frame_hdl) !=
8689 8712 DDI_SUCCESS) ||
8690 8713 (mptsas_check_acc_handle(mpt->m_acc_free_queue_hdl) !=
8691 8714 DDI_SUCCESS) ||
8692 8715 (mptsas_check_acc_handle(mpt->m_acc_post_queue_hdl) !=
8693 8716 DDI_SUCCESS) ||
8694 8717 (mptsas_check_acc_handle(mpt->m_hshk_acc_hdl) !=
8695 8718 DDI_SUCCESS) ||
8696 8719 (mptsas_check_acc_handle(mpt->m_config_handle) !=
8697 8720 DDI_SUCCESS)) {
8698 8721 ddi_fm_service_impact(mpt->m_dip,
8699 8722 DDI_SERVICE_UNAFFECTED);
8700 8723 ddi_fm_acc_err_clear(mpt->m_config_handle,
8701 8724 DDI_FME_VER0);
8702 8725 pkt->pkt_reason = CMD_TRAN_ERR;
8703 8726 pkt->pkt_statistics = 0;
8704 8727 }
8705 8728 if ((mptsas_check_dma_handle(mpt->m_dma_req_frame_hdl) !=
8706 8729 DDI_SUCCESS) ||
8707 8730 (mptsas_check_dma_handle(mpt->m_dma_req_sense_hdl) !=
8708 8731 DDI_SUCCESS) ||
8709 8732 (mptsas_check_dma_handle(mpt->m_dma_reply_frame_hdl) !=
8710 8733 DDI_SUCCESS) ||
8711 8734 (mptsas_check_dma_handle(mpt->m_dma_free_queue_hdl) !=
8712 8735 DDI_SUCCESS) ||
8713 8736 (mptsas_check_dma_handle(mpt->m_dma_post_queue_hdl) !=
8714 8737 DDI_SUCCESS) ||
8715 8738 (mptsas_check_dma_handle(mpt->m_hshk_dma_hdl) !=
8716 8739 DDI_SUCCESS)) {
8717 8740 ddi_fm_service_impact(mpt->m_dip,
8718 8741 DDI_SERVICE_UNAFFECTED);
8719 8742 pkt->pkt_reason = CMD_TRAN_ERR;
8720 8743 pkt->pkt_statistics = 0;
8721 8744 }
8722 8745 if (cmd->cmd_dmahandle &&
8723 8746 (mptsas_check_dma_handle(cmd->cmd_dmahandle) != DDI_SUCCESS)) {
8724 8747 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
8725 8748 pkt->pkt_reason = CMD_TRAN_ERR;
8726 8749 pkt->pkt_statistics = 0;
8727 8750 }
8728 8751 if ((cmd->cmd_extra_frames &&
8729 8752 ((mptsas_check_dma_handle(cmd->cmd_extra_frames->m_dma_hdl) !=
8730 8753 DDI_SUCCESS) ||
8731 8754 (mptsas_check_acc_handle(cmd->cmd_extra_frames->m_acc_hdl) !=
8732 8755 DDI_SUCCESS)))) {
8733 8756 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
8734 8757 pkt->pkt_reason = CMD_TRAN_ERR;
8735 8758 pkt->pkt_statistics = 0;
8736 8759 }
8737 8760 }
8738 8761
8739 8762 /*
8740 8763 * These routines manipulate the queue of commands that
8741 8764 * are waiting for their completion routines to be called.
8742 8765 * The queue is usually in FIFO order but on an MP system
8743 8766 * it's possible for the completion routines to get out
8744 8767 * of order. If that's a problem you need to add a global
8745 8768 * mutex around the code that calls the completion routine
8746 8769 * in the interrupt handler.
8747 8770 */
8748 8771 static void
8749 8772 mptsas_doneq_add(mptsas_t *mpt, mptsas_cmd_t *cmd)
8750 8773 {
8751 8774 struct scsi_pkt *pkt = CMD2PKT(cmd);
8752 8775
8753 8776 NDBG31(("mptsas_doneq_add: cmd=0x%p", (void *)cmd));
8754 8777
8755 8778 ASSERT((cmd->cmd_flags & CFLAG_COMPLETED) == 0);
8756 8779 cmd->cmd_linkp = NULL;
8757 8780 cmd->cmd_flags |= CFLAG_FINISHED;
8758 8781 cmd->cmd_flags &= ~CFLAG_IN_TRANSPORT;
8759 8782
8760 8783 mptsas_fma_check(mpt, cmd);
8761 8784
8762 8785 /*
8763 8786 * only add scsi pkts that have completion routines to
8764 8787 * the doneq. no intr cmds do not have callbacks.
8765 8788 */
8766 8789 if (pkt && (pkt->pkt_comp)) {
8767 8790 *mpt->m_donetail = cmd;
8768 8791 mpt->m_donetail = &cmd->cmd_linkp;
8769 8792 mpt->m_doneq_len++;
8770 8793 }
8771 8794 }
8772 8795
8773 8796 static mptsas_cmd_t *
8774 8797 mptsas_doneq_thread_rm(mptsas_t *mpt, uint64_t t)
8775 8798 {
8776 8799 mptsas_cmd_t *cmd;
8777 8800 mptsas_doneq_thread_list_t *item = &mpt->m_doneq_thread_id[t];
8778 8801
8779 8802 /* pop one off the done queue */
8780 8803 if ((cmd = item->doneq) != NULL) {
8781 8804 /* if the queue is now empty fix the tail pointer */
8782 8805 NDBG31(("mptsas_doneq_thread_rm: cmd=0x%p", (void *)cmd));
8783 8806 if ((item->doneq = cmd->cmd_linkp) == NULL) {
8784 8807 item->donetail = &item->doneq;
8785 8808 }
8786 8809 cmd->cmd_linkp = NULL;
8787 8810 item->len--;
8788 8811 }
8789 8812 return (cmd);
8790 8813 }
8791 8814
8792 8815 static void
8793 8816 mptsas_doneq_empty(mptsas_t *mpt)
8794 8817 {
8795 8818 if (mpt->m_doneq && !mpt->m_in_callback) {
8796 8819 mptsas_cmd_t *cmd, *next;
8797 8820 struct scsi_pkt *pkt;
8798 8821
8799 8822 mpt->m_in_callback = 1;
8800 8823 cmd = mpt->m_doneq;
8801 8824 mpt->m_doneq = NULL;
8802 8825 mpt->m_donetail = &mpt->m_doneq;
8803 8826 mpt->m_doneq_len = 0;
8804 8827
8805 8828 mutex_exit(&mpt->m_mutex);
8806 8829 /*
8807 8830 * run the completion routines of all the
8808 8831 * completed commands
8809 8832 */
8810 8833 while (cmd != NULL) {
8811 8834 next = cmd->cmd_linkp;
8812 8835 cmd->cmd_linkp = NULL;
8813 8836 /* run this command's completion routine */
8814 8837 cmd->cmd_flags |= CFLAG_COMPLETED;
8815 8838 pkt = CMD2PKT(cmd);
8816 8839 mptsas_pkt_comp(pkt, cmd);
8817 8840 cmd = next;
8818 8841 }
8819 8842 mutex_enter(&mpt->m_mutex);
8820 8843 mpt->m_in_callback = 0;
8821 8844 }
8822 8845 }
8823 8846
8824 8847 /*
8825 8848 * These routines manipulate the target's queue of pending requests
8826 8849 */
8827 8850 void
8828 8851 mptsas_waitq_add(mptsas_t *mpt, mptsas_cmd_t *cmd)
8829 8852 {
8830 8853 NDBG7(("mptsas_waitq_add: cmd=0x%p", (void *)cmd));
8831 8854 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
8832 8855 cmd->cmd_queued = TRUE;
8833 8856 if (ptgt)
8834 8857 ptgt->m_t_nwait++;
8835 8858 if (cmd->cmd_pkt_flags & FLAG_HEAD) {
8836 8859 if ((cmd->cmd_linkp = mpt->m_waitq) == NULL) {
8837 8860 mpt->m_waitqtail = &cmd->cmd_linkp;
8838 8861 }
8839 8862 mpt->m_waitq = cmd;
8840 8863 } else {
8841 8864 cmd->cmd_linkp = NULL;
8842 8865 *(mpt->m_waitqtail) = cmd;
8843 8866 mpt->m_waitqtail = &cmd->cmd_linkp;
8844 8867 }
8845 8868 }
8846 8869
8847 8870 static mptsas_cmd_t *
8848 8871 mptsas_waitq_rm(mptsas_t *mpt)
8849 8872 {
8850 8873 mptsas_cmd_t *cmd;
8851 8874 mptsas_target_t *ptgt;
8852 8875 NDBG7(("mptsas_waitq_rm"));
8853 8876
8854 8877 MPTSAS_WAITQ_RM(mpt, cmd);
8855 8878
8856 8879 NDBG7(("mptsas_waitq_rm: cmd=0x%p", (void *)cmd));
8857 8880 if (cmd) {
8858 8881 ptgt = cmd->cmd_tgt_addr;
8859 8882 if (ptgt) {
8860 8883 ptgt->m_t_nwait--;
8861 8884 ASSERT(ptgt->m_t_nwait >= 0);
8862 8885 }
8863 8886 }
8864 8887 return (cmd);
8865 8888 }
8866 8889
8867 8890 /*
8868 8891 * remove specified cmd from the middle of the wait queue.
8869 8892 */
8870 8893 static void
8871 8894 mptsas_waitq_delete(mptsas_t *mpt, mptsas_cmd_t *cmd)
8872 8895 {
8873 8896 mptsas_cmd_t *prevp = mpt->m_waitq;
8874 8897 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
8875 8898
8876 8899 NDBG7(("mptsas_waitq_delete: mpt=0x%p cmd=0x%p",
8877 8900 (void *)mpt, (void *)cmd));
8878 8901 if (ptgt) {
8879 8902 ptgt->m_t_nwait--;
8880 8903 ASSERT(ptgt->m_t_nwait >= 0);
8881 8904 }
8882 8905
8883 8906 if (prevp == cmd) {
8884 8907 if ((mpt->m_waitq = cmd->cmd_linkp) == NULL)
8885 8908 mpt->m_waitqtail = &mpt->m_waitq;
8886 8909
8887 8910 cmd->cmd_linkp = NULL;
8888 8911 cmd->cmd_queued = FALSE;
8889 8912 NDBG7(("mptsas_waitq_delete: mpt=0x%p cmd=0x%p",
8890 8913 (void *)mpt, (void *)cmd));
8891 8914 return;
8892 8915 }
8893 8916
8894 8917 while (prevp != NULL) {
8895 8918 if (prevp->cmd_linkp == cmd) {
8896 8919 if ((prevp->cmd_linkp = cmd->cmd_linkp) == NULL)
8897 8920 mpt->m_waitqtail = &prevp->cmd_linkp;
8898 8921
8899 8922 cmd->cmd_linkp = NULL;
8900 8923 cmd->cmd_queued = FALSE;
8901 8924 NDBG7(("mptsas_waitq_delete: mpt=0x%p cmd=0x%p",
8902 8925 (void *)mpt, (void *)cmd));
8903 8926 return;
8904 8927 }
8905 8928 prevp = prevp->cmd_linkp;
8906 8929 }
8907 8930 cmn_err(CE_PANIC, "mpt: mptsas_waitq_delete: queue botch");
8908 8931 }
8909 8932
8910 8933 static mptsas_cmd_t *
8911 8934 mptsas_tx_waitq_rm(mptsas_t *mpt)
8912 8935 {
8913 8936 mptsas_cmd_t *cmd;
8914 8937 NDBG7(("mptsas_tx_waitq_rm"));
8915 8938
8916 8939 MPTSAS_TX_WAITQ_RM(mpt, cmd);
8917 8940
8918 8941 NDBG7(("mptsas_tx_waitq_rm: cmd=0x%p", (void *)cmd));
8919 8942
8920 8943 return (cmd);
8921 8944 }
8922 8945
8923 8946 /*
8924 8947 * remove specified cmd from the middle of the tx_waitq.
8925 8948 */
8926 8949 static void
8927 8950 mptsas_tx_waitq_delete(mptsas_t *mpt, mptsas_cmd_t *cmd)
8928 8951 {
8929 8952 mptsas_cmd_t *prevp = mpt->m_tx_waitq;
8930 8953
8931 8954 NDBG7(("mptsas_tx_waitq_delete: mpt=0x%p cmd=0x%p",
8932 8955 (void *)mpt, (void *)cmd));
8933 8956
8934 8957 if (prevp == cmd) {
8935 8958 if ((mpt->m_tx_waitq = cmd->cmd_linkp) == NULL)
8936 8959 mpt->m_tx_waitqtail = &mpt->m_tx_waitq;
8937 8960
8938 8961 cmd->cmd_linkp = NULL;
8939 8962 cmd->cmd_queued = FALSE;
8940 8963 NDBG7(("mptsas_tx_waitq_delete: mpt=0x%p cmd=0x%p",
8941 8964 (void *)mpt, (void *)cmd));
8942 8965 return;
8943 8966 }
8944 8967
8945 8968 while (prevp != NULL) {
8946 8969 if (prevp->cmd_linkp == cmd) {
8947 8970 if ((prevp->cmd_linkp = cmd->cmd_linkp) == NULL)
8948 8971 mpt->m_tx_waitqtail = &prevp->cmd_linkp;
8949 8972
8950 8973 cmd->cmd_linkp = NULL;
8951 8974 cmd->cmd_queued = FALSE;
8952 8975 NDBG7(("mptsas_tx_waitq_delete: mpt=0x%p cmd=0x%p",
8953 8976 (void *)mpt, (void *)cmd));
8954 8977 return;
8955 8978 }
8956 8979 prevp = prevp->cmd_linkp;
8957 8980 }
8958 8981 cmn_err(CE_PANIC, "mpt: mptsas_tx_waitq_delete: queue botch");
8959 8982 }
8960 8983
8961 8984 /*
8962 8985 * device and bus reset handling
8963 8986 *
8964 8987 * Notes:
8965 8988 * - RESET_ALL: reset the controller
8966 8989 * - RESET_TARGET: reset the target specified in scsi_address
8967 8990 */
8968 8991 static int
8969 8992 mptsas_scsi_reset(struct scsi_address *ap, int level)
8970 8993 {
8971 8994 mptsas_t *mpt = ADDR2MPT(ap);
8972 8995 int rval;
8973 8996 mptsas_tgt_private_t *tgt_private;
8974 8997 mptsas_target_t *ptgt = NULL;
8975 8998
8976 8999 tgt_private = (mptsas_tgt_private_t *)ap->a_hba_tran->tran_tgt_private;
8977 9000 ptgt = tgt_private->t_private;
8978 9001 if (ptgt == NULL) {
8979 9002 return (FALSE);
8980 9003 }
8981 9004 NDBG22(("mptsas_scsi_reset: target=%d level=%d", ptgt->m_devhdl,
8982 9005 level));
8983 9006
8984 9007 mutex_enter(&mpt->m_mutex);
8985 9008 /*
8986 9009 * if we are not in panic set up a reset delay for this target
8987 9010 */
8988 9011 if (!ddi_in_panic()) {
8989 9012 mptsas_setup_bus_reset_delay(mpt);
8990 9013 } else {
8991 9014 drv_usecwait(mpt->m_scsi_reset_delay * 1000);
8992 9015 }
8993 9016 rval = mptsas_do_scsi_reset(mpt, ptgt->m_devhdl);
8994 9017 mutex_exit(&mpt->m_mutex);
8995 9018
8996 9019 /*
8997 9020 * The transport layer expect to only see TRUE and
8998 9021 * FALSE. Therefore, we will adjust the return value
8999 9022 * if mptsas_do_scsi_reset returns FAILED.
9000 9023 */
9001 9024 if (rval == FAILED)
9002 9025 rval = FALSE;
9003 9026 return (rval);
9004 9027 }
9005 9028
9006 9029 static int
9007 9030 mptsas_do_scsi_reset(mptsas_t *mpt, uint16_t devhdl)
9008 9031 {
9009 9032 int rval = FALSE;
9010 9033 uint8_t config, disk;
9011 9034
9012 9035 ASSERT(mutex_owned(&mpt->m_mutex));
9013 9036
9014 9037 if (mptsas_debug_resets) {
9015 9038 mptsas_log(mpt, CE_WARN, "mptsas_do_scsi_reset: target=%d",
9016 9039 devhdl);
9017 9040 }
9018 9041
9019 9042 /*
9020 9043 * Issue a Target Reset message to the target specified but not to a
9021 9044 * disk making up a raid volume. Just look through the RAID config
9022 9045 * Phys Disk list of DevHandles. If the target's DevHandle is in this
9023 9046 * list, then don't reset this target.
9024 9047 */
9025 9048 for (config = 0; config < mpt->m_num_raid_configs; config++) {
9026 9049 for (disk = 0; disk < MPTSAS_MAX_DISKS_IN_CONFIG; disk++) {
9027 9050 if (devhdl == mpt->m_raidconfig[config].
9028 9051 m_physdisk_devhdl[disk]) {
9029 9052 return (TRUE);
9030 9053 }
9031 9054 }
9032 9055 }
9033 9056
9034 9057 rval = mptsas_ioc_task_management(mpt,
9035 9058 MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET, devhdl, 0, NULL, 0, 0);
9036 9059
9037 9060 mptsas_doneq_empty(mpt);
9038 9061 return (rval);
9039 9062 }
9040 9063
9041 9064 static int
9042 9065 mptsas_scsi_reset_notify(struct scsi_address *ap, int flag,
9043 9066 void (*callback)(caddr_t), caddr_t arg)
9044 9067 {
9045 9068 mptsas_t *mpt = ADDR2MPT(ap);
9046 9069
9047 9070 NDBG22(("mptsas_scsi_reset_notify: tgt=%d", ap->a_target));
9048 9071
9049 9072 return (scsi_hba_reset_notify_setup(ap, flag, callback, arg,
9050 9073 &mpt->m_mutex, &mpt->m_reset_notify_listf));
9051 9074 }
9052 9075
9053 9076 static int
9054 9077 mptsas_get_name(struct scsi_device *sd, char *name, int len)
9055 9078 {
9056 9079 dev_info_t *lun_dip = NULL;
9057 9080
9058 9081 ASSERT(sd != NULL);
9059 9082 ASSERT(name != NULL);
9060 9083 lun_dip = sd->sd_dev;
9061 9084 ASSERT(lun_dip != NULL);
9062 9085
9063 9086 if (mptsas_name_child(lun_dip, name, len) == DDI_SUCCESS) {
9064 9087 return (1);
9065 9088 } else {
9066 9089 return (0);
9067 9090 }
9068 9091 }
9069 9092
9070 9093 static int
9071 9094 mptsas_get_bus_addr(struct scsi_device *sd, char *name, int len)
9072 9095 {
9073 9096 return (mptsas_get_name(sd, name, len));
9074 9097 }
9075 9098
9076 9099 void
9077 9100 mptsas_set_throttle(mptsas_t *mpt, mptsas_target_t *ptgt, int what)
9078 9101 {
9079 9102
9080 9103 NDBG25(("mptsas_set_throttle: throttle=%x", what));
9081 9104
9082 9105 /*
9083 9106 * if the bus is draining/quiesced, no changes to the throttles
9084 9107 * are allowed. Not allowing change of throttles during draining
9085 9108 * limits error recovery but will reduce draining time
9086 9109 *
9087 9110 * all throttles should have been set to HOLD_THROTTLE
9088 9111 */
9089 9112 if (mpt->m_softstate & (MPTSAS_SS_QUIESCED | MPTSAS_SS_DRAINING)) {
9090 9113 return;
9091 9114 }
9092 9115
9093 9116 if (what == HOLD_THROTTLE) {
9094 9117 ptgt->m_t_throttle = HOLD_THROTTLE;
9095 9118 } else if (ptgt->m_reset_delay == 0) {
9096 9119 ptgt->m_t_throttle = what;
9097 9120 }
9098 9121 }
9099 9122
9100 9123 /*
9101 9124 * Clean up from a device reset.
9102 9125 * For the case of target reset, this function clears the waitq of all
9103 9126 * commands for a particular target. For the case of abort task set, this
9104 9127 * function clears the waitq of all commonds for a particular target/lun.
9105 9128 */
9106 9129 static void
9107 9130 mptsas_flush_target(mptsas_t *mpt, ushort_t target, int lun, uint8_t tasktype)
9108 9131 {
9109 9132 mptsas_slots_t *slots = mpt->m_active;
9110 9133 mptsas_cmd_t *cmd, *next_cmd;
9111 9134 int slot;
9112 9135 uchar_t reason;
9113 9136 uint_t stat;
9114 9137 hrtime_t timestamp;
9115 9138
9116 9139 NDBG25(("mptsas_flush_target: target=%d lun=%d", target, lun));
9117 9140
9118 9141 timestamp = gethrtime();
9119 9142
9120 9143 /*
9121 9144 * Make sure the I/O Controller has flushed all cmds
9122 9145 * that are associated with this target for a target reset
9123 9146 * and target/lun for abort task set.
9124 9147 * Account for TM requests, which use the last SMID.
9125 9148 */
9126 9149 for (slot = 0; slot <= mpt->m_active->m_n_normal; slot++) {
9127 9150 if ((cmd = slots->m_slot[slot]) == NULL)
9128 9151 continue;
9129 9152 reason = CMD_RESET;
9130 9153 stat = STAT_DEV_RESET;
9131 9154 switch (tasktype) {
9132 9155 case MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET:
9133 9156 if (Tgt(cmd) == target) {
9134 9157 if (cmd->cmd_active_expiration <= timestamp) {
9135 9158 /*
9136 9159 * When timeout requested, propagate
9137 9160 * proper reason and statistics to
9138 9161 * target drivers.
9139 9162 */
9140 9163 reason = CMD_TIMEOUT;
9141 9164 stat |= STAT_TIMEOUT;
9142 9165 }
9143 9166 NDBG25(("mptsas_flush_target discovered non-"
9144 9167 "NULL cmd in slot %d, tasktype 0x%x", slot,
9145 9168 tasktype));
9146 9169 mptsas_dump_cmd(mpt, cmd);
9147 9170 mptsas_remove_cmd(mpt, cmd);
9148 9171 mptsas_set_pkt_reason(mpt, cmd, reason, stat);
9149 9172 mptsas_doneq_add(mpt, cmd);
9150 9173 }
9151 9174 break;
9152 9175 case MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET:
9153 9176 reason = CMD_ABORTED;
9154 9177 stat = STAT_ABORTED;
9155 9178 /*FALLTHROUGH*/
9156 9179 case MPI2_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET:
9157 9180 if ((Tgt(cmd) == target) && (Lun(cmd) == lun)) {
9158 9181
9159 9182 NDBG25(("mptsas_flush_target discovered non-"
9160 9183 "NULL cmd in slot %d, tasktype 0x%x", slot,
9161 9184 tasktype));
9162 9185 mptsas_dump_cmd(mpt, cmd);
9163 9186 mptsas_remove_cmd(mpt, cmd);
9164 9187 mptsas_set_pkt_reason(mpt, cmd, reason,
9165 9188 stat);
9166 9189 mptsas_doneq_add(mpt, cmd);
9167 9190 }
9168 9191 break;
9169 9192 default:
9170 9193 break;
9171 9194 }
9172 9195 }
9173 9196
9174 9197 /*
9175 9198 * Flush the waitq and tx_waitq of this target's cmds
9176 9199 */
9177 9200 cmd = mpt->m_waitq;
9178 9201
9179 9202 reason = CMD_RESET;
9180 9203 stat = STAT_DEV_RESET;
9181 9204
9182 9205 switch (tasktype) {
9183 9206 case MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET:
9184 9207 while (cmd != NULL) {
9185 9208 next_cmd = cmd->cmd_linkp;
9186 9209 if (Tgt(cmd) == target) {
9187 9210 mptsas_waitq_delete(mpt, cmd);
9188 9211 mptsas_set_pkt_reason(mpt, cmd,
9189 9212 reason, stat);
9190 9213 mptsas_doneq_add(mpt, cmd);
9191 9214 }
9192 9215 cmd = next_cmd;
9193 9216 }
9194 9217 mutex_enter(&mpt->m_tx_waitq_mutex);
9195 9218 cmd = mpt->m_tx_waitq;
9196 9219 while (cmd != NULL) {
9197 9220 next_cmd = cmd->cmd_linkp;
9198 9221 if (Tgt(cmd) == target) {
9199 9222 mptsas_tx_waitq_delete(mpt, cmd);
9200 9223 mutex_exit(&mpt->m_tx_waitq_mutex);
9201 9224 mptsas_set_pkt_reason(mpt, cmd,
9202 9225 reason, stat);
9203 9226 mptsas_doneq_add(mpt, cmd);
9204 9227 mutex_enter(&mpt->m_tx_waitq_mutex);
9205 9228 }
9206 9229 cmd = next_cmd;
9207 9230 }
9208 9231 mutex_exit(&mpt->m_tx_waitq_mutex);
9209 9232 break;
9210 9233 case MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET:
9211 9234 reason = CMD_ABORTED;
9212 9235 stat = STAT_ABORTED;
9213 9236 /*FALLTHROUGH*/
9214 9237 case MPI2_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET:
9215 9238 while (cmd != NULL) {
9216 9239 next_cmd = cmd->cmd_linkp;
9217 9240 if ((Tgt(cmd) == target) && (Lun(cmd) == lun)) {
9218 9241 mptsas_waitq_delete(mpt, cmd);
9219 9242 mptsas_set_pkt_reason(mpt, cmd,
9220 9243 reason, stat);
9221 9244 mptsas_doneq_add(mpt, cmd);
9222 9245 }
9223 9246 cmd = next_cmd;
9224 9247 }
9225 9248 mutex_enter(&mpt->m_tx_waitq_mutex);
9226 9249 cmd = mpt->m_tx_waitq;
9227 9250 while (cmd != NULL) {
9228 9251 next_cmd = cmd->cmd_linkp;
9229 9252 if ((Tgt(cmd) == target) && (Lun(cmd) == lun)) {
9230 9253 mptsas_tx_waitq_delete(mpt, cmd);
9231 9254 mutex_exit(&mpt->m_tx_waitq_mutex);
9232 9255 mptsas_set_pkt_reason(mpt, cmd,
9233 9256 reason, stat);
9234 9257 mptsas_doneq_add(mpt, cmd);
9235 9258 mutex_enter(&mpt->m_tx_waitq_mutex);
9236 9259 }
9237 9260 cmd = next_cmd;
9238 9261 }
9239 9262 mutex_exit(&mpt->m_tx_waitq_mutex);
9240 9263 break;
9241 9264 default:
9242 9265 mptsas_log(mpt, CE_WARN, "Unknown task management type %d.",
9243 9266 tasktype);
9244 9267 break;
9245 9268 }
9246 9269 }
9247 9270
9248 9271 /*
9249 9272 * Clean up hba state, abort all outstanding command and commands in waitq
9250 9273 * reset timeout of all targets.
9251 9274 */
9252 9275 static void
9253 9276 mptsas_flush_hba(mptsas_t *mpt)
9254 9277 {
9255 9278 mptsas_slots_t *slots = mpt->m_active;
9256 9279 mptsas_cmd_t *cmd;
9257 9280 int slot;
9258 9281
9259 9282 NDBG25(("mptsas_flush_hba"));
9260 9283
9261 9284 /*
9262 9285 * The I/O Controller should have already sent back
9263 9286 * all commands via the scsi I/O reply frame. Make
9264 9287 * sure all commands have been flushed.
9265 9288 * Account for TM request, which use the last SMID.
9266 9289 */
9267 9290 for (slot = 0; slot <= mpt->m_active->m_n_normal; slot++) {
9268 9291 if ((cmd = slots->m_slot[slot]) == NULL)
9269 9292 continue;
9270 9293
9271 9294 if (cmd->cmd_flags & CFLAG_CMDIOC) {
9272 9295 /*
9273 9296 * Need to make sure to tell everyone that might be
9274 9297 * waiting on this command that it's going to fail. If
9275 9298 * we get here, this command will never timeout because
9276 9299 * the active command table is going to be re-allocated,
9277 9300 * so there will be nothing to check against a time out.
9278 9301 * Instead, mark the command as failed due to reset.
9279 9302 */
9280 9303 mptsas_set_pkt_reason(mpt, cmd, CMD_RESET,
9281 9304 STAT_BUS_RESET);
9282 9305 if ((cmd->cmd_flags &
9283 9306 (CFLAG_PASSTHRU | CFLAG_CONFIG | CFLAG_FW_DIAG))) {
9284 9307 cmd->cmd_flags |= CFLAG_FINISHED;
9285 9308 cv_broadcast(&mpt->m_passthru_cv);
9286 9309 cv_broadcast(&mpt->m_config_cv);
9287 9310 cv_broadcast(&mpt->m_fw_diag_cv);
9288 9311 }
9289 9312 continue;
9290 9313 }
9291 9314
9292 9315 NDBG25(("mptsas_flush_hba discovered non-NULL cmd in slot %d",
9293 9316 slot));
9294 9317 mptsas_dump_cmd(mpt, cmd);
9295 9318
9296 9319 mptsas_remove_cmd(mpt, cmd);
9297 9320 mptsas_set_pkt_reason(mpt, cmd, CMD_RESET, STAT_BUS_RESET);
9298 9321 mptsas_doneq_add(mpt, cmd);
9299 9322 }
9300 9323
9301 9324 /*
9302 9325 * Flush the waitq.
9303 9326 */
9304 9327 while ((cmd = mptsas_waitq_rm(mpt)) != NULL) {
9305 9328 mptsas_set_pkt_reason(mpt, cmd, CMD_RESET, STAT_BUS_RESET);
9306 9329 if ((cmd->cmd_flags & CFLAG_PASSTHRU) ||
9307 9330 (cmd->cmd_flags & CFLAG_CONFIG) ||
9308 9331 (cmd->cmd_flags & CFLAG_FW_DIAG)) {
9309 9332 cmd->cmd_flags |= CFLAG_FINISHED;
9310 9333 cv_broadcast(&mpt->m_passthru_cv);
9311 9334 cv_broadcast(&mpt->m_config_cv);
9312 9335 cv_broadcast(&mpt->m_fw_diag_cv);
9313 9336 } else {
9314 9337 mptsas_doneq_add(mpt, cmd);
9315 9338 }
9316 9339 }
9317 9340
9318 9341 /*
9319 9342 * Flush the tx_waitq
9320 9343 */
9321 9344 mutex_enter(&mpt->m_tx_waitq_mutex);
9322 9345 while ((cmd = mptsas_tx_waitq_rm(mpt)) != NULL) {
9323 9346 mutex_exit(&mpt->m_tx_waitq_mutex);
9324 9347 mptsas_set_pkt_reason(mpt, cmd, CMD_RESET, STAT_BUS_RESET);
9325 9348 mptsas_doneq_add(mpt, cmd);
9326 9349 mutex_enter(&mpt->m_tx_waitq_mutex);
9327 9350 }
9328 9351 mutex_exit(&mpt->m_tx_waitq_mutex);
9329 9352
9330 9353 /*
9331 9354 * Drain the taskqs prior to reallocating resources. The thread
9332 9355 * passing through here could be launched from either (dr)
9333 9356 * or (event) taskqs so only wait on the 'other' queue since
9334 9357 * waiting on 'this' queue is a deadlock condition.
9335 9358 */
9336 9359 mutex_exit(&mpt->m_mutex);
9337 9360 if (!taskq_member((taskq_t *)mpt->m_event_taskq, curthread))
9338 9361 ddi_taskq_wait(mpt->m_event_taskq);
9339 9362 if (!taskq_member((taskq_t *)mpt->m_dr_taskq, curthread))
9340 9363 ddi_taskq_wait(mpt->m_dr_taskq);
9341 9364
9342 9365 mutex_enter(&mpt->m_mutex);
9343 9366 }
9344 9367
9345 9368 /*
9346 9369 * set pkt_reason and OR in pkt_statistics flag
9347 9370 */
9348 9371 static void
9349 9372 mptsas_set_pkt_reason(mptsas_t *mpt, mptsas_cmd_t *cmd, uchar_t reason,
9350 9373 uint_t stat)
9351 9374 {
9352 9375 #ifndef __lock_lint
9353 9376 _NOTE(ARGUNUSED(mpt))
9354 9377 #endif
9355 9378
9356 9379 NDBG25(("mptsas_set_pkt_reason: cmd=0x%p reason=%x stat=%x",
9357 9380 (void *)cmd, reason, stat));
9358 9381
9359 9382 if (cmd) {
9360 9383 if (cmd->cmd_pkt->pkt_reason == CMD_CMPLT) {
9361 9384 cmd->cmd_pkt->pkt_reason = reason;
9362 9385 }
9363 9386 cmd->cmd_pkt->pkt_statistics |= stat;
9364 9387 }
9365 9388 }
9366 9389
9367 9390 static void
9368 9391 mptsas_start_watch_reset_delay()
9369 9392 {
9370 9393 NDBG22(("mptsas_start_watch_reset_delay"));
9371 9394
9372 9395 mutex_enter(&mptsas_global_mutex);
9373 9396 if (mptsas_reset_watch == NULL && mptsas_timeouts_enabled) {
9374 9397 mptsas_reset_watch = timeout(mptsas_watch_reset_delay, NULL,
9375 9398 drv_usectohz((clock_t)
9376 9399 MPTSAS_WATCH_RESET_DELAY_TICK * 1000));
9377 9400 ASSERT(mptsas_reset_watch != NULL);
9378 9401 }
9379 9402 mutex_exit(&mptsas_global_mutex);
9380 9403 }
9381 9404
9382 9405 static void
9383 9406 mptsas_setup_bus_reset_delay(mptsas_t *mpt)
9384 9407 {
9385 9408 mptsas_target_t *ptgt = NULL;
9386 9409
9387 9410 ASSERT(MUTEX_HELD(&mpt->m_mutex));
9388 9411
9389 9412 NDBG22(("mptsas_setup_bus_reset_delay"));
9390 9413 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL;
9391 9414 ptgt = refhash_next(mpt->m_targets, ptgt)) {
9392 9415 mptsas_set_throttle(mpt, ptgt, HOLD_THROTTLE);
9393 9416 ptgt->m_reset_delay = mpt->m_scsi_reset_delay;
9394 9417 }
9395 9418
9396 9419 mptsas_start_watch_reset_delay();
9397 9420 }
9398 9421
9399 9422 /*
9400 9423 * mptsas_watch_reset_delay(_subr) is invoked by timeout() and checks every
9401 9424 * mpt instance for active reset delays
9402 9425 */
9403 9426 static void
9404 9427 mptsas_watch_reset_delay(void *arg)
9405 9428 {
9406 9429 #ifndef __lock_lint
9407 9430 _NOTE(ARGUNUSED(arg))
9408 9431 #endif
9409 9432
9410 9433 mptsas_t *mpt;
9411 9434 int not_done = 0;
9412 9435
9413 9436 NDBG22(("mptsas_watch_reset_delay"));
9414 9437
9415 9438 mutex_enter(&mptsas_global_mutex);
9416 9439 mptsas_reset_watch = 0;
9417 9440 mutex_exit(&mptsas_global_mutex);
9418 9441 rw_enter(&mptsas_global_rwlock, RW_READER);
9419 9442 for (mpt = mptsas_head; mpt != NULL; mpt = mpt->m_next) {
9420 9443 if (mpt->m_tran == 0) {
9421 9444 continue;
9422 9445 }
9423 9446 mutex_enter(&mpt->m_mutex);
9424 9447 not_done += mptsas_watch_reset_delay_subr(mpt);
9425 9448 mutex_exit(&mpt->m_mutex);
9426 9449 }
9427 9450 rw_exit(&mptsas_global_rwlock);
9428 9451
9429 9452 if (not_done) {
9430 9453 mptsas_start_watch_reset_delay();
9431 9454 }
9432 9455 }
9433 9456
9434 9457 static int
9435 9458 mptsas_watch_reset_delay_subr(mptsas_t *mpt)
9436 9459 {
9437 9460 int done = 0;
9438 9461 int restart = 0;
9439 9462 mptsas_target_t *ptgt = NULL;
9440 9463
9441 9464 NDBG22(("mptsas_watch_reset_delay_subr: mpt=0x%p", (void *)mpt));
9442 9465
9443 9466 ASSERT(mutex_owned(&mpt->m_mutex));
9444 9467
9445 9468 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL;
9446 9469 ptgt = refhash_next(mpt->m_targets, ptgt)) {
9447 9470 if (ptgt->m_reset_delay != 0) {
9448 9471 ptgt->m_reset_delay -=
9449 9472 MPTSAS_WATCH_RESET_DELAY_TICK;
9450 9473 if (ptgt->m_reset_delay <= 0) {
9451 9474 ptgt->m_reset_delay = 0;
9452 9475 mptsas_set_throttle(mpt, ptgt,
9453 9476 MAX_THROTTLE);
9454 9477 restart++;
9455 9478 } else {
9456 9479 done = -1;
9457 9480 }
9458 9481 }
9459 9482 }
9460 9483
9461 9484 if (restart > 0) {
9462 9485 mptsas_restart_hba(mpt);
9463 9486 }
9464 9487 return (done);
9465 9488 }
9466 9489
9467 9490 #ifdef MPTSAS_TEST
9468 9491 static void
9469 9492 mptsas_test_reset(mptsas_t *mpt, int target)
9470 9493 {
9471 9494 mptsas_target_t *ptgt = NULL;
9472 9495
9473 9496 if (mptsas_rtest == target) {
9474 9497 if (mptsas_do_scsi_reset(mpt, target) == TRUE) {
9475 9498 mptsas_rtest = -1;
9476 9499 }
9477 9500 if (mptsas_rtest == -1) {
9478 9501 NDBG22(("mptsas_test_reset success"));
9479 9502 }
9480 9503 }
9481 9504 }
9482 9505 #endif
9483 9506
9484 9507 /*
9485 9508 * abort handling:
9486 9509 *
9487 9510 * Notes:
9488 9511 * - if pkt is not NULL, abort just that command
9489 9512 * - if pkt is NULL, abort all outstanding commands for target
9490 9513 */
9491 9514 static int
9492 9515 mptsas_scsi_abort(struct scsi_address *ap, struct scsi_pkt *pkt)
9493 9516 {
9494 9517 mptsas_t *mpt = ADDR2MPT(ap);
9495 9518 int rval;
9496 9519 mptsas_tgt_private_t *tgt_private;
9497 9520 int target, lun;
9498 9521
9499 9522 tgt_private = (mptsas_tgt_private_t *)ap->a_hba_tran->
9500 9523 tran_tgt_private;
9501 9524 ASSERT(tgt_private != NULL);
9502 9525 target = tgt_private->t_private->m_devhdl;
9503 9526 lun = tgt_private->t_lun;
9504 9527
9505 9528 NDBG23(("mptsas_scsi_abort: target=%d.%d", target, lun));
9506 9529
9507 9530 mutex_enter(&mpt->m_mutex);
9508 9531 rval = mptsas_do_scsi_abort(mpt, target, lun, pkt);
9509 9532 mutex_exit(&mpt->m_mutex);
9510 9533 return (rval);
9511 9534 }
9512 9535
9513 9536 static int
9514 9537 mptsas_do_scsi_abort(mptsas_t *mpt, int target, int lun, struct scsi_pkt *pkt)
9515 9538 {
9516 9539 mptsas_cmd_t *sp = NULL;
9517 9540 mptsas_slots_t *slots = mpt->m_active;
9518 9541 int rval = FALSE;
9519 9542
9520 9543 ASSERT(mutex_owned(&mpt->m_mutex));
9521 9544
9522 9545 /*
9523 9546 * Abort the command pkt on the target/lun in ap. If pkt is
9524 9547 * NULL, abort all outstanding commands on that target/lun.
9525 9548 * If you can abort them, return 1, else return 0.
9526 9549 * Each packet that's aborted should be sent back to the target
9527 9550 * driver through the callback routine, with pkt_reason set to
9528 9551 * CMD_ABORTED.
9529 9552 *
9530 9553 * abort cmd pkt on HBA hardware; clean out of outstanding
9531 9554 * command lists, etc.
9532 9555 */
9533 9556 if (pkt != NULL) {
9534 9557 /* abort the specified packet */
9535 9558 sp = PKT2CMD(pkt);
9536 9559
9537 9560 if (sp->cmd_queued) {
9538 9561 NDBG23(("mptsas_do_scsi_abort: queued sp=0x%p aborted",
9539 9562 (void *)sp));
9540 9563 mptsas_waitq_delete(mpt, sp);
9541 9564 mptsas_set_pkt_reason(mpt, sp, CMD_ABORTED,
9542 9565 STAT_ABORTED);
9543 9566 mptsas_doneq_add(mpt, sp);
9544 9567 rval = TRUE;
9545 9568 goto done;
9546 9569 }
9547 9570
9548 9571 /*
9549 9572 * Have mpt firmware abort this command
9550 9573 */
9551 9574
9552 9575 if (slots->m_slot[sp->cmd_slot] != NULL) {
9553 9576 rval = mptsas_ioc_task_management(mpt,
9554 9577 MPI2_SCSITASKMGMT_TASKTYPE_ABORT_TASK, target,
9555 9578 lun, NULL, 0, 0);
9556 9579
9557 9580 /*
9558 9581 * The transport layer expects only TRUE and FALSE.
9559 9582 * Therefore, if mptsas_ioc_task_management returns
9560 9583 * FAILED we will return FALSE.
9561 9584 */
9562 9585 if (rval == FAILED)
9563 9586 rval = FALSE;
9564 9587 goto done;
9565 9588 }
9566 9589 }
9567 9590
9568 9591 /*
9569 9592 * If pkt is NULL then abort task set
9570 9593 */
9571 9594 rval = mptsas_ioc_task_management(mpt,
9572 9595 MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET, target, lun, NULL, 0, 0);
9573 9596
9574 9597 /*
9575 9598 * The transport layer expects only TRUE and FALSE.
9576 9599 * Therefore, if mptsas_ioc_task_management returns
9577 9600 * FAILED we will return FALSE.
9578 9601 */
9579 9602 if (rval == FAILED)
9580 9603 rval = FALSE;
9581 9604
9582 9605 #ifdef MPTSAS_TEST
9583 9606 if (rval && mptsas_test_stop) {
9584 9607 debug_enter("mptsas_do_scsi_abort");
9585 9608 }
9586 9609 #endif
9587 9610
9588 9611 done:
9589 9612 mptsas_doneq_empty(mpt);
9590 9613 return (rval);
9591 9614 }
9592 9615
9593 9616 /*
9594 9617 * capability handling:
9595 9618 * (*tran_getcap). Get the capability named, and return its value.
9596 9619 */
9597 9620 static int
9598 9621 mptsas_scsi_getcap(struct scsi_address *ap, char *cap, int tgtonly)
9599 9622 {
9600 9623 mptsas_t *mpt = ADDR2MPT(ap);
9601 9624 int ckey;
9602 9625 int rval = FALSE;
9603 9626
9604 9627 NDBG24(("mptsas_scsi_getcap: target=%d, cap=%s tgtonly=%x",
9605 9628 ap->a_target, cap, tgtonly));
9606 9629
9607 9630 mutex_enter(&mpt->m_mutex);
9608 9631
9609 9632 if ((mptsas_scsi_capchk(cap, tgtonly, &ckey)) != TRUE) {
9610 9633 mutex_exit(&mpt->m_mutex);
9611 9634 return (UNDEFINED);
9612 9635 }
9613 9636
9614 9637 switch (ckey) {
9615 9638 case SCSI_CAP_DMA_MAX:
9616 9639 rval = (int)mpt->m_msg_dma_attr.dma_attr_maxxfer;
9617 9640 break;
9618 9641 case SCSI_CAP_ARQ:
9619 9642 rval = TRUE;
9620 9643 break;
9621 9644 case SCSI_CAP_MSG_OUT:
9622 9645 case SCSI_CAP_PARITY:
9623 9646 case SCSI_CAP_UNTAGGED_QING:
9624 9647 rval = TRUE;
9625 9648 break;
9626 9649 case SCSI_CAP_TAGGED_QING:
9627 9650 rval = TRUE;
9628 9651 break;
9629 9652 case SCSI_CAP_RESET_NOTIFICATION:
9630 9653 rval = TRUE;
9631 9654 break;
9632 9655 case SCSI_CAP_LINKED_CMDS:
9633 9656 rval = FALSE;
9634 9657 break;
9635 9658 case SCSI_CAP_QFULL_RETRIES:
9636 9659 rval = ((mptsas_tgt_private_t *)(ap->a_hba_tran->
9637 9660 tran_tgt_private))->t_private->m_qfull_retries;
9638 9661 break;
9639 9662 case SCSI_CAP_QFULL_RETRY_INTERVAL:
9640 9663 rval = drv_hztousec(((mptsas_tgt_private_t *)
9641 9664 (ap->a_hba_tran->tran_tgt_private))->
9642 9665 t_private->m_qfull_retry_interval) / 1000;
9643 9666 break;
9644 9667 case SCSI_CAP_CDB_LEN:
9645 9668 rval = CDB_GROUP4;
9646 9669 break;
9647 9670 case SCSI_CAP_INTERCONNECT_TYPE:
9648 9671 rval = INTERCONNECT_SAS;
9649 9672 break;
9650 9673 case SCSI_CAP_TRAN_LAYER_RETRIES:
9651 9674 if (mpt->m_ioc_capabilities &
9652 9675 MPI2_IOCFACTS_CAPABILITY_TLR)
9653 9676 rval = TRUE;
9654 9677 else
9655 9678 rval = FALSE;
9656 9679 break;
9657 9680 default:
9658 9681 rval = UNDEFINED;
9659 9682 break;
9660 9683 }
9661 9684
9662 9685 NDBG24(("mptsas_scsi_getcap: %s, rval=%x", cap, rval));
9663 9686
9664 9687 mutex_exit(&mpt->m_mutex);
9665 9688 return (rval);
9666 9689 }
9667 9690
9668 9691 /*
9669 9692 * (*tran_setcap). Set the capability named to the value given.
9670 9693 */
9671 9694 static int
9672 9695 mptsas_scsi_setcap(struct scsi_address *ap, char *cap, int value, int tgtonly)
9673 9696 {
9674 9697 mptsas_t *mpt = ADDR2MPT(ap);
9675 9698 int ckey;
9676 9699 int rval = FALSE;
9677 9700
9678 9701 NDBG24(("mptsas_scsi_setcap: target=%d, cap=%s value=%x tgtonly=%x",
9679 9702 ap->a_target, cap, value, tgtonly));
9680 9703
9681 9704 if (!tgtonly) {
9682 9705 return (rval);
9683 9706 }
9684 9707
9685 9708 mutex_enter(&mpt->m_mutex);
9686 9709
9687 9710 if ((mptsas_scsi_capchk(cap, tgtonly, &ckey)) != TRUE) {
9688 9711 mutex_exit(&mpt->m_mutex);
9689 9712 return (UNDEFINED);
9690 9713 }
9691 9714
9692 9715 switch (ckey) {
9693 9716 case SCSI_CAP_DMA_MAX:
9694 9717 case SCSI_CAP_MSG_OUT:
9695 9718 case SCSI_CAP_PARITY:
9696 9719 case SCSI_CAP_INITIATOR_ID:
9697 9720 case SCSI_CAP_LINKED_CMDS:
9698 9721 case SCSI_CAP_UNTAGGED_QING:
9699 9722 case SCSI_CAP_RESET_NOTIFICATION:
9700 9723 /*
9701 9724 * None of these are settable via
9702 9725 * the capability interface.
9703 9726 */
9704 9727 break;
9705 9728 case SCSI_CAP_ARQ:
9706 9729 /*
9707 9730 * We cannot turn off arq so return false if asked to
9708 9731 */
9709 9732 if (value) {
9710 9733 rval = TRUE;
9711 9734 } else {
9712 9735 rval = FALSE;
9713 9736 }
9714 9737 break;
9715 9738 case SCSI_CAP_TAGGED_QING:
9716 9739 mptsas_set_throttle(mpt, ((mptsas_tgt_private_t *)
9717 9740 (ap->a_hba_tran->tran_tgt_private))->t_private,
9718 9741 MAX_THROTTLE);
9719 9742 rval = TRUE;
9720 9743 break;
9721 9744 case SCSI_CAP_QFULL_RETRIES:
9722 9745 ((mptsas_tgt_private_t *)(ap->a_hba_tran->tran_tgt_private))->
9723 9746 t_private->m_qfull_retries = (uchar_t)value;
9724 9747 rval = TRUE;
9725 9748 break;
9726 9749 case SCSI_CAP_QFULL_RETRY_INTERVAL:
9727 9750 ((mptsas_tgt_private_t *)(ap->a_hba_tran->tran_tgt_private))->
9728 9751 t_private->m_qfull_retry_interval =
9729 9752 drv_usectohz(value * 1000);
9730 9753 rval = TRUE;
9731 9754 break;
9732 9755 default:
9733 9756 rval = UNDEFINED;
9734 9757 break;
9735 9758 }
9736 9759 mutex_exit(&mpt->m_mutex);
9737 9760 return (rval);
9738 9761 }
9739 9762
9740 9763 /*
9741 9764 * Utility routine for mptsas_ifsetcap/ifgetcap
9742 9765 */
9743 9766 /*ARGSUSED*/
9744 9767 static int
9745 9768 mptsas_scsi_capchk(char *cap, int tgtonly, int *cidxp)
9746 9769 {
9747 9770 NDBG24(("mptsas_scsi_capchk: cap=%s", cap));
9748 9771
9749 9772 if (!cap)
9750 9773 return (FALSE);
9751 9774
9752 9775 *cidxp = scsi_hba_lookup_capstr(cap);
9753 9776 return (TRUE);
9754 9777 }
9755 9778
9756 9779 static int
9757 9780 mptsas_alloc_active_slots(mptsas_t *mpt, int flag)
9758 9781 {
9759 9782 mptsas_slots_t *old_active = mpt->m_active;
9760 9783 mptsas_slots_t *new_active;
9761 9784 size_t size;
9762 9785
9763 9786 /*
9764 9787 * if there are active commands, then we cannot
9765 9788 * change size of active slots array.
9766 9789 */
9767 9790 ASSERT(mpt->m_ncmds == 0);
9768 9791
9769 9792 size = MPTSAS_SLOTS_SIZE(mpt);
9770 9793 new_active = kmem_zalloc(size, flag);
9771 9794 if (new_active == NULL) {
9772 9795 NDBG1(("new active alloc failed"));
9773 9796 return (-1);
9774 9797 }
9775 9798 /*
9776 9799 * Since SMID 0 is reserved and the TM slot is reserved, the
9777 9800 * number of slots that can be used at any one time is
9778 9801 * m_max_requests - 2.
9779 9802 */
9780 9803 new_active->m_n_normal = (mpt->m_max_requests - 2);
9781 9804 new_active->m_size = size;
9782 9805 new_active->m_rotor = 1;
9783 9806 if (old_active)
9784 9807 mptsas_free_active_slots(mpt);
9785 9808 mpt->m_active = new_active;
9786 9809
9787 9810 return (0);
9788 9811 }
9789 9812
9790 9813 static void
9791 9814 mptsas_free_active_slots(mptsas_t *mpt)
9792 9815 {
9793 9816 mptsas_slots_t *active = mpt->m_active;
9794 9817 size_t size;
9795 9818
9796 9819 if (active == NULL)
9797 9820 return;
9798 9821 size = active->m_size;
9799 9822 kmem_free(active, size);
9800 9823 mpt->m_active = NULL;
9801 9824 }
9802 9825
9803 9826 /*
9804 9827 * Error logging, printing, and debug print routines.
9805 9828 */
9806 9829 static char *mptsas_label = "mpt_sas";
9807 9830
9808 9831 /*PRINTFLIKE3*/
9809 9832 void
9810 9833 mptsas_log(mptsas_t *mpt, int level, char *fmt, ...)
9811 9834 {
9812 9835 dev_info_t *dev;
9813 9836 va_list ap;
9814 9837
9815 9838 if (mpt) {
9816 9839 dev = mpt->m_dip;
9817 9840 } else {
9818 9841 dev = 0;
9819 9842 }
9820 9843
9821 9844 mutex_enter(&mptsas_log_mutex);
9822 9845
9823 9846 va_start(ap, fmt);
9824 9847 (void) vsprintf(mptsas_log_buf, fmt, ap);
9825 9848 va_end(ap);
9826 9849
9827 9850 if (level == CE_CONT) {
9828 9851 scsi_log(dev, mptsas_label, level, "%s\n", mptsas_log_buf);
9829 9852 } else {
9830 9853 scsi_log(dev, mptsas_label, level, "%s", mptsas_log_buf);
9831 9854 }
9832 9855
9833 9856 mutex_exit(&mptsas_log_mutex);
9834 9857 }
9835 9858
9836 9859 #ifdef MPTSAS_DEBUG
9837 9860 /*
9838 9861 * Use a circular buffer to log messages to private memory.
9839 9862 * Increment idx atomically to minimize risk to miss lines.
9840 9863 * It's fast and does not hold up the proceedings too much.
9841 9864 */
9842 9865 static const size_t mptsas_dbglog_linecnt = MPTSAS_DBGLOG_LINECNT;
9843 9866 static const size_t mptsas_dbglog_linelen = MPTSAS_DBGLOG_LINELEN;
9844 9867 static char mptsas_dbglog_bufs[MPTSAS_DBGLOG_LINECNT][MPTSAS_DBGLOG_LINELEN];
9845 9868 static uint32_t mptsas_dbglog_idx = 0;
9846 9869
9847 9870 /*PRINTFLIKE1*/
9848 9871 void
9849 9872 mptsas_debug_log(char *fmt, ...)
9850 9873 {
9851 9874 va_list ap;
9852 9875 uint32_t idx;
9853 9876
9854 9877 idx = atomic_inc_32_nv(&mptsas_dbglog_idx) &
9855 9878 (mptsas_dbglog_linecnt - 1);
9856 9879
9857 9880 va_start(ap, fmt);
9858 9881 (void) vsnprintf(mptsas_dbglog_bufs[idx],
9859 9882 mptsas_dbglog_linelen, fmt, ap);
9860 9883 va_end(ap);
9861 9884 }
9862 9885
9863 9886 /*PRINTFLIKE1*/
9864 9887 void
9865 9888 mptsas_printf(char *fmt, ...)
9866 9889 {
9867 9890 dev_info_t *dev = 0;
9868 9891 va_list ap;
9869 9892
9870 9893 mutex_enter(&mptsas_log_mutex);
9871 9894
9872 9895 va_start(ap, fmt);
9873 9896 (void) vsprintf(mptsas_log_buf, fmt, ap);
9874 9897 va_end(ap);
9875 9898
9876 9899 #ifdef PROM_PRINTF
9877 9900 prom_printf("%s:\t%s\n", mptsas_label, mptsas_log_buf);
9878 9901 #else
9879 9902 scsi_log(dev, mptsas_label, CE_CONT, "!%s\n", mptsas_log_buf);
9880 9903 #endif
9881 9904 mutex_exit(&mptsas_log_mutex);
9882 9905 }
9883 9906 #endif
9884 9907
9885 9908 /*
9886 9909 * timeout handling
9887 9910 */
9888 9911 static void
9889 9912 mptsas_watch(void *arg)
9890 9913 {
9891 9914 #ifndef __lock_lint
9892 9915 _NOTE(ARGUNUSED(arg))
9893 9916 #endif
9894 9917
9895 9918 mptsas_t *mpt;
9896 9919 uint32_t doorbell;
9897 9920
9898 9921 NDBG30(("mptsas_watch"));
9899 9922
9900 9923 rw_enter(&mptsas_global_rwlock, RW_READER);
9901 9924 for (mpt = mptsas_head; mpt != (mptsas_t *)NULL; mpt = mpt->m_next) {
9902 9925
9903 9926 mutex_enter(&mpt->m_mutex);
9904 9927
9905 9928 /* Skip device if not powered on */
9906 9929 if (mpt->m_options & MPTSAS_OPT_PM) {
9907 9930 if (mpt->m_power_level == PM_LEVEL_D0) {
9908 9931 (void) pm_busy_component(mpt->m_dip, 0);
9909 9932 mpt->m_busy = 1;
9910 9933 } else {
9911 9934 mutex_exit(&mpt->m_mutex);
9912 9935 continue;
9913 9936 }
9914 9937 }
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9915 9938
9916 9939 /*
9917 9940 * Check if controller is in a FAULT state. If so, reset it.
9918 9941 */
9919 9942 doorbell = ddi_get32(mpt->m_datap, &mpt->m_reg->Doorbell);
9920 9943 if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
9921 9944 doorbell &= MPI2_DOORBELL_DATA_MASK;
9922 9945 mptsas_log(mpt, CE_WARN, "MPT Firmware Fault, "
9923 9946 "code: %04x", doorbell);
9924 9947 mpt->m_softstate &= ~MPTSAS_SS_MSG_UNIT_RESET;
9925 - if ((mptsas_restart_ioc(mpt)) == DDI_FAILURE) {
9948 + if ((mptsas_reset_handler(mpt)) == DDI_FAILURE) {
9926 9949 mptsas_log(mpt, CE_WARN, "Reset failed"
9927 9950 "after fault was detected");
9928 9951 }
9929 9952 }
9930 9953
9931 9954 /*
9932 9955 * For now, always call mptsas_watchsubr.
9933 9956 */
9934 9957 mptsas_watchsubr(mpt);
9935 9958
9936 9959 if (mpt->m_options & MPTSAS_OPT_PM) {
9937 9960 mpt->m_busy = 0;
9938 9961 (void) pm_idle_component(mpt->m_dip, 0);
9939 9962 }
9940 9963
9941 9964 mutex_exit(&mpt->m_mutex);
9942 9965 }
9943 9966 rw_exit(&mptsas_global_rwlock);
9944 9967
9945 9968 mutex_enter(&mptsas_global_mutex);
9946 9969 if (mptsas_timeouts_enabled)
9947 9970 mptsas_timeout_id = timeout(mptsas_watch, NULL, mptsas_tick);
9948 9971 mutex_exit(&mptsas_global_mutex);
9949 9972 }
9950 9973
9951 9974 static void
9952 9975 mptsas_watchsubr_tgt(mptsas_t *mpt, mptsas_target_t *ptgt, hrtime_t timestamp)
9953 9976 {
9954 9977 mptsas_cmd_t *cmd;
9955 9978
9956 9979 /*
9957 9980 * If we were draining due to a qfull condition,
9958 9981 * go back to full throttle.
9959 9982 */
9960 9983 if ((ptgt->m_t_throttle < MAX_THROTTLE) &&
9961 9984 (ptgt->m_t_throttle > HOLD_THROTTLE) &&
9962 9985 (ptgt->m_t_ncmds < ptgt->m_t_throttle)) {
9963 9986 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE);
9964 9987 mptsas_restart_hba(mpt);
9965 9988 }
9966 9989
9967 9990 cmd = TAILQ_LAST(&ptgt->m_active_cmdq, mptsas_active_cmdq);
9968 9991 if (cmd == NULL)
9969 9992 return;
9970 9993
9971 9994 if (cmd->cmd_active_expiration <= timestamp) {
9972 9995 /*
9973 9996 * Earliest command timeout expired. Drain throttle.
9974 9997 */
9975 9998 mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE);
9976 9999
9977 10000 /*
9978 10001 * Check for remaining commands.
9979 10002 */
9980 10003 cmd = TAILQ_FIRST(&ptgt->m_active_cmdq);
9981 10004 if (cmd->cmd_active_expiration > timestamp) {
9982 10005 /*
9983 10006 * Wait for remaining commands to complete or
9984 10007 * time out.
9985 10008 */
9986 10009 NDBG23(("command timed out, pending drain"));
9987 10010 return;
9988 10011 }
9989 10012
9990 10013 /*
9991 10014 * All command timeouts expired.
9992 10015 */
9993 10016 mptsas_log(mpt, CE_NOTE, "Timeout of %d seconds "
9994 10017 "expired with %d commands on target %d lun %d.",
9995 10018 cmd->cmd_pkt->pkt_time, ptgt->m_t_ncmds,
9996 10019 ptgt->m_devhdl, Lun(cmd));
9997 10020
9998 10021 mptsas_cmd_timeout(mpt, ptgt);
9999 10022 } else if (cmd->cmd_active_expiration <=
10000 10023 timestamp + (hrtime_t)mptsas_scsi_watchdog_tick * NANOSEC) {
10001 10024 NDBG23(("pending timeout"));
10002 10025 mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE);
10003 10026 }
10004 10027 }
10005 10028
10006 10029 static void
10007 10030 mptsas_watchsubr(mptsas_t *mpt)
10008 10031 {
10009 10032 int i;
10010 10033 mptsas_cmd_t *cmd;
10011 10034 mptsas_target_t *ptgt = NULL;
10012 10035 hrtime_t timestamp = gethrtime();
10013 10036
10014 10037 ASSERT(MUTEX_HELD(&mpt->m_mutex));
10015 10038
10016 10039 NDBG30(("mptsas_watchsubr: mpt=0x%p", (void *)mpt));
10017 10040
10018 10041 #ifdef MPTSAS_TEST
10019 10042 if (mptsas_enable_untagged) {
10020 10043 mptsas_test_untagged++;
10021 10044 }
10022 10045 #endif
10023 10046
10024 10047 /*
10025 10048 * Check for commands stuck in active slot
10026 10049 * Account for TM requests, which use the last SMID.
10027 10050 */
10028 10051 for (i = 0; i <= mpt->m_active->m_n_normal; i++) {
10029 10052 if ((cmd = mpt->m_active->m_slot[i]) != NULL) {
10030 10053 if (cmd->cmd_active_expiration <= timestamp) {
10031 10054 if ((cmd->cmd_flags & CFLAG_CMDIOC) == 0) {
10032 10055 /*
10033 10056 * There seems to be a command stuck
10034 10057 * in the active slot. Drain throttle.
10035 10058 */
10036 10059 mptsas_set_throttle(mpt,
10037 10060 cmd->cmd_tgt_addr,
10038 10061 DRAIN_THROTTLE);
10039 10062 } else if (cmd->cmd_flags &
10040 10063 (CFLAG_PASSTHRU | CFLAG_CONFIG |
10041 10064 CFLAG_FW_DIAG)) {
10042 10065 /*
10043 10066 * passthrough command timeout
10044 10067 */
10045 10068 cmd->cmd_flags |= (CFLAG_FINISHED |
10046 10069 CFLAG_TIMEOUT);
10047 10070 cv_broadcast(&mpt->m_passthru_cv);
10048 10071 cv_broadcast(&mpt->m_config_cv);
10049 10072 cv_broadcast(&mpt->m_fw_diag_cv);
10050 10073 }
10051 10074 }
10052 10075 }
10053 10076 }
10054 10077
10055 10078 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL;
10056 10079 ptgt = refhash_next(mpt->m_targets, ptgt)) {
10057 10080 mptsas_watchsubr_tgt(mpt, ptgt, timestamp);
10058 10081 }
10059 10082
10060 10083 for (ptgt = refhash_first(mpt->m_tmp_targets); ptgt != NULL;
10061 10084 ptgt = refhash_next(mpt->m_tmp_targets, ptgt)) {
10062 10085 mptsas_watchsubr_tgt(mpt, ptgt, timestamp);
10063 10086 }
10064 10087 }
10065 10088
10066 10089 /*
10067 10090 * timeout recovery
10068 10091 */
10069 10092 static void
10070 10093 mptsas_cmd_timeout(mptsas_t *mpt, mptsas_target_t *ptgt)
10071 10094 {
10072 10095 uint16_t devhdl;
10073 10096 uint64_t sas_wwn;
10074 10097 uint8_t phy;
10075 10098 char wwn_str[MPTSAS_WWN_STRLEN];
10076 10099
10077 10100 devhdl = ptgt->m_devhdl;
10078 10101 sas_wwn = ptgt->m_addr.mta_wwn;
10079 10102 phy = ptgt->m_phynum;
10080 10103 if (sas_wwn == 0) {
10081 10104 (void) sprintf(wwn_str, "p%x", phy);
10082 10105 } else {
10083 10106 (void) sprintf(wwn_str, "w%016"PRIx64, sas_wwn);
10084 10107 }
10085 10108
10086 10109 NDBG29(("mptsas_cmd_timeout: target=%d", devhdl));
10087 10110 mptsas_log(mpt, CE_WARN, "Disconnected command timeout for "
10088 10111 "target %d %s, enclosure %u", devhdl, wwn_str,
10089 10112 ptgt->m_enclosure);
10090 10113
10091 10114 /*
10092 10115 * Abort all outstanding commands on the device.
10093 10116 */
10094 10117 NDBG29(("mptsas_cmd_timeout: device reset"));
10095 10118 if (mptsas_do_scsi_reset(mpt, devhdl) != TRUE) {
10096 10119 mptsas_log(mpt, CE_WARN, "Target %d reset for command timeout "
10097 10120 "recovery failed!", devhdl);
10098 10121 }
10099 10122 }
10100 10123
10101 10124 /*
10102 10125 * Device / Hotplug control
10103 10126 */
10104 10127 static int
10105 10128 mptsas_scsi_quiesce(dev_info_t *dip)
10106 10129 {
10107 10130 mptsas_t *mpt;
10108 10131 scsi_hba_tran_t *tran;
10109 10132
10110 10133 tran = ddi_get_driver_private(dip);
10111 10134 if (tran == NULL || (mpt = TRAN2MPT(tran)) == NULL)
10112 10135 return (-1);
10113 10136
10114 10137 return (mptsas_quiesce_bus(mpt));
10115 10138 }
10116 10139
10117 10140 static int
10118 10141 mptsas_scsi_unquiesce(dev_info_t *dip)
10119 10142 {
10120 10143 mptsas_t *mpt;
10121 10144 scsi_hba_tran_t *tran;
10122 10145
10123 10146 tran = ddi_get_driver_private(dip);
10124 10147 if (tran == NULL || (mpt = TRAN2MPT(tran)) == NULL)
10125 10148 return (-1);
10126 10149
10127 10150 return (mptsas_unquiesce_bus(mpt));
10128 10151 }
10129 10152
10130 10153 static int
10131 10154 mptsas_quiesce_bus(mptsas_t *mpt)
10132 10155 {
10133 10156 mptsas_target_t *ptgt = NULL;
10134 10157
10135 10158 NDBG28(("mptsas_quiesce_bus"));
10136 10159 mutex_enter(&mpt->m_mutex);
10137 10160
10138 10161 /* Set all the throttles to zero */
10139 10162 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL;
10140 10163 ptgt = refhash_next(mpt->m_targets, ptgt)) {
10141 10164 mptsas_set_throttle(mpt, ptgt, HOLD_THROTTLE);
10142 10165 }
10143 10166
10144 10167 /* If there are any outstanding commands in the queue */
10145 10168 if (mpt->m_ncmds) {
10146 10169 mpt->m_softstate |= MPTSAS_SS_DRAINING;
10147 10170 mpt->m_quiesce_timeid = timeout(mptsas_ncmds_checkdrain,
10148 10171 mpt, (MPTSAS_QUIESCE_TIMEOUT * drv_usectohz(1000000)));
10149 10172 if (cv_wait_sig(&mpt->m_cv, &mpt->m_mutex) == 0) {
10150 10173 /*
10151 10174 * Quiesce has been interrupted
10152 10175 */
10153 10176 mpt->m_softstate &= ~MPTSAS_SS_DRAINING;
10154 10177 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL;
10155 10178 ptgt = refhash_next(mpt->m_targets, ptgt)) {
10156 10179 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE);
10157 10180 }
10158 10181 mptsas_restart_hba(mpt);
10159 10182 if (mpt->m_quiesce_timeid != 0) {
10160 10183 timeout_id_t tid = mpt->m_quiesce_timeid;
10161 10184 mpt->m_quiesce_timeid = 0;
10162 10185 mutex_exit(&mpt->m_mutex);
10163 10186 (void) untimeout(tid);
10164 10187 return (-1);
10165 10188 }
10166 10189 mutex_exit(&mpt->m_mutex);
10167 10190 return (-1);
10168 10191 } else {
10169 10192 /* Bus has been quiesced */
10170 10193 ASSERT(mpt->m_quiesce_timeid == 0);
10171 10194 mpt->m_softstate &= ~MPTSAS_SS_DRAINING;
10172 10195 mpt->m_softstate |= MPTSAS_SS_QUIESCED;
10173 10196 mutex_exit(&mpt->m_mutex);
10174 10197 return (0);
10175 10198 }
10176 10199 }
10177 10200 /* Bus was not busy - QUIESCED */
10178 10201 mutex_exit(&mpt->m_mutex);
10179 10202
10180 10203 return (0);
10181 10204 }
10182 10205
10183 10206 static int
10184 10207 mptsas_unquiesce_bus(mptsas_t *mpt)
10185 10208 {
10186 10209 mptsas_target_t *ptgt = NULL;
10187 10210
10188 10211 NDBG28(("mptsas_unquiesce_bus"));
10189 10212 mutex_enter(&mpt->m_mutex);
10190 10213 mpt->m_softstate &= ~MPTSAS_SS_QUIESCED;
10191 10214 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL;
10192 10215 ptgt = refhash_next(mpt->m_targets, ptgt)) {
10193 10216 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE);
10194 10217 }
10195 10218 mptsas_restart_hba(mpt);
10196 10219 mutex_exit(&mpt->m_mutex);
10197 10220 return (0);
10198 10221 }
10199 10222
10200 10223 static void
10201 10224 mptsas_ncmds_checkdrain(void *arg)
10202 10225 {
10203 10226 mptsas_t *mpt = arg;
10204 10227 mptsas_target_t *ptgt = NULL;
10205 10228
10206 10229 mutex_enter(&mpt->m_mutex);
10207 10230 if (mpt->m_softstate & MPTSAS_SS_DRAINING) {
10208 10231 mpt->m_quiesce_timeid = 0;
10209 10232 if (mpt->m_ncmds == 0) {
10210 10233 /* Command queue has been drained */
10211 10234 cv_signal(&mpt->m_cv);
10212 10235 } else {
10213 10236 /*
10214 10237 * The throttle may have been reset because
10215 10238 * of a SCSI bus reset
10216 10239 */
10217 10240 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL;
10218 10241 ptgt = refhash_next(mpt->m_targets, ptgt)) {
10219 10242 mptsas_set_throttle(mpt, ptgt, HOLD_THROTTLE);
10220 10243 }
10221 10244
10222 10245 mpt->m_quiesce_timeid = timeout(mptsas_ncmds_checkdrain,
10223 10246 mpt, (MPTSAS_QUIESCE_TIMEOUT *
10224 10247 drv_usectohz(1000000)));
10225 10248 }
10226 10249 }
10227 10250 mutex_exit(&mpt->m_mutex);
10228 10251 }
10229 10252
10230 10253 /*ARGSUSED*/
10231 10254 static void
10232 10255 mptsas_dump_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd)
10233 10256 {
10234 10257 int i;
10235 10258 uint8_t *cp = (uchar_t *)cmd->cmd_pkt->pkt_cdbp;
10236 10259 char buf[128];
10237 10260
10238 10261 buf[0] = '\0';
10239 10262 NDBG25(("?Cmd (0x%p) dump for Target %d Lun %d:\n", (void *)cmd,
10240 10263 Tgt(cmd), Lun(cmd)));
10241 10264 (void) sprintf(&buf[0], "\tcdb=[");
10242 10265 for (i = 0; i < (int)cmd->cmd_cdblen; i++) {
10243 10266 (void) sprintf(&buf[strlen(buf)], " 0x%x", *cp++);
10244 10267 }
10245 10268 (void) sprintf(&buf[strlen(buf)], " ]");
10246 10269 NDBG25(("?%s\n", buf));
10247 10270 NDBG25(("?pkt_flags=0x%x pkt_statistics=0x%x pkt_state=0x%x\n",
10248 10271 cmd->cmd_pkt->pkt_flags, cmd->cmd_pkt->pkt_statistics,
10249 10272 cmd->cmd_pkt->pkt_state));
10250 10273 NDBG25(("?pkt_scbp=0x%x cmd_flags=0x%x\n", cmd->cmd_pkt->pkt_scbp ?
10251 10274 *(cmd->cmd_pkt->pkt_scbp) : 0, cmd->cmd_flags));
10252 10275 }
10253 10276
10254 10277 static void
10255 10278 mptsas_passthru_sge(ddi_acc_handle_t acc_hdl, mptsas_pt_request_t *pt,
10256 10279 pMpi2SGESimple64_t sgep)
10257 10280 {
10258 10281 uint32_t sge_flags;
10259 10282 uint32_t data_size, dataout_size;
10260 10283 ddi_dma_cookie_t data_cookie;
10261 10284 ddi_dma_cookie_t dataout_cookie;
10262 10285
10263 10286 data_size = pt->data_size;
10264 10287 dataout_size = pt->dataout_size;
10265 10288 data_cookie = pt->data_cookie;
10266 10289 dataout_cookie = pt->dataout_cookie;
10267 10290
10268 10291 if (dataout_size) {
10269 10292 sge_flags = dataout_size |
10270 10293 ((uint32_t)(MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
10271 10294 MPI2_SGE_FLAGS_END_OF_BUFFER |
10272 10295 MPI2_SGE_FLAGS_HOST_TO_IOC |
10273 10296 MPI2_SGE_FLAGS_64_BIT_ADDRESSING) <<
10274 10297 MPI2_SGE_FLAGS_SHIFT);
10275 10298 ddi_put32(acc_hdl, &sgep->FlagsLength, sge_flags);
10276 10299 ddi_put32(acc_hdl, &sgep->Address.Low,
10277 10300 (uint32_t)(dataout_cookie.dmac_laddress &
10278 10301 0xffffffffull));
10279 10302 ddi_put32(acc_hdl, &sgep->Address.High,
10280 10303 (uint32_t)(dataout_cookie.dmac_laddress
10281 10304 >> 32));
10282 10305 sgep++;
10283 10306 }
10284 10307 sge_flags = data_size;
10285 10308 sge_flags |= ((uint32_t)(MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
10286 10309 MPI2_SGE_FLAGS_LAST_ELEMENT |
10287 10310 MPI2_SGE_FLAGS_END_OF_BUFFER |
10288 10311 MPI2_SGE_FLAGS_END_OF_LIST |
10289 10312 MPI2_SGE_FLAGS_64_BIT_ADDRESSING) <<
10290 10313 MPI2_SGE_FLAGS_SHIFT);
10291 10314 if (pt->direction == MPTSAS_PASS_THRU_DIRECTION_WRITE) {
10292 10315 sge_flags |= ((uint32_t)(MPI2_SGE_FLAGS_HOST_TO_IOC) <<
10293 10316 MPI2_SGE_FLAGS_SHIFT);
10294 10317 } else {
10295 10318 sge_flags |= ((uint32_t)(MPI2_SGE_FLAGS_IOC_TO_HOST) <<
10296 10319 MPI2_SGE_FLAGS_SHIFT);
10297 10320 }
10298 10321 ddi_put32(acc_hdl, &sgep->FlagsLength,
10299 10322 sge_flags);
10300 10323 ddi_put32(acc_hdl, &sgep->Address.Low,
10301 10324 (uint32_t)(data_cookie.dmac_laddress &
10302 10325 0xffffffffull));
10303 10326 ddi_put32(acc_hdl, &sgep->Address.High,
10304 10327 (uint32_t)(data_cookie.dmac_laddress >> 32));
10305 10328 }
10306 10329
10307 10330 static void
10308 10331 mptsas_passthru_ieee_sge(ddi_acc_handle_t acc_hdl, mptsas_pt_request_t *pt,
10309 10332 pMpi2IeeeSgeSimple64_t ieeesgep)
10310 10333 {
10311 10334 uint8_t sge_flags;
10312 10335 uint32_t data_size, dataout_size;
10313 10336 ddi_dma_cookie_t data_cookie;
10314 10337 ddi_dma_cookie_t dataout_cookie;
10315 10338
10316 10339 data_size = pt->data_size;
10317 10340 dataout_size = pt->dataout_size;
10318 10341 data_cookie = pt->data_cookie;
10319 10342 dataout_cookie = pt->dataout_cookie;
10320 10343
10321 10344 sge_flags = (MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
10322 10345 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR);
10323 10346 if (dataout_size) {
10324 10347 ddi_put32(acc_hdl, &ieeesgep->Length, dataout_size);
10325 10348 ddi_put32(acc_hdl, &ieeesgep->Address.Low,
10326 10349 (uint32_t)(dataout_cookie.dmac_laddress &
10327 10350 0xffffffffull));
10328 10351 ddi_put32(acc_hdl, &ieeesgep->Address.High,
10329 10352 (uint32_t)(dataout_cookie.dmac_laddress >> 32));
10330 10353 ddi_put8(acc_hdl, &ieeesgep->Flags, sge_flags);
10331 10354 ieeesgep++;
10332 10355 }
10333 10356 sge_flags |= MPI25_IEEE_SGE_FLAGS_END_OF_LIST;
10334 10357 ddi_put32(acc_hdl, &ieeesgep->Length, data_size);
10335 10358 ddi_put32(acc_hdl, &ieeesgep->Address.Low,
10336 10359 (uint32_t)(data_cookie.dmac_laddress & 0xffffffffull));
10337 10360 ddi_put32(acc_hdl, &ieeesgep->Address.High,
10338 10361 (uint32_t)(data_cookie.dmac_laddress >> 32));
10339 10362 ddi_put8(acc_hdl, &ieeesgep->Flags, sge_flags);
10340 10363 }
10341 10364
10342 10365 static void
10343 10366 mptsas_start_passthru(mptsas_t *mpt, mptsas_cmd_t *cmd)
10344 10367 {
10345 10368 caddr_t memp;
10346 10369 pMPI2RequestHeader_t request_hdrp;
10347 10370 struct scsi_pkt *pkt = cmd->cmd_pkt;
10348 10371 mptsas_pt_request_t *pt = pkt->pkt_ha_private;
10349 10372 uint32_t request_size;
10350 10373 uint32_t i;
10351 10374 uint64_t request_desc = 0;
10352 10375 uint8_t desc_type;
10353 10376 uint16_t SMID;
10354 10377 uint8_t *request, function;
10355 10378 ddi_dma_handle_t dma_hdl = mpt->m_dma_req_frame_hdl;
10356 10379 ddi_acc_handle_t acc_hdl = mpt->m_acc_req_frame_hdl;
10357 10380
10358 10381 desc_type = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE;
10359 10382
10360 10383 request = pt->request;
10361 10384 request_size = pt->request_size;
10362 10385
10363 10386 SMID = cmd->cmd_slot;
10364 10387
10365 10388 /*
10366 10389 * Store the passthrough message in memory location
10367 10390 * corresponding to our slot number
10368 10391 */
10369 10392 memp = mpt->m_req_frame + (mpt->m_req_frame_size * SMID);
10370 10393 request_hdrp = (pMPI2RequestHeader_t)memp;
10371 10394 bzero(memp, mpt->m_req_frame_size);
10372 10395
10373 10396 for (i = 0; i < request_size; i++) {
10374 10397 bcopy(request + i, memp + i, 1);
10375 10398 }
10376 10399
10377 10400 NDBG15(("mptsas_start_passthru: Func 0x%x, MsgFlags 0x%x, "
10378 10401 "size=%d, in %d, out %d, SMID %d", request_hdrp->Function,
10379 10402 request_hdrp->MsgFlags, request_size,
10380 10403 pt->data_size, pt->dataout_size, SMID));
10381 10404
10382 10405 /*
10383 10406 * Add an SGE, even if the length is zero.
10384 10407 */
10385 10408 if (mpt->m_MPI25 && pt->simple == 0) {
10386 10409 mptsas_passthru_ieee_sge(acc_hdl, pt,
10387 10410 (pMpi2IeeeSgeSimple64_t)
10388 10411 ((uint8_t *)request_hdrp + pt->sgl_offset));
10389 10412 } else {
10390 10413 mptsas_passthru_sge(acc_hdl, pt,
10391 10414 (pMpi2SGESimple64_t)
10392 10415 ((uint8_t *)request_hdrp + pt->sgl_offset));
10393 10416 }
10394 10417
10395 10418 function = request_hdrp->Function;
10396 10419 if ((function == MPI2_FUNCTION_SCSI_IO_REQUEST) ||
10397 10420 (function == MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH)) {
10398 10421 pMpi2SCSIIORequest_t scsi_io_req;
10399 10422 caddr_t arsbuf;
10400 10423 uint8_t ars_size;
10401 10424 uint32_t ars_dmaaddrlow;
10402 10425
10403 10426 NDBG15(("mptsas_start_passthru: Is SCSI IO Req"));
10404 10427 scsi_io_req = (pMpi2SCSIIORequest_t)request_hdrp;
10405 10428
10406 10429 if (cmd->cmd_extrqslen != 0) {
10407 10430 /*
10408 10431 * Mapping of the buffer was done in
10409 10432 * mptsas_do_passthru().
10410 10433 * Calculate the DMA address with the same offset.
10411 10434 */
10412 10435 arsbuf = cmd->cmd_arq_buf;
10413 10436 ars_size = cmd->cmd_extrqslen;
10414 10437 ars_dmaaddrlow = (mpt->m_req_sense_dma_addr +
10415 10438 ((uintptr_t)arsbuf - (uintptr_t)mpt->m_req_sense)) &
10416 10439 0xffffffffu;
10417 10440 } else {
10418 10441 arsbuf = mpt->m_req_sense +
10419 10442 (mpt->m_req_sense_size * (SMID-1));
10420 10443 cmd->cmd_arq_buf = arsbuf;
10421 10444 ars_size = mpt->m_req_sense_size;
10422 10445 ars_dmaaddrlow = (mpt->m_req_sense_dma_addr +
10423 10446 (mpt->m_req_sense_size * (SMID-1))) &
10424 10447 0xffffffffu;
10425 10448 }
10426 10449 bzero(arsbuf, ars_size);
10427 10450
10428 10451 ddi_put8(acc_hdl, &scsi_io_req->SenseBufferLength, ars_size);
10429 10452 ddi_put32(acc_hdl, &scsi_io_req->SenseBufferLowAddress,
10430 10453 ars_dmaaddrlow);
10431 10454
10432 10455 /*
10433 10456 * Put SGE for data and data_out buffer at the end of
10434 10457 * scsi_io_request message header.(64 bytes in total)
10435 10458 * Set SGLOffset0 value
10436 10459 */
10437 10460 ddi_put8(acc_hdl, &scsi_io_req->SGLOffset0,
10438 10461 offsetof(MPI2_SCSI_IO_REQUEST, SGL) / 4);
10439 10462
10440 10463 /*
10441 10464 * Setup descriptor info. RAID passthrough must use the
10442 10465 * default request descriptor which is already set, so if this
10443 10466 * is a SCSI IO request, change the descriptor to SCSI IO.
10444 10467 */
10445 10468 if (function == MPI2_FUNCTION_SCSI_IO_REQUEST) {
10446 10469 desc_type = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO;
10447 10470 request_desc = ((uint64_t)ddi_get16(acc_hdl,
10448 10471 &scsi_io_req->DevHandle) << 48);
10449 10472 }
10450 10473 (void) ddi_dma_sync(mpt->m_dma_req_sense_hdl, 0, 0,
10451 10474 DDI_DMA_SYNC_FORDEV);
10452 10475 }
10453 10476
10454 10477 /*
10455 10478 * We must wait till the message has been completed before
10456 10479 * beginning the next message so we wait for this one to
10457 10480 * finish.
10458 10481 */
10459 10482 (void) ddi_dma_sync(dma_hdl, 0, 0, DDI_DMA_SYNC_FORDEV);
10460 10483 request_desc |= (SMID << 16) + desc_type;
10461 10484 cmd->cmd_rfm = NULL;
10462 10485 MPTSAS_START_CMD(mpt, request_desc);
10463 10486 if ((mptsas_check_dma_handle(dma_hdl) != DDI_SUCCESS) ||
10464 10487 (mptsas_check_acc_handle(acc_hdl) != DDI_SUCCESS)) {
10465 10488 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
10466 10489 }
10467 10490 }
10468 10491
10469 10492 typedef void (mptsas_pre_f)(mptsas_t *, mptsas_pt_request_t *);
10470 10493 static mptsas_pre_f mpi_pre_ioc_facts;
10471 10494 static mptsas_pre_f mpi_pre_port_facts;
10472 10495 static mptsas_pre_f mpi_pre_fw_download;
10473 10496 static mptsas_pre_f mpi_pre_fw_25_download;
10474 10497 static mptsas_pre_f mpi_pre_fw_upload;
10475 10498 static mptsas_pre_f mpi_pre_fw_25_upload;
10476 10499 static mptsas_pre_f mpi_pre_sata_passthrough;
10477 10500 static mptsas_pre_f mpi_pre_smp_passthrough;
10478 10501 static mptsas_pre_f mpi_pre_config;
10479 10502 static mptsas_pre_f mpi_pre_sas_io_unit_control;
10480 10503 static mptsas_pre_f mpi_pre_scsi_io_req;
10481 10504
10482 10505 /*
10483 10506 * Prepare the pt for a SAS2 FW_DOWNLOAD request.
10484 10507 */
10485 10508 static void
10486 10509 mpi_pre_fw_download(mptsas_t *mpt, mptsas_pt_request_t *pt)
10487 10510 {
10488 10511 pMpi2FWDownloadTCSGE_t tcsge;
10489 10512 pMpi2FWDownloadRequest req;
10490 10513
10491 10514 /*
10492 10515 * If SAS3, call separate function.
10493 10516 */
10494 10517 if (mpt->m_MPI25) {
10495 10518 mpi_pre_fw_25_download(mpt, pt);
10496 10519 return;
10497 10520 }
10498 10521
10499 10522 /*
10500 10523 * User requests should come in with the Transaction
10501 10524 * context element where the SGL will go. Putting the
10502 10525 * SGL after that seems to work, but don't really know
10503 10526 * why. Other drivers tend to create an extra SGL and
10504 10527 * refer to the TCE through that.
10505 10528 */
10506 10529 req = (pMpi2FWDownloadRequest)pt->request;
10507 10530 tcsge = (pMpi2FWDownloadTCSGE_t)&req->SGL;
10508 10531 if (tcsge->ContextSize != 0 || tcsge->DetailsLength != 12 ||
10509 10532 tcsge->Flags != MPI2_SGE_FLAGS_TRANSACTION_ELEMENT) {
10510 10533 mptsas_log(mpt, CE_WARN, "FW Download tce invalid!");
10511 10534 }
10512 10535
10513 10536 pt->sgl_offset = offsetof(MPI2_FW_DOWNLOAD_REQUEST, SGL) +
10514 10537 sizeof (*tcsge);
10515 10538 if (pt->request_size != pt->sgl_offset)
10516 10539 NDBG15(("mpi_pre_fw_download(): Incorrect req size, "
10517 10540 "0x%x, should be 0x%x, dataoutsz 0x%x",
10518 10541 (int)pt->request_size, (int)pt->sgl_offset,
10519 10542 (int)pt->dataout_size));
10520 10543 if (pt->data_size < sizeof (MPI2_FW_DOWNLOAD_REPLY))
10521 10544 NDBG15(("mpi_pre_fw_download(): Incorrect rep size, "
10522 10545 "0x%x, should be 0x%x", pt->data_size,
10523 10546 (int)sizeof (MPI2_FW_DOWNLOAD_REPLY)));
10524 10547 }
10525 10548
10526 10549 /*
10527 10550 * Prepare the pt for a SAS3 FW_DOWNLOAD request.
10528 10551 */
10529 10552 static void
10530 10553 mpi_pre_fw_25_download(mptsas_t *mpt, mptsas_pt_request_t *pt)
10531 10554 {
10532 10555 pMpi2FWDownloadTCSGE_t tcsge;
10533 10556 pMpi2FWDownloadRequest req2;
10534 10557 pMpi25FWDownloadRequest req25;
10535 10558
10536 10559 /*
10537 10560 * User requests should come in with the Transaction
10538 10561 * context element where the SGL will go. The new firmware
10539 10562 * Doesn't use TCE and has space in the main request for
10540 10563 * this information. So move to the right place.
10541 10564 */
10542 10565 req2 = (pMpi2FWDownloadRequest)pt->request;
10543 10566 req25 = (pMpi25FWDownloadRequest)pt->request;
10544 10567 tcsge = (pMpi2FWDownloadTCSGE_t)&req2->SGL;
10545 10568 if (tcsge->ContextSize != 0 || tcsge->DetailsLength != 12 ||
10546 10569 tcsge->Flags != MPI2_SGE_FLAGS_TRANSACTION_ELEMENT) {
10547 10570 mptsas_log(mpt, CE_WARN, "FW Download tce invalid!");
10548 10571 }
10549 10572 req25->ImageOffset = tcsge->ImageOffset;
10550 10573 req25->ImageSize = tcsge->ImageSize;
10551 10574
10552 10575 pt->sgl_offset = offsetof(MPI25_FW_DOWNLOAD_REQUEST, SGL);
10553 10576 if (pt->request_size != pt->sgl_offset)
10554 10577 NDBG15(("mpi_pre_fw_25_download(): Incorrect req size, "
10555 10578 "0x%x, should be 0x%x, dataoutsz 0x%x",
10556 10579 pt->request_size, pt->sgl_offset,
10557 10580 pt->dataout_size));
10558 10581 if (pt->data_size < sizeof (MPI2_FW_DOWNLOAD_REPLY))
10559 10582 NDBG15(("mpi_pre_fw_25_download(): Incorrect rep size, "
10560 10583 "0x%x, should be 0x%x", pt->data_size,
10561 10584 (int)sizeof (MPI2_FW_UPLOAD_REPLY)));
10562 10585 }
10563 10586
10564 10587 /*
10565 10588 * Prepare the pt for a SAS2 FW_UPLOAD request.
10566 10589 */
10567 10590 static void
10568 10591 mpi_pre_fw_upload(mptsas_t *mpt, mptsas_pt_request_t *pt)
10569 10592 {
10570 10593 pMpi2FWUploadTCSGE_t tcsge;
10571 10594 pMpi2FWUploadRequest_t req;
10572 10595
10573 10596 /*
10574 10597 * If SAS3, call separate function.
10575 10598 */
10576 10599 if (mpt->m_MPI25) {
10577 10600 mpi_pre_fw_25_upload(mpt, pt);
10578 10601 return;
10579 10602 }
10580 10603
10581 10604 /*
10582 10605 * User requests should come in with the Transaction
10583 10606 * context element where the SGL will go. Putting the
10584 10607 * SGL after that seems to work, but don't really know
10585 10608 * why. Other drivers tend to create an extra SGL and
10586 10609 * refer to the TCE through that.
10587 10610 */
10588 10611 req = (pMpi2FWUploadRequest_t)pt->request;
10589 10612 tcsge = (pMpi2FWUploadTCSGE_t)&req->SGL;
10590 10613 if (tcsge->ContextSize != 0 || tcsge->DetailsLength != 12 ||
10591 10614 tcsge->Flags != MPI2_SGE_FLAGS_TRANSACTION_ELEMENT) {
10592 10615 mptsas_log(mpt, CE_WARN, "FW Upload tce invalid!");
10593 10616 }
10594 10617
10595 10618 pt->sgl_offset = offsetof(MPI2_FW_UPLOAD_REQUEST, SGL) +
10596 10619 sizeof (*tcsge);
10597 10620 if (pt->request_size != pt->sgl_offset)
10598 10621 NDBG15(("mpi_pre_fw_upload(): Incorrect req size, "
10599 10622 "0x%x, should be 0x%x, dataoutsz 0x%x",
10600 10623 pt->request_size, pt->sgl_offset,
10601 10624 pt->dataout_size));
10602 10625 if (pt->data_size < sizeof (MPI2_FW_UPLOAD_REPLY))
10603 10626 NDBG15(("mpi_pre_fw_upload(): Incorrect rep size, "
10604 10627 "0x%x, should be 0x%x", pt->data_size,
10605 10628 (int)sizeof (MPI2_FW_UPLOAD_REPLY)));
10606 10629 }
10607 10630
10608 10631 /*
10609 10632 * Prepare the pt a SAS3 FW_UPLOAD request.
10610 10633 */
10611 10634 static void
10612 10635 mpi_pre_fw_25_upload(mptsas_t *mpt, mptsas_pt_request_t *pt)
10613 10636 {
10614 10637 pMpi2FWUploadTCSGE_t tcsge;
10615 10638 pMpi2FWUploadRequest_t req2;
10616 10639 pMpi25FWUploadRequest_t req25;
10617 10640
10618 10641 /*
10619 10642 * User requests should come in with the Transaction
10620 10643 * context element where the SGL will go. The new firmware
10621 10644 * Doesn't use TCE and has space in the main request for
10622 10645 * this information. So move to the right place.
10623 10646 */
10624 10647 req2 = (pMpi2FWUploadRequest_t)pt->request;
10625 10648 req25 = (pMpi25FWUploadRequest_t)pt->request;
10626 10649 tcsge = (pMpi2FWUploadTCSGE_t)&req2->SGL;
10627 10650 if (tcsge->ContextSize != 0 || tcsge->DetailsLength != 12 ||
10628 10651 tcsge->Flags != MPI2_SGE_FLAGS_TRANSACTION_ELEMENT) {
10629 10652 mptsas_log(mpt, CE_WARN, "FW Upload tce invalid!");
10630 10653 }
10631 10654 req25->ImageOffset = tcsge->ImageOffset;
10632 10655 req25->ImageSize = tcsge->ImageSize;
10633 10656
10634 10657 pt->sgl_offset = offsetof(MPI25_FW_UPLOAD_REQUEST, SGL);
10635 10658 if (pt->request_size != pt->sgl_offset)
10636 10659 NDBG15(("mpi_pre_fw_25_upload(): Incorrect req size, "
10637 10660 "0x%x, should be 0x%x, dataoutsz 0x%x",
10638 10661 pt->request_size, pt->sgl_offset,
10639 10662 pt->dataout_size));
10640 10663 if (pt->data_size < sizeof (MPI2_FW_UPLOAD_REPLY))
10641 10664 NDBG15(("mpi_pre_fw_25_upload(): Incorrect rep size, "
10642 10665 "0x%x, should be 0x%x", pt->data_size,
10643 10666 (int)sizeof (MPI2_FW_UPLOAD_REPLY)));
10644 10667 }
10645 10668
10646 10669 /*
10647 10670 * Prepare the pt for an IOC_FACTS request.
10648 10671 */
10649 10672 static void
10650 10673 mpi_pre_ioc_facts(mptsas_t *mpt, mptsas_pt_request_t *pt)
10651 10674 {
10652 10675 #ifndef __lock_lint
10653 10676 _NOTE(ARGUNUSED(mpt))
10654 10677 #endif
10655 10678 if (pt->request_size != sizeof (MPI2_IOC_FACTS_REQUEST))
10656 10679 NDBG15(("mpi_pre_ioc_facts(): Incorrect req size, "
10657 10680 "0x%x, should be 0x%x, dataoutsz 0x%x",
10658 10681 pt->request_size,
10659 10682 (int)sizeof (MPI2_IOC_FACTS_REQUEST),
10660 10683 pt->dataout_size));
10661 10684 if (pt->data_size != sizeof (MPI2_IOC_FACTS_REPLY))
10662 10685 NDBG15(("mpi_pre_ioc_facts(): Incorrect rep size, "
10663 10686 "0x%x, should be 0x%x", pt->data_size,
10664 10687 (int)sizeof (MPI2_IOC_FACTS_REPLY)));
10665 10688 pt->sgl_offset = (uint16_t)pt->request_size;
10666 10689 }
10667 10690
10668 10691 /*
10669 10692 * Prepare the pt for a PORT_FACTS request.
10670 10693 */
10671 10694 static void
10672 10695 mpi_pre_port_facts(mptsas_t *mpt, mptsas_pt_request_t *pt)
10673 10696 {
10674 10697 #ifndef __lock_lint
10675 10698 _NOTE(ARGUNUSED(mpt))
10676 10699 #endif
10677 10700 if (pt->request_size != sizeof (MPI2_PORT_FACTS_REQUEST))
10678 10701 NDBG15(("mpi_pre_port_facts(): Incorrect req size, "
10679 10702 "0x%x, should be 0x%x, dataoutsz 0x%x",
10680 10703 pt->request_size,
10681 10704 (int)sizeof (MPI2_PORT_FACTS_REQUEST),
10682 10705 pt->dataout_size));
10683 10706 if (pt->data_size != sizeof (MPI2_PORT_FACTS_REPLY))
10684 10707 NDBG15(("mpi_pre_port_facts(): Incorrect rep size, "
10685 10708 "0x%x, should be 0x%x", pt->data_size,
10686 10709 (int)sizeof (MPI2_PORT_FACTS_REPLY)));
10687 10710 pt->sgl_offset = (uint16_t)pt->request_size;
10688 10711 }
10689 10712
10690 10713 /*
10691 10714 * Prepare pt for a SATA_PASSTHROUGH request.
10692 10715 */
10693 10716 static void
10694 10717 mpi_pre_sata_passthrough(mptsas_t *mpt, mptsas_pt_request_t *pt)
10695 10718 {
10696 10719 #ifndef __lock_lint
10697 10720 _NOTE(ARGUNUSED(mpt))
10698 10721 #endif
10699 10722 pt->sgl_offset = offsetof(MPI2_SATA_PASSTHROUGH_REQUEST, SGL);
10700 10723 if (pt->request_size != pt->sgl_offset)
10701 10724 NDBG15(("mpi_pre_sata_passthrough(): Incorrect req size, "
10702 10725 "0x%x, should be 0x%x, dataoutsz 0x%x",
10703 10726 pt->request_size, pt->sgl_offset,
10704 10727 pt->dataout_size));
10705 10728 if (pt->data_size != sizeof (MPI2_SATA_PASSTHROUGH_REPLY))
10706 10729 NDBG15(("mpi_pre_sata_passthrough(): Incorrect rep size, "
10707 10730 "0x%x, should be 0x%x", pt->data_size,
10708 10731 (int)sizeof (MPI2_SATA_PASSTHROUGH_REPLY)));
10709 10732 }
10710 10733
10711 10734 static void
10712 10735 mpi_pre_smp_passthrough(mptsas_t *mpt, mptsas_pt_request_t *pt)
10713 10736 {
10714 10737 #ifndef __lock_lint
10715 10738 _NOTE(ARGUNUSED(mpt))
10716 10739 #endif
10717 10740 pt->sgl_offset = offsetof(MPI2_SMP_PASSTHROUGH_REQUEST, SGL);
10718 10741 if (pt->request_size != pt->sgl_offset)
10719 10742 NDBG15(("mpi_pre_smp_passthrough(): Incorrect req size, "
10720 10743 "0x%x, should be 0x%x, dataoutsz 0x%x",
10721 10744 pt->request_size, pt->sgl_offset,
10722 10745 pt->dataout_size));
10723 10746 if (pt->data_size != sizeof (MPI2_SMP_PASSTHROUGH_REPLY))
10724 10747 NDBG15(("mpi_pre_smp_passthrough(): Incorrect rep size, "
10725 10748 "0x%x, should be 0x%x", pt->data_size,
10726 10749 (int)sizeof (MPI2_SMP_PASSTHROUGH_REPLY)));
10727 10750 }
10728 10751
10729 10752 /*
10730 10753 * Prepare pt for a CONFIG request.
10731 10754 */
10732 10755 static void
10733 10756 mpi_pre_config(mptsas_t *mpt, mptsas_pt_request_t *pt)
10734 10757 {
10735 10758 #ifndef __lock_lint
10736 10759 _NOTE(ARGUNUSED(mpt))
10737 10760 #endif
10738 10761 pt->sgl_offset = offsetof(MPI2_CONFIG_REQUEST, PageBufferSGE);
10739 10762 if (pt->request_size != pt->sgl_offset)
10740 10763 NDBG15(("mpi_pre_config(): Incorrect req size, 0x%x, "
10741 10764 "should be 0x%x, dataoutsz 0x%x", pt->request_size,
10742 10765 pt->sgl_offset, pt->dataout_size));
10743 10766 if (pt->data_size != sizeof (MPI2_CONFIG_REPLY))
10744 10767 NDBG15(("mpi_pre_config(): Incorrect rep size, 0x%x, "
10745 10768 "should be 0x%x", pt->data_size,
10746 10769 (int)sizeof (MPI2_CONFIG_REPLY)));
10747 10770 pt->simple = 1;
10748 10771 }
10749 10772
10750 10773 /*
10751 10774 * Prepare pt for a SCSI_IO_REQ request.
10752 10775 */
10753 10776 static void
10754 10777 mpi_pre_scsi_io_req(mptsas_t *mpt, mptsas_pt_request_t *pt)
10755 10778 {
10756 10779 #ifndef __lock_lint
10757 10780 _NOTE(ARGUNUSED(mpt))
10758 10781 #endif
10759 10782 pt->sgl_offset = offsetof(MPI2_SCSI_IO_REQUEST, SGL);
10760 10783 if (pt->request_size != pt->sgl_offset)
10761 10784 NDBG15(("mpi_pre_config(): Incorrect req size, 0x%x, "
10762 10785 "should be 0x%x, dataoutsz 0x%x", pt->request_size,
10763 10786 pt->sgl_offset,
10764 10787 pt->dataout_size));
10765 10788 if (pt->data_size != sizeof (MPI2_SCSI_IO_REPLY))
10766 10789 NDBG15(("mpi_pre_config(): Incorrect rep size, 0x%x, "
10767 10790 "should be 0x%x", pt->data_size,
10768 10791 (int)sizeof (MPI2_SCSI_IO_REPLY)));
10769 10792 }
10770 10793
10771 10794 /*
10772 10795 * Prepare the mptsas_cmd for a SAS_IO_UNIT_CONTROL request.
10773 10796 */
10774 10797 static void
10775 10798 mpi_pre_sas_io_unit_control(mptsas_t *mpt, mptsas_pt_request_t *pt)
10776 10799 {
10777 10800 #ifndef __lock_lint
10778 10801 _NOTE(ARGUNUSED(mpt))
10779 10802 #endif
10780 10803 pt->sgl_offset = (uint16_t)pt->request_size;
10781 10804 }
10782 10805
10783 10806 /*
10784 10807 * A set of functions to prepare an mptsas_cmd for the various
10785 10808 * supported requests.
10786 10809 */
10787 10810 static struct mptsas_func {
10788 10811 U8 Function;
10789 10812 char *Name;
10790 10813 mptsas_pre_f *f_pre;
10791 10814 } mptsas_func_list[] = {
10792 10815 { MPI2_FUNCTION_IOC_FACTS, "IOC_FACTS", mpi_pre_ioc_facts },
10793 10816 { MPI2_FUNCTION_PORT_FACTS, "PORT_FACTS", mpi_pre_port_facts },
10794 10817 { MPI2_FUNCTION_FW_DOWNLOAD, "FW_DOWNLOAD", mpi_pre_fw_download },
10795 10818 { MPI2_FUNCTION_FW_UPLOAD, "FW_UPLOAD", mpi_pre_fw_upload },
10796 10819 { MPI2_FUNCTION_SATA_PASSTHROUGH, "SATA_PASSTHROUGH",
10797 10820 mpi_pre_sata_passthrough },
10798 10821 { MPI2_FUNCTION_SMP_PASSTHROUGH, "SMP_PASSTHROUGH",
10799 10822 mpi_pre_smp_passthrough},
10800 10823 { MPI2_FUNCTION_SCSI_IO_REQUEST, "SCSI_IO_REQUEST",
10801 10824 mpi_pre_scsi_io_req},
10802 10825 { MPI2_FUNCTION_CONFIG, "CONFIG", mpi_pre_config},
10803 10826 { MPI2_FUNCTION_SAS_IO_UNIT_CONTROL, "SAS_IO_UNIT_CONTROL",
10804 10827 mpi_pre_sas_io_unit_control },
10805 10828 { 0xFF, NULL, NULL } /* list end */
10806 10829 };
10807 10830
10808 10831 static void
10809 10832 mptsas_prep_sgl_offset(mptsas_t *mpt, mptsas_pt_request_t *pt)
10810 10833 {
10811 10834 pMPI2RequestHeader_t hdr;
10812 10835 struct mptsas_func *f;
10813 10836
10814 10837 hdr = (pMPI2RequestHeader_t)pt->request;
10815 10838
10816 10839 for (f = mptsas_func_list; f->f_pre != NULL; f++) {
10817 10840 if (hdr->Function == f->Function) {
10818 10841 f->f_pre(mpt, pt);
10819 10842 NDBG15(("mptsas_prep_sgl_offset: Function %s,"
10820 10843 " sgl_offset 0x%x", f->Name,
10821 10844 pt->sgl_offset));
10822 10845 return;
10823 10846 }
10824 10847 }
10825 10848 NDBG15(("mptsas_prep_sgl_offset: Unknown Function 0x%02x,"
10826 10849 " returning req_size 0x%x for sgl_offset",
10827 10850 hdr->Function, pt->request_size));
10828 10851 pt->sgl_offset = (uint16_t)pt->request_size;
10829 10852 }
10830 10853
10831 10854
10832 10855 static int
10833 10856 mptsas_do_passthru(mptsas_t *mpt, uint8_t *request, uint8_t *reply,
10834 10857 uint8_t *data, uint32_t request_size, uint32_t reply_size,
10835 10858 uint32_t data_size, uint32_t direction, uint8_t *dataout,
10836 10859 uint32_t dataout_size, short timeout, int mode)
10837 10860 {
10838 10861 mptsas_pt_request_t pt;
10839 10862 mptsas_dma_alloc_state_t data_dma_state;
10840 10863 mptsas_dma_alloc_state_t dataout_dma_state;
10841 10864 caddr_t memp;
10842 10865 mptsas_cmd_t *cmd = NULL;
10843 10866 struct scsi_pkt *pkt;
10844 10867 uint32_t reply_len = 0, sense_len = 0;
10845 10868 pMPI2RequestHeader_t request_hdrp;
10846 10869 pMPI2RequestHeader_t request_msg;
10847 10870 pMPI2DefaultReply_t reply_msg;
10848 10871 Mpi2SCSIIOReply_t rep_msg;
10849 10872 int rvalue;
10850 10873 int i, status = 0, pt_flags = 0, rv = 0;
10851 10874 uint8_t function;
10852 10875
10853 10876 ASSERT(mutex_owned(&mpt->m_mutex));
10854 10877
10855 10878 reply_msg = (pMPI2DefaultReply_t)(&rep_msg);
10856 10879 bzero(reply_msg, sizeof (MPI2_DEFAULT_REPLY));
10857 10880 request_msg = kmem_zalloc(request_size, KM_SLEEP);
10858 10881
10859 10882 mutex_exit(&mpt->m_mutex);
10860 10883 /*
10861 10884 * copy in the request buffer since it could be used by
10862 10885 * another thread when the pt request into waitq
10863 10886 */
10864 10887 if (ddi_copyin(request, request_msg, request_size, mode)) {
10865 10888 mutex_enter(&mpt->m_mutex);
10866 10889 status = EFAULT;
10867 10890 mptsas_log(mpt, CE_WARN, "failed to copy request data");
10868 10891 goto out;
10869 10892 }
10870 10893 NDBG27(("mptsas_do_passthru: mode 0x%x, size 0x%x, Func 0x%x",
10871 10894 mode, request_size, request_msg->Function));
10872 10895 mutex_enter(&mpt->m_mutex);
10873 10896
10874 10897 function = request_msg->Function;
10875 10898 if (function == MPI2_FUNCTION_SCSI_TASK_MGMT) {
10876 10899 pMpi2SCSITaskManagementRequest_t task;
10877 10900 task = (pMpi2SCSITaskManagementRequest_t)request_msg;
10878 10901 mptsas_setup_bus_reset_delay(mpt);
10879 10902 rv = mptsas_ioc_task_management(mpt, task->TaskType,
10880 10903 task->DevHandle, (int)task->LUN[1], reply, reply_size,
10881 10904 mode);
10882 10905
10883 10906 if (rv != TRUE) {
10884 10907 status = EIO;
10885 10908 mptsas_log(mpt, CE_WARN, "task management failed");
10886 10909 }
10887 10910 goto out;
10888 10911 }
10889 10912
10890 10913 if (data_size != 0) {
10891 10914 data_dma_state.size = data_size;
10892 10915 if (mptsas_dma_alloc(mpt, &data_dma_state) != DDI_SUCCESS) {
10893 10916 status = ENOMEM;
10894 10917 mptsas_log(mpt, CE_WARN, "failed to alloc DMA "
10895 10918 "resource");
10896 10919 goto out;
10897 10920 }
10898 10921 pt_flags |= MPTSAS_DATA_ALLOCATED;
10899 10922 if (direction == MPTSAS_PASS_THRU_DIRECTION_WRITE) {
10900 10923 mutex_exit(&mpt->m_mutex);
10901 10924 for (i = 0; i < data_size; i++) {
10902 10925 if (ddi_copyin(data + i, (uint8_t *)
10903 10926 data_dma_state.memp + i, 1, mode)) {
10904 10927 mutex_enter(&mpt->m_mutex);
10905 10928 status = EFAULT;
10906 10929 mptsas_log(mpt, CE_WARN, "failed to "
10907 10930 "copy read data");
10908 10931 goto out;
10909 10932 }
10910 10933 }
10911 10934 mutex_enter(&mpt->m_mutex);
10912 10935 }
10913 10936 } else {
10914 10937 bzero(&data_dma_state, sizeof (data_dma_state));
10915 10938 }
10916 10939
10917 10940 if (dataout_size != 0) {
10918 10941 dataout_dma_state.size = dataout_size;
10919 10942 if (mptsas_dma_alloc(mpt, &dataout_dma_state) != DDI_SUCCESS) {
10920 10943 status = ENOMEM;
10921 10944 mptsas_log(mpt, CE_WARN, "failed to alloc DMA "
10922 10945 "resource");
10923 10946 goto out;
10924 10947 }
10925 10948 pt_flags |= MPTSAS_DATAOUT_ALLOCATED;
10926 10949 mutex_exit(&mpt->m_mutex);
10927 10950 for (i = 0; i < dataout_size; i++) {
10928 10951 if (ddi_copyin(dataout + i, (uint8_t *)
10929 10952 dataout_dma_state.memp + i, 1, mode)) {
10930 10953 mutex_enter(&mpt->m_mutex);
10931 10954 mptsas_log(mpt, CE_WARN, "failed to copy out"
10932 10955 " data");
10933 10956 status = EFAULT;
10934 10957 goto out;
10935 10958 }
10936 10959 }
10937 10960 mutex_enter(&mpt->m_mutex);
10938 10961 } else {
10939 10962 bzero(&dataout_dma_state, sizeof (dataout_dma_state));
10940 10963 }
10941 10964
10942 10965 if ((rvalue = (mptsas_request_from_pool(mpt, &cmd, &pkt))) == -1) {
10943 10966 status = EAGAIN;
10944 10967 mptsas_log(mpt, CE_NOTE, "event ack command pool is full");
10945 10968 goto out;
10946 10969 }
10947 10970 pt_flags |= MPTSAS_REQUEST_POOL_CMD;
10948 10971
10949 10972 bzero((caddr_t)cmd, sizeof (*cmd));
10950 10973 bzero((caddr_t)pkt, scsi_pkt_size());
10951 10974 bzero((caddr_t)&pt, sizeof (pt));
10952 10975
10953 10976 cmd->ioc_cmd_slot = (uint32_t)(rvalue);
10954 10977
10955 10978 pt.request = (uint8_t *)request_msg;
10956 10979 pt.direction = direction;
10957 10980 pt.simple = 0;
10958 10981 pt.request_size = request_size;
10959 10982 pt.data_size = data_size;
10960 10983 pt.dataout_size = dataout_size;
10961 10984 pt.data_cookie = data_dma_state.cookie;
10962 10985 pt.dataout_cookie = dataout_dma_state.cookie;
10963 10986 mptsas_prep_sgl_offset(mpt, &pt);
10964 10987
10965 10988 /*
10966 10989 * Form a blank cmd/pkt to store the acknowledgement message
10967 10990 */
10968 10991 pkt->pkt_cdbp = (opaque_t)&cmd->cmd_cdb[0];
10969 10992 pkt->pkt_scbp = (opaque_t)&cmd->cmd_scb;
10970 10993 pkt->pkt_ha_private = (opaque_t)&pt;
10971 10994 pkt->pkt_flags = FLAG_HEAD;
10972 10995 pkt->pkt_time = timeout;
10973 10996 cmd->cmd_pkt = pkt;
10974 10997 cmd->cmd_flags = CFLAG_CMDIOC | CFLAG_PASSTHRU;
10975 10998
10976 10999 if ((function == MPI2_FUNCTION_SCSI_IO_REQUEST) ||
10977 11000 (function == MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH)) {
10978 11001 uint8_t com, cdb_group_id;
10979 11002 boolean_t ret;
10980 11003
10981 11004 pkt->pkt_cdbp = ((pMpi2SCSIIORequest_t)request_msg)->CDB.CDB32;
10982 11005 com = pkt->pkt_cdbp[0];
10983 11006 cdb_group_id = CDB_GROUPID(com);
10984 11007 switch (cdb_group_id) {
10985 11008 case CDB_GROUPID_0: cmd->cmd_cdblen = CDB_GROUP0; break;
10986 11009 case CDB_GROUPID_1: cmd->cmd_cdblen = CDB_GROUP1; break;
10987 11010 case CDB_GROUPID_2: cmd->cmd_cdblen = CDB_GROUP2; break;
10988 11011 case CDB_GROUPID_4: cmd->cmd_cdblen = CDB_GROUP4; break;
10989 11012 case CDB_GROUPID_5: cmd->cmd_cdblen = CDB_GROUP5; break;
10990 11013 default:
10991 11014 NDBG27(("mptsas_do_passthru: SCSI_IO, reserved "
10992 11015 "CDBGROUP 0x%x requested!", cdb_group_id));
10993 11016 break;
10994 11017 }
10995 11018
10996 11019 reply_len = sizeof (MPI2_SCSI_IO_REPLY);
10997 11020 sense_len = reply_size - reply_len;
10998 11021 ret = mptsas_cmdarqsize(mpt, cmd, sense_len, KM_SLEEP);
10999 11022 VERIFY(ret == B_TRUE);
11000 11023 } else {
11001 11024 reply_len = reply_size;
11002 11025 sense_len = 0;
11003 11026 }
11004 11027
11005 11028 NDBG27(("mptsas_do_passthru: %s, dsz 0x%x, dosz 0x%x, replen 0x%x, "
11006 11029 "snslen 0x%x",
11007 11030 (direction == MPTSAS_PASS_THRU_DIRECTION_WRITE)?"Write":"Read",
11008 11031 data_size, dataout_size, reply_len, sense_len));
11009 11032
11010 11033 /*
11011 11034 * Save the command in a slot
11012 11035 */
11013 11036 if (mptsas_save_cmd(mpt, cmd) == TRUE) {
11014 11037 /*
11015 11038 * Once passthru command get slot, set cmd_flags
11016 11039 * CFLAG_PREPARED.
11017 11040 */
11018 11041 cmd->cmd_flags |= CFLAG_PREPARED;
11019 11042 mptsas_start_passthru(mpt, cmd);
11020 11043 } else {
11021 11044 mptsas_waitq_add(mpt, cmd);
11022 11045 }
11023 11046
11024 11047 while ((cmd->cmd_flags & CFLAG_FINISHED) == 0) {
11025 11048 cv_wait(&mpt->m_passthru_cv, &mpt->m_mutex);
11026 11049 }
11027 11050
11028 11051 NDBG27(("mptsas_do_passthru: Cmd complete, flags 0x%x, rfm 0x%x "
11029 11052 "pktreason 0x%x", cmd->cmd_flags, cmd->cmd_rfm,
11030 11053 pkt->pkt_reason));
11031 11054
11032 11055 if (cmd->cmd_flags & CFLAG_PREPARED) {
11033 11056 memp = mpt->m_req_frame + (mpt->m_req_frame_size *
11034 11057 cmd->cmd_slot);
11035 11058 request_hdrp = (pMPI2RequestHeader_t)memp;
11036 11059 }
11037 11060
11038 11061 if (cmd->cmd_flags & CFLAG_TIMEOUT) {
11039 11062 status = ETIMEDOUT;
11040 11063 mptsas_log(mpt, CE_WARN, "passthrough command timeout");
11041 11064 pt_flags |= MPTSAS_CMD_TIMEOUT;
11042 11065 goto out;
11043 11066 }
11044 11067
11045 11068 if (cmd->cmd_rfm) {
11046 11069 /*
11047 11070 * cmd_rfm is zero means the command reply is a CONTEXT
11048 11071 * reply and no PCI Write to post the free reply SMFA
11049 11072 * because no reply message frame is used.
11050 11073 * cmd_rfm is non-zero means the reply is a ADDRESS
11051 11074 * reply and reply message frame is used.
11052 11075 */
11053 11076 pt_flags |= MPTSAS_ADDRESS_REPLY;
11054 11077 (void) ddi_dma_sync(mpt->m_dma_reply_frame_hdl, 0, 0,
11055 11078 DDI_DMA_SYNC_FORCPU);
11056 11079 reply_msg = (pMPI2DefaultReply_t)
11057 11080 (mpt->m_reply_frame + (cmd->cmd_rfm -
11058 11081 (mpt->m_reply_frame_dma_addr & 0xffffffffu)));
11059 11082 }
11060 11083
11061 11084 mptsas_fma_check(mpt, cmd);
11062 11085 if (pkt->pkt_reason == CMD_TRAN_ERR) {
11063 11086 status = EAGAIN;
11064 11087 mptsas_log(mpt, CE_WARN, "passthru fma error");
11065 11088 goto out;
11066 11089 }
11067 11090 if (pkt->pkt_reason == CMD_RESET) {
11068 11091 status = EAGAIN;
11069 11092 mptsas_log(mpt, CE_WARN, "ioc reset abort passthru");
11070 11093 goto out;
11071 11094 }
11072 11095
11073 11096 if (pkt->pkt_reason == CMD_INCOMPLETE) {
11074 11097 status = EIO;
11075 11098 mptsas_log(mpt, CE_WARN, "passthrough command incomplete");
11076 11099 goto out;
11077 11100 }
11078 11101
11079 11102 mutex_exit(&mpt->m_mutex);
11080 11103 if (cmd->cmd_flags & CFLAG_PREPARED) {
11081 11104 function = request_hdrp->Function;
11082 11105 if ((function == MPI2_FUNCTION_SCSI_IO_REQUEST) ||
11083 11106 (function == MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH)) {
11084 11107 reply_len = sizeof (MPI2_SCSI_IO_REPLY);
11085 11108 sense_len = cmd->cmd_extrqslen ?
11086 11109 min(sense_len, cmd->cmd_extrqslen) :
11087 11110 min(sense_len, cmd->cmd_rqslen);
11088 11111 } else {
11089 11112 reply_len = reply_size;
11090 11113 sense_len = 0;
11091 11114 }
11092 11115
11093 11116 for (i = 0; i < reply_len; i++) {
11094 11117 if (ddi_copyout((uint8_t *)reply_msg + i, reply + i, 1,
11095 11118 mode)) {
11096 11119 mutex_enter(&mpt->m_mutex);
11097 11120 status = EFAULT;
11098 11121 mptsas_log(mpt, CE_WARN, "failed to copy out "
11099 11122 "reply data");
11100 11123 goto out;
11101 11124 }
11102 11125 }
11103 11126 for (i = 0; i < sense_len; i++) {
11104 11127 if (ddi_copyout((uint8_t *)request_hdrp + 64 + i,
11105 11128 reply + reply_len + i, 1, mode)) {
11106 11129 mutex_enter(&mpt->m_mutex);
11107 11130 status = EFAULT;
11108 11131 mptsas_log(mpt, CE_WARN, "failed to copy out "
11109 11132 "sense data");
11110 11133 goto out;
11111 11134 }
11112 11135 }
11113 11136 }
11114 11137
11115 11138 if (data_size) {
11116 11139 if (direction != MPTSAS_PASS_THRU_DIRECTION_WRITE) {
11117 11140 (void) ddi_dma_sync(data_dma_state.handle, 0, 0,
11118 11141 DDI_DMA_SYNC_FORCPU);
11119 11142 for (i = 0; i < data_size; i++) {
11120 11143 if (ddi_copyout((uint8_t *)(
11121 11144 data_dma_state.memp + i), data + i, 1,
11122 11145 mode)) {
11123 11146 mutex_enter(&mpt->m_mutex);
11124 11147 status = EFAULT;
11125 11148 mptsas_log(mpt, CE_WARN, "failed to "
11126 11149 "copy out the reply data");
11127 11150 goto out;
11128 11151 }
11129 11152 }
11130 11153 }
11131 11154 }
11132 11155 mutex_enter(&mpt->m_mutex);
11133 11156 out:
11134 11157 /*
11135 11158 * Put the reply frame back on the free queue, increment the free
11136 11159 * index, and write the new index to the free index register. But only
11137 11160 * if this reply is an ADDRESS reply.
11138 11161 */
11139 11162 if (pt_flags & MPTSAS_ADDRESS_REPLY) {
11140 11163 ddi_put32(mpt->m_acc_free_queue_hdl,
11141 11164 &((uint32_t *)(void *)mpt->m_free_queue)[mpt->m_free_index],
11142 11165 cmd->cmd_rfm);
11143 11166 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0,
11144 11167 DDI_DMA_SYNC_FORDEV);
11145 11168 if (++mpt->m_free_index == mpt->m_free_queue_depth) {
11146 11169 mpt->m_free_index = 0;
11147 11170 }
11148 11171 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex,
11149 11172 mpt->m_free_index);
11150 11173 }
11151 11174 if (cmd) {
11152 11175 if (cmd->cmd_extrqslen != 0) {
11153 11176 rmfree(mpt->m_erqsense_map, cmd->cmd_extrqschunks,
11154 11177 cmd->cmd_extrqsidx + 1);
11155 11178 }
11156 11179 if (cmd->cmd_flags & CFLAG_PREPARED) {
11157 11180 mptsas_remove_cmd(mpt, cmd);
11158 11181 pt_flags &= (~MPTSAS_REQUEST_POOL_CMD);
11159 11182 }
11160 11183 }
11161 11184 if (pt_flags & MPTSAS_REQUEST_POOL_CMD)
11162 11185 mptsas_return_to_pool(mpt, cmd);
11163 11186 if (pt_flags & MPTSAS_DATA_ALLOCATED) {
11164 11187 if (mptsas_check_dma_handle(data_dma_state.handle) !=
11165 11188 DDI_SUCCESS) {
11166 11189 ddi_fm_service_impact(mpt->m_dip,
11167 11190 DDI_SERVICE_UNAFFECTED);
11168 11191 status = EFAULT;
11169 11192 }
11170 11193 mptsas_dma_free(&data_dma_state);
11171 11194 }
↓ open down ↓ |
1236 lines elided |
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11172 11195 if (pt_flags & MPTSAS_DATAOUT_ALLOCATED) {
11173 11196 if (mptsas_check_dma_handle(dataout_dma_state.handle) !=
11174 11197 DDI_SUCCESS) {
11175 11198 ddi_fm_service_impact(mpt->m_dip,
11176 11199 DDI_SERVICE_UNAFFECTED);
11177 11200 status = EFAULT;
11178 11201 }
11179 11202 mptsas_dma_free(&dataout_dma_state);
11180 11203 }
11181 11204 if (pt_flags & MPTSAS_CMD_TIMEOUT) {
11182 - if ((mptsas_restart_ioc(mpt)) == DDI_FAILURE) {
11183 - mptsas_log(mpt, CE_WARN, "mptsas_restart_ioc failed");
11205 + if ((mptsas_reset_handler(mpt)) == DDI_FAILURE) {
11206 + mptsas_log(mpt, CE_WARN, "mptsas_reset_handler failed");
11184 11207 }
11185 11208 }
11186 11209 if (request_msg)
11187 11210 kmem_free(request_msg, request_size);
11188 11211 NDBG27(("mptsas_do_passthru: Done status 0x%x", status));
11189 11212
11190 11213 return (status);
11191 11214 }
11192 11215
11193 11216 static int
11194 11217 mptsas_pass_thru(mptsas_t *mpt, mptsas_pass_thru_t *data, int mode)
11195 11218 {
11196 11219 /*
11197 11220 * If timeout is 0, set timeout to default of 60 seconds.
11198 11221 */
11199 11222 if (data->Timeout == 0) {
11200 11223 data->Timeout = MPTSAS_PASS_THRU_TIME_DEFAULT;
11201 11224 }
11202 11225
11203 11226 if (((data->DataSize == 0) &&
11204 11227 (data->DataDirection == MPTSAS_PASS_THRU_DIRECTION_NONE)) ||
11205 11228 ((data->DataSize != 0) &&
11206 11229 ((data->DataDirection == MPTSAS_PASS_THRU_DIRECTION_READ) ||
11207 11230 (data->DataDirection == MPTSAS_PASS_THRU_DIRECTION_WRITE) ||
11208 11231 ((data->DataDirection == MPTSAS_PASS_THRU_DIRECTION_BOTH) &&
11209 11232 (data->DataOutSize != 0))))) {
11210 11233 if (data->DataDirection == MPTSAS_PASS_THRU_DIRECTION_BOTH) {
11211 11234 data->DataDirection = MPTSAS_PASS_THRU_DIRECTION_READ;
11212 11235 } else {
11213 11236 data->DataOutSize = 0;
11214 11237 }
11215 11238 /*
11216 11239 * Send passthru request messages
11217 11240 */
11218 11241 return (mptsas_do_passthru(mpt,
11219 11242 (uint8_t *)((uintptr_t)data->PtrRequest),
11220 11243 (uint8_t *)((uintptr_t)data->PtrReply),
11221 11244 (uint8_t *)((uintptr_t)data->PtrData),
11222 11245 data->RequestSize, data->ReplySize,
11223 11246 data->DataSize, data->DataDirection,
11224 11247 (uint8_t *)((uintptr_t)data->PtrDataOut),
11225 11248 data->DataOutSize, data->Timeout, mode));
11226 11249 } else {
11227 11250 return (EINVAL);
11228 11251 }
11229 11252 }
11230 11253
11231 11254 static uint8_t
11232 11255 mptsas_get_fw_diag_buffer_number(mptsas_t *mpt, uint32_t unique_id)
11233 11256 {
11234 11257 uint8_t index;
11235 11258
11236 11259 for (index = 0; index < MPI2_DIAG_BUF_TYPE_COUNT; index++) {
11237 11260 if (mpt->m_fw_diag_buffer_list[index].unique_id == unique_id) {
11238 11261 return (index);
11239 11262 }
11240 11263 }
11241 11264
11242 11265 return (MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND);
11243 11266 }
11244 11267
11245 11268 static void
11246 11269 mptsas_start_diag(mptsas_t *mpt, mptsas_cmd_t *cmd)
11247 11270 {
11248 11271 pMpi2DiagBufferPostRequest_t pDiag_post_msg;
11249 11272 pMpi2DiagReleaseRequest_t pDiag_release_msg;
11250 11273 struct scsi_pkt *pkt = cmd->cmd_pkt;
11251 11274 mptsas_diag_request_t *diag = pkt->pkt_ha_private;
11252 11275 uint32_t i;
11253 11276 uint64_t request_desc;
11254 11277
11255 11278 ASSERT(mutex_owned(&mpt->m_mutex));
11256 11279
11257 11280 /*
11258 11281 * Form the diag message depending on the post or release function.
11259 11282 */
11260 11283 if (diag->function == MPI2_FUNCTION_DIAG_BUFFER_POST) {
11261 11284 pDiag_post_msg = (pMpi2DiagBufferPostRequest_t)
11262 11285 (mpt->m_req_frame + (mpt->m_req_frame_size *
11263 11286 cmd->cmd_slot));
11264 11287 bzero(pDiag_post_msg, mpt->m_req_frame_size);
11265 11288 ddi_put8(mpt->m_acc_req_frame_hdl, &pDiag_post_msg->Function,
11266 11289 diag->function);
11267 11290 ddi_put8(mpt->m_acc_req_frame_hdl, &pDiag_post_msg->BufferType,
11268 11291 diag->pBuffer->buffer_type);
11269 11292 ddi_put8(mpt->m_acc_req_frame_hdl,
11270 11293 &pDiag_post_msg->ExtendedType,
11271 11294 diag->pBuffer->extended_type);
11272 11295 ddi_put32(mpt->m_acc_req_frame_hdl,
11273 11296 &pDiag_post_msg->BufferLength,
11274 11297 diag->pBuffer->buffer_data.size);
11275 11298 for (i = 0; i < (sizeof (pDiag_post_msg->ProductSpecific) / 4);
11276 11299 i++) {
11277 11300 ddi_put32(mpt->m_acc_req_frame_hdl,
11278 11301 &pDiag_post_msg->ProductSpecific[i],
11279 11302 diag->pBuffer->product_specific[i]);
11280 11303 }
11281 11304 ddi_put32(mpt->m_acc_req_frame_hdl,
11282 11305 &pDiag_post_msg->BufferAddress.Low,
11283 11306 (uint32_t)(diag->pBuffer->buffer_data.cookie.dmac_laddress
11284 11307 & 0xffffffffull));
11285 11308 ddi_put32(mpt->m_acc_req_frame_hdl,
11286 11309 &pDiag_post_msg->BufferAddress.High,
11287 11310 (uint32_t)(diag->pBuffer->buffer_data.cookie.dmac_laddress
11288 11311 >> 32));
11289 11312 } else {
11290 11313 pDiag_release_msg = (pMpi2DiagReleaseRequest_t)
11291 11314 (mpt->m_req_frame + (mpt->m_req_frame_size *
11292 11315 cmd->cmd_slot));
11293 11316 bzero(pDiag_release_msg, mpt->m_req_frame_size);
11294 11317 ddi_put8(mpt->m_acc_req_frame_hdl,
11295 11318 &pDiag_release_msg->Function, diag->function);
11296 11319 ddi_put8(mpt->m_acc_req_frame_hdl,
11297 11320 &pDiag_release_msg->BufferType,
11298 11321 diag->pBuffer->buffer_type);
11299 11322 }
11300 11323
11301 11324 /*
11302 11325 * Send the message
11303 11326 */
11304 11327 (void) ddi_dma_sync(mpt->m_dma_req_frame_hdl, 0, 0,
11305 11328 DDI_DMA_SYNC_FORDEV);
11306 11329 request_desc = (cmd->cmd_slot << 16) +
11307 11330 MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE;
11308 11331 cmd->cmd_rfm = NULL;
11309 11332 MPTSAS_START_CMD(mpt, request_desc);
11310 11333 if ((mptsas_check_dma_handle(mpt->m_dma_req_frame_hdl) !=
11311 11334 DDI_SUCCESS) ||
11312 11335 (mptsas_check_acc_handle(mpt->m_acc_req_frame_hdl) !=
11313 11336 DDI_SUCCESS)) {
11314 11337 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
11315 11338 }
11316 11339 }
11317 11340
11318 11341 static int
11319 11342 mptsas_post_fw_diag_buffer(mptsas_t *mpt,
11320 11343 mptsas_fw_diagnostic_buffer_t *pBuffer, uint32_t *return_code)
11321 11344 {
11322 11345 mptsas_diag_request_t diag;
11323 11346 int status, slot_num, post_flags = 0;
11324 11347 mptsas_cmd_t *cmd = NULL;
11325 11348 struct scsi_pkt *pkt;
11326 11349 pMpi2DiagBufferPostReply_t reply;
11327 11350 uint16_t iocstatus;
11328 11351 uint32_t iocloginfo, transfer_length;
11329 11352
11330 11353 /*
11331 11354 * If buffer is not enabled, just leave.
11332 11355 */
11333 11356 *return_code = MPTSAS_FW_DIAG_ERROR_POST_FAILED;
11334 11357 if (!pBuffer->enabled) {
11335 11358 status = DDI_FAILURE;
11336 11359 goto out;
11337 11360 }
11338 11361
11339 11362 /*
11340 11363 * Clear some flags initially.
11341 11364 */
11342 11365 pBuffer->force_release = FALSE;
11343 11366 pBuffer->valid_data = FALSE;
11344 11367 pBuffer->owned_by_firmware = FALSE;
11345 11368
11346 11369 /*
11347 11370 * Get a cmd buffer from the cmd buffer pool
11348 11371 */
11349 11372 if ((slot_num = (mptsas_request_from_pool(mpt, &cmd, &pkt))) == -1) {
11350 11373 status = DDI_FAILURE;
11351 11374 mptsas_log(mpt, CE_NOTE, "command pool is full: Post FW Diag");
11352 11375 goto out;
11353 11376 }
11354 11377 post_flags |= MPTSAS_REQUEST_POOL_CMD;
11355 11378
11356 11379 bzero((caddr_t)cmd, sizeof (*cmd));
11357 11380 bzero((caddr_t)pkt, scsi_pkt_size());
11358 11381
11359 11382 cmd->ioc_cmd_slot = (uint32_t)(slot_num);
11360 11383
11361 11384 diag.pBuffer = pBuffer;
11362 11385 diag.function = MPI2_FUNCTION_DIAG_BUFFER_POST;
11363 11386
11364 11387 /*
11365 11388 * Form a blank cmd/pkt to store the acknowledgement message
11366 11389 */
11367 11390 pkt->pkt_ha_private = (opaque_t)&diag;
11368 11391 pkt->pkt_flags = FLAG_HEAD;
11369 11392 pkt->pkt_time = 60;
11370 11393 cmd->cmd_pkt = pkt;
11371 11394 cmd->cmd_flags = CFLAG_CMDIOC | CFLAG_FW_DIAG;
11372 11395
11373 11396 /*
11374 11397 * Save the command in a slot
11375 11398 */
11376 11399 if (mptsas_save_cmd(mpt, cmd) == TRUE) {
11377 11400 /*
11378 11401 * Once passthru command get slot, set cmd_flags
11379 11402 * CFLAG_PREPARED.
11380 11403 */
11381 11404 cmd->cmd_flags |= CFLAG_PREPARED;
11382 11405 mptsas_start_diag(mpt, cmd);
11383 11406 } else {
11384 11407 mptsas_waitq_add(mpt, cmd);
11385 11408 }
11386 11409
11387 11410 while ((cmd->cmd_flags & CFLAG_FINISHED) == 0) {
11388 11411 cv_wait(&mpt->m_fw_diag_cv, &mpt->m_mutex);
11389 11412 }
11390 11413
11391 11414 if (cmd->cmd_flags & CFLAG_TIMEOUT) {
11392 11415 status = DDI_FAILURE;
11393 11416 mptsas_log(mpt, CE_WARN, "Post FW Diag command timeout");
11394 11417 goto out;
11395 11418 }
11396 11419
11397 11420 /*
11398 11421 * cmd_rfm points to the reply message if a reply was given. Check the
11399 11422 * IOCStatus to make sure everything went OK with the FW diag request
11400 11423 * and set buffer flags.
11401 11424 */
11402 11425 if (cmd->cmd_rfm) {
11403 11426 post_flags |= MPTSAS_ADDRESS_REPLY;
11404 11427 (void) ddi_dma_sync(mpt->m_dma_reply_frame_hdl, 0, 0,
11405 11428 DDI_DMA_SYNC_FORCPU);
11406 11429 reply = (pMpi2DiagBufferPostReply_t)(mpt->m_reply_frame +
11407 11430 (cmd->cmd_rfm -
11408 11431 (mpt->m_reply_frame_dma_addr & 0xffffffffu)));
11409 11432
11410 11433 /*
11411 11434 * Get the reply message data
11412 11435 */
11413 11436 iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl,
11414 11437 &reply->IOCStatus);
11415 11438 iocloginfo = ddi_get32(mpt->m_acc_reply_frame_hdl,
11416 11439 &reply->IOCLogInfo);
11417 11440 transfer_length = ddi_get32(mpt->m_acc_reply_frame_hdl,
11418 11441 &reply->TransferLength);
11419 11442
11420 11443 /*
11421 11444 * If post failed quit.
11422 11445 */
11423 11446 if (iocstatus != MPI2_IOCSTATUS_SUCCESS) {
11424 11447 status = DDI_FAILURE;
11425 11448 NDBG13(("post FW Diag Buffer failed: IOCStatus=0x%x, "
11426 11449 "IOCLogInfo=0x%x, TransferLength=0x%x", iocstatus,
11427 11450 iocloginfo, transfer_length));
11428 11451 goto out;
11429 11452 }
11430 11453
11431 11454 /*
11432 11455 * Post was successful.
11433 11456 */
11434 11457 pBuffer->valid_data = TRUE;
11435 11458 pBuffer->owned_by_firmware = TRUE;
11436 11459 *return_code = MPTSAS_FW_DIAG_ERROR_SUCCESS;
11437 11460 status = DDI_SUCCESS;
11438 11461 }
11439 11462
11440 11463 out:
11441 11464 /*
11442 11465 * Put the reply frame back on the free queue, increment the free
11443 11466 * index, and write the new index to the free index register. But only
11444 11467 * if this reply is an ADDRESS reply.
11445 11468 */
11446 11469 if (post_flags & MPTSAS_ADDRESS_REPLY) {
11447 11470 ddi_put32(mpt->m_acc_free_queue_hdl,
11448 11471 &((uint32_t *)(void *)mpt->m_free_queue)[mpt->m_free_index],
11449 11472 cmd->cmd_rfm);
11450 11473 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0,
11451 11474 DDI_DMA_SYNC_FORDEV);
11452 11475 if (++mpt->m_free_index == mpt->m_free_queue_depth) {
11453 11476 mpt->m_free_index = 0;
11454 11477 }
11455 11478 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex,
11456 11479 mpt->m_free_index);
11457 11480 }
11458 11481 if (cmd && (cmd->cmd_flags & CFLAG_PREPARED)) {
11459 11482 mptsas_remove_cmd(mpt, cmd);
11460 11483 post_flags &= (~MPTSAS_REQUEST_POOL_CMD);
11461 11484 }
11462 11485 if (post_flags & MPTSAS_REQUEST_POOL_CMD) {
11463 11486 mptsas_return_to_pool(mpt, cmd);
11464 11487 }
11465 11488
11466 11489 return (status);
11467 11490 }
11468 11491
11469 11492 static int
11470 11493 mptsas_release_fw_diag_buffer(mptsas_t *mpt,
11471 11494 mptsas_fw_diagnostic_buffer_t *pBuffer, uint32_t *return_code,
11472 11495 uint32_t diag_type)
11473 11496 {
11474 11497 mptsas_diag_request_t diag;
11475 11498 int status, slot_num, rel_flags = 0;
11476 11499 mptsas_cmd_t *cmd = NULL;
11477 11500 struct scsi_pkt *pkt;
11478 11501 pMpi2DiagReleaseReply_t reply;
11479 11502 uint16_t iocstatus;
11480 11503 uint32_t iocloginfo;
11481 11504
11482 11505 /*
11483 11506 * If buffer is not enabled, just leave.
11484 11507 */
11485 11508 *return_code = MPTSAS_FW_DIAG_ERROR_RELEASE_FAILED;
11486 11509 if (!pBuffer->enabled) {
11487 11510 mptsas_log(mpt, CE_NOTE, "This buffer type is not supported "
11488 11511 "by the IOC");
11489 11512 status = DDI_FAILURE;
11490 11513 goto out;
11491 11514 }
11492 11515
11493 11516 /*
11494 11517 * Clear some flags initially.
11495 11518 */
11496 11519 pBuffer->force_release = FALSE;
11497 11520 pBuffer->valid_data = FALSE;
11498 11521 pBuffer->owned_by_firmware = FALSE;
11499 11522
11500 11523 /*
11501 11524 * Get a cmd buffer from the cmd buffer pool
11502 11525 */
11503 11526 if ((slot_num = (mptsas_request_from_pool(mpt, &cmd, &pkt))) == -1) {
11504 11527 status = DDI_FAILURE;
11505 11528 mptsas_log(mpt, CE_NOTE, "command pool is full: Release FW "
11506 11529 "Diag");
11507 11530 goto out;
11508 11531 }
11509 11532 rel_flags |= MPTSAS_REQUEST_POOL_CMD;
11510 11533
11511 11534 bzero((caddr_t)cmd, sizeof (*cmd));
11512 11535 bzero((caddr_t)pkt, scsi_pkt_size());
11513 11536
11514 11537 cmd->ioc_cmd_slot = (uint32_t)(slot_num);
11515 11538
11516 11539 diag.pBuffer = pBuffer;
11517 11540 diag.function = MPI2_FUNCTION_DIAG_RELEASE;
11518 11541
11519 11542 /*
11520 11543 * Form a blank cmd/pkt to store the acknowledgement message
11521 11544 */
11522 11545 pkt->pkt_ha_private = (opaque_t)&diag;
11523 11546 pkt->pkt_flags = FLAG_HEAD;
11524 11547 pkt->pkt_time = 60;
11525 11548 cmd->cmd_pkt = pkt;
11526 11549 cmd->cmd_flags = CFLAG_CMDIOC | CFLAG_FW_DIAG;
11527 11550
11528 11551 /*
11529 11552 * Save the command in a slot
11530 11553 */
11531 11554 if (mptsas_save_cmd(mpt, cmd) == TRUE) {
11532 11555 /*
11533 11556 * Once passthru command get slot, set cmd_flags
11534 11557 * CFLAG_PREPARED.
11535 11558 */
11536 11559 cmd->cmd_flags |= CFLAG_PREPARED;
11537 11560 mptsas_start_diag(mpt, cmd);
11538 11561 } else {
11539 11562 mptsas_waitq_add(mpt, cmd);
11540 11563 }
11541 11564
11542 11565 while ((cmd->cmd_flags & CFLAG_FINISHED) == 0) {
11543 11566 cv_wait(&mpt->m_fw_diag_cv, &mpt->m_mutex);
11544 11567 }
11545 11568
11546 11569 if (cmd->cmd_flags & CFLAG_TIMEOUT) {
11547 11570 status = DDI_FAILURE;
11548 11571 mptsas_log(mpt, CE_WARN, "Release FW Diag command timeout");
11549 11572 goto out;
11550 11573 }
11551 11574
11552 11575 /*
11553 11576 * cmd_rfm points to the reply message if a reply was given. Check the
11554 11577 * IOCStatus to make sure everything went OK with the FW diag request
11555 11578 * and set buffer flags.
11556 11579 */
11557 11580 if (cmd->cmd_rfm) {
11558 11581 rel_flags |= MPTSAS_ADDRESS_REPLY;
11559 11582 (void) ddi_dma_sync(mpt->m_dma_reply_frame_hdl, 0, 0,
11560 11583 DDI_DMA_SYNC_FORCPU);
11561 11584 reply = (pMpi2DiagReleaseReply_t)(mpt->m_reply_frame +
11562 11585 (cmd->cmd_rfm -
11563 11586 (mpt->m_reply_frame_dma_addr & 0xffffffffu)));
11564 11587
11565 11588 /*
11566 11589 * Get the reply message data
11567 11590 */
11568 11591 iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl,
11569 11592 &reply->IOCStatus);
11570 11593 iocloginfo = ddi_get32(mpt->m_acc_reply_frame_hdl,
11571 11594 &reply->IOCLogInfo);
11572 11595
11573 11596 /*
11574 11597 * If release failed quit.
11575 11598 */
11576 11599 if ((iocstatus != MPI2_IOCSTATUS_SUCCESS) ||
11577 11600 pBuffer->owned_by_firmware) {
11578 11601 status = DDI_FAILURE;
11579 11602 NDBG13(("release FW Diag Buffer failed: "
11580 11603 "IOCStatus=0x%x, IOCLogInfo=0x%x", iocstatus,
11581 11604 iocloginfo));
11582 11605 goto out;
11583 11606 }
11584 11607
11585 11608 /*
11586 11609 * Release was successful.
11587 11610 */
11588 11611 *return_code = MPTSAS_FW_DIAG_ERROR_SUCCESS;
11589 11612 status = DDI_SUCCESS;
11590 11613
11591 11614 /*
11592 11615 * If this was for an UNREGISTER diag type command, clear the
11593 11616 * unique ID.
11594 11617 */
11595 11618 if (diag_type == MPTSAS_FW_DIAG_TYPE_UNREGISTER) {
11596 11619 pBuffer->unique_id = MPTSAS_FW_DIAG_INVALID_UID;
11597 11620 }
11598 11621 }
11599 11622
11600 11623 out:
11601 11624 /*
11602 11625 * Put the reply frame back on the free queue, increment the free
11603 11626 * index, and write the new index to the free index register. But only
11604 11627 * if this reply is an ADDRESS reply.
11605 11628 */
11606 11629 if (rel_flags & MPTSAS_ADDRESS_REPLY) {
11607 11630 ddi_put32(mpt->m_acc_free_queue_hdl,
11608 11631 &((uint32_t *)(void *)mpt->m_free_queue)[mpt->m_free_index],
11609 11632 cmd->cmd_rfm);
11610 11633 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0,
11611 11634 DDI_DMA_SYNC_FORDEV);
11612 11635 if (++mpt->m_free_index == mpt->m_free_queue_depth) {
11613 11636 mpt->m_free_index = 0;
11614 11637 }
11615 11638 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex,
11616 11639 mpt->m_free_index);
11617 11640 }
11618 11641 if (cmd && (cmd->cmd_flags & CFLAG_PREPARED)) {
11619 11642 mptsas_remove_cmd(mpt, cmd);
11620 11643 rel_flags &= (~MPTSAS_REQUEST_POOL_CMD);
11621 11644 }
11622 11645 if (rel_flags & MPTSAS_REQUEST_POOL_CMD) {
11623 11646 mptsas_return_to_pool(mpt, cmd);
11624 11647 }
11625 11648
11626 11649 return (status);
11627 11650 }
11628 11651
11629 11652 static int
11630 11653 mptsas_diag_register(mptsas_t *mpt, mptsas_fw_diag_register_t *diag_register,
11631 11654 uint32_t *return_code)
11632 11655 {
11633 11656 mptsas_fw_diagnostic_buffer_t *pBuffer;
11634 11657 uint8_t extended_type, buffer_type, i;
11635 11658 uint32_t buffer_size;
11636 11659 uint32_t unique_id;
11637 11660 int status;
11638 11661
11639 11662 ASSERT(mutex_owned(&mpt->m_mutex));
11640 11663
11641 11664 extended_type = diag_register->ExtendedType;
11642 11665 buffer_type = diag_register->BufferType;
11643 11666 buffer_size = diag_register->RequestedBufferSize;
11644 11667 unique_id = diag_register->UniqueId;
11645 11668
11646 11669 /*
11647 11670 * Check for valid buffer type
11648 11671 */
11649 11672 if (buffer_type >= MPI2_DIAG_BUF_TYPE_COUNT) {
11650 11673 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER;
11651 11674 return (DDI_FAILURE);
11652 11675 }
11653 11676
11654 11677 /*
11655 11678 * Get the current buffer and look up the unique ID. The unique ID
11656 11679 * should not be found. If it is, the ID is already in use.
11657 11680 */
11658 11681 i = mptsas_get_fw_diag_buffer_number(mpt, unique_id);
11659 11682 pBuffer = &mpt->m_fw_diag_buffer_list[buffer_type];
11660 11683 if (i != MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND) {
11661 11684 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID;
11662 11685 return (DDI_FAILURE);
11663 11686 }
11664 11687
11665 11688 /*
11666 11689 * The buffer's unique ID should not be registered yet, and the given
11667 11690 * unique ID cannot be 0.
11668 11691 */
11669 11692 if ((pBuffer->unique_id != MPTSAS_FW_DIAG_INVALID_UID) ||
11670 11693 (unique_id == MPTSAS_FW_DIAG_INVALID_UID)) {
11671 11694 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID;
11672 11695 return (DDI_FAILURE);
11673 11696 }
11674 11697
11675 11698 /*
11676 11699 * If this buffer is already posted as immediate, just change owner.
11677 11700 */
11678 11701 if (pBuffer->immediate && pBuffer->owned_by_firmware &&
11679 11702 (pBuffer->unique_id == MPTSAS_FW_DIAG_INVALID_UID)) {
11680 11703 pBuffer->immediate = FALSE;
11681 11704 pBuffer->unique_id = unique_id;
11682 11705 return (DDI_SUCCESS);
11683 11706 }
11684 11707
11685 11708 /*
11686 11709 * Post a new buffer after checking if it's enabled. The DMA buffer
11687 11710 * that is allocated will be contiguous (sgl_len = 1).
11688 11711 */
11689 11712 if (!pBuffer->enabled) {
11690 11713 *return_code = MPTSAS_FW_DIAG_ERROR_NO_BUFFER;
11691 11714 return (DDI_FAILURE);
11692 11715 }
11693 11716 bzero(&pBuffer->buffer_data, sizeof (mptsas_dma_alloc_state_t));
11694 11717 pBuffer->buffer_data.size = buffer_size;
11695 11718 if (mptsas_dma_alloc(mpt, &pBuffer->buffer_data) != DDI_SUCCESS) {
11696 11719 mptsas_log(mpt, CE_WARN, "failed to alloc DMA resource for "
11697 11720 "diag buffer: size = %d bytes", buffer_size);
11698 11721 *return_code = MPTSAS_FW_DIAG_ERROR_NO_BUFFER;
11699 11722 return (DDI_FAILURE);
11700 11723 }
11701 11724
11702 11725 /*
11703 11726 * Copy the given info to the diag buffer and post the buffer.
11704 11727 */
11705 11728 pBuffer->buffer_type = buffer_type;
11706 11729 pBuffer->immediate = FALSE;
11707 11730 if (buffer_type == MPI2_DIAG_BUF_TYPE_TRACE) {
11708 11731 for (i = 0; i < (sizeof (pBuffer->product_specific) / 4);
11709 11732 i++) {
11710 11733 pBuffer->product_specific[i] =
11711 11734 diag_register->ProductSpecific[i];
11712 11735 }
11713 11736 }
11714 11737 pBuffer->extended_type = extended_type;
11715 11738 pBuffer->unique_id = unique_id;
11716 11739 status = mptsas_post_fw_diag_buffer(mpt, pBuffer, return_code);
11717 11740
11718 11741 if (mptsas_check_dma_handle(pBuffer->buffer_data.handle) !=
11719 11742 DDI_SUCCESS) {
11720 11743 mptsas_log(mpt, CE_WARN, "Check of DMA handle failed in "
11721 11744 "mptsas_diag_register.");
11722 11745 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
11723 11746 status = DDI_FAILURE;
11724 11747 }
11725 11748
11726 11749 /*
11727 11750 * In case there was a failure, free the DMA buffer.
11728 11751 */
11729 11752 if (status == DDI_FAILURE) {
11730 11753 mptsas_dma_free(&pBuffer->buffer_data);
11731 11754 }
11732 11755
11733 11756 return (status);
11734 11757 }
11735 11758
11736 11759 static int
11737 11760 mptsas_diag_unregister(mptsas_t *mpt,
11738 11761 mptsas_fw_diag_unregister_t *diag_unregister, uint32_t *return_code)
11739 11762 {
11740 11763 mptsas_fw_diagnostic_buffer_t *pBuffer;
11741 11764 uint8_t i;
11742 11765 uint32_t unique_id;
11743 11766 int status;
11744 11767
11745 11768 ASSERT(mutex_owned(&mpt->m_mutex));
11746 11769
11747 11770 unique_id = diag_unregister->UniqueId;
11748 11771
11749 11772 /*
11750 11773 * Get the current buffer and look up the unique ID. The unique ID
11751 11774 * should be there.
11752 11775 */
11753 11776 i = mptsas_get_fw_diag_buffer_number(mpt, unique_id);
11754 11777 if (i == MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND) {
11755 11778 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID;
11756 11779 return (DDI_FAILURE);
11757 11780 }
11758 11781
11759 11782 pBuffer = &mpt->m_fw_diag_buffer_list[i];
11760 11783
11761 11784 /*
11762 11785 * Try to release the buffer from FW before freeing it. If release
11763 11786 * fails, don't free the DMA buffer in case FW tries to access it
11764 11787 * later. If buffer is not owned by firmware, can't release it.
11765 11788 */
11766 11789 if (!pBuffer->owned_by_firmware) {
11767 11790 status = DDI_SUCCESS;
11768 11791 } else {
11769 11792 status = mptsas_release_fw_diag_buffer(mpt, pBuffer,
11770 11793 return_code, MPTSAS_FW_DIAG_TYPE_UNREGISTER);
11771 11794 }
11772 11795
11773 11796 /*
11774 11797 * At this point, return the current status no matter what happens with
11775 11798 * the DMA buffer.
11776 11799 */
11777 11800 pBuffer->unique_id = MPTSAS_FW_DIAG_INVALID_UID;
11778 11801 if (status == DDI_SUCCESS) {
11779 11802 if (mptsas_check_dma_handle(pBuffer->buffer_data.handle) !=
11780 11803 DDI_SUCCESS) {
11781 11804 mptsas_log(mpt, CE_WARN, "Check of DMA handle failed "
11782 11805 "in mptsas_diag_unregister.");
11783 11806 ddi_fm_service_impact(mpt->m_dip,
11784 11807 DDI_SERVICE_UNAFFECTED);
11785 11808 }
11786 11809 mptsas_dma_free(&pBuffer->buffer_data);
11787 11810 }
11788 11811
11789 11812 return (status);
11790 11813 }
11791 11814
11792 11815 static int
11793 11816 mptsas_diag_query(mptsas_t *mpt, mptsas_fw_diag_query_t *diag_query,
11794 11817 uint32_t *return_code)
11795 11818 {
11796 11819 mptsas_fw_diagnostic_buffer_t *pBuffer;
11797 11820 uint8_t i;
11798 11821 uint32_t unique_id;
11799 11822
11800 11823 ASSERT(mutex_owned(&mpt->m_mutex));
11801 11824
11802 11825 unique_id = diag_query->UniqueId;
11803 11826
11804 11827 /*
11805 11828 * If ID is valid, query on ID.
11806 11829 * If ID is invalid, query on buffer type.
11807 11830 */
11808 11831 if (unique_id == MPTSAS_FW_DIAG_INVALID_UID) {
11809 11832 i = diag_query->BufferType;
11810 11833 if (i >= MPI2_DIAG_BUF_TYPE_COUNT) {
11811 11834 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID;
11812 11835 return (DDI_FAILURE);
11813 11836 }
11814 11837 } else {
11815 11838 i = mptsas_get_fw_diag_buffer_number(mpt, unique_id);
11816 11839 if (i == MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND) {
11817 11840 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID;
11818 11841 return (DDI_FAILURE);
11819 11842 }
11820 11843 }
11821 11844
11822 11845 /*
11823 11846 * Fill query structure with the diag buffer info.
11824 11847 */
11825 11848 pBuffer = &mpt->m_fw_diag_buffer_list[i];
11826 11849 diag_query->BufferType = pBuffer->buffer_type;
11827 11850 diag_query->ExtendedType = pBuffer->extended_type;
11828 11851 if (diag_query->BufferType == MPI2_DIAG_BUF_TYPE_TRACE) {
11829 11852 for (i = 0; i < (sizeof (diag_query->ProductSpecific) / 4);
11830 11853 i++) {
11831 11854 diag_query->ProductSpecific[i] =
11832 11855 pBuffer->product_specific[i];
11833 11856 }
11834 11857 }
11835 11858 diag_query->TotalBufferSize = pBuffer->buffer_data.size;
11836 11859 diag_query->DriverAddedBufferSize = 0;
11837 11860 diag_query->UniqueId = pBuffer->unique_id;
11838 11861 diag_query->ApplicationFlags = 0;
11839 11862 diag_query->DiagnosticFlags = 0;
11840 11863
11841 11864 /*
11842 11865 * Set/Clear application flags
11843 11866 */
11844 11867 if (pBuffer->immediate) {
11845 11868 diag_query->ApplicationFlags &= ~MPTSAS_FW_DIAG_FLAG_APP_OWNED;
11846 11869 } else {
11847 11870 diag_query->ApplicationFlags |= MPTSAS_FW_DIAG_FLAG_APP_OWNED;
11848 11871 }
11849 11872 if (pBuffer->valid_data || pBuffer->owned_by_firmware) {
11850 11873 diag_query->ApplicationFlags |=
11851 11874 MPTSAS_FW_DIAG_FLAG_BUFFER_VALID;
11852 11875 } else {
11853 11876 diag_query->ApplicationFlags &=
11854 11877 ~MPTSAS_FW_DIAG_FLAG_BUFFER_VALID;
11855 11878 }
11856 11879 if (pBuffer->owned_by_firmware) {
11857 11880 diag_query->ApplicationFlags |=
11858 11881 MPTSAS_FW_DIAG_FLAG_FW_BUFFER_ACCESS;
11859 11882 } else {
11860 11883 diag_query->ApplicationFlags &=
11861 11884 ~MPTSAS_FW_DIAG_FLAG_FW_BUFFER_ACCESS;
11862 11885 }
11863 11886
11864 11887 return (DDI_SUCCESS);
11865 11888 }
11866 11889
11867 11890 static int
11868 11891 mptsas_diag_read_buffer(mptsas_t *mpt,
11869 11892 mptsas_diag_read_buffer_t *diag_read_buffer, uint8_t *ioctl_buf,
11870 11893 uint32_t *return_code, int ioctl_mode)
11871 11894 {
11872 11895 mptsas_fw_diagnostic_buffer_t *pBuffer;
11873 11896 uint8_t i, *pData;
11874 11897 uint32_t unique_id, byte;
11875 11898 int status;
11876 11899
11877 11900 ASSERT(mutex_owned(&mpt->m_mutex));
11878 11901
11879 11902 unique_id = diag_read_buffer->UniqueId;
11880 11903
11881 11904 /*
11882 11905 * Get the current buffer and look up the unique ID. The unique ID
11883 11906 * should be there.
11884 11907 */
11885 11908 i = mptsas_get_fw_diag_buffer_number(mpt, unique_id);
11886 11909 if (i == MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND) {
11887 11910 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID;
11888 11911 return (DDI_FAILURE);
11889 11912 }
11890 11913
11891 11914 pBuffer = &mpt->m_fw_diag_buffer_list[i];
11892 11915
11893 11916 /*
11894 11917 * Make sure requested read is within limits
11895 11918 */
11896 11919 if (diag_read_buffer->StartingOffset + diag_read_buffer->BytesToRead >
11897 11920 pBuffer->buffer_data.size) {
11898 11921 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER;
11899 11922 return (DDI_FAILURE);
11900 11923 }
11901 11924
11902 11925 /*
11903 11926 * Copy the requested data from DMA to the diag_read_buffer. The DMA
11904 11927 * buffer that was allocated is one contiguous buffer.
11905 11928 */
11906 11929 pData = (uint8_t *)(pBuffer->buffer_data.memp +
11907 11930 diag_read_buffer->StartingOffset);
11908 11931 (void) ddi_dma_sync(pBuffer->buffer_data.handle, 0, 0,
11909 11932 DDI_DMA_SYNC_FORCPU);
11910 11933 for (byte = 0; byte < diag_read_buffer->BytesToRead; byte++) {
11911 11934 if (ddi_copyout(pData + byte, ioctl_buf + byte, 1, ioctl_mode)
11912 11935 != 0) {
11913 11936 return (DDI_FAILURE);
11914 11937 }
11915 11938 }
11916 11939 diag_read_buffer->Status = 0;
11917 11940
11918 11941 /*
11919 11942 * Set or clear the Force Release flag.
11920 11943 */
11921 11944 if (pBuffer->force_release) {
11922 11945 diag_read_buffer->Flags |= MPTSAS_FW_DIAG_FLAG_FORCE_RELEASE;
11923 11946 } else {
11924 11947 diag_read_buffer->Flags &= ~MPTSAS_FW_DIAG_FLAG_FORCE_RELEASE;
11925 11948 }
11926 11949
11927 11950 /*
11928 11951 * If buffer is to be reregistered, make sure it's not already owned by
11929 11952 * firmware first.
11930 11953 */
11931 11954 status = DDI_SUCCESS;
11932 11955 if (!pBuffer->owned_by_firmware) {
11933 11956 if (diag_read_buffer->Flags & MPTSAS_FW_DIAG_FLAG_REREGISTER) {
11934 11957 status = mptsas_post_fw_diag_buffer(mpt, pBuffer,
11935 11958 return_code);
11936 11959 }
11937 11960 }
11938 11961
11939 11962 return (status);
11940 11963 }
11941 11964
11942 11965 static int
11943 11966 mptsas_diag_release(mptsas_t *mpt, mptsas_fw_diag_release_t *diag_release,
11944 11967 uint32_t *return_code)
11945 11968 {
11946 11969 mptsas_fw_diagnostic_buffer_t *pBuffer;
11947 11970 uint8_t i;
11948 11971 uint32_t unique_id;
11949 11972 int status;
11950 11973
11951 11974 ASSERT(mutex_owned(&mpt->m_mutex));
11952 11975
11953 11976 unique_id = diag_release->UniqueId;
11954 11977
11955 11978 /*
11956 11979 * Get the current buffer and look up the unique ID. The unique ID
11957 11980 * should be there.
11958 11981 */
11959 11982 i = mptsas_get_fw_diag_buffer_number(mpt, unique_id);
11960 11983 if (i == MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND) {
11961 11984 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID;
11962 11985 return (DDI_FAILURE);
11963 11986 }
11964 11987
11965 11988 pBuffer = &mpt->m_fw_diag_buffer_list[i];
11966 11989
11967 11990 /*
11968 11991 * If buffer is not owned by firmware, it's already been released.
11969 11992 */
11970 11993 if (!pBuffer->owned_by_firmware) {
11971 11994 *return_code = MPTSAS_FW_DIAG_ERROR_ALREADY_RELEASED;
11972 11995 return (DDI_FAILURE);
11973 11996 }
11974 11997
11975 11998 /*
11976 11999 * Release the buffer.
11977 12000 */
11978 12001 status = mptsas_release_fw_diag_buffer(mpt, pBuffer, return_code,
11979 12002 MPTSAS_FW_DIAG_TYPE_RELEASE);
11980 12003 return (status);
11981 12004 }
11982 12005
11983 12006 static int
11984 12007 mptsas_do_diag_action(mptsas_t *mpt, uint32_t action, uint8_t *diag_action,
11985 12008 uint32_t length, uint32_t *return_code, int ioctl_mode)
11986 12009 {
11987 12010 mptsas_fw_diag_register_t diag_register;
11988 12011 mptsas_fw_diag_unregister_t diag_unregister;
11989 12012 mptsas_fw_diag_query_t diag_query;
11990 12013 mptsas_diag_read_buffer_t diag_read_buffer;
11991 12014 mptsas_fw_diag_release_t diag_release;
11992 12015 int status = DDI_SUCCESS;
11993 12016 uint32_t original_return_code, read_buf_len;
11994 12017
11995 12018 ASSERT(mutex_owned(&mpt->m_mutex));
11996 12019
11997 12020 original_return_code = *return_code;
11998 12021 *return_code = MPTSAS_FW_DIAG_ERROR_SUCCESS;
11999 12022
12000 12023 switch (action) {
12001 12024 case MPTSAS_FW_DIAG_TYPE_REGISTER:
12002 12025 if (!length) {
12003 12026 *return_code =
12004 12027 MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER;
12005 12028 status = DDI_FAILURE;
12006 12029 break;
12007 12030 }
12008 12031 if (ddi_copyin(diag_action, &diag_register,
12009 12032 sizeof (diag_register), ioctl_mode) != 0) {
12010 12033 return (DDI_FAILURE);
12011 12034 }
12012 12035 status = mptsas_diag_register(mpt, &diag_register,
12013 12036 return_code);
12014 12037 break;
12015 12038
12016 12039 case MPTSAS_FW_DIAG_TYPE_UNREGISTER:
12017 12040 if (length < sizeof (diag_unregister)) {
12018 12041 *return_code =
12019 12042 MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER;
12020 12043 status = DDI_FAILURE;
12021 12044 break;
12022 12045 }
12023 12046 if (ddi_copyin(diag_action, &diag_unregister,
12024 12047 sizeof (diag_unregister), ioctl_mode) != 0) {
12025 12048 return (DDI_FAILURE);
12026 12049 }
12027 12050 status = mptsas_diag_unregister(mpt, &diag_unregister,
12028 12051 return_code);
12029 12052 break;
12030 12053
12031 12054 case MPTSAS_FW_DIAG_TYPE_QUERY:
12032 12055 if (length < sizeof (diag_query)) {
12033 12056 *return_code =
12034 12057 MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER;
12035 12058 status = DDI_FAILURE;
12036 12059 break;
12037 12060 }
12038 12061 if (ddi_copyin(diag_action, &diag_query,
12039 12062 sizeof (diag_query), ioctl_mode) != 0) {
12040 12063 return (DDI_FAILURE);
12041 12064 }
12042 12065 status = mptsas_diag_query(mpt, &diag_query,
12043 12066 return_code);
12044 12067 if (status == DDI_SUCCESS) {
12045 12068 if (ddi_copyout(&diag_query, diag_action,
12046 12069 sizeof (diag_query), ioctl_mode) != 0) {
12047 12070 return (DDI_FAILURE);
12048 12071 }
12049 12072 }
12050 12073 break;
12051 12074
12052 12075 case MPTSAS_FW_DIAG_TYPE_READ_BUFFER:
12053 12076 if (ddi_copyin(diag_action, &diag_read_buffer,
12054 12077 sizeof (diag_read_buffer) - 4, ioctl_mode) != 0) {
12055 12078 return (DDI_FAILURE);
12056 12079 }
12057 12080 read_buf_len = sizeof (diag_read_buffer) -
12058 12081 sizeof (diag_read_buffer.DataBuffer) +
12059 12082 diag_read_buffer.BytesToRead;
12060 12083 if (length < read_buf_len) {
12061 12084 *return_code =
12062 12085 MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER;
12063 12086 status = DDI_FAILURE;
12064 12087 break;
12065 12088 }
12066 12089 status = mptsas_diag_read_buffer(mpt,
12067 12090 &diag_read_buffer, diag_action +
12068 12091 sizeof (diag_read_buffer) - 4, return_code,
12069 12092 ioctl_mode);
12070 12093 if (status == DDI_SUCCESS) {
12071 12094 if (ddi_copyout(&diag_read_buffer, diag_action,
12072 12095 sizeof (diag_read_buffer) - 4, ioctl_mode)
12073 12096 != 0) {
12074 12097 return (DDI_FAILURE);
12075 12098 }
12076 12099 }
12077 12100 break;
12078 12101
12079 12102 case MPTSAS_FW_DIAG_TYPE_RELEASE:
12080 12103 if (length < sizeof (diag_release)) {
12081 12104 *return_code =
12082 12105 MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER;
12083 12106 status = DDI_FAILURE;
12084 12107 break;
12085 12108 }
12086 12109 if (ddi_copyin(diag_action, &diag_release,
12087 12110 sizeof (diag_release), ioctl_mode) != 0) {
12088 12111 return (DDI_FAILURE);
12089 12112 }
12090 12113 status = mptsas_diag_release(mpt, &diag_release,
12091 12114 return_code);
12092 12115 break;
12093 12116
12094 12117 default:
12095 12118 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER;
12096 12119 status = DDI_FAILURE;
12097 12120 break;
12098 12121 }
12099 12122
12100 12123 if ((status == DDI_FAILURE) &&
12101 12124 (original_return_code == MPTSAS_FW_DIAG_NEW) &&
12102 12125 (*return_code != MPTSAS_FW_DIAG_ERROR_SUCCESS)) {
12103 12126 status = DDI_SUCCESS;
12104 12127 }
12105 12128
12106 12129 return (status);
12107 12130 }
12108 12131
12109 12132 static int
12110 12133 mptsas_diag_action(mptsas_t *mpt, mptsas_diag_action_t *user_data, int mode)
12111 12134 {
12112 12135 int status;
12113 12136 mptsas_diag_action_t driver_data;
12114 12137
12115 12138 ASSERT(mutex_owned(&mpt->m_mutex));
12116 12139
12117 12140 /*
12118 12141 * Copy the user data to a driver data buffer.
12119 12142 */
12120 12143 if (ddi_copyin(user_data, &driver_data, sizeof (mptsas_diag_action_t),
12121 12144 mode) == 0) {
12122 12145 /*
12123 12146 * Send diag action request if Action is valid
12124 12147 */
12125 12148 if (driver_data.Action == MPTSAS_FW_DIAG_TYPE_REGISTER ||
12126 12149 driver_data.Action == MPTSAS_FW_DIAG_TYPE_UNREGISTER ||
12127 12150 driver_data.Action == MPTSAS_FW_DIAG_TYPE_QUERY ||
12128 12151 driver_data.Action == MPTSAS_FW_DIAG_TYPE_READ_BUFFER ||
12129 12152 driver_data.Action == MPTSAS_FW_DIAG_TYPE_RELEASE) {
12130 12153 status = mptsas_do_diag_action(mpt, driver_data.Action,
12131 12154 (void *)(uintptr_t)driver_data.PtrDiagAction,
12132 12155 driver_data.Length, &driver_data.ReturnCode,
12133 12156 mode);
12134 12157 if (status == DDI_SUCCESS) {
12135 12158 if (ddi_copyout(&driver_data.ReturnCode,
12136 12159 &user_data->ReturnCode,
12137 12160 sizeof (user_data->ReturnCode), mode)
12138 12161 != 0) {
12139 12162 status = EFAULT;
12140 12163 } else {
12141 12164 status = 0;
12142 12165 }
12143 12166 } else {
12144 12167 status = EIO;
12145 12168 }
12146 12169 } else {
12147 12170 status = EINVAL;
12148 12171 }
12149 12172 } else {
12150 12173 status = EFAULT;
12151 12174 }
12152 12175
12153 12176 return (status);
12154 12177 }
12155 12178
12156 12179 /*
12157 12180 * This routine handles the "event query" ioctl.
12158 12181 */
12159 12182 static int
12160 12183 mptsas_event_query(mptsas_t *mpt, mptsas_event_query_t *data, int mode,
12161 12184 int *rval)
12162 12185 {
12163 12186 int status;
12164 12187 mptsas_event_query_t driverdata;
12165 12188 uint8_t i;
12166 12189
12167 12190 driverdata.Entries = MPTSAS_EVENT_QUEUE_SIZE;
12168 12191
12169 12192 mutex_enter(&mpt->m_mutex);
12170 12193 for (i = 0; i < 4; i++) {
12171 12194 driverdata.Types[i] = mpt->m_event_mask[i];
12172 12195 }
12173 12196 mutex_exit(&mpt->m_mutex);
12174 12197
12175 12198 if (ddi_copyout(&driverdata, data, sizeof (driverdata), mode) != 0) {
12176 12199 status = EFAULT;
12177 12200 } else {
12178 12201 *rval = MPTIOCTL_STATUS_GOOD;
12179 12202 status = 0;
12180 12203 }
12181 12204
12182 12205 return (status);
12183 12206 }
12184 12207
12185 12208 /*
12186 12209 * This routine handles the "event enable" ioctl.
12187 12210 */
12188 12211 static int
12189 12212 mptsas_event_enable(mptsas_t *mpt, mptsas_event_enable_t *data, int mode,
12190 12213 int *rval)
12191 12214 {
12192 12215 int status;
12193 12216 mptsas_event_enable_t driverdata;
12194 12217 uint8_t i;
12195 12218
12196 12219 if (ddi_copyin(data, &driverdata, sizeof (driverdata), mode) == 0) {
12197 12220 mutex_enter(&mpt->m_mutex);
12198 12221 for (i = 0; i < 4; i++) {
12199 12222 mpt->m_event_mask[i] = driverdata.Types[i];
12200 12223 }
12201 12224 mutex_exit(&mpt->m_mutex);
12202 12225
12203 12226 *rval = MPTIOCTL_STATUS_GOOD;
12204 12227 status = 0;
12205 12228 } else {
12206 12229 status = EFAULT;
12207 12230 }
12208 12231 return (status);
12209 12232 }
12210 12233
12211 12234 /*
12212 12235 * This routine handles the "event report" ioctl.
12213 12236 */
12214 12237 static int
12215 12238 mptsas_event_report(mptsas_t *mpt, mptsas_event_report_t *data, int mode,
12216 12239 int *rval)
12217 12240 {
12218 12241 int status;
12219 12242 mptsas_event_report_t driverdata;
12220 12243
12221 12244 mutex_enter(&mpt->m_mutex);
12222 12245
12223 12246 if (ddi_copyin(&data->Size, &driverdata.Size, sizeof (driverdata.Size),
12224 12247 mode) == 0) {
12225 12248 if (driverdata.Size >= sizeof (mpt->m_events)) {
12226 12249 if (ddi_copyout(mpt->m_events, data->Events,
12227 12250 sizeof (mpt->m_events), mode) != 0) {
12228 12251 status = EFAULT;
12229 12252 } else {
12230 12253 if (driverdata.Size > sizeof (mpt->m_events)) {
12231 12254 driverdata.Size =
12232 12255 sizeof (mpt->m_events);
12233 12256 if (ddi_copyout(&driverdata.Size,
12234 12257 &data->Size,
12235 12258 sizeof (driverdata.Size),
12236 12259 mode) != 0) {
12237 12260 status = EFAULT;
12238 12261 } else {
12239 12262 *rval = MPTIOCTL_STATUS_GOOD;
12240 12263 status = 0;
12241 12264 }
12242 12265 } else {
12243 12266 *rval = MPTIOCTL_STATUS_GOOD;
12244 12267 status = 0;
12245 12268 }
12246 12269 }
12247 12270 } else {
12248 12271 *rval = MPTIOCTL_STATUS_LEN_TOO_SHORT;
12249 12272 status = 0;
12250 12273 }
12251 12274 } else {
12252 12275 status = EFAULT;
12253 12276 }
12254 12277
12255 12278 mutex_exit(&mpt->m_mutex);
12256 12279 return (status);
12257 12280 }
12258 12281
12259 12282 static void
12260 12283 mptsas_lookup_pci_data(mptsas_t *mpt, mptsas_adapter_data_t *adapter_data)
12261 12284 {
12262 12285 int *reg_data;
12263 12286 uint_t reglen;
12264 12287
12265 12288 /*
12266 12289 * Lookup the 'reg' property and extract the other data
12267 12290 */
12268 12291 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, mpt->m_dip,
12269 12292 DDI_PROP_DONTPASS, "reg", ®_data, ®len) ==
12270 12293 DDI_PROP_SUCCESS) {
12271 12294 /*
12272 12295 * Extract the PCI data from the 'reg' property first DWORD.
12273 12296 * The entry looks like the following:
12274 12297 * First DWORD:
12275 12298 * Bits 0 - 7 8-bit Register number
12276 12299 * Bits 8 - 10 3-bit Function number
12277 12300 * Bits 11 - 15 5-bit Device number
12278 12301 * Bits 16 - 23 8-bit Bus number
12279 12302 * Bits 24 - 25 2-bit Address Space type identifier
12280 12303 *
12281 12304 */
12282 12305 adapter_data->PciInformation.u.bits.BusNumber =
12283 12306 (reg_data[0] & 0x00FF0000) >> 16;
12284 12307 adapter_data->PciInformation.u.bits.DeviceNumber =
12285 12308 (reg_data[0] & 0x0000F800) >> 11;
12286 12309 adapter_data->PciInformation.u.bits.FunctionNumber =
12287 12310 (reg_data[0] & 0x00000700) >> 8;
12288 12311 ddi_prop_free((void *)reg_data);
12289 12312 } else {
12290 12313 /*
12291 12314 * If we can't determine the PCI data then we fill in FF's for
12292 12315 * the data to indicate this.
12293 12316 */
12294 12317 adapter_data->PCIDeviceHwId = 0xFFFFFFFF;
12295 12318 adapter_data->MpiPortNumber = 0xFFFFFFFF;
12296 12319 adapter_data->PciInformation.u.AsDWORD = 0xFFFFFFFF;
12297 12320 }
12298 12321
12299 12322 /*
12300 12323 * Saved in the mpt->m_fwversion
12301 12324 */
12302 12325 adapter_data->MpiFirmwareVersion = mpt->m_fwversion;
12303 12326 }
12304 12327
12305 12328 static void
12306 12329 mptsas_read_adapter_data(mptsas_t *mpt, mptsas_adapter_data_t *adapter_data)
12307 12330 {
12308 12331 char *driver_verstr = MPTSAS_MOD_STRING;
12309 12332
12310 12333 mptsas_lookup_pci_data(mpt, adapter_data);
12311 12334 adapter_data->AdapterType = mpt->m_MPI25 ?
12312 12335 MPTIOCTL_ADAPTER_TYPE_SAS3 :
12313 12336 MPTIOCTL_ADAPTER_TYPE_SAS2;
12314 12337 adapter_data->PCIDeviceHwId = (uint32_t)mpt->m_devid;
12315 12338 adapter_data->PCIDeviceHwRev = (uint32_t)mpt->m_revid;
12316 12339 adapter_data->SubSystemId = (uint32_t)mpt->m_ssid;
12317 12340 adapter_data->SubsystemVendorId = (uint32_t)mpt->m_svid;
12318 12341 (void) strcpy((char *)&adapter_data->DriverVersion[0], driver_verstr);
12319 12342 adapter_data->BiosVersion = 0;
12320 12343 (void) mptsas_get_bios_page3(mpt, &adapter_data->BiosVersion);
12321 12344 }
12322 12345
12323 12346 static void
12324 12347 mptsas_read_pci_info(mptsas_t *mpt, mptsas_pci_info_t *pci_info)
12325 12348 {
12326 12349 int *reg_data, i;
12327 12350 uint_t reglen;
12328 12351
12329 12352 /*
12330 12353 * Lookup the 'reg' property and extract the other data
12331 12354 */
12332 12355 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, mpt->m_dip,
12333 12356 DDI_PROP_DONTPASS, "reg", ®_data, ®len) ==
12334 12357 DDI_PROP_SUCCESS) {
12335 12358 /*
12336 12359 * Extract the PCI data from the 'reg' property first DWORD.
12337 12360 * The entry looks like the following:
12338 12361 * First DWORD:
12339 12362 * Bits 8 - 10 3-bit Function number
12340 12363 * Bits 11 - 15 5-bit Device number
12341 12364 * Bits 16 - 23 8-bit Bus number
12342 12365 */
12343 12366 pci_info->BusNumber = (reg_data[0] & 0x00FF0000) >> 16;
12344 12367 pci_info->DeviceNumber = (reg_data[0] & 0x0000F800) >> 11;
12345 12368 pci_info->FunctionNumber = (reg_data[0] & 0x00000700) >> 8;
12346 12369 ddi_prop_free((void *)reg_data);
12347 12370 } else {
12348 12371 /*
12349 12372 * If we can't determine the PCI info then we fill in FF's for
12350 12373 * the data to indicate this.
12351 12374 */
12352 12375 pci_info->BusNumber = 0xFFFFFFFF;
12353 12376 pci_info->DeviceNumber = 0xFF;
12354 12377 pci_info->FunctionNumber = 0xFF;
12355 12378 }
12356 12379
12357 12380 /*
12358 12381 * Now get the interrupt vector and the pci header. The vector can
12359 12382 * only be 0 right now. The header is the first 256 bytes of config
12360 12383 * space.
12361 12384 */
12362 12385 pci_info->InterruptVector = 0;
12363 12386 for (i = 0; i < sizeof (pci_info->PciHeader); i++) {
12364 12387 pci_info->PciHeader[i] = pci_config_get8(mpt->m_config_handle,
12365 12388 i);
12366 12389 }
12367 12390 }
12368 12391
12369 12392 static int
12370 12393 mptsas_reg_access(mptsas_t *mpt, mptsas_reg_access_t *data, int mode)
12371 12394 {
12372 12395 int status = 0;
12373 12396 mptsas_reg_access_t driverdata;
12374 12397
12375 12398 mutex_enter(&mpt->m_mutex);
12376 12399 if (ddi_copyin(data, &driverdata, sizeof (driverdata), mode) == 0) {
12377 12400 switch (driverdata.Command) {
12378 12401 /*
12379 12402 * IO access is not supported.
12380 12403 */
12381 12404 case REG_IO_READ:
12382 12405 case REG_IO_WRITE:
12383 12406 mptsas_log(mpt, CE_WARN, "IO access is not "
12384 12407 "supported. Use memory access.");
12385 12408 status = EINVAL;
12386 12409 break;
12387 12410
12388 12411 case REG_MEM_READ:
12389 12412 driverdata.RegData = ddi_get32(mpt->m_datap,
12390 12413 (uint32_t *)(void *)mpt->m_reg +
12391 12414 driverdata.RegOffset);
12392 12415 if (ddi_copyout(&driverdata.RegData,
12393 12416 &data->RegData,
12394 12417 sizeof (driverdata.RegData), mode) != 0) {
12395 12418 mptsas_log(mpt, CE_WARN, "Register "
12396 12419 "Read Failed");
12397 12420 status = EFAULT;
12398 12421 }
12399 12422 break;
12400 12423
12401 12424 case REG_MEM_WRITE:
12402 12425 ddi_put32(mpt->m_datap,
12403 12426 (uint32_t *)(void *)mpt->m_reg +
12404 12427 driverdata.RegOffset,
12405 12428 driverdata.RegData);
12406 12429 break;
12407 12430
12408 12431 default:
12409 12432 status = EINVAL;
12410 12433 break;
12411 12434 }
12412 12435 } else {
12413 12436 status = EFAULT;
12414 12437 }
12415 12438
12416 12439 mutex_exit(&mpt->m_mutex);
12417 12440 return (status);
12418 12441 }
12419 12442
12420 12443 static int
12421 12444 led_control(mptsas_t *mpt, intptr_t data, int mode)
12422 12445 {
12423 12446 int ret = 0;
12424 12447 mptsas_led_control_t lc;
12425 12448 mptsas_target_t *ptgt;
12426 12449
12427 12450 if (ddi_copyin((void *)data, &lc, sizeof (lc), mode) != 0) {
12428 12451 return (EFAULT);
12429 12452 }
12430 12453
12431 12454 if ((lc.Command != MPTSAS_LEDCTL_FLAG_SET &&
12432 12455 lc.Command != MPTSAS_LEDCTL_FLAG_GET) ||
12433 12456 lc.Led < MPTSAS_LEDCTL_LED_MIN ||
12434 12457 lc.Led > MPTSAS_LEDCTL_LED_MAX ||
12435 12458 (lc.Command == MPTSAS_LEDCTL_FLAG_SET && lc.LedStatus != 0 &&
12436 12459 lc.LedStatus != 1)) {
12437 12460 return (EINVAL);
12438 12461 }
12439 12462
12440 12463 if ((lc.Command == MPTSAS_LEDCTL_FLAG_SET && (mode & FWRITE) == 0) ||
12441 12464 (lc.Command == MPTSAS_LEDCTL_FLAG_GET && (mode & FREAD) == 0))
12442 12465 return (EACCES);
12443 12466
12444 12467 /* Locate the target we're interrogating... */
12445 12468 mutex_enter(&mpt->m_mutex);
12446 12469 ptgt = refhash_linear_search(mpt->m_targets,
12447 12470 mptsas_target_eval_slot, &lc);
12448 12471 if (ptgt == NULL) {
12449 12472 /* We could not find a target for that enclosure/slot. */
12450 12473 mutex_exit(&mpt->m_mutex);
12451 12474 return (ENOENT);
12452 12475 }
12453 12476
12454 12477 if (lc.Command == MPTSAS_LEDCTL_FLAG_SET) {
12455 12478 /* Update our internal LED state. */
12456 12479 ptgt->m_led_status &= ~(1 << (lc.Led - 1));
12457 12480 ptgt->m_led_status |= lc.LedStatus << (lc.Led - 1);
12458 12481
12459 12482 /* Flush it to the controller. */
12460 12483 ret = mptsas_flush_led_status(mpt, ptgt);
12461 12484 mutex_exit(&mpt->m_mutex);
12462 12485 return (ret);
12463 12486 }
12464 12487
12465 12488 /* Return our internal LED state. */
12466 12489 lc.LedStatus = (ptgt->m_led_status >> (lc.Led - 1)) & 1;
12467 12490 mutex_exit(&mpt->m_mutex);
12468 12491
12469 12492 if (ddi_copyout(&lc, (void *)data, sizeof (lc), mode) != 0) {
12470 12493 return (EFAULT);
12471 12494 }
12472 12495
12473 12496 return (0);
12474 12497 }
12475 12498
12476 12499 static int
12477 12500 get_disk_info(mptsas_t *mpt, intptr_t data, int mode)
12478 12501 {
12479 12502 uint16_t i = 0;
12480 12503 uint16_t count = 0;
12481 12504 int ret = 0;
12482 12505 mptsas_target_t *ptgt;
12483 12506 mptsas_disk_info_t *di;
12484 12507 STRUCT_DECL(mptsas_get_disk_info, gdi);
12485 12508
12486 12509 if ((mode & FREAD) == 0)
12487 12510 return (EACCES);
12488 12511
12489 12512 STRUCT_INIT(gdi, get_udatamodel());
12490 12513
12491 12514 if (ddi_copyin((void *)data, STRUCT_BUF(gdi), STRUCT_SIZE(gdi),
12492 12515 mode) != 0) {
12493 12516 return (EFAULT);
12494 12517 }
12495 12518
12496 12519 /* Find out how many targets there are. */
12497 12520 mutex_enter(&mpt->m_mutex);
12498 12521 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL;
12499 12522 ptgt = refhash_next(mpt->m_targets, ptgt)) {
12500 12523 count++;
12501 12524 }
12502 12525 mutex_exit(&mpt->m_mutex);
12503 12526
12504 12527 /*
12505 12528 * If we haven't been asked to copy out information on each target,
12506 12529 * then just return the count.
12507 12530 */
12508 12531 STRUCT_FSET(gdi, DiskCount, count);
12509 12532 if (STRUCT_FGETP(gdi, PtrDiskInfoArray) == NULL)
12510 12533 goto copy_out;
12511 12534
12512 12535 /*
12513 12536 * If we haven't been given a large enough buffer to copy out into,
12514 12537 * let the caller know.
12515 12538 */
12516 12539 if (STRUCT_FGET(gdi, DiskInfoArraySize) <
12517 12540 count * sizeof (mptsas_disk_info_t)) {
12518 12541 ret = ENOSPC;
12519 12542 goto copy_out;
12520 12543 }
12521 12544
12522 12545 di = kmem_zalloc(count * sizeof (mptsas_disk_info_t), KM_SLEEP);
12523 12546
12524 12547 mutex_enter(&mpt->m_mutex);
12525 12548 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL;
12526 12549 ptgt = refhash_next(mpt->m_targets, ptgt)) {
12527 12550 if (i >= count) {
12528 12551 /*
12529 12552 * The number of targets changed while we weren't
12530 12553 * looking, so give up.
12531 12554 */
12532 12555 refhash_rele(mpt->m_targets, ptgt);
12533 12556 mutex_exit(&mpt->m_mutex);
12534 12557 kmem_free(di, count * sizeof (mptsas_disk_info_t));
12535 12558 return (EAGAIN);
12536 12559 }
12537 12560 di[i].Instance = mpt->m_instance;
12538 12561 di[i].Enclosure = ptgt->m_enclosure;
12539 12562 di[i].Slot = ptgt->m_slot_num;
12540 12563 di[i].SasAddress = ptgt->m_addr.mta_wwn;
12541 12564 i++;
12542 12565 }
12543 12566 mutex_exit(&mpt->m_mutex);
12544 12567 STRUCT_FSET(gdi, DiskCount, i);
12545 12568
12546 12569 /* Copy out the disk information to the caller. */
12547 12570 if (ddi_copyout((void *)di, STRUCT_FGETP(gdi, PtrDiskInfoArray),
12548 12571 i * sizeof (mptsas_disk_info_t), mode) != 0) {
12549 12572 ret = EFAULT;
12550 12573 }
12551 12574
12552 12575 kmem_free(di, count * sizeof (mptsas_disk_info_t));
12553 12576
12554 12577 copy_out:
12555 12578 if (ddi_copyout(STRUCT_BUF(gdi), (void *)data, STRUCT_SIZE(gdi),
12556 12579 mode) != 0) {
12557 12580 ret = EFAULT;
12558 12581 }
12559 12582
12560 12583 return (ret);
12561 12584 }
12562 12585
12563 12586 static int
12564 12587 mptsas_ioctl(dev_t dev, int cmd, intptr_t data, int mode, cred_t *credp,
12565 12588 int *rval)
12566 12589 {
12567 12590 int status = 0;
12568 12591 mptsas_t *mpt;
12569 12592 mptsas_update_flash_t flashdata;
12570 12593 mptsas_pass_thru_t passthru_data;
12571 12594 mptsas_adapter_data_t adapter_data;
12572 12595 mptsas_pci_info_t pci_info;
12573 12596 int copylen;
12574 12597
12575 12598 int iport_flag = 0;
12576 12599 dev_info_t *dip = NULL;
12577 12600 mptsas_phymask_t phymask = 0;
12578 12601 struct devctl_iocdata *dcp = NULL;
12579 12602 char *addr = NULL;
12580 12603 mptsas_target_t *ptgt = NULL;
12581 12604
12582 12605 *rval = MPTIOCTL_STATUS_GOOD;
12583 12606 if (secpolicy_sys_config(credp, B_FALSE) != 0) {
12584 12607 return (EPERM);
12585 12608 }
12586 12609
12587 12610 mpt = ddi_get_soft_state(mptsas_state, MINOR2INST(getminor(dev)));
12588 12611 if (mpt == NULL) {
12589 12612 /*
12590 12613 * Called from iport node, get the states
12591 12614 */
12592 12615 iport_flag = 1;
12593 12616 dip = mptsas_get_dip_from_dev(dev, &phymask);
12594 12617 if (dip == NULL) {
12595 12618 return (ENXIO);
12596 12619 }
12597 12620 mpt = DIP2MPT(dip);
12598 12621 }
12599 12622 /* Make sure power level is D0 before accessing registers */
12600 12623 mutex_enter(&mpt->m_mutex);
12601 12624 if (mpt->m_options & MPTSAS_OPT_PM) {
12602 12625 (void) pm_busy_component(mpt->m_dip, 0);
12603 12626 if (mpt->m_power_level != PM_LEVEL_D0) {
12604 12627 mutex_exit(&mpt->m_mutex);
12605 12628 if (pm_raise_power(mpt->m_dip, 0, PM_LEVEL_D0) !=
12606 12629 DDI_SUCCESS) {
12607 12630 mptsas_log(mpt, CE_WARN,
12608 12631 "mptsas%d: mptsas_ioctl: Raise power "
12609 12632 "request failed.", mpt->m_instance);
12610 12633 (void) pm_idle_component(mpt->m_dip, 0);
12611 12634 return (ENXIO);
12612 12635 }
12613 12636 } else {
12614 12637 mutex_exit(&mpt->m_mutex);
12615 12638 }
12616 12639 } else {
12617 12640 mutex_exit(&mpt->m_mutex);
12618 12641 }
12619 12642
12620 12643 if (iport_flag) {
12621 12644 status = scsi_hba_ioctl(dev, cmd, data, mode, credp, rval);
12622 12645 if (status != 0) {
12623 12646 goto out;
12624 12647 }
12625 12648 /*
12626 12649 * The following code control the OK2RM LED, it doesn't affect
12627 12650 * the ioctl return status.
12628 12651 */
12629 12652 if ((cmd == DEVCTL_DEVICE_ONLINE) ||
12630 12653 (cmd == DEVCTL_DEVICE_OFFLINE)) {
12631 12654 if (ndi_dc_allochdl((void *)data, &dcp) !=
12632 12655 NDI_SUCCESS) {
12633 12656 goto out;
12634 12657 }
12635 12658 addr = ndi_dc_getaddr(dcp);
12636 12659 ptgt = mptsas_addr_to_ptgt(mpt, addr, phymask);
12637 12660 if (ptgt == NULL) {
12638 12661 NDBG14(("mptsas_ioctl led control: tgt %s not "
12639 12662 "found", addr));
12640 12663 ndi_dc_freehdl(dcp);
12641 12664 goto out;
12642 12665 }
12643 12666 mutex_enter(&mpt->m_mutex);
12644 12667 if (cmd == DEVCTL_DEVICE_ONLINE) {
12645 12668 ptgt->m_tgt_unconfigured = 0;
12646 12669 } else if (cmd == DEVCTL_DEVICE_OFFLINE) {
12647 12670 ptgt->m_tgt_unconfigured = 1;
12648 12671 }
12649 12672 if (cmd == DEVCTL_DEVICE_OFFLINE) {
12650 12673 ptgt->m_led_status |=
12651 12674 (1 << (MPTSAS_LEDCTL_LED_OK2RM - 1));
12652 12675 } else {
12653 12676 ptgt->m_led_status &=
12654 12677 ~(1 << (MPTSAS_LEDCTL_LED_OK2RM - 1));
12655 12678 }
12656 12679 (void) mptsas_flush_led_status(mpt, ptgt);
12657 12680 mutex_exit(&mpt->m_mutex);
12658 12681 ndi_dc_freehdl(dcp);
12659 12682 }
12660 12683 goto out;
12661 12684 }
12662 12685 switch (cmd) {
12663 12686 case MPTIOCTL_GET_DISK_INFO:
12664 12687 status = get_disk_info(mpt, data, mode);
12665 12688 break;
12666 12689 case MPTIOCTL_LED_CONTROL:
12667 12690 status = led_control(mpt, data, mode);
12668 12691 break;
12669 12692 case MPTIOCTL_UPDATE_FLASH:
12670 12693 if (ddi_copyin((void *)data, &flashdata,
12671 12694 sizeof (struct mptsas_update_flash), mode)) {
12672 12695 status = EFAULT;
12673 12696 break;
12674 12697 }
12675 12698
12676 12699 mutex_enter(&mpt->m_mutex);
12677 12700 if (mptsas_update_flash(mpt,
↓ open down ↓ |
1484 lines elided |
↑ open up ↑ |
12678 12701 (caddr_t)(long)flashdata.PtrBuffer,
12679 12702 flashdata.ImageSize, flashdata.ImageType, mode)) {
12680 12703 status = EFAULT;
12681 12704 }
12682 12705
12683 12706 /*
12684 12707 * Reset the chip to start using the new
12685 12708 * firmware. Reset if failed also.
12686 12709 */
12687 12710 mpt->m_softstate &= ~MPTSAS_SS_MSG_UNIT_RESET;
12688 - if (mptsas_restart_ioc(mpt) == DDI_FAILURE) {
12711 + if (mptsas_reset_handler(mpt) == DDI_FAILURE) {
12689 12712 status = EFAULT;
12690 12713 }
12691 12714 mutex_exit(&mpt->m_mutex);
12692 12715 break;
12693 12716 case MPTIOCTL_PASS_THRU:
12694 12717 /*
12695 12718 * The user has requested to pass through a command to
12696 12719 * be executed by the MPT firmware. Call our routine
12697 12720 * which does this. Only allow one passthru IOCTL at
12698 12721 * one time. Other threads will block on
12699 12722 * m_passthru_mutex, which is of adaptive variant.
12700 12723 */
12701 12724 if (ddi_copyin((void *)data, &passthru_data,
12702 12725 sizeof (mptsas_pass_thru_t), mode)) {
12703 12726 status = EFAULT;
12704 12727 break;
12705 12728 }
12706 12729 mutex_enter(&mpt->m_passthru_mutex);
12707 12730 mutex_enter(&mpt->m_mutex);
12708 12731 status = mptsas_pass_thru(mpt, &passthru_data, mode);
12709 12732 mutex_exit(&mpt->m_mutex);
12710 12733 mutex_exit(&mpt->m_passthru_mutex);
12711 12734
12712 12735 break;
12713 12736 case MPTIOCTL_GET_ADAPTER_DATA:
12714 12737 /*
12715 12738 * The user has requested to read adapter data. Call
12716 12739 * our routine which does this.
12717 12740 */
12718 12741 bzero(&adapter_data, sizeof (mptsas_adapter_data_t));
12719 12742 if (ddi_copyin((void *)data, (void *)&adapter_data,
12720 12743 sizeof (mptsas_adapter_data_t), mode)) {
12721 12744 status = EFAULT;
12722 12745 break;
12723 12746 }
12724 12747 if (adapter_data.StructureLength >=
12725 12748 sizeof (mptsas_adapter_data_t)) {
12726 12749 adapter_data.StructureLength = (uint32_t)
12727 12750 sizeof (mptsas_adapter_data_t);
12728 12751 copylen = sizeof (mptsas_adapter_data_t);
12729 12752 mutex_enter(&mpt->m_mutex);
12730 12753 mptsas_read_adapter_data(mpt, &adapter_data);
12731 12754 mutex_exit(&mpt->m_mutex);
12732 12755 } else {
12733 12756 adapter_data.StructureLength = (uint32_t)
12734 12757 sizeof (mptsas_adapter_data_t);
12735 12758 copylen = sizeof (adapter_data.StructureLength);
12736 12759 *rval = MPTIOCTL_STATUS_LEN_TOO_SHORT;
12737 12760 }
12738 12761 if (ddi_copyout((void *)(&adapter_data), (void *)data,
12739 12762 copylen, mode) != 0) {
12740 12763 status = EFAULT;
12741 12764 }
12742 12765 break;
12743 12766 case MPTIOCTL_GET_PCI_INFO:
12744 12767 /*
12745 12768 * The user has requested to read pci info. Call
12746 12769 * our routine which does this.
12747 12770 */
12748 12771 bzero(&pci_info, sizeof (mptsas_pci_info_t));
12749 12772 mutex_enter(&mpt->m_mutex);
↓ open down ↓ |
51 lines elided |
↑ open up ↑ |
12750 12773 mptsas_read_pci_info(mpt, &pci_info);
12751 12774 mutex_exit(&mpt->m_mutex);
12752 12775 if (ddi_copyout((void *)(&pci_info), (void *)data,
12753 12776 sizeof (mptsas_pci_info_t), mode) != 0) {
12754 12777 status = EFAULT;
12755 12778 }
12756 12779 break;
12757 12780 case MPTIOCTL_RESET_ADAPTER:
12758 12781 mutex_enter(&mpt->m_mutex);
12759 12782 mpt->m_softstate &= ~MPTSAS_SS_MSG_UNIT_RESET;
12760 - if ((mptsas_restart_ioc(mpt)) == DDI_FAILURE) {
12783 + if ((mptsas_reset_handler(mpt)) == DDI_FAILURE) {
12761 12784 mptsas_log(mpt, CE_WARN, "reset adapter IOCTL "
12762 12785 "failed");
12763 12786 status = EFAULT;
12764 12787 }
12765 12788 mutex_exit(&mpt->m_mutex);
12766 12789 break;
12767 12790 case MPTIOCTL_DIAG_ACTION:
12768 12791 /*
12769 12792 * The user has done a diag buffer action. Call our
12770 12793 * routine which does this. Only allow one diag action
12771 12794 * at one time.
12772 12795 */
12773 12796 mutex_enter(&mpt->m_mutex);
12774 12797 if (mpt->m_diag_action_in_progress) {
12775 12798 mutex_exit(&mpt->m_mutex);
12776 12799 return (EBUSY);
12777 12800 }
12778 12801 mpt->m_diag_action_in_progress = 1;
12779 12802 status = mptsas_diag_action(mpt,
12780 12803 (mptsas_diag_action_t *)data, mode);
12781 12804 mpt->m_diag_action_in_progress = 0;
12782 12805 mutex_exit(&mpt->m_mutex);
12783 12806 break;
12784 12807 case MPTIOCTL_EVENT_QUERY:
12785 12808 /*
12786 12809 * The user has done an event query. Call our routine
12787 12810 * which does this.
12788 12811 */
12789 12812 status = mptsas_event_query(mpt,
12790 12813 (mptsas_event_query_t *)data, mode, rval);
12791 12814 break;
12792 12815 case MPTIOCTL_EVENT_ENABLE:
12793 12816 /*
12794 12817 * The user has done an event enable. Call our routine
12795 12818 * which does this.
12796 12819 */
12797 12820 status = mptsas_event_enable(mpt,
12798 12821 (mptsas_event_enable_t *)data, mode, rval);
12799 12822 break;
12800 12823 case MPTIOCTL_EVENT_REPORT:
12801 12824 /*
12802 12825 * The user has done an event report. Call our routine
12803 12826 * which does this.
12804 12827 */
12805 12828 status = mptsas_event_report(mpt,
12806 12829 (mptsas_event_report_t *)data, mode, rval);
12807 12830 break;
12808 12831 case MPTIOCTL_REG_ACCESS:
12809 12832 /*
12810 12833 * The user has requested register access. Call our
12811 12834 * routine which does this.
12812 12835 */
12813 12836 status = mptsas_reg_access(mpt,
12814 12837 (mptsas_reg_access_t *)data, mode);
12815 12838 break;
12816 12839 default:
↓ open down ↓ |
46 lines elided |
↑ open up ↑ |
12817 12840 status = scsi_hba_ioctl(dev, cmd, data, mode, credp,
12818 12841 rval);
12819 12842 break;
12820 12843 }
12821 12844
12822 12845 out:
12823 12846 return (status);
12824 12847 }
12825 12848
12826 12849 int
12827 -mptsas_restart_ioc(mptsas_t *mpt)
12850 +mptsas_reset_handler(mptsas_t *mpt)
12828 12851 {
12829 12852 int rval = DDI_SUCCESS;
12830 12853 mptsas_target_t *ptgt = NULL;
12831 12854
12832 12855 ASSERT(mutex_owned(&mpt->m_mutex));
12833 12856
12834 12857 /*
12835 - * Set a flag telling I/O path that we're processing a reset. This is
12836 - * needed because after the reset is complete, the hash table still
12858 + * Set a flag telling task management we are processing a reset. This
12859 + * is needed because after the reset is complete, the hash table still
12837 12860 * needs to be rebuilt. If I/Os are started before the hash table is
12838 12861 * rebuilt, I/O errors will occur. This flag allows I/Os to be marked
12839 12862 * so that they can be retried.
12840 12863 */
12864 + mutex_enter(&mpt->m_taskmgmt_mutex);
12865 + if (mpt->m_in_reset == TRUE) {
12866 + mutex_exit(&mpt->m_taskmgmt_mutex);
12867 + return (DDI_FAILURE);
12868 + }
12841 12869 mpt->m_in_reset = TRUE;
12870 + mutex_exit(&mpt->m_taskmgmt_mutex);
12842 12871
12843 12872 /*
12844 12873 * Wait until all the allocated sense data buffers for DMA are freed.
12845 12874 */
12846 12875 while (mpt->m_extreq_sense_refcount > 0)
12847 12876 cv_wait(&mpt->m_extreq_sense_refcount_cv, &mpt->m_mutex);
12848 12877
12849 12878 /*
12850 12879 * Set all throttles to HOLD
12851 12880 */
12852 12881 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL;
12853 12882 ptgt = refhash_next(mpt->m_targets, ptgt)) {
12854 12883 mptsas_set_throttle(mpt, ptgt, HOLD_THROTTLE);
12855 12884 }
12856 12885
12857 12886 /*
12858 12887 * Disable interrupts
12859 12888 */
12860 12889 MPTSAS_DISABLE_INTR(mpt);
12861 12890
12862 12891 /*
12863 12892 * Abort all commands: outstanding commands, commands in waitq and
12864 12893 * tx_waitq.
12865 12894 */
12866 12895 mptsas_flush_hba(mpt);
12867 12896
12868 12897 /*
12869 12898 * Reinitialize the chip.
12870 12899 */
12871 12900 if (mptsas_init_chip(mpt, FALSE) == DDI_FAILURE) {
12872 12901 rval = DDI_FAILURE;
12873 12902 }
12874 12903
12875 12904 /*
12876 12905 * Enable interrupts again
12877 12906 */
12878 12907 MPTSAS_ENABLE_INTR(mpt);
12879 12908
12880 12909 /*
12881 12910 * If mptsas_init_chip was successful, update the driver data.
12882 12911 */
12883 12912 if (rval == DDI_SUCCESS) {
12884 12913 mptsas_update_driver_data(mpt);
12885 12914 }
12886 12915
12887 12916 /*
12888 12917 * Reset the throttles
12889 12918 */
12890 12919 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL;
12891 12920 ptgt = refhash_next(mpt->m_targets, ptgt)) {
12892 12921 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE);
12893 12922 }
12894 12923
12895 12924 mptsas_doneq_empty(mpt);
↓ open down ↓ |
44 lines elided |
↑ open up ↑ |
12896 12925 mptsas_restart_hba(mpt);
12897 12926
12898 12927 if (rval != DDI_SUCCESS) {
12899 12928 mptsas_fm_ereport(mpt, DDI_FM_DEVICE_NO_RESPONSE);
12900 12929 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_LOST);
12901 12930 }
12902 12931
12903 12932 /*
12904 12933 * Clear the reset flag so that I/Os can continue.
12905 12934 */
12935 + mutex_enter(&mpt->m_taskmgmt_mutex);
12906 12936 mpt->m_in_reset = FALSE;
12937 + mutex_exit(&mpt->m_taskmgmt_mutex);
12907 12938
12908 12939 return (rval);
12909 12940 }
12910 12941
12911 12942 static int
12912 12943 mptsas_init_chip(mptsas_t *mpt, int first_time)
12913 12944 {
12914 12945 ddi_dma_cookie_t cookie;
12915 12946 uint32_t i;
12916 12947 int rval;
12917 12948
12918 12949 /*
12919 12950 * Check to see if the firmware image is valid
12920 12951 */
12921 12952 if (ddi_get32(mpt->m_datap, &mpt->m_reg->HostDiagnostic) &
12922 12953 MPI2_DIAG_FLASH_BAD_SIG) {
12923 12954 mptsas_log(mpt, CE_WARN, "mptsas bad flash signature!");
12924 12955 goto fail;
12925 12956 }
12926 12957
12927 12958 /*
12928 12959 * Reset the chip
12929 12960 */
12930 12961 rval = mptsas_ioc_reset(mpt, first_time);
12931 12962 if (rval == MPTSAS_RESET_FAIL) {
12932 12963 mptsas_log(mpt, CE_WARN, "hard reset failed!");
12933 12964 goto fail;
12934 12965 }
12935 12966
12936 12967 if ((rval == MPTSAS_SUCCESS_MUR) && (!first_time)) {
12937 12968 goto mur;
12938 12969 }
12939 12970 /*
12940 12971 * Setup configuration space
12941 12972 */
12942 12973 if (mptsas_config_space_init(mpt) == FALSE) {
12943 12974 mptsas_log(mpt, CE_WARN, "mptsas_config_space_init "
12944 12975 "failed!");
12945 12976 goto fail;
12946 12977 }
12947 12978
12948 12979 /*
12949 12980 * IOC facts can change after a diag reset so all buffers that are
12950 12981 * based on these numbers must be de-allocated and re-allocated. Get
12951 12982 * new IOC facts each time chip is initialized.
12952 12983 */
12953 12984 if (mptsas_ioc_get_facts(mpt) == DDI_FAILURE) {
12954 12985 mptsas_log(mpt, CE_WARN, "mptsas_ioc_get_facts failed");
12955 12986 goto fail;
12956 12987 }
12957 12988
12958 12989 if (mptsas_alloc_active_slots(mpt, KM_SLEEP)) {
12959 12990 goto fail;
12960 12991 }
12961 12992 /*
12962 12993 * Allocate request message frames, reply free queue, reply descriptor
12963 12994 * post queue, and reply message frames using latest IOC facts.
12964 12995 */
12965 12996 if (mptsas_alloc_request_frames(mpt) == DDI_FAILURE) {
12966 12997 mptsas_log(mpt, CE_WARN, "mptsas_alloc_request_frames failed");
12967 12998 goto fail;
12968 12999 }
12969 13000 if (mptsas_alloc_sense_bufs(mpt) == DDI_FAILURE) {
12970 13001 mptsas_log(mpt, CE_WARN, "mptsas_alloc_sense_bufs failed");
12971 13002 goto fail;
12972 13003 }
12973 13004 if (mptsas_alloc_free_queue(mpt) == DDI_FAILURE) {
12974 13005 mptsas_log(mpt, CE_WARN, "mptsas_alloc_free_queue failed!");
12975 13006 goto fail;
12976 13007 }
12977 13008 if (mptsas_alloc_post_queue(mpt) == DDI_FAILURE) {
12978 13009 mptsas_log(mpt, CE_WARN, "mptsas_alloc_post_queue failed!");
12979 13010 goto fail;
12980 13011 }
12981 13012 if (mptsas_alloc_reply_frames(mpt) == DDI_FAILURE) {
12982 13013 mptsas_log(mpt, CE_WARN, "mptsas_alloc_reply_frames failed!");
12983 13014 goto fail;
12984 13015 }
12985 13016
12986 13017 mur:
12987 13018 /*
12988 13019 * Re-Initialize ioc to operational state
12989 13020 */
12990 13021 if (mptsas_ioc_init(mpt) == DDI_FAILURE) {
12991 13022 mptsas_log(mpt, CE_WARN, "mptsas_ioc_init failed");
12992 13023 goto fail;
12993 13024 }
12994 13025
12995 13026 mptsas_alloc_reply_args(mpt);
12996 13027
12997 13028 /*
12998 13029 * Initialize reply post index. Reply free index is initialized after
12999 13030 * the next loop.
13000 13031 */
13001 13032 mpt->m_post_index = 0;
13002 13033
13003 13034 /*
13004 13035 * Initialize the Reply Free Queue with the physical addresses of our
13005 13036 * reply frames.
13006 13037 */
13007 13038 cookie.dmac_address = mpt->m_reply_frame_dma_addr & 0xffffffffu;
13008 13039 for (i = 0; i < mpt->m_max_replies; i++) {
13009 13040 ddi_put32(mpt->m_acc_free_queue_hdl,
13010 13041 &((uint32_t *)(void *)mpt->m_free_queue)[i],
13011 13042 cookie.dmac_address);
13012 13043 cookie.dmac_address += mpt->m_reply_frame_size;
13013 13044 }
13014 13045 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0,
13015 13046 DDI_DMA_SYNC_FORDEV);
13016 13047
13017 13048 /*
13018 13049 * Initialize the reply free index to one past the last frame on the
13019 13050 * queue. This will signify that the queue is empty to start with.
13020 13051 */
13021 13052 mpt->m_free_index = i;
13022 13053 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex, i);
13023 13054
13024 13055 /*
13025 13056 * Initialize the reply post queue to 0xFFFFFFFF,0xFFFFFFFF's.
13026 13057 */
13027 13058 for (i = 0; i < mpt->m_post_queue_depth; i++) {
13028 13059 ddi_put64(mpt->m_acc_post_queue_hdl,
13029 13060 &((uint64_t *)(void *)mpt->m_post_queue)[i],
13030 13061 0xFFFFFFFFFFFFFFFF);
13031 13062 }
13032 13063 (void) ddi_dma_sync(mpt->m_dma_post_queue_hdl, 0, 0,
13033 13064 DDI_DMA_SYNC_FORDEV);
13034 13065
13035 13066 /*
13036 13067 * Enable ports
13037 13068 */
13038 13069 if (mptsas_ioc_enable_port(mpt) == DDI_FAILURE) {
13039 13070 mptsas_log(mpt, CE_WARN, "mptsas_ioc_enable_port failed");
13040 13071 goto fail;
13041 13072 }
13042 13073
13043 13074 /*
13044 13075 * enable events
13045 13076 */
13046 13077 if (mptsas_ioc_enable_event_notification(mpt)) {
13047 13078 mptsas_log(mpt, CE_WARN,
13048 13079 "mptsas_ioc_enable_event_notification failed");
13049 13080 goto fail;
13050 13081 }
13051 13082
13052 13083 /*
13053 13084 * We need checks in attach and these.
13054 13085 * chip_init is called in mult. places
13055 13086 */
13056 13087
13057 13088 if ((mptsas_check_dma_handle(mpt->m_dma_req_frame_hdl) !=
13058 13089 DDI_SUCCESS) ||
13059 13090 (mptsas_check_dma_handle(mpt->m_dma_req_sense_hdl) !=
13060 13091 DDI_SUCCESS) ||
13061 13092 (mptsas_check_dma_handle(mpt->m_dma_reply_frame_hdl) !=
13062 13093 DDI_SUCCESS) ||
13063 13094 (mptsas_check_dma_handle(mpt->m_dma_free_queue_hdl) !=
13064 13095 DDI_SUCCESS) ||
13065 13096 (mptsas_check_dma_handle(mpt->m_dma_post_queue_hdl) !=
13066 13097 DDI_SUCCESS) ||
13067 13098 (mptsas_check_dma_handle(mpt->m_hshk_dma_hdl) !=
13068 13099 DDI_SUCCESS)) {
13069 13100 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
13070 13101 goto fail;
13071 13102 }
13072 13103
13073 13104 /* Check all acc handles */
13074 13105 if ((mptsas_check_acc_handle(mpt->m_datap) != DDI_SUCCESS) ||
13075 13106 (mptsas_check_acc_handle(mpt->m_acc_req_frame_hdl) !=
13076 13107 DDI_SUCCESS) ||
13077 13108 (mptsas_check_acc_handle(mpt->m_acc_req_sense_hdl) !=
13078 13109 DDI_SUCCESS) ||
13079 13110 (mptsas_check_acc_handle(mpt->m_acc_reply_frame_hdl) !=
13080 13111 DDI_SUCCESS) ||
13081 13112 (mptsas_check_acc_handle(mpt->m_acc_free_queue_hdl) !=
13082 13113 DDI_SUCCESS) ||
13083 13114 (mptsas_check_acc_handle(mpt->m_acc_post_queue_hdl) !=
13084 13115 DDI_SUCCESS) ||
13085 13116 (mptsas_check_acc_handle(mpt->m_hshk_acc_hdl) !=
13086 13117 DDI_SUCCESS) ||
13087 13118 (mptsas_check_acc_handle(mpt->m_config_handle) !=
13088 13119 DDI_SUCCESS)) {
13089 13120 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
13090 13121 goto fail;
13091 13122 }
13092 13123
13093 13124 return (DDI_SUCCESS);
13094 13125
13095 13126 fail:
13096 13127 return (DDI_FAILURE);
13097 13128 }
13098 13129
13099 13130 static int
13100 13131 mptsas_get_pci_cap(mptsas_t *mpt)
13101 13132 {
13102 13133 ushort_t caps_ptr, cap, cap_count;
13103 13134
13104 13135 if (mpt->m_config_handle == NULL)
13105 13136 return (FALSE);
13106 13137 /*
13107 13138 * Check if capabilities list is supported and if so,
13108 13139 * get initial capabilities pointer and clear bits 0,1.
13109 13140 */
13110 13141 if (pci_config_get16(mpt->m_config_handle, PCI_CONF_STAT)
13111 13142 & PCI_STAT_CAP) {
13112 13143 caps_ptr = P2ALIGN(pci_config_get8(mpt->m_config_handle,
13113 13144 PCI_CONF_CAP_PTR), 4);
13114 13145 } else {
13115 13146 caps_ptr = PCI_CAP_NEXT_PTR_NULL;
13116 13147 }
13117 13148
13118 13149 /*
13119 13150 * Walk capabilities if supported.
13120 13151 */
13121 13152 for (cap_count = 0; caps_ptr != PCI_CAP_NEXT_PTR_NULL; ) {
13122 13153
13123 13154 /*
13124 13155 * Check that we haven't exceeded the maximum number of
13125 13156 * capabilities and that the pointer is in a valid range.
13126 13157 */
13127 13158 if (++cap_count > 48) {
13128 13159 mptsas_log(mpt, CE_WARN,
13129 13160 "too many device capabilities.\n");
13130 13161 break;
13131 13162 }
13132 13163 if (caps_ptr < 64) {
13133 13164 mptsas_log(mpt, CE_WARN,
13134 13165 "capabilities pointer 0x%x out of range.\n",
13135 13166 caps_ptr);
13136 13167 break;
13137 13168 }
13138 13169
13139 13170 /*
13140 13171 * Get next capability and check that it is valid.
13141 13172 * For now, we only support power management.
13142 13173 */
13143 13174 cap = pci_config_get8(mpt->m_config_handle, caps_ptr);
13144 13175 switch (cap) {
13145 13176 case PCI_CAP_ID_PM:
13146 13177 mptsas_log(mpt, CE_NOTE,
13147 13178 "?mptsas%d supports power management.\n",
13148 13179 mpt->m_instance);
13149 13180 mpt->m_options |= MPTSAS_OPT_PM;
13150 13181
13151 13182 /* Save PMCSR offset */
13152 13183 mpt->m_pmcsr_offset = caps_ptr + PCI_PMCSR;
13153 13184 break;
13154 13185 /*
13155 13186 * The following capabilities are valid. Any others
13156 13187 * will cause a message to be logged.
13157 13188 */
13158 13189 case PCI_CAP_ID_VPD:
13159 13190 case PCI_CAP_ID_MSI:
13160 13191 case PCI_CAP_ID_PCIX:
13161 13192 case PCI_CAP_ID_PCI_E:
13162 13193 case PCI_CAP_ID_MSI_X:
13163 13194 break;
13164 13195 default:
13165 13196 mptsas_log(mpt, CE_NOTE,
13166 13197 "?mptsas%d unrecognized capability "
13167 13198 "0x%x.\n", mpt->m_instance, cap);
13168 13199 break;
13169 13200 }
13170 13201
13171 13202 /*
13172 13203 * Get next capabilities pointer and clear bits 0,1.
13173 13204 */
13174 13205 caps_ptr = P2ALIGN(pci_config_get8(mpt->m_config_handle,
13175 13206 (caps_ptr + PCI_CAP_NEXT_PTR)), 4);
13176 13207 }
13177 13208 return (TRUE);
13178 13209 }
13179 13210
13180 13211 static int
13181 13212 mptsas_init_pm(mptsas_t *mpt)
13182 13213 {
13183 13214 char pmc_name[16];
13184 13215 char *pmc[] = {
13185 13216 NULL,
13186 13217 "0=Off (PCI D3 State)",
13187 13218 "3=On (PCI D0 State)",
13188 13219 NULL
13189 13220 };
13190 13221 uint16_t pmcsr_stat;
13191 13222
13192 13223 if (mptsas_get_pci_cap(mpt) == FALSE) {
13193 13224 return (DDI_FAILURE);
13194 13225 }
13195 13226 /*
13196 13227 * If PCI's capability does not support PM, then don't need
13197 13228 * to registe the pm-components
13198 13229 */
13199 13230 if (!(mpt->m_options & MPTSAS_OPT_PM))
13200 13231 return (DDI_SUCCESS);
13201 13232 /*
13202 13233 * If power management is supported by this chip, create
13203 13234 * pm-components property for the power management framework
13204 13235 */
13205 13236 (void) sprintf(pmc_name, "NAME=mptsas%d", mpt->m_instance);
13206 13237 pmc[0] = pmc_name;
13207 13238 if (ddi_prop_update_string_array(DDI_DEV_T_NONE, mpt->m_dip,
13208 13239 "pm-components", pmc, 3) != DDI_PROP_SUCCESS) {
13209 13240 mpt->m_options &= ~MPTSAS_OPT_PM;
13210 13241 mptsas_log(mpt, CE_WARN,
13211 13242 "mptsas%d: pm-component property creation failed.",
13212 13243 mpt->m_instance);
13213 13244 return (DDI_FAILURE);
13214 13245 }
13215 13246
13216 13247 /*
13217 13248 * Power on device.
13218 13249 */
13219 13250 (void) pm_busy_component(mpt->m_dip, 0);
13220 13251 pmcsr_stat = pci_config_get16(mpt->m_config_handle,
13221 13252 mpt->m_pmcsr_offset);
13222 13253 if ((pmcsr_stat & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_D0) {
13223 13254 mptsas_log(mpt, CE_WARN, "mptsas%d: Power up the device",
13224 13255 mpt->m_instance);
13225 13256 pci_config_put16(mpt->m_config_handle, mpt->m_pmcsr_offset,
13226 13257 PCI_PMCSR_D0);
13227 13258 }
13228 13259 if (pm_power_has_changed(mpt->m_dip, 0, PM_LEVEL_D0) != DDI_SUCCESS) {
13229 13260 mptsas_log(mpt, CE_WARN, "pm_power_has_changed failed");
13230 13261 return (DDI_FAILURE);
13231 13262 }
13232 13263 mpt->m_power_level = PM_LEVEL_D0;
13233 13264 /*
13234 13265 * Set pm idle delay.
13235 13266 */
13236 13267 mpt->m_pm_idle_delay = ddi_prop_get_int(DDI_DEV_T_ANY,
13237 13268 mpt->m_dip, 0, "mptsas-pm-idle-delay", MPTSAS_PM_IDLE_TIMEOUT);
13238 13269
13239 13270 return (DDI_SUCCESS);
13240 13271 }
13241 13272
13242 13273 static int
13243 13274 mptsas_register_intrs(mptsas_t *mpt)
13244 13275 {
13245 13276 dev_info_t *dip;
13246 13277 int intr_types;
13247 13278
13248 13279 dip = mpt->m_dip;
13249 13280
13250 13281 /* Get supported interrupt types */
13251 13282 if (ddi_intr_get_supported_types(dip, &intr_types) != DDI_SUCCESS) {
13252 13283 mptsas_log(mpt, CE_WARN, "ddi_intr_get_supported_types "
13253 13284 "failed\n");
13254 13285 return (FALSE);
13255 13286 }
13256 13287
13257 13288 NDBG6(("ddi_intr_get_supported_types() returned: 0x%x", intr_types));
13258 13289
13259 13290 /*
13260 13291 * Try MSI, but fall back to FIXED
13261 13292 */
13262 13293 if (mptsas_enable_msi && (intr_types & DDI_INTR_TYPE_MSI)) {
13263 13294 if (mptsas_add_intrs(mpt, DDI_INTR_TYPE_MSI) == DDI_SUCCESS) {
13264 13295 NDBG0(("Using MSI interrupt type"));
13265 13296 mpt->m_intr_type = DDI_INTR_TYPE_MSI;
13266 13297 return (TRUE);
13267 13298 }
13268 13299 }
13269 13300 if (intr_types & DDI_INTR_TYPE_FIXED) {
13270 13301 if (mptsas_add_intrs(mpt, DDI_INTR_TYPE_FIXED) == DDI_SUCCESS) {
13271 13302 NDBG0(("Using FIXED interrupt type"));
13272 13303 mpt->m_intr_type = DDI_INTR_TYPE_FIXED;
13273 13304 return (TRUE);
13274 13305 } else {
13275 13306 NDBG0(("FIXED interrupt registration failed"));
13276 13307 return (FALSE);
13277 13308 }
13278 13309 }
13279 13310
13280 13311 return (FALSE);
13281 13312 }
13282 13313
13283 13314 static void
13284 13315 mptsas_unregister_intrs(mptsas_t *mpt)
13285 13316 {
13286 13317 mptsas_rem_intrs(mpt);
13287 13318 }
13288 13319
13289 13320 /*
13290 13321 * mptsas_add_intrs:
13291 13322 *
13292 13323 * Register FIXED or MSI interrupts.
13293 13324 */
13294 13325 static int
13295 13326 mptsas_add_intrs(mptsas_t *mpt, int intr_type)
13296 13327 {
13297 13328 dev_info_t *dip = mpt->m_dip;
13298 13329 int avail, actual, count = 0;
13299 13330 int i, flag, ret;
13300 13331
13301 13332 NDBG6(("mptsas_add_intrs:interrupt type 0x%x", intr_type));
13302 13333
13303 13334 /* Get number of interrupts */
13304 13335 ret = ddi_intr_get_nintrs(dip, intr_type, &count);
13305 13336 if ((ret != DDI_SUCCESS) || (count <= 0)) {
13306 13337 mptsas_log(mpt, CE_WARN, "ddi_intr_get_nintrs() failed, "
13307 13338 "ret %d count %d\n", ret, count);
13308 13339
13309 13340 return (DDI_FAILURE);
13310 13341 }
13311 13342
13312 13343 /* Get number of available interrupts */
13313 13344 ret = ddi_intr_get_navail(dip, intr_type, &avail);
13314 13345 if ((ret != DDI_SUCCESS) || (avail == 0)) {
13315 13346 mptsas_log(mpt, CE_WARN, "ddi_intr_get_navail() failed, "
13316 13347 "ret %d avail %d\n", ret, avail);
13317 13348
13318 13349 return (DDI_FAILURE);
13319 13350 }
13320 13351
13321 13352 if (avail < count) {
13322 13353 mptsas_log(mpt, CE_NOTE, "ddi_intr_get_nvail returned %d, "
13323 13354 "navail() returned %d", count, avail);
13324 13355 }
13325 13356
13326 13357 /* Mpt only have one interrupt routine */
13327 13358 if ((intr_type == DDI_INTR_TYPE_MSI) && (count > 1)) {
13328 13359 count = 1;
13329 13360 }
13330 13361
13331 13362 /* Allocate an array of interrupt handles */
13332 13363 mpt->m_intr_size = count * sizeof (ddi_intr_handle_t);
13333 13364 mpt->m_htable = kmem_alloc(mpt->m_intr_size, KM_SLEEP);
13334 13365
13335 13366 flag = DDI_INTR_ALLOC_NORMAL;
13336 13367
13337 13368 /* call ddi_intr_alloc() */
13338 13369 ret = ddi_intr_alloc(dip, mpt->m_htable, intr_type, 0,
13339 13370 count, &actual, flag);
13340 13371
13341 13372 if ((ret != DDI_SUCCESS) || (actual == 0)) {
13342 13373 mptsas_log(mpt, CE_WARN, "ddi_intr_alloc() failed, ret %d\n",
13343 13374 ret);
13344 13375 kmem_free(mpt->m_htable, mpt->m_intr_size);
13345 13376 return (DDI_FAILURE);
13346 13377 }
13347 13378
13348 13379 /* use interrupt count returned or abort? */
13349 13380 if (actual < count) {
13350 13381 mptsas_log(mpt, CE_NOTE, "Requested: %d, Received: %d\n",
13351 13382 count, actual);
13352 13383 }
13353 13384
13354 13385 mpt->m_intr_cnt = actual;
13355 13386
13356 13387 /*
13357 13388 * Get priority for first msi, assume remaining are all the same
13358 13389 */
13359 13390 if ((ret = ddi_intr_get_pri(mpt->m_htable[0],
13360 13391 &mpt->m_intr_pri)) != DDI_SUCCESS) {
13361 13392 mptsas_log(mpt, CE_WARN, "ddi_intr_get_pri() failed %d\n", ret);
13362 13393
13363 13394 /* Free already allocated intr */
13364 13395 for (i = 0; i < actual; i++) {
13365 13396 (void) ddi_intr_free(mpt->m_htable[i]);
13366 13397 }
13367 13398
13368 13399 kmem_free(mpt->m_htable, mpt->m_intr_size);
13369 13400 return (DDI_FAILURE);
13370 13401 }
13371 13402
13372 13403 /* Test for high level mutex */
13373 13404 if (mpt->m_intr_pri >= ddi_intr_get_hilevel_pri()) {
13374 13405 mptsas_log(mpt, CE_WARN, "mptsas_add_intrs: "
13375 13406 "Hi level interrupt not supported\n");
13376 13407
13377 13408 /* Free already allocated intr */
13378 13409 for (i = 0; i < actual; i++) {
13379 13410 (void) ddi_intr_free(mpt->m_htable[i]);
13380 13411 }
13381 13412
13382 13413 kmem_free(mpt->m_htable, mpt->m_intr_size);
13383 13414 return (DDI_FAILURE);
13384 13415 }
13385 13416
13386 13417 /* Call ddi_intr_add_handler() */
13387 13418 for (i = 0; i < actual; i++) {
13388 13419 if ((ret = ddi_intr_add_handler(mpt->m_htable[i], mptsas_intr,
13389 13420 (caddr_t)mpt, (caddr_t)(uintptr_t)i)) != DDI_SUCCESS) {
13390 13421 mptsas_log(mpt, CE_WARN, "ddi_intr_add_handler() "
13391 13422 "failed %d\n", ret);
13392 13423
13393 13424 /* Free already allocated intr */
13394 13425 for (i = 0; i < actual; i++) {
13395 13426 (void) ddi_intr_free(mpt->m_htable[i]);
13396 13427 }
13397 13428
13398 13429 kmem_free(mpt->m_htable, mpt->m_intr_size);
13399 13430 return (DDI_FAILURE);
13400 13431 }
13401 13432 }
13402 13433
13403 13434 if ((ret = ddi_intr_get_cap(mpt->m_htable[0], &mpt->m_intr_cap))
13404 13435 != DDI_SUCCESS) {
13405 13436 mptsas_log(mpt, CE_WARN, "ddi_intr_get_cap() failed %d\n", ret);
13406 13437
13407 13438 /* Free already allocated intr */
13408 13439 for (i = 0; i < actual; i++) {
13409 13440 (void) ddi_intr_free(mpt->m_htable[i]);
13410 13441 }
13411 13442
13412 13443 kmem_free(mpt->m_htable, mpt->m_intr_size);
13413 13444 return (DDI_FAILURE);
13414 13445 }
13415 13446
13416 13447 /*
13417 13448 * Enable interrupts
13418 13449 */
13419 13450 if (mpt->m_intr_cap & DDI_INTR_FLAG_BLOCK) {
13420 13451 /* Call ddi_intr_block_enable() for MSI interrupts */
13421 13452 (void) ddi_intr_block_enable(mpt->m_htable, mpt->m_intr_cnt);
13422 13453 } else {
13423 13454 /* Call ddi_intr_enable for MSI or FIXED interrupts */
13424 13455 for (i = 0; i < mpt->m_intr_cnt; i++) {
13425 13456 (void) ddi_intr_enable(mpt->m_htable[i]);
13426 13457 }
13427 13458 }
13428 13459 return (DDI_SUCCESS);
13429 13460 }
13430 13461
13431 13462 /*
13432 13463 * mptsas_rem_intrs:
13433 13464 *
13434 13465 * Unregister FIXED or MSI interrupts
13435 13466 */
13436 13467 static void
13437 13468 mptsas_rem_intrs(mptsas_t *mpt)
13438 13469 {
13439 13470 int i;
13440 13471
13441 13472 NDBG6(("mptsas_rem_intrs"));
13442 13473
13443 13474 /* Disable all interrupts */
13444 13475 if (mpt->m_intr_cap & DDI_INTR_FLAG_BLOCK) {
13445 13476 /* Call ddi_intr_block_disable() */
13446 13477 (void) ddi_intr_block_disable(mpt->m_htable, mpt->m_intr_cnt);
13447 13478 } else {
13448 13479 for (i = 0; i < mpt->m_intr_cnt; i++) {
13449 13480 (void) ddi_intr_disable(mpt->m_htable[i]);
13450 13481 }
13451 13482 }
13452 13483
13453 13484 /* Call ddi_intr_remove_handler() */
13454 13485 for (i = 0; i < mpt->m_intr_cnt; i++) {
13455 13486 (void) ddi_intr_remove_handler(mpt->m_htable[i]);
13456 13487 (void) ddi_intr_free(mpt->m_htable[i]);
13457 13488 }
13458 13489
13459 13490 kmem_free(mpt->m_htable, mpt->m_intr_size);
13460 13491 }
13461 13492
13462 13493 /*
13463 13494 * The IO fault service error handling callback function
13464 13495 */
13465 13496 /*ARGSUSED*/
13466 13497 static int
13467 13498 mptsas_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, const void *impl_data)
13468 13499 {
13469 13500 /*
13470 13501 * as the driver can always deal with an error in any dma or
13471 13502 * access handle, we can just return the fme_status value.
13472 13503 */
13473 13504 pci_ereport_post(dip, err, NULL);
13474 13505 return (err->fme_status);
13475 13506 }
13476 13507
13477 13508 /*
13478 13509 * mptsas_fm_init - initialize fma capabilities and register with IO
13479 13510 * fault services.
13480 13511 */
13481 13512 static void
13482 13513 mptsas_fm_init(mptsas_t *mpt)
13483 13514 {
13484 13515 /*
13485 13516 * Need to change iblock to priority for new MSI intr
13486 13517 */
13487 13518 ddi_iblock_cookie_t fm_ibc;
13488 13519
13489 13520 /* Only register with IO Fault Services if we have some capability */
13490 13521 if (mpt->m_fm_capabilities) {
13491 13522 /* Adjust access and dma attributes for FMA */
13492 13523 mpt->m_reg_acc_attr.devacc_attr_access = DDI_FLAGERR_ACC;
13493 13524 mpt->m_msg_dma_attr.dma_attr_flags |= DDI_DMA_FLAGERR;
13494 13525 mpt->m_io_dma_attr.dma_attr_flags |= DDI_DMA_FLAGERR;
13495 13526
13496 13527 /*
13497 13528 * Register capabilities with IO Fault Services.
13498 13529 * mpt->m_fm_capabilities will be updated to indicate
13499 13530 * capabilities actually supported (not requested.)
13500 13531 */
13501 13532 ddi_fm_init(mpt->m_dip, &mpt->m_fm_capabilities, &fm_ibc);
13502 13533
13503 13534 /*
13504 13535 * Initialize pci ereport capabilities if ereport
13505 13536 * capable (should always be.)
13506 13537 */
13507 13538 if (DDI_FM_EREPORT_CAP(mpt->m_fm_capabilities) ||
13508 13539 DDI_FM_ERRCB_CAP(mpt->m_fm_capabilities)) {
13509 13540 pci_ereport_setup(mpt->m_dip);
13510 13541 }
13511 13542
13512 13543 /*
13513 13544 * Register error callback if error callback capable.
13514 13545 */
13515 13546 if (DDI_FM_ERRCB_CAP(mpt->m_fm_capabilities)) {
13516 13547 ddi_fm_handler_register(mpt->m_dip,
13517 13548 mptsas_fm_error_cb, (void *) mpt);
13518 13549 }
13519 13550 }
13520 13551 }
13521 13552
13522 13553 /*
13523 13554 * mptsas_fm_fini - Releases fma capabilities and un-registers with IO
13524 13555 * fault services.
13525 13556 *
13526 13557 */
13527 13558 static void
13528 13559 mptsas_fm_fini(mptsas_t *mpt)
13529 13560 {
13530 13561 /* Only unregister FMA capabilities if registered */
13531 13562 if (mpt->m_fm_capabilities) {
13532 13563
13533 13564 /*
13534 13565 * Un-register error callback if error callback capable.
13535 13566 */
13536 13567
13537 13568 if (DDI_FM_ERRCB_CAP(mpt->m_fm_capabilities)) {
13538 13569 ddi_fm_handler_unregister(mpt->m_dip);
13539 13570 }
13540 13571
13541 13572 /*
13542 13573 * Release any resources allocated by pci_ereport_setup()
13543 13574 */
13544 13575
13545 13576 if (DDI_FM_EREPORT_CAP(mpt->m_fm_capabilities) ||
13546 13577 DDI_FM_ERRCB_CAP(mpt->m_fm_capabilities)) {
13547 13578 pci_ereport_teardown(mpt->m_dip);
13548 13579 }
13549 13580
13550 13581 /* Unregister from IO Fault Services */
13551 13582 ddi_fm_fini(mpt->m_dip);
13552 13583
13553 13584 /* Adjust access and dma attributes for FMA */
13554 13585 mpt->m_reg_acc_attr.devacc_attr_access = DDI_DEFAULT_ACC;
13555 13586 mpt->m_msg_dma_attr.dma_attr_flags &= ~DDI_DMA_FLAGERR;
13556 13587 mpt->m_io_dma_attr.dma_attr_flags &= ~DDI_DMA_FLAGERR;
13557 13588
13558 13589 }
13559 13590 }
13560 13591
13561 13592 int
13562 13593 mptsas_check_acc_handle(ddi_acc_handle_t handle)
13563 13594 {
13564 13595 ddi_fm_error_t de;
13565 13596
13566 13597 if (handle == NULL)
13567 13598 return (DDI_FAILURE);
13568 13599 ddi_fm_acc_err_get(handle, &de, DDI_FME_VER0);
13569 13600 return (de.fme_status);
13570 13601 }
13571 13602
13572 13603 int
13573 13604 mptsas_check_dma_handle(ddi_dma_handle_t handle)
13574 13605 {
13575 13606 ddi_fm_error_t de;
13576 13607
13577 13608 if (handle == NULL)
13578 13609 return (DDI_FAILURE);
13579 13610 ddi_fm_dma_err_get(handle, &de, DDI_FME_VER0);
13580 13611 return (de.fme_status);
13581 13612 }
13582 13613
13583 13614 void
13584 13615 mptsas_fm_ereport(mptsas_t *mpt, char *detail)
13585 13616 {
13586 13617 uint64_t ena;
13587 13618 char buf[FM_MAX_CLASS];
13588 13619
13589 13620 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", DDI_FM_DEVICE, detail);
13590 13621 ena = fm_ena_generate(0, FM_ENA_FMT1);
13591 13622 if (DDI_FM_EREPORT_CAP(mpt->m_fm_capabilities)) {
13592 13623 ddi_fm_ereport_post(mpt->m_dip, buf, ena, DDI_NOSLEEP,
13593 13624 FM_VERSION, DATA_TYPE_UINT8, FM_EREPORT_VERS0, NULL);
13594 13625 }
13595 13626 }
13596 13627
13597 13628 static int
13598 13629 mptsas_get_target_device_info(mptsas_t *mpt, uint32_t page_address,
13599 13630 uint16_t *dev_handle, mptsas_target_t **pptgt)
13600 13631 {
13601 13632 int rval;
13602 13633 uint32_t dev_info;
13603 13634 uint64_t sas_wwn;
13604 13635 mptsas_phymask_t phymask;
13605 13636 uint8_t physport, phynum, config, disk;
13606 13637 uint64_t devicename;
13607 13638 uint16_t pdev_hdl;
13608 13639 mptsas_target_t *tmp_tgt = NULL;
13609 13640 uint16_t bay_num, enclosure, io_flags;
13610 13641
13611 13642 ASSERT(*pptgt == NULL);
13612 13643
13613 13644 rval = mptsas_get_sas_device_page0(mpt, page_address, dev_handle,
13614 13645 &sas_wwn, &dev_info, &physport, &phynum, &pdev_hdl,
13615 13646 &bay_num, &enclosure, &io_flags);
13616 13647 if (rval != DDI_SUCCESS) {
13617 13648 rval = DEV_INFO_FAIL_PAGE0;
13618 13649 return (rval);
13619 13650 }
13620 13651
13621 13652 if ((dev_info & (MPI2_SAS_DEVICE_INFO_SSP_TARGET |
13622 13653 MPI2_SAS_DEVICE_INFO_SATA_DEVICE |
13623 13654 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) == NULL) {
13624 13655 rval = DEV_INFO_WRONG_DEVICE_TYPE;
13625 13656 return (rval);
13626 13657 }
13627 13658
13628 13659 /*
13629 13660 * Check if the dev handle is for a Phys Disk. If so, set return value
13630 13661 * and exit. Don't add Phys Disks to hash.
13631 13662 */
13632 13663 for (config = 0; config < mpt->m_num_raid_configs; config++) {
13633 13664 for (disk = 0; disk < MPTSAS_MAX_DISKS_IN_CONFIG; disk++) {
13634 13665 if (*dev_handle == mpt->m_raidconfig[config].
13635 13666 m_physdisk_devhdl[disk]) {
13636 13667 rval = DEV_INFO_PHYS_DISK;
13637 13668 return (rval);
13638 13669 }
13639 13670 }
13640 13671 }
13641 13672
13642 13673 /*
13643 13674 * Get SATA Device Name from SAS device page0 for
13644 13675 * sata device, if device name doesn't exist, set mta_wwn to
13645 13676 * 0 for direct attached SATA. For the device behind the expander
13646 13677 * we still can use STP address assigned by expander.
13647 13678 */
13648 13679 if (dev_info & (MPI2_SAS_DEVICE_INFO_SATA_DEVICE |
13649 13680 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) {
13650 13681 /* alloc a temporary target to send the cmd to */
13651 13682 tmp_tgt = mptsas_tgt_alloc(mpt->m_tmp_targets, *dev_handle,
13652 13683 0, dev_info, 0, 0);
13653 13684 mutex_exit(&mpt->m_mutex);
13654 13685
13655 13686 devicename = mptsas_get_sata_guid(mpt, tmp_tgt, 0);
13656 13687
13657 13688 if (devicename == -1) {
13658 13689 mutex_enter(&mpt->m_mutex);
13659 13690 refhash_remove(mpt->m_tmp_targets, tmp_tgt);
13660 13691 rval = DEV_INFO_FAIL_GUID;
13661 13692 return (rval);
13662 13693 }
13663 13694
13664 13695 if (devicename != 0 && (((devicename >> 56) & 0xf0) == 0x50)) {
13665 13696 sas_wwn = devicename;
13666 13697 } else if (dev_info & MPI2_SAS_DEVICE_INFO_DIRECT_ATTACH) {
13667 13698 sas_wwn = 0;
13668 13699 }
13669 13700
13670 13701 mutex_enter(&mpt->m_mutex);
13671 13702 refhash_remove(mpt->m_tmp_targets, tmp_tgt);
13672 13703 }
13673 13704
13674 13705 phymask = mptsas_physport_to_phymask(mpt, physport);
13675 13706 *pptgt = mptsas_tgt_alloc(mpt->m_targets, *dev_handle, sas_wwn,
13676 13707 dev_info, phymask, phynum);
13677 13708 if (*pptgt == NULL) {
13678 13709 mptsas_log(mpt, CE_WARN, "Failed to allocated target"
13679 13710 "structure!");
13680 13711 rval = DEV_INFO_FAIL_ALLOC;
13681 13712 return (rval);
13682 13713 }
13683 13714 (*pptgt)->m_io_flags = io_flags;
13684 13715 (*pptgt)->m_enclosure = enclosure;
13685 13716 (*pptgt)->m_slot_num = bay_num;
13686 13717 return (DEV_INFO_SUCCESS);
13687 13718 }
13688 13719
13689 13720 uint64_t
13690 13721 mptsas_get_sata_guid(mptsas_t *mpt, mptsas_target_t *ptgt, int lun)
13691 13722 {
13692 13723 uint64_t sata_guid = 0, *pwwn = NULL;
13693 13724 int target = ptgt->m_devhdl;
13694 13725 uchar_t *inq83 = NULL;
13695 13726 int inq83_len = 0xFF;
13696 13727 uchar_t *dblk = NULL;
13697 13728 int inq83_retry = 3;
13698 13729 int rval = DDI_FAILURE;
13699 13730
13700 13731 inq83 = kmem_zalloc(inq83_len, KM_SLEEP);
13701 13732
13702 13733 inq83_retry:
13703 13734 rval = mptsas_inquiry(mpt, ptgt, lun, 0x83, inq83,
13704 13735 inq83_len, NULL, 1);
13705 13736 if (rval != DDI_SUCCESS) {
13706 13737 mptsas_log(mpt, CE_WARN, "!mptsas request inquiry page "
13707 13738 "0x83 for target:%x, lun:%x failed!", target, lun);
13708 13739 sata_guid = -1;
13709 13740 goto out;
13710 13741 }
13711 13742 /* According to SAT2, the first descriptor is logic unit name */
13712 13743 dblk = &inq83[4];
13713 13744 if ((dblk[1] & 0x30) != 0) {
13714 13745 mptsas_log(mpt, CE_WARN, "!Descriptor is not lun associated.");
13715 13746 goto out;
13716 13747 }
13717 13748 pwwn = (uint64_t *)(void *)(&dblk[4]);
13718 13749 if ((dblk[4] & 0xf0) == 0x50) {
13719 13750 sata_guid = BE_64(*pwwn);
13720 13751 goto out;
13721 13752 } else if (dblk[4] == 'A') {
13722 13753 NDBG20(("SATA drive has no NAA format GUID."));
13723 13754 goto out;
13724 13755 } else {
13725 13756 /* The data is not ready, wait and retry */
13726 13757 inq83_retry--;
13727 13758 if (inq83_retry <= 0) {
13728 13759 goto out;
13729 13760 }
13730 13761 NDBG20(("The GUID is not ready, retry..."));
13731 13762 delay(1 * drv_usectohz(1000000));
13732 13763 goto inq83_retry;
13733 13764 }
13734 13765 out:
13735 13766 kmem_free(inq83, inq83_len);
13736 13767 return (sata_guid);
13737 13768 }
13738 13769
13739 13770 static int
13740 13771 mptsas_inquiry(mptsas_t *mpt, mptsas_target_t *ptgt, int lun, uchar_t page,
13741 13772 unsigned char *buf, int len, int *reallen, uchar_t evpd)
13742 13773 {
13743 13774 uchar_t cdb[CDB_GROUP0];
13744 13775 struct scsi_address ap;
13745 13776 struct buf *data_bp = NULL;
13746 13777 int resid = 0;
13747 13778 int ret = DDI_FAILURE;
13748 13779
13749 13780 ASSERT(len <= 0xffff);
13750 13781
13751 13782 ap.a_target = MPTSAS_INVALID_DEVHDL;
13752 13783 ap.a_lun = (uchar_t)(lun);
13753 13784 ap.a_hba_tran = mpt->m_tran;
13754 13785
13755 13786 data_bp = scsi_alloc_consistent_buf(&ap,
13756 13787 (struct buf *)NULL, len, B_READ, NULL_FUNC, NULL);
13757 13788 if (data_bp == NULL) {
13758 13789 return (ret);
13759 13790 }
13760 13791 bzero(cdb, CDB_GROUP0);
13761 13792 cdb[0] = SCMD_INQUIRY;
13762 13793 cdb[1] = evpd;
13763 13794 cdb[2] = page;
13764 13795 cdb[3] = (len & 0xff00) >> 8;
13765 13796 cdb[4] = (len & 0x00ff);
13766 13797 cdb[5] = 0;
13767 13798
13768 13799 ret = mptsas_send_scsi_cmd(mpt, &ap, ptgt, &cdb[0], CDB_GROUP0, data_bp,
13769 13800 &resid);
13770 13801 if (ret == DDI_SUCCESS) {
13771 13802 if (reallen) {
13772 13803 *reallen = len - resid;
13773 13804 }
13774 13805 bcopy((caddr_t)data_bp->b_un.b_addr, buf, len);
13775 13806 }
13776 13807 if (data_bp) {
13777 13808 scsi_free_consistent_buf(data_bp);
13778 13809 }
13779 13810 return (ret);
13780 13811 }
13781 13812
13782 13813 static int
13783 13814 mptsas_send_scsi_cmd(mptsas_t *mpt, struct scsi_address *ap,
13784 13815 mptsas_target_t *ptgt, uchar_t *cdb, int cdblen, struct buf *data_bp,
13785 13816 int *resid)
13786 13817 {
13787 13818 struct scsi_pkt *pktp = NULL;
13788 13819 scsi_hba_tran_t *tran_clone = NULL;
13789 13820 mptsas_tgt_private_t *tgt_private = NULL;
13790 13821 int ret = DDI_FAILURE;
13791 13822
13792 13823 /*
13793 13824 * scsi_hba_tran_t->tran_tgt_private is used to pass the address
13794 13825 * information to scsi_init_pkt, allocate a scsi_hba_tran structure
13795 13826 * to simulate the cmds from sd
13796 13827 */
13797 13828 tran_clone = kmem_alloc(
13798 13829 sizeof (scsi_hba_tran_t), KM_SLEEP);
13799 13830 if (tran_clone == NULL) {
13800 13831 goto out;
13801 13832 }
13802 13833 bcopy((caddr_t)mpt->m_tran,
13803 13834 (caddr_t)tran_clone, sizeof (scsi_hba_tran_t));
13804 13835 tgt_private = kmem_alloc(
13805 13836 sizeof (mptsas_tgt_private_t), KM_SLEEP);
13806 13837 if (tgt_private == NULL) {
13807 13838 goto out;
13808 13839 }
13809 13840 tgt_private->t_lun = ap->a_lun;
13810 13841 tgt_private->t_private = ptgt;
13811 13842 tran_clone->tran_tgt_private = tgt_private;
13812 13843 ap->a_hba_tran = tran_clone;
13813 13844
13814 13845 pktp = scsi_init_pkt(ap, (struct scsi_pkt *)NULL,
13815 13846 data_bp, cdblen, sizeof (struct scsi_arq_status),
13816 13847 0, PKT_CONSISTENT, NULL, NULL);
13817 13848 if (pktp == NULL) {
13818 13849 goto out;
13819 13850 }
13820 13851 bcopy(cdb, pktp->pkt_cdbp, cdblen);
13821 13852 pktp->pkt_flags = FLAG_NOPARITY;
13822 13853 if (scsi_poll(pktp) < 0) {
13823 13854 goto out;
13824 13855 }
13825 13856 if (((struct scsi_status *)pktp->pkt_scbp)->sts_chk) {
13826 13857 goto out;
13827 13858 }
13828 13859 if (resid != NULL) {
13829 13860 *resid = pktp->pkt_resid;
13830 13861 }
13831 13862
13832 13863 ret = DDI_SUCCESS;
13833 13864 out:
13834 13865 if (pktp) {
13835 13866 scsi_destroy_pkt(pktp);
13836 13867 }
13837 13868 if (tran_clone) {
13838 13869 kmem_free(tran_clone, sizeof (scsi_hba_tran_t));
13839 13870 }
13840 13871 if (tgt_private) {
13841 13872 kmem_free(tgt_private, sizeof (mptsas_tgt_private_t));
13842 13873 }
13843 13874 return (ret);
13844 13875 }
13845 13876 static int
13846 13877 mptsas_parse_address(char *name, uint64_t *wwid, uint8_t *phy, int *lun)
13847 13878 {
13848 13879 char *cp = NULL;
13849 13880 char *ptr = NULL;
13850 13881 size_t s = 0;
13851 13882 char *wwid_str = NULL;
13852 13883 char *lun_str = NULL;
13853 13884 long lunnum;
13854 13885 long phyid = -1;
13855 13886 int rc = DDI_FAILURE;
13856 13887
13857 13888 ptr = name;
13858 13889 ASSERT(ptr[0] == 'w' || ptr[0] == 'p');
13859 13890 ptr++;
13860 13891 if ((cp = strchr(ptr, ',')) == NULL) {
13861 13892 return (DDI_FAILURE);
13862 13893 }
13863 13894
13864 13895 wwid_str = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
13865 13896 s = (uintptr_t)cp - (uintptr_t)ptr;
13866 13897
13867 13898 bcopy(ptr, wwid_str, s);
13868 13899 wwid_str[s] = '\0';
13869 13900
13870 13901 ptr = ++cp;
13871 13902
13872 13903 if ((cp = strchr(ptr, '\0')) == NULL) {
13873 13904 goto out;
13874 13905 }
13875 13906 lun_str = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
13876 13907 s = (uintptr_t)cp - (uintptr_t)ptr;
13877 13908
13878 13909 bcopy(ptr, lun_str, s);
13879 13910 lun_str[s] = '\0';
13880 13911
13881 13912 if (name[0] == 'p') {
13882 13913 rc = ddi_strtol(wwid_str, NULL, 0x10, &phyid);
13883 13914 } else {
13884 13915 rc = scsi_wwnstr_to_wwn(wwid_str, wwid);
13885 13916 }
13886 13917 if (rc != DDI_SUCCESS)
13887 13918 goto out;
13888 13919
13889 13920 if (phyid != -1) {
13890 13921 ASSERT(phyid < MPTSAS_MAX_PHYS);
13891 13922 *phy = (uint8_t)phyid;
13892 13923 }
13893 13924 rc = ddi_strtol(lun_str, NULL, 0x10, &lunnum);
13894 13925 if (rc != 0)
13895 13926 goto out;
13896 13927
13897 13928 *lun = (int)lunnum;
13898 13929 rc = DDI_SUCCESS;
13899 13930 out:
13900 13931 if (wwid_str)
13901 13932 kmem_free(wwid_str, SCSI_MAXNAMELEN);
13902 13933 if (lun_str)
13903 13934 kmem_free(lun_str, SCSI_MAXNAMELEN);
13904 13935
13905 13936 return (rc);
13906 13937 }
13907 13938
13908 13939 /*
13909 13940 * mptsas_parse_smp_name() is to parse sas wwn string
13910 13941 * which format is "wWWN"
13911 13942 */
13912 13943 static int
13913 13944 mptsas_parse_smp_name(char *name, uint64_t *wwn)
13914 13945 {
13915 13946 char *ptr = name;
13916 13947
13917 13948 if (*ptr != 'w') {
13918 13949 return (DDI_FAILURE);
13919 13950 }
13920 13951
13921 13952 ptr++;
13922 13953 if (scsi_wwnstr_to_wwn(ptr, wwn)) {
13923 13954 return (DDI_FAILURE);
13924 13955 }
13925 13956 return (DDI_SUCCESS);
13926 13957 }
13927 13958
13928 13959 static int
13929 13960 mptsas_bus_config(dev_info_t *pdip, uint_t flag,
13930 13961 ddi_bus_config_op_t op, void *arg, dev_info_t **childp)
13931 13962 {
13932 13963 int ret = NDI_FAILURE;
13933 13964 int circ = 0;
13934 13965 int circ1 = 0;
13935 13966 mptsas_t *mpt;
13936 13967 char *ptr = NULL;
13937 13968 char *devnm = NULL;
13938 13969 uint64_t wwid = 0;
13939 13970 uint8_t phy = 0xFF;
13940 13971 int lun = 0;
13941 13972 uint_t mflags = flag;
13942 13973 int bconfig = TRUE;
13943 13974
13944 13975 if (scsi_hba_iport_unit_address(pdip) == 0) {
13945 13976 return (DDI_FAILURE);
13946 13977 }
13947 13978
13948 13979 mpt = DIP2MPT(pdip);
13949 13980 if (!mpt) {
13950 13981 return (DDI_FAILURE);
13951 13982 }
13952 13983 /*
13953 13984 * Hold the nexus across the bus_config
13954 13985 */
13955 13986 ndi_devi_enter(scsi_vhci_dip, &circ);
13956 13987 ndi_devi_enter(pdip, &circ1);
13957 13988 switch (op) {
13958 13989 case BUS_CONFIG_ONE:
13959 13990 /* parse wwid/target name out of name given */
13960 13991 if ((ptr = strchr((char *)arg, '@')) == NULL) {
13961 13992 ret = NDI_FAILURE;
13962 13993 break;
13963 13994 }
13964 13995 ptr++;
13965 13996 if (strncmp((char *)arg, "smp", 3) == 0) {
13966 13997 /*
13967 13998 * This is a SMP target device
13968 13999 */
13969 14000 ret = mptsas_parse_smp_name(ptr, &wwid);
13970 14001 if (ret != DDI_SUCCESS) {
13971 14002 ret = NDI_FAILURE;
13972 14003 break;
13973 14004 }
13974 14005 ret = mptsas_config_smp(pdip, wwid, childp);
13975 14006 } else if ((ptr[0] == 'w') || (ptr[0] == 'p')) {
13976 14007 /*
13977 14008 * OBP could pass down a non-canonical form
13978 14009 * bootpath without LUN part when LUN is 0.
13979 14010 * So driver need adjust the string.
13980 14011 */
13981 14012 if (strchr(ptr, ',') == NULL) {
13982 14013 devnm = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
13983 14014 (void) sprintf(devnm, "%s,0", (char *)arg);
13984 14015 ptr = strchr(devnm, '@');
13985 14016 ptr++;
13986 14017 }
13987 14018
13988 14019 /*
13989 14020 * The device path is wWWID format and the device
13990 14021 * is not SMP target device.
13991 14022 */
13992 14023 ret = mptsas_parse_address(ptr, &wwid, &phy, &lun);
13993 14024 if (ret != DDI_SUCCESS) {
13994 14025 ret = NDI_FAILURE;
13995 14026 break;
13996 14027 }
13997 14028 *childp = NULL;
13998 14029 if (ptr[0] == 'w') {
13999 14030 ret = mptsas_config_one_addr(pdip, wwid,
14000 14031 lun, childp);
14001 14032 } else if (ptr[0] == 'p') {
14002 14033 ret = mptsas_config_one_phy(pdip, phy, lun,
14003 14034 childp);
14004 14035 }
14005 14036
14006 14037 /*
14007 14038 * If this is CD/DVD device in OBP path, the
14008 14039 * ndi_busop_bus_config can be skipped as config one
14009 14040 * operation is done above.
14010 14041 */
14011 14042 if ((ret == NDI_SUCCESS) && (*childp != NULL) &&
14012 14043 (strcmp(ddi_node_name(*childp), "cdrom") == 0) &&
14013 14044 (strncmp((char *)arg, "disk", 4) == 0)) {
14014 14045 bconfig = FALSE;
14015 14046 ndi_hold_devi(*childp);
14016 14047 }
14017 14048 } else {
14018 14049 ret = NDI_FAILURE;
14019 14050 break;
14020 14051 }
14021 14052
14022 14053 /*
14023 14054 * DDI group instructed us to use this flag.
14024 14055 */
14025 14056 mflags |= NDI_MDI_FALLBACK;
14026 14057 break;
14027 14058 case BUS_CONFIG_DRIVER:
14028 14059 case BUS_CONFIG_ALL:
14029 14060 mptsas_config_all(pdip);
14030 14061 ret = NDI_SUCCESS;
14031 14062 break;
14032 14063 }
14033 14064
14034 14065 if ((ret == NDI_SUCCESS) && bconfig) {
14035 14066 ret = ndi_busop_bus_config(pdip, mflags, op,
14036 14067 (devnm == NULL) ? arg : devnm, childp, 0);
14037 14068 }
14038 14069
14039 14070 ndi_devi_exit(pdip, circ1);
14040 14071 ndi_devi_exit(scsi_vhci_dip, circ);
14041 14072 if (devnm != NULL)
14042 14073 kmem_free(devnm, SCSI_MAXNAMELEN);
14043 14074 return (ret);
14044 14075 }
14045 14076
14046 14077 static int
14047 14078 mptsas_probe_lun(dev_info_t *pdip, int lun, dev_info_t **dip,
14048 14079 mptsas_target_t *ptgt)
14049 14080 {
14050 14081 int rval = DDI_FAILURE;
14051 14082 struct scsi_inquiry *sd_inq = NULL;
14052 14083 mptsas_t *mpt = DIP2MPT(pdip);
14053 14084
14054 14085 sd_inq = (struct scsi_inquiry *)kmem_alloc(SUN_INQSIZE, KM_SLEEP);
14055 14086
14056 14087 rval = mptsas_inquiry(mpt, ptgt, lun, 0, (uchar_t *)sd_inq,
14057 14088 SUN_INQSIZE, 0, (uchar_t)0);
14058 14089
14059 14090 if ((rval == DDI_SUCCESS) && MPTSAS_VALID_LUN(sd_inq)) {
14060 14091 rval = mptsas_create_lun(pdip, sd_inq, dip, ptgt, lun);
14061 14092 } else {
14062 14093 rval = DDI_FAILURE;
14063 14094 }
14064 14095
14065 14096 kmem_free(sd_inq, SUN_INQSIZE);
14066 14097 return (rval);
14067 14098 }
14068 14099
14069 14100 static int
14070 14101 mptsas_config_one_addr(dev_info_t *pdip, uint64_t sasaddr, int lun,
14071 14102 dev_info_t **lundip)
14072 14103 {
14073 14104 int rval;
14074 14105 mptsas_t *mpt = DIP2MPT(pdip);
14075 14106 int phymask;
14076 14107 mptsas_target_t *ptgt = NULL;
14077 14108
14078 14109 /*
14079 14110 * Get the physical port associated to the iport
14080 14111 */
14081 14112 phymask = ddi_prop_get_int(DDI_DEV_T_ANY, pdip, 0,
14082 14113 "phymask", 0);
14083 14114
14084 14115 ptgt = mptsas_wwid_to_ptgt(mpt, phymask, sasaddr);
14085 14116 if (ptgt == NULL) {
14086 14117 /*
14087 14118 * didn't match any device by searching
14088 14119 */
14089 14120 return (DDI_FAILURE);
14090 14121 }
14091 14122 /*
14092 14123 * If the LUN already exists and the status is online,
14093 14124 * we just return the pointer to dev_info_t directly.
14094 14125 * For the mdi_pathinfo node, we'll handle it in
14095 14126 * mptsas_create_virt_lun()
14096 14127 * TODO should be also in mptsas_handle_dr
14097 14128 */
14098 14129
14099 14130 *lundip = mptsas_find_child_addr(pdip, sasaddr, lun);
14100 14131 if (*lundip != NULL) {
14101 14132 /*
14102 14133 * TODO Another senario is, we hotplug the same disk
14103 14134 * on the same slot, the devhdl changed, is this
14104 14135 * possible?
14105 14136 * tgt_private->t_private != ptgt
14106 14137 */
14107 14138 if (sasaddr != ptgt->m_addr.mta_wwn) {
14108 14139 /*
14109 14140 * The device has changed although the devhdl is the
14110 14141 * same (Enclosure mapping mode, change drive on the
14111 14142 * same slot)
14112 14143 */
14113 14144 return (DDI_FAILURE);
14114 14145 }
14115 14146 return (DDI_SUCCESS);
14116 14147 }
14117 14148
14118 14149 if (phymask == 0) {
14119 14150 /*
14120 14151 * Configure IR volume
14121 14152 */
14122 14153 rval = mptsas_config_raid(pdip, ptgt->m_devhdl, lundip);
14123 14154 return (rval);
14124 14155 }
14125 14156 rval = mptsas_probe_lun(pdip, lun, lundip, ptgt);
14126 14157
14127 14158 return (rval);
14128 14159 }
14129 14160
14130 14161 static int
14131 14162 mptsas_config_one_phy(dev_info_t *pdip, uint8_t phy, int lun,
14132 14163 dev_info_t **lundip)
14133 14164 {
14134 14165 int rval;
14135 14166 mptsas_t *mpt = DIP2MPT(pdip);
14136 14167 mptsas_phymask_t phymask;
14137 14168 mptsas_target_t *ptgt = NULL;
14138 14169
14139 14170 /*
14140 14171 * Get the physical port associated to the iport
14141 14172 */
14142 14173 phymask = (mptsas_phymask_t)ddi_prop_get_int(DDI_DEV_T_ANY, pdip, 0,
14143 14174 "phymask", 0);
14144 14175
14145 14176 ptgt = mptsas_phy_to_tgt(mpt, phymask, phy);
14146 14177 if (ptgt == NULL) {
14147 14178 /*
14148 14179 * didn't match any device by searching
14149 14180 */
14150 14181 return (DDI_FAILURE);
14151 14182 }
14152 14183
14153 14184 /*
14154 14185 * If the LUN already exists and the status is online,
14155 14186 * we just return the pointer to dev_info_t directly.
14156 14187 * For the mdi_pathinfo node, we'll handle it in
14157 14188 * mptsas_create_virt_lun().
14158 14189 */
14159 14190
14160 14191 *lundip = mptsas_find_child_phy(pdip, phy);
14161 14192 if (*lundip != NULL) {
14162 14193 return (DDI_SUCCESS);
14163 14194 }
14164 14195
14165 14196 rval = mptsas_probe_lun(pdip, lun, lundip, ptgt);
14166 14197
14167 14198 return (rval);
14168 14199 }
14169 14200
14170 14201 static int
14171 14202 mptsas_retrieve_lundata(int lun_cnt, uint8_t *buf, uint16_t *lun_num,
14172 14203 uint8_t *lun_addr_type)
14173 14204 {
14174 14205 uint32_t lun_idx = 0;
14175 14206
14176 14207 ASSERT(lun_num != NULL);
14177 14208 ASSERT(lun_addr_type != NULL);
14178 14209
14179 14210 lun_idx = (lun_cnt + 1) * MPTSAS_SCSI_REPORTLUNS_ADDRESS_SIZE;
14180 14211 /* determine report luns addressing type */
14181 14212 switch (buf[lun_idx] & MPTSAS_SCSI_REPORTLUNS_ADDRESS_MASK) {
14182 14213 /*
14183 14214 * Vendors in the field have been found to be concatenating
14184 14215 * bus/target/lun to equal the complete lun value instead
14185 14216 * of switching to flat space addressing
14186 14217 */
14187 14218 /* 00b - peripheral device addressing method */
14188 14219 case MPTSAS_SCSI_REPORTLUNS_ADDRESS_PERIPHERAL:
14189 14220 /* FALLTHRU */
14190 14221 /* 10b - logical unit addressing method */
14191 14222 case MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT:
14192 14223 /* FALLTHRU */
14193 14224 /* 01b - flat space addressing method */
14194 14225 case MPTSAS_SCSI_REPORTLUNS_ADDRESS_FLAT_SPACE:
14195 14226 /* byte0 bit0-5=msb lun byte1 bit0-7=lsb lun */
14196 14227 *lun_addr_type = (buf[lun_idx] &
14197 14228 MPTSAS_SCSI_REPORTLUNS_ADDRESS_MASK) >> 6;
14198 14229 *lun_num = (buf[lun_idx] & 0x3F) << 8;
14199 14230 *lun_num |= buf[lun_idx + 1];
14200 14231 return (DDI_SUCCESS);
14201 14232 default:
14202 14233 return (DDI_FAILURE);
14203 14234 }
14204 14235 }
14205 14236
14206 14237 static int
14207 14238 mptsas_config_luns(dev_info_t *pdip, mptsas_target_t *ptgt)
14208 14239 {
14209 14240 struct buf *repluns_bp = NULL;
14210 14241 struct scsi_address ap;
14211 14242 uchar_t cdb[CDB_GROUP5];
14212 14243 int ret = DDI_FAILURE;
14213 14244 int retry = 0;
14214 14245 int lun_list_len = 0;
14215 14246 uint16_t lun_num = 0;
14216 14247 uint8_t lun_addr_type = 0;
14217 14248 uint32_t lun_cnt = 0;
14218 14249 uint32_t lun_total = 0;
14219 14250 dev_info_t *cdip = NULL;
14220 14251 uint16_t *saved_repluns = NULL;
14221 14252 char *buffer = NULL;
14222 14253 int buf_len = 128;
14223 14254 mptsas_t *mpt = DIP2MPT(pdip);
14224 14255 uint64_t sas_wwn = 0;
14225 14256 uint8_t phy = 0xFF;
14226 14257 uint32_t dev_info = 0;
14227 14258
14228 14259 mutex_enter(&mpt->m_mutex);
14229 14260 sas_wwn = ptgt->m_addr.mta_wwn;
14230 14261 phy = ptgt->m_phynum;
14231 14262 dev_info = ptgt->m_deviceinfo;
14232 14263 mutex_exit(&mpt->m_mutex);
14233 14264
14234 14265 if (sas_wwn == 0) {
14235 14266 /*
14236 14267 * It's a SATA without Device Name
14237 14268 * So don't try multi-LUNs
14238 14269 */
14239 14270 if (mptsas_find_child_phy(pdip, phy)) {
14240 14271 return (DDI_SUCCESS);
14241 14272 } else {
14242 14273 /*
14243 14274 * need configure and create node
14244 14275 */
14245 14276 return (DDI_FAILURE);
14246 14277 }
14247 14278 }
14248 14279
14249 14280 /*
14250 14281 * WWN (SAS address or Device Name exist)
14251 14282 */
14252 14283 if (dev_info & (MPI2_SAS_DEVICE_INFO_SATA_DEVICE |
14253 14284 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) {
14254 14285 /*
14255 14286 * SATA device with Device Name
14256 14287 * So don't try multi-LUNs
14257 14288 */
14258 14289 if (mptsas_find_child_addr(pdip, sas_wwn, 0)) {
14259 14290 return (DDI_SUCCESS);
14260 14291 } else {
14261 14292 return (DDI_FAILURE);
14262 14293 }
14263 14294 }
14264 14295
14265 14296 do {
14266 14297 ap.a_target = MPTSAS_INVALID_DEVHDL;
14267 14298 ap.a_lun = 0;
14268 14299 ap.a_hba_tran = mpt->m_tran;
14269 14300 repluns_bp = scsi_alloc_consistent_buf(&ap,
14270 14301 (struct buf *)NULL, buf_len, B_READ, NULL_FUNC, NULL);
14271 14302 if (repluns_bp == NULL) {
14272 14303 retry++;
14273 14304 continue;
14274 14305 }
14275 14306 bzero(cdb, CDB_GROUP5);
14276 14307 cdb[0] = SCMD_REPORT_LUNS;
14277 14308 cdb[6] = (buf_len & 0xff000000) >> 24;
14278 14309 cdb[7] = (buf_len & 0x00ff0000) >> 16;
14279 14310 cdb[8] = (buf_len & 0x0000ff00) >> 8;
14280 14311 cdb[9] = (buf_len & 0x000000ff);
14281 14312
14282 14313 ret = mptsas_send_scsi_cmd(mpt, &ap, ptgt, &cdb[0], CDB_GROUP5,
14283 14314 repluns_bp, NULL);
14284 14315 if (ret != DDI_SUCCESS) {
14285 14316 scsi_free_consistent_buf(repluns_bp);
14286 14317 retry++;
14287 14318 continue;
14288 14319 }
14289 14320 lun_list_len = BE_32(*(int *)((void *)(
14290 14321 repluns_bp->b_un.b_addr)));
14291 14322 if (buf_len >= lun_list_len + 8) {
14292 14323 ret = DDI_SUCCESS;
14293 14324 break;
14294 14325 }
14295 14326 scsi_free_consistent_buf(repluns_bp);
14296 14327 buf_len = lun_list_len + 8;
14297 14328
14298 14329 } while (retry < 3);
14299 14330
14300 14331 if (ret != DDI_SUCCESS)
14301 14332 return (ret);
14302 14333 buffer = (char *)repluns_bp->b_un.b_addr;
14303 14334 /*
14304 14335 * find out the number of luns returned by the SCSI ReportLun call
14305 14336 * and allocate buffer space
14306 14337 */
14307 14338 lun_total = lun_list_len / MPTSAS_SCSI_REPORTLUNS_ADDRESS_SIZE;
14308 14339 saved_repluns = kmem_zalloc(sizeof (uint16_t) * lun_total, KM_SLEEP);
14309 14340 if (saved_repluns == NULL) {
14310 14341 scsi_free_consistent_buf(repluns_bp);
14311 14342 return (DDI_FAILURE);
14312 14343 }
14313 14344 for (lun_cnt = 0; lun_cnt < lun_total; lun_cnt++) {
14314 14345 if (mptsas_retrieve_lundata(lun_cnt, (uint8_t *)(buffer),
14315 14346 &lun_num, &lun_addr_type) != DDI_SUCCESS) {
14316 14347 continue;
14317 14348 }
14318 14349 saved_repluns[lun_cnt] = lun_num;
14319 14350 if (cdip = mptsas_find_child_addr(pdip, sas_wwn, lun_num))
14320 14351 ret = DDI_SUCCESS;
14321 14352 else
14322 14353 ret = mptsas_probe_lun(pdip, lun_num, &cdip,
14323 14354 ptgt);
14324 14355 if ((ret == DDI_SUCCESS) && (cdip != NULL)) {
14325 14356 (void) ndi_prop_remove(DDI_DEV_T_NONE, cdip,
14326 14357 MPTSAS_DEV_GONE);
14327 14358 }
14328 14359 }
14329 14360 mptsas_offline_missed_luns(pdip, saved_repluns, lun_total, ptgt);
14330 14361 kmem_free(saved_repluns, sizeof (uint16_t) * lun_total);
14331 14362 scsi_free_consistent_buf(repluns_bp);
14332 14363 return (DDI_SUCCESS);
14333 14364 }
14334 14365
14335 14366 static int
14336 14367 mptsas_config_raid(dev_info_t *pdip, uint16_t target, dev_info_t **dip)
14337 14368 {
14338 14369 int rval = DDI_FAILURE;
14339 14370 struct scsi_inquiry *sd_inq = NULL;
14340 14371 mptsas_t *mpt = DIP2MPT(pdip);
14341 14372 mptsas_target_t *ptgt = NULL;
14342 14373
14343 14374 mutex_enter(&mpt->m_mutex);
14344 14375 ptgt = refhash_linear_search(mpt->m_targets,
14345 14376 mptsas_target_eval_devhdl, &target);
14346 14377 mutex_exit(&mpt->m_mutex);
14347 14378 if (ptgt == NULL) {
14348 14379 mptsas_log(mpt, CE_WARN, "Volume with VolDevHandle of 0x%x "
14349 14380 "not found.", target);
14350 14381 return (rval);
14351 14382 }
14352 14383
14353 14384 sd_inq = (struct scsi_inquiry *)kmem_alloc(SUN_INQSIZE, KM_SLEEP);
14354 14385 rval = mptsas_inquiry(mpt, ptgt, 0, 0, (uchar_t *)sd_inq,
14355 14386 SUN_INQSIZE, 0, (uchar_t)0);
14356 14387
14357 14388 if ((rval == DDI_SUCCESS) && MPTSAS_VALID_LUN(sd_inq)) {
14358 14389 rval = mptsas_create_phys_lun(pdip, sd_inq, NULL, dip, ptgt,
14359 14390 0);
14360 14391 } else {
14361 14392 rval = DDI_FAILURE;
14362 14393 }
14363 14394
14364 14395 kmem_free(sd_inq, SUN_INQSIZE);
14365 14396 return (rval);
14366 14397 }
14367 14398
14368 14399 /*
14369 14400 * configure all RAID volumes for virtual iport
14370 14401 */
14371 14402 static void
14372 14403 mptsas_config_all_viport(dev_info_t *pdip)
14373 14404 {
14374 14405 mptsas_t *mpt = DIP2MPT(pdip);
14375 14406 int config, vol;
14376 14407 int target;
14377 14408 dev_info_t *lundip = NULL;
14378 14409
14379 14410 /*
14380 14411 * Get latest RAID info and search for any Volume DevHandles. If any
14381 14412 * are found, configure the volume.
14382 14413 */
14383 14414 mutex_enter(&mpt->m_mutex);
14384 14415 for (config = 0; config < mpt->m_num_raid_configs; config++) {
14385 14416 for (vol = 0; vol < MPTSAS_MAX_RAIDVOLS; vol++) {
14386 14417 if (mpt->m_raidconfig[config].m_raidvol[vol].m_israid
14387 14418 == 1) {
14388 14419 target = mpt->m_raidconfig[config].
14389 14420 m_raidvol[vol].m_raidhandle;
14390 14421 mutex_exit(&mpt->m_mutex);
14391 14422 (void) mptsas_config_raid(pdip, target,
14392 14423 &lundip);
14393 14424 mutex_enter(&mpt->m_mutex);
14394 14425 }
14395 14426 }
14396 14427 }
14397 14428 mutex_exit(&mpt->m_mutex);
14398 14429 }
14399 14430
14400 14431 static void
14401 14432 mptsas_offline_missed_luns(dev_info_t *pdip, uint16_t *repluns,
14402 14433 int lun_cnt, mptsas_target_t *ptgt)
14403 14434 {
14404 14435 dev_info_t *child = NULL, *savechild = NULL;
14405 14436 mdi_pathinfo_t *pip = NULL, *savepip = NULL;
14406 14437 uint64_t sas_wwn, wwid;
14407 14438 uint8_t phy;
14408 14439 int lun;
14409 14440 int i;
14410 14441 int find;
14411 14442 char *addr;
14412 14443 char *nodename;
14413 14444 mptsas_t *mpt = DIP2MPT(pdip);
14414 14445
14415 14446 mutex_enter(&mpt->m_mutex);
14416 14447 wwid = ptgt->m_addr.mta_wwn;
14417 14448 mutex_exit(&mpt->m_mutex);
14418 14449
14419 14450 child = ddi_get_child(pdip);
14420 14451 while (child) {
14421 14452 find = 0;
14422 14453 savechild = child;
14423 14454 child = ddi_get_next_sibling(child);
14424 14455
14425 14456 nodename = ddi_node_name(savechild);
14426 14457 if (strcmp(nodename, "smp") == 0) {
14427 14458 continue;
14428 14459 }
14429 14460
14430 14461 addr = ddi_get_name_addr(savechild);
14431 14462 if (addr == NULL) {
14432 14463 continue;
14433 14464 }
14434 14465
14435 14466 if (mptsas_parse_address(addr, &sas_wwn, &phy, &lun) !=
14436 14467 DDI_SUCCESS) {
14437 14468 continue;
14438 14469 }
14439 14470
14440 14471 if (wwid == sas_wwn) {
14441 14472 for (i = 0; i < lun_cnt; i++) {
14442 14473 if (repluns[i] == lun) {
14443 14474 find = 1;
14444 14475 break;
14445 14476 }
14446 14477 }
14447 14478 } else {
14448 14479 continue;
14449 14480 }
14450 14481 if (find == 0) {
14451 14482 /*
14452 14483 * The lun has not been there already
14453 14484 */
14454 14485 (void) mptsas_offline_lun(pdip, savechild, NULL,
14455 14486 NDI_DEVI_REMOVE);
14456 14487 }
14457 14488 }
14458 14489
14459 14490 pip = mdi_get_next_client_path(pdip, NULL);
14460 14491 while (pip) {
14461 14492 find = 0;
14462 14493 savepip = pip;
14463 14494 addr = MDI_PI(pip)->pi_addr;
14464 14495
14465 14496 pip = mdi_get_next_client_path(pdip, pip);
14466 14497
14467 14498 if (addr == NULL) {
14468 14499 continue;
14469 14500 }
14470 14501
14471 14502 if (mptsas_parse_address(addr, &sas_wwn, &phy,
14472 14503 &lun) != DDI_SUCCESS) {
14473 14504 continue;
14474 14505 }
14475 14506
14476 14507 if (sas_wwn == wwid) {
14477 14508 for (i = 0; i < lun_cnt; i++) {
14478 14509 if (repluns[i] == lun) {
14479 14510 find = 1;
14480 14511 break;
14481 14512 }
14482 14513 }
14483 14514 } else {
14484 14515 continue;
14485 14516 }
14486 14517
14487 14518 if (find == 0) {
14488 14519 /*
14489 14520 * The lun has not been there already
14490 14521 */
14491 14522 (void) mptsas_offline_lun(pdip, NULL, savepip,
14492 14523 NDI_DEVI_REMOVE);
14493 14524 }
14494 14525 }
14495 14526 }
14496 14527
14497 14528 void
14498 14529 mptsas_update_hashtab(struct mptsas *mpt)
14499 14530 {
14500 14531 uint32_t page_address;
14501 14532 int rval = 0;
14502 14533 uint16_t dev_handle;
14503 14534 mptsas_target_t *ptgt = NULL;
14504 14535 mptsas_smp_t smp_node;
14505 14536
14506 14537 /*
14507 14538 * Get latest RAID info.
14508 14539 */
14509 14540 (void) mptsas_get_raid_info(mpt);
14510 14541
14511 14542 dev_handle = mpt->m_smp_devhdl;
14512 14543 for (; mpt->m_done_traverse_smp == 0; ) {
14513 14544 page_address = (MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL &
14514 14545 MPI2_SAS_EXPAND_PGAD_FORM_MASK) | (uint32_t)dev_handle;
14515 14546 if (mptsas_get_sas_expander_page0(mpt, page_address, &smp_node)
14516 14547 != DDI_SUCCESS) {
14517 14548 break;
14518 14549 }
14519 14550 mpt->m_smp_devhdl = dev_handle = smp_node.m_devhdl;
14520 14551 (void) mptsas_smp_alloc(mpt, &smp_node);
14521 14552 }
14522 14553
14523 14554 /*
14524 14555 * Config target devices
14525 14556 */
14526 14557 dev_handle = mpt->m_dev_handle;
14527 14558
14528 14559 /*
14529 14560 * Do loop to get sas device page 0 by GetNextHandle till the
14530 14561 * the last handle. If the sas device is a SATA/SSP target,
14531 14562 * we try to config it.
14532 14563 */
14533 14564 for (; mpt->m_done_traverse_dev == 0; ) {
14534 14565 ptgt = NULL;
14535 14566 page_address =
14536 14567 (MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE &
14537 14568 MPI2_SAS_DEVICE_PGAD_FORM_MASK) |
14538 14569 (uint32_t)dev_handle;
14539 14570 rval = mptsas_get_target_device_info(mpt, page_address,
14540 14571 &dev_handle, &ptgt);
14541 14572 if ((rval == DEV_INFO_FAIL_PAGE0) ||
14542 14573 (rval == DEV_INFO_FAIL_ALLOC) ||
14543 14574 (rval == DEV_INFO_FAIL_GUID)) {
14544 14575 break;
14545 14576 }
14546 14577
14547 14578 mpt->m_dev_handle = dev_handle;
14548 14579 }
14549 14580
14550 14581 }
14551 14582
14552 14583 void
14553 14584 mptsas_update_driver_data(struct mptsas *mpt)
14554 14585 {
14555 14586 mptsas_target_t *tp;
14556 14587 mptsas_smp_t *sp;
14557 14588
14558 14589 ASSERT(MUTEX_HELD(&mpt->m_mutex));
14559 14590
14560 14591 /*
14561 14592 * TODO after hard reset, update the driver data structures
14562 14593 * 1. update port/phymask mapping table mpt->m_phy_info
14563 14594 * 2. invalid all the entries in hash table
14564 14595 * m_devhdl = 0xffff and m_deviceinfo = 0
14565 14596 * 3. call sas_device_page/expander_page to update hash table
14566 14597 */
14567 14598 mptsas_update_phymask(mpt);
14568 14599
14569 14600 /*
14570 14601 * Remove all the devhdls for existing entries but leave their
14571 14602 * addresses alone. In update_hashtab() below, we'll find all
14572 14603 * targets that are still present and reassociate them with
14573 14604 * their potentially new devhdls. Leaving the targets around in
14574 14605 * this fashion allows them to be used on the tx waitq even
14575 14606 * while IOC reset is occurring.
14576 14607 */
14577 14608 for (tp = refhash_first(mpt->m_targets); tp != NULL;
14578 14609 tp = refhash_next(mpt->m_targets, tp)) {
14579 14610 tp->m_devhdl = MPTSAS_INVALID_DEVHDL;
14580 14611 tp->m_deviceinfo = 0;
14581 14612 tp->m_dr_flag = MPTSAS_DR_INACTIVE;
14582 14613 }
14583 14614 for (sp = refhash_first(mpt->m_smp_targets); sp != NULL;
14584 14615 sp = refhash_next(mpt->m_smp_targets, sp)) {
14585 14616 sp->m_devhdl = MPTSAS_INVALID_DEVHDL;
14586 14617 sp->m_deviceinfo = 0;
14587 14618 }
14588 14619 mpt->m_done_traverse_dev = 0;
14589 14620 mpt->m_done_traverse_smp = 0;
14590 14621 mpt->m_dev_handle = mpt->m_smp_devhdl = MPTSAS_INVALID_DEVHDL;
14591 14622 mptsas_update_hashtab(mpt);
14592 14623 }
14593 14624
14594 14625 static void
14595 14626 mptsas_config_all(dev_info_t *pdip)
14596 14627 {
14597 14628 dev_info_t *smpdip = NULL;
14598 14629 mptsas_t *mpt = DIP2MPT(pdip);
14599 14630 int phymask = 0;
14600 14631 mptsas_phymask_t phy_mask;
14601 14632 mptsas_target_t *ptgt = NULL;
14602 14633 mptsas_smp_t *psmp;
14603 14634
14604 14635 /*
14605 14636 * Get the phymask associated to the iport
14606 14637 */
14607 14638 phymask = ddi_prop_get_int(DDI_DEV_T_ANY, pdip, 0,
14608 14639 "phymask", 0);
14609 14640
14610 14641 /*
14611 14642 * Enumerate RAID volumes here (phymask == 0).
14612 14643 */
14613 14644 if (phymask == 0) {
14614 14645 mptsas_config_all_viport(pdip);
14615 14646 return;
14616 14647 }
14617 14648
14618 14649 mutex_enter(&mpt->m_mutex);
14619 14650
14620 14651 if (!mpt->m_done_traverse_dev || !mpt->m_done_traverse_smp) {
14621 14652 mptsas_update_hashtab(mpt);
14622 14653 }
14623 14654
14624 14655 for (psmp = refhash_first(mpt->m_smp_targets); psmp != NULL;
14625 14656 psmp = refhash_next(mpt->m_smp_targets, psmp)) {
14626 14657 phy_mask = psmp->m_addr.mta_phymask;
14627 14658 if (phy_mask == phymask) {
14628 14659 smpdip = NULL;
14629 14660 mutex_exit(&mpt->m_mutex);
14630 14661 (void) mptsas_online_smp(pdip, psmp, &smpdip);
14631 14662 mutex_enter(&mpt->m_mutex);
14632 14663 }
14633 14664 }
14634 14665
14635 14666 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL;
14636 14667 ptgt = refhash_next(mpt->m_targets, ptgt)) {
14637 14668 phy_mask = ptgt->m_addr.mta_phymask;
14638 14669 if (phy_mask == phymask) {
14639 14670 mutex_exit(&mpt->m_mutex);
14640 14671 (void) mptsas_config_target(pdip, ptgt);
14641 14672 mutex_enter(&mpt->m_mutex);
14642 14673 }
14643 14674 }
14644 14675 mutex_exit(&mpt->m_mutex);
14645 14676 }
14646 14677
14647 14678 static int
14648 14679 mptsas_config_target(dev_info_t *pdip, mptsas_target_t *ptgt)
14649 14680 {
14650 14681 int rval = DDI_FAILURE;
14651 14682 dev_info_t *tdip;
14652 14683
14653 14684 rval = mptsas_config_luns(pdip, ptgt);
14654 14685 if (rval != DDI_SUCCESS) {
14655 14686 /*
14656 14687 * The return value means the SCMD_REPORT_LUNS
14657 14688 * did not execute successfully. The target maybe
14658 14689 * doesn't support such command.
14659 14690 */
14660 14691 rval = mptsas_probe_lun(pdip, 0, &tdip, ptgt);
14661 14692 }
14662 14693 return (rval);
14663 14694 }
14664 14695
14665 14696 /*
14666 14697 * Return fail if not all the childs/paths are freed.
14667 14698 * if there is any path under the HBA, the return value will be always fail
14668 14699 * because we didn't call mdi_pi_free for path
14669 14700 */
14670 14701 static int
14671 14702 mptsas_offline_target(dev_info_t *pdip, char *name)
14672 14703 {
14673 14704 dev_info_t *child = NULL, *prechild = NULL;
14674 14705 mdi_pathinfo_t *pip = NULL, *savepip = NULL;
14675 14706 int tmp_rval, rval = DDI_SUCCESS;
14676 14707 char *addr, *cp;
14677 14708 size_t s;
14678 14709 mptsas_t *mpt = DIP2MPT(pdip);
14679 14710
14680 14711 child = ddi_get_child(pdip);
14681 14712 while (child) {
14682 14713 addr = ddi_get_name_addr(child);
14683 14714 prechild = child;
14684 14715 child = ddi_get_next_sibling(child);
14685 14716
14686 14717 if (addr == NULL) {
14687 14718 continue;
14688 14719 }
14689 14720 if ((cp = strchr(addr, ',')) == NULL) {
14690 14721 continue;
14691 14722 }
14692 14723
14693 14724 s = (uintptr_t)cp - (uintptr_t)addr;
14694 14725
14695 14726 if (strncmp(addr, name, s) != 0) {
14696 14727 continue;
14697 14728 }
14698 14729
14699 14730 tmp_rval = mptsas_offline_lun(pdip, prechild, NULL,
14700 14731 NDI_DEVI_REMOVE);
14701 14732 if (tmp_rval != DDI_SUCCESS) {
14702 14733 rval = DDI_FAILURE;
14703 14734 if (ndi_prop_create_boolean(DDI_DEV_T_NONE,
14704 14735 prechild, MPTSAS_DEV_GONE) !=
14705 14736 DDI_PROP_SUCCESS) {
14706 14737 mptsas_log(mpt, CE_WARN, "mptsas driver "
14707 14738 "unable to create property for "
14708 14739 "SAS %s (MPTSAS_DEV_GONE)", addr);
14709 14740 }
14710 14741 }
14711 14742 }
14712 14743
14713 14744 pip = mdi_get_next_client_path(pdip, NULL);
14714 14745 while (pip) {
14715 14746 addr = MDI_PI(pip)->pi_addr;
14716 14747 savepip = pip;
14717 14748 pip = mdi_get_next_client_path(pdip, pip);
14718 14749 if (addr == NULL) {
14719 14750 continue;
14720 14751 }
14721 14752
14722 14753 if ((cp = strchr(addr, ',')) == NULL) {
14723 14754 continue;
14724 14755 }
14725 14756
14726 14757 s = (uintptr_t)cp - (uintptr_t)addr;
14727 14758
14728 14759 if (strncmp(addr, name, s) != 0) {
14729 14760 continue;
14730 14761 }
14731 14762
14732 14763 (void) mptsas_offline_lun(pdip, NULL, savepip,
14733 14764 NDI_DEVI_REMOVE);
14734 14765 /*
14735 14766 * driver will not invoke mdi_pi_free, so path will not
14736 14767 * be freed forever, return DDI_FAILURE.
14737 14768 */
14738 14769 rval = DDI_FAILURE;
14739 14770 }
14740 14771 return (rval);
14741 14772 }
14742 14773
14743 14774 static int
14744 14775 mptsas_offline_lun(dev_info_t *pdip, dev_info_t *rdip,
14745 14776 mdi_pathinfo_t *rpip, uint_t flags)
14746 14777 {
14747 14778 int rval = DDI_FAILURE;
14748 14779 char *devname;
14749 14780 dev_info_t *cdip, *parent;
14750 14781
14751 14782 if (rpip != NULL) {
14752 14783 parent = scsi_vhci_dip;
14753 14784 cdip = mdi_pi_get_client(rpip);
14754 14785 } else if (rdip != NULL) {
14755 14786 parent = pdip;
14756 14787 cdip = rdip;
14757 14788 } else {
14758 14789 return (DDI_FAILURE);
14759 14790 }
14760 14791
14761 14792 /*
14762 14793 * Make sure node is attached otherwise
14763 14794 * it won't have related cache nodes to
14764 14795 * clean up. i_ddi_devi_attached is
14765 14796 * similiar to i_ddi_node_state(cdip) >=
14766 14797 * DS_ATTACHED.
14767 14798 */
14768 14799 if (i_ddi_devi_attached(cdip)) {
14769 14800
14770 14801 /* Get full devname */
14771 14802 devname = kmem_alloc(MAXNAMELEN + 1, KM_SLEEP);
14772 14803 (void) ddi_deviname(cdip, devname);
14773 14804 /* Clean cache */
14774 14805 (void) devfs_clean(parent, devname + 1,
14775 14806 DV_CLEAN_FORCE);
14776 14807 kmem_free(devname, MAXNAMELEN + 1);
14777 14808 }
14778 14809 if (rpip != NULL) {
14779 14810 if (MDI_PI_IS_OFFLINE(rpip)) {
14780 14811 rval = DDI_SUCCESS;
14781 14812 } else {
14782 14813 rval = mdi_pi_offline(rpip, 0);
14783 14814 }
14784 14815 } else {
14785 14816 rval = ndi_devi_offline(cdip, flags);
14786 14817 }
14787 14818
14788 14819 return (rval);
14789 14820 }
14790 14821
14791 14822 static dev_info_t *
14792 14823 mptsas_find_smp_child(dev_info_t *parent, char *str_wwn)
14793 14824 {
14794 14825 dev_info_t *child = NULL;
14795 14826 char *smp_wwn = NULL;
14796 14827
14797 14828 child = ddi_get_child(parent);
14798 14829 while (child) {
14799 14830 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, child,
14800 14831 DDI_PROP_DONTPASS, SMP_WWN, &smp_wwn)
14801 14832 != DDI_SUCCESS) {
14802 14833 child = ddi_get_next_sibling(child);
14803 14834 continue;
14804 14835 }
14805 14836
14806 14837 if (strcmp(smp_wwn, str_wwn) == 0) {
14807 14838 ddi_prop_free(smp_wwn);
14808 14839 break;
14809 14840 }
14810 14841 child = ddi_get_next_sibling(child);
14811 14842 ddi_prop_free(smp_wwn);
14812 14843 }
14813 14844 return (child);
14814 14845 }
14815 14846
14816 14847 static int
14817 14848 mptsas_offline_smp(dev_info_t *pdip, mptsas_smp_t *smp_node, uint_t flags)
14818 14849 {
14819 14850 int rval = DDI_FAILURE;
14820 14851 char *devname;
14821 14852 char wwn_str[MPTSAS_WWN_STRLEN];
14822 14853 dev_info_t *cdip;
14823 14854
14824 14855 (void) sprintf(wwn_str, "%"PRIx64, smp_node->m_addr.mta_wwn);
14825 14856
14826 14857 cdip = mptsas_find_smp_child(pdip, wwn_str);
14827 14858
14828 14859 if (cdip == NULL)
14829 14860 return (DDI_SUCCESS);
14830 14861
14831 14862 /*
14832 14863 * Make sure node is attached otherwise
14833 14864 * it won't have related cache nodes to
14834 14865 * clean up. i_ddi_devi_attached is
14835 14866 * similiar to i_ddi_node_state(cdip) >=
14836 14867 * DS_ATTACHED.
14837 14868 */
14838 14869 if (i_ddi_devi_attached(cdip)) {
14839 14870
14840 14871 /* Get full devname */
14841 14872 devname = kmem_alloc(MAXNAMELEN + 1, KM_SLEEP);
14842 14873 (void) ddi_deviname(cdip, devname);
14843 14874 /* Clean cache */
14844 14875 (void) devfs_clean(pdip, devname + 1,
14845 14876 DV_CLEAN_FORCE);
14846 14877 kmem_free(devname, MAXNAMELEN + 1);
14847 14878 }
14848 14879
14849 14880 rval = ndi_devi_offline(cdip, flags);
14850 14881
14851 14882 return (rval);
14852 14883 }
14853 14884
14854 14885 static dev_info_t *
14855 14886 mptsas_find_child(dev_info_t *pdip, char *name)
14856 14887 {
14857 14888 dev_info_t *child = NULL;
14858 14889 char *rname = NULL;
14859 14890 int rval = DDI_FAILURE;
14860 14891
14861 14892 rname = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
14862 14893
14863 14894 child = ddi_get_child(pdip);
14864 14895 while (child) {
14865 14896 rval = mptsas_name_child(child, rname, SCSI_MAXNAMELEN);
14866 14897 if (rval != DDI_SUCCESS) {
14867 14898 child = ddi_get_next_sibling(child);
14868 14899 bzero(rname, SCSI_MAXNAMELEN);
14869 14900 continue;
14870 14901 }
14871 14902
14872 14903 if (strcmp(rname, name) == 0) {
14873 14904 break;
14874 14905 }
14875 14906 child = ddi_get_next_sibling(child);
14876 14907 bzero(rname, SCSI_MAXNAMELEN);
14877 14908 }
14878 14909
14879 14910 kmem_free(rname, SCSI_MAXNAMELEN);
14880 14911
14881 14912 return (child);
14882 14913 }
14883 14914
14884 14915
14885 14916 static dev_info_t *
14886 14917 mptsas_find_child_addr(dev_info_t *pdip, uint64_t sasaddr, int lun)
14887 14918 {
14888 14919 dev_info_t *child = NULL;
14889 14920 char *name = NULL;
14890 14921 char *addr = NULL;
14891 14922
14892 14923 name = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
14893 14924 addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
14894 14925 (void) sprintf(name, "%016"PRIx64, sasaddr);
14895 14926 (void) sprintf(addr, "w%s,%x", name, lun);
14896 14927 child = mptsas_find_child(pdip, addr);
14897 14928 kmem_free(name, SCSI_MAXNAMELEN);
14898 14929 kmem_free(addr, SCSI_MAXNAMELEN);
14899 14930 return (child);
14900 14931 }
14901 14932
14902 14933 static dev_info_t *
14903 14934 mptsas_find_child_phy(dev_info_t *pdip, uint8_t phy)
14904 14935 {
14905 14936 dev_info_t *child;
14906 14937 char *addr;
14907 14938
14908 14939 addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
14909 14940 (void) sprintf(addr, "p%x,0", phy);
14910 14941 child = mptsas_find_child(pdip, addr);
14911 14942 kmem_free(addr, SCSI_MAXNAMELEN);
14912 14943 return (child);
14913 14944 }
14914 14945
14915 14946 static mdi_pathinfo_t *
14916 14947 mptsas_find_path_phy(dev_info_t *pdip, uint8_t phy)
14917 14948 {
14918 14949 mdi_pathinfo_t *path;
14919 14950 char *addr = NULL;
14920 14951
14921 14952 addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
14922 14953 (void) sprintf(addr, "p%x,0", phy);
14923 14954 path = mdi_pi_find(pdip, NULL, addr);
14924 14955 kmem_free(addr, SCSI_MAXNAMELEN);
14925 14956 return (path);
14926 14957 }
14927 14958
14928 14959 static mdi_pathinfo_t *
14929 14960 mptsas_find_path_addr(dev_info_t *parent, uint64_t sasaddr, int lun)
14930 14961 {
14931 14962 mdi_pathinfo_t *path;
14932 14963 char *name = NULL;
14933 14964 char *addr = NULL;
14934 14965
14935 14966 name = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
14936 14967 addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
14937 14968 (void) sprintf(name, "%016"PRIx64, sasaddr);
14938 14969 (void) sprintf(addr, "w%s,%x", name, lun);
14939 14970 path = mdi_pi_find(parent, NULL, addr);
14940 14971 kmem_free(name, SCSI_MAXNAMELEN);
14941 14972 kmem_free(addr, SCSI_MAXNAMELEN);
14942 14973
14943 14974 return (path);
14944 14975 }
14945 14976
14946 14977 static int
14947 14978 mptsas_create_lun(dev_info_t *pdip, struct scsi_inquiry *sd_inq,
14948 14979 dev_info_t **lun_dip, mptsas_target_t *ptgt, int lun)
14949 14980 {
14950 14981 int i = 0;
14951 14982 uchar_t *inq83 = NULL;
14952 14983 int inq83_len1 = 0xFF;
14953 14984 int inq83_len = 0;
14954 14985 int rval = DDI_FAILURE;
14955 14986 ddi_devid_t devid;
14956 14987 char *guid = NULL;
14957 14988 int target = ptgt->m_devhdl;
14958 14989 mdi_pathinfo_t *pip = NULL;
14959 14990 mptsas_t *mpt = DIP2MPT(pdip);
14960 14991
14961 14992 /*
14962 14993 * For DVD/CD ROM and tape devices and optical
14963 14994 * devices, we won't try to enumerate them under
14964 14995 * scsi_vhci, so no need to try page83
14965 14996 */
14966 14997 if (sd_inq && (sd_inq->inq_dtype == DTYPE_RODIRECT ||
14967 14998 sd_inq->inq_dtype == DTYPE_OPTICAL ||
14968 14999 sd_inq->inq_dtype == DTYPE_ESI))
14969 15000 goto create_lun;
14970 15001
14971 15002 /*
14972 15003 * The LCA returns good SCSI status, but corrupt page 83 data the first
14973 15004 * time it is queried. The solution is to keep trying to request page83
14974 15005 * and verify the GUID is not (DDI_NOT_WELL_FORMED) in
14975 15006 * mptsas_inq83_retry_timeout seconds. If the timeout expires, driver
14976 15007 * give up to get VPD page at this stage and fail the enumeration.
14977 15008 */
14978 15009
14979 15010 inq83 = kmem_zalloc(inq83_len1, KM_SLEEP);
14980 15011
14981 15012 for (i = 0; i < mptsas_inq83_retry_timeout; i++) {
14982 15013 rval = mptsas_inquiry(mpt, ptgt, lun, 0x83, inq83,
14983 15014 inq83_len1, &inq83_len, 1);
14984 15015 if (rval != 0) {
14985 15016 mptsas_log(mpt, CE_WARN, "!mptsas request inquiry page "
14986 15017 "0x83 for target:%x, lun:%x failed!", target, lun);
14987 15018 if (mptsas_physical_bind_failed_page_83 != B_FALSE)
14988 15019 goto create_lun;
14989 15020 goto out;
14990 15021 }
14991 15022 /*
14992 15023 * create DEVID from inquiry data
14993 15024 */
14994 15025 if ((rval = ddi_devid_scsi_encode(
14995 15026 DEVID_SCSI_ENCODE_VERSION_LATEST, NULL, (uchar_t *)sd_inq,
14996 15027 sizeof (struct scsi_inquiry), NULL, 0, inq83,
14997 15028 (size_t)inq83_len, &devid)) == DDI_SUCCESS) {
14998 15029 /*
14999 15030 * extract GUID from DEVID
15000 15031 */
15001 15032 guid = ddi_devid_to_guid(devid);
15002 15033
15003 15034 /*
15004 15035 * Do not enable MPXIO if the strlen(guid) is greater
15005 15036 * than MPTSAS_MAX_GUID_LEN, this constrain would be
15006 15037 * handled by framework later.
15007 15038 */
15008 15039 if (guid && (strlen(guid) > MPTSAS_MAX_GUID_LEN)) {
15009 15040 ddi_devid_free_guid(guid);
15010 15041 guid = NULL;
15011 15042 if (mpt->m_mpxio_enable == TRUE) {
15012 15043 mptsas_log(mpt, CE_NOTE, "!Target:%x, "
15013 15044 "lun:%x doesn't have a valid GUID, "
15014 15045 "multipathing for this drive is "
15015 15046 "not enabled", target, lun);
15016 15047 }
15017 15048 }
15018 15049
15019 15050 /*
15020 15051 * devid no longer needed
15021 15052 */
15022 15053 ddi_devid_free(devid);
15023 15054 break;
15024 15055 } else if (rval == DDI_NOT_WELL_FORMED) {
15025 15056 /*
15026 15057 * return value of ddi_devid_scsi_encode equal to
15027 15058 * DDI_NOT_WELL_FORMED means DEVID_RETRY, it worth
15028 15059 * to retry inquiry page 0x83 and get GUID.
15029 15060 */
15030 15061 NDBG20(("Not well formed devid, retry..."));
15031 15062 delay(1 * drv_usectohz(1000000));
15032 15063 continue;
15033 15064 } else {
15034 15065 mptsas_log(mpt, CE_WARN, "!Encode devid failed for "
15035 15066 "path target:%x, lun:%x", target, lun);
15036 15067 rval = DDI_FAILURE;
15037 15068 goto create_lun;
15038 15069 }
15039 15070 }
15040 15071
15041 15072 if (i == mptsas_inq83_retry_timeout) {
15042 15073 mptsas_log(mpt, CE_WARN, "!Repeated page83 requests timeout "
15043 15074 "for path target:%x, lun:%x", target, lun);
15044 15075 }
15045 15076
15046 15077 rval = DDI_FAILURE;
15047 15078
15048 15079 create_lun:
15049 15080 if ((guid != NULL) && (mpt->m_mpxio_enable == TRUE)) {
15050 15081 rval = mptsas_create_virt_lun(pdip, sd_inq, guid, lun_dip, &pip,
15051 15082 ptgt, lun);
15052 15083 }
15053 15084 if (rval != DDI_SUCCESS) {
15054 15085 rval = mptsas_create_phys_lun(pdip, sd_inq, guid, lun_dip,
15055 15086 ptgt, lun);
15056 15087
15057 15088 }
15058 15089 out:
15059 15090 if (guid != NULL) {
15060 15091 /*
15061 15092 * guid no longer needed
15062 15093 */
15063 15094 ddi_devid_free_guid(guid);
15064 15095 }
15065 15096 if (inq83 != NULL)
15066 15097 kmem_free(inq83, inq83_len1);
15067 15098 return (rval);
15068 15099 }
15069 15100
15070 15101 static int
15071 15102 mptsas_create_virt_lun(dev_info_t *pdip, struct scsi_inquiry *inq, char *guid,
15072 15103 dev_info_t **lun_dip, mdi_pathinfo_t **pip, mptsas_target_t *ptgt, int lun)
15073 15104 {
15074 15105 int target;
15075 15106 char *nodename = NULL;
15076 15107 char **compatible = NULL;
15077 15108 int ncompatible = 0;
15078 15109 int mdi_rtn = MDI_FAILURE;
15079 15110 int rval = DDI_FAILURE;
15080 15111 char *old_guid = NULL;
15081 15112 mptsas_t *mpt = DIP2MPT(pdip);
15082 15113 char *lun_addr = NULL;
15083 15114 char *wwn_str = NULL;
15084 15115 char *attached_wwn_str = NULL;
15085 15116 char *component = NULL;
15086 15117 uint8_t phy = 0xFF;
15087 15118 uint64_t sas_wwn;
15088 15119 int64_t lun64 = 0;
15089 15120 uint32_t devinfo;
15090 15121 uint16_t dev_hdl;
15091 15122 uint16_t pdev_hdl;
15092 15123 uint64_t dev_sas_wwn;
15093 15124 uint64_t pdev_sas_wwn;
15094 15125 uint32_t pdev_info;
15095 15126 uint8_t physport;
15096 15127 uint8_t phy_id;
15097 15128 uint32_t page_address;
15098 15129 uint16_t bay_num, enclosure, io_flags;
15099 15130 char pdev_wwn_str[MPTSAS_WWN_STRLEN];
15100 15131 uint32_t dev_info;
15101 15132
15102 15133 mutex_enter(&mpt->m_mutex);
15103 15134 target = ptgt->m_devhdl;
15104 15135 sas_wwn = ptgt->m_addr.mta_wwn;
15105 15136 devinfo = ptgt->m_deviceinfo;
15106 15137 phy = ptgt->m_phynum;
15107 15138 mutex_exit(&mpt->m_mutex);
15108 15139
15109 15140 if (sas_wwn) {
15110 15141 *pip = mptsas_find_path_addr(pdip, sas_wwn, lun);
15111 15142 } else {
15112 15143 *pip = mptsas_find_path_phy(pdip, phy);
15113 15144 }
15114 15145
15115 15146 if (*pip != NULL) {
15116 15147 *lun_dip = MDI_PI(*pip)->pi_client->ct_dip;
15117 15148 ASSERT(*lun_dip != NULL);
15118 15149 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, *lun_dip,
15119 15150 (DDI_PROP_DONTPASS | DDI_PROP_NOTPROM),
15120 15151 MDI_CLIENT_GUID_PROP, &old_guid) == DDI_SUCCESS) {
15121 15152 if (strncmp(guid, old_guid, strlen(guid)) == 0) {
15122 15153 /*
15123 15154 * Same path back online again.
15124 15155 */
15125 15156 (void) ddi_prop_free(old_guid);
15126 15157 if ((!MDI_PI_IS_ONLINE(*pip)) &&
15127 15158 (!MDI_PI_IS_STANDBY(*pip)) &&
15128 15159 (ptgt->m_tgt_unconfigured == 0)) {
15129 15160 rval = mdi_pi_online(*pip, 0);
15130 15161 mutex_enter(&mpt->m_mutex);
15131 15162 ptgt->m_led_status = 0;
15132 15163 (void) mptsas_flush_led_status(mpt,
15133 15164 ptgt);
15134 15165 mutex_exit(&mpt->m_mutex);
15135 15166 } else {
15136 15167 rval = DDI_SUCCESS;
15137 15168 }
15138 15169 if (rval != DDI_SUCCESS) {
15139 15170 mptsas_log(mpt, CE_WARN, "path:target: "
15140 15171 "%x, lun:%x online failed!", target,
15141 15172 lun);
15142 15173 *pip = NULL;
15143 15174 *lun_dip = NULL;
15144 15175 }
15145 15176 return (rval);
15146 15177 } else {
15147 15178 /*
15148 15179 * The GUID of the LUN has changed which maybe
15149 15180 * because customer mapped another volume to the
15150 15181 * same LUN.
15151 15182 */
15152 15183 mptsas_log(mpt, CE_WARN, "The GUID of the "
15153 15184 "target:%x, lun:%x was changed, maybe "
15154 15185 "because someone mapped another volume "
15155 15186 "to the same LUN", target, lun);
15156 15187 (void) ddi_prop_free(old_guid);
15157 15188 if (!MDI_PI_IS_OFFLINE(*pip)) {
15158 15189 rval = mdi_pi_offline(*pip, 0);
15159 15190 if (rval != MDI_SUCCESS) {
15160 15191 mptsas_log(mpt, CE_WARN, "path:"
15161 15192 "target:%x, lun:%x offline "
15162 15193 "failed!", target, lun);
15163 15194 *pip = NULL;
15164 15195 *lun_dip = NULL;
15165 15196 return (DDI_FAILURE);
15166 15197 }
15167 15198 }
15168 15199 if (mdi_pi_free(*pip, 0) != MDI_SUCCESS) {
15169 15200 mptsas_log(mpt, CE_WARN, "path:target:"
15170 15201 "%x, lun:%x free failed!", target,
15171 15202 lun);
15172 15203 *pip = NULL;
15173 15204 *lun_dip = NULL;
15174 15205 return (DDI_FAILURE);
15175 15206 }
15176 15207 }
15177 15208 } else {
15178 15209 mptsas_log(mpt, CE_WARN, "Can't get client-guid "
15179 15210 "property for path:target:%x, lun:%x", target, lun);
15180 15211 *pip = NULL;
15181 15212 *lun_dip = NULL;
15182 15213 return (DDI_FAILURE);
15183 15214 }
15184 15215 }
15185 15216 scsi_hba_nodename_compatible_get(inq, NULL,
15186 15217 inq->inq_dtype, NULL, &nodename, &compatible, &ncompatible);
15187 15218
15188 15219 /*
15189 15220 * if nodename can't be determined then print a message and skip it
15190 15221 */
15191 15222 if (nodename == NULL) {
15192 15223 mptsas_log(mpt, CE_WARN, "mptsas driver found no compatible "
15193 15224 "driver for target%d lun %d dtype:0x%02x", target, lun,
15194 15225 inq->inq_dtype);
15195 15226 return (DDI_FAILURE);
15196 15227 }
15197 15228
15198 15229 wwn_str = kmem_zalloc(MPTSAS_WWN_STRLEN, KM_SLEEP);
15199 15230 /* The property is needed by MPAPI */
15200 15231 (void) sprintf(wwn_str, "%016"PRIx64, sas_wwn);
15201 15232
15202 15233 lun_addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
15203 15234 if (guid) {
15204 15235 (void) sprintf(lun_addr, "w%s,%x", wwn_str, lun);
15205 15236 (void) sprintf(wwn_str, "w%016"PRIx64, sas_wwn);
15206 15237 } else {
15207 15238 (void) sprintf(lun_addr, "p%x,%x", phy, lun);
15208 15239 (void) sprintf(wwn_str, "p%x", phy);
15209 15240 }
15210 15241
15211 15242 mdi_rtn = mdi_pi_alloc_compatible(pdip, nodename,
15212 15243 guid, lun_addr, compatible, ncompatible,
15213 15244 0, pip);
15214 15245 if (mdi_rtn == MDI_SUCCESS) {
15215 15246
15216 15247 if (mdi_prop_update_string(*pip, MDI_GUID,
15217 15248 guid) != DDI_SUCCESS) {
15218 15249 mptsas_log(mpt, CE_WARN, "mptsas driver unable to "
15219 15250 "create prop for target %d lun %d (MDI_GUID)",
15220 15251 target, lun);
15221 15252 mdi_rtn = MDI_FAILURE;
15222 15253 goto virt_create_done;
15223 15254 }
15224 15255
15225 15256 if (mdi_prop_update_int(*pip, LUN_PROP,
15226 15257 lun) != DDI_SUCCESS) {
15227 15258 mptsas_log(mpt, CE_WARN, "mptsas driver unable to "
15228 15259 "create prop for target %d lun %d (LUN_PROP)",
15229 15260 target, lun);
15230 15261 mdi_rtn = MDI_FAILURE;
15231 15262 goto virt_create_done;
15232 15263 }
15233 15264 lun64 = (int64_t)lun;
15234 15265 if (mdi_prop_update_int64(*pip, LUN64_PROP,
15235 15266 lun64) != DDI_SUCCESS) {
15236 15267 mptsas_log(mpt, CE_WARN, "mptsas driver unable to "
15237 15268 "create prop for target %d (LUN64_PROP)",
15238 15269 target);
15239 15270 mdi_rtn = MDI_FAILURE;
15240 15271 goto virt_create_done;
15241 15272 }
15242 15273 if (mdi_prop_update_string_array(*pip, "compatible",
15243 15274 compatible, ncompatible) !=
15244 15275 DDI_PROP_SUCCESS) {
15245 15276 mptsas_log(mpt, CE_WARN, "mptsas driver unable to "
15246 15277 "create prop for target %d lun %d (COMPATIBLE)",
15247 15278 target, lun);
15248 15279 mdi_rtn = MDI_FAILURE;
15249 15280 goto virt_create_done;
15250 15281 }
15251 15282 if (sas_wwn && (mdi_prop_update_string(*pip,
15252 15283 SCSI_ADDR_PROP_TARGET_PORT, wwn_str) != DDI_PROP_SUCCESS)) {
15253 15284 mptsas_log(mpt, CE_WARN, "mptsas driver unable to "
15254 15285 "create prop for target %d lun %d "
15255 15286 "(target-port)", target, lun);
15256 15287 mdi_rtn = MDI_FAILURE;
15257 15288 goto virt_create_done;
15258 15289 } else if ((sas_wwn == 0) && (mdi_prop_update_int(*pip,
15259 15290 "sata-phy", phy) != DDI_PROP_SUCCESS)) {
15260 15291 /*
15261 15292 * Direct attached SATA device without DeviceName
15262 15293 */
15263 15294 mptsas_log(mpt, CE_WARN, "mptsas driver unable to "
15264 15295 "create prop for SAS target %d lun %d "
15265 15296 "(sata-phy)", target, lun);
15266 15297 mdi_rtn = MDI_FAILURE;
15267 15298 goto virt_create_done;
15268 15299 }
15269 15300 mutex_enter(&mpt->m_mutex);
15270 15301
15271 15302 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE &
15272 15303 MPI2_SAS_DEVICE_PGAD_FORM_MASK) |
15273 15304 (uint32_t)ptgt->m_devhdl;
15274 15305 rval = mptsas_get_sas_device_page0(mpt, page_address,
15275 15306 &dev_hdl, &dev_sas_wwn, &dev_info, &physport,
15276 15307 &phy_id, &pdev_hdl, &bay_num, &enclosure, &io_flags);
15277 15308 if (rval != DDI_SUCCESS) {
15278 15309 mutex_exit(&mpt->m_mutex);
15279 15310 mptsas_log(mpt, CE_WARN, "mptsas unable to get "
15280 15311 "parent device for handle %d", page_address);
15281 15312 mdi_rtn = MDI_FAILURE;
15282 15313 goto virt_create_done;
15283 15314 }
15284 15315
15285 15316 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE &
15286 15317 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | (uint32_t)pdev_hdl;
15287 15318 rval = mptsas_get_sas_device_page0(mpt, page_address,
15288 15319 &dev_hdl, &pdev_sas_wwn, &pdev_info, &physport,
15289 15320 &phy_id, &pdev_hdl, &bay_num, &enclosure, &io_flags);
15290 15321 if (rval != DDI_SUCCESS) {
15291 15322 mutex_exit(&mpt->m_mutex);
15292 15323 mptsas_log(mpt, CE_WARN, "mptsas unable to get"
15293 15324 "device info for handle %d", page_address);
15294 15325 mdi_rtn = MDI_FAILURE;
15295 15326 goto virt_create_done;
15296 15327 }
15297 15328
15298 15329 mutex_exit(&mpt->m_mutex);
15299 15330
15300 15331 /*
15301 15332 * If this device direct attached to the controller
15302 15333 * set the attached-port to the base wwid
15303 15334 */
15304 15335 if ((ptgt->m_deviceinfo & DEVINFO_DIRECT_ATTACHED)
15305 15336 != DEVINFO_DIRECT_ATTACHED) {
15306 15337 (void) sprintf(pdev_wwn_str, "w%016"PRIx64,
15307 15338 pdev_sas_wwn);
15308 15339 } else {
15309 15340 /*
15310 15341 * Update the iport's attached-port to guid
15311 15342 */
15312 15343 if (sas_wwn == 0) {
15313 15344 (void) sprintf(wwn_str, "p%x", phy);
15314 15345 } else {
15315 15346 (void) sprintf(wwn_str, "w%016"PRIx64, sas_wwn);
15316 15347 }
15317 15348 if (ddi_prop_update_string(DDI_DEV_T_NONE,
15318 15349 pdip, SCSI_ADDR_PROP_ATTACHED_PORT, wwn_str) !=
15319 15350 DDI_PROP_SUCCESS) {
15320 15351 mptsas_log(mpt, CE_WARN,
15321 15352 "mptsas unable to create "
15322 15353 "property for iport target-port"
15323 15354 " %s (sas_wwn)",
15324 15355 wwn_str);
15325 15356 mdi_rtn = MDI_FAILURE;
15326 15357 goto virt_create_done;
15327 15358 }
15328 15359
15329 15360 (void) sprintf(pdev_wwn_str, "w%016"PRIx64,
15330 15361 mpt->un.m_base_wwid);
15331 15362 }
15332 15363
15333 15364 if (mdi_prop_update_string(*pip,
15334 15365 SCSI_ADDR_PROP_ATTACHED_PORT, pdev_wwn_str) !=
15335 15366 DDI_PROP_SUCCESS) {
15336 15367 mptsas_log(mpt, CE_WARN, "mptsas unable to create "
15337 15368 "property for iport attached-port %s (sas_wwn)",
15338 15369 attached_wwn_str);
15339 15370 mdi_rtn = MDI_FAILURE;
15340 15371 goto virt_create_done;
15341 15372 }
15342 15373
15343 15374
15344 15375 if (inq->inq_dtype == 0) {
15345 15376 component = kmem_zalloc(MAXPATHLEN, KM_SLEEP);
15346 15377 /*
15347 15378 * set obp path for pathinfo
15348 15379 */
15349 15380 (void) snprintf(component, MAXPATHLEN,
15350 15381 "disk@%s", lun_addr);
15351 15382
15352 15383 if (mdi_pi_pathname_obp_set(*pip, component) !=
15353 15384 DDI_SUCCESS) {
15354 15385 mptsas_log(mpt, CE_WARN, "mpt_sas driver "
15355 15386 "unable to set obp-path for object %s",
15356 15387 component);
15357 15388 mdi_rtn = MDI_FAILURE;
15358 15389 goto virt_create_done;
15359 15390 }
15360 15391 }
15361 15392
15362 15393 *lun_dip = MDI_PI(*pip)->pi_client->ct_dip;
15363 15394 if (devinfo & (MPI2_SAS_DEVICE_INFO_SATA_DEVICE |
15364 15395 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) {
15365 15396 if ((ndi_prop_update_int(DDI_DEV_T_NONE, *lun_dip,
15366 15397 "pm-capable", 1)) !=
15367 15398 DDI_PROP_SUCCESS) {
15368 15399 mptsas_log(mpt, CE_WARN, "mptsas driver"
15369 15400 "failed to create pm-capable "
15370 15401 "property, target %d", target);
15371 15402 mdi_rtn = MDI_FAILURE;
15372 15403 goto virt_create_done;
15373 15404 }
15374 15405 }
15375 15406 /*
15376 15407 * Create the phy-num property
15377 15408 */
15378 15409 if (mdi_prop_update_int(*pip, "phy-num",
15379 15410 ptgt->m_phynum) != DDI_SUCCESS) {
15380 15411 mptsas_log(mpt, CE_WARN, "mptsas driver unable to "
15381 15412 "create phy-num property for target %d lun %d",
15382 15413 target, lun);
15383 15414 mdi_rtn = MDI_FAILURE;
15384 15415 goto virt_create_done;
15385 15416 }
15386 15417 NDBG20(("new path:%s onlining,", MDI_PI(*pip)->pi_addr));
15387 15418 mdi_rtn = mdi_pi_online(*pip, 0);
15388 15419 if (mdi_rtn == MDI_SUCCESS) {
15389 15420 mutex_enter(&mpt->m_mutex);
15390 15421 ptgt->m_led_status = 0;
15391 15422 (void) mptsas_flush_led_status(mpt, ptgt);
15392 15423 mutex_exit(&mpt->m_mutex);
15393 15424 }
15394 15425 if (mdi_rtn == MDI_NOT_SUPPORTED) {
15395 15426 mdi_rtn = MDI_FAILURE;
15396 15427 }
15397 15428 virt_create_done:
15398 15429 if (*pip && mdi_rtn != MDI_SUCCESS) {
15399 15430 (void) mdi_pi_free(*pip, 0);
15400 15431 *pip = NULL;
15401 15432 *lun_dip = NULL;
15402 15433 }
15403 15434 }
15404 15435
15405 15436 scsi_hba_nodename_compatible_free(nodename, compatible);
15406 15437 if (lun_addr != NULL) {
15407 15438 kmem_free(lun_addr, SCSI_MAXNAMELEN);
15408 15439 }
15409 15440 if (wwn_str != NULL) {
15410 15441 kmem_free(wwn_str, MPTSAS_WWN_STRLEN);
15411 15442 }
15412 15443 if (component != NULL) {
15413 15444 kmem_free(component, MAXPATHLEN);
15414 15445 }
15415 15446
15416 15447 return ((mdi_rtn == MDI_SUCCESS) ? DDI_SUCCESS : DDI_FAILURE);
15417 15448 }
15418 15449
15419 15450 static int
15420 15451 mptsas_create_phys_lun(dev_info_t *pdip, struct scsi_inquiry *inq,
15421 15452 char *guid, dev_info_t **lun_dip, mptsas_target_t *ptgt, int lun)
15422 15453 {
15423 15454 int target;
15424 15455 int rval;
15425 15456 int ndi_rtn = NDI_FAILURE;
15426 15457 uint64_t be_sas_wwn;
15427 15458 char *nodename = NULL;
15428 15459 char **compatible = NULL;
15429 15460 int ncompatible = 0;
15430 15461 int instance = 0;
15431 15462 mptsas_t *mpt = DIP2MPT(pdip);
15432 15463 char *wwn_str = NULL;
15433 15464 char *component = NULL;
15434 15465 char *attached_wwn_str = NULL;
15435 15466 uint8_t phy = 0xFF;
15436 15467 uint64_t sas_wwn;
15437 15468 uint32_t devinfo;
15438 15469 uint16_t dev_hdl;
15439 15470 uint16_t pdev_hdl;
15440 15471 uint64_t pdev_sas_wwn;
15441 15472 uint64_t dev_sas_wwn;
15442 15473 uint32_t pdev_info;
15443 15474 uint8_t physport;
15444 15475 uint8_t phy_id;
15445 15476 uint32_t page_address;
15446 15477 uint16_t bay_num, enclosure, io_flags;
15447 15478 char pdev_wwn_str[MPTSAS_WWN_STRLEN];
15448 15479 uint32_t dev_info;
15449 15480 int64_t lun64 = 0;
15450 15481
15451 15482 mutex_enter(&mpt->m_mutex);
15452 15483 target = ptgt->m_devhdl;
15453 15484 sas_wwn = ptgt->m_addr.mta_wwn;
15454 15485 devinfo = ptgt->m_deviceinfo;
15455 15486 phy = ptgt->m_phynum;
15456 15487 mutex_exit(&mpt->m_mutex);
15457 15488
15458 15489 /*
15459 15490 * generate compatible property with binding-set "mpt"
15460 15491 */
15461 15492 scsi_hba_nodename_compatible_get(inq, NULL, inq->inq_dtype, NULL,
15462 15493 &nodename, &compatible, &ncompatible);
15463 15494
15464 15495 /*
15465 15496 * if nodename can't be determined then print a message and skip it
15466 15497 */
15467 15498 if (nodename == NULL) {
15468 15499 mptsas_log(mpt, CE_WARN, "mptsas found no compatible driver "
15469 15500 "for target %d lun %d", target, lun);
15470 15501 return (DDI_FAILURE);
15471 15502 }
15472 15503
15473 15504 ndi_rtn = ndi_devi_alloc(pdip, nodename,
15474 15505 DEVI_SID_NODEID, lun_dip);
15475 15506
15476 15507 /*
15477 15508 * if lun alloc success, set props
15478 15509 */
15479 15510 if (ndi_rtn == NDI_SUCCESS) {
15480 15511
15481 15512 if (ndi_prop_update_int(DDI_DEV_T_NONE,
15482 15513 *lun_dip, LUN_PROP, lun) !=
15483 15514 DDI_PROP_SUCCESS) {
15484 15515 mptsas_log(mpt, CE_WARN, "mptsas unable to create "
15485 15516 "property for target %d lun %d (LUN_PROP)",
15486 15517 target, lun);
15487 15518 ndi_rtn = NDI_FAILURE;
15488 15519 goto phys_create_done;
15489 15520 }
15490 15521
15491 15522 lun64 = (int64_t)lun;
15492 15523 if (ndi_prop_update_int64(DDI_DEV_T_NONE,
15493 15524 *lun_dip, LUN64_PROP, lun64) !=
15494 15525 DDI_PROP_SUCCESS) {
15495 15526 mptsas_log(mpt, CE_WARN, "mptsas unable to create "
15496 15527 "property for target %d lun64 %d (LUN64_PROP)",
15497 15528 target, lun);
15498 15529 ndi_rtn = NDI_FAILURE;
15499 15530 goto phys_create_done;
15500 15531 }
15501 15532 if (ndi_prop_update_string_array(DDI_DEV_T_NONE,
15502 15533 *lun_dip, "compatible", compatible, ncompatible)
15503 15534 != DDI_PROP_SUCCESS) {
15504 15535 mptsas_log(mpt, CE_WARN, "mptsas unable to create "
15505 15536 "property for target %d lun %d (COMPATIBLE)",
15506 15537 target, lun);
15507 15538 ndi_rtn = NDI_FAILURE;
15508 15539 goto phys_create_done;
15509 15540 }
15510 15541
15511 15542 /*
15512 15543 * We need the SAS WWN for non-multipath devices, so
15513 15544 * we'll use the same property as that multipathing
15514 15545 * devices need to present for MPAPI. If we don't have
15515 15546 * a WWN (e.g. parallel SCSI), don't create the prop.
15516 15547 */
15517 15548 wwn_str = kmem_zalloc(MPTSAS_WWN_STRLEN, KM_SLEEP);
15518 15549 (void) sprintf(wwn_str, "w%016"PRIx64, sas_wwn);
15519 15550 if (sas_wwn && ndi_prop_update_string(DDI_DEV_T_NONE,
15520 15551 *lun_dip, SCSI_ADDR_PROP_TARGET_PORT, wwn_str)
15521 15552 != DDI_PROP_SUCCESS) {
15522 15553 mptsas_log(mpt, CE_WARN, "mptsas unable to "
15523 15554 "create property for SAS target %d lun %d "
15524 15555 "(target-port)", target, lun);
15525 15556 ndi_rtn = NDI_FAILURE;
15526 15557 goto phys_create_done;
15527 15558 }
15528 15559
15529 15560 be_sas_wwn = BE_64(sas_wwn);
15530 15561 if (sas_wwn && ndi_prop_update_byte_array(
15531 15562 DDI_DEV_T_NONE, *lun_dip, "port-wwn",
15532 15563 (uchar_t *)&be_sas_wwn, 8) != DDI_PROP_SUCCESS) {
15533 15564 mptsas_log(mpt, CE_WARN, "mptsas unable to "
15534 15565 "create property for SAS target %d lun %d "
15535 15566 "(port-wwn)", target, lun);
15536 15567 ndi_rtn = NDI_FAILURE;
15537 15568 goto phys_create_done;
15538 15569 } else if ((sas_wwn == 0) && (ndi_prop_update_int(
15539 15570 DDI_DEV_T_NONE, *lun_dip, "sata-phy", phy) !=
15540 15571 DDI_PROP_SUCCESS)) {
15541 15572 /*
15542 15573 * Direct attached SATA device without DeviceName
15543 15574 */
15544 15575 mptsas_log(mpt, CE_WARN, "mptsas unable to "
15545 15576 "create property for SAS target %d lun %d "
15546 15577 "(sata-phy)", target, lun);
15547 15578 ndi_rtn = NDI_FAILURE;
15548 15579 goto phys_create_done;
15549 15580 }
15550 15581
15551 15582 if (ndi_prop_create_boolean(DDI_DEV_T_NONE,
15552 15583 *lun_dip, SAS_PROP) != DDI_PROP_SUCCESS) {
15553 15584 mptsas_log(mpt, CE_WARN, "mptsas unable to"
15554 15585 "create property for SAS target %d lun %d"
15555 15586 " (SAS_PROP)", target, lun);
15556 15587 ndi_rtn = NDI_FAILURE;
15557 15588 goto phys_create_done;
15558 15589 }
15559 15590 if (guid && (ndi_prop_update_string(DDI_DEV_T_NONE,
15560 15591 *lun_dip, NDI_GUID, guid) != DDI_SUCCESS)) {
15561 15592 mptsas_log(mpt, CE_WARN, "mptsas unable "
15562 15593 "to create guid property for target %d "
15563 15594 "lun %d", target, lun);
15564 15595 ndi_rtn = NDI_FAILURE;
15565 15596 goto phys_create_done;
15566 15597 }
15567 15598
15568 15599 /*
15569 15600 * The following code is to set properties for SM-HBA support,
15570 15601 * it doesn't apply to RAID volumes
15571 15602 */
15572 15603 if (ptgt->m_addr.mta_phymask == 0)
15573 15604 goto phys_raid_lun;
15574 15605
15575 15606 mutex_enter(&mpt->m_mutex);
15576 15607
15577 15608 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE &
15578 15609 MPI2_SAS_DEVICE_PGAD_FORM_MASK) |
15579 15610 (uint32_t)ptgt->m_devhdl;
15580 15611 rval = mptsas_get_sas_device_page0(mpt, page_address,
15581 15612 &dev_hdl, &dev_sas_wwn, &dev_info,
15582 15613 &physport, &phy_id, &pdev_hdl,
15583 15614 &bay_num, &enclosure, &io_flags);
15584 15615 if (rval != DDI_SUCCESS) {
15585 15616 mutex_exit(&mpt->m_mutex);
15586 15617 mptsas_log(mpt, CE_WARN, "mptsas unable to get"
15587 15618 "parent device for handle %d.", page_address);
15588 15619 ndi_rtn = NDI_FAILURE;
15589 15620 goto phys_create_done;
15590 15621 }
15591 15622
15592 15623 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE &
15593 15624 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | (uint32_t)pdev_hdl;
15594 15625 rval = mptsas_get_sas_device_page0(mpt, page_address,
15595 15626 &dev_hdl, &pdev_sas_wwn, &pdev_info, &physport,
15596 15627 &phy_id, &pdev_hdl, &bay_num, &enclosure, &io_flags);
15597 15628 if (rval != DDI_SUCCESS) {
15598 15629 mutex_exit(&mpt->m_mutex);
15599 15630 mptsas_log(mpt, CE_WARN, "mptsas unable to create "
15600 15631 "device for handle %d.", page_address);
15601 15632 ndi_rtn = NDI_FAILURE;
15602 15633 goto phys_create_done;
15603 15634 }
15604 15635
15605 15636 mutex_exit(&mpt->m_mutex);
15606 15637
15607 15638 /*
15608 15639 * If this device direct attached to the controller
15609 15640 * set the attached-port to the base wwid
15610 15641 */
15611 15642 if ((ptgt->m_deviceinfo & DEVINFO_DIRECT_ATTACHED)
15612 15643 != DEVINFO_DIRECT_ATTACHED) {
15613 15644 (void) sprintf(pdev_wwn_str, "w%016"PRIx64,
15614 15645 pdev_sas_wwn);
15615 15646 } else {
15616 15647 /*
15617 15648 * Update the iport's attached-port to guid
15618 15649 */
15619 15650 if (sas_wwn == 0) {
15620 15651 (void) sprintf(wwn_str, "p%x", phy);
15621 15652 } else {
15622 15653 (void) sprintf(wwn_str, "w%016"PRIx64, sas_wwn);
15623 15654 }
15624 15655 if (ddi_prop_update_string(DDI_DEV_T_NONE,
15625 15656 pdip, SCSI_ADDR_PROP_ATTACHED_PORT, wwn_str) !=
15626 15657 DDI_PROP_SUCCESS) {
15627 15658 mptsas_log(mpt, CE_WARN,
15628 15659 "mptsas unable to create "
15629 15660 "property for iport target-port"
15630 15661 " %s (sas_wwn)",
15631 15662 wwn_str);
15632 15663 ndi_rtn = NDI_FAILURE;
15633 15664 goto phys_create_done;
15634 15665 }
15635 15666
15636 15667 (void) sprintf(pdev_wwn_str, "w%016"PRIx64,
15637 15668 mpt->un.m_base_wwid);
15638 15669 }
15639 15670
15640 15671 if (ndi_prop_update_string(DDI_DEV_T_NONE,
15641 15672 *lun_dip, SCSI_ADDR_PROP_ATTACHED_PORT, pdev_wwn_str) !=
15642 15673 DDI_PROP_SUCCESS) {
15643 15674 mptsas_log(mpt, CE_WARN,
15644 15675 "mptsas unable to create "
15645 15676 "property for iport attached-port %s (sas_wwn)",
15646 15677 attached_wwn_str);
15647 15678 ndi_rtn = NDI_FAILURE;
15648 15679 goto phys_create_done;
15649 15680 }
15650 15681
15651 15682 if (IS_SATA_DEVICE(dev_info)) {
15652 15683 if (ndi_prop_update_string(DDI_DEV_T_NONE,
15653 15684 *lun_dip, MPTSAS_VARIANT, "sata") !=
15654 15685 DDI_PROP_SUCCESS) {
15655 15686 mptsas_log(mpt, CE_WARN,
15656 15687 "mptsas unable to create "
15657 15688 "property for device variant ");
15658 15689 ndi_rtn = NDI_FAILURE;
15659 15690 goto phys_create_done;
15660 15691 }
15661 15692 }
15662 15693
15663 15694 if (IS_ATAPI_DEVICE(dev_info)) {
15664 15695 if (ndi_prop_update_string(DDI_DEV_T_NONE,
15665 15696 *lun_dip, MPTSAS_VARIANT, "atapi") !=
15666 15697 DDI_PROP_SUCCESS) {
15667 15698 mptsas_log(mpt, CE_WARN,
15668 15699 "mptsas unable to create "
15669 15700 "property for device variant ");
15670 15701 ndi_rtn = NDI_FAILURE;
15671 15702 goto phys_create_done;
15672 15703 }
15673 15704 }
15674 15705
15675 15706 phys_raid_lun:
15676 15707 /*
15677 15708 * if this is a SAS controller, and the target is a SATA
15678 15709 * drive, set the 'pm-capable' property for sd and if on
15679 15710 * an OPL platform, also check if this is an ATAPI
15680 15711 * device.
15681 15712 */
15682 15713 instance = ddi_get_instance(mpt->m_dip);
15683 15714 if (devinfo & (MPI2_SAS_DEVICE_INFO_SATA_DEVICE |
15684 15715 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) {
15685 15716 NDBG2(("mptsas%d: creating pm-capable property, "
15686 15717 "target %d", instance, target));
15687 15718
15688 15719 if ((ndi_prop_update_int(DDI_DEV_T_NONE,
15689 15720 *lun_dip, "pm-capable", 1)) !=
15690 15721 DDI_PROP_SUCCESS) {
15691 15722 mptsas_log(mpt, CE_WARN, "mptsas "
15692 15723 "failed to create pm-capable "
15693 15724 "property, target %d", target);
15694 15725 ndi_rtn = NDI_FAILURE;
15695 15726 goto phys_create_done;
15696 15727 }
15697 15728
15698 15729 }
15699 15730
15700 15731 if ((inq->inq_dtype == 0) || (inq->inq_dtype == 5)) {
15701 15732 /*
15702 15733 * add 'obp-path' properties for devinfo
15703 15734 */
15704 15735 bzero(wwn_str, sizeof (wwn_str));
15705 15736 (void) sprintf(wwn_str, "%016"PRIx64, sas_wwn);
15706 15737 component = kmem_zalloc(MAXPATHLEN, KM_SLEEP);
15707 15738 if (guid) {
15708 15739 (void) snprintf(component, MAXPATHLEN,
15709 15740 "disk@w%s,%x", wwn_str, lun);
15710 15741 } else {
15711 15742 (void) snprintf(component, MAXPATHLEN,
15712 15743 "disk@p%x,%x", phy, lun);
15713 15744 }
15714 15745 if (ddi_pathname_obp_set(*lun_dip, component)
15715 15746 != DDI_SUCCESS) {
15716 15747 mptsas_log(mpt, CE_WARN, "mpt_sas driver "
15717 15748 "unable to set obp-path for SAS "
15718 15749 "object %s", component);
15719 15750 ndi_rtn = NDI_FAILURE;
15720 15751 goto phys_create_done;
15721 15752 }
15722 15753 }
15723 15754 /*
15724 15755 * Create the phy-num property for non-raid disk
15725 15756 */
15726 15757 if (ptgt->m_addr.mta_phymask != 0) {
15727 15758 if (ndi_prop_update_int(DDI_DEV_T_NONE,
15728 15759 *lun_dip, "phy-num", ptgt->m_phynum) !=
15729 15760 DDI_PROP_SUCCESS) {
15730 15761 mptsas_log(mpt, CE_WARN, "mptsas driver "
15731 15762 "failed to create phy-num property for "
15732 15763 "target %d", target);
15733 15764 ndi_rtn = NDI_FAILURE;
15734 15765 goto phys_create_done;
15735 15766 }
15736 15767 }
15737 15768 phys_create_done:
15738 15769 /*
15739 15770 * If props were setup ok, online the lun
15740 15771 */
15741 15772 if (ndi_rtn == NDI_SUCCESS) {
15742 15773 /*
15743 15774 * Try to online the new node
15744 15775 */
15745 15776 ndi_rtn = ndi_devi_online(*lun_dip, NDI_ONLINE_ATTACH);
15746 15777 }
15747 15778 if (ndi_rtn == NDI_SUCCESS) {
15748 15779 mutex_enter(&mpt->m_mutex);
15749 15780 ptgt->m_led_status = 0;
15750 15781 (void) mptsas_flush_led_status(mpt, ptgt);
15751 15782 mutex_exit(&mpt->m_mutex);
15752 15783 }
15753 15784
15754 15785 /*
15755 15786 * If success set rtn flag, else unwire alloc'd lun
15756 15787 */
15757 15788 if (ndi_rtn != NDI_SUCCESS) {
15758 15789 NDBG12(("mptsas driver unable to online "
15759 15790 "target %d lun %d", target, lun));
15760 15791 ndi_prop_remove_all(*lun_dip);
15761 15792 (void) ndi_devi_free(*lun_dip);
15762 15793 *lun_dip = NULL;
15763 15794 }
15764 15795 }
15765 15796
15766 15797 scsi_hba_nodename_compatible_free(nodename, compatible);
15767 15798
15768 15799 if (wwn_str != NULL) {
15769 15800 kmem_free(wwn_str, MPTSAS_WWN_STRLEN);
15770 15801 }
15771 15802 if (component != NULL) {
15772 15803 kmem_free(component, MAXPATHLEN);
15773 15804 }
15774 15805
15775 15806
15776 15807 return ((ndi_rtn == NDI_SUCCESS) ? DDI_SUCCESS : DDI_FAILURE);
15777 15808 }
15778 15809
15779 15810 static int
15780 15811 mptsas_probe_smp(dev_info_t *pdip, uint64_t wwn)
15781 15812 {
15782 15813 mptsas_t *mpt = DIP2MPT(pdip);
15783 15814 struct smp_device smp_sd;
15784 15815
15785 15816 /* XXX An HBA driver should not be allocating an smp_device. */
15786 15817 bzero(&smp_sd, sizeof (struct smp_device));
15787 15818 smp_sd.smp_sd_address.smp_a_hba_tran = mpt->m_smptran;
15788 15819 bcopy(&wwn, smp_sd.smp_sd_address.smp_a_wwn, SAS_WWN_BYTE_SIZE);
15789 15820
15790 15821 if (smp_probe(&smp_sd) != DDI_PROBE_SUCCESS)
15791 15822 return (NDI_FAILURE);
15792 15823 return (NDI_SUCCESS);
15793 15824 }
15794 15825
15795 15826 static int
15796 15827 mptsas_config_smp(dev_info_t *pdip, uint64_t sas_wwn, dev_info_t **smp_dip)
15797 15828 {
15798 15829 mptsas_t *mpt = DIP2MPT(pdip);
15799 15830 mptsas_smp_t *psmp = NULL;
15800 15831 int rval;
15801 15832 int phymask;
15802 15833
15803 15834 /*
15804 15835 * Get the physical port associated to the iport
15805 15836 * PHYMASK TODO
15806 15837 */
15807 15838 phymask = ddi_prop_get_int(DDI_DEV_T_ANY, pdip, 0,
15808 15839 "phymask", 0);
15809 15840 /*
15810 15841 * Find the smp node in hash table with specified sas address and
15811 15842 * physical port
15812 15843 */
15813 15844 psmp = mptsas_wwid_to_psmp(mpt, phymask, sas_wwn);
15814 15845 if (psmp == NULL) {
15815 15846 return (DDI_FAILURE);
15816 15847 }
15817 15848
15818 15849 rval = mptsas_online_smp(pdip, psmp, smp_dip);
15819 15850
15820 15851 return (rval);
15821 15852 }
15822 15853
15823 15854 static int
15824 15855 mptsas_online_smp(dev_info_t *pdip, mptsas_smp_t *smp_node,
15825 15856 dev_info_t **smp_dip)
15826 15857 {
15827 15858 char wwn_str[MPTSAS_WWN_STRLEN];
15828 15859 char attached_wwn_str[MPTSAS_WWN_STRLEN];
15829 15860 int ndi_rtn = NDI_FAILURE;
15830 15861 int rval = 0;
15831 15862 mptsas_smp_t dev_info;
15832 15863 uint32_t page_address;
15833 15864 mptsas_t *mpt = DIP2MPT(pdip);
15834 15865 uint16_t dev_hdl;
15835 15866 uint64_t sas_wwn;
15836 15867 uint64_t smp_sas_wwn;
15837 15868 uint8_t physport;
15838 15869 uint8_t phy_id;
15839 15870 uint16_t pdev_hdl;
15840 15871 uint8_t numphys = 0;
15841 15872 uint16_t i = 0;
15842 15873 char phymask[MPTSAS_MAX_PHYS];
15843 15874 char *iport = NULL;
15844 15875 mptsas_phymask_t phy_mask = 0;
15845 15876 uint16_t attached_devhdl;
15846 15877 uint16_t bay_num, enclosure, io_flags;
15847 15878
15848 15879 (void) sprintf(wwn_str, "%"PRIx64, smp_node->m_addr.mta_wwn);
15849 15880
15850 15881 /*
15851 15882 * Probe smp device, prevent the node of removed device from being
15852 15883 * configured succesfully
15853 15884 */
15854 15885 if (mptsas_probe_smp(pdip, smp_node->m_addr.mta_wwn) != NDI_SUCCESS) {
15855 15886 return (DDI_FAILURE);
15856 15887 }
15857 15888
15858 15889 if ((*smp_dip = mptsas_find_smp_child(pdip, wwn_str)) != NULL) {
15859 15890 return (DDI_SUCCESS);
15860 15891 }
15861 15892
15862 15893 ndi_rtn = ndi_devi_alloc(pdip, "smp", DEVI_SID_NODEID, smp_dip);
15863 15894
15864 15895 /*
15865 15896 * if lun alloc success, set props
15866 15897 */
15867 15898 if (ndi_rtn == NDI_SUCCESS) {
15868 15899 /*
15869 15900 * Set the flavor of the child to be SMP flavored
15870 15901 */
15871 15902 ndi_flavor_set(*smp_dip, SCSA_FLAVOR_SMP);
15872 15903
15873 15904 if (ndi_prop_update_string(DDI_DEV_T_NONE,
15874 15905 *smp_dip, SMP_WWN, wwn_str) !=
15875 15906 DDI_PROP_SUCCESS) {
15876 15907 mptsas_log(mpt, CE_WARN, "mptsas unable to create "
15877 15908 "property for smp device %s (sas_wwn)",
15878 15909 wwn_str);
15879 15910 ndi_rtn = NDI_FAILURE;
15880 15911 goto smp_create_done;
15881 15912 }
15882 15913 (void) sprintf(wwn_str, "w%"PRIx64, smp_node->m_addr.mta_wwn);
15883 15914 if (ndi_prop_update_string(DDI_DEV_T_NONE,
15884 15915 *smp_dip, SCSI_ADDR_PROP_TARGET_PORT, wwn_str) !=
15885 15916 DDI_PROP_SUCCESS) {
15886 15917 mptsas_log(mpt, CE_WARN, "mptsas unable to create "
15887 15918 "property for iport target-port %s (sas_wwn)",
15888 15919 wwn_str);
15889 15920 ndi_rtn = NDI_FAILURE;
15890 15921 goto smp_create_done;
15891 15922 }
15892 15923
15893 15924 mutex_enter(&mpt->m_mutex);
15894 15925
15895 15926 page_address = (MPI2_SAS_EXPAND_PGAD_FORM_HNDL &
15896 15927 MPI2_SAS_EXPAND_PGAD_FORM_MASK) | smp_node->m_devhdl;
15897 15928 rval = mptsas_get_sas_expander_page0(mpt, page_address,
15898 15929 &dev_info);
15899 15930 if (rval != DDI_SUCCESS) {
15900 15931 mutex_exit(&mpt->m_mutex);
15901 15932 mptsas_log(mpt, CE_WARN,
15902 15933 "mptsas unable to get expander "
15903 15934 "parent device info for %x", page_address);
15904 15935 ndi_rtn = NDI_FAILURE;
15905 15936 goto smp_create_done;
15906 15937 }
15907 15938
15908 15939 smp_node->m_pdevhdl = dev_info.m_pdevhdl;
15909 15940 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE &
15910 15941 MPI2_SAS_DEVICE_PGAD_FORM_MASK) |
15911 15942 (uint32_t)dev_info.m_pdevhdl;
15912 15943 rval = mptsas_get_sas_device_page0(mpt, page_address,
15913 15944 &dev_hdl, &sas_wwn, &smp_node->m_pdevinfo, &physport,
15914 15945 &phy_id, &pdev_hdl, &bay_num, &enclosure, &io_flags);
15915 15946 if (rval != DDI_SUCCESS) {
15916 15947 mutex_exit(&mpt->m_mutex);
15917 15948 mptsas_log(mpt, CE_WARN, "mptsas unable to get "
15918 15949 "device info for %x", page_address);
15919 15950 ndi_rtn = NDI_FAILURE;
15920 15951 goto smp_create_done;
15921 15952 }
15922 15953
15923 15954 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE &
15924 15955 MPI2_SAS_DEVICE_PGAD_FORM_MASK) |
15925 15956 (uint32_t)dev_info.m_devhdl;
15926 15957 rval = mptsas_get_sas_device_page0(mpt, page_address,
15927 15958 &dev_hdl, &smp_sas_wwn, &smp_node->m_deviceinfo,
15928 15959 &physport, &phy_id, &pdev_hdl, &bay_num, &enclosure,
15929 15960 &io_flags);
15930 15961 if (rval != DDI_SUCCESS) {
15931 15962 mutex_exit(&mpt->m_mutex);
15932 15963 mptsas_log(mpt, CE_WARN, "mptsas unable to get "
15933 15964 "device info for %x", page_address);
15934 15965 ndi_rtn = NDI_FAILURE;
15935 15966 goto smp_create_done;
15936 15967 }
15937 15968 mutex_exit(&mpt->m_mutex);
15938 15969
15939 15970 /*
15940 15971 * If this smp direct attached to the controller
15941 15972 * set the attached-port to the base wwid
15942 15973 */
15943 15974 if ((smp_node->m_deviceinfo & DEVINFO_DIRECT_ATTACHED)
15944 15975 != DEVINFO_DIRECT_ATTACHED) {
15945 15976 (void) sprintf(attached_wwn_str, "w%016"PRIx64,
15946 15977 sas_wwn);
15947 15978 } else {
15948 15979 (void) sprintf(attached_wwn_str, "w%016"PRIx64,
15949 15980 mpt->un.m_base_wwid);
15950 15981 }
15951 15982
15952 15983 if (ndi_prop_update_string(DDI_DEV_T_NONE,
15953 15984 *smp_dip, SCSI_ADDR_PROP_ATTACHED_PORT, attached_wwn_str) !=
15954 15985 DDI_PROP_SUCCESS) {
15955 15986 mptsas_log(mpt, CE_WARN, "mptsas unable to create "
15956 15987 "property for smp attached-port %s (sas_wwn)",
15957 15988 attached_wwn_str);
15958 15989 ndi_rtn = NDI_FAILURE;
15959 15990 goto smp_create_done;
15960 15991 }
15961 15992
15962 15993 if (ndi_prop_create_boolean(DDI_DEV_T_NONE,
15963 15994 *smp_dip, SMP_PROP) != DDI_PROP_SUCCESS) {
15964 15995 mptsas_log(mpt, CE_WARN, "mptsas unable to "
15965 15996 "create property for SMP %s (SMP_PROP) ",
15966 15997 wwn_str);
15967 15998 ndi_rtn = NDI_FAILURE;
15968 15999 goto smp_create_done;
15969 16000 }
15970 16001
15971 16002 /*
15972 16003 * check the smp to see whether it direct
15973 16004 * attached to the controller
15974 16005 */
15975 16006 if ((smp_node->m_deviceinfo & DEVINFO_DIRECT_ATTACHED)
15976 16007 != DEVINFO_DIRECT_ATTACHED) {
15977 16008 goto smp_create_done;
15978 16009 }
15979 16010 numphys = ddi_prop_get_int(DDI_DEV_T_ANY, pdip,
15980 16011 DDI_PROP_DONTPASS, MPTSAS_NUM_PHYS, -1);
15981 16012 if (numphys > 0) {
15982 16013 goto smp_create_done;
15983 16014 }
15984 16015 /*
15985 16016 * this iport is an old iport, we need to
15986 16017 * reconfig the props for it.
15987 16018 */
15988 16019 if (ddi_prop_update_int(DDI_DEV_T_NONE, pdip,
15989 16020 MPTSAS_VIRTUAL_PORT, 0) !=
15990 16021 DDI_PROP_SUCCESS) {
15991 16022 (void) ddi_prop_remove(DDI_DEV_T_NONE, pdip,
15992 16023 MPTSAS_VIRTUAL_PORT);
15993 16024 mptsas_log(mpt, CE_WARN, "mptsas virtual port "
15994 16025 "prop update failed");
15995 16026 goto smp_create_done;
15996 16027 }
15997 16028
15998 16029 mutex_enter(&mpt->m_mutex);
15999 16030 numphys = 0;
16000 16031 iport = ddi_get_name_addr(pdip);
16001 16032 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
16002 16033 bzero(phymask, sizeof (phymask));
16003 16034 (void) sprintf(phymask,
16004 16035 "%x", mpt->m_phy_info[i].phy_mask);
16005 16036 if (strcmp(phymask, iport) == 0) {
16006 16037 phy_mask = mpt->m_phy_info[i].phy_mask;
16007 16038 break;
16008 16039 }
16009 16040 }
16010 16041
16011 16042 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
16012 16043 if ((phy_mask >> i) & 0x01) {
16013 16044 numphys++;
16014 16045 }
16015 16046 }
16016 16047 /*
16017 16048 * Update PHY info for smhba
16018 16049 */
16019 16050 if (mptsas_smhba_phy_init(mpt)) {
16020 16051 mutex_exit(&mpt->m_mutex);
16021 16052 mptsas_log(mpt, CE_WARN, "mptsas phy update "
16022 16053 "failed");
16023 16054 goto smp_create_done;
16024 16055 }
16025 16056 mutex_exit(&mpt->m_mutex);
16026 16057
16027 16058 mptsas_smhba_set_all_phy_props(mpt, pdip, numphys, phy_mask,
16028 16059 &attached_devhdl);
16029 16060
16030 16061 if (ddi_prop_update_int(DDI_DEV_T_NONE, pdip,
16031 16062 MPTSAS_NUM_PHYS, numphys) !=
16032 16063 DDI_PROP_SUCCESS) {
16033 16064 (void) ddi_prop_remove(DDI_DEV_T_NONE, pdip,
16034 16065 MPTSAS_NUM_PHYS);
16035 16066 mptsas_log(mpt, CE_WARN, "mptsas update "
16036 16067 "num phys props failed");
16037 16068 goto smp_create_done;
16038 16069 }
16039 16070 /*
16040 16071 * Add parent's props for SMHBA support
16041 16072 */
16042 16073 if (ddi_prop_update_string(DDI_DEV_T_NONE, pdip,
16043 16074 SCSI_ADDR_PROP_ATTACHED_PORT, wwn_str) !=
16044 16075 DDI_PROP_SUCCESS) {
16045 16076 (void) ddi_prop_remove(DDI_DEV_T_NONE, pdip,
16046 16077 SCSI_ADDR_PROP_ATTACHED_PORT);
16047 16078 mptsas_log(mpt, CE_WARN, "mptsas update iport"
16048 16079 "attached-port failed");
16049 16080 goto smp_create_done;
16050 16081 }
16051 16082
16052 16083 smp_create_done:
16053 16084 /*
16054 16085 * If props were setup ok, online the lun
16055 16086 */
16056 16087 if (ndi_rtn == NDI_SUCCESS) {
16057 16088 /*
16058 16089 * Try to online the new node
16059 16090 */
16060 16091 ndi_rtn = ndi_devi_online(*smp_dip, NDI_ONLINE_ATTACH);
16061 16092 }
16062 16093
16063 16094 /*
16064 16095 * If success set rtn flag, else unwire alloc'd lun
16065 16096 */
16066 16097 if (ndi_rtn != NDI_SUCCESS) {
16067 16098 NDBG12(("mptsas unable to online "
16068 16099 "SMP target %s", wwn_str));
16069 16100 ndi_prop_remove_all(*smp_dip);
16070 16101 (void) ndi_devi_free(*smp_dip);
16071 16102 }
16072 16103 }
16073 16104
16074 16105 return ((ndi_rtn == NDI_SUCCESS) ? DDI_SUCCESS : DDI_FAILURE);
16075 16106 }
16076 16107
16077 16108 /* smp transport routine */
16078 16109 static int mptsas_smp_start(struct smp_pkt *smp_pkt)
16079 16110 {
16080 16111 uint64_t wwn;
16081 16112 Mpi2SmpPassthroughRequest_t req;
16082 16113 Mpi2SmpPassthroughReply_t rep;
16083 16114 uint32_t direction = 0;
16084 16115 mptsas_t *mpt;
16085 16116 int ret;
16086 16117 uint64_t tmp64;
16087 16118
16088 16119 mpt = (mptsas_t *)smp_pkt->smp_pkt_address->
16089 16120 smp_a_hba_tran->smp_tran_hba_private;
16090 16121
16091 16122 bcopy(smp_pkt->smp_pkt_address->smp_a_wwn, &wwn, SAS_WWN_BYTE_SIZE);
16092 16123 /*
16093 16124 * Need to compose a SMP request message
16094 16125 * and call mptsas_do_passthru() function
16095 16126 */
16096 16127 bzero(&req, sizeof (req));
16097 16128 bzero(&rep, sizeof (rep));
16098 16129 req.PassthroughFlags = 0;
16099 16130 req.PhysicalPort = 0xff;
16100 16131 req.ChainOffset = 0;
16101 16132 req.Function = MPI2_FUNCTION_SMP_PASSTHROUGH;
16102 16133
16103 16134 if ((smp_pkt->smp_pkt_reqsize & 0xffff0000ul) != 0) {
16104 16135 smp_pkt->smp_pkt_reason = ERANGE;
16105 16136 return (DDI_FAILURE);
16106 16137 }
16107 16138 req.RequestDataLength = LE_16((uint16_t)(smp_pkt->smp_pkt_reqsize - 4));
16108 16139
16109 16140 req.MsgFlags = 0;
16110 16141 tmp64 = LE_64(wwn);
16111 16142 bcopy(&tmp64, &req.SASAddress, SAS_WWN_BYTE_SIZE);
16112 16143 if (smp_pkt->smp_pkt_rspsize > 0) {
16113 16144 direction |= MPTSAS_PASS_THRU_DIRECTION_READ;
16114 16145 }
16115 16146 if (smp_pkt->smp_pkt_reqsize > 0) {
16116 16147 direction |= MPTSAS_PASS_THRU_DIRECTION_WRITE;
16117 16148 }
16118 16149
16119 16150 mutex_enter(&mpt->m_mutex);
16120 16151 ret = mptsas_do_passthru(mpt, (uint8_t *)&req, (uint8_t *)&rep,
16121 16152 (uint8_t *)smp_pkt->smp_pkt_rsp,
16122 16153 offsetof(Mpi2SmpPassthroughRequest_t, SGL), sizeof (rep),
16123 16154 smp_pkt->smp_pkt_rspsize - 4, direction,
16124 16155 (uint8_t *)smp_pkt->smp_pkt_req, smp_pkt->smp_pkt_reqsize - 4,
16125 16156 smp_pkt->smp_pkt_timeout, FKIOCTL);
16126 16157 mutex_exit(&mpt->m_mutex);
16127 16158 if (ret != 0) {
16128 16159 cmn_err(CE_WARN, "smp_start do passthru error %d", ret);
16129 16160 smp_pkt->smp_pkt_reason = (uchar_t)(ret);
16130 16161 return (DDI_FAILURE);
16131 16162 }
16132 16163 /* do passthrough success, check the smp status */
16133 16164 if (LE_16(rep.IOCStatus) != MPI2_IOCSTATUS_SUCCESS) {
16134 16165 switch (LE_16(rep.IOCStatus)) {
16135 16166 case MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE:
16136 16167 smp_pkt->smp_pkt_reason = ENODEV;
16137 16168 break;
16138 16169 case MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN:
16139 16170 smp_pkt->smp_pkt_reason = EOVERFLOW;
16140 16171 break;
16141 16172 case MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED:
16142 16173 smp_pkt->smp_pkt_reason = EIO;
16143 16174 break;
16144 16175 default:
16145 16176 mptsas_log(mpt, CE_NOTE, "smp_start: get unknown ioc"
16146 16177 "status:%x", LE_16(rep.IOCStatus));
16147 16178 smp_pkt->smp_pkt_reason = EIO;
16148 16179 break;
16149 16180 }
16150 16181 return (DDI_FAILURE);
16151 16182 }
16152 16183 if (rep.SASStatus != MPI2_SASSTATUS_SUCCESS) {
16153 16184 mptsas_log(mpt, CE_NOTE, "smp_start: get error SAS status:%x",
16154 16185 rep.SASStatus);
16155 16186 smp_pkt->smp_pkt_reason = EIO;
16156 16187 return (DDI_FAILURE);
16157 16188 }
16158 16189
16159 16190 return (DDI_SUCCESS);
16160 16191 }
16161 16192
16162 16193 /*
16163 16194 * If we didn't get a match, we need to get sas page0 for each device, and
16164 16195 * untill we get a match. If failed, return NULL
16165 16196 */
16166 16197 static mptsas_target_t *
16167 16198 mptsas_phy_to_tgt(mptsas_t *mpt, mptsas_phymask_t phymask, uint8_t phy)
16168 16199 {
16169 16200 int i, j = 0;
16170 16201 int rval = 0;
16171 16202 uint16_t cur_handle;
16172 16203 uint32_t page_address;
16173 16204 mptsas_target_t *ptgt = NULL;
16174 16205
16175 16206 /*
16176 16207 * PHY named device must be direct attached and attaches to
16177 16208 * narrow port, if the iport is not parent of the device which
16178 16209 * we are looking for.
16179 16210 */
16180 16211 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
16181 16212 if ((1 << i) & phymask)
16182 16213 j++;
16183 16214 }
16184 16215
16185 16216 if (j > 1)
16186 16217 return (NULL);
16187 16218
16188 16219 /*
16189 16220 * Must be a narrow port and single device attached to the narrow port
16190 16221 * So the physical port num of device which is equal to the iport's
16191 16222 * port num is the device what we are looking for.
16192 16223 */
16193 16224
16194 16225 if (mpt->m_phy_info[phy].phy_mask != phymask)
16195 16226 return (NULL);
16196 16227
16197 16228 mutex_enter(&mpt->m_mutex);
16198 16229
16199 16230 ptgt = refhash_linear_search(mpt->m_targets, mptsas_target_eval_nowwn,
16200 16231 &phy);
16201 16232 if (ptgt != NULL) {
16202 16233 mutex_exit(&mpt->m_mutex);
16203 16234 return (ptgt);
16204 16235 }
16205 16236
16206 16237 if (mpt->m_done_traverse_dev) {
16207 16238 mutex_exit(&mpt->m_mutex);
16208 16239 return (NULL);
16209 16240 }
16210 16241
16211 16242 /* If didn't get a match, come here */
16212 16243 cur_handle = mpt->m_dev_handle;
16213 16244 for (; ; ) {
16214 16245 ptgt = NULL;
16215 16246 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE &
16216 16247 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | (uint32_t)cur_handle;
16217 16248 rval = mptsas_get_target_device_info(mpt, page_address,
16218 16249 &cur_handle, &ptgt);
16219 16250 if ((rval == DEV_INFO_FAIL_PAGE0) ||
16220 16251 (rval == DEV_INFO_FAIL_ALLOC) ||
16221 16252 (rval == DEV_INFO_FAIL_GUID)) {
16222 16253 break;
16223 16254 }
16224 16255 if ((rval == DEV_INFO_WRONG_DEVICE_TYPE) ||
16225 16256 (rval == DEV_INFO_PHYS_DISK)) {
16226 16257 continue;
16227 16258 }
16228 16259 mpt->m_dev_handle = cur_handle;
16229 16260
16230 16261 if ((ptgt->m_addr.mta_wwn == 0) && (ptgt->m_phynum == phy)) {
16231 16262 break;
16232 16263 }
16233 16264 }
16234 16265
16235 16266 mutex_exit(&mpt->m_mutex);
16236 16267 return (ptgt);
16237 16268 }
16238 16269
16239 16270 /*
16240 16271 * The ptgt->m_addr.mta_wwn contains the wwid for each disk.
16241 16272 * For Raid volumes, we need to check m_raidvol[x].m_raidwwid
16242 16273 * If we didn't get a match, we need to get sas page0 for each device, and
16243 16274 * untill we get a match
16244 16275 * If failed, return NULL
16245 16276 */
16246 16277 static mptsas_target_t *
16247 16278 mptsas_wwid_to_ptgt(mptsas_t *mpt, mptsas_phymask_t phymask, uint64_t wwid)
16248 16279 {
16249 16280 int rval = 0;
16250 16281 uint16_t cur_handle;
16251 16282 uint32_t page_address;
16252 16283 mptsas_target_t *tmp_tgt = NULL;
16253 16284 mptsas_target_addr_t addr;
16254 16285
16255 16286 addr.mta_wwn = wwid;
16256 16287 addr.mta_phymask = phymask;
16257 16288 mutex_enter(&mpt->m_mutex);
16258 16289 tmp_tgt = refhash_lookup(mpt->m_targets, &addr);
16259 16290 if (tmp_tgt != NULL) {
16260 16291 mutex_exit(&mpt->m_mutex);
16261 16292 return (tmp_tgt);
16262 16293 }
16263 16294
16264 16295 if (phymask == 0) {
16265 16296 /*
16266 16297 * It's IR volume
16267 16298 */
16268 16299 rval = mptsas_get_raid_info(mpt);
16269 16300 if (rval) {
16270 16301 tmp_tgt = refhash_lookup(mpt->m_targets, &addr);
16271 16302 }
16272 16303 mutex_exit(&mpt->m_mutex);
16273 16304 return (tmp_tgt);
16274 16305 }
16275 16306
16276 16307 if (mpt->m_done_traverse_dev) {
16277 16308 mutex_exit(&mpt->m_mutex);
16278 16309 return (NULL);
16279 16310 }
16280 16311
16281 16312 /* If didn't get a match, come here */
16282 16313 cur_handle = mpt->m_dev_handle;
16283 16314 for (;;) {
16284 16315 tmp_tgt = NULL;
16285 16316 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE &
16286 16317 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | cur_handle;
16287 16318 rval = mptsas_get_target_device_info(mpt, page_address,
16288 16319 &cur_handle, &tmp_tgt);
16289 16320 if ((rval == DEV_INFO_FAIL_PAGE0) ||
16290 16321 (rval == DEV_INFO_FAIL_ALLOC) ||
16291 16322 (rval == DEV_INFO_FAIL_GUID)) {
16292 16323 tmp_tgt = NULL;
16293 16324 break;
16294 16325 }
16295 16326 if ((rval == DEV_INFO_WRONG_DEVICE_TYPE) ||
16296 16327 (rval == DEV_INFO_PHYS_DISK)) {
16297 16328 continue;
16298 16329 }
16299 16330 mpt->m_dev_handle = cur_handle;
16300 16331 if ((tmp_tgt->m_addr.mta_wwn) &&
16301 16332 (tmp_tgt->m_addr.mta_wwn == wwid) &&
16302 16333 (tmp_tgt->m_addr.mta_phymask == phymask)) {
16303 16334 break;
16304 16335 }
16305 16336 }
16306 16337
16307 16338 mutex_exit(&mpt->m_mutex);
16308 16339 return (tmp_tgt);
16309 16340 }
16310 16341
16311 16342 static mptsas_smp_t *
16312 16343 mptsas_wwid_to_psmp(mptsas_t *mpt, mptsas_phymask_t phymask, uint64_t wwid)
16313 16344 {
16314 16345 int rval = 0;
16315 16346 uint16_t cur_handle;
16316 16347 uint32_t page_address;
16317 16348 mptsas_smp_t smp_node, *psmp = NULL;
16318 16349 mptsas_target_addr_t addr;
16319 16350
16320 16351 addr.mta_wwn = wwid;
16321 16352 addr.mta_phymask = phymask;
16322 16353 mutex_enter(&mpt->m_mutex);
16323 16354 psmp = refhash_lookup(mpt->m_smp_targets, &addr);
16324 16355 if (psmp != NULL) {
16325 16356 mutex_exit(&mpt->m_mutex);
16326 16357 return (psmp);
16327 16358 }
16328 16359
16329 16360 if (mpt->m_done_traverse_smp) {
16330 16361 mutex_exit(&mpt->m_mutex);
16331 16362 return (NULL);
16332 16363 }
16333 16364
16334 16365 /* If didn't get a match, come here */
16335 16366 cur_handle = mpt->m_smp_devhdl;
16336 16367 for (;;) {
16337 16368 psmp = NULL;
16338 16369 page_address = (MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL &
16339 16370 MPI2_SAS_EXPAND_PGAD_FORM_MASK) | (uint32_t)cur_handle;
16340 16371 rval = mptsas_get_sas_expander_page0(mpt, page_address,
16341 16372 &smp_node);
16342 16373 if (rval != DDI_SUCCESS) {
16343 16374 break;
16344 16375 }
16345 16376 mpt->m_smp_devhdl = cur_handle = smp_node.m_devhdl;
16346 16377 psmp = mptsas_smp_alloc(mpt, &smp_node);
16347 16378 ASSERT(psmp);
16348 16379 if ((psmp->m_addr.mta_wwn) && (psmp->m_addr.mta_wwn == wwid) &&
16349 16380 (psmp->m_addr.mta_phymask == phymask)) {
16350 16381 break;
16351 16382 }
16352 16383 }
16353 16384
16354 16385 mutex_exit(&mpt->m_mutex);
16355 16386 return (psmp);
16356 16387 }
16357 16388
16358 16389 mptsas_target_t *
16359 16390 mptsas_tgt_alloc(refhash_t *refhash, uint16_t devhdl, uint64_t wwid,
16360 16391 uint32_t devinfo, mptsas_phymask_t phymask, uint8_t phynum)
16361 16392 {
16362 16393 mptsas_target_t *tmp_tgt = NULL;
16363 16394 mptsas_target_addr_t addr;
16364 16395
16365 16396 addr.mta_wwn = wwid;
16366 16397 addr.mta_phymask = phymask;
16367 16398 tmp_tgt = refhash_lookup(refhash, &addr);
16368 16399 if (tmp_tgt != NULL) {
16369 16400 NDBG20(("Hash item already exist"));
16370 16401 tmp_tgt->m_deviceinfo = devinfo;
16371 16402 tmp_tgt->m_devhdl = devhdl; /* XXX - duplicate? */
16372 16403 return (tmp_tgt);
16373 16404 }
16374 16405 tmp_tgt = kmem_zalloc(sizeof (struct mptsas_target), KM_SLEEP);
16375 16406 if (tmp_tgt == NULL) {
16376 16407 cmn_err(CE_WARN, "Fatal, allocated tgt failed");
16377 16408 return (NULL);
16378 16409 }
16379 16410 tmp_tgt->m_devhdl = devhdl;
16380 16411 tmp_tgt->m_addr.mta_wwn = wwid;
16381 16412 tmp_tgt->m_deviceinfo = devinfo;
16382 16413 tmp_tgt->m_addr.mta_phymask = phymask;
16383 16414 tmp_tgt->m_phynum = phynum;
16384 16415 /* Initialized the tgt structure */
16385 16416 tmp_tgt->m_qfull_retries = QFULL_RETRIES;
16386 16417 tmp_tgt->m_qfull_retry_interval =
16387 16418 drv_usectohz(QFULL_RETRY_INTERVAL * 1000);
16388 16419 tmp_tgt->m_t_throttle = MAX_THROTTLE;
16389 16420 TAILQ_INIT(&tmp_tgt->m_active_cmdq);
16390 16421
16391 16422 refhash_insert(refhash, tmp_tgt);
16392 16423
16393 16424 return (tmp_tgt);
16394 16425 }
16395 16426
16396 16427 static void
16397 16428 mptsas_smp_target_copy(mptsas_smp_t *src, mptsas_smp_t *dst)
16398 16429 {
16399 16430 dst->m_devhdl = src->m_devhdl;
16400 16431 dst->m_deviceinfo = src->m_deviceinfo;
16401 16432 dst->m_pdevhdl = src->m_pdevhdl;
16402 16433 dst->m_pdevinfo = src->m_pdevinfo;
16403 16434 }
16404 16435
16405 16436 static mptsas_smp_t *
16406 16437 mptsas_smp_alloc(mptsas_t *mpt, mptsas_smp_t *data)
16407 16438 {
16408 16439 mptsas_target_addr_t addr;
16409 16440 mptsas_smp_t *ret_data;
16410 16441
16411 16442 addr.mta_wwn = data->m_addr.mta_wwn;
16412 16443 addr.mta_phymask = data->m_addr.mta_phymask;
16413 16444 ret_data = refhash_lookup(mpt->m_smp_targets, &addr);
16414 16445 /*
16415 16446 * If there's already a matching SMP target, update its fields
16416 16447 * in place. Since the address is not changing, it's safe to do
16417 16448 * this. We cannot just bcopy() here because the structure we've
16418 16449 * been given has invalid hash links.
16419 16450 */
16420 16451 if (ret_data != NULL) {
16421 16452 mptsas_smp_target_copy(data, ret_data);
16422 16453 return (ret_data);
16423 16454 }
16424 16455
16425 16456 ret_data = kmem_alloc(sizeof (mptsas_smp_t), KM_SLEEP);
16426 16457 bcopy(data, ret_data, sizeof (mptsas_smp_t));
16427 16458 refhash_insert(mpt->m_smp_targets, ret_data);
16428 16459 return (ret_data);
16429 16460 }
16430 16461
16431 16462 /*
16432 16463 * Functions for SGPIO LED support
16433 16464 */
16434 16465 static dev_info_t *
16435 16466 mptsas_get_dip_from_dev(dev_t dev, mptsas_phymask_t *phymask)
16436 16467 {
16437 16468 dev_info_t *dip;
16438 16469 int prop;
16439 16470 dip = e_ddi_hold_devi_by_dev(dev, 0);
16440 16471 if (dip == NULL)
16441 16472 return (dip);
16442 16473 prop = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 0,
16443 16474 "phymask", 0);
16444 16475 *phymask = (mptsas_phymask_t)prop;
16445 16476 ddi_release_devi(dip);
16446 16477 return (dip);
16447 16478 }
16448 16479 static mptsas_target_t *
16449 16480 mptsas_addr_to_ptgt(mptsas_t *mpt, char *addr, mptsas_phymask_t phymask)
16450 16481 {
16451 16482 uint8_t phynum;
16452 16483 uint64_t wwn;
16453 16484 int lun;
16454 16485 mptsas_target_t *ptgt = NULL;
16455 16486
16456 16487 if (mptsas_parse_address(addr, &wwn, &phynum, &lun) != DDI_SUCCESS) {
16457 16488 return (NULL);
16458 16489 }
16459 16490 if (addr[0] == 'w') {
16460 16491 ptgt = mptsas_wwid_to_ptgt(mpt, (int)phymask, wwn);
16461 16492 } else {
16462 16493 ptgt = mptsas_phy_to_tgt(mpt, (int)phymask, phynum);
16463 16494 }
16464 16495 return (ptgt);
16465 16496 }
16466 16497
16467 16498 static int
16468 16499 mptsas_flush_led_status(mptsas_t *mpt, mptsas_target_t *ptgt)
16469 16500 {
16470 16501 uint32_t slotstatus = 0;
16471 16502
16472 16503 /* Build an MPI2 Slot Status based on our view of the world */
16473 16504 if (ptgt->m_led_status & (1 << (MPTSAS_LEDCTL_LED_IDENT - 1)))
16474 16505 slotstatus |= MPI2_SEP_REQ_SLOTSTATUS_IDENTIFY_REQUEST;
16475 16506 if (ptgt->m_led_status & (1 << (MPTSAS_LEDCTL_LED_FAIL - 1)))
16476 16507 slotstatus |= MPI2_SEP_REQ_SLOTSTATUS_PREDICTED_FAULT;
16477 16508 if (ptgt->m_led_status & (1 << (MPTSAS_LEDCTL_LED_OK2RM - 1)))
16478 16509 slotstatus |= MPI2_SEP_REQ_SLOTSTATUS_REQUEST_REMOVE;
16479 16510
16480 16511 /* Write it to the controller */
16481 16512 NDBG14(("mptsas_ioctl: set LED status %x for slot %x",
16482 16513 slotstatus, ptgt->m_slot_num));
16483 16514 return (mptsas_send_sep(mpt, ptgt, &slotstatus,
16484 16515 MPI2_SEP_REQ_ACTION_WRITE_STATUS));
16485 16516 }
16486 16517
16487 16518 /*
16488 16519 * send sep request, use enclosure/slot addressing
16489 16520 */
16490 16521 static int
16491 16522 mptsas_send_sep(mptsas_t *mpt, mptsas_target_t *ptgt,
16492 16523 uint32_t *status, uint8_t act)
16493 16524 {
16494 16525 Mpi2SepRequest_t req;
16495 16526 Mpi2SepReply_t rep;
16496 16527 int ret;
16497 16528
16498 16529 ASSERT(mutex_owned(&mpt->m_mutex));
16499 16530
16500 16531 /*
16501 16532 * We only support SEP control of directly-attached targets, in which
16502 16533 * case the "SEP" we're talking to is a virtual one contained within
16503 16534 * the HBA itself. This is necessary because DA targets typically have
16504 16535 * no other mechanism for LED control. Targets for which a separate
16505 16536 * enclosure service processor exists should be controlled via ses(7d)
16506 16537 * or sgen(7d). Furthermore, since such requests can time out, they
16507 16538 * should be made in user context rather than in response to
16508 16539 * asynchronous fabric changes.
16509 16540 *
16510 16541 * In addition, we do not support this operation for RAID volumes,
16511 16542 * since there is no slot associated with them.
16512 16543 */
16513 16544 if (!(ptgt->m_deviceinfo & DEVINFO_DIRECT_ATTACHED) ||
16514 16545 ptgt->m_addr.mta_phymask == 0) {
16515 16546 return (ENOTTY);
16516 16547 }
16517 16548
16518 16549 bzero(&req, sizeof (req));
16519 16550 bzero(&rep, sizeof (rep));
16520 16551
16521 16552 req.Function = MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR;
16522 16553 req.Action = act;
16523 16554 req.Flags = MPI2_SEP_REQ_FLAGS_ENCLOSURE_SLOT_ADDRESS;
16524 16555 req.EnclosureHandle = LE_16(ptgt->m_enclosure);
16525 16556 req.Slot = LE_16(ptgt->m_slot_num);
16526 16557 if (act == MPI2_SEP_REQ_ACTION_WRITE_STATUS) {
16527 16558 req.SlotStatus = LE_32(*status);
16528 16559 }
16529 16560 ret = mptsas_do_passthru(mpt, (uint8_t *)&req, (uint8_t *)&rep, NULL,
16530 16561 sizeof (req), sizeof (rep), NULL, 0, NULL, 0, 60, FKIOCTL);
16531 16562 if (ret != 0) {
16532 16563 mptsas_log(mpt, CE_NOTE, "mptsas_send_sep: passthru SEP "
16533 16564 "Processor Request message error %d", ret);
16534 16565 return (ret);
16535 16566 }
16536 16567 /* do passthrough success, check the ioc status */
16537 16568 if (LE_16(rep.IOCStatus) != MPI2_IOCSTATUS_SUCCESS) {
16538 16569 mptsas_log(mpt, CE_NOTE, "send_sep act %x: ioc "
16539 16570 "status:%x loginfo %x", act, LE_16(rep.IOCStatus),
16540 16571 LE_32(rep.IOCLogInfo));
16541 16572 switch (LE_16(rep.IOCStatus) & MPI2_IOCSTATUS_MASK) {
16542 16573 case MPI2_IOCSTATUS_INVALID_FUNCTION:
16543 16574 case MPI2_IOCSTATUS_INVALID_VPID:
16544 16575 case MPI2_IOCSTATUS_INVALID_FIELD:
16545 16576 case MPI2_IOCSTATUS_INVALID_STATE:
16546 16577 case MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED:
16547 16578 case MPI2_IOCSTATUS_CONFIG_INVALID_ACTION:
16548 16579 case MPI2_IOCSTATUS_CONFIG_INVALID_TYPE:
16549 16580 case MPI2_IOCSTATUS_CONFIG_INVALID_PAGE:
16550 16581 case MPI2_IOCSTATUS_CONFIG_INVALID_DATA:
16551 16582 case MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS:
16552 16583 return (EINVAL);
16553 16584 case MPI2_IOCSTATUS_BUSY:
16554 16585 return (EBUSY);
16555 16586 case MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES:
16556 16587 return (EAGAIN);
16557 16588 case MPI2_IOCSTATUS_INVALID_SGL:
16558 16589 case MPI2_IOCSTATUS_INTERNAL_ERROR:
16559 16590 case MPI2_IOCSTATUS_CONFIG_CANT_COMMIT:
16560 16591 default:
16561 16592 return (EIO);
16562 16593 }
16563 16594 }
16564 16595 if (act != MPI2_SEP_REQ_ACTION_WRITE_STATUS) {
16565 16596 *status = LE_32(rep.SlotStatus);
16566 16597 }
16567 16598
16568 16599 return (0);
16569 16600 }
16570 16601
16571 16602 int
16572 16603 mptsas_dma_addr_create(mptsas_t *mpt, ddi_dma_attr_t dma_attr,
16573 16604 ddi_dma_handle_t *dma_hdp, ddi_acc_handle_t *acc_hdp, caddr_t *dma_memp,
16574 16605 uint32_t alloc_size, ddi_dma_cookie_t *cookiep)
16575 16606 {
16576 16607 ddi_dma_cookie_t new_cookie;
16577 16608 size_t alloc_len;
16578 16609 uint_t ncookie;
16579 16610
16580 16611 if (cookiep == NULL)
16581 16612 cookiep = &new_cookie;
16582 16613
16583 16614 if (ddi_dma_alloc_handle(mpt->m_dip, &dma_attr, DDI_DMA_SLEEP,
16584 16615 NULL, dma_hdp) != DDI_SUCCESS) {
16585 16616 return (FALSE);
16586 16617 }
16587 16618
16588 16619 if (ddi_dma_mem_alloc(*dma_hdp, alloc_size, &mpt->m_dev_acc_attr,
16589 16620 DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, NULL, dma_memp, &alloc_len,
16590 16621 acc_hdp) != DDI_SUCCESS) {
16591 16622 ddi_dma_free_handle(dma_hdp);
16592 16623 *dma_hdp = NULL;
16593 16624 return (FALSE);
16594 16625 }
16595 16626
16596 16627 if (ddi_dma_addr_bind_handle(*dma_hdp, NULL, *dma_memp, alloc_len,
16597 16628 (DDI_DMA_RDWR | DDI_DMA_CONSISTENT), DDI_DMA_SLEEP, NULL,
16598 16629 cookiep, &ncookie) != DDI_DMA_MAPPED) {
16599 16630 (void) ddi_dma_mem_free(acc_hdp);
16600 16631 ddi_dma_free_handle(dma_hdp);
16601 16632 *dma_hdp = NULL;
16602 16633 return (FALSE);
16603 16634 }
16604 16635
16605 16636 return (TRUE);
16606 16637 }
16607 16638
16608 16639 void
16609 16640 mptsas_dma_addr_destroy(ddi_dma_handle_t *dma_hdp, ddi_acc_handle_t *acc_hdp)
16610 16641 {
16611 16642 if (*dma_hdp == NULL)
16612 16643 return;
16613 16644
16614 16645 (void) ddi_dma_unbind_handle(*dma_hdp);
16615 16646 (void) ddi_dma_mem_free(acc_hdp);
16616 16647 ddi_dma_free_handle(dma_hdp);
16617 16648 *dma_hdp = NULL;
16618 16649 }
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