1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright (c) 2009, 2010, Oracle and/or its affiliates. All rights reserved.
24 * Copyright 2016 Nexenta Systems, Inc. All rights reserved.
25 * Copyright (c) 2014, Joyent, Inc. All rights reserved.
26 * Copyright 2014 OmniTI Computer Consulting, Inc. All rights reserved.
27 * Copyright (c) 2014, Tegile Systems Inc. All rights reserved.
28 */
29
30 /*
31 * Copyright (c) 2000 to 2010, LSI Corporation.
32 * All rights reserved.
33 *
34 * Redistribution and use in source and binary forms of all code within
35 * this file that is exclusively owned by LSI, with or without
36 * modification, is permitted provided that, in addition to the CDDL 1.0
37 * License requirements, the following conditions are met:
38 *
39 * Neither the name of the author nor the names of its contributors may be
40 * used to endorse or promote products derived from this software without
41 * specific prior written permission.
42 *
43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
46 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
47 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
48 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
49 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
50 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
51 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
52 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
53 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
54 * DAMAGE.
55 */
56
57 /*
58 * mptsas - This is a driver based on LSI Logic's MPT2.0/2.5 interface.
59 *
60 */
61
62 #if defined(lint) || defined(DEBUG)
63 #define MPTSAS_DEBUG
64 #endif
65
66 /*
67 * standard header files.
68 */
69 #include <sys/note.h>
70 #include <sys/scsi/scsi.h>
71 #include <sys/pci.h>
72 #include <sys/file.h>
73 #include <sys/policy.h>
74 #include <sys/model.h>
75 #include <sys/sysevent.h>
76 #include <sys/sysevent/eventdefs.h>
77 #include <sys/sysevent/dr.h>
78 #include <sys/sata/sata_defs.h>
79 #include <sys/sata/sata_hba.h>
80 #include <sys/scsi/generic/sas.h>
81 #include <sys/scsi/impl/scsi_sas.h>
82
83 #pragma pack(1)
84 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_type.h>
85 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2.h>
86 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_cnfg.h>
87 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_init.h>
88 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_ioc.h>
89 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_sas.h>
90 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_tool.h>
91 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_raid.h>
92 #pragma pack()
93
94 /*
95 * private header files.
96 *
97 */
98 #include <sys/scsi/impl/scsi_reset_notify.h>
99 #include <sys/scsi/adapters/mpt_sas/mptsas_var.h>
100 #include <sys/scsi/adapters/mpt_sas/mptsas_ioctl.h>
101 #include <sys/scsi/adapters/mpt_sas/mptsas_smhba.h>
102 #include <sys/scsi/adapters/mpt_sas/mptsas_hash.h>
103 #include <sys/raidioctl.h>
104
105 #include <sys/fs/dv_node.h> /* devfs_clean */
106
107 /*
108 * FMA header files
109 */
110 #include <sys/ddifm.h>
111 #include <sys/fm/protocol.h>
112 #include <sys/fm/util.h>
113 #include <sys/fm/io/ddi.h>
114
115 /*
116 * autoconfiguration data and routines.
117 */
118 static int mptsas_attach(dev_info_t *dip, ddi_attach_cmd_t cmd);
119 static int mptsas_detach(dev_info_t *devi, ddi_detach_cmd_t cmd);
120 static int mptsas_power(dev_info_t *dip, int component, int level);
121
122 /*
123 * cb_ops function
124 */
125 static int mptsas_ioctl(dev_t dev, int cmd, intptr_t data, int mode,
126 cred_t *credp, int *rval);
127 #ifdef __sparc
128 static int mptsas_reset(dev_info_t *devi, ddi_reset_cmd_t cmd);
129 #else /* __sparc */
130 static int mptsas_quiesce(dev_info_t *devi);
131 #endif /* __sparc */
132
133 /*
134 * Resource initilaization for hardware
135 */
136 static void mptsas_setup_cmd_reg(mptsas_t *mpt);
137 static void mptsas_disable_bus_master(mptsas_t *mpt);
138 static void mptsas_hba_fini(mptsas_t *mpt);
139 static void mptsas_cfg_fini(mptsas_t *mptsas_blkp);
140 static int mptsas_hba_setup(mptsas_t *mpt);
141 static void mptsas_hba_teardown(mptsas_t *mpt);
142 static int mptsas_config_space_init(mptsas_t *mpt);
143 static void mptsas_config_space_fini(mptsas_t *mpt);
144 static void mptsas_iport_register(mptsas_t *mpt);
145 static int mptsas_smp_setup(mptsas_t *mpt);
146 static void mptsas_smp_teardown(mptsas_t *mpt);
147 static int mptsas_cache_create(mptsas_t *mpt);
148 static void mptsas_cache_destroy(mptsas_t *mpt);
149 static int mptsas_alloc_request_frames(mptsas_t *mpt);
150 static int mptsas_alloc_sense_bufs(mptsas_t *mpt);
151 static int mptsas_alloc_reply_frames(mptsas_t *mpt);
152 static int mptsas_alloc_free_queue(mptsas_t *mpt);
153 static int mptsas_alloc_post_queue(mptsas_t *mpt);
154 static void mptsas_alloc_reply_args(mptsas_t *mpt);
155 static int mptsas_alloc_extra_sgl_frame(mptsas_t *mpt, mptsas_cmd_t *cmd);
156 static void mptsas_free_extra_sgl_frame(mptsas_t *mpt, mptsas_cmd_t *cmd);
157 static int mptsas_init_chip(mptsas_t *mpt, int first_time);
158
159 /*
160 * SCSA function prototypes
161 */
162 static int mptsas_scsi_start(struct scsi_address *ap, struct scsi_pkt *pkt);
163 static int mptsas_scsi_reset(struct scsi_address *ap, int level);
164 static int mptsas_scsi_abort(struct scsi_address *ap, struct scsi_pkt *pkt);
165 static int mptsas_scsi_getcap(struct scsi_address *ap, char *cap, int tgtonly);
166 static int mptsas_scsi_setcap(struct scsi_address *ap, char *cap, int value,
167 int tgtonly);
168 static void mptsas_scsi_dmafree(struct scsi_address *ap, struct scsi_pkt *pkt);
169 static struct scsi_pkt *mptsas_scsi_init_pkt(struct scsi_address *ap,
170 struct scsi_pkt *pkt, struct buf *bp, int cmdlen, int statuslen,
171 int tgtlen, int flags, int (*callback)(), caddr_t arg);
172 static void mptsas_scsi_sync_pkt(struct scsi_address *ap, struct scsi_pkt *pkt);
173 static void mptsas_scsi_destroy_pkt(struct scsi_address *ap,
174 struct scsi_pkt *pkt);
175 static int mptsas_scsi_tgt_init(dev_info_t *hba_dip, dev_info_t *tgt_dip,
176 scsi_hba_tran_t *hba_tran, struct scsi_device *sd);
177 static void mptsas_scsi_tgt_free(dev_info_t *hba_dip, dev_info_t *tgt_dip,
178 scsi_hba_tran_t *hba_tran, struct scsi_device *sd);
179 static int mptsas_scsi_reset_notify(struct scsi_address *ap, int flag,
180 void (*callback)(caddr_t), caddr_t arg);
181 static int mptsas_get_name(struct scsi_device *sd, char *name, int len);
182 static int mptsas_get_bus_addr(struct scsi_device *sd, char *name, int len);
183 static int mptsas_scsi_quiesce(dev_info_t *dip);
184 static int mptsas_scsi_unquiesce(dev_info_t *dip);
185 static int mptsas_bus_config(dev_info_t *pdip, uint_t flags,
186 ddi_bus_config_op_t op, void *arg, dev_info_t **childp);
187
188 /*
189 * SMP functions
190 */
191 static int mptsas_smp_start(struct smp_pkt *smp_pkt);
192
193 /*
194 * internal function prototypes.
195 */
196 static void mptsas_list_add(mptsas_t *mpt);
197 static void mptsas_list_del(mptsas_t *mpt);
198
199 static int mptsas_quiesce_bus(mptsas_t *mpt);
200 static int mptsas_unquiesce_bus(mptsas_t *mpt);
201
202 static int mptsas_alloc_handshake_msg(mptsas_t *mpt, size_t alloc_size);
203 static void mptsas_free_handshake_msg(mptsas_t *mpt);
204
205 static void mptsas_ncmds_checkdrain(void *arg);
206
207 static int mptsas_prepare_pkt(mptsas_cmd_t *cmd);
208 static int mptsas_accept_pkt(mptsas_t *mpt, mptsas_cmd_t *sp);
209 static int mptsas_accept_txwq_and_pkt(mptsas_t *mpt, mptsas_cmd_t *sp);
210 static void mptsas_accept_tx_waitq(mptsas_t *mpt);
211
212 static int mptsas_do_detach(dev_info_t *dev);
213 static int mptsas_do_scsi_reset(mptsas_t *mpt, uint16_t devhdl);
214 static int mptsas_do_scsi_abort(mptsas_t *mpt, int target, int lun,
215 struct scsi_pkt *pkt);
216 static int mptsas_scsi_capchk(char *cap, int tgtonly, int *cidxp);
217
218 static void mptsas_handle_qfull(mptsas_t *mpt, mptsas_cmd_t *cmd);
219 static void mptsas_handle_event(void *args);
220 static int mptsas_handle_event_sync(void *args);
221 static void mptsas_handle_dr(void *args);
222 static void mptsas_handle_topo_change(mptsas_topo_change_list_t *topo_node,
223 dev_info_t *pdip);
224
225 static void mptsas_restart_cmd(void *);
226
227 static void mptsas_flush_hba(mptsas_t *mpt);
228 static void mptsas_flush_target(mptsas_t *mpt, ushort_t target, int lun,
229 uint8_t tasktype);
230 static void mptsas_set_pkt_reason(mptsas_t *mpt, mptsas_cmd_t *cmd,
231 uchar_t reason, uint_t stat);
232
233 static uint_t mptsas_intr(caddr_t arg1, caddr_t arg2);
234 static void mptsas_process_intr(mptsas_t *mpt,
235 pMpi2ReplyDescriptorsUnion_t reply_desc_union);
236 static void mptsas_handle_scsi_io_success(mptsas_t *mpt,
237 pMpi2ReplyDescriptorsUnion_t reply_desc);
238 static void mptsas_handle_address_reply(mptsas_t *mpt,
239 pMpi2ReplyDescriptorsUnion_t reply_desc);
240 static int mptsas_wait_intr(mptsas_t *mpt, int polltime);
241 static void mptsas_sge_setup(mptsas_t *mpt, mptsas_cmd_t *cmd,
242 uint32_t *control, pMpi2SCSIIORequest_t frame, ddi_acc_handle_t acc_hdl);
243
244 static void mptsas_watch(void *arg);
245 static void mptsas_watchsubr(mptsas_t *mpt);
246 static void mptsas_cmd_timeout(mptsas_t *mpt, mptsas_target_t *ptgt);
247
248 static void mptsas_start_passthru(mptsas_t *mpt, mptsas_cmd_t *cmd);
249 static int mptsas_do_passthru(mptsas_t *mpt, uint8_t *request, uint8_t *reply,
250 uint8_t *data, uint32_t request_size, uint32_t reply_size,
251 uint32_t data_size, uint32_t direction, uint8_t *dataout,
252 uint32_t dataout_size, short timeout, int mode);
253 static int mptsas_free_devhdl(mptsas_t *mpt, uint16_t devhdl);
254
255 static uint8_t mptsas_get_fw_diag_buffer_number(mptsas_t *mpt,
256 uint32_t unique_id);
257 static void mptsas_start_diag(mptsas_t *mpt, mptsas_cmd_t *cmd);
258 static int mptsas_post_fw_diag_buffer(mptsas_t *mpt,
259 mptsas_fw_diagnostic_buffer_t *pBuffer, uint32_t *return_code);
260 static int mptsas_release_fw_diag_buffer(mptsas_t *mpt,
261 mptsas_fw_diagnostic_buffer_t *pBuffer, uint32_t *return_code,
262 uint32_t diag_type);
263 static int mptsas_diag_register(mptsas_t *mpt,
264 mptsas_fw_diag_register_t *diag_register, uint32_t *return_code);
265 static int mptsas_diag_unregister(mptsas_t *mpt,
266 mptsas_fw_diag_unregister_t *diag_unregister, uint32_t *return_code);
267 static int mptsas_diag_query(mptsas_t *mpt, mptsas_fw_diag_query_t *diag_query,
268 uint32_t *return_code);
269 static int mptsas_diag_read_buffer(mptsas_t *mpt,
270 mptsas_diag_read_buffer_t *diag_read_buffer, uint8_t *ioctl_buf,
271 uint32_t *return_code, int ioctl_mode);
272 static int mptsas_diag_release(mptsas_t *mpt,
273 mptsas_fw_diag_release_t *diag_release, uint32_t *return_code);
274 static int mptsas_do_diag_action(mptsas_t *mpt, uint32_t action,
275 uint8_t *diag_action, uint32_t length, uint32_t *return_code,
276 int ioctl_mode);
277 static int mptsas_diag_action(mptsas_t *mpt, mptsas_diag_action_t *data,
278 int mode);
279
280 static int mptsas_pkt_alloc_extern(mptsas_t *mpt, mptsas_cmd_t *cmd,
281 int cmdlen, int tgtlen, int statuslen, int kf);
282 static void mptsas_pkt_destroy_extern(mptsas_t *mpt, mptsas_cmd_t *cmd);
283
284 static int mptsas_kmem_cache_constructor(void *buf, void *cdrarg, int kmflags);
285 static void mptsas_kmem_cache_destructor(void *buf, void *cdrarg);
286
287 static int mptsas_cache_frames_constructor(void *buf, void *cdrarg,
288 int kmflags);
289 static void mptsas_cache_frames_destructor(void *buf, void *cdrarg);
290
291 static void mptsas_check_scsi_io_error(mptsas_t *mpt, pMpi2SCSIIOReply_t reply,
292 mptsas_cmd_t *cmd);
293 static void mptsas_check_task_mgt(mptsas_t *mpt,
294 pMpi2SCSIManagementReply_t reply, mptsas_cmd_t *cmd);
295 static int mptsas_send_scsi_cmd(mptsas_t *mpt, struct scsi_address *ap,
296 mptsas_target_t *ptgt, uchar_t *cdb, int cdblen, struct buf *data_bp,
297 int *resid);
298
299 static int mptsas_alloc_active_slots(mptsas_t *mpt, int flag);
300 static void mptsas_free_active_slots(mptsas_t *mpt);
301 static int mptsas_start_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd);
302
303 static void mptsas_restart_hba(mptsas_t *mpt);
304 static void mptsas_restart_waitq(mptsas_t *mpt);
305
306 static void mptsas_deliver_doneq_thread(mptsas_t *mpt);
307 static void mptsas_doneq_add(mptsas_t *mpt, mptsas_cmd_t *cmd);
308 static void mptsas_doneq_mv(mptsas_t *mpt, uint64_t t);
309
310 static mptsas_cmd_t *mptsas_doneq_thread_rm(mptsas_t *mpt, uint64_t t);
311 static void mptsas_doneq_empty(mptsas_t *mpt);
312 static void mptsas_doneq_thread(mptsas_doneq_thread_arg_t *arg);
313
314 static mptsas_cmd_t *mptsas_waitq_rm(mptsas_t *mpt);
315 static void mptsas_waitq_delete(mptsas_t *mpt, mptsas_cmd_t *cmd);
316 static mptsas_cmd_t *mptsas_tx_waitq_rm(mptsas_t *mpt);
317 static void mptsas_tx_waitq_delete(mptsas_t *mpt, mptsas_cmd_t *cmd);
318
319
320 static void mptsas_start_watch_reset_delay();
321 static void mptsas_setup_bus_reset_delay(mptsas_t *mpt);
322 static void mptsas_watch_reset_delay(void *arg);
323 static int mptsas_watch_reset_delay_subr(mptsas_t *mpt);
324
325 /*
326 * helper functions
327 */
328 static void mptsas_dump_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd);
329
330 static dev_info_t *mptsas_find_child(dev_info_t *pdip, char *name);
331 static dev_info_t *mptsas_find_child_phy(dev_info_t *pdip, uint8_t phy);
332 static dev_info_t *mptsas_find_child_addr(dev_info_t *pdip, uint64_t sasaddr,
333 int lun);
334 static mdi_pathinfo_t *mptsas_find_path_addr(dev_info_t *pdip, uint64_t sasaddr,
335 int lun);
336 static mdi_pathinfo_t *mptsas_find_path_phy(dev_info_t *pdip, uint8_t phy);
337 static dev_info_t *mptsas_find_smp_child(dev_info_t *pdip, char *str_wwn);
338
339 static int mptsas_parse_address(char *name, uint64_t *wwid, uint8_t *phy,
340 int *lun);
341 static int mptsas_parse_smp_name(char *name, uint64_t *wwn);
342
343 static mptsas_target_t *mptsas_phy_to_tgt(mptsas_t *mpt,
344 mptsas_phymask_t phymask, uint8_t phy);
345 static mptsas_target_t *mptsas_wwid_to_ptgt(mptsas_t *mpt,
346 mptsas_phymask_t phymask, uint64_t wwid);
347 static mptsas_smp_t *mptsas_wwid_to_psmp(mptsas_t *mpt,
348 mptsas_phymask_t phymask, uint64_t wwid);
349
350 static int mptsas_inquiry(mptsas_t *mpt, mptsas_target_t *ptgt, int lun,
351 uchar_t page, unsigned char *buf, int len, int *rlen, uchar_t evpd);
352
353 static int mptsas_get_target_device_info(mptsas_t *mpt, uint32_t page_address,
354 uint16_t *handle, mptsas_target_t **pptgt);
355 static void mptsas_update_phymask(mptsas_t *mpt);
356
357 static int mptsas_send_sep(mptsas_t *mpt, mptsas_target_t *ptgt,
358 uint32_t *status, uint8_t cmd);
359 static dev_info_t *mptsas_get_dip_from_dev(dev_t dev,
360 mptsas_phymask_t *phymask);
361 static mptsas_target_t *mptsas_addr_to_ptgt(mptsas_t *mpt, char *addr,
362 mptsas_phymask_t phymask);
363 static int mptsas_flush_led_status(mptsas_t *mpt, mptsas_target_t *ptgt);
364
365
366 /*
367 * Enumeration / DR functions
368 */
369 static void mptsas_config_all(dev_info_t *pdip);
370 static int mptsas_config_one_addr(dev_info_t *pdip, uint64_t sasaddr, int lun,
371 dev_info_t **lundip);
372 static int mptsas_config_one_phy(dev_info_t *pdip, uint8_t phy, int lun,
373 dev_info_t **lundip);
374
375 static int mptsas_config_target(dev_info_t *pdip, mptsas_target_t *ptgt);
376 static int mptsas_offline_target(dev_info_t *pdip, char *name);
377
378 static int mptsas_config_raid(dev_info_t *pdip, uint16_t target,
379 dev_info_t **dip);
380
381 static int mptsas_config_luns(dev_info_t *pdip, mptsas_target_t *ptgt);
382 static int mptsas_probe_lun(dev_info_t *pdip, int lun,
383 dev_info_t **dip, mptsas_target_t *ptgt);
384
385 static int mptsas_create_lun(dev_info_t *pdip, struct scsi_inquiry *sd_inq,
386 dev_info_t **dip, mptsas_target_t *ptgt, int lun);
387
388 static int mptsas_create_phys_lun(dev_info_t *pdip, struct scsi_inquiry *sd,
389 char *guid, dev_info_t **dip, mptsas_target_t *ptgt, int lun);
390 static int mptsas_create_virt_lun(dev_info_t *pdip, struct scsi_inquiry *sd,
391 char *guid, dev_info_t **dip, mdi_pathinfo_t **pip, mptsas_target_t *ptgt,
392 int lun);
393
394 static void mptsas_offline_missed_luns(dev_info_t *pdip,
395 uint16_t *repluns, int lun_cnt, mptsas_target_t *ptgt);
396 static int mptsas_offline_lun(dev_info_t *pdip, dev_info_t *rdip,
397 mdi_pathinfo_t *rpip, uint_t flags);
398
399 static int mptsas_config_smp(dev_info_t *pdip, uint64_t sas_wwn,
400 dev_info_t **smp_dip);
401 static int mptsas_offline_smp(dev_info_t *pdip, mptsas_smp_t *smp_node,
402 uint_t flags);
403
404 static int mptsas_event_query(mptsas_t *mpt, mptsas_event_query_t *data,
405 int mode, int *rval);
406 static int mptsas_event_enable(mptsas_t *mpt, mptsas_event_enable_t *data,
407 int mode, int *rval);
408 static int mptsas_event_report(mptsas_t *mpt, mptsas_event_report_t *data,
409 int mode, int *rval);
410 static void mptsas_record_event(void *args);
411 static int mptsas_reg_access(mptsas_t *mpt, mptsas_reg_access_t *data,
412 int mode);
413
414 mptsas_target_t *mptsas_tgt_alloc(refhash_t *, uint16_t, uint64_t,
415 uint32_t, mptsas_phymask_t, uint8_t);
416 static mptsas_smp_t *mptsas_smp_alloc(mptsas_t *, mptsas_smp_t *);
417 static int mptsas_online_smp(dev_info_t *pdip, mptsas_smp_t *smp_node,
418 dev_info_t **smp_dip);
419
420 /*
421 * Power management functions
422 */
423 static int mptsas_get_pci_cap(mptsas_t *mpt);
424 static int mptsas_init_pm(mptsas_t *mpt);
425
426 /*
427 * MPT MSI tunable:
428 *
429 * By default MSI is enabled on all supported platforms.
430 */
431 boolean_t mptsas_enable_msi = B_TRUE;
432 boolean_t mptsas_physical_bind_failed_page_83 = B_FALSE;
433
434 /*
435 * Global switch for use of MPI2.5 FAST PATH.
436 * We don't really know what FAST PATH actually does, so if it is suspected
437 * to cause problems it can be turned off by setting this variable to B_FALSE.
438 */
439 boolean_t mptsas_use_fastpath = B_TRUE;
440
441 static int mptsas_register_intrs(mptsas_t *);
442 static void mptsas_unregister_intrs(mptsas_t *);
443 static int mptsas_add_intrs(mptsas_t *, int);
444 static void mptsas_rem_intrs(mptsas_t *);
445
446 /*
447 * FMA Prototypes
448 */
449 static void mptsas_fm_init(mptsas_t *mpt);
450 static void mptsas_fm_fini(mptsas_t *mpt);
451 static int mptsas_fm_error_cb(dev_info_t *, ddi_fm_error_t *, const void *);
452
453 extern pri_t minclsyspri, maxclsyspri;
454
455 /*
456 * This device is created by the SCSI pseudo nexus driver (SCSI vHCI). It is
457 * under this device that the paths to a physical device are created when
458 * MPxIO is used.
459 */
460 extern dev_info_t *scsi_vhci_dip;
461
462 /*
463 * Tunable timeout value for Inquiry VPD page 0x83
464 * By default the value is 30 seconds.
465 */
466 int mptsas_inq83_retry_timeout = 30;
467
468 /*
469 * This is used to allocate memory for message frame storage, not for
470 * data I/O DMA. All message frames must be stored in the first 4G of
471 * physical memory.
472 */
473 ddi_dma_attr_t mptsas_dma_attrs = {
474 DMA_ATTR_V0, /* attribute layout version */
475 0x0ull, /* address low - should be 0 (longlong) */
476 0xffffffffull, /* address high - 32-bit max range */
477 0x00ffffffull, /* count max - max DMA object size */
478 4, /* allocation alignment requirements */
479 0x78, /* burstsizes - binary encoded values */
480 1, /* minxfer - gran. of DMA engine */
481 0x00ffffffull, /* maxxfer - gran. of DMA engine */
482 0xffffffffull, /* max segment size (DMA boundary) */
483 MPTSAS_MAX_DMA_SEGS, /* scatter/gather list length */
484 512, /* granularity - device transfer size */
485 0 /* flags, set to 0 */
486 };
487
488 /*
489 * This is used for data I/O DMA memory allocation. (full 64-bit DMA
490 * physical addresses are supported.)
491 */
492 ddi_dma_attr_t mptsas_dma_attrs64 = {
493 DMA_ATTR_V0, /* attribute layout version */
494 0x0ull, /* address low - should be 0 (longlong) */
495 0xffffffffffffffffull, /* address high - 64-bit max */
496 0x00ffffffull, /* count max - max DMA object size */
497 4, /* allocation alignment requirements */
498 0x78, /* burstsizes - binary encoded values */
499 1, /* minxfer - gran. of DMA engine */
500 0x00ffffffull, /* maxxfer - gran. of DMA engine */
501 0xffffffffull, /* max segment size (DMA boundary) */
502 MPTSAS_MAX_DMA_SEGS, /* scatter/gather list length */
503 512, /* granularity - device transfer size */
504 0 /* flags, set to 0 */
505 };
506
507 ddi_device_acc_attr_t mptsas_dev_attr = {
508 DDI_DEVICE_ATTR_V1,
509 DDI_STRUCTURE_LE_ACC,
510 DDI_STRICTORDER_ACC,
511 DDI_DEFAULT_ACC
512 };
513
514 static struct cb_ops mptsas_cb_ops = {
515 scsi_hba_open, /* open */
516 scsi_hba_close, /* close */
517 nodev, /* strategy */
518 nodev, /* print */
519 nodev, /* dump */
520 nodev, /* read */
521 nodev, /* write */
522 mptsas_ioctl, /* ioctl */
523 nodev, /* devmap */
524 nodev, /* mmap */
525 nodev, /* segmap */
526 nochpoll, /* chpoll */
527 ddi_prop_op, /* cb_prop_op */
528 NULL, /* streamtab */
529 D_MP, /* cb_flag */
530 CB_REV, /* rev */
531 nodev, /* aread */
532 nodev /* awrite */
533 };
534
535 static struct dev_ops mptsas_ops = {
536 DEVO_REV, /* devo_rev, */
537 0, /* refcnt */
538 ddi_no_info, /* info */
539 nulldev, /* identify */
540 nulldev, /* probe */
541 mptsas_attach, /* attach */
542 mptsas_detach, /* detach */
543 #ifdef __sparc
544 mptsas_reset,
545 #else
546 nodev, /* reset */
547 #endif /* __sparc */
548 &mptsas_cb_ops, /* driver operations */
549 NULL, /* bus operations */
550 mptsas_power, /* power management */
551 #ifdef __sparc
552 ddi_quiesce_not_needed
553 #else
554 mptsas_quiesce /* quiesce */
555 #endif /* __sparc */
556 };
557
558
559 #define MPTSAS_MOD_STRING "MPTSAS HBA Driver 00.00.00.24X"
560
561 static struct modldrv modldrv = {
562 &mod_driverops, /* Type of module. This one is a driver */
563 MPTSAS_MOD_STRING, /* Name of the module. */
564 &mptsas_ops, /* driver ops */
565 };
566
567 static struct modlinkage modlinkage = {
568 MODREV_1, &modldrv, NULL
569 };
570 #define TARGET_PROP "target"
571 #define LUN_PROP "lun"
572 #define LUN64_PROP "lun64"
573 #define SAS_PROP "sas-mpt"
574 #define MDI_GUID "wwn"
575 #define NDI_GUID "guid"
576 #define MPTSAS_DEV_GONE "mptsas_dev_gone"
577
578 /*
579 * Local static data
580 */
581 #if defined(MPTSAS_DEBUG)
582 /*
583 * Flags to indicate which debug messages are to be printed and which go to the
584 * debug log ring buffer. Default is to not print anything, and to log
585 * everything except the watchsubr() output which normally happens every second.
586 */
587 uint32_t mptsas_debugprt_flags = 0x0;
588 uint32_t mptsas_debuglog_flags = ~(1U << 30);
589 #endif /* defined(MPTSAS_DEBUG) */
590 uint32_t mptsas_debug_resets = 0;
591
592 static kmutex_t mptsas_global_mutex;
593 static void *mptsas_state; /* soft state ptr */
594 static krwlock_t mptsas_global_rwlock;
595
596 static kmutex_t mptsas_log_mutex;
597 static char mptsas_log_buf[256];
598 _NOTE(MUTEX_PROTECTS_DATA(mptsas_log_mutex, mptsas_log_buf))
599
600 static mptsas_t *mptsas_head, *mptsas_tail;
601 static clock_t mptsas_scsi_watchdog_tick;
602 static clock_t mptsas_tick;
603 static timeout_id_t mptsas_reset_watch;
604 static timeout_id_t mptsas_timeout_id;
605 static int mptsas_timeouts_enabled = 0;
606
607 /*
608 * Default length for extended auto request sense buffers.
609 * All sense buffers need to be under the same alloc because there
610 * is only one common top 32bits (of 64bits) address register.
611 * Most requests only require 32 bytes, but some request >256.
612 * We use rmalloc()/rmfree() on this additional memory to manage the
613 * "extended" requests.
614 */
615 int mptsas_extreq_sense_bufsize = 256*64;
616
617 /*
618 * We believe that all software resrictions of having to run with DMA
619 * attributes to limit allocation to the first 4G are removed.
620 * However, this flag remains to enable quick switchback should suspicious
621 * problems emerge.
622 * Note that scsi_alloc_consistent_buf() does still adhere to allocating
623 * 32 bit addressable memory, but we can cope if that is changed now.
624 */
625 int mptsas_use_64bit_msgaddr = 1;
626
627 /*
628 * warlock directives
629 */
630 _NOTE(SCHEME_PROTECTS_DATA("unique per pkt", scsi_pkt \
631 mptsas_cmd NcrTableIndirect buf scsi_cdb scsi_status))
632 _NOTE(SCHEME_PROTECTS_DATA("unique per pkt", smp_pkt))
633 _NOTE(SCHEME_PROTECTS_DATA("stable data", scsi_device scsi_address))
634 _NOTE(SCHEME_PROTECTS_DATA("No Mutex Needed", mptsas_tgt_private))
635 _NOTE(SCHEME_PROTECTS_DATA("No Mutex Needed", scsi_hba_tran::tran_tgt_private))
636
637 /*
638 * SM - HBA statics
639 */
640 char *mptsas_driver_rev = MPTSAS_MOD_STRING;
641
642 #ifdef MPTSAS_DEBUG
643 void debug_enter(char *);
644 #endif
645
646 /*
647 * Notes:
648 * - scsi_hba_init(9F) initializes SCSI HBA modules
649 * - must call scsi_hba_fini(9F) if modload() fails
650 */
651 int
652 _init(void)
653 {
654 int status;
655 /* CONSTCOND */
656 ASSERT(NO_COMPETING_THREADS);
657
658 NDBG0(("_init"));
659
660 status = ddi_soft_state_init(&mptsas_state, MPTSAS_SIZE,
661 MPTSAS_INITIAL_SOFT_SPACE);
662 if (status != 0) {
663 return (status);
664 }
665
666 if ((status = scsi_hba_init(&modlinkage)) != 0) {
667 ddi_soft_state_fini(&mptsas_state);
668 return (status);
669 }
670
671 mutex_init(&mptsas_global_mutex, NULL, MUTEX_DRIVER, NULL);
672 rw_init(&mptsas_global_rwlock, NULL, RW_DRIVER, NULL);
673 mutex_init(&mptsas_log_mutex, NULL, MUTEX_DRIVER, NULL);
674
675 if ((status = mod_install(&modlinkage)) != 0) {
676 mutex_destroy(&mptsas_log_mutex);
677 rw_destroy(&mptsas_global_rwlock);
678 mutex_destroy(&mptsas_global_mutex);
679 ddi_soft_state_fini(&mptsas_state);
680 scsi_hba_fini(&modlinkage);
681 }
682
683 return (status);
684 }
685
686 /*
687 * Notes:
688 * - scsi_hba_fini(9F) uninitializes SCSI HBA modules
689 */
690 int
691 _fini(void)
692 {
693 int status;
694 /* CONSTCOND */
695 ASSERT(NO_COMPETING_THREADS);
696
697 NDBG0(("_fini"));
698
699 if ((status = mod_remove(&modlinkage)) == 0) {
700 ddi_soft_state_fini(&mptsas_state);
701 scsi_hba_fini(&modlinkage);
702 mutex_destroy(&mptsas_global_mutex);
703 rw_destroy(&mptsas_global_rwlock);
704 mutex_destroy(&mptsas_log_mutex);
705 }
706 return (status);
707 }
708
709 /*
710 * The loadable-module _info(9E) entry point
711 */
712 int
713 _info(struct modinfo *modinfop)
714 {
715 /* CONSTCOND */
716 ASSERT(NO_COMPETING_THREADS);
717 NDBG0(("mptsas _info"));
718
719 return (mod_info(&modlinkage, modinfop));
720 }
721
722 static int
723 mptsas_target_eval_devhdl(const void *op, void *arg)
724 {
725 uint16_t dh = *(uint16_t *)arg;
726 const mptsas_target_t *tp = op;
727
728 return ((int)tp->m_devhdl - (int)dh);
729 }
730
731 static int
732 mptsas_target_eval_slot(const void *op, void *arg)
733 {
734 mptsas_led_control_t *lcp = arg;
735 const mptsas_target_t *tp = op;
736
737 if (tp->m_enclosure != lcp->Enclosure)
738 return ((int)tp->m_enclosure - (int)lcp->Enclosure);
739
740 return ((int)tp->m_slot_num - (int)lcp->Slot);
741 }
742
743 static int
744 mptsas_target_eval_nowwn(const void *op, void *arg)
745 {
746 uint8_t phy = *(uint8_t *)arg;
747 const mptsas_target_t *tp = op;
748
749 if (tp->m_addr.mta_wwn != 0)
750 return (-1);
751
752 return ((int)tp->m_phynum - (int)phy);
753 }
754
755 static int
756 mptsas_smp_eval_devhdl(const void *op, void *arg)
757 {
758 uint16_t dh = *(uint16_t *)arg;
759 const mptsas_smp_t *sp = op;
760
761 return ((int)sp->m_devhdl - (int)dh);
762 }
763
764 static uint64_t
765 mptsas_target_addr_hash(const void *tp)
766 {
767 const mptsas_target_addr_t *tap = tp;
768
769 return ((tap->mta_wwn & 0xffffffffffffULL) |
770 ((uint64_t)tap->mta_phymask << 48));
771 }
772
773 static int
774 mptsas_target_addr_cmp(const void *a, const void *b)
775 {
776 const mptsas_target_addr_t *aap = a;
777 const mptsas_target_addr_t *bap = b;
778
779 if (aap->mta_wwn < bap->mta_wwn)
780 return (-1);
781 if (aap->mta_wwn > bap->mta_wwn)
782 return (1);
783 return ((int)bap->mta_phymask - (int)aap->mta_phymask);
784 }
785
786 static uint64_t
787 mptsas_tmp_target_hash(const void *tp)
788 {
789 return ((uint64_t)(uintptr_t)tp);
790 }
791
792 static int
793 mptsas_tmp_target_cmp(const void *a, const void *b)
794 {
795 if (a > b)
796 return (1);
797 if (b < a)
798 return (-1);
799
800 return (0);
801 }
802
803 static void
804 mptsas_target_free(void *op)
805 {
806 kmem_free(op, sizeof (mptsas_target_t));
807 }
808
809 static void
810 mptsas_smp_free(void *op)
811 {
812 kmem_free(op, sizeof (mptsas_smp_t));
813 }
814
815 static void
816 mptsas_destroy_hashes(mptsas_t *mpt)
817 {
818 mptsas_target_t *tp;
819 mptsas_smp_t *sp;
820
821 for (tp = refhash_first(mpt->m_targets); tp != NULL;
822 tp = refhash_next(mpt->m_targets, tp)) {
823 refhash_remove(mpt->m_targets, tp);
824 }
825 for (sp = refhash_first(mpt->m_smp_targets); sp != NULL;
826 sp = refhash_next(mpt->m_smp_targets, sp)) {
827 refhash_remove(mpt->m_smp_targets, sp);
828 }
829 refhash_destroy(mpt->m_tmp_targets);
830 refhash_destroy(mpt->m_targets);
831 refhash_destroy(mpt->m_smp_targets);
832 mpt->m_targets = NULL;
833 mpt->m_smp_targets = NULL;
834 }
835
836 static int
837 mptsas_iport_attach(dev_info_t *dip, ddi_attach_cmd_t cmd)
838 {
839 dev_info_t *pdip;
840 mptsas_t *mpt;
841 scsi_hba_tran_t *hba_tran;
842 char *iport = NULL;
843 char phymask[MPTSAS_MAX_PHYS];
844 mptsas_phymask_t phy_mask = 0;
845 int dynamic_port = 0;
846 uint32_t page_address;
847 char initiator_wwnstr[MPTSAS_WWN_STRLEN];
848 int rval = DDI_FAILURE;
849 int i = 0;
850 uint8_t numphys = 0;
851 uint8_t phy_id;
852 uint8_t phy_port = 0;
853 uint16_t attached_devhdl = 0;
854 uint32_t dev_info;
855 uint64_t attached_sas_wwn;
856 uint16_t dev_hdl;
857 uint16_t pdev_hdl;
858 uint16_t bay_num, enclosure, io_flags;
859 char attached_wwnstr[MPTSAS_WWN_STRLEN];
860
861 /* CONSTCOND */
862 ASSERT(NO_COMPETING_THREADS);
863
864 switch (cmd) {
865 case DDI_ATTACH:
866 break;
867
868 case DDI_RESUME:
869 /*
870 * If this a scsi-iport node, nothing to do here.
871 */
872 return (DDI_SUCCESS);
873
874 default:
875 return (DDI_FAILURE);
876 }
877
878 pdip = ddi_get_parent(dip);
879
880 if ((hba_tran = ndi_flavorv_get(pdip, SCSA_FLAVOR_SCSI_DEVICE)) ==
881 NULL) {
882 cmn_err(CE_WARN, "Failed attach iport because fail to "
883 "get tran vector for the HBA node");
884 return (DDI_FAILURE);
885 }
886
887 mpt = TRAN2MPT(hba_tran);
888 ASSERT(mpt != NULL);
889 if (mpt == NULL)
890 return (DDI_FAILURE);
891
892 if ((hba_tran = ndi_flavorv_get(dip, SCSA_FLAVOR_SCSI_DEVICE)) ==
893 NULL) {
894 mptsas_log(mpt, CE_WARN, "Failed attach iport because fail to "
895 "get tran vector for the iport node");
896 return (DDI_FAILURE);
897 }
898
899 /*
900 * Overwrite parent's tran_hba_private to iport's tran vector
901 */
902 hba_tran->tran_hba_private = mpt;
903
904 ddi_report_dev(dip);
905
906 /*
907 * Get SAS address for initiator port according dev_handle
908 */
909 iport = ddi_get_name_addr(dip);
910 if (iport && strncmp(iport, "v0", 2) == 0) {
911 if (ddi_prop_update_int(DDI_DEV_T_NONE, dip,
912 MPTSAS_VIRTUAL_PORT, 1) !=
913 DDI_PROP_SUCCESS) {
914 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip,
915 MPTSAS_VIRTUAL_PORT);
916 mptsas_log(mpt, CE_WARN, "mptsas virtual port "
917 "prop update failed");
918 return (DDI_FAILURE);
919 }
920 return (DDI_SUCCESS);
921 }
922
923 mutex_enter(&mpt->m_mutex);
924 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
925 bzero(phymask, sizeof (phymask));
926 (void) sprintf(phymask,
927 "%x", mpt->m_phy_info[i].phy_mask);
928 if (strcmp(phymask, iport) == 0) {
929 break;
930 }
931 }
932
933 if (i == MPTSAS_MAX_PHYS) {
934 mptsas_log(mpt, CE_WARN, "Failed attach port %s because port"
935 "seems not exist", iport);
936 mutex_exit(&mpt->m_mutex);
937 return (DDI_FAILURE);
938 }
939
940 phy_mask = mpt->m_phy_info[i].phy_mask;
941
942 if (mpt->m_phy_info[i].port_flags & AUTO_PORT_CONFIGURATION)
943 dynamic_port = 1;
944 else
945 dynamic_port = 0;
946
947 /*
948 * Update PHY info for smhba
949 */
950 if (mptsas_smhba_phy_init(mpt)) {
951 mutex_exit(&mpt->m_mutex);
952 mptsas_log(mpt, CE_WARN, "mptsas phy update "
953 "failed");
954 return (DDI_FAILURE);
955 }
956
957 mutex_exit(&mpt->m_mutex);
958
959 numphys = 0;
960 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
961 if ((phy_mask >> i) & 0x01) {
962 numphys++;
963 }
964 }
965
966 bzero(initiator_wwnstr, sizeof (initiator_wwnstr));
967 (void) sprintf(initiator_wwnstr, "w%016"PRIx64,
968 mpt->un.m_base_wwid);
969
970 if (ddi_prop_update_string(DDI_DEV_T_NONE, dip,
971 SCSI_ADDR_PROP_INITIATOR_PORT, initiator_wwnstr) !=
972 DDI_PROP_SUCCESS) {
973 (void) ddi_prop_remove(DDI_DEV_T_NONE,
974 dip, SCSI_ADDR_PROP_INITIATOR_PORT);
975 mptsas_log(mpt, CE_WARN, "mptsas Initiator port "
976 "prop update failed");
977 return (DDI_FAILURE);
978 }
979 if (ddi_prop_update_int(DDI_DEV_T_NONE, dip,
980 MPTSAS_NUM_PHYS, numphys) !=
981 DDI_PROP_SUCCESS) {
982 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, MPTSAS_NUM_PHYS);
983 return (DDI_FAILURE);
984 }
985
986 if (ddi_prop_update_int(DDI_DEV_T_NONE, dip,
987 "phymask", phy_mask) !=
988 DDI_PROP_SUCCESS) {
989 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "phymask");
990 mptsas_log(mpt, CE_WARN, "mptsas phy mask "
991 "prop update failed");
992 return (DDI_FAILURE);
993 }
994
995 if (ddi_prop_update_int(DDI_DEV_T_NONE, dip,
996 "dynamic-port", dynamic_port) !=
997 DDI_PROP_SUCCESS) {
998 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "dynamic-port");
999 mptsas_log(mpt, CE_WARN, "mptsas dynamic port "
1000 "prop update failed");
1001 return (DDI_FAILURE);
1002 }
1003 if (ddi_prop_update_int(DDI_DEV_T_NONE, dip,
1004 MPTSAS_VIRTUAL_PORT, 0) !=
1005 DDI_PROP_SUCCESS) {
1006 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip,
1007 MPTSAS_VIRTUAL_PORT);
1008 mptsas_log(mpt, CE_WARN, "mptsas virtual port "
1009 "prop update failed");
1010 return (DDI_FAILURE);
1011 }
1012 mptsas_smhba_set_all_phy_props(mpt, dip, numphys, phy_mask,
1013 &attached_devhdl);
1014
1015 mutex_enter(&mpt->m_mutex);
1016 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE &
1017 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | (uint32_t)attached_devhdl;
1018 rval = mptsas_get_sas_device_page0(mpt, page_address, &dev_hdl,
1019 &attached_sas_wwn, &dev_info, &phy_port, &phy_id,
1020 &pdev_hdl, &bay_num, &enclosure, &io_flags);
1021 if (rval != DDI_SUCCESS) {
1022 mptsas_log(mpt, CE_WARN,
1023 "Failed to get device page0 for handle:%d",
1024 attached_devhdl);
1025 mutex_exit(&mpt->m_mutex);
1026 return (DDI_FAILURE);
1027 }
1028
1029 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
1030 bzero(phymask, sizeof (phymask));
1031 (void) sprintf(phymask, "%x", mpt->m_phy_info[i].phy_mask);
1032 if (strcmp(phymask, iport) == 0) {
1033 (void) sprintf(&mpt->m_phy_info[i].smhba_info.path[0],
1034 "%x",
1035 mpt->m_phy_info[i].phy_mask);
1036 }
1037 }
1038 mutex_exit(&mpt->m_mutex);
1039
1040 bzero(attached_wwnstr, sizeof (attached_wwnstr));
1041 (void) sprintf(attached_wwnstr, "w%016"PRIx64,
1042 attached_sas_wwn);
1043 if (ddi_prop_update_string(DDI_DEV_T_NONE, dip,
1044 SCSI_ADDR_PROP_ATTACHED_PORT, attached_wwnstr) !=
1045 DDI_PROP_SUCCESS) {
1046 (void) ddi_prop_remove(DDI_DEV_T_NONE,
1047 dip, SCSI_ADDR_PROP_ATTACHED_PORT);
1048 return (DDI_FAILURE);
1049 }
1050
1051 /* Create kstats for each phy on this iport */
1052
1053 mptsas_create_phy_stats(mpt, iport, dip);
1054
1055 /*
1056 * register sas hba iport with mdi (MPxIO/vhci)
1057 */
1058 if (mdi_phci_register(MDI_HCI_CLASS_SCSI,
1059 dip, 0) == MDI_SUCCESS) {
1060 mpt->m_mpxio_enable = TRUE;
1061 }
1062 return (DDI_SUCCESS);
1063 }
1064
1065 /*
1066 * Notes:
1067 * Set up all device state and allocate data structures,
1068 * mutexes, condition variables, etc. for device operation.
1069 * Add interrupts needed.
1070 * Return DDI_SUCCESS if device is ready, else return DDI_FAILURE.
1071 */
1072 static int
1073 mptsas_attach(dev_info_t *dip, ddi_attach_cmd_t cmd)
1074 {
1075 mptsas_t *mpt = NULL;
1076 int instance, i, j;
1077 int doneq_thread_num;
1078 char intr_added = 0;
1079 char map_setup = 0;
1080 char config_setup = 0;
1081 char hba_attach_setup = 0;
1082 char smp_attach_setup = 0;
1083 char mutex_init_done = 0;
1084 char event_taskq_create = 0;
1085 char dr_taskq_create = 0;
1086 char doneq_thread_create = 0;
1087 char added_watchdog = 0;
1088 scsi_hba_tran_t *hba_tran;
1089 uint_t mem_bar = MEM_SPACE;
1090 int rval = DDI_FAILURE;
1091
1092 /* CONSTCOND */
1093 ASSERT(NO_COMPETING_THREADS);
1094
1095 if (scsi_hba_iport_unit_address(dip)) {
1096 return (mptsas_iport_attach(dip, cmd));
1097 }
1098
1099 switch (cmd) {
1100 case DDI_ATTACH:
1101 break;
1102
1103 case DDI_RESUME:
1104 if ((hba_tran = ddi_get_driver_private(dip)) == NULL)
1105 return (DDI_FAILURE);
1106
1107 mpt = TRAN2MPT(hba_tran);
1108
1109 if (!mpt) {
1110 return (DDI_FAILURE);
1111 }
1112
1113 /*
1114 * Reset hardware and softc to "no outstanding commands"
1115 * Note that a check condition can result on first command
1116 * to a target.
1117 */
1118 mutex_enter(&mpt->m_mutex);
1119
1120 /*
1121 * raise power.
1122 */
1123 if (mpt->m_options & MPTSAS_OPT_PM) {
1124 mutex_exit(&mpt->m_mutex);
1125 (void) pm_busy_component(dip, 0);
1126 rval = pm_power_has_changed(dip, 0, PM_LEVEL_D0);
1127 if (rval == DDI_SUCCESS) {
1128 mutex_enter(&mpt->m_mutex);
1129 } else {
1130 /*
1131 * The pm_raise_power() call above failed,
1132 * and that can only occur if we were unable
1133 * to reset the hardware. This is probably
1134 * due to unhealty hardware, and because
1135 * important filesystems(such as the root
1136 * filesystem) could be on the attached disks,
1137 * it would not be a good idea to continue,
1138 * as we won't be entirely certain we are
1139 * writing correct data. So we panic() here
1140 * to not only prevent possible data corruption,
1141 * but to give developers or end users a hope
1142 * of identifying and correcting any problems.
1143 */
1144 fm_panic("mptsas could not reset hardware "
1145 "during resume");
1146 }
1147 }
1148
1149 mpt->m_suspended = 0;
1150
1151 /*
1152 * Reinitialize ioc
1153 */
1154 mpt->m_softstate |= MPTSAS_SS_MSG_UNIT_RESET;
1155 if (mptsas_init_chip(mpt, FALSE) == DDI_FAILURE) {
1156 mutex_exit(&mpt->m_mutex);
1157 if (mpt->m_options & MPTSAS_OPT_PM) {
1158 (void) pm_idle_component(dip, 0);
1159 }
1160 fm_panic("mptsas init chip fail during resume");
1161 }
1162 /*
1163 * mptsas_update_driver_data needs interrupts so enable them
1164 * first.
1165 */
1166 MPTSAS_ENABLE_INTR(mpt);
1167 mptsas_update_driver_data(mpt);
1168
1169 /* start requests, if possible */
1170 mptsas_restart_hba(mpt);
1171
1172 mutex_exit(&mpt->m_mutex);
1173
1174 /*
1175 * Restart watch thread
1176 */
1177 mutex_enter(&mptsas_global_mutex);
1178 if (mptsas_timeout_id == 0) {
1179 mptsas_timeout_id = timeout(mptsas_watch, NULL,
1180 mptsas_tick);
1181 mptsas_timeouts_enabled = 1;
1182 }
1183 mutex_exit(&mptsas_global_mutex);
1184
1185 /* report idle status to pm framework */
1186 if (mpt->m_options & MPTSAS_OPT_PM) {
1187 (void) pm_idle_component(dip, 0);
1188 }
1189
1190 return (DDI_SUCCESS);
1191
1192 default:
1193 return (DDI_FAILURE);
1194
1195 }
1196
1197 instance = ddi_get_instance(dip);
1198
1199 /*
1200 * Allocate softc information.
1201 */
1202 if (ddi_soft_state_zalloc(mptsas_state, instance) != DDI_SUCCESS) {
1203 mptsas_log(NULL, CE_WARN,
1204 "mptsas%d: cannot allocate soft state", instance);
1205 goto fail;
1206 }
1207
1208 mpt = ddi_get_soft_state(mptsas_state, instance);
1209
1210 if (mpt == NULL) {
1211 mptsas_log(NULL, CE_WARN,
1212 "mptsas%d: cannot get soft state", instance);
1213 goto fail;
1214 }
1215
1216 /* Indicate that we are 'sizeof (scsi_*(9S))' clean. */
1217 scsi_size_clean(dip);
1218
1219 mpt->m_dip = dip;
1220 mpt->m_instance = instance;
1221
1222 /* Make a per-instance copy of the structures */
1223 mpt->m_io_dma_attr = mptsas_dma_attrs64;
1224 if (mptsas_use_64bit_msgaddr) {
1225 mpt->m_msg_dma_attr = mptsas_dma_attrs64;
1226 } else {
1227 mpt->m_msg_dma_attr = mptsas_dma_attrs;
1228 }
1229 mpt->m_reg_acc_attr = mptsas_dev_attr;
1230 mpt->m_dev_acc_attr = mptsas_dev_attr;
1231
1232 /*
1233 * Size of individual request sense buffer
1234 */
1235 mpt->m_req_sense_size = EXTCMDS_STATUS_SIZE;
1236
1237 /*
1238 * Initialize FMA
1239 */
1240 mpt->m_fm_capabilities = ddi_getprop(DDI_DEV_T_ANY, mpt->m_dip,
1241 DDI_PROP_CANSLEEP | DDI_PROP_DONTPASS, "fm-capable",
1242 DDI_FM_EREPORT_CAPABLE | DDI_FM_ACCCHK_CAPABLE |
1243 DDI_FM_DMACHK_CAPABLE | DDI_FM_ERRCB_CAPABLE);
1244
1245 mptsas_fm_init(mpt);
1246
1247 if (mptsas_alloc_handshake_msg(mpt,
1248 sizeof (Mpi2SCSITaskManagementRequest_t)) == DDI_FAILURE) {
1249 mptsas_log(mpt, CE_WARN, "cannot initialize handshake msg.");
1250 goto fail;
1251 }
1252
1253 /*
1254 * Setup configuration space
1255 */
1256 if (mptsas_config_space_init(mpt) == FALSE) {
1257 mptsas_log(mpt, CE_WARN, "mptsas_config_space_init failed");
1258 goto fail;
1259 }
1260 config_setup++;
1261
1262 if (ddi_regs_map_setup(dip, mem_bar, (caddr_t *)&mpt->m_reg,
1263 0, 0, &mpt->m_reg_acc_attr, &mpt->m_datap) != DDI_SUCCESS) {
1264 mptsas_log(mpt, CE_WARN, "map setup failed");
1265 goto fail;
1266 }
1267 map_setup++;
1268
1269 /*
1270 * A taskq is created for dealing with the event handler
1271 */
1272 if ((mpt->m_event_taskq = ddi_taskq_create(dip, "mptsas_event_taskq",
1273 1, TASKQ_DEFAULTPRI, 0)) == NULL) {
1274 mptsas_log(mpt, CE_NOTE, "ddi_taskq_create failed");
1275 goto fail;
1276 }
1277 event_taskq_create++;
1278
1279 /*
1280 * A taskq is created for dealing with dr events
1281 */
1282 if ((mpt->m_dr_taskq = ddi_taskq_create(dip,
1283 "mptsas_dr_taskq",
1284 1, TASKQ_DEFAULTPRI, 0)) == NULL) {
1285 mptsas_log(mpt, CE_NOTE, "ddi_taskq_create for discovery "
1286 "failed");
1287 goto fail;
1288 }
1289 dr_taskq_create++;
1290
1291 mpt->m_doneq_thread_threshold = ddi_prop_get_int(DDI_DEV_T_ANY, dip,
1292 0, "mptsas_doneq_thread_threshold_prop", 10);
1293 mpt->m_doneq_length_threshold = ddi_prop_get_int(DDI_DEV_T_ANY, dip,
1294 0, "mptsas_doneq_length_threshold_prop", 8);
1295 mpt->m_doneq_thread_n = ddi_prop_get_int(DDI_DEV_T_ANY, dip,
1296 0, "mptsas_doneq_thread_n_prop", 8);
1297
1298 if (mpt->m_doneq_thread_n) {
1299 cv_init(&mpt->m_doneq_thread_cv, NULL, CV_DRIVER, NULL);
1300 mutex_init(&mpt->m_doneq_mutex, NULL, MUTEX_DRIVER, NULL);
1301
1302 mutex_enter(&mpt->m_doneq_mutex);
1303 mpt->m_doneq_thread_id =
1304 kmem_zalloc(sizeof (mptsas_doneq_thread_list_t)
1305 * mpt->m_doneq_thread_n, KM_SLEEP);
1306
1307 for (j = 0; j < mpt->m_doneq_thread_n; j++) {
1308 cv_init(&mpt->m_doneq_thread_id[j].cv, NULL,
1309 CV_DRIVER, NULL);
1310 mutex_init(&mpt->m_doneq_thread_id[j].mutex, NULL,
1311 MUTEX_DRIVER, NULL);
1312 mutex_enter(&mpt->m_doneq_thread_id[j].mutex);
1313 mpt->m_doneq_thread_id[j].flag |=
1314 MPTSAS_DONEQ_THREAD_ACTIVE;
1315 mpt->m_doneq_thread_id[j].arg.mpt = mpt;
1316 mpt->m_doneq_thread_id[j].arg.t = j;
1317 mpt->m_doneq_thread_id[j].threadp =
1318 thread_create(NULL, 0, mptsas_doneq_thread,
1319 &mpt->m_doneq_thread_id[j].arg,
1320 0, &p0, TS_RUN, minclsyspri);
1321 mpt->m_doneq_thread_id[j].donetail =
1322 &mpt->m_doneq_thread_id[j].doneq;
1323 mutex_exit(&mpt->m_doneq_thread_id[j].mutex);
1324 }
1325 mutex_exit(&mpt->m_doneq_mutex);
1326 doneq_thread_create++;
1327 }
1328
1329 /*
1330 * Disable hardware interrupt since we're not ready to
1331 * handle it yet.
1332 */
1333 MPTSAS_DISABLE_INTR(mpt);
1334 if (mptsas_register_intrs(mpt) == FALSE)
1335 goto fail;
1336 intr_added++;
1337
1338 /*
1339 * The mutex to protect task management during reset
1340 */
1341 mutex_init(&mpt->m_taskmgmt_mutex, NULL, MUTEX_SPIN,
1342 DDI_INTR_PRI(mpt->m_intr_pri));
1343
1344 /* Initialize mutex used in interrupt handler */
1345 mutex_init(&mpt->m_mutex, NULL, MUTEX_DRIVER,
1346 DDI_INTR_PRI(mpt->m_intr_pri));
1347 mutex_init(&mpt->m_passthru_mutex, NULL, MUTEX_DRIVER, NULL);
1348 mutex_init(&mpt->m_tx_waitq_mutex, NULL, MUTEX_DRIVER,
1349 DDI_INTR_PRI(mpt->m_intr_pri));
1350 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
1351 mutex_init(&mpt->m_phy_info[i].smhba_info.phy_mutex,
1352 NULL, MUTEX_DRIVER,
1353 DDI_INTR_PRI(mpt->m_intr_pri));
1354 }
1355
1356 cv_init(&mpt->m_cv, NULL, CV_DRIVER, NULL);
1357 cv_init(&mpt->m_passthru_cv, NULL, CV_DRIVER, NULL);
1358 cv_init(&mpt->m_fw_cv, NULL, CV_DRIVER, NULL);
1359 cv_init(&mpt->m_config_cv, NULL, CV_DRIVER, NULL);
1360 cv_init(&mpt->m_fw_diag_cv, NULL, CV_DRIVER, NULL);
1361 cv_init(&mpt->m_extreq_sense_refcount_cv, NULL, CV_DRIVER, NULL);
1362 mutex_init_done++;
1363
1364 mutex_enter(&mpt->m_mutex);
1365 /*
1366 * Initialize power management component
1367 */
1368 if (mpt->m_options & MPTSAS_OPT_PM) {
1369 if (mptsas_init_pm(mpt)) {
1370 mutex_exit(&mpt->m_mutex);
1371 mptsas_log(mpt, CE_WARN, "mptsas pm initialization "
1372 "failed");
1373 goto fail;
1374 }
1375 }
1376
1377 /*
1378 * Initialize chip using Message Unit Reset, if allowed
1379 */
1380 mpt->m_softstate |= MPTSAS_SS_MSG_UNIT_RESET;
1381 if (mptsas_init_chip(mpt, TRUE) == DDI_FAILURE) {
1382 mutex_exit(&mpt->m_mutex);
1383 mptsas_log(mpt, CE_WARN, "mptsas chip initialization failed");
1384 goto fail;
1385 }
1386
1387 mpt->m_targets = refhash_create(MPTSAS_TARGET_BUCKET_COUNT,
1388 mptsas_target_addr_hash, mptsas_target_addr_cmp,
1389 mptsas_target_free, sizeof (mptsas_target_t),
1390 offsetof(mptsas_target_t, m_link),
1391 offsetof(mptsas_target_t, m_addr), KM_SLEEP);
1392
1393 /*
1394 * The refhash for temporary targets uses the address of the target
1395 * struct itself as tag, so the tag offset is 0. See the implementation
1396 * of mptsas_tmp_target_hash() and mptsas_tmp_target_cmp().
1397 */
1398 mpt->m_tmp_targets = refhash_create(MPTSAS_TMP_TARGET_BUCKET_COUNT,
1399 mptsas_tmp_target_hash, mptsas_tmp_target_cmp,
1400 mptsas_target_free, sizeof (mptsas_target_t),
1401 offsetof(mptsas_target_t, m_link), 0, KM_SLEEP);
1402
1403 /*
1404 * Fill in the phy_info structure and get the base WWID
1405 */
1406 if (mptsas_get_manufacture_page5(mpt) == DDI_FAILURE) {
1407 mptsas_log(mpt, CE_WARN,
1408 "mptsas_get_manufacture_page5 failed!");
1409 goto fail;
1410 }
1411
1412 if (mptsas_get_sas_io_unit_page_hndshk(mpt)) {
1413 mptsas_log(mpt, CE_WARN,
1414 "mptsas_get_sas_io_unit_page_hndshk failed!");
1415 goto fail;
1416 }
1417
1418 if (mptsas_get_manufacture_page0(mpt) == DDI_FAILURE) {
1419 mptsas_log(mpt, CE_WARN,
1420 "mptsas_get_manufacture_page0 failed!");
1421 goto fail;
1422 }
1423
1424 mutex_exit(&mpt->m_mutex);
1425
1426 /*
1427 * Register the iport for multiple port HBA
1428 */
1429 mptsas_iport_register(mpt);
1430
1431 /*
1432 * initialize SCSI HBA transport structure
1433 */
1434 if (mptsas_hba_setup(mpt) == FALSE)
1435 goto fail;
1436 hba_attach_setup++;
1437
1438 if (mptsas_smp_setup(mpt) == FALSE)
1439 goto fail;
1440 smp_attach_setup++;
1441
1442 if (mptsas_cache_create(mpt) == FALSE)
1443 goto fail;
1444
1445 mpt->m_scsi_reset_delay = ddi_prop_get_int(DDI_DEV_T_ANY,
1446 dip, 0, "scsi-reset-delay", SCSI_DEFAULT_RESET_DELAY);
1447 if (mpt->m_scsi_reset_delay == 0) {
1448 mptsas_log(mpt, CE_NOTE,
1449 "scsi_reset_delay of 0 is not recommended,"
1450 " resetting to SCSI_DEFAULT_RESET_DELAY\n");
1451 mpt->m_scsi_reset_delay = SCSI_DEFAULT_RESET_DELAY;
1452 }
1453
1454 /*
1455 * Initialize the wait and done FIFO queue
1456 */
1457 mpt->m_donetail = &mpt->m_doneq;
1458 mpt->m_waitqtail = &mpt->m_waitq;
1459 mpt->m_tx_waitqtail = &mpt->m_tx_waitq;
1460 mpt->m_tx_draining = 0;
1461
1462 /*
1463 * ioc cmd queue initialize
1464 */
1465 mpt->m_ioc_event_cmdtail = &mpt->m_ioc_event_cmdq;
1466 mpt->m_dev_handle = 0xFFFF;
1467
1468 MPTSAS_ENABLE_INTR(mpt);
1469
1470 /*
1471 * enable event notification
1472 */
1473 mutex_enter(&mpt->m_mutex);
1474 if (mptsas_ioc_enable_event_notification(mpt)) {
1475 mutex_exit(&mpt->m_mutex);
1476 goto fail;
1477 }
1478 mutex_exit(&mpt->m_mutex);
1479
1480 /*
1481 * used for mptsas_watch
1482 */
1483 mptsas_list_add(mpt);
1484
1485 mutex_enter(&mptsas_global_mutex);
1486 if (mptsas_timeouts_enabled == 0) {
1487 mptsas_scsi_watchdog_tick = ddi_prop_get_int(DDI_DEV_T_ANY,
1488 dip, 0, "scsi-watchdog-tick", DEFAULT_WD_TICK);
1489
1490 mptsas_tick = mptsas_scsi_watchdog_tick *
1491 drv_usectohz((clock_t)1000000);
1492
1493 mptsas_timeout_id = timeout(mptsas_watch, NULL, mptsas_tick);
1494 mptsas_timeouts_enabled = 1;
1495 }
1496 mutex_exit(&mptsas_global_mutex);
1497 added_watchdog++;
1498
1499 /*
1500 * Initialize PHY info for smhba.
1501 * This requires watchdog to be enabled otherwise if interrupts
1502 * don't work the system will hang.
1503 */
1504 if (mptsas_smhba_setup(mpt)) {
1505 mptsas_log(mpt, CE_WARN, "mptsas phy initialization "
1506 "failed");
1507 goto fail;
1508 }
1509
1510 /* Check all dma handles allocated in attach */
1511 if ((mptsas_check_dma_handle(mpt->m_dma_req_frame_hdl)
1512 != DDI_SUCCESS) ||
1513 (mptsas_check_dma_handle(mpt->m_dma_req_sense_hdl)
1514 != DDI_SUCCESS) ||
1515 (mptsas_check_dma_handle(mpt->m_dma_reply_frame_hdl)
1516 != DDI_SUCCESS) ||
1517 (mptsas_check_dma_handle(mpt->m_dma_free_queue_hdl)
1518 != DDI_SUCCESS) ||
1519 (mptsas_check_dma_handle(mpt->m_dma_post_queue_hdl)
1520 != DDI_SUCCESS) ||
1521 (mptsas_check_dma_handle(mpt->m_hshk_dma_hdl)
1522 != DDI_SUCCESS)) {
1523 goto fail;
1524 }
1525
1526 /* Check all acc handles allocated in attach */
1527 if ((mptsas_check_acc_handle(mpt->m_datap) != DDI_SUCCESS) ||
1528 (mptsas_check_acc_handle(mpt->m_acc_req_frame_hdl)
1529 != DDI_SUCCESS) ||
1530 (mptsas_check_acc_handle(mpt->m_acc_req_sense_hdl)
1531 != DDI_SUCCESS) ||
1532 (mptsas_check_acc_handle(mpt->m_acc_reply_frame_hdl)
1533 != DDI_SUCCESS) ||
1534 (mptsas_check_acc_handle(mpt->m_acc_free_queue_hdl)
1535 != DDI_SUCCESS) ||
1536 (mptsas_check_acc_handle(mpt->m_acc_post_queue_hdl)
1537 != DDI_SUCCESS) ||
1538 (mptsas_check_acc_handle(mpt->m_hshk_acc_hdl)
1539 != DDI_SUCCESS) ||
1540 (mptsas_check_acc_handle(mpt->m_config_handle)
1541 != DDI_SUCCESS)) {
1542 goto fail;
1543 }
1544
1545 /*
1546 * After this point, we are not going to fail the attach.
1547 */
1548
1549 /* Print message of HBA present */
1550 ddi_report_dev(dip);
1551
1552 /* report idle status to pm framework */
1553 if (mpt->m_options & MPTSAS_OPT_PM) {
1554 (void) pm_idle_component(dip, 0);
1555 }
1556
1557 return (DDI_SUCCESS);
1558
1559 fail:
1560 mptsas_log(mpt, CE_WARN, "attach failed");
1561 mptsas_fm_ereport(mpt, DDI_FM_DEVICE_NO_RESPONSE);
1562 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_LOST);
1563 if (mpt) {
1564 /* deallocate in reverse order */
1565 if (added_watchdog) {
1566 mptsas_list_del(mpt);
1567 mutex_enter(&mptsas_global_mutex);
1568
1569 if (mptsas_timeout_id && (mptsas_head == NULL)) {
1570 timeout_id_t tid = mptsas_timeout_id;
1571 mptsas_timeouts_enabled = 0;
1572 mptsas_timeout_id = 0;
1573 mutex_exit(&mptsas_global_mutex);
1574 (void) untimeout(tid);
1575 mutex_enter(&mptsas_global_mutex);
1576 }
1577 mutex_exit(&mptsas_global_mutex);
1578 }
1579
1580 mptsas_cache_destroy(mpt);
1581
1582 if (smp_attach_setup) {
1583 mptsas_smp_teardown(mpt);
1584 }
1585 if (hba_attach_setup) {
1586 mptsas_hba_teardown(mpt);
1587 }
1588
1589 if (mpt->m_tmp_targets)
1590 refhash_destroy(mpt->m_tmp_targets);
1591 if (mpt->m_targets)
1592 refhash_destroy(mpt->m_targets);
1593 if (mpt->m_smp_targets)
1594 refhash_destroy(mpt->m_smp_targets);
1595
1596 if (mpt->m_active) {
1597 mptsas_free_active_slots(mpt);
1598 }
1599 if (intr_added) {
1600 mptsas_unregister_intrs(mpt);
1601 }
1602
1603 if (doneq_thread_create) {
1604 mutex_enter(&mpt->m_doneq_mutex);
1605 doneq_thread_num = mpt->m_doneq_thread_n;
1606 for (j = 0; j < mpt->m_doneq_thread_n; j++) {
1607 mutex_enter(&mpt->m_doneq_thread_id[j].mutex);
1608 mpt->m_doneq_thread_id[j].flag &=
1609 (~MPTSAS_DONEQ_THREAD_ACTIVE);
1610 cv_signal(&mpt->m_doneq_thread_id[j].cv);
1611 mutex_exit(&mpt->m_doneq_thread_id[j].mutex);
1612 }
1613 while (mpt->m_doneq_thread_n) {
1614 cv_wait(&mpt->m_doneq_thread_cv,
1615 &mpt->m_doneq_mutex);
1616 }
1617 for (j = 0; j < doneq_thread_num; j++) {
1618 cv_destroy(&mpt->m_doneq_thread_id[j].cv);
1619 mutex_destroy(&mpt->m_doneq_thread_id[j].mutex);
1620 }
1621 kmem_free(mpt->m_doneq_thread_id,
1622 sizeof (mptsas_doneq_thread_list_t)
1623 * doneq_thread_num);
1624 mutex_exit(&mpt->m_doneq_mutex);
1625 cv_destroy(&mpt->m_doneq_thread_cv);
1626 mutex_destroy(&mpt->m_doneq_mutex);
1627 }
1628 if (event_taskq_create) {
1629 ddi_taskq_destroy(mpt->m_event_taskq);
1630 }
1631 if (dr_taskq_create) {
1632 ddi_taskq_destroy(mpt->m_dr_taskq);
1633 }
1634 if (mutex_init_done) {
1635 mutex_destroy(&mpt->m_tx_waitq_mutex);
1636 mutex_destroy(&mpt->m_passthru_mutex);
1637 mutex_destroy(&mpt->m_mutex);
1638 mutex_destroy(&mpt->m_taskmgmt_mutex);
1639 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
1640 mutex_destroy(
1641 &mpt->m_phy_info[i].smhba_info.phy_mutex);
1642 }
1643 cv_destroy(&mpt->m_cv);
1644 cv_destroy(&mpt->m_passthru_cv);
1645 cv_destroy(&mpt->m_fw_cv);
1646 cv_destroy(&mpt->m_config_cv);
1647 cv_destroy(&mpt->m_fw_diag_cv);
1648 cv_destroy(&mpt->m_extreq_sense_refcount_cv);
1649 }
1650
1651 if (map_setup) {
1652 mptsas_cfg_fini(mpt);
1653 }
1654 if (config_setup) {
1655 mptsas_config_space_fini(mpt);
1656 }
1657 mptsas_free_handshake_msg(mpt);
1658 mptsas_hba_fini(mpt);
1659
1660 mptsas_fm_fini(mpt);
1661 ddi_soft_state_free(mptsas_state, instance);
1662 ddi_prop_remove_all(dip);
1663 }
1664 return (DDI_FAILURE);
1665 }
1666
1667 static int
1668 mptsas_suspend(dev_info_t *devi)
1669 {
1670 mptsas_t *mpt, *g;
1671 scsi_hba_tran_t *tran;
1672
1673 if (scsi_hba_iport_unit_address(devi)) {
1674 return (DDI_SUCCESS);
1675 }
1676
1677 if ((tran = ddi_get_driver_private(devi)) == NULL)
1678 return (DDI_SUCCESS);
1679
1680 mpt = TRAN2MPT(tran);
1681 if (!mpt) {
1682 return (DDI_SUCCESS);
1683 }
1684
1685 mutex_enter(&mpt->m_mutex);
1686
1687 if (mpt->m_suspended++) {
1688 mutex_exit(&mpt->m_mutex);
1689 return (DDI_SUCCESS);
1690 }
1691
1692 /*
1693 * Cancel timeout threads for this mpt
1694 */
1695 if (mpt->m_quiesce_timeid) {
1696 timeout_id_t tid = mpt->m_quiesce_timeid;
1697 mpt->m_quiesce_timeid = 0;
1698 mutex_exit(&mpt->m_mutex);
1699 (void) untimeout(tid);
1700 mutex_enter(&mpt->m_mutex);
1701 }
1702
1703 if (mpt->m_restart_cmd_timeid) {
1704 timeout_id_t tid = mpt->m_restart_cmd_timeid;
1705 mpt->m_restart_cmd_timeid = 0;
1706 mutex_exit(&mpt->m_mutex);
1707 (void) untimeout(tid);
1708 mutex_enter(&mpt->m_mutex);
1709 }
1710
1711 mutex_exit(&mpt->m_mutex);
1712
1713 (void) pm_idle_component(mpt->m_dip, 0);
1714
1715 /*
1716 * Cancel watch threads if all mpts suspended
1717 */
1718 rw_enter(&mptsas_global_rwlock, RW_WRITER);
1719 for (g = mptsas_head; g != NULL; g = g->m_next) {
1720 if (!g->m_suspended)
1721 break;
1722 }
1723 rw_exit(&mptsas_global_rwlock);
1724
1725 mutex_enter(&mptsas_global_mutex);
1726 if (g == NULL) {
1727 timeout_id_t tid;
1728
1729 mptsas_timeouts_enabled = 0;
1730 if (mptsas_timeout_id) {
1731 tid = mptsas_timeout_id;
1732 mptsas_timeout_id = 0;
1733 mutex_exit(&mptsas_global_mutex);
1734 (void) untimeout(tid);
1735 mutex_enter(&mptsas_global_mutex);
1736 }
1737 if (mptsas_reset_watch) {
1738 tid = mptsas_reset_watch;
1739 mptsas_reset_watch = 0;
1740 mutex_exit(&mptsas_global_mutex);
1741 (void) untimeout(tid);
1742 mutex_enter(&mptsas_global_mutex);
1743 }
1744 }
1745 mutex_exit(&mptsas_global_mutex);
1746
1747 mutex_enter(&mpt->m_mutex);
1748
1749 /*
1750 * If this mpt is not in full power(PM_LEVEL_D0), just return.
1751 */
1752 if ((mpt->m_options & MPTSAS_OPT_PM) &&
1753 (mpt->m_power_level != PM_LEVEL_D0)) {
1754 mutex_exit(&mpt->m_mutex);
1755 return (DDI_SUCCESS);
1756 }
1757
1758 /* Disable HBA interrupts in hardware */
1759 MPTSAS_DISABLE_INTR(mpt);
1760 /*
1761 * Send RAID action system shutdown to sync IR
1762 */
1763 mptsas_raid_action_system_shutdown(mpt);
1764
1765 mutex_exit(&mpt->m_mutex);
1766
1767 /* drain the taskq */
1768 ddi_taskq_wait(mpt->m_event_taskq);
1769 ddi_taskq_wait(mpt->m_dr_taskq);
1770
1771 return (DDI_SUCCESS);
1772 }
1773
1774 #ifdef __sparc
1775 /*ARGSUSED*/
1776 static int
1777 mptsas_reset(dev_info_t *devi, ddi_reset_cmd_t cmd)
1778 {
1779 mptsas_t *mpt;
1780 scsi_hba_tran_t *tran;
1781
1782 /*
1783 * If this call is for iport, just return.
1784 */
1785 if (scsi_hba_iport_unit_address(devi))
1786 return (DDI_SUCCESS);
1787
1788 if ((tran = ddi_get_driver_private(devi)) == NULL)
1789 return (DDI_SUCCESS);
1790
1791 if ((mpt = TRAN2MPT(tran)) == NULL)
1792 return (DDI_SUCCESS);
1793
1794 /*
1795 * Send RAID action system shutdown to sync IR. Disable HBA
1796 * interrupts in hardware first.
1797 */
1798 MPTSAS_DISABLE_INTR(mpt);
1799 mptsas_raid_action_system_shutdown(mpt);
1800
1801 return (DDI_SUCCESS);
1802 }
1803 #else /* __sparc */
1804 /*
1805 * quiesce(9E) entry point.
1806 *
1807 * This function is called when the system is single-threaded at high
1808 * PIL with preemption disabled. Therefore, this function must not be
1809 * blocked.
1810 *
1811 * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure.
1812 * DDI_FAILURE indicates an error condition and should almost never happen.
1813 */
1814 static int
1815 mptsas_quiesce(dev_info_t *devi)
1816 {
1817 mptsas_t *mpt;
1818 scsi_hba_tran_t *tran;
1819
1820 /*
1821 * If this call is for iport, just return.
1822 */
1823 if (scsi_hba_iport_unit_address(devi))
1824 return (DDI_SUCCESS);
1825
1826 if ((tran = ddi_get_driver_private(devi)) == NULL)
1827 return (DDI_SUCCESS);
1828
1829 if ((mpt = TRAN2MPT(tran)) == NULL)
1830 return (DDI_SUCCESS);
1831
1832 /* Disable HBA interrupts in hardware */
1833 MPTSAS_DISABLE_INTR(mpt);
1834 /* Send RAID action system shutdonw to sync IR */
1835 mptsas_raid_action_system_shutdown(mpt);
1836
1837 return (DDI_SUCCESS);
1838 }
1839 #endif /* __sparc */
1840
1841 /*
1842 * detach(9E). Remove all device allocations and system resources;
1843 * disable device interrupts.
1844 * Return DDI_SUCCESS if done; DDI_FAILURE if there's a problem.
1845 */
1846 static int
1847 mptsas_detach(dev_info_t *devi, ddi_detach_cmd_t cmd)
1848 {
1849 /* CONSTCOND */
1850 ASSERT(NO_COMPETING_THREADS);
1851 NDBG0(("mptsas_detach: dip=0x%p cmd=0x%p", (void *)devi, (void *)cmd));
1852
1853 switch (cmd) {
1854 case DDI_DETACH:
1855 return (mptsas_do_detach(devi));
1856
1857 case DDI_SUSPEND:
1858 return (mptsas_suspend(devi));
1859
1860 default:
1861 return (DDI_FAILURE);
1862 }
1863 /* NOTREACHED */
1864 }
1865
1866 static int
1867 mptsas_do_detach(dev_info_t *dip)
1868 {
1869 mptsas_t *mpt;
1870 scsi_hba_tran_t *tran;
1871 int circ = 0;
1872 int circ1 = 0;
1873 mdi_pathinfo_t *pip = NULL;
1874 int i;
1875 int doneq_thread_num = 0;
1876
1877 NDBG0(("mptsas_do_detach: dip=0x%p", (void *)dip));
1878
1879 if ((tran = ndi_flavorv_get(dip, SCSA_FLAVOR_SCSI_DEVICE)) == NULL)
1880 return (DDI_FAILURE);
1881
1882 mpt = TRAN2MPT(tran);
1883 if (!mpt) {
1884 return (DDI_FAILURE);
1885 }
1886 /*
1887 * Still have pathinfo child, should not detach mpt driver
1888 */
1889 if (scsi_hba_iport_unit_address(dip)) {
1890 if (mpt->m_mpxio_enable) {
1891 /*
1892 * MPxIO enabled for the iport
1893 */
1894 ndi_devi_enter(scsi_vhci_dip, &circ1);
1895 ndi_devi_enter(dip, &circ);
1896 while (pip = mdi_get_next_client_path(dip, NULL)) {
1897 if (mdi_pi_free(pip, 0) == MDI_SUCCESS) {
1898 continue;
1899 }
1900 ndi_devi_exit(dip, circ);
1901 ndi_devi_exit(scsi_vhci_dip, circ1);
1902 NDBG12(("detach failed because of "
1903 "outstanding path info"));
1904 return (DDI_FAILURE);
1905 }
1906 ndi_devi_exit(dip, circ);
1907 ndi_devi_exit(scsi_vhci_dip, circ1);
1908 (void) mdi_phci_unregister(dip, 0);
1909 }
1910
1911 ddi_prop_remove_all(dip);
1912
1913 return (DDI_SUCCESS);
1914 }
1915
1916 /* Make sure power level is D0 before accessing registers */
1917 if (mpt->m_options & MPTSAS_OPT_PM) {
1918 (void) pm_busy_component(dip, 0);
1919 if (mpt->m_power_level != PM_LEVEL_D0) {
1920 if (pm_raise_power(dip, 0, PM_LEVEL_D0) !=
1921 DDI_SUCCESS) {
1922 mptsas_log(mpt, CE_WARN,
1923 "mptsas%d: Raise power request failed.",
1924 mpt->m_instance);
1925 (void) pm_idle_component(dip, 0);
1926 return (DDI_FAILURE);
1927 }
1928 }
1929 }
1930
1931 /*
1932 * Send RAID action system shutdown to sync IR. After action, send a
1933 * Message Unit Reset. Since after that DMA resource will be freed,
1934 * set ioc to READY state will avoid HBA initiated DMA operation.
1935 */
1936 mutex_enter(&mpt->m_mutex);
1937 MPTSAS_DISABLE_INTR(mpt);
1938 mptsas_raid_action_system_shutdown(mpt);
1939 mpt->m_softstate |= MPTSAS_SS_MSG_UNIT_RESET;
1940 (void) mptsas_ioc_reset(mpt, FALSE);
1941 mutex_exit(&mpt->m_mutex);
1942 mptsas_rem_intrs(mpt);
1943 ddi_taskq_destroy(mpt->m_event_taskq);
1944 ddi_taskq_destroy(mpt->m_dr_taskq);
1945
1946 if (mpt->m_doneq_thread_n) {
1947 mutex_enter(&mpt->m_doneq_mutex);
1948 doneq_thread_num = mpt->m_doneq_thread_n;
1949 for (i = 0; i < mpt->m_doneq_thread_n; i++) {
1950 mutex_enter(&mpt->m_doneq_thread_id[i].mutex);
1951 mpt->m_doneq_thread_id[i].flag &=
1952 (~MPTSAS_DONEQ_THREAD_ACTIVE);
1953 cv_signal(&mpt->m_doneq_thread_id[i].cv);
1954 mutex_exit(&mpt->m_doneq_thread_id[i].mutex);
1955 }
1956 while (mpt->m_doneq_thread_n) {
1957 cv_wait(&mpt->m_doneq_thread_cv,
1958 &mpt->m_doneq_mutex);
1959 }
1960 for (i = 0; i < doneq_thread_num; i++) {
1961 cv_destroy(&mpt->m_doneq_thread_id[i].cv);
1962 mutex_destroy(&mpt->m_doneq_thread_id[i].mutex);
1963 }
1964 kmem_free(mpt->m_doneq_thread_id,
1965 sizeof (mptsas_doneq_thread_list_t)
1966 * doneq_thread_num);
1967 mutex_exit(&mpt->m_doneq_mutex);
1968 cv_destroy(&mpt->m_doneq_thread_cv);
1969 mutex_destroy(&mpt->m_doneq_mutex);
1970 }
1971
1972 scsi_hba_reset_notify_tear_down(mpt->m_reset_notify_listf);
1973
1974 mptsas_list_del(mpt);
1975
1976 /*
1977 * Cancel timeout threads for this mpt
1978 */
1979 mutex_enter(&mpt->m_mutex);
1980 if (mpt->m_quiesce_timeid) {
1981 timeout_id_t tid = mpt->m_quiesce_timeid;
1982 mpt->m_quiesce_timeid = 0;
1983 mutex_exit(&mpt->m_mutex);
1984 (void) untimeout(tid);
1985 mutex_enter(&mpt->m_mutex);
1986 }
1987
1988 if (mpt->m_restart_cmd_timeid) {
1989 timeout_id_t tid = mpt->m_restart_cmd_timeid;
1990 mpt->m_restart_cmd_timeid = 0;
1991 mutex_exit(&mpt->m_mutex);
1992 (void) untimeout(tid);
1993 mutex_enter(&mpt->m_mutex);
1994 }
1995
1996 mutex_exit(&mpt->m_mutex);
1997
1998 /*
1999 * last mpt? ... if active, CANCEL watch threads.
2000 */
2001 mutex_enter(&mptsas_global_mutex);
2002 if (mptsas_head == NULL) {
2003 timeout_id_t tid;
2004 /*
2005 * Clear mptsas_timeouts_enable so that the watch thread
2006 * gets restarted on DDI_ATTACH
2007 */
2008 mptsas_timeouts_enabled = 0;
2009 if (mptsas_timeout_id) {
2010 tid = mptsas_timeout_id;
2011 mptsas_timeout_id = 0;
2012 mutex_exit(&mptsas_global_mutex);
2013 (void) untimeout(tid);
2014 mutex_enter(&mptsas_global_mutex);
2015 }
2016 if (mptsas_reset_watch) {
2017 tid = mptsas_reset_watch;
2018 mptsas_reset_watch = 0;
2019 mutex_exit(&mptsas_global_mutex);
2020 (void) untimeout(tid);
2021 mutex_enter(&mptsas_global_mutex);
2022 }
2023 }
2024 mutex_exit(&mptsas_global_mutex);
2025
2026 /*
2027 * Delete Phy stats
2028 */
2029 mptsas_destroy_phy_stats(mpt);
2030
2031 mptsas_destroy_hashes(mpt);
2032
2033 /*
2034 * Delete nt_active.
2035 */
2036 mutex_enter(&mpt->m_mutex);
2037 mptsas_free_active_slots(mpt);
2038 mutex_exit(&mpt->m_mutex);
2039
2040 /* deallocate everything that was allocated in mptsas_attach */
2041 mptsas_cache_destroy(mpt);
2042
2043 mptsas_hba_fini(mpt);
2044 mptsas_cfg_fini(mpt);
2045
2046 /* Lower the power informing PM Framework */
2047 if (mpt->m_options & MPTSAS_OPT_PM) {
2048 if (pm_lower_power(dip, 0, PM_LEVEL_D3) != DDI_SUCCESS)
2049 mptsas_log(mpt, CE_WARN,
2050 "!mptsas%d: Lower power request failed "
2051 "during detach, ignoring.",
2052 mpt->m_instance);
2053 }
2054
2055 mutex_destroy(&mpt->m_tx_waitq_mutex);
2056 mutex_destroy(&mpt->m_passthru_mutex);
2057 mutex_destroy(&mpt->m_mutex);
2058 mutex_destroy(&mpt->m_taskmgmt_mutex);
2059 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
2060 mutex_destroy(&mpt->m_phy_info[i].smhba_info.phy_mutex);
2061 }
2062 cv_destroy(&mpt->m_cv);
2063 cv_destroy(&mpt->m_passthru_cv);
2064 cv_destroy(&mpt->m_fw_cv);
2065 cv_destroy(&mpt->m_config_cv);
2066 cv_destroy(&mpt->m_fw_diag_cv);
2067 cv_destroy(&mpt->m_extreq_sense_refcount_cv);
2068
2069 mptsas_smp_teardown(mpt);
2070 mptsas_hba_teardown(mpt);
2071
2072 mptsas_config_space_fini(mpt);
2073
2074 mptsas_free_handshake_msg(mpt);
2075
2076 mptsas_fm_fini(mpt);
2077 ddi_soft_state_free(mptsas_state, ddi_get_instance(dip));
2078 ddi_prop_remove_all(dip);
2079
2080 return (DDI_SUCCESS);
2081 }
2082
2083 static void
2084 mptsas_list_add(mptsas_t *mpt)
2085 {
2086 rw_enter(&mptsas_global_rwlock, RW_WRITER);
2087
2088 if (mptsas_head == NULL) {
2089 mptsas_head = mpt;
2090 } else {
2091 mptsas_tail->m_next = mpt;
2092 }
2093 mptsas_tail = mpt;
2094 rw_exit(&mptsas_global_rwlock);
2095 }
2096
2097 static void
2098 mptsas_list_del(mptsas_t *mpt)
2099 {
2100 mptsas_t *m;
2101 /*
2102 * Remove device instance from the global linked list
2103 */
2104 rw_enter(&mptsas_global_rwlock, RW_WRITER);
2105 if (mptsas_head == mpt) {
2106 m = mptsas_head = mpt->m_next;
2107 } else {
2108 for (m = mptsas_head; m != NULL; m = m->m_next) {
2109 if (m->m_next == mpt) {
2110 m->m_next = mpt->m_next;
2111 break;
2112 }
2113 }
2114 if (m == NULL) {
2115 mptsas_log(mpt, CE_PANIC, "Not in softc list!");
2116 }
2117 }
2118
2119 if (mptsas_tail == mpt) {
2120 mptsas_tail = m;
2121 }
2122 rw_exit(&mptsas_global_rwlock);
2123 }
2124
2125 static int
2126 mptsas_alloc_handshake_msg(mptsas_t *mpt, size_t alloc_size)
2127 {
2128 ddi_dma_attr_t task_dma_attrs;
2129
2130 mpt->m_hshk_dma_size = 0;
2131 task_dma_attrs = mpt->m_msg_dma_attr;
2132 task_dma_attrs.dma_attr_sgllen = 1;
2133 task_dma_attrs.dma_attr_granular = (uint32_t)(alloc_size);
2134
2135 /* allocate Task Management ddi_dma resources */
2136 if (mptsas_dma_addr_create(mpt, task_dma_attrs,
2137 &mpt->m_hshk_dma_hdl, &mpt->m_hshk_acc_hdl, &mpt->m_hshk_memp,
2138 alloc_size, NULL) == FALSE) {
2139 return (DDI_FAILURE);
2140 }
2141 mpt->m_hshk_dma_size = alloc_size;
2142
2143 return (DDI_SUCCESS);
2144 }
2145
2146 static void
2147 mptsas_free_handshake_msg(mptsas_t *mpt)
2148 {
2149 if (mpt->m_hshk_dma_size == 0)
2150 return;
2151 mptsas_dma_addr_destroy(&mpt->m_hshk_dma_hdl, &mpt->m_hshk_acc_hdl);
2152 mpt->m_hshk_dma_size = 0;
2153 }
2154
2155 static int
2156 mptsas_hba_setup(mptsas_t *mpt)
2157 {
2158 scsi_hba_tran_t *hba_tran;
2159 int tran_flags;
2160
2161 /* Allocate a transport structure */
2162 hba_tran = mpt->m_tran = scsi_hba_tran_alloc(mpt->m_dip,
2163 SCSI_HBA_CANSLEEP);
2164 ASSERT(mpt->m_tran != NULL);
2165
2166 hba_tran->tran_hba_private = mpt;
2167 hba_tran->tran_tgt_private = NULL;
2168
2169 hba_tran->tran_tgt_init = mptsas_scsi_tgt_init;
2170 hba_tran->tran_tgt_free = mptsas_scsi_tgt_free;
2171
2172 hba_tran->tran_start = mptsas_scsi_start;
2173 hba_tran->tran_reset = mptsas_scsi_reset;
2174 hba_tran->tran_abort = mptsas_scsi_abort;
2175 hba_tran->tran_getcap = mptsas_scsi_getcap;
2176 hba_tran->tran_setcap = mptsas_scsi_setcap;
2177 hba_tran->tran_init_pkt = mptsas_scsi_init_pkt;
2178 hba_tran->tran_destroy_pkt = mptsas_scsi_destroy_pkt;
2179
2180 hba_tran->tran_dmafree = mptsas_scsi_dmafree;
2181 hba_tran->tran_sync_pkt = mptsas_scsi_sync_pkt;
2182 hba_tran->tran_reset_notify = mptsas_scsi_reset_notify;
2183
2184 hba_tran->tran_get_bus_addr = mptsas_get_bus_addr;
2185 hba_tran->tran_get_name = mptsas_get_name;
2186
2187 hba_tran->tran_quiesce = mptsas_scsi_quiesce;
2188 hba_tran->tran_unquiesce = mptsas_scsi_unquiesce;
2189 hba_tran->tran_bus_reset = NULL;
2190
2191 hba_tran->tran_add_eventcall = NULL;
2192 hba_tran->tran_get_eventcookie = NULL;
2193 hba_tran->tran_post_event = NULL;
2194 hba_tran->tran_remove_eventcall = NULL;
2195
2196 hba_tran->tran_bus_config = mptsas_bus_config;
2197
2198 hba_tran->tran_interconnect_type = INTERCONNECT_SAS;
2199
2200 /*
2201 * All children of the HBA are iports. We need tran was cloned.
2202 * So we pass the flags to SCSA. SCSI_HBA_TRAN_CLONE will be
2203 * inherited to iport's tran vector.
2204 */
2205 tran_flags = (SCSI_HBA_HBA | SCSI_HBA_TRAN_CLONE);
2206
2207 if (scsi_hba_attach_setup(mpt->m_dip, &mpt->m_msg_dma_attr,
2208 hba_tran, tran_flags) != DDI_SUCCESS) {
2209 mptsas_log(mpt, CE_WARN, "hba attach setup failed");
2210 scsi_hba_tran_free(hba_tran);
2211 mpt->m_tran = NULL;
2212 return (FALSE);
2213 }
2214 return (TRUE);
2215 }
2216
2217 static void
2218 mptsas_hba_teardown(mptsas_t *mpt)
2219 {
2220 (void) scsi_hba_detach(mpt->m_dip);
2221 if (mpt->m_tran != NULL) {
2222 scsi_hba_tran_free(mpt->m_tran);
2223 mpt->m_tran = NULL;
2224 }
2225 }
2226
2227 static void
2228 mptsas_iport_register(mptsas_t *mpt)
2229 {
2230 int i, j;
2231 mptsas_phymask_t mask = 0x0;
2232 /*
2233 * initial value of mask is 0
2234 */
2235 mutex_enter(&mpt->m_mutex);
2236 for (i = 0; i < mpt->m_num_phys; i++) {
2237 mptsas_phymask_t phy_mask = 0x0;
2238 char phy_mask_name[MPTSAS_MAX_PHYS];
2239 uint8_t current_port;
2240
2241 if (mpt->m_phy_info[i].attached_devhdl == 0)
2242 continue;
2243
2244 bzero(phy_mask_name, sizeof (phy_mask_name));
2245
2246 current_port = mpt->m_phy_info[i].port_num;
2247
2248 if ((mask & (1 << i)) != 0)
2249 continue;
2250
2251 for (j = 0; j < mpt->m_num_phys; j++) {
2252 if (mpt->m_phy_info[j].attached_devhdl &&
2253 (mpt->m_phy_info[j].port_num == current_port)) {
2254 phy_mask |= (1 << j);
2255 }
2256 }
2257 mask = mask | phy_mask;
2258
2259 for (j = 0; j < mpt->m_num_phys; j++) {
2260 if ((phy_mask >> j) & 0x01) {
2261 mpt->m_phy_info[j].phy_mask = phy_mask;
2262 }
2263 }
2264
2265 (void) sprintf(phy_mask_name, "%x", phy_mask);
2266
2267 mutex_exit(&mpt->m_mutex);
2268 /*
2269 * register a iport
2270 */
2271 (void) scsi_hba_iport_register(mpt->m_dip, phy_mask_name);
2272 mutex_enter(&mpt->m_mutex);
2273 }
2274 mutex_exit(&mpt->m_mutex);
2275 /*
2276 * register a virtual port for RAID volume always
2277 */
2278 (void) scsi_hba_iport_register(mpt->m_dip, "v0");
2279
2280 }
2281
2282 static int
2283 mptsas_smp_setup(mptsas_t *mpt)
2284 {
2285 mpt->m_smptran = smp_hba_tran_alloc(mpt->m_dip);
2286 ASSERT(mpt->m_smptran != NULL);
2287 mpt->m_smptran->smp_tran_hba_private = mpt;
2288 mpt->m_smptran->smp_tran_start = mptsas_smp_start;
2289 if (smp_hba_attach_setup(mpt->m_dip, mpt->m_smptran) != DDI_SUCCESS) {
2290 mptsas_log(mpt, CE_WARN, "smp attach setup failed");
2291 smp_hba_tran_free(mpt->m_smptran);
2292 mpt->m_smptran = NULL;
2293 return (FALSE);
2294 }
2295 /*
2296 * Initialize smp hash table
2297 */
2298 mpt->m_smp_targets = refhash_create(MPTSAS_SMP_BUCKET_COUNT,
2299 mptsas_target_addr_hash, mptsas_target_addr_cmp,
2300 mptsas_smp_free, sizeof (mptsas_smp_t),
2301 offsetof(mptsas_smp_t, m_link), offsetof(mptsas_smp_t, m_addr),
2302 KM_SLEEP);
2303 mpt->m_smp_devhdl = 0xFFFF;
2304
2305 return (TRUE);
2306 }
2307
2308 static void
2309 mptsas_smp_teardown(mptsas_t *mpt)
2310 {
2311 (void) smp_hba_detach(mpt->m_dip);
2312 if (mpt->m_smptran != NULL) {
2313 smp_hba_tran_free(mpt->m_smptran);
2314 mpt->m_smptran = NULL;
2315 }
2316 mpt->m_smp_devhdl = 0;
2317 }
2318
2319 static int
2320 mptsas_cache_create(mptsas_t *mpt)
2321 {
2322 int instance = mpt->m_instance;
2323 char buf[64];
2324
2325 /*
2326 * create kmem cache for packets
2327 */
2328 (void) sprintf(buf, "mptsas%d_cache", instance);
2329 mpt->m_kmem_cache = kmem_cache_create(buf,
2330 sizeof (struct mptsas_cmd) + scsi_pkt_size(), 8,
2331 mptsas_kmem_cache_constructor, mptsas_kmem_cache_destructor,
2332 NULL, (void *)mpt, NULL, 0);
2333
2334 if (mpt->m_kmem_cache == NULL) {
2335 mptsas_log(mpt, CE_WARN, "creating kmem cache failed");
2336 return (FALSE);
2337 }
2338
2339 /*
2340 * create kmem cache for extra SGL frames if SGL cannot
2341 * be accomodated into main request frame.
2342 */
2343 (void) sprintf(buf, "mptsas%d_cache_frames", instance);
2344 mpt->m_cache_frames = kmem_cache_create(buf,
2345 sizeof (mptsas_cache_frames_t), 8,
2346 mptsas_cache_frames_constructor, mptsas_cache_frames_destructor,
2347 NULL, (void *)mpt, NULL, 0);
2348
2349 if (mpt->m_cache_frames == NULL) {
2350 mptsas_log(mpt, CE_WARN, "creating cache for frames failed");
2351 return (FALSE);
2352 }
2353
2354 return (TRUE);
2355 }
2356
2357 static void
2358 mptsas_cache_destroy(mptsas_t *mpt)
2359 {
2360 /* deallocate in reverse order */
2361 if (mpt->m_cache_frames) {
2362 kmem_cache_destroy(mpt->m_cache_frames);
2363 mpt->m_cache_frames = NULL;
2364 }
2365 if (mpt->m_kmem_cache) {
2366 kmem_cache_destroy(mpt->m_kmem_cache);
2367 mpt->m_kmem_cache = NULL;
2368 }
2369 }
2370
2371 static int
2372 mptsas_power(dev_info_t *dip, int component, int level)
2373 {
2374 #ifndef __lock_lint
2375 _NOTE(ARGUNUSED(component))
2376 #endif
2377 mptsas_t *mpt;
2378 int rval = DDI_SUCCESS;
2379 int polls = 0;
2380 uint32_t ioc_status;
2381
2382 if (scsi_hba_iport_unit_address(dip) != 0)
2383 return (DDI_SUCCESS);
2384
2385 mpt = ddi_get_soft_state(mptsas_state, ddi_get_instance(dip));
2386 if (mpt == NULL) {
2387 return (DDI_FAILURE);
2388 }
2389
2390 mutex_enter(&mpt->m_mutex);
2391
2392 /*
2393 * If the device is busy, don't lower its power level
2394 */
2395 if (mpt->m_busy && (mpt->m_power_level > level)) {
2396 mutex_exit(&mpt->m_mutex);
2397 return (DDI_FAILURE);
2398 }
2399 switch (level) {
2400 case PM_LEVEL_D0:
2401 NDBG11(("mptsas%d: turning power ON.", mpt->m_instance));
2402 MPTSAS_POWER_ON(mpt);
2403 /*
2404 * Wait up to 30 seconds for IOC to come out of reset.
2405 */
2406 while (((ioc_status = ddi_get32(mpt->m_datap,
2407 &mpt->m_reg->Doorbell)) &
2408 MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_RESET) {
2409 if (polls++ > 3000) {
2410 break;
2411 }
2412 delay(drv_usectohz(10000));
2413 }
2414 /*
2415 * If IOC is not in operational state, try to hard reset it.
2416 */
2417 if ((ioc_status & MPI2_IOC_STATE_MASK) !=
2418 MPI2_IOC_STATE_OPERATIONAL) {
2419 mpt->m_softstate &= ~MPTSAS_SS_MSG_UNIT_RESET;
2420 if (mptsas_reset_handler(mpt) == DDI_FAILURE) {
2421 mptsas_log(mpt, CE_WARN,
2422 "mptsas_power: hard reset failed");
2423 mutex_exit(&mpt->m_mutex);
2424 return (DDI_FAILURE);
2425 }
2426 }
2427 mpt->m_power_level = PM_LEVEL_D0;
2428 break;
2429 case PM_LEVEL_D3:
2430 NDBG11(("mptsas%d: turning power OFF.", mpt->m_instance));
2431 MPTSAS_POWER_OFF(mpt);
2432 break;
2433 default:
2434 mptsas_log(mpt, CE_WARN, "mptsas%d: unknown power level <%x>.",
2435 mpt->m_instance, level);
2436 rval = DDI_FAILURE;
2437 break;
2438 }
2439 mutex_exit(&mpt->m_mutex);
2440 return (rval);
2441 }
2442
2443 /*
2444 * Initialize configuration space and figure out which
2445 * chip and revison of the chip the mpt driver is using.
2446 */
2447 static int
2448 mptsas_config_space_init(mptsas_t *mpt)
2449 {
2450 NDBG0(("mptsas_config_space_init"));
2451
2452 if (mpt->m_config_handle != NULL)
2453 return (TRUE);
2454
2455 if (pci_config_setup(mpt->m_dip,
2456 &mpt->m_config_handle) != DDI_SUCCESS) {
2457 mptsas_log(mpt, CE_WARN, "cannot map configuration space.");
2458 return (FALSE);
2459 }
2460
2461 /*
2462 * This is a workaround for a XMITS ASIC bug which does not
2463 * drive the CBE upper bits.
2464 */
2465 if (pci_config_get16(mpt->m_config_handle, PCI_CONF_STAT) &
2466 PCI_STAT_PERROR) {
2467 pci_config_put16(mpt->m_config_handle, PCI_CONF_STAT,
2468 PCI_STAT_PERROR);
2469 }
2470
2471 mptsas_setup_cmd_reg(mpt);
2472
2473 /*
2474 * Get the chip device id:
2475 */
2476 mpt->m_devid = pci_config_get16(mpt->m_config_handle, PCI_CONF_DEVID);
2477
2478 /*
2479 * Save the revision.
2480 */
2481 mpt->m_revid = pci_config_get8(mpt->m_config_handle, PCI_CONF_REVID);
2482
2483 /*
2484 * Save the SubSystem Vendor and Device IDs
2485 */
2486 mpt->m_svid = pci_config_get16(mpt->m_config_handle, PCI_CONF_SUBVENID);
2487 mpt->m_ssid = pci_config_get16(mpt->m_config_handle, PCI_CONF_SUBSYSID);
2488
2489 /*
2490 * Set the latency timer to 0x40 as specified by the upa -> pci
2491 * bridge chip design team. This may be done by the sparc pci
2492 * bus nexus driver, but the driver should make sure the latency
2493 * timer is correct for performance reasons.
2494 */
2495 pci_config_put8(mpt->m_config_handle, PCI_CONF_LATENCY_TIMER,
2496 MPTSAS_LATENCY_TIMER);
2497
2498 (void) mptsas_get_pci_cap(mpt);
2499 return (TRUE);
2500 }
2501
2502 static void
2503 mptsas_config_space_fini(mptsas_t *mpt)
2504 {
2505 if (mpt->m_config_handle != NULL) {
2506 mptsas_disable_bus_master(mpt);
2507 pci_config_teardown(&mpt->m_config_handle);
2508 mpt->m_config_handle = NULL;
2509 }
2510 }
2511
2512 static void
2513 mptsas_setup_cmd_reg(mptsas_t *mpt)
2514 {
2515 ushort_t cmdreg;
2516
2517 /*
2518 * Set the command register to the needed values.
2519 */
2520 cmdreg = pci_config_get16(mpt->m_config_handle, PCI_CONF_COMM);
2521 cmdreg |= (PCI_COMM_ME | PCI_COMM_SERR_ENABLE |
2522 PCI_COMM_PARITY_DETECT | PCI_COMM_MAE);
2523 cmdreg &= ~PCI_COMM_IO;
2524 pci_config_put16(mpt->m_config_handle, PCI_CONF_COMM, cmdreg);
2525 }
2526
2527 static void
2528 mptsas_disable_bus_master(mptsas_t *mpt)
2529 {
2530 ushort_t cmdreg;
2531
2532 /*
2533 * Clear the master enable bit in the PCI command register.
2534 * This prevents any bus mastering activity like DMA.
2535 */
2536 cmdreg = pci_config_get16(mpt->m_config_handle, PCI_CONF_COMM);
2537 cmdreg &= ~PCI_COMM_ME;
2538 pci_config_put16(mpt->m_config_handle, PCI_CONF_COMM, cmdreg);
2539 }
2540
2541 int
2542 mptsas_dma_alloc(mptsas_t *mpt, mptsas_dma_alloc_state_t *dma_statep)
2543 {
2544 ddi_dma_attr_t attrs;
2545
2546 attrs = mpt->m_io_dma_attr;
2547 attrs.dma_attr_sgllen = 1;
2548
2549 ASSERT(dma_statep != NULL);
2550
2551 if (mptsas_dma_addr_create(mpt, attrs, &dma_statep->handle,
2552 &dma_statep->accessp, &dma_statep->memp, dma_statep->size,
2553 &dma_statep->cookie) == FALSE) {
2554 return (DDI_FAILURE);
2555 }
2556
2557 return (DDI_SUCCESS);
2558 }
2559
2560 void
2561 mptsas_dma_free(mptsas_dma_alloc_state_t *dma_statep)
2562 {
2563 ASSERT(dma_statep != NULL);
2564 mptsas_dma_addr_destroy(&dma_statep->handle, &dma_statep->accessp);
2565 dma_statep->size = 0;
2566 }
2567
2568 int
2569 mptsas_do_dma(mptsas_t *mpt, uint32_t size, int var, int (*callback)())
2570 {
2571 ddi_dma_attr_t attrs;
2572 ddi_dma_handle_t dma_handle;
2573 caddr_t memp;
2574 ddi_acc_handle_t accessp;
2575 int rval;
2576
2577 ASSERT(mutex_owned(&mpt->m_mutex));
2578
2579 attrs = mpt->m_msg_dma_attr;
2580 attrs.dma_attr_sgllen = 1;
2581 attrs.dma_attr_granular = size;
2582
2583 if (mptsas_dma_addr_create(mpt, attrs, &dma_handle,
2584 &accessp, &memp, size, NULL) == FALSE) {
2585 return (DDI_FAILURE);
2586 }
2587
2588 rval = (*callback) (mpt, memp, var, accessp);
2589
2590 if ((mptsas_check_dma_handle(dma_handle) != DDI_SUCCESS) ||
2591 (mptsas_check_acc_handle(accessp) != DDI_SUCCESS)) {
2592 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
2593 rval = DDI_FAILURE;
2594 }
2595
2596 mptsas_dma_addr_destroy(&dma_handle, &accessp);
2597 return (rval);
2598
2599 }
2600
2601 static int
2602 mptsas_alloc_request_frames(mptsas_t *mpt)
2603 {
2604 ddi_dma_attr_t frame_dma_attrs;
2605 caddr_t memp;
2606 ddi_dma_cookie_t cookie;
2607 size_t mem_size;
2608
2609 /*
2610 * re-alloc when it has already alloced
2611 */
2612 if (mpt->m_dma_req_frame_hdl)
2613 mptsas_dma_addr_destroy(&mpt->m_dma_req_frame_hdl,
2614 &mpt->m_acc_req_frame_hdl);
2615
2616 /*
2617 * The size of the request frame pool is:
2618 * Number of Request Frames * Request Frame Size
2619 */
2620 mem_size = mpt->m_max_requests * mpt->m_req_frame_size;
2621
2622 /*
2623 * set the DMA attributes. System Request Message Frames must be
2624 * aligned on a 16-byte boundry.
2625 */
2626 frame_dma_attrs = mpt->m_msg_dma_attr;
2627 frame_dma_attrs.dma_attr_align = 16;
2628 frame_dma_attrs.dma_attr_sgllen = 1;
2629
2630 /*
2631 * allocate the request frame pool.
2632 */
2633 if (mptsas_dma_addr_create(mpt, frame_dma_attrs,
2634 &mpt->m_dma_req_frame_hdl, &mpt->m_acc_req_frame_hdl, &memp,
2635 mem_size, &cookie) == FALSE) {
2636 return (DDI_FAILURE);
2637 }
2638
2639 /*
2640 * Store the request frame memory address. This chip uses this
2641 * address to dma to and from the driver's frame. The second
2642 * address is the address mpt uses to fill in the frame.
2643 */
2644 mpt->m_req_frame_dma_addr = cookie.dmac_laddress;
2645 mpt->m_req_frame = memp;
2646
2647 /*
2648 * Clear the request frame pool.
2649 */
2650 bzero(mpt->m_req_frame, mem_size);
2651
2652 return (DDI_SUCCESS);
2653 }
2654
2655 static int
2656 mptsas_alloc_sense_bufs(mptsas_t *mpt)
2657 {
2658 ddi_dma_attr_t sense_dma_attrs;
2659 caddr_t memp;
2660 ddi_dma_cookie_t cookie;
2661 size_t mem_size;
2662 int num_extrqsense_bufs;
2663
2664 ASSERT(mpt->m_extreq_sense_refcount == 0);
2665
2666 /*
2667 * re-alloc when it has already alloced
2668 */
2669 if (mpt->m_dma_req_sense_hdl) {
2670 rmfreemap(mpt->m_erqsense_map);
2671 mptsas_dma_addr_destroy(&mpt->m_dma_req_sense_hdl,
2672 &mpt->m_acc_req_sense_hdl);
2673 }
2674
2675 /*
2676 * The size of the request sense pool is:
2677 * (Number of Request Frames - 2 ) * Request Sense Size +
2678 * extra memory for extended sense requests.
2679 */
2680 mem_size = ((mpt->m_max_requests - 2) * mpt->m_req_sense_size) +
2681 mptsas_extreq_sense_bufsize;
2682
2683 /*
2684 * set the DMA attributes. ARQ buffers
2685 * aligned on a 16-byte boundry.
2686 */
2687 sense_dma_attrs = mpt->m_msg_dma_attr;
2688 sense_dma_attrs.dma_attr_align = 16;
2689 sense_dma_attrs.dma_attr_sgllen = 1;
2690
2691 /*
2692 * allocate the request sense buffer pool.
2693 */
2694 if (mptsas_dma_addr_create(mpt, sense_dma_attrs,
2695 &mpt->m_dma_req_sense_hdl, &mpt->m_acc_req_sense_hdl, &memp,
2696 mem_size, &cookie) == FALSE) {
2697 return (DDI_FAILURE);
2698 }
2699
2700 /*
2701 * Store the request sense base memory address. This chip uses this
2702 * address to dma the request sense data. The second
2703 * address is the address mpt uses to access the data.
2704 * The third is the base for the extended rqsense buffers.
2705 */
2706 mpt->m_req_sense_dma_addr = cookie.dmac_laddress;
2707 mpt->m_req_sense = memp;
2708 memp += (mpt->m_max_requests - 2) * mpt->m_req_sense_size;
2709 mpt->m_extreq_sense = memp;
2710
2711 /*
2712 * The extra memory is divided up into multiples of the base
2713 * buffer size in order to allocate via rmalloc().
2714 * Note that the rmallocmap cannot start at zero!
2715 */
2716 num_extrqsense_bufs = mptsas_extreq_sense_bufsize /
2717 mpt->m_req_sense_size;
2718 mpt->m_erqsense_map = rmallocmap_wait(num_extrqsense_bufs);
2719 rmfree(mpt->m_erqsense_map, num_extrqsense_bufs, 1);
2720
2721 /*
2722 * Clear the pool.
2723 */
2724 bzero(mpt->m_req_sense, mem_size);
2725
2726 return (DDI_SUCCESS);
2727 }
2728
2729 static int
2730 mptsas_alloc_reply_frames(mptsas_t *mpt)
2731 {
2732 ddi_dma_attr_t frame_dma_attrs;
2733 caddr_t memp;
2734 ddi_dma_cookie_t cookie;
2735 size_t mem_size;
2736
2737 /*
2738 * re-alloc when it has already alloced
2739 */
2740 if (mpt->m_dma_reply_frame_hdl) {
2741 mptsas_dma_addr_destroy(&mpt->m_dma_reply_frame_hdl,
2742 &mpt->m_acc_reply_frame_hdl);
2743 }
2744
2745 /*
2746 * The size of the reply frame pool is:
2747 * Number of Reply Frames * Reply Frame Size
2748 */
2749 mem_size = mpt->m_max_replies * mpt->m_reply_frame_size;
2750
2751 /*
2752 * set the DMA attributes. System Reply Message Frames must be
2753 * aligned on a 4-byte boundry. This is the default.
2754 */
2755 frame_dma_attrs = mpt->m_msg_dma_attr;
2756 frame_dma_attrs.dma_attr_sgllen = 1;
2757
2758 /*
2759 * allocate the reply frame pool
2760 */
2761 if (mptsas_dma_addr_create(mpt, frame_dma_attrs,
2762 &mpt->m_dma_reply_frame_hdl, &mpt->m_acc_reply_frame_hdl, &memp,
2763 mem_size, &cookie) == FALSE) {
2764 return (DDI_FAILURE);
2765 }
2766
2767 /*
2768 * Store the reply frame memory address. This chip uses this
2769 * address to dma to and from the driver's frame. The second
2770 * address is the address mpt uses to process the frame.
2771 */
2772 mpt->m_reply_frame_dma_addr = cookie.dmac_laddress;
2773 mpt->m_reply_frame = memp;
2774
2775 /*
2776 * Clear the reply frame pool.
2777 */
2778 bzero(mpt->m_reply_frame, mem_size);
2779
2780 return (DDI_SUCCESS);
2781 }
2782
2783 static int
2784 mptsas_alloc_free_queue(mptsas_t *mpt)
2785 {
2786 ddi_dma_attr_t frame_dma_attrs;
2787 caddr_t memp;
2788 ddi_dma_cookie_t cookie;
2789 size_t mem_size;
2790
2791 /*
2792 * re-alloc when it has already alloced
2793 */
2794 if (mpt->m_dma_free_queue_hdl) {
2795 mptsas_dma_addr_destroy(&mpt->m_dma_free_queue_hdl,
2796 &mpt->m_acc_free_queue_hdl);
2797 }
2798
2799 /*
2800 * The reply free queue size is:
2801 * Reply Free Queue Depth * 4
2802 * The "4" is the size of one 32 bit address (low part of 64-bit
2803 * address)
2804 */
2805 mem_size = mpt->m_free_queue_depth * 4;
2806
2807 /*
2808 * set the DMA attributes The Reply Free Queue must be aligned on a
2809 * 16-byte boundry.
2810 */
2811 frame_dma_attrs = mpt->m_msg_dma_attr;
2812 frame_dma_attrs.dma_attr_align = 16;
2813 frame_dma_attrs.dma_attr_sgllen = 1;
2814
2815 /*
2816 * allocate the reply free queue
2817 */
2818 if (mptsas_dma_addr_create(mpt, frame_dma_attrs,
2819 &mpt->m_dma_free_queue_hdl, &mpt->m_acc_free_queue_hdl, &memp,
2820 mem_size, &cookie) == FALSE) {
2821 return (DDI_FAILURE);
2822 }
2823
2824 /*
2825 * Store the reply free queue memory address. This chip uses this
2826 * address to read from the reply free queue. The second address
2827 * is the address mpt uses to manage the queue.
2828 */
2829 mpt->m_free_queue_dma_addr = cookie.dmac_laddress;
2830 mpt->m_free_queue = memp;
2831
2832 /*
2833 * Clear the reply free queue memory.
2834 */
2835 bzero(mpt->m_free_queue, mem_size);
2836
2837 return (DDI_SUCCESS);
2838 }
2839
2840 static int
2841 mptsas_alloc_post_queue(mptsas_t *mpt)
2842 {
2843 ddi_dma_attr_t frame_dma_attrs;
2844 caddr_t memp;
2845 ddi_dma_cookie_t cookie;
2846 size_t mem_size;
2847
2848 /*
2849 * re-alloc when it has already alloced
2850 */
2851 if (mpt->m_dma_post_queue_hdl) {
2852 mptsas_dma_addr_destroy(&mpt->m_dma_post_queue_hdl,
2853 &mpt->m_acc_post_queue_hdl);
2854 }
2855
2856 /*
2857 * The reply descriptor post queue size is:
2858 * Reply Descriptor Post Queue Depth * 8
2859 * The "8" is the size of each descriptor (8 bytes or 64 bits).
2860 */
2861 mem_size = mpt->m_post_queue_depth * 8;
2862
2863 /*
2864 * set the DMA attributes. The Reply Descriptor Post Queue must be
2865 * aligned on a 16-byte boundry.
2866 */
2867 frame_dma_attrs = mpt->m_msg_dma_attr;
2868 frame_dma_attrs.dma_attr_align = 16;
2869 frame_dma_attrs.dma_attr_sgllen = 1;
2870
2871 /*
2872 * allocate the reply post queue
2873 */
2874 if (mptsas_dma_addr_create(mpt, frame_dma_attrs,
2875 &mpt->m_dma_post_queue_hdl, &mpt->m_acc_post_queue_hdl, &memp,
2876 mem_size, &cookie) == FALSE) {
2877 return (DDI_FAILURE);
2878 }
2879
2880 /*
2881 * Store the reply descriptor post queue memory address. This chip
2882 * uses this address to write to the reply descriptor post queue. The
2883 * second address is the address mpt uses to manage the queue.
2884 */
2885 mpt->m_post_queue_dma_addr = cookie.dmac_laddress;
2886 mpt->m_post_queue = memp;
2887
2888 /*
2889 * Clear the reply post queue memory.
2890 */
2891 bzero(mpt->m_post_queue, mem_size);
2892
2893 return (DDI_SUCCESS);
2894 }
2895
2896 static void
2897 mptsas_alloc_reply_args(mptsas_t *mpt)
2898 {
2899 if (mpt->m_replyh_args == NULL) {
2900 mpt->m_replyh_args = kmem_zalloc(sizeof (m_replyh_arg_t) *
2901 mpt->m_max_replies, KM_SLEEP);
2902 }
2903 }
2904
2905 static int
2906 mptsas_alloc_extra_sgl_frame(mptsas_t *mpt, mptsas_cmd_t *cmd)
2907 {
2908 mptsas_cache_frames_t *frames = NULL;
2909 if (cmd->cmd_extra_frames == NULL) {
2910 frames = kmem_cache_alloc(mpt->m_cache_frames, KM_NOSLEEP);
2911 if (frames == NULL) {
2912 return (DDI_FAILURE);
2913 }
2914 cmd->cmd_extra_frames = frames;
2915 }
2916 return (DDI_SUCCESS);
2917 }
2918
2919 static void
2920 mptsas_free_extra_sgl_frame(mptsas_t *mpt, mptsas_cmd_t *cmd)
2921 {
2922 if (cmd->cmd_extra_frames) {
2923 kmem_cache_free(mpt->m_cache_frames,
2924 (void *)cmd->cmd_extra_frames);
2925 cmd->cmd_extra_frames = NULL;
2926 }
2927 }
2928
2929 static void
2930 mptsas_cfg_fini(mptsas_t *mpt)
2931 {
2932 NDBG0(("mptsas_cfg_fini"));
2933 ddi_regs_map_free(&mpt->m_datap);
2934 }
2935
2936 static void
2937 mptsas_hba_fini(mptsas_t *mpt)
2938 {
2939 NDBG0(("mptsas_hba_fini"));
2940
2941 /*
2942 * Free up any allocated memory
2943 */
2944 if (mpt->m_dma_req_frame_hdl) {
2945 mptsas_dma_addr_destroy(&mpt->m_dma_req_frame_hdl,
2946 &mpt->m_acc_req_frame_hdl);
2947 }
2948
2949 if (mpt->m_dma_req_sense_hdl) {
2950 rmfreemap(mpt->m_erqsense_map);
2951 mptsas_dma_addr_destroy(&mpt->m_dma_req_sense_hdl,
2952 &mpt->m_acc_req_sense_hdl);
2953 }
2954
2955 if (mpt->m_dma_reply_frame_hdl) {
2956 mptsas_dma_addr_destroy(&mpt->m_dma_reply_frame_hdl,
2957 &mpt->m_acc_reply_frame_hdl);
2958 }
2959
2960 if (mpt->m_dma_free_queue_hdl) {
2961 mptsas_dma_addr_destroy(&mpt->m_dma_free_queue_hdl,
2962 &mpt->m_acc_free_queue_hdl);
2963 }
2964
2965 if (mpt->m_dma_post_queue_hdl) {
2966 mptsas_dma_addr_destroy(&mpt->m_dma_post_queue_hdl,
2967 &mpt->m_acc_post_queue_hdl);
2968 }
2969
2970 if (mpt->m_replyh_args != NULL) {
2971 kmem_free(mpt->m_replyh_args, sizeof (m_replyh_arg_t)
2972 * mpt->m_max_replies);
2973 }
2974 }
2975
2976 static int
2977 mptsas_name_child(dev_info_t *lun_dip, char *name, int len)
2978 {
2979 int lun = 0;
2980 char *sas_wwn = NULL;
2981 int phynum = -1;
2982 int reallen = 0;
2983
2984 /* Get the target num */
2985 lun = ddi_prop_get_int(DDI_DEV_T_ANY, lun_dip, DDI_PROP_DONTPASS,
2986 LUN_PROP, 0);
2987
2988 if ((phynum = ddi_prop_get_int(DDI_DEV_T_ANY, lun_dip,
2989 DDI_PROP_DONTPASS, "sata-phy", -1)) != -1) {
2990 /*
2991 * Stick in the address of form "pPHY,LUN"
2992 */
2993 reallen = snprintf(name, len, "p%x,%x", phynum, lun);
2994 } else if (ddi_prop_lookup_string(DDI_DEV_T_ANY, lun_dip,
2995 DDI_PROP_DONTPASS, SCSI_ADDR_PROP_TARGET_PORT, &sas_wwn)
2996 == DDI_PROP_SUCCESS) {
2997 /*
2998 * Stick in the address of the form "wWWN,LUN"
2999 */
3000 reallen = snprintf(name, len, "%s,%x", sas_wwn, lun);
3001 ddi_prop_free(sas_wwn);
3002 } else {
3003 return (DDI_FAILURE);
3004 }
3005
3006 ASSERT(reallen < len);
3007 if (reallen >= len) {
3008 mptsas_log(0, CE_WARN, "!mptsas_get_name: name parameter "
3009 "length too small, it needs to be %d bytes", reallen + 1);
3010 }
3011 return (DDI_SUCCESS);
3012 }
3013
3014 /*
3015 * tran_tgt_init(9E) - target device instance initialization
3016 */
3017 static int
3018 mptsas_scsi_tgt_init(dev_info_t *hba_dip, dev_info_t *tgt_dip,
3019 scsi_hba_tran_t *hba_tran, struct scsi_device *sd)
3020 {
3021 #ifndef __lock_lint
3022 _NOTE(ARGUNUSED(hba_tran))
3023 #endif
3024
3025 /*
3026 * At this point, the scsi_device structure already exists
3027 * and has been initialized.
3028 *
3029 * Use this function to allocate target-private data structures,
3030 * if needed by this HBA. Add revised flow-control and queue
3031 * properties for child here, if desired and if you can tell they
3032 * support tagged queueing by now.
3033 */
3034 mptsas_t *mpt;
3035 int lun = sd->sd_address.a_lun;
3036 mdi_pathinfo_t *pip = NULL;
3037 mptsas_tgt_private_t *tgt_private = NULL;
3038 mptsas_target_t *ptgt = NULL;
3039 char *psas_wwn = NULL;
3040 mptsas_phymask_t phymask = 0;
3041 uint64_t sas_wwn = 0;
3042 mptsas_target_addr_t addr;
3043 mpt = SDEV2MPT(sd);
3044
3045 ASSERT(scsi_hba_iport_unit_address(hba_dip) != 0);
3046
3047 NDBG0(("mptsas_scsi_tgt_init: hbadip=0x%p tgtdip=0x%p lun=%d",
3048 (void *)hba_dip, (void *)tgt_dip, lun));
3049
3050 if (ndi_dev_is_persistent_node(tgt_dip) == 0) {
3051 (void) ndi_merge_node(tgt_dip, mptsas_name_child);
3052 ddi_set_name_addr(tgt_dip, NULL);
3053 return (DDI_FAILURE);
3054 }
3055 /*
3056 * phymask is 0 means the virtual port for RAID
3057 */
3058 phymask = (mptsas_phymask_t)ddi_prop_get_int(DDI_DEV_T_ANY, hba_dip, 0,
3059 "phymask", 0);
3060 if (mdi_component_is_client(tgt_dip, NULL) == MDI_SUCCESS) {
3061 if ((pip = (void *)(sd->sd_private)) == NULL) {
3062 /*
3063 * Very bad news if this occurs. Somehow scsi_vhci has
3064 * lost the pathinfo node for this target.
3065 */
3066 return (DDI_NOT_WELL_FORMED);
3067 }
3068
3069 if (mdi_prop_lookup_int(pip, LUN_PROP, &lun) !=
3070 DDI_PROP_SUCCESS) {
3071 mptsas_log(mpt, CE_WARN, "Get lun property failed\n");
3072 return (DDI_FAILURE);
3073 }
3074
3075 if (mdi_prop_lookup_string(pip, SCSI_ADDR_PROP_TARGET_PORT,
3076 &psas_wwn) == MDI_SUCCESS) {
3077 if (scsi_wwnstr_to_wwn(psas_wwn, &sas_wwn)) {
3078 sas_wwn = 0;
3079 }
3080 (void) mdi_prop_free(psas_wwn);
3081 }
3082 } else {
3083 lun = ddi_prop_get_int(DDI_DEV_T_ANY, tgt_dip,
3084 DDI_PROP_DONTPASS, LUN_PROP, 0);
3085 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, tgt_dip,
3086 DDI_PROP_DONTPASS, SCSI_ADDR_PROP_TARGET_PORT, &psas_wwn) ==
3087 DDI_PROP_SUCCESS) {
3088 if (scsi_wwnstr_to_wwn(psas_wwn, &sas_wwn)) {
3089 sas_wwn = 0;
3090 }
3091 ddi_prop_free(psas_wwn);
3092 } else {
3093 sas_wwn = 0;
3094 }
3095 }
3096
3097 ASSERT((sas_wwn != 0) || (phymask != 0));
3098 addr.mta_wwn = sas_wwn;
3099 addr.mta_phymask = phymask;
3100 mutex_enter(&mpt->m_mutex);
3101 ptgt = refhash_lookup(mpt->m_targets, &addr);
3102 mutex_exit(&mpt->m_mutex);
3103 if (ptgt == NULL) {
3104 mptsas_log(mpt, CE_WARN, "!tgt_init: target doesn't exist or "
3105 "gone already! phymask:%x, saswwn %"PRIx64, phymask,
3106 sas_wwn);
3107 return (DDI_FAILURE);
3108 }
3109 if (hba_tran->tran_tgt_private == NULL) {
3110 tgt_private = kmem_zalloc(sizeof (mptsas_tgt_private_t),
3111 KM_SLEEP);
3112 tgt_private->t_lun = lun;
3113 tgt_private->t_private = ptgt;
3114 hba_tran->tran_tgt_private = tgt_private;
3115 }
3116
3117 if (mdi_component_is_client(tgt_dip, NULL) == MDI_SUCCESS) {
3118 return (DDI_SUCCESS);
3119 }
3120 mutex_enter(&mpt->m_mutex);
3121
3122 if (ptgt->m_deviceinfo &
3123 (MPI2_SAS_DEVICE_INFO_SATA_DEVICE |
3124 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) {
3125 uchar_t *inq89 = NULL;
3126 int inq89_len = 0x238;
3127 int reallen = 0;
3128 int rval = 0;
3129 struct sata_id *sid = NULL;
3130 char model[SATA_ID_MODEL_LEN + 1];
3131 char fw[SATA_ID_FW_LEN + 1];
3132 char *vid, *pid;
3133
3134 mutex_exit(&mpt->m_mutex);
3135 /*
3136 * According SCSI/ATA Translation -2 (SAT-2) revision 01a
3137 * chapter 12.4.2 VPD page 89h includes 512 bytes ATA IDENTIFY
3138 * DEVICE data or ATA IDENTIFY PACKET DEVICE data.
3139 */
3140 inq89 = kmem_zalloc(inq89_len, KM_SLEEP);
3141 rval = mptsas_inquiry(mpt, ptgt, 0, 0x89,
3142 inq89, inq89_len, &reallen, 1);
3143
3144 if (rval != 0) {
3145 if (inq89 != NULL) {
3146 kmem_free(inq89, inq89_len);
3147 }
3148
3149 mptsas_log(mpt, CE_WARN, "!mptsas request inquiry page "
3150 "0x89 for SATA target:%x failed!", ptgt->m_devhdl);
3151 return (DDI_SUCCESS);
3152 }
3153 sid = (void *)(&inq89[60]);
3154
3155 swab(sid->ai_model, model, SATA_ID_MODEL_LEN);
3156 swab(sid->ai_fw, fw, SATA_ID_FW_LEN);
3157
3158 model[SATA_ID_MODEL_LEN] = 0;
3159 fw[SATA_ID_FW_LEN] = 0;
3160
3161 sata_split_model(model, &vid, &pid);
3162
3163 /*
3164 * override SCSA "inquiry-*" properties
3165 */
3166 if (vid)
3167 (void) scsi_device_prop_update_inqstring(sd,
3168 INQUIRY_VENDOR_ID, vid, strlen(vid));
3169 if (pid)
3170 (void) scsi_device_prop_update_inqstring(sd,
3171 INQUIRY_PRODUCT_ID, pid, strlen(pid));
3172 (void) scsi_device_prop_update_inqstring(sd,
3173 INQUIRY_REVISION_ID, fw, strlen(fw));
3174
3175 if (inq89 != NULL) {
3176 kmem_free(inq89, inq89_len);
3177 }
3178 } else {
3179 mutex_exit(&mpt->m_mutex);
3180 }
3181
3182 return (DDI_SUCCESS);
3183 }
3184 /*
3185 * tran_tgt_free(9E) - target device instance deallocation
3186 */
3187 static void
3188 mptsas_scsi_tgt_free(dev_info_t *hba_dip, dev_info_t *tgt_dip,
3189 scsi_hba_tran_t *hba_tran, struct scsi_device *sd)
3190 {
3191 #ifndef __lock_lint
3192 _NOTE(ARGUNUSED(hba_dip, tgt_dip, hba_tran, sd))
3193 #endif
3194
3195 mptsas_tgt_private_t *tgt_private = hba_tran->tran_tgt_private;
3196
3197 if (tgt_private != NULL) {
3198 kmem_free(tgt_private, sizeof (mptsas_tgt_private_t));
3199 hba_tran->tran_tgt_private = NULL;
3200 }
3201 }
3202
3203 /*
3204 * scsi_pkt handling
3205 *
3206 * Visible to the external world via the transport structure.
3207 */
3208
3209 /*
3210 * Notes:
3211 * - transport the command to the addressed SCSI target/lun device
3212 * - normal operation is to schedule the command to be transported,
3213 * and return TRAN_ACCEPT if this is successful.
3214 * - if NO_INTR, tran_start must poll device for command completion
3215 */
3216 static int
3217 mptsas_scsi_start(struct scsi_address *ap, struct scsi_pkt *pkt)
3218 {
3219 #ifndef __lock_lint
3220 _NOTE(ARGUNUSED(ap))
3221 #endif
3222 mptsas_t *mpt = PKT2MPT(pkt);
3223 mptsas_cmd_t *cmd = PKT2CMD(pkt);
3224 int rval;
3225 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
3226
3227 NDBG1(("mptsas_scsi_start: pkt=0x%p", (void *)pkt));
3228 ASSERT(ptgt);
3229 if (ptgt == NULL)
3230 return (TRAN_FATAL_ERROR);
3231
3232 /*
3233 * prepare the pkt before taking mutex.
3234 */
3235 rval = mptsas_prepare_pkt(cmd);
3236 if (rval != TRAN_ACCEPT) {
3237 return (rval);
3238 }
3239
3240 /*
3241 * Send the command to target/lun, however your HBA requires it.
3242 * If busy, return TRAN_BUSY; if there's some other formatting error
3243 * in the packet, return TRAN_BADPKT; otherwise, fall through to the
3244 * return of TRAN_ACCEPT.
3245 *
3246 * Remember that access to shared resources, including the mptsas_t
3247 * data structure and the HBA hardware registers, must be protected
3248 * with mutexes, here and everywhere.
3249 *
3250 * Also remember that at interrupt time, you'll get an argument
3251 * to the interrupt handler which is a pointer to your mptsas_t
3252 * structure; you'll have to remember which commands are outstanding
3253 * and which scsi_pkt is the currently-running command so the
3254 * interrupt handler can refer to the pkt to set completion
3255 * status, call the target driver back through pkt_comp, etc.
3256 *
3257 * If the instance lock is held by other thread, don't spin to wait
3258 * for it. Instead, queue the cmd and next time when the instance lock
3259 * is not held, accept all the queued cmd. A extra tx_waitq is
3260 * introduced to protect the queue.
3261 *
3262 * The polled cmd will not be queud and accepted as usual.
3263 *
3264 * Under the tx_waitq mutex, record whether a thread is draining
3265 * the tx_waitq. An IO requesting thread that finds the instance
3266 * mutex contended appends to the tx_waitq and while holding the
3267 * tx_wait mutex, if the draining flag is not set, sets it and then
3268 * proceeds to spin for the instance mutex. This scheme ensures that
3269 * the last cmd in a burst be processed.
3270 *
3271 * we enable this feature only when the helper threads are enabled,
3272 * at which we think the loads are heavy.
3273 *
3274 * per instance mutex m_tx_waitq_mutex is introduced to protect the
3275 * m_tx_waitqtail, m_tx_waitq, m_tx_draining.
3276 */
3277
3278 if (mpt->m_doneq_thread_n) {
3279 if (mutex_tryenter(&mpt->m_mutex) != 0) {
3280 rval = mptsas_accept_txwq_and_pkt(mpt, cmd);
3281 mutex_exit(&mpt->m_mutex);
3282 } else if (cmd->cmd_pkt_flags & FLAG_NOINTR) {
3283 mutex_enter(&mpt->m_mutex);
3284 rval = mptsas_accept_txwq_and_pkt(mpt, cmd);
3285 mutex_exit(&mpt->m_mutex);
3286 } else {
3287 mutex_enter(&mpt->m_tx_waitq_mutex);
3288 /*
3289 * ptgt->m_dr_flag is protected by m_mutex or
3290 * m_tx_waitq_mutex. In this case, m_tx_waitq_mutex
3291 * is acquired.
3292 */
3293 if (ptgt->m_dr_flag == MPTSAS_DR_INTRANSITION) {
3294 if (cmd->cmd_pkt_flags & FLAG_NOQUEUE) {
3295 /*
3296 * The command should be allowed to
3297 * retry by returning TRAN_BUSY to
3298 * to stall the I/O's which come from
3299 * scsi_vhci since the device/path is
3300 * in unstable state now.
3301 */
3302 mutex_exit(&mpt->m_tx_waitq_mutex);
3303 return (TRAN_BUSY);
3304 } else {
3305 /*
3306 * The device is offline, just fail the
3307 * command by returning
3308 * TRAN_FATAL_ERROR.
3309 */
3310 mutex_exit(&mpt->m_tx_waitq_mutex);
3311 return (TRAN_FATAL_ERROR);
3312 }
3313 }
3314 if (mpt->m_tx_draining) {
3315 cmd->cmd_flags |= CFLAG_TXQ;
3316 *mpt->m_tx_waitqtail = cmd;
3317 mpt->m_tx_waitqtail = &cmd->cmd_linkp;
3318 mutex_exit(&mpt->m_tx_waitq_mutex);
3319 } else { /* drain the queue */
3320 mpt->m_tx_draining = 1;
3321 mutex_exit(&mpt->m_tx_waitq_mutex);
3322 mutex_enter(&mpt->m_mutex);
3323 rval = mptsas_accept_txwq_and_pkt(mpt, cmd);
3324 mutex_exit(&mpt->m_mutex);
3325 }
3326 }
3327 } else {
3328 mutex_enter(&mpt->m_mutex);
3329 /*
3330 * ptgt->m_dr_flag is protected by m_mutex or m_tx_waitq_mutex
3331 * in this case, m_mutex is acquired.
3332 */
3333 if (ptgt->m_dr_flag == MPTSAS_DR_INTRANSITION) {
3334 if (cmd->cmd_pkt_flags & FLAG_NOQUEUE) {
3335 /*
3336 * commands should be allowed to retry by
3337 * returning TRAN_BUSY to stall the I/O's
3338 * which come from scsi_vhci since the device/
3339 * path is in unstable state now.
3340 */
3341 mutex_exit(&mpt->m_mutex);
3342 return (TRAN_BUSY);
3343 } else {
3344 /*
3345 * The device is offline, just fail the
3346 * command by returning TRAN_FATAL_ERROR.
3347 */
3348 mutex_exit(&mpt->m_mutex);
3349 return (TRAN_FATAL_ERROR);
3350 }
3351 }
3352 rval = mptsas_accept_pkt(mpt, cmd);
3353 mutex_exit(&mpt->m_mutex);
3354 }
3355
3356 return (rval);
3357 }
3358
3359 /*
3360 * Accept all the queued cmds(if any) before accept the current one.
3361 */
3362 static int
3363 mptsas_accept_txwq_and_pkt(mptsas_t *mpt, mptsas_cmd_t *cmd)
3364 {
3365 int rval;
3366 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
3367
3368 ASSERT(mutex_owned(&mpt->m_mutex));
3369 /*
3370 * The call to mptsas_accept_tx_waitq() must always be performed
3371 * because that is where mpt->m_tx_draining is cleared.
3372 */
3373 mutex_enter(&mpt->m_tx_waitq_mutex);
3374 mptsas_accept_tx_waitq(mpt);
3375 mutex_exit(&mpt->m_tx_waitq_mutex);
3376 /*
3377 * ptgt->m_dr_flag is protected by m_mutex or m_tx_waitq_mutex
3378 * in this case, m_mutex is acquired.
3379 */
3380 if (ptgt->m_dr_flag == MPTSAS_DR_INTRANSITION) {
3381 if (cmd->cmd_pkt_flags & FLAG_NOQUEUE) {
3382 /*
3383 * The command should be allowed to retry by returning
3384 * TRAN_BUSY to stall the I/O's which come from
3385 * scsi_vhci since the device/path is in unstable state
3386 * now.
3387 */
3388 return (TRAN_BUSY);
3389 } else {
3390 /*
3391 * The device is offline, just fail the command by
3392 * return TRAN_FATAL_ERROR.
3393 */
3394 return (TRAN_FATAL_ERROR);
3395 }
3396 }
3397 rval = mptsas_accept_pkt(mpt, cmd);
3398
3399 return (rval);
3400 }
3401
3402 static int
3403 mptsas_accept_pkt(mptsas_t *mpt, mptsas_cmd_t *cmd)
3404 {
3405 int rval = TRAN_ACCEPT;
3406 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
3407
3408 NDBG1(("mptsas_accept_pkt: cmd=0x%p", (void *)cmd));
3409
3410 ASSERT(mutex_owned(&mpt->m_mutex));
3411
3412 if ((cmd->cmd_flags & CFLAG_PREPARED) == 0) {
3413 rval = mptsas_prepare_pkt(cmd);
3414 if (rval != TRAN_ACCEPT) {
3415 cmd->cmd_flags &= ~CFLAG_TRANFLAG;
3416 return (rval);
3417 }
3418 }
3419
3420 /*
3421 * reset the throttle if we were draining
3422 */
3423 if ((ptgt->m_t_ncmds == 0) &&
3424 (ptgt->m_t_throttle == DRAIN_THROTTLE)) {
3425 NDBG23(("reset throttle"));
3426 ASSERT(ptgt->m_reset_delay == 0);
3427 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE);
3428 }
3429
3430 /*
3431 * If HBA is being reset, the DevHandles are being re-initialized,
3432 * which means that they could be invalid even if the target is still
3433 * attached. Check if being reset and if DevHandle is being
3434 * re-initialized. If this is the case, return BUSY so the I/O can be
3435 * retried later.
3436 */
3437 mutex_enter(&mpt->m_taskmgmt_mutex);
3438 if ((ptgt->m_devhdl == MPTSAS_INVALID_DEVHDL) && mpt->m_in_reset) {
3439 mptsas_set_pkt_reason(mpt, cmd, CMD_RESET, STAT_BUS_RESET);
3440 if (cmd->cmd_flags & CFLAG_TXQ) {
3441 mptsas_doneq_add(mpt, cmd);
3442 mptsas_doneq_empty(mpt);
3443 mutex_exit(&mpt->m_taskmgmt_mutex);
3444 return (rval);
3445 } else {
3446 mutex_exit(&mpt->m_taskmgmt_mutex);
3447 return (TRAN_BUSY);
3448 }
3449 }
3450 mutex_exit(&mpt->m_taskmgmt_mutex);
3451
3452 /*
3453 * If device handle has already been invalidated, just
3454 * fail the command. In theory, command from scsi_vhci
3455 * client is impossible send down command with invalid
3456 * devhdl since devhdl is set after path offline, target
3457 * driver is not suppose to select a offlined path.
3458 */
3459 if (ptgt->m_devhdl == MPTSAS_INVALID_DEVHDL) {
3460 NDBG3(("rejecting command, it might because invalid devhdl "
3461 "request."));
3462 mptsas_set_pkt_reason(mpt, cmd, CMD_DEV_GONE, STAT_TERMINATED);
3463 if (cmd->cmd_flags & CFLAG_TXQ) {
3464 mptsas_doneq_add(mpt, cmd);
3465 mptsas_doneq_empty(mpt);
3466 return (rval);
3467 } else {
3468 return (TRAN_FATAL_ERROR);
3469 }
3470 }
3471 /*
3472 * The first case is the normal case. mpt gets a command from the
3473 * target driver and starts it.
3474 * Since SMID 0 is reserved and the TM slot is reserved, the actual max
3475 * commands is m_max_requests - 2.
3476 */
3477 if ((mpt->m_ncmds <= (mpt->m_max_requests - 2)) &&
3478 (ptgt->m_t_throttle > HOLD_THROTTLE) &&
3479 (ptgt->m_t_ncmds < ptgt->m_t_throttle) &&
3480 (ptgt->m_reset_delay == 0) &&
3481 (ptgt->m_t_nwait == 0) &&
3482 ((cmd->cmd_pkt_flags & FLAG_NOINTR) == 0)) {
3483 if (mptsas_save_cmd(mpt, cmd) == TRUE) {
3484 (void) mptsas_start_cmd(mpt, cmd);
3485 } else {
3486 mptsas_waitq_add(mpt, cmd);
3487 }
3488 } else {
3489 /*
3490 * Add this pkt to the work queue
3491 */
3492 mptsas_waitq_add(mpt, cmd);
3493
3494 if (cmd->cmd_pkt_flags & FLAG_NOINTR) {
3495 (void) mptsas_poll(mpt, cmd, MPTSAS_POLL_TIME);
3496
3497 /*
3498 * Only flush the doneq if this is not a TM
3499 * cmd. For TM cmds the flushing of the
3500 * doneq will be done in those routines.
3501 */
3502 if ((cmd->cmd_flags & CFLAG_TM_CMD) == 0) {
3503 mptsas_doneq_empty(mpt);
3504 }
3505 }
3506 }
3507 return (rval);
3508 }
3509
3510 int
3511 mptsas_save_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd)
3512 {
3513 mptsas_slots_t *slots = mpt->m_active;
3514 uint_t slot, start_rotor;
3515 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
3516
3517 ASSERT(MUTEX_HELD(&mpt->m_mutex));
3518
3519 /*
3520 * Account for reserved TM request slot and reserved SMID of 0.
3521 */
3522 ASSERT(slots->m_n_normal == (mpt->m_max_requests - 2));
3523
3524 /*
3525 * Find the next available slot, beginning at m_rotor. If no slot is
3526 * available, we'll return FALSE to indicate that. This mechanism
3527 * considers only the normal slots, not the reserved slot 0 nor the
3528 * task management slot m_n_normal + 1. The rotor is left to point to
3529 * the normal slot after the one we select, unless we select the last
3530 * normal slot in which case it returns to slot 1.
3531 */
3532 start_rotor = slots->m_rotor;
3533 do {
3534 slot = slots->m_rotor++;
3535 if (slots->m_rotor > slots->m_n_normal)
3536 slots->m_rotor = 1;
3537
3538 if (slots->m_rotor == start_rotor)
3539 break;
3540 } while (slots->m_slot[slot] != NULL);
3541
3542 if (slots->m_slot[slot] != NULL)
3543 return (FALSE);
3544
3545 ASSERT(slot != 0 && slot <= slots->m_n_normal);
3546
3547 cmd->cmd_slot = slot;
3548 slots->m_slot[slot] = cmd;
3549 mpt->m_ncmds++;
3550
3551 /*
3552 * only increment per target ncmds if this is not a
3553 * command that has no target associated with it (i.e. a
3554 * event acknoledgment)
3555 */
3556 if ((cmd->cmd_flags & CFLAG_CMDIOC) == 0) {
3557 /*
3558 * Expiration time is set in mptsas_start_cmd
3559 */
3560 ptgt->m_t_ncmds++;
3561 cmd->cmd_active_expiration = 0;
3562 } else {
3563 /*
3564 * Initialize expiration time for passthrough commands,
3565 */
3566 cmd->cmd_active_expiration = gethrtime() +
3567 (hrtime_t)cmd->cmd_pkt->pkt_time * NANOSEC;
3568 }
3569 return (TRUE);
3570 }
3571
3572 /*
3573 * prepare the pkt:
3574 * the pkt may have been resubmitted or just reused so
3575 * initialize some fields and do some checks.
3576 */
3577 static int
3578 mptsas_prepare_pkt(mptsas_cmd_t *cmd)
3579 {
3580 struct scsi_pkt *pkt = CMD2PKT(cmd);
3581
3582 NDBG1(("mptsas_prepare_pkt: cmd=0x%p", (void *)cmd));
3583
3584 /*
3585 * Reinitialize some fields that need it; the packet may
3586 * have been resubmitted
3587 */
3588 pkt->pkt_reason = CMD_CMPLT;
3589 pkt->pkt_state = 0;
3590 pkt->pkt_statistics = 0;
3591 pkt->pkt_resid = 0;
3592 cmd->cmd_age = 0;
3593 cmd->cmd_pkt_flags = pkt->pkt_flags;
3594
3595 /*
3596 * zero status byte.
3597 */
3598 *(pkt->pkt_scbp) = 0;
3599
3600 if (cmd->cmd_flags & CFLAG_DMAVALID) {
3601 pkt->pkt_resid = cmd->cmd_dmacount;
3602
3603 /*
3604 * consistent packets need to be sync'ed first
3605 * (only for data going out)
3606 */
3607 if ((cmd->cmd_flags & CFLAG_CMDIOPB) &&
3608 (cmd->cmd_flags & CFLAG_DMASEND)) {
3609 (void) ddi_dma_sync(cmd->cmd_dmahandle, 0, 0,
3610 DDI_DMA_SYNC_FORDEV);
3611 }
3612 }
3613
3614 cmd->cmd_flags =
3615 (cmd->cmd_flags & ~(CFLAG_TRANFLAG)) |
3616 CFLAG_PREPARED | CFLAG_IN_TRANSPORT;
3617
3618 return (TRAN_ACCEPT);
3619 }
3620
3621 /*
3622 * tran_init_pkt(9E) - allocate scsi_pkt(9S) for command
3623 *
3624 * One of three possibilities:
3625 * - allocate scsi_pkt
3626 * - allocate scsi_pkt and DMA resources
3627 * - allocate DMA resources to an already-allocated pkt
3628 */
3629 static struct scsi_pkt *
3630 mptsas_scsi_init_pkt(struct scsi_address *ap, struct scsi_pkt *pkt,
3631 struct buf *bp, int cmdlen, int statuslen, int tgtlen, int flags,
3632 int (*callback)(), caddr_t arg)
3633 {
3634 mptsas_cmd_t *cmd, *new_cmd;
3635 mptsas_t *mpt = ADDR2MPT(ap);
3636 uint_t oldcookiec;
3637 mptsas_target_t *ptgt = NULL;
3638 int rval;
3639 mptsas_tgt_private_t *tgt_private;
3640 int kf;
3641
3642 kf = (callback == SLEEP_FUNC)? KM_SLEEP: KM_NOSLEEP;
3643
3644 tgt_private = (mptsas_tgt_private_t *)ap->a_hba_tran->
3645 tran_tgt_private;
3646 ASSERT(tgt_private != NULL);
3647 if (tgt_private == NULL) {
3648 return (NULL);
3649 }
3650 ptgt = tgt_private->t_private;
3651 ASSERT(ptgt != NULL);
3652 if (ptgt == NULL)
3653 return (NULL);
3654 ap->a_target = ptgt->m_devhdl;
3655 ap->a_lun = tgt_private->t_lun;
3656
3657 ASSERT(callback == NULL_FUNC || callback == SLEEP_FUNC);
3658 #ifdef MPTSAS_TEST_EXTRN_ALLOC
3659 statuslen *= 100; tgtlen *= 4;
3660 #endif
3661 NDBG3(("mptsas_scsi_init_pkt:\n"
3662 "\ttgt=%d in=0x%p bp=0x%p clen=%d slen=%d tlen=%d flags=%x",
3663 ap->a_target, (void *)pkt, (void *)bp,
3664 cmdlen, statuslen, tgtlen, flags));
3665
3666 /*
3667 * Allocate the new packet.
3668 */
3669 if (pkt == NULL) {
3670 ddi_dma_handle_t save_dma_handle;
3671
3672 cmd = kmem_cache_alloc(mpt->m_kmem_cache, kf);
3673 if (cmd == NULL)
3674 return (NULL);
3675
3676 save_dma_handle = cmd->cmd_dmahandle;
3677 bzero(cmd, sizeof (*cmd) + scsi_pkt_size());
3678 cmd->cmd_dmahandle = save_dma_handle;
3679
3680 pkt = (void *)((uchar_t *)cmd +
3681 sizeof (struct mptsas_cmd));
3682 pkt->pkt_ha_private = (opaque_t)cmd;
3683 pkt->pkt_address = *ap;
3684 pkt->pkt_private = (opaque_t)cmd->cmd_pkt_private;
3685 pkt->pkt_scbp = (opaque_t)&cmd->cmd_scb;
3686 pkt->pkt_cdbp = (opaque_t)&cmd->cmd_cdb;
3687 cmd->cmd_pkt = (struct scsi_pkt *)pkt;
3688 cmd->cmd_cdblen = (uchar_t)cmdlen;
3689 cmd->cmd_scblen = statuslen;
3690 cmd->cmd_rqslen = SENSE_LENGTH;
3691 cmd->cmd_tgt_addr = ptgt;
3692
3693 if ((cmdlen > sizeof (cmd->cmd_cdb)) ||
3694 (tgtlen > PKT_PRIV_LEN) ||
3695 (statuslen > EXTCMDS_STATUS_SIZE)) {
3696 int failure;
3697
3698 /*
3699 * We are going to allocate external packet space which
3700 * might include the sense data buffer for DMA so we
3701 * need to increase the reference counter here. In a
3702 * case the HBA is in reset we just simply free the
3703 * allocated packet and bail out.
3704 */
3705 mutex_enter(&mpt->m_mutex);
3706 mutex_enter(&mpt->m_taskmgmt_mutex);
3707 if (mpt->m_in_reset == TRUE) {
3708 mutex_exit(&mpt->m_taskmgmt_mutex);
3709 mutex_exit(&mpt->m_mutex);
3710
3711 cmd->cmd_flags = CFLAG_FREE;
3712 kmem_cache_free(mpt->m_kmem_cache, cmd);
3713 return (NULL);
3714 }
3715 mutex_exit(&mpt->m_taskmgmt_mutex);
3716 mpt->m_extreq_sense_refcount++;
3717 ASSERT(mpt->m_extreq_sense_refcount > 0);
3718 mutex_exit(&mpt->m_mutex);
3719
3720 /*
3721 * if extern alloc fails, all will be
3722 * deallocated, including cmd
3723 */
3724 failure = mptsas_pkt_alloc_extern(mpt, cmd,
3725 cmdlen, tgtlen, statuslen, kf);
3726
3727 if (failure != 0 || cmd->cmd_extrqslen == 0) {
3728 /*
3729 * If the external packet space allocation
3730 * failed, or we didn't allocated the sense
3731 * data buffer for DMA we need to decrease the
3732 * reference counter.
3733 */
3734 mutex_enter(&mpt->m_mutex);
3735 ASSERT(mpt->m_extreq_sense_refcount > 0);
3736 mpt->m_extreq_sense_refcount--;
3737 if (mpt->m_extreq_sense_refcount == 0)
3738 cv_broadcast(
3739 &mpt->m_extreq_sense_refcount_cv);
3740 mutex_exit(&mpt->m_mutex);
3741
3742 if (failure != 0) {
3743 /*
3744 * if extern allocation fails, it will
3745 * deallocate the new pkt as well
3746 */
3747 return (NULL);
3748 }
3749 }
3750 }
3751 new_cmd = cmd;
3752
3753 } else {
3754 cmd = PKT2CMD(pkt);
3755 new_cmd = NULL;
3756 }
3757
3758
3759 /* grab cmd->cmd_cookiec here as oldcookiec */
3760
3761 oldcookiec = cmd->cmd_cookiec;
3762
3763 /*
3764 * If the dma was broken up into PARTIAL transfers cmd_nwin will be
3765 * greater than 0 and we'll need to grab the next dma window
3766 */
3767 /*
3768 * SLM-not doing extra command frame right now; may add later
3769 */
3770
3771 if (cmd->cmd_nwin > 0) {
3772
3773 /*
3774 * Make sure we havn't gone past the the total number
3775 * of windows
3776 */
3777 if (++cmd->cmd_winindex >= cmd->cmd_nwin) {
3778 return (NULL);
3779 }
3780 if (ddi_dma_getwin(cmd->cmd_dmahandle, cmd->cmd_winindex,
3781 &cmd->cmd_dma_offset, &cmd->cmd_dma_len,
3782 &cmd->cmd_cookie, &cmd->cmd_cookiec) == DDI_FAILURE) {
3783 return (NULL);
3784 }
3785 goto get_dma_cookies;
3786 }
3787
3788
3789 if (flags & PKT_XARQ) {
3790 cmd->cmd_flags |= CFLAG_XARQ;
3791 }
3792
3793 /*
3794 * DMA resource allocation. This version assumes your
3795 * HBA has some sort of bus-mastering or onboard DMA capability, with a
3796 * scatter-gather list of length MPTSAS_MAX_DMA_SEGS, as given in the
3797 * ddi_dma_attr_t structure and passed to scsi_impl_dmaget.
3798 */
3799 if (bp && (bp->b_bcount != 0) &&
3800 (cmd->cmd_flags & CFLAG_DMAVALID) == 0) {
3801
3802 int cnt, dma_flags;
3803 mptti_t *dmap; /* ptr to the S/G list */
3804
3805 /*
3806 * Set up DMA memory and position to the next DMA segment.
3807 */
3808 ASSERT(cmd->cmd_dmahandle != NULL);
3809
3810 if (bp->b_flags & B_READ) {
3811 dma_flags = DDI_DMA_READ;
3812 cmd->cmd_flags &= ~CFLAG_DMASEND;
3813 } else {
3814 dma_flags = DDI_DMA_WRITE;
3815 cmd->cmd_flags |= CFLAG_DMASEND;
3816 }
3817 if (flags & PKT_CONSISTENT) {
3818 cmd->cmd_flags |= CFLAG_CMDIOPB;
3819 dma_flags |= DDI_DMA_CONSISTENT;
3820 }
3821
3822 if (flags & PKT_DMA_PARTIAL) {
3823 dma_flags |= DDI_DMA_PARTIAL;
3824 }
3825
3826 /*
3827 * workaround for byte hole issue on psycho and
3828 * schizo pre 2.1
3829 */
3830 if ((bp->b_flags & B_READ) && ((bp->b_flags &
3831 (B_PAGEIO|B_REMAPPED)) != B_PAGEIO) &&
3832 ((uintptr_t)bp->b_un.b_addr & 0x7)) {
3833 dma_flags |= DDI_DMA_CONSISTENT;
3834 }
3835
3836 rval = ddi_dma_buf_bind_handle(cmd->cmd_dmahandle, bp,
3837 dma_flags, callback, arg,
3838 &cmd->cmd_cookie, &cmd->cmd_cookiec);
3839 if (rval == DDI_DMA_PARTIAL_MAP) {
3840 (void) ddi_dma_numwin(cmd->cmd_dmahandle,
3841 &cmd->cmd_nwin);
3842 cmd->cmd_winindex = 0;
3843 (void) ddi_dma_getwin(cmd->cmd_dmahandle,
3844 cmd->cmd_winindex, &cmd->cmd_dma_offset,
3845 &cmd->cmd_dma_len, &cmd->cmd_cookie,
3846 &cmd->cmd_cookiec);
3847 } else if (rval && (rval != DDI_DMA_MAPPED)) {
3848 switch (rval) {
3849 case DDI_DMA_NORESOURCES:
3850 bioerror(bp, 0);
3851 break;
3852 case DDI_DMA_BADATTR:
3853 case DDI_DMA_NOMAPPING:
3854 bioerror(bp, EFAULT);
3855 break;
3856 case DDI_DMA_TOOBIG:
3857 default:
3858 bioerror(bp, EINVAL);
3859 break;
3860 }
3861 cmd->cmd_flags &= ~CFLAG_DMAVALID;
3862 if (new_cmd) {
3863 mptsas_scsi_destroy_pkt(ap, pkt);
3864 }
3865 return ((struct scsi_pkt *)NULL);
3866 }
3867
3868 get_dma_cookies:
3869 cmd->cmd_flags |= CFLAG_DMAVALID;
3870 ASSERT(cmd->cmd_cookiec > 0);
3871
3872 if (cmd->cmd_cookiec > MPTSAS_MAX_CMD_SEGS) {
3873 mptsas_log(mpt, CE_NOTE, "large cookiec received %d\n",
3874 cmd->cmd_cookiec);
3875 bioerror(bp, EINVAL);
3876 if (new_cmd) {
3877 mptsas_scsi_destroy_pkt(ap, pkt);
3878 }
3879 return ((struct scsi_pkt *)NULL);
3880 }
3881
3882 /*
3883 * Allocate extra SGL buffer if needed.
3884 */
3885 if ((cmd->cmd_cookiec > MPTSAS_MAX_FRAME_SGES64(mpt)) &&
3886 (cmd->cmd_extra_frames == NULL)) {
3887 if (mptsas_alloc_extra_sgl_frame(mpt, cmd) ==
3888 DDI_FAILURE) {
3889 mptsas_log(mpt, CE_WARN, "MPT SGL mem alloc "
3890 "failed");
3891 bioerror(bp, ENOMEM);
3892 if (new_cmd) {
3893 mptsas_scsi_destroy_pkt(ap, pkt);
3894 }
3895 return ((struct scsi_pkt *)NULL);
3896 }
3897 }
3898
3899 /*
3900 * Always use scatter-gather transfer
3901 * Use the loop below to store physical addresses of
3902 * DMA segments, from the DMA cookies, into your HBA's
3903 * scatter-gather list.
3904 * We need to ensure we have enough kmem alloc'd
3905 * for the sg entries since we are no longer using an
3906 * array inside mptsas_cmd_t.
3907 *
3908 * We check cmd->cmd_cookiec against oldcookiec so
3909 * the scatter-gather list is correctly allocated
3910 */
3911
3912 if (oldcookiec != cmd->cmd_cookiec) {
3913 if (cmd->cmd_sg != (mptti_t *)NULL) {
3914 kmem_free(cmd->cmd_sg, sizeof (mptti_t) *
3915 oldcookiec);
3916 cmd->cmd_sg = NULL;
3917 }
3918 }
3919
3920 if (cmd->cmd_sg == (mptti_t *)NULL) {
3921 cmd->cmd_sg = kmem_alloc((size_t)(sizeof (mptti_t)*
3922 cmd->cmd_cookiec), kf);
3923
3924 if (cmd->cmd_sg == (mptti_t *)NULL) {
3925 mptsas_log(mpt, CE_WARN,
3926 "unable to kmem_alloc enough memory "
3927 "for scatter/gather list");
3928 /*
3929 * if we have an ENOMEM condition we need to behave
3930 * the same way as the rest of this routine
3931 */
3932
3933 bioerror(bp, ENOMEM);
3934 if (new_cmd) {
3935 mptsas_scsi_destroy_pkt(ap, pkt);
3936 }
3937 return ((struct scsi_pkt *)NULL);
3938 }
3939 }
3940
3941 dmap = cmd->cmd_sg;
3942
3943 ASSERT(cmd->cmd_cookie.dmac_size != 0);
3944
3945 /*
3946 * store the first segment into the S/G list
3947 */
3948 dmap->count = cmd->cmd_cookie.dmac_size;
3949 dmap->addr.address64.Low = (uint32_t)
3950 (cmd->cmd_cookie.dmac_laddress & 0xffffffffull);
3951 dmap->addr.address64.High = (uint32_t)
3952 (cmd->cmd_cookie.dmac_laddress >> 32);
3953
3954 /*
3955 * dmacount counts the size of the dma for this window
3956 * (if partial dma is being used). totaldmacount
3957 * keeps track of the total amount of dma we have
3958 * transferred for all the windows (needed to calculate
3959 * the resid value below).
3960 */
3961 cmd->cmd_dmacount = cmd->cmd_cookie.dmac_size;
3962 cmd->cmd_totaldmacount += cmd->cmd_cookie.dmac_size;
3963
3964 /*
3965 * We already stored the first DMA scatter gather segment,
3966 * start at 1 if we need to store more.
3967 */
3968 for (cnt = 1; cnt < cmd->cmd_cookiec; cnt++) {
3969 /*
3970 * Get next DMA cookie
3971 */
3972 ddi_dma_nextcookie(cmd->cmd_dmahandle,
3973 &cmd->cmd_cookie);
3974 dmap++;
3975
3976 cmd->cmd_dmacount += cmd->cmd_cookie.dmac_size;
3977 cmd->cmd_totaldmacount += cmd->cmd_cookie.dmac_size;
3978
3979 /*
3980 * store the segment parms into the S/G list
3981 */
3982 dmap->count = cmd->cmd_cookie.dmac_size;
3983 dmap->addr.address64.Low = (uint32_t)
3984 (cmd->cmd_cookie.dmac_laddress & 0xffffffffull);
3985 dmap->addr.address64.High = (uint32_t)
3986 (cmd->cmd_cookie.dmac_laddress >> 32);
3987 }
3988
3989 /*
3990 * If this was partially allocated we set the resid
3991 * the amount of data NOT transferred in this window
3992 * If there is only one window, the resid will be 0
3993 */
3994 pkt->pkt_resid = (bp->b_bcount - cmd->cmd_totaldmacount);
3995 NDBG3(("mptsas_scsi_init_pkt: cmd_dmacount=%d.",
3996 cmd->cmd_dmacount));
3997 }
3998 return (pkt);
3999 }
4000
4001 /*
4002 * tran_destroy_pkt(9E) - scsi_pkt(9s) deallocation
4003 *
4004 * Notes:
4005 * - also frees DMA resources if allocated
4006 * - implicit DMA synchonization
4007 */
4008 static void
4009 mptsas_scsi_destroy_pkt(struct scsi_address *ap, struct scsi_pkt *pkt)
4010 {
4011 mptsas_cmd_t *cmd = PKT2CMD(pkt);
4012 mptsas_t *mpt = ADDR2MPT(ap);
4013
4014 NDBG3(("mptsas_scsi_destroy_pkt: target=%d pkt=0x%p",
4015 ap->a_target, (void *)pkt));
4016
4017 if (cmd->cmd_flags & CFLAG_DMAVALID) {
4018 (void) ddi_dma_unbind_handle(cmd->cmd_dmahandle);
4019 cmd->cmd_flags &= ~CFLAG_DMAVALID;
4020 }
4021
4022 if (cmd->cmd_sg) {
4023 kmem_free(cmd->cmd_sg, sizeof (mptti_t) * cmd->cmd_cookiec);
4024 cmd->cmd_sg = NULL;
4025 }
4026
4027 mptsas_free_extra_sgl_frame(mpt, cmd);
4028
4029 if ((cmd->cmd_flags &
4030 (CFLAG_FREE | CFLAG_CDBEXTERN | CFLAG_PRIVEXTERN |
4031 CFLAG_SCBEXTERN)) == 0) {
4032 cmd->cmd_flags = CFLAG_FREE;
4033 kmem_cache_free(mpt->m_kmem_cache, (void *)cmd);
4034 } else {
4035 boolean_t extrqslen = cmd->cmd_extrqslen != 0;
4036
4037 mptsas_pkt_destroy_extern(mpt, cmd);
4038
4039 /*
4040 * If the packet had the sense data buffer for DMA allocated we
4041 * need to decrease the reference counter.
4042 */
4043 if (extrqslen) {
4044 mutex_enter(&mpt->m_mutex);
4045 ASSERT(mpt->m_extreq_sense_refcount > 0);
4046 mpt->m_extreq_sense_refcount--;
4047 if (mpt->m_extreq_sense_refcount == 0)
4048 cv_broadcast(&mpt->m_extreq_sense_refcount_cv);
4049 mutex_exit(&mpt->m_mutex);
4050 }
4051 }
4052 }
4053
4054 /*
4055 * kmem cache constructor and destructor:
4056 * When constructing, we bzero the cmd and allocate the dma handle
4057 * When destructing, just free the dma handle
4058 */
4059 static int
4060 mptsas_kmem_cache_constructor(void *buf, void *cdrarg, int kmflags)
4061 {
4062 mptsas_cmd_t *cmd = buf;
4063 mptsas_t *mpt = cdrarg;
4064 int (*callback)(caddr_t);
4065
4066 callback = (kmflags == KM_SLEEP)? DDI_DMA_SLEEP: DDI_DMA_DONTWAIT;
4067
4068 NDBG4(("mptsas_kmem_cache_constructor"));
4069
4070 /*
4071 * allocate a dma handle
4072 */
4073 if ((ddi_dma_alloc_handle(mpt->m_dip, &mpt->m_io_dma_attr, callback,
4074 NULL, &cmd->cmd_dmahandle)) != DDI_SUCCESS) {
4075 cmd->cmd_dmahandle = NULL;
4076 return (-1);
4077 }
4078 return (0);
4079 }
4080
4081 static void
4082 mptsas_kmem_cache_destructor(void *buf, void *cdrarg)
4083 {
4084 #ifndef __lock_lint
4085 _NOTE(ARGUNUSED(cdrarg))
4086 #endif
4087 mptsas_cmd_t *cmd = buf;
4088
4089 NDBG4(("mptsas_kmem_cache_destructor"));
4090
4091 if (cmd->cmd_dmahandle) {
4092 ddi_dma_free_handle(&cmd->cmd_dmahandle);
4093 cmd->cmd_dmahandle = NULL;
4094 }
4095 }
4096
4097 static int
4098 mptsas_cache_frames_constructor(void *buf, void *cdrarg, int kmflags)
4099 {
4100 mptsas_cache_frames_t *p = buf;
4101 mptsas_t *mpt = cdrarg;
4102 ddi_dma_attr_t frame_dma_attr;
4103 size_t mem_size, alloc_len;
4104 ddi_dma_cookie_t cookie;
4105 uint_t ncookie;
4106 int (*callback)(caddr_t) = (kmflags == KM_SLEEP)
4107 ? DDI_DMA_SLEEP: DDI_DMA_DONTWAIT;
4108
4109 frame_dma_attr = mpt->m_msg_dma_attr;
4110 frame_dma_attr.dma_attr_align = 0x10;
4111 frame_dma_attr.dma_attr_sgllen = 1;
4112
4113 if (ddi_dma_alloc_handle(mpt->m_dip, &frame_dma_attr, callback, NULL,
4114 &p->m_dma_hdl) != DDI_SUCCESS) {
4115 mptsas_log(mpt, CE_WARN, "Unable to allocate dma handle for"
4116 " extra SGL.");
4117 return (DDI_FAILURE);
4118 }
4119
4120 mem_size = (mpt->m_max_request_frames - 1) * mpt->m_req_frame_size;
4121
4122 if (ddi_dma_mem_alloc(p->m_dma_hdl, mem_size, &mpt->m_dev_acc_attr,
4123 DDI_DMA_CONSISTENT, callback, NULL, (caddr_t *)&p->m_frames_addr,
4124 &alloc_len, &p->m_acc_hdl) != DDI_SUCCESS) {
4125 ddi_dma_free_handle(&p->m_dma_hdl);
4126 p->m_dma_hdl = NULL;
4127 mptsas_log(mpt, CE_WARN, "Unable to allocate dma memory for"
4128 " extra SGL.");
4129 return (DDI_FAILURE);
4130 }
4131
4132 if (ddi_dma_addr_bind_handle(p->m_dma_hdl, NULL, p->m_frames_addr,
4133 alloc_len, DDI_DMA_RDWR | DDI_DMA_CONSISTENT, callback, NULL,
4134 &cookie, &ncookie) != DDI_DMA_MAPPED) {
4135 (void) ddi_dma_mem_free(&p->m_acc_hdl);
4136 ddi_dma_free_handle(&p->m_dma_hdl);
4137 p->m_dma_hdl = NULL;
4138 mptsas_log(mpt, CE_WARN, "Unable to bind DMA resources for"
4139 " extra SGL");
4140 return (DDI_FAILURE);
4141 }
4142
4143 /*
4144 * Store the SGL memory address. This chip uses this
4145 * address to dma to and from the driver. The second
4146 * address is the address mpt uses to fill in the SGL.
4147 */
4148 p->m_phys_addr = cookie.dmac_laddress;
4149
4150 return (DDI_SUCCESS);
4151 }
4152
4153 static void
4154 mptsas_cache_frames_destructor(void *buf, void *cdrarg)
4155 {
4156 #ifndef __lock_lint
4157 _NOTE(ARGUNUSED(cdrarg))
4158 #endif
4159 mptsas_cache_frames_t *p = buf;
4160 if (p->m_dma_hdl != NULL) {
4161 (void) ddi_dma_unbind_handle(p->m_dma_hdl);
4162 (void) ddi_dma_mem_free(&p->m_acc_hdl);
4163 ddi_dma_free_handle(&p->m_dma_hdl);
4164 p->m_phys_addr = NULL;
4165 p->m_frames_addr = NULL;
4166 p->m_dma_hdl = NULL;
4167 p->m_acc_hdl = NULL;
4168 }
4169
4170 }
4171
4172 /*
4173 * Figure out if we need to use a different method for the request
4174 * sense buffer and allocate from the map if necessary.
4175 */
4176 static boolean_t
4177 mptsas_cmdarqsize(mptsas_t *mpt, mptsas_cmd_t *cmd, size_t senselength, int kf)
4178 {
4179 if (senselength > mpt->m_req_sense_size) {
4180 unsigned long i;
4181
4182 /* Sense length is limited to an 8 bit value in MPI Spec. */
4183 if (senselength > 255)
4184 senselength = 255;
4185 cmd->cmd_extrqschunks = (senselength +
4186 (mpt->m_req_sense_size - 1))/mpt->m_req_sense_size;
4187 i = (kf == KM_SLEEP ? rmalloc_wait : rmalloc)
4188 (mpt->m_erqsense_map, cmd->cmd_extrqschunks);
4189
4190 if (i == 0)
4191 return (B_FALSE);
4192
4193 cmd->cmd_extrqslen = (uint16_t)senselength;
4194 cmd->cmd_extrqsidx = i - 1;
4195 cmd->cmd_arq_buf = mpt->m_extreq_sense +
4196 (cmd->cmd_extrqsidx * mpt->m_req_sense_size);
4197 } else {
4198 cmd->cmd_rqslen = (uchar_t)senselength;
4199 }
4200
4201 return (B_TRUE);
4202 }
4203
4204 /*
4205 * allocate and deallocate external pkt space (ie. not part of mptsas_cmd)
4206 * for non-standard length cdb, pkt_private, status areas
4207 * if allocation fails, then deallocate all external space and the pkt
4208 */
4209 /* ARGSUSED */
4210 static int
4211 mptsas_pkt_alloc_extern(mptsas_t *mpt, mptsas_cmd_t *cmd,
4212 int cmdlen, int tgtlen, int statuslen, int kf)
4213 {
4214 caddr_t cdbp, scbp, tgt;
4215
4216 NDBG3(("mptsas_pkt_alloc_extern: "
4217 "cmd=0x%p cmdlen=%d tgtlen=%d statuslen=%d kf=%x",
4218 (void *)cmd, cmdlen, tgtlen, statuslen, kf));
4219
4220 tgt = cdbp = scbp = NULL;
4221 cmd->cmd_scblen = statuslen;
4222 cmd->cmd_privlen = (uchar_t)tgtlen;
4223
4224 if (cmdlen > sizeof (cmd->cmd_cdb)) {
4225 if ((cdbp = kmem_zalloc((size_t)cmdlen, kf)) == NULL) {
4226 goto fail;
4227 }
4228 cmd->cmd_pkt->pkt_cdbp = (opaque_t)cdbp;
4229 cmd->cmd_flags |= CFLAG_CDBEXTERN;
4230 }
4231 if (tgtlen > PKT_PRIV_LEN) {
4232 if ((tgt = kmem_zalloc((size_t)tgtlen, kf)) == NULL) {
4233 goto fail;
4234 }
4235 cmd->cmd_flags |= CFLAG_PRIVEXTERN;
4236 cmd->cmd_pkt->pkt_private = tgt;
4237 }
4238 if (statuslen > EXTCMDS_STATUS_SIZE) {
4239 if ((scbp = kmem_zalloc((size_t)statuslen, kf)) == NULL) {
4240 goto fail;
4241 }
4242 cmd->cmd_flags |= CFLAG_SCBEXTERN;
4243 cmd->cmd_pkt->pkt_scbp = (opaque_t)scbp;
4244
4245 /* allocate sense data buf for DMA */
4246 if (mptsas_cmdarqsize(mpt, cmd, statuslen -
4247 MPTSAS_GET_ITEM_OFF(struct scsi_arq_status, sts_sensedata),
4248 kf) == B_FALSE)
4249 goto fail;
4250 }
4251 return (0);
4252 fail:
4253 mptsas_pkt_destroy_extern(mpt, cmd);
4254 return (1);
4255 }
4256
4257 /*
4258 * deallocate external pkt space and deallocate the pkt
4259 */
4260 static void
4261 mptsas_pkt_destroy_extern(mptsas_t *mpt, mptsas_cmd_t *cmd)
4262 {
4263 NDBG3(("mptsas_pkt_destroy_extern: cmd=0x%p", (void *)cmd));
4264
4265 if (cmd->cmd_flags & CFLAG_FREE) {
4266 mptsas_log(mpt, CE_PANIC,
4267 "mptsas_pkt_destroy_extern: freeing free packet");
4268 _NOTE(NOT_REACHED)
4269 /* NOTREACHED */
4270 }
4271 if (cmd->cmd_extrqslen != 0) {
4272 rmfree(mpt->m_erqsense_map, cmd->cmd_extrqschunks,
4273 cmd->cmd_extrqsidx + 1);
4274 }
4275 if (cmd->cmd_flags & CFLAG_CDBEXTERN) {
4276 kmem_free(cmd->cmd_pkt->pkt_cdbp, (size_t)cmd->cmd_cdblen);
4277 }
4278 if (cmd->cmd_flags & CFLAG_SCBEXTERN) {
4279 kmem_free(cmd->cmd_pkt->pkt_scbp, (size_t)cmd->cmd_scblen);
4280 }
4281 if (cmd->cmd_flags & CFLAG_PRIVEXTERN) {
4282 kmem_free(cmd->cmd_pkt->pkt_private, (size_t)cmd->cmd_privlen);
4283 }
4284 cmd->cmd_flags = CFLAG_FREE;
4285 kmem_cache_free(mpt->m_kmem_cache, (void *)cmd);
4286 }
4287
4288 /*
4289 * tran_sync_pkt(9E) - explicit DMA synchronization
4290 */
4291 /*ARGSUSED*/
4292 static void
4293 mptsas_scsi_sync_pkt(struct scsi_address *ap, struct scsi_pkt *pkt)
4294 {
4295 mptsas_cmd_t *cmd = PKT2CMD(pkt);
4296
4297 NDBG3(("mptsas_scsi_sync_pkt: target=%d, pkt=0x%p",
4298 ap->a_target, (void *)pkt));
4299
4300 if (cmd->cmd_dmahandle) {
4301 (void) ddi_dma_sync(cmd->cmd_dmahandle, 0, 0,
4302 (cmd->cmd_flags & CFLAG_DMASEND) ?
4303 DDI_DMA_SYNC_FORDEV : DDI_DMA_SYNC_FORCPU);
4304 }
4305 }
4306
4307 /*
4308 * tran_dmafree(9E) - deallocate DMA resources allocated for command
4309 */
4310 /*ARGSUSED*/
4311 static void
4312 mptsas_scsi_dmafree(struct scsi_address *ap, struct scsi_pkt *pkt)
4313 {
4314 mptsas_cmd_t *cmd = PKT2CMD(pkt);
4315 mptsas_t *mpt = ADDR2MPT(ap);
4316
4317 NDBG3(("mptsas_scsi_dmafree: target=%d pkt=0x%p",
4318 ap->a_target, (void *)pkt));
4319
4320 if (cmd->cmd_flags & CFLAG_DMAVALID) {
4321 (void) ddi_dma_unbind_handle(cmd->cmd_dmahandle);
4322 cmd->cmd_flags &= ~CFLAG_DMAVALID;
4323 }
4324
4325 mptsas_free_extra_sgl_frame(mpt, cmd);
4326 }
4327
4328 static void
4329 mptsas_pkt_comp(struct scsi_pkt *pkt, mptsas_cmd_t *cmd)
4330 {
4331 if ((cmd->cmd_flags & CFLAG_CMDIOPB) &&
4332 (!(cmd->cmd_flags & CFLAG_DMASEND))) {
4333 (void) ddi_dma_sync(cmd->cmd_dmahandle, 0, 0,
4334 DDI_DMA_SYNC_FORCPU);
4335 }
4336 (*pkt->pkt_comp)(pkt);
4337 }
4338
4339 static void
4340 mptsas_sge_mainframe(mptsas_cmd_t *cmd, pMpi2SCSIIORequest_t frame,
4341 ddi_acc_handle_t acc_hdl, uint_t cookiec, uint32_t end_flags)
4342 {
4343 pMpi2SGESimple64_t sge;
4344 mptti_t *dmap;
4345 uint32_t flags;
4346
4347 dmap = cmd->cmd_sg;
4348
4349 sge = (pMpi2SGESimple64_t)(&frame->SGL);
4350 while (cookiec--) {
4351 ddi_put32(acc_hdl,
4352 &sge->Address.Low, dmap->addr.address64.Low);
4353 ddi_put32(acc_hdl,
4354 &sge->Address.High, dmap->addr.address64.High);
4355 ddi_put32(acc_hdl, &sge->FlagsLength,
4356 dmap->count);
4357 flags = ddi_get32(acc_hdl, &sge->FlagsLength);
4358 flags |= ((uint32_t)
4359 (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
4360 MPI2_SGE_FLAGS_SYSTEM_ADDRESS |
4361 MPI2_SGE_FLAGS_64_BIT_ADDRESSING) <<
4362 MPI2_SGE_FLAGS_SHIFT);
4363
4364 /*
4365 * If this is the last cookie, we set the flags
4366 * to indicate so
4367 */
4368 if (cookiec == 0) {
4369 flags |= end_flags;
4370 }
4371 if (cmd->cmd_flags & CFLAG_DMASEND) {
4372 flags |= (MPI2_SGE_FLAGS_HOST_TO_IOC <<
4373 MPI2_SGE_FLAGS_SHIFT);
4374 } else {
4375 flags |= (MPI2_SGE_FLAGS_IOC_TO_HOST <<
4376 MPI2_SGE_FLAGS_SHIFT);
4377 }
4378 ddi_put32(acc_hdl, &sge->FlagsLength, flags);
4379 dmap++;
4380 sge++;
4381 }
4382 }
4383
4384 static void
4385 mptsas_sge_chain(mptsas_t *mpt, mptsas_cmd_t *cmd,
4386 pMpi2SCSIIORequest_t frame, ddi_acc_handle_t acc_hdl)
4387 {
4388 pMpi2SGESimple64_t sge;
4389 pMpi2SGEChain64_t sgechain;
4390 uint64_t nframe_phys_addr;
4391 uint_t cookiec;
4392 mptti_t *dmap;
4393 uint32_t flags;
4394
4395 /*
4396 * Save the number of entries in the DMA
4397 * Scatter/Gather list
4398 */
4399 cookiec = cmd->cmd_cookiec;
4400
4401 /*
4402 * Hereby we start to deal with multiple frames.
4403 * The process is as follows:
4404 * 1. Determine how many frames are needed for SGL element
4405 * storage; Note that all frames are stored in contiguous
4406 * memory space and in 64-bit DMA mode each element is
4407 * 3 double-words (12 bytes) long.
4408 * 2. Fill up the main frame. We need to do this separately
4409 * since it contains the SCSI IO request header and needs
4410 * dedicated processing. Note that the last 4 double-words
4411 * of the SCSI IO header is for SGL element storage
4412 * (MPI2_SGE_IO_UNION).
4413 * 3. Fill the chain element in the main frame, so the DMA
4414 * engine can use the following frames.
4415 * 4. Enter a loop to fill the remaining frames. Note that the
4416 * last frame contains no chain element. The remaining
4417 * frames go into the mpt SGL buffer allocated on the fly,
4418 * not immediately following the main message frame, as in
4419 * Gen1.
4420 * Some restrictions:
4421 * 1. For 64-bit DMA, the simple element and chain element
4422 * are both of 3 double-words (12 bytes) in size, even
4423 * though all frames are stored in the first 4G of mem
4424 * range and the higher 32-bits of the address are always 0.
4425 * 2. On some controllers (like the 1064/1068), a frame can
4426 * hold SGL elements with the last 1 or 2 double-words
4427 * (4 or 8 bytes) un-used. On these controllers, we should
4428 * recognize that there's not enough room for another SGL
4429 * element and move the sge pointer to the next frame.
4430 */
4431 int i, j, k, l, frames, sgemax;
4432 int temp;
4433 uint8_t chainflags;
4434 uint16_t chainlength;
4435 mptsas_cache_frames_t *p;
4436
4437 /*
4438 * Sgemax is the number of SGE's that will fit
4439 * each extra frame and frames is total
4440 * number of frames we'll need. 1 sge entry per
4441 * frame is reseverd for the chain element thus the -1 below.
4442 */
4443 sgemax = ((mpt->m_req_frame_size / sizeof (MPI2_SGE_SIMPLE64))
4444 - 1);
4445 temp = (cookiec - (MPTSAS_MAX_FRAME_SGES64(mpt) - 1)) / sgemax;
4446
4447 /*
4448 * A little check to see if we need to round up the number
4449 * of frames we need
4450 */
4451 if ((cookiec - (MPTSAS_MAX_FRAME_SGES64(mpt) - 1)) - (temp *
4452 sgemax) > 1) {
4453 frames = (temp + 1);
4454 } else {
4455 frames = temp;
4456 }
4457 dmap = cmd->cmd_sg;
4458 sge = (pMpi2SGESimple64_t)(&frame->SGL);
4459
4460 /*
4461 * First fill in the main frame
4462 */
4463 j = MPTSAS_MAX_FRAME_SGES64(mpt) - 1;
4464 mptsas_sge_mainframe(cmd, frame, acc_hdl, j,
4465 ((uint32_t)(MPI2_SGE_FLAGS_LAST_ELEMENT) <<
4466 MPI2_SGE_FLAGS_SHIFT));
4467 dmap += j;
4468 sge += j;
4469 j++;
4470
4471 /*
4472 * Fill in the chain element in the main frame.
4473 * About calculation on ChainOffset:
4474 * 1. Struct msg_scsi_io_request has 4 double-words (16 bytes)
4475 * in the end reserved for SGL element storage
4476 * (MPI2_SGE_IO_UNION); we should count it in our
4477 * calculation. See its definition in the header file.
4478 * 2. Constant j is the counter of the current SGL element
4479 * that will be processed, and (j - 1) is the number of
4480 * SGL elements that have been processed (stored in the
4481 * main frame).
4482 * 3. ChainOffset value should be in units of double-words (4
4483 * bytes) so the last value should be divided by 4.
4484 */
4485 ddi_put8(acc_hdl, &frame->ChainOffset,
4486 (sizeof (MPI2_SCSI_IO_REQUEST) -
4487 sizeof (MPI2_SGE_IO_UNION) +
4488 (j - 1) * sizeof (MPI2_SGE_SIMPLE64)) >> 2);
4489 sgechain = (pMpi2SGEChain64_t)sge;
4490 chainflags = (MPI2_SGE_FLAGS_CHAIN_ELEMENT |
4491 MPI2_SGE_FLAGS_SYSTEM_ADDRESS |
4492 MPI2_SGE_FLAGS_64_BIT_ADDRESSING);
4493 ddi_put8(acc_hdl, &sgechain->Flags, chainflags);
4494
4495 /*
4496 * The size of the next frame is the accurate size of space
4497 * (in bytes) used to store the SGL elements. j is the counter
4498 * of SGL elements. (j - 1) is the number of SGL elements that
4499 * have been processed (stored in frames).
4500 */
4501 if (frames >= 2) {
4502 ASSERT(mpt->m_req_frame_size >= sizeof (MPI2_SGE_SIMPLE64));
4503 chainlength = mpt->m_req_frame_size /
4504 sizeof (MPI2_SGE_SIMPLE64) *
4505 sizeof (MPI2_SGE_SIMPLE64);
4506 } else {
4507 chainlength = ((cookiec - (j - 1)) *
4508 sizeof (MPI2_SGE_SIMPLE64));
4509 }
4510
4511 p = cmd->cmd_extra_frames;
4512
4513 ddi_put16(acc_hdl, &sgechain->Length, chainlength);
4514 ddi_put32(acc_hdl, &sgechain->Address.Low, p->m_phys_addr);
4515 ddi_put32(acc_hdl, &sgechain->Address.High, p->m_phys_addr >> 32);
4516
4517 /*
4518 * If there are more than 2 frames left we have to
4519 * fill in the next chain offset to the location of
4520 * the chain element in the next frame.
4521 * sgemax is the number of simple elements in an extra
4522 * frame. Note that the value NextChainOffset should be
4523 * in double-words (4 bytes).
4524 */
4525 if (frames >= 2) {
4526 ddi_put8(acc_hdl, &sgechain->NextChainOffset,
4527 (sgemax * sizeof (MPI2_SGE_SIMPLE64)) >> 2);
4528 } else {
4529 ddi_put8(acc_hdl, &sgechain->NextChainOffset, 0);
4530 }
4531
4532 /*
4533 * Jump to next frame;
4534 * Starting here, chain buffers go into the per command SGL.
4535 * This buffer is allocated when chain buffers are needed.
4536 */
4537 sge = (pMpi2SGESimple64_t)p->m_frames_addr;
4538 i = cookiec;
4539
4540 /*
4541 * Start filling in frames with SGE's. If we
4542 * reach the end of frame and still have SGE's
4543 * to fill we need to add a chain element and
4544 * use another frame. j will be our counter
4545 * for what cookie we are at and i will be
4546 * the total cookiec. k is the current frame
4547 */
4548 for (k = 1; k <= frames; k++) {
4549 for (l = 1; (l <= (sgemax + 1)) && (j <= i); j++, l++) {
4550
4551 /*
4552 * If we have reached the end of frame
4553 * and we have more SGE's to fill in
4554 * we have to fill the final entry
4555 * with a chain element and then
4556 * continue to the next frame
4557 */
4558 if ((l == (sgemax + 1)) && (k != frames)) {
4559 sgechain = (pMpi2SGEChain64_t)sge;
4560 j--;
4561 chainflags = (
4562 MPI2_SGE_FLAGS_CHAIN_ELEMENT |
4563 MPI2_SGE_FLAGS_SYSTEM_ADDRESS |
4564 MPI2_SGE_FLAGS_64_BIT_ADDRESSING);
4565 ddi_put8(p->m_acc_hdl,
4566 &sgechain->Flags, chainflags);
4567 /*
4568 * k is the frame counter and (k + 1)
4569 * is the number of the next frame.
4570 * Note that frames are in contiguous
4571 * memory space.
4572 */
4573 nframe_phys_addr = p->m_phys_addr +
4574 (mpt->m_req_frame_size * k);
4575 ddi_put32(p->m_acc_hdl,
4576 &sgechain->Address.Low,
4577 nframe_phys_addr);
4578 ddi_put32(p->m_acc_hdl,
4579 &sgechain->Address.High,
4580 nframe_phys_addr >> 32);
4581
4582 /*
4583 * If there are more than 2 frames left
4584 * we have to next chain offset to
4585 * the location of the chain element
4586 * in the next frame and fill in the
4587 * length of the next chain
4588 */
4589 if ((frames - k) >= 2) {
4590 ddi_put8(p->m_acc_hdl,
4591 &sgechain->NextChainOffset,
4592 (sgemax *
4593 sizeof (MPI2_SGE_SIMPLE64))
4594 >> 2);
4595 ddi_put16(p->m_acc_hdl,
4596 &sgechain->Length,
4597 mpt->m_req_frame_size /
4598 sizeof (MPI2_SGE_SIMPLE64) *
4599 sizeof (MPI2_SGE_SIMPLE64));
4600 } else {
4601 /*
4602 * This is the last frame. Set
4603 * the NextChainOffset to 0 and
4604 * Length is the total size of
4605 * all remaining simple elements
4606 */
4607 ddi_put8(p->m_acc_hdl,
4608 &sgechain->NextChainOffset,
4609 0);
4610 ddi_put16(p->m_acc_hdl,
4611 &sgechain->Length,
4612 (cookiec - j) *
4613 sizeof (MPI2_SGE_SIMPLE64));
4614 }
4615
4616 /* Jump to the next frame */
4617 sge = (pMpi2SGESimple64_t)
4618 ((char *)p->m_frames_addr +
4619 (int)mpt->m_req_frame_size * k);
4620
4621 continue;
4622 }
4623
4624 ddi_put32(p->m_acc_hdl,
4625 &sge->Address.Low,
4626 dmap->addr.address64.Low);
4627 ddi_put32(p->m_acc_hdl,
4628 &sge->Address.High,
4629 dmap->addr.address64.High);
4630 ddi_put32(p->m_acc_hdl,
4631 &sge->FlagsLength, dmap->count);
4632 flags = ddi_get32(p->m_acc_hdl,
4633 &sge->FlagsLength);
4634 flags |= ((uint32_t)(
4635 MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
4636 MPI2_SGE_FLAGS_SYSTEM_ADDRESS |
4637 MPI2_SGE_FLAGS_64_BIT_ADDRESSING) <<
4638 MPI2_SGE_FLAGS_SHIFT);
4639
4640 /*
4641 * If we are at the end of the frame and
4642 * there is another frame to fill in
4643 * we set the last simple element as last
4644 * element
4645 */
4646 if ((l == sgemax) && (k != frames)) {
4647 flags |= ((uint32_t)
4648 (MPI2_SGE_FLAGS_LAST_ELEMENT) <<
4649 MPI2_SGE_FLAGS_SHIFT);
4650 }
4651
4652 /*
4653 * If this is the final cookie we
4654 * indicate it by setting the flags
4655 */
4656 if (j == i) {
4657 flags |= ((uint32_t)
4658 (MPI2_SGE_FLAGS_LAST_ELEMENT |
4659 MPI2_SGE_FLAGS_END_OF_BUFFER |
4660 MPI2_SGE_FLAGS_END_OF_LIST) <<
4661 MPI2_SGE_FLAGS_SHIFT);
4662 }
4663 if (cmd->cmd_flags & CFLAG_DMASEND) {
4664 flags |=
4665 (MPI2_SGE_FLAGS_HOST_TO_IOC <<
4666 MPI2_SGE_FLAGS_SHIFT);
4667 } else {
4668 flags |=
4669 (MPI2_SGE_FLAGS_IOC_TO_HOST <<
4670 MPI2_SGE_FLAGS_SHIFT);
4671 }
4672 ddi_put32(p->m_acc_hdl,
4673 &sge->FlagsLength, flags);
4674 dmap++;
4675 sge++;
4676 }
4677 }
4678
4679 /*
4680 * Sync DMA with the chain buffers that were just created
4681 */
4682 (void) ddi_dma_sync(p->m_dma_hdl, 0, 0, DDI_DMA_SYNC_FORDEV);
4683 }
4684
4685 static void
4686 mptsas_ieee_sge_mainframe(mptsas_cmd_t *cmd, pMpi2SCSIIORequest_t frame,
4687 ddi_acc_handle_t acc_hdl, uint_t cookiec, uint8_t end_flag)
4688 {
4689 pMpi2IeeeSgeSimple64_t ieeesge;
4690 mptti_t *dmap;
4691 uint8_t flags;
4692
4693 dmap = cmd->cmd_sg;
4694
4695 NDBG1(("mptsas_ieee_sge_mainframe: cookiec=%d, %s", cookiec,
4696 cmd->cmd_flags & CFLAG_DMASEND?"Out":"In"));
4697
4698 ieeesge = (pMpi2IeeeSgeSimple64_t)(&frame->SGL);
4699 while (cookiec--) {
4700 ddi_put32(acc_hdl,
4701 &ieeesge->Address.Low, dmap->addr.address64.Low);
4702 ddi_put32(acc_hdl,
4703 &ieeesge->Address.High, dmap->addr.address64.High);
4704 ddi_put32(acc_hdl, &ieeesge->Length,
4705 dmap->count);
4706 NDBG1(("mptsas_ieee_sge_mainframe: len=%d", dmap->count));
4707 flags = (MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
4708 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR);
4709
4710 /*
4711 * If this is the last cookie, we set the flags
4712 * to indicate so
4713 */
4714 if (cookiec == 0) {
4715 flags |= end_flag;
4716 }
4717
4718 ddi_put8(acc_hdl, &ieeesge->Flags, flags);
4719 dmap++;
4720 ieeesge++;
4721 }
4722 }
4723
4724 static void
4725 mptsas_ieee_sge_chain(mptsas_t *mpt, mptsas_cmd_t *cmd,
4726 pMpi2SCSIIORequest_t frame, ddi_acc_handle_t acc_hdl)
4727 {
4728 pMpi2IeeeSgeSimple64_t ieeesge;
4729 pMpi25IeeeSgeChain64_t ieeesgechain;
4730 uint64_t nframe_phys_addr;
4731 uint_t cookiec;
4732 mptti_t *dmap;
4733 uint8_t flags;
4734
4735 /*
4736 * Save the number of entries in the DMA
4737 * Scatter/Gather list
4738 */
4739 cookiec = cmd->cmd_cookiec;
4740
4741 NDBG1(("mptsas_ieee_sge_chain: cookiec=%d", cookiec));
4742
4743 /*
4744 * Hereby we start to deal with multiple frames.
4745 * The process is as follows:
4746 * 1. Determine how many frames are needed for SGL element
4747 * storage; Note that all frames are stored in contiguous
4748 * memory space and in 64-bit DMA mode each element is
4749 * 4 double-words (16 bytes) long.
4750 * 2. Fill up the main frame. We need to do this separately
4751 * since it contains the SCSI IO request header and needs
4752 * dedicated processing. Note that the last 4 double-words
4753 * of the SCSI IO header is for SGL element storage
4754 * (MPI2_SGE_IO_UNION).
4755 * 3. Fill the chain element in the main frame, so the DMA
4756 * engine can use the following frames.
4757 * 4. Enter a loop to fill the remaining frames. Note that the
4758 * last frame contains no chain element. The remaining
4759 * frames go into the mpt SGL buffer allocated on the fly,
4760 * not immediately following the main message frame, as in
4761 * Gen1.
4762 * Restrictions:
4763 * For 64-bit DMA, the simple element and chain element
4764 * are both of 4 double-words (16 bytes) in size, even
4765 * though all frames are stored in the first 4G of mem
4766 * range and the higher 32-bits of the address are always 0.
4767 */
4768 int i, j, k, l, frames, sgemax;
4769 int temp;
4770 uint8_t chainflags;
4771 uint32_t chainlength;
4772 mptsas_cache_frames_t *p;
4773
4774 /*
4775 * Sgemax is the number of SGE's that will fit
4776 * each extra frame and frames is total
4777 * number of frames we'll need. 1 sge entry per
4778 * frame is reseverd for the chain element thus the -1 below.
4779 */
4780 sgemax = ((mpt->m_req_frame_size / sizeof (MPI2_IEEE_SGE_SIMPLE64))
4781 - 1);
4782 temp = (cookiec - (MPTSAS_MAX_FRAME_SGES64(mpt) - 1)) / sgemax;
4783
4784 /*
4785 * A little check to see if we need to round up the number
4786 * of frames we need
4787 */
4788 if ((cookiec - (MPTSAS_MAX_FRAME_SGES64(mpt) - 1)) - (temp *
4789 sgemax) > 1) {
4790 frames = (temp + 1);
4791 } else {
4792 frames = temp;
4793 }
4794 NDBG1(("mptsas_ieee_sge_chain: temp=%d, frames=%d", temp, frames));
4795 dmap = cmd->cmd_sg;
4796 ieeesge = (pMpi2IeeeSgeSimple64_t)(&frame->SGL);
4797
4798 /*
4799 * First fill in the main frame
4800 */
4801 j = MPTSAS_MAX_FRAME_SGES64(mpt) - 1;
4802 mptsas_ieee_sge_mainframe(cmd, frame, acc_hdl, j, 0);
4803 dmap += j;
4804 ieeesge += j;
4805 j++;
4806
4807 /*
4808 * Fill in the chain element in the main frame.
4809 * About calculation on ChainOffset:
4810 * 1. Struct msg_scsi_io_request has 4 double-words (16 bytes)
4811 * in the end reserved for SGL element storage
4812 * (MPI2_SGE_IO_UNION); we should count it in our
4813 * calculation. See its definition in the header file.
4814 * 2. Constant j is the counter of the current SGL element
4815 * that will be processed, and (j - 1) is the number of
4816 * SGL elements that have been processed (stored in the
4817 * main frame).
4818 * 3. ChainOffset value should be in units of quad-words (16
4819 * bytes) so the last value should be divided by 16.
4820 */
4821 ddi_put8(acc_hdl, &frame->ChainOffset,
4822 (sizeof (MPI2_SCSI_IO_REQUEST) -
4823 sizeof (MPI2_SGE_IO_UNION) +
4824 (j - 1) * sizeof (MPI2_IEEE_SGE_SIMPLE64)) >> 4);
4825 ieeesgechain = (pMpi25IeeeSgeChain64_t)ieeesge;
4826 chainflags = (MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT |
4827 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR);
4828 ddi_put8(acc_hdl, &ieeesgechain->Flags, chainflags);
4829
4830 /*
4831 * The size of the next frame is the accurate size of space
4832 * (in bytes) used to store the SGL elements. j is the counter
4833 * of SGL elements. (j - 1) is the number of SGL elements that
4834 * have been processed (stored in frames).
4835 */
4836 if (frames >= 2) {
4837 ASSERT(mpt->m_req_frame_size >=
4838 sizeof (MPI2_IEEE_SGE_SIMPLE64));
4839 chainlength = mpt->m_req_frame_size /
4840 sizeof (MPI2_IEEE_SGE_SIMPLE64) *
4841 sizeof (MPI2_IEEE_SGE_SIMPLE64);
4842 } else {
4843 chainlength = ((cookiec - (j - 1)) *
4844 sizeof (MPI2_IEEE_SGE_SIMPLE64));
4845 }
4846
4847 p = cmd->cmd_extra_frames;
4848
4849 ddi_put32(acc_hdl, &ieeesgechain->Length, chainlength);
4850 ddi_put32(acc_hdl, &ieeesgechain->Address.Low, p->m_phys_addr);
4851 ddi_put32(acc_hdl, &ieeesgechain->Address.High, p->m_phys_addr >> 32);
4852
4853 /*
4854 * If there are more than 2 frames left we have to
4855 * fill in the next chain offset to the location of
4856 * the chain element in the next frame.
4857 * sgemax is the number of simple elements in an extra
4858 * frame. Note that the value NextChainOffset should be
4859 * in double-words (4 bytes).
4860 */
4861 if (frames >= 2) {
4862 ddi_put8(acc_hdl, &ieeesgechain->NextChainOffset,
4863 (sgemax * sizeof (MPI2_IEEE_SGE_SIMPLE64)) >> 4);
4864 } else {
4865 ddi_put8(acc_hdl, &ieeesgechain->NextChainOffset, 0);
4866 }
4867
4868 /*
4869 * Jump to next frame;
4870 * Starting here, chain buffers go into the per command SGL.
4871 * This buffer is allocated when chain buffers are needed.
4872 */
4873 ieeesge = (pMpi2IeeeSgeSimple64_t)p->m_frames_addr;
4874 i = cookiec;
4875
4876 /*
4877 * Start filling in frames with SGE's. If we
4878 * reach the end of frame and still have SGE's
4879 * to fill we need to add a chain element and
4880 * use another frame. j will be our counter
4881 * for what cookie we are at and i will be
4882 * the total cookiec. k is the current frame
4883 */
4884 for (k = 1; k <= frames; k++) {
4885 for (l = 1; (l <= (sgemax + 1)) && (j <= i); j++, l++) {
4886
4887 /*
4888 * If we have reached the end of frame
4889 * and we have more SGE's to fill in
4890 * we have to fill the final entry
4891 * with a chain element and then
4892 * continue to the next frame
4893 */
4894 if ((l == (sgemax + 1)) && (k != frames)) {
4895 ieeesgechain = (pMpi25IeeeSgeChain64_t)ieeesge;
4896 j--;
4897 chainflags =
4898 MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT |
4899 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
4900 ddi_put8(p->m_acc_hdl,
4901 &ieeesgechain->Flags, chainflags);
4902 /*
4903 * k is the frame counter and (k + 1)
4904 * is the number of the next frame.
4905 * Note that frames are in contiguous
4906 * memory space.
4907 */
4908 nframe_phys_addr = p->m_phys_addr +
4909 (mpt->m_req_frame_size * k);
4910 ddi_put32(p->m_acc_hdl,
4911 &ieeesgechain->Address.Low,
4912 nframe_phys_addr);
4913 ddi_put32(p->m_acc_hdl,
4914 &ieeesgechain->Address.High,
4915 nframe_phys_addr >> 32);
4916
4917 /*
4918 * If there are more than 2 frames left
4919 * we have to next chain offset to
4920 * the location of the chain element
4921 * in the next frame and fill in the
4922 * length of the next chain
4923 */
4924 if ((frames - k) >= 2) {
4925 ddi_put8(p->m_acc_hdl,
4926 &ieeesgechain->NextChainOffset,
4927 (sgemax *
4928 sizeof (MPI2_IEEE_SGE_SIMPLE64))
4929 >> 4);
4930 ASSERT(mpt->m_req_frame_size >=
4931 sizeof (MPI2_IEEE_SGE_SIMPLE64));
4932 ddi_put32(p->m_acc_hdl,
4933 &ieeesgechain->Length,
4934 mpt->m_req_frame_size /
4935 sizeof (MPI2_IEEE_SGE_SIMPLE64) *
4936 sizeof (MPI2_IEEE_SGE_SIMPLE64));
4937 } else {
4938 /*
4939 * This is the last frame. Set
4940 * the NextChainOffset to 0 and
4941 * Length is the total size of
4942 * all remaining simple elements
4943 */
4944 ddi_put8(p->m_acc_hdl,
4945 &ieeesgechain->NextChainOffset,
4946 0);
4947 ddi_put32(p->m_acc_hdl,
4948 &ieeesgechain->Length,
4949 (cookiec - j) *
4950 sizeof (MPI2_IEEE_SGE_SIMPLE64));
4951 }
4952
4953 /* Jump to the next frame */
4954 ieeesge = (pMpi2IeeeSgeSimple64_t)
4955 ((char *)p->m_frames_addr +
4956 (int)mpt->m_req_frame_size * k);
4957
4958 continue;
4959 }
4960
4961 ddi_put32(p->m_acc_hdl,
4962 &ieeesge->Address.Low,
4963 dmap->addr.address64.Low);
4964 ddi_put32(p->m_acc_hdl,
4965 &ieeesge->Address.High,
4966 dmap->addr.address64.High);
4967 ddi_put32(p->m_acc_hdl,
4968 &ieeesge->Length, dmap->count);
4969 flags = (MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
4970 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR);
4971
4972 /*
4973 * If we are at the end of the frame and
4974 * there is another frame to fill in
4975 * do we need to do anything?
4976 * if ((l == sgemax) && (k != frames)) {
4977 * }
4978 */
4979
4980 /*
4981 * If this is the final cookie set end of list.
4982 */
4983 if (j == i) {
4984 flags |= MPI25_IEEE_SGE_FLAGS_END_OF_LIST;
4985 }
4986
4987 ddi_put8(p->m_acc_hdl, &ieeesge->Flags, flags);
4988 dmap++;
4989 ieeesge++;
4990 }
4991 }
4992
4993 /*
4994 * Sync DMA with the chain buffers that were just created
4995 */
4996 (void) ddi_dma_sync(p->m_dma_hdl, 0, 0, DDI_DMA_SYNC_FORDEV);
4997 }
4998
4999 static void
5000 mptsas_sge_setup(mptsas_t *mpt, mptsas_cmd_t *cmd, uint32_t *control,
5001 pMpi2SCSIIORequest_t frame, ddi_acc_handle_t acc_hdl)
5002 {
5003 ASSERT(cmd->cmd_flags & CFLAG_DMAVALID);
5004
5005 NDBG1(("mptsas_sge_setup: cookiec=%d", cmd->cmd_cookiec));
5006
5007 /*
5008 * Set read/write bit in control.
5009 */
5010 if (cmd->cmd_flags & CFLAG_DMASEND) {
5011 *control |= MPI2_SCSIIO_CONTROL_WRITE;
5012 } else {
5013 *control |= MPI2_SCSIIO_CONTROL_READ;
5014 }
5015
5016 ddi_put32(acc_hdl, &frame->DataLength, cmd->cmd_dmacount);
5017
5018 /*
5019 * We have 4 cases here. First where we can fit all the
5020 * SG elements into the main frame, and the case
5021 * where we can't. The SG element is also different when using
5022 * MPI2.5 interface.
5023 * If we have more cookies than we can attach to a frame
5024 * we will need to use a chain element to point
5025 * a location of memory where the rest of the S/G
5026 * elements reside.
5027 */
5028 if (cmd->cmd_cookiec <= MPTSAS_MAX_FRAME_SGES64(mpt)) {
5029 if (mpt->m_MPI25) {
5030 mptsas_ieee_sge_mainframe(cmd, frame, acc_hdl,
5031 cmd->cmd_cookiec,
5032 MPI25_IEEE_SGE_FLAGS_END_OF_LIST);
5033 } else {
5034 mptsas_sge_mainframe(cmd, frame, acc_hdl,
5035 cmd->cmd_cookiec,
5036 ((uint32_t)(MPI2_SGE_FLAGS_LAST_ELEMENT
5037 | MPI2_SGE_FLAGS_END_OF_BUFFER
5038 | MPI2_SGE_FLAGS_END_OF_LIST) <<
5039 MPI2_SGE_FLAGS_SHIFT));
5040 }
5041 } else {
5042 if (mpt->m_MPI25) {
5043 mptsas_ieee_sge_chain(mpt, cmd, frame, acc_hdl);
5044 } else {
5045 mptsas_sge_chain(mpt, cmd, frame, acc_hdl);
5046 }
5047 }
5048 }
5049
5050 /*
5051 * Interrupt handling
5052 * Utility routine. Poll for status of a command sent to HBA
5053 * without interrupts (a FLAG_NOINTR command).
5054 */
5055 int
5056 mptsas_poll(mptsas_t *mpt, mptsas_cmd_t *poll_cmd, int polltime)
5057 {
5058 int rval = TRUE;
5059
5060 NDBG5(("mptsas_poll: cmd=0x%p", (void *)poll_cmd));
5061
5062 if ((poll_cmd->cmd_flags & CFLAG_TM_CMD) == 0) {
5063 mptsas_restart_hba(mpt);
5064 }
5065
5066 /*
5067 * Wait, using drv_usecwait(), long enough for the command to
5068 * reasonably return from the target if the target isn't
5069 * "dead". A polled command may well be sent from scsi_poll, and
5070 * there are retries built in to scsi_poll if the transport
5071 * accepted the packet (TRAN_ACCEPT). scsi_poll waits 1 second
5072 * and retries the transport up to scsi_poll_busycnt times
5073 * (currently 60) if
5074 * 1. pkt_reason is CMD_INCOMPLETE and pkt_state is 0, or
5075 * 2. pkt_reason is CMD_CMPLT and *pkt_scbp has STATUS_BUSY
5076 *
5077 * limit the waiting to avoid a hang in the event that the
5078 * cmd never gets started but we are still receiving interrupts
5079 */
5080 while (!(poll_cmd->cmd_flags & CFLAG_FINISHED)) {
5081 if (mptsas_wait_intr(mpt, polltime) == FALSE) {
5082 NDBG5(("mptsas_poll: command incomplete"));
5083 rval = FALSE;
5084 break;
5085 }
5086 }
5087
5088 if (rval == FALSE) {
5089
5090 /*
5091 * this isn't supposed to happen, the hba must be wedged
5092 * Mark this cmd as a timeout.
5093 */
5094 mptsas_set_pkt_reason(mpt, poll_cmd, CMD_TIMEOUT,
5095 (STAT_TIMEOUT|STAT_ABORTED));
5096
5097 if (poll_cmd->cmd_queued == FALSE) {
5098
5099 NDBG5(("mptsas_poll: not on waitq"));
5100
5101 poll_cmd->cmd_pkt->pkt_state |=
5102 (STATE_GOT_BUS|STATE_GOT_TARGET|STATE_SENT_CMD);
5103 } else {
5104
5105 /* find and remove it from the waitq */
5106 NDBG5(("mptsas_poll: delete from waitq"));
5107 mptsas_waitq_delete(mpt, poll_cmd);
5108 }
5109
5110 }
5111 mptsas_fma_check(mpt, poll_cmd);
5112 NDBG5(("mptsas_poll: done"));
5113 return (rval);
5114 }
5115
5116 /*
5117 * Used for polling cmds and TM function
5118 */
5119 static int
5120 mptsas_wait_intr(mptsas_t *mpt, int polltime)
5121 {
5122 int cnt;
5123 pMpi2ReplyDescriptorsUnion_t reply_desc_union;
5124 uint32_t int_mask;
5125
5126 NDBG5(("mptsas_wait_intr"));
5127
5128 mpt->m_polled_intr = 1;
5129
5130 /*
5131 * Get the current interrupt mask and disable interrupts. When
5132 * re-enabling ints, set mask to saved value.
5133 */
5134 int_mask = ddi_get32(mpt->m_datap, &mpt->m_reg->HostInterruptMask);
5135 MPTSAS_DISABLE_INTR(mpt);
5136
5137 /*
5138 * Keep polling for at least (polltime * 1000) seconds
5139 */
5140 for (cnt = 0; cnt < polltime; cnt++) {
5141 (void) ddi_dma_sync(mpt->m_dma_post_queue_hdl, 0, 0,
5142 DDI_DMA_SYNC_FORCPU);
5143
5144 reply_desc_union = (pMpi2ReplyDescriptorsUnion_t)
5145 MPTSAS_GET_NEXT_REPLY(mpt, mpt->m_post_index);
5146
5147 if (ddi_get32(mpt->m_acc_post_queue_hdl,
5148 &reply_desc_union->Words.Low) == 0xFFFFFFFF ||
5149 ddi_get32(mpt->m_acc_post_queue_hdl,
5150 &reply_desc_union->Words.High) == 0xFFFFFFFF) {
5151 drv_usecwait(1000);
5152 continue;
5153 }
5154
5155 /*
5156 * The reply is valid, process it according to its
5157 * type.
5158 */
5159 mptsas_process_intr(mpt, reply_desc_union);
5160
5161 if (++mpt->m_post_index == mpt->m_post_queue_depth) {
5162 mpt->m_post_index = 0;
5163 }
5164
5165 /*
5166 * Update the global reply index
5167 */
5168 ddi_put32(mpt->m_datap,
5169 &mpt->m_reg->ReplyPostHostIndex, mpt->m_post_index);
5170 mpt->m_polled_intr = 0;
5171
5172 /*
5173 * Re-enable interrupts and quit.
5174 */
5175 ddi_put32(mpt->m_datap, &mpt->m_reg->HostInterruptMask,
5176 int_mask);
5177 return (TRUE);
5178
5179 }
5180
5181 /*
5182 * Clear polling flag, re-enable interrupts and quit.
5183 */
5184 mpt->m_polled_intr = 0;
5185 ddi_put32(mpt->m_datap, &mpt->m_reg->HostInterruptMask, int_mask);
5186 return (FALSE);
5187 }
5188
5189 static void
5190 mptsas_handle_scsi_io_success(mptsas_t *mpt,
5191 pMpi2ReplyDescriptorsUnion_t reply_desc)
5192 {
5193 pMpi2SCSIIOSuccessReplyDescriptor_t scsi_io_success;
5194 uint16_t SMID;
5195 mptsas_slots_t *slots = mpt->m_active;
5196 mptsas_cmd_t *cmd = NULL;
5197 struct scsi_pkt *pkt;
5198
5199 ASSERT(mutex_owned(&mpt->m_mutex));
5200
5201 scsi_io_success = (pMpi2SCSIIOSuccessReplyDescriptor_t)reply_desc;
5202 SMID = ddi_get16(mpt->m_acc_post_queue_hdl, &scsi_io_success->SMID);
5203
5204 /*
5205 * This is a success reply so just complete the IO. First, do a sanity
5206 * check on the SMID. The final slot is used for TM requests, which
5207 * would not come into this reply handler.
5208 */
5209 if ((SMID == 0) || (SMID > slots->m_n_normal)) {
5210 mptsas_log(mpt, CE_WARN, "?Received invalid SMID of %d\n",
5211 SMID);
5212 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
5213 return;
5214 }
5215
5216 cmd = slots->m_slot[SMID];
5217
5218 /*
5219 * print warning and return if the slot is empty
5220 */
5221 if (cmd == NULL) {
5222 mptsas_log(mpt, CE_WARN, "?NULL command for successful SCSI IO "
5223 "in slot %d", SMID);
5224 return;
5225 }
5226
5227 pkt = CMD2PKT(cmd);
5228 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET | STATE_SENT_CMD |
5229 STATE_GOT_STATUS);
5230 if (cmd->cmd_flags & CFLAG_DMAVALID) {
5231 pkt->pkt_state |= STATE_XFERRED_DATA;
5232 }
5233 pkt->pkt_resid = 0;
5234
5235 if (cmd->cmd_flags & CFLAG_PASSTHRU) {
5236 cmd->cmd_flags |= CFLAG_FINISHED;
5237 cv_broadcast(&mpt->m_passthru_cv);
5238 return;
5239 } else {
5240 mptsas_remove_cmd(mpt, cmd);
5241 }
5242
5243 if (cmd->cmd_flags & CFLAG_RETRY) {
5244 /*
5245 * The target returned QFULL or busy, do not add tihs
5246 * pkt to the doneq since the hba will retry
5247 * this cmd.
5248 *
5249 * The pkt has already been resubmitted in
5250 * mptsas_handle_qfull() or in mptsas_check_scsi_io_error().
5251 * Remove this cmd_flag here.
5252 */
5253 cmd->cmd_flags &= ~CFLAG_RETRY;
5254 } else {
5255 mptsas_doneq_add(mpt, cmd);
5256 }
5257 }
5258
5259 static void
5260 mptsas_handle_address_reply(mptsas_t *mpt,
5261 pMpi2ReplyDescriptorsUnion_t reply_desc)
5262 {
5263 pMpi2AddressReplyDescriptor_t address_reply;
5264 pMPI2DefaultReply_t reply;
5265 mptsas_fw_diagnostic_buffer_t *pBuffer;
5266 uint32_t reply_addr, reply_frame_dma_baseaddr;
5267 uint16_t SMID, iocstatus;
5268 mptsas_slots_t *slots = mpt->m_active;
5269 mptsas_cmd_t *cmd = NULL;
5270 uint8_t function, buffer_type;
5271 m_replyh_arg_t *args;
5272 int reply_frame_no;
5273
5274 ASSERT(mutex_owned(&mpt->m_mutex));
5275
5276 address_reply = (pMpi2AddressReplyDescriptor_t)reply_desc;
5277 reply_addr = ddi_get32(mpt->m_acc_post_queue_hdl,
5278 &address_reply->ReplyFrameAddress);
5279 SMID = ddi_get16(mpt->m_acc_post_queue_hdl, &address_reply->SMID);
5280
5281 /*
5282 * If reply frame is not in the proper range we should ignore this
5283 * message and exit the interrupt handler.
5284 */
5285 reply_frame_dma_baseaddr = mpt->m_reply_frame_dma_addr & 0xffffffffu;
5286 if ((reply_addr < reply_frame_dma_baseaddr) ||
5287 (reply_addr >= (reply_frame_dma_baseaddr +
5288 (mpt->m_reply_frame_size * mpt->m_max_replies))) ||
5289 ((reply_addr - reply_frame_dma_baseaddr) %
5290 mpt->m_reply_frame_size != 0)) {
5291 mptsas_log(mpt, CE_WARN, "?Received invalid reply frame "
5292 "address 0x%x\n", reply_addr);
5293 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
5294 return;
5295 }
5296
5297 (void) ddi_dma_sync(mpt->m_dma_reply_frame_hdl, 0, 0,
5298 DDI_DMA_SYNC_FORCPU);
5299 reply = (pMPI2DefaultReply_t)(mpt->m_reply_frame + (reply_addr -
5300 reply_frame_dma_baseaddr));
5301 function = ddi_get8(mpt->m_acc_reply_frame_hdl, &reply->Function);
5302
5303 NDBG31(("mptsas_handle_address_reply: function 0x%x, reply_addr=0x%x",
5304 function, reply_addr));
5305
5306 /*
5307 * don't get slot information and command for events since these values
5308 * don't exist
5309 */
5310 if ((function != MPI2_FUNCTION_EVENT_NOTIFICATION) &&
5311 (function != MPI2_FUNCTION_DIAG_BUFFER_POST)) {
5312 /*
5313 * This could be a TM reply, which use the last allocated SMID,
5314 * so allow for that.
5315 */
5316 if ((SMID == 0) || (SMID > (slots->m_n_normal + 1))) {
5317 mptsas_log(mpt, CE_WARN, "?Received invalid SMID of "
5318 "%d\n", SMID);
5319 ddi_fm_service_impact(mpt->m_dip,
5320 DDI_SERVICE_UNAFFECTED);
5321 return;
5322 }
5323
5324 cmd = slots->m_slot[SMID];
5325
5326 /*
5327 * print warning and return if the slot is empty
5328 */
5329 if (cmd == NULL) {
5330 mptsas_log(mpt, CE_WARN, "?NULL command for address "
5331 "reply in slot %d", SMID);
5332 return;
5333 }
5334 if ((cmd->cmd_flags &
5335 (CFLAG_PASSTHRU | CFLAG_CONFIG | CFLAG_FW_DIAG))) {
5336 cmd->cmd_rfm = reply_addr;
5337 cmd->cmd_flags |= CFLAG_FINISHED;
5338 cv_broadcast(&mpt->m_passthru_cv);
5339 cv_broadcast(&mpt->m_config_cv);
5340 cv_broadcast(&mpt->m_fw_diag_cv);
5341 return;
5342 } else if (!(cmd->cmd_flags & CFLAG_FW_CMD)) {
5343 mptsas_remove_cmd(mpt, cmd);
5344 }
5345 NDBG31(("\t\tmptsas_process_intr: slot=%d", SMID));
5346 }
5347 /*
5348 * Depending on the function, we need to handle
5349 * the reply frame (and cmd) differently.
5350 */
5351 switch (function) {
5352 case MPI2_FUNCTION_SCSI_IO_REQUEST:
5353 mptsas_check_scsi_io_error(mpt, (pMpi2SCSIIOReply_t)reply, cmd);
5354 break;
5355 case MPI2_FUNCTION_SCSI_TASK_MGMT:
5356 cmd->cmd_rfm = reply_addr;
5357 mptsas_check_task_mgt(mpt, (pMpi2SCSIManagementReply_t)reply,
5358 cmd);
5359 break;
5360 case MPI2_FUNCTION_FW_DOWNLOAD:
5361 cmd->cmd_flags |= CFLAG_FINISHED;
5362 cv_signal(&mpt->m_fw_cv);
5363 break;
5364 case MPI2_FUNCTION_EVENT_NOTIFICATION:
5365 reply_frame_no = (reply_addr - reply_frame_dma_baseaddr) /
5366 mpt->m_reply_frame_size;
5367 args = &mpt->m_replyh_args[reply_frame_no];
5368 args->mpt = (void *)mpt;
5369 args->rfm = reply_addr;
5370
5371 /*
5372 * Record the event if its type is enabled in
5373 * this mpt instance by ioctl.
5374 */
5375 mptsas_record_event(args);
5376
5377 /*
5378 * Handle time critical events
5379 * NOT_RESPONDING/ADDED only now
5380 */
5381 if (mptsas_handle_event_sync(args) == DDI_SUCCESS) {
5382 /*
5383 * Would not return main process,
5384 * just let taskq resolve ack action
5385 * and ack would be sent in taskq thread
5386 */
5387 NDBG20(("send mptsas_handle_event_sync success"));
5388 }
5389
5390 mutex_enter(&mpt->m_taskmgmt_mutex);
5391 if (mpt->m_in_reset == TRUE) {
5392 NDBG20(("dropping event received during reset"));
5393 mutex_exit(&mpt->m_taskmgmt_mutex);
5394 return;
5395 }
5396 mutex_exit(&mpt->m_taskmgmt_mutex);
5397
5398 if ((ddi_taskq_dispatch(mpt->m_event_taskq, mptsas_handle_event,
5399 (void *)args, DDI_NOSLEEP)) != DDI_SUCCESS) {
5400 mptsas_log(mpt, CE_WARN, "No memory available"
5401 "for dispatch taskq");
5402 /*
5403 * Return the reply frame to the free queue.
5404 */
5405 ddi_put32(mpt->m_acc_free_queue_hdl,
5406 &((uint32_t *)(void *)
5407 mpt->m_free_queue)[mpt->m_free_index], reply_addr);
5408 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0,
5409 DDI_DMA_SYNC_FORDEV);
5410 if (++mpt->m_free_index == mpt->m_free_queue_depth) {
5411 mpt->m_free_index = 0;
5412 }
5413
5414 ddi_put32(mpt->m_datap,
5415 &mpt->m_reg->ReplyFreeHostIndex, mpt->m_free_index);
5416 }
5417 return;
5418 case MPI2_FUNCTION_DIAG_BUFFER_POST:
5419 /*
5420 * If SMID is 0, this implies that the reply is due to a
5421 * release function with a status that the buffer has been
5422 * released. Set the buffer flags accordingly.
5423 */
5424 if (SMID == 0) {
5425 iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl,
5426 &reply->IOCStatus);
5427 buffer_type = ddi_get8(mpt->m_acc_reply_frame_hdl,
5428 &(((pMpi2DiagBufferPostReply_t)reply)->BufferType));
5429 if (iocstatus == MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED) {
5430 pBuffer =
5431 &mpt->m_fw_diag_buffer_list[buffer_type];
5432 pBuffer->valid_data = TRUE;
5433 pBuffer->owned_by_firmware = FALSE;
5434 pBuffer->immediate = FALSE;
5435 }
5436 } else {
5437 /*
5438 * Normal handling of diag post reply with SMID.
5439 */
5440 cmd = slots->m_slot[SMID];
5441
5442 /*
5443 * print warning and return if the slot is empty
5444 */
5445 if (cmd == NULL) {
5446 mptsas_log(mpt, CE_WARN, "?NULL command for "
5447 "address reply in slot %d", SMID);
5448 return;
5449 }
5450 cmd->cmd_rfm = reply_addr;
5451 cmd->cmd_flags |= CFLAG_FINISHED;
5452 cv_broadcast(&mpt->m_fw_diag_cv);
5453 }
5454 return;
5455 default:
5456 mptsas_log(mpt, CE_WARN, "Unknown function 0x%x ", function);
5457 break;
5458 }
5459
5460 /*
5461 * Return the reply frame to the free queue.
5462 */
5463 ddi_put32(mpt->m_acc_free_queue_hdl,
5464 &((uint32_t *)(void *)mpt->m_free_queue)[mpt->m_free_index],
5465 reply_addr);
5466 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0,
5467 DDI_DMA_SYNC_FORDEV);
5468 if (++mpt->m_free_index == mpt->m_free_queue_depth) {
5469 mpt->m_free_index = 0;
5470 }
5471 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex,
5472 mpt->m_free_index);
5473
5474 if (cmd->cmd_flags & CFLAG_FW_CMD)
5475 return;
5476
5477 if (cmd->cmd_flags & CFLAG_RETRY) {
5478 /*
5479 * The target returned QFULL or busy, do not add this
5480 * pkt to the doneq since the hba will retry
5481 * this cmd.
5482 *
5483 * The pkt has already been resubmitted in
5484 * mptsas_handle_qfull() or in mptsas_check_scsi_io_error().
5485 * Remove this cmd_flag here.
5486 */
5487 cmd->cmd_flags &= ~CFLAG_RETRY;
5488 } else {
5489 mptsas_doneq_add(mpt, cmd);
5490 }
5491 }
5492
5493 #ifdef MPTSAS_DEBUG
5494 static uint8_t mptsas_last_sense[256];
5495 #endif
5496
5497 static void
5498 mptsas_check_scsi_io_error(mptsas_t *mpt, pMpi2SCSIIOReply_t reply,
5499 mptsas_cmd_t *cmd)
5500 {
5501 uint8_t scsi_status, scsi_state;
5502 uint16_t ioc_status, cmd_rqs_len;
5503 uint32_t xferred, sensecount, responsedata, loginfo = 0;
5504 struct scsi_pkt *pkt;
5505 struct scsi_arq_status *arqstat;
5506 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
5507 uint8_t *sensedata = NULL;
5508 uint64_t sas_wwn;
5509 uint8_t phy;
5510 char wwn_str[MPTSAS_WWN_STRLEN];
5511
5512 scsi_status = ddi_get8(mpt->m_acc_reply_frame_hdl, &reply->SCSIStatus);
5513 ioc_status = ddi_get16(mpt->m_acc_reply_frame_hdl, &reply->IOCStatus);
5514 scsi_state = ddi_get8(mpt->m_acc_reply_frame_hdl, &reply->SCSIState);
5515 xferred = ddi_get32(mpt->m_acc_reply_frame_hdl, &reply->TransferCount);
5516 sensecount = ddi_get32(mpt->m_acc_reply_frame_hdl, &reply->SenseCount);
5517 responsedata = ddi_get32(mpt->m_acc_reply_frame_hdl,
5518 &reply->ResponseInfo);
5519
5520 if (ioc_status & MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) {
5521 sas_wwn = ptgt->m_addr.mta_wwn;
5522 phy = ptgt->m_phynum;
5523 if (sas_wwn == 0) {
5524 (void) sprintf(wwn_str, "p%x", phy);
5525 } else {
5526 (void) sprintf(wwn_str, "w%016"PRIx64, sas_wwn);
5527 }
5528 loginfo = ddi_get32(mpt->m_acc_reply_frame_hdl,
5529 &reply->IOCLogInfo);
5530 mptsas_log(mpt, CE_NOTE,
5531 "?Log info 0x%x received for target %d %s.\n"
5532 "\tscsi_status=0x%x, ioc_status=0x%x, scsi_state=0x%x",
5533 loginfo, Tgt(cmd), wwn_str, scsi_status, ioc_status,
5534 scsi_state);
5535 }
5536
5537 NDBG31(("\t\tscsi_status=0x%x, ioc_status=0x%x, scsi_state=0x%x",
5538 scsi_status, ioc_status, scsi_state));
5539
5540 pkt = CMD2PKT(cmd);
5541 *(pkt->pkt_scbp) = scsi_status;
5542
5543 if (loginfo == 0x31170000) {
5544 /*
5545 * if loginfo PL_LOGINFO_CODE_IO_DEVICE_MISSING_DELAY_RETRY
5546 * 0x31170000 comes, that means the device missing delay
5547 * is in progressing, the command need retry later.
5548 */
5549 *(pkt->pkt_scbp) = STATUS_BUSY;
5550 return;
5551 }
5552
5553 if ((scsi_state & MPI2_SCSI_STATE_NO_SCSI_STATUS) &&
5554 ((ioc_status & MPI2_IOCSTATUS_MASK) ==
5555 MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE)) {
5556 pkt->pkt_reason = CMD_INCOMPLETE;
5557 pkt->pkt_state |= STATE_GOT_BUS;
5558 if (ptgt->m_reset_delay == 0) {
5559 mptsas_set_throttle(mpt, ptgt,
5560 DRAIN_THROTTLE);
5561 }
5562 return;
5563 }
5564
5565 if (scsi_state & MPI2_SCSI_STATE_RESPONSE_INFO_VALID) {
5566 responsedata &= 0x000000FF;
5567 if (responsedata & MPTSAS_SCSI_RESPONSE_CODE_TLR_OFF) {
5568 mptsas_log(mpt, CE_NOTE, "Do not support the TLR\n");
5569 pkt->pkt_reason = CMD_TLR_OFF;
5570 return;
5571 }
5572 }
5573
5574
5575 switch (scsi_status) {
5576 case MPI2_SCSI_STATUS_CHECK_CONDITION:
5577 pkt->pkt_resid = (cmd->cmd_dmacount - xferred);
5578 arqstat = (void*)(pkt->pkt_scbp);
5579 arqstat->sts_rqpkt_status = *((struct scsi_status *)
5580 (pkt->pkt_scbp));
5581 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET |
5582 STATE_SENT_CMD | STATE_GOT_STATUS | STATE_ARQ_DONE);
5583 if (cmd->cmd_flags & CFLAG_XARQ) {
5584 pkt->pkt_state |= STATE_XARQ_DONE;
5585 }
5586 if (pkt->pkt_resid != cmd->cmd_dmacount) {
5587 pkt->pkt_state |= STATE_XFERRED_DATA;
5588 }
5589 arqstat->sts_rqpkt_reason = pkt->pkt_reason;
5590 arqstat->sts_rqpkt_state = pkt->pkt_state;
5591 arqstat->sts_rqpkt_state |= STATE_XFERRED_DATA;
5592 arqstat->sts_rqpkt_statistics = pkt->pkt_statistics;
5593 sensedata = (uint8_t *)&arqstat->sts_sensedata;
5594 cmd_rqs_len = cmd->cmd_extrqslen ?
5595 cmd->cmd_extrqslen : cmd->cmd_rqslen;
5596 (void) ddi_dma_sync(mpt->m_dma_req_sense_hdl, 0, 0,
5597 DDI_DMA_SYNC_FORKERNEL);
5598 #ifdef MPTSAS_DEBUG
5599 bcopy(cmd->cmd_arq_buf, mptsas_last_sense,
5600 ((cmd_rqs_len >= sizeof (mptsas_last_sense)) ?
5601 sizeof (mptsas_last_sense):cmd_rqs_len));
5602 #endif
5603 bcopy((uchar_t *)cmd->cmd_arq_buf, sensedata,
5604 ((cmd_rqs_len >= sensecount) ? sensecount :
5605 cmd_rqs_len));
5606 arqstat->sts_rqpkt_resid = (cmd_rqs_len - sensecount);
5607 cmd->cmd_flags |= CFLAG_CMDARQ;
5608 /*
5609 * Set proper status for pkt if autosense was valid
5610 */
5611 if (scsi_state & MPI2_SCSI_STATE_AUTOSENSE_VALID) {
5612 struct scsi_status zero_status = { 0 };
5613 arqstat->sts_rqpkt_status = zero_status;
5614 }
5615
5616 /*
5617 * ASC=0x47 is parity error
5618 * ASC=0x48 is initiator detected error received
5619 */
5620 if ((scsi_sense_key(sensedata) == KEY_ABORTED_COMMAND) &&
5621 ((scsi_sense_asc(sensedata) == 0x47) ||
5622 (scsi_sense_asc(sensedata) == 0x48))) {
5623 mptsas_log(mpt, CE_NOTE, "Aborted_command!");
5624 }
5625
5626 /*
5627 * ASC/ASCQ=0x3F/0x0E means report_luns data changed
5628 * ASC/ASCQ=0x25/0x00 means invalid lun
5629 */
5630 if (((scsi_sense_key(sensedata) == KEY_UNIT_ATTENTION) &&
5631 (scsi_sense_asc(sensedata) == 0x3F) &&
5632 (scsi_sense_ascq(sensedata) == 0x0E)) ||
5633 ((scsi_sense_key(sensedata) == KEY_ILLEGAL_REQUEST) &&
5634 (scsi_sense_asc(sensedata) == 0x25) &&
5635 (scsi_sense_ascq(sensedata) == 0x00))) {
5636 mptsas_topo_change_list_t *topo_node = NULL;
5637
5638 topo_node = kmem_zalloc(
5639 sizeof (mptsas_topo_change_list_t),
5640 KM_NOSLEEP);
5641 if (topo_node == NULL) {
5642 mptsas_log(mpt, CE_NOTE, "No memory"
5643 "resource for handle SAS dynamic"
5644 "reconfigure.\n");
5645 break;
5646 }
5647 topo_node->mpt = mpt;
5648 topo_node->event = MPTSAS_DR_EVENT_RECONFIG_TARGET;
5649 topo_node->un.phymask = ptgt->m_addr.mta_phymask;
5650 topo_node->devhdl = ptgt->m_devhdl;
5651 topo_node->object = (void *)ptgt;
5652 topo_node->flags = MPTSAS_TOPO_FLAG_LUN_ASSOCIATED;
5653
5654 if ((ddi_taskq_dispatch(mpt->m_dr_taskq,
5655 mptsas_handle_dr,
5656 (void *)topo_node,
5657 DDI_NOSLEEP)) != DDI_SUCCESS) {
5658 kmem_free(topo_node,
5659 sizeof (mptsas_topo_change_list_t));
5660 mptsas_log(mpt, CE_NOTE, "mptsas start taskq"
5661 "for handle SAS dynamic reconfigure"
5662 "failed. \n");
5663 }
5664 }
5665 break;
5666 case MPI2_SCSI_STATUS_GOOD:
5667 switch (ioc_status & MPI2_IOCSTATUS_MASK) {
5668 case MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE:
5669 pkt->pkt_reason = CMD_DEV_GONE;
5670 pkt->pkt_state |= STATE_GOT_BUS;
5671 if (ptgt->m_reset_delay == 0) {
5672 mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE);
5673 }
5674 NDBG31(("lost disk for target%d, command:%x",
5675 Tgt(cmd), pkt->pkt_cdbp[0]));
5676 break;
5677 case MPI2_IOCSTATUS_SCSI_DATA_OVERRUN:
5678 NDBG31(("data overrun: xferred=%d", xferred));
5679 NDBG31(("dmacount=%d", cmd->cmd_dmacount));
5680 pkt->pkt_reason = CMD_DATA_OVR;
5681 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET
5682 | STATE_SENT_CMD | STATE_GOT_STATUS
5683 | STATE_XFERRED_DATA);
5684 pkt->pkt_resid = 0;
5685 break;
5686 case MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH:
5687 case MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN:
5688 NDBG31(("data underrun: xferred=%d", xferred));
5689 NDBG31(("dmacount=%d", cmd->cmd_dmacount));
5690 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET
5691 | STATE_SENT_CMD | STATE_GOT_STATUS);
5692 pkt->pkt_resid = (cmd->cmd_dmacount - xferred);
5693 if (pkt->pkt_resid != cmd->cmd_dmacount) {
5694 pkt->pkt_state |= STATE_XFERRED_DATA;
5695 }
5696 break;
5697 case MPI2_IOCSTATUS_SCSI_TASK_TERMINATED:
5698 if (cmd->cmd_active_expiration <= gethrtime()) {
5699 /*
5700 * When timeout requested, propagate
5701 * proper reason and statistics to
5702 * target drivers.
5703 */
5704 mptsas_set_pkt_reason(mpt, cmd, CMD_TIMEOUT,
5705 STAT_BUS_RESET | STAT_TIMEOUT);
5706 } else {
5707 mptsas_set_pkt_reason(mpt, cmd, CMD_RESET,
5708 STAT_BUS_RESET);
5709 }
5710 break;
5711 case MPI2_IOCSTATUS_SCSI_IOC_TERMINATED:
5712 case MPI2_IOCSTATUS_SCSI_EXT_TERMINATED:
5713 mptsas_set_pkt_reason(mpt,
5714 cmd, CMD_RESET, STAT_DEV_RESET);
5715 break;
5716 case MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR:
5717 case MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR:
5718 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET);
5719 mptsas_set_pkt_reason(mpt,
5720 cmd, CMD_TERMINATED, STAT_TERMINATED);
5721 break;
5722 case MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES:
5723 case MPI2_IOCSTATUS_BUSY:
5724 /*
5725 * set throttles to drain
5726 */
5727 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL;
5728 ptgt = refhash_next(mpt->m_targets, ptgt)) {
5729 mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE);
5730 }
5731
5732 /*
5733 * retry command
5734 */
5735 cmd->cmd_flags |= CFLAG_RETRY;
5736 cmd->cmd_pkt_flags |= FLAG_HEAD;
5737
5738 (void) mptsas_accept_pkt(mpt, cmd);
5739 break;
5740 default:
5741 mptsas_log(mpt, CE_WARN,
5742 "unknown ioc_status = %x\n", ioc_status);
5743 mptsas_log(mpt, CE_CONT, "scsi_state = %x, transfer "
5744 "count = %x, scsi_status = %x", scsi_state,
5745 xferred, scsi_status);
5746 break;
5747 }
5748 break;
5749 case MPI2_SCSI_STATUS_TASK_SET_FULL:
5750 mptsas_handle_qfull(mpt, cmd);
5751 break;
5752 case MPI2_SCSI_STATUS_BUSY:
5753 NDBG31(("scsi_status busy received"));
5754 break;
5755 case MPI2_SCSI_STATUS_RESERVATION_CONFLICT:
5756 NDBG31(("scsi_status reservation conflict received"));
5757 break;
5758 default:
5759 mptsas_log(mpt, CE_WARN, "scsi_status=%x, ioc_status=%x\n",
5760 scsi_status, ioc_status);
5761 mptsas_log(mpt, CE_WARN,
5762 "mptsas_process_intr: invalid scsi status\n");
5763 break;
5764 }
5765 }
5766
5767 static void
5768 mptsas_check_task_mgt(mptsas_t *mpt, pMpi2SCSIManagementReply_t reply,
5769 mptsas_cmd_t *cmd)
5770 {
5771 uint8_t task_type;
5772 uint16_t ioc_status;
5773 uint32_t log_info;
5774 uint16_t dev_handle;
5775 struct scsi_pkt *pkt = CMD2PKT(cmd);
5776
5777 task_type = ddi_get8(mpt->m_acc_reply_frame_hdl, &reply->TaskType);
5778 ioc_status = ddi_get16(mpt->m_acc_reply_frame_hdl, &reply->IOCStatus);
5779 log_info = ddi_get32(mpt->m_acc_reply_frame_hdl, &reply->IOCLogInfo);
5780 dev_handle = ddi_get16(mpt->m_acc_reply_frame_hdl, &reply->DevHandle);
5781
5782 if (ioc_status != MPI2_IOCSTATUS_SUCCESS) {
5783 mptsas_log(mpt, CE_WARN, "mptsas_check_task_mgt: Task 0x%x "
5784 "failed. IOCStatus=0x%x IOCLogInfo=0x%x target=%d\n",
5785 task_type, ioc_status, log_info, dev_handle);
5786 pkt->pkt_reason = CMD_INCOMPLETE;
5787 return;
5788 }
5789
5790 switch (task_type) {
5791 case MPI2_SCSITASKMGMT_TASKTYPE_ABORT_TASK:
5792 case MPI2_SCSITASKMGMT_TASKTYPE_CLEAR_TASK_SET:
5793 case MPI2_SCSITASKMGMT_TASKTYPE_QUERY_TASK:
5794 case MPI2_SCSITASKMGMT_TASKTYPE_CLR_ACA:
5795 case MPI2_SCSITASKMGMT_TASKTYPE_QRY_TASK_SET:
5796 case MPI2_SCSITASKMGMT_TASKTYPE_QRY_UNIT_ATTENTION:
5797 break;
5798 case MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET:
5799 case MPI2_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET:
5800 case MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET:
5801 /*
5802 * Check for invalid DevHandle of 0 in case application
5803 * sends bad command. DevHandle of 0 could cause problems.
5804 */
5805 if (dev_handle == 0) {
5806 mptsas_log(mpt, CE_WARN, "!Can't flush target with"
5807 " DevHandle of 0.");
5808 } else {
5809 mptsas_flush_target(mpt, dev_handle, Lun(cmd),
5810 task_type);
5811 }
5812 break;
5813 default:
5814 mptsas_log(mpt, CE_WARN, "Unknown task management type %d.",
5815 task_type);
5816 mptsas_log(mpt, CE_WARN, "ioc status = %x", ioc_status);
5817 break;
5818 }
5819 }
5820
5821 static void
5822 mptsas_doneq_thread(mptsas_doneq_thread_arg_t *arg)
5823 {
5824 mptsas_t *mpt = arg->mpt;
5825 uint64_t t = arg->t;
5826 mptsas_cmd_t *cmd;
5827 struct scsi_pkt *pkt;
5828 mptsas_doneq_thread_list_t *item = &mpt->m_doneq_thread_id[t];
5829
5830 mutex_enter(&item->mutex);
5831 while (item->flag & MPTSAS_DONEQ_THREAD_ACTIVE) {
5832 if (!item->doneq) {
5833 cv_wait(&item->cv, &item->mutex);
5834 }
5835 pkt = NULL;
5836 if ((cmd = mptsas_doneq_thread_rm(mpt, t)) != NULL) {
5837 cmd->cmd_flags |= CFLAG_COMPLETED;
5838 pkt = CMD2PKT(cmd);
5839 }
5840 mutex_exit(&item->mutex);
5841 if (pkt) {
5842 mptsas_pkt_comp(pkt, cmd);
5843 }
5844 mutex_enter(&item->mutex);
5845 }
5846 mutex_exit(&item->mutex);
5847 mutex_enter(&mpt->m_doneq_mutex);
5848 mpt->m_doneq_thread_n--;
5849 cv_broadcast(&mpt->m_doneq_thread_cv);
5850 mutex_exit(&mpt->m_doneq_mutex);
5851 }
5852
5853
5854 /*
5855 * mpt interrupt handler.
5856 */
5857 static uint_t
5858 mptsas_intr(caddr_t arg1, caddr_t arg2)
5859 {
5860 mptsas_t *mpt = (void *)arg1;
5861 pMpi2ReplyDescriptorsUnion_t reply_desc_union;
5862 uchar_t did_reply = FALSE;
5863
5864 NDBG1(("mptsas_intr: arg1 0x%p arg2 0x%p", (void *)arg1, (void *)arg2));
5865
5866 mutex_enter(&mpt->m_mutex);
5867
5868 /*
5869 * If interrupts are shared by two channels then check whether this
5870 * interrupt is genuinely for this channel by making sure first the
5871 * chip is in high power state.
5872 */
5873 if ((mpt->m_options & MPTSAS_OPT_PM) &&
5874 (mpt->m_power_level != PM_LEVEL_D0)) {
5875 mutex_exit(&mpt->m_mutex);
5876 return (DDI_INTR_UNCLAIMED);
5877 }
5878
5879 /*
5880 * If polling, interrupt was triggered by some shared interrupt because
5881 * IOC interrupts are disabled during polling, so polling routine will
5882 * handle any replies. Considering this, if polling is happening,
5883 * return with interrupt unclaimed.
5884 */
5885 if (mpt->m_polled_intr) {
5886 mutex_exit(&mpt->m_mutex);
5887 mptsas_log(mpt, CE_WARN, "mpt_sas: Unclaimed interrupt");
5888 return (DDI_INTR_UNCLAIMED);
5889 }
5890
5891 /*
5892 * Read the istat register.
5893 */
5894 if ((INTPENDING(mpt)) != 0) {
5895 /*
5896 * read fifo until empty.
5897 */
5898 #ifndef __lock_lint
5899 _NOTE(CONSTCOND)
5900 #endif
5901 while (TRUE) {
5902 (void) ddi_dma_sync(mpt->m_dma_post_queue_hdl, 0, 0,
5903 DDI_DMA_SYNC_FORCPU);
5904 reply_desc_union = (pMpi2ReplyDescriptorsUnion_t)
5905 MPTSAS_GET_NEXT_REPLY(mpt, mpt->m_post_index);
5906
5907 if (ddi_get32(mpt->m_acc_post_queue_hdl,
5908 &reply_desc_union->Words.Low) == 0xFFFFFFFF ||
5909 ddi_get32(mpt->m_acc_post_queue_hdl,
5910 &reply_desc_union->Words.High) == 0xFFFFFFFF) {
5911 break;
5912 }
5913
5914 /*
5915 * The reply is valid, process it according to its
5916 * type. Also, set a flag for updating the reply index
5917 * after they've all been processed.
5918 */
5919 did_reply = TRUE;
5920
5921 mptsas_process_intr(mpt, reply_desc_union);
5922
5923 /*
5924 * Increment post index and roll over if needed.
5925 */
5926 if (++mpt->m_post_index == mpt->m_post_queue_depth) {
5927 mpt->m_post_index = 0;
5928 }
5929 }
5930
5931 /*
5932 * Update the global reply index if at least one reply was
5933 * processed.
5934 */
5935 if (did_reply) {
5936 ddi_put32(mpt->m_datap,
5937 &mpt->m_reg->ReplyPostHostIndex, mpt->m_post_index);
5938 }
5939 } else {
5940 mutex_exit(&mpt->m_mutex);
5941 return (DDI_INTR_UNCLAIMED);
5942 }
5943 NDBG1(("mptsas_intr complete"));
5944
5945 /*
5946 * If no helper threads are created, process the doneq in ISR. If
5947 * helpers are created, use the doneq length as a metric to measure the
5948 * load on the interrupt CPU. If it is long enough, which indicates the
5949 * load is heavy, then we deliver the IO completions to the helpers.
5950 * This measurement has some limitations, although it is simple and
5951 * straightforward and works well for most of the cases at present.
5952 */
5953 if (!mpt->m_doneq_thread_n ||
5954 (mpt->m_doneq_len <= mpt->m_doneq_length_threshold)) {
5955 mptsas_doneq_empty(mpt);
5956 } else {
5957 mptsas_deliver_doneq_thread(mpt);
5958 }
5959
5960 /*
5961 * If there are queued cmd, start them now.
5962 */
5963 if (mpt->m_waitq != NULL) {
5964 mptsas_restart_waitq(mpt);
5965 }
5966
5967 mutex_exit(&mpt->m_mutex);
5968 return (DDI_INTR_CLAIMED);
5969 }
5970
5971 static void
5972 mptsas_process_intr(mptsas_t *mpt,
5973 pMpi2ReplyDescriptorsUnion_t reply_desc_union)
5974 {
5975 uint8_t reply_type;
5976
5977 ASSERT(mutex_owned(&mpt->m_mutex));
5978
5979 /*
5980 * The reply is valid, process it according to its
5981 * type. Also, set a flag for updated the reply index
5982 * after they've all been processed.
5983 */
5984 reply_type = ddi_get8(mpt->m_acc_post_queue_hdl,
5985 &reply_desc_union->Default.ReplyFlags);
5986 reply_type &= MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK;
5987 if (reply_type == MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS ||
5988 reply_type == MPI25_RPY_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO_SUCCESS) {
5989 mptsas_handle_scsi_io_success(mpt, reply_desc_union);
5990 } else if (reply_type == MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY) {
5991 mptsas_handle_address_reply(mpt, reply_desc_union);
5992 } else {
5993 mptsas_log(mpt, CE_WARN, "?Bad reply type %x", reply_type);
5994 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
5995 }
5996
5997 /*
5998 * Clear the reply descriptor for re-use and increment
5999 * index.
6000 */
6001 ddi_put64(mpt->m_acc_post_queue_hdl,
6002 &((uint64_t *)(void *)mpt->m_post_queue)[mpt->m_post_index],
6003 0xFFFFFFFFFFFFFFFF);
6004 (void) ddi_dma_sync(mpt->m_dma_post_queue_hdl, 0, 0,
6005 DDI_DMA_SYNC_FORDEV);
6006 }
6007
6008 /*
6009 * handle qfull condition
6010 */
6011 static void
6012 mptsas_handle_qfull(mptsas_t *mpt, mptsas_cmd_t *cmd)
6013 {
6014 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
6015
6016 if ((++cmd->cmd_qfull_retries > ptgt->m_qfull_retries) ||
6017 (ptgt->m_qfull_retries == 0)) {
6018 /*
6019 * We have exhausted the retries on QFULL, or,
6020 * the target driver has indicated that it
6021 * wants to handle QFULL itself by setting
6022 * qfull-retries capability to 0. In either case
6023 * we want the target driver's QFULL handling
6024 * to kick in. We do this by having pkt_reason
6025 * as CMD_CMPLT and pkt_scbp as STATUS_QFULL.
6026 */
6027 mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE);
6028 } else {
6029 if (ptgt->m_reset_delay == 0) {
6030 ptgt->m_t_throttle =
6031 max((ptgt->m_t_ncmds - 2), 0);
6032 }
6033
6034 cmd->cmd_pkt_flags |= FLAG_HEAD;
6035 cmd->cmd_flags &= ~(CFLAG_TRANFLAG);
6036 cmd->cmd_flags |= CFLAG_RETRY;
6037
6038 (void) mptsas_accept_pkt(mpt, cmd);
6039
6040 /*
6041 * when target gives queue full status with no commands
6042 * outstanding (m_t_ncmds == 0), throttle is set to 0
6043 * (HOLD_THROTTLE), and the queue full handling start
6044 * (see psarc/1994/313); if there are commands outstanding,
6045 * throttle is set to (m_t_ncmds - 2)
6046 */
6047 if (ptgt->m_t_throttle == HOLD_THROTTLE) {
6048 /*
6049 * By setting throttle to QFULL_THROTTLE, we
6050 * avoid submitting new commands and in
6051 * mptsas_restart_cmd find out slots which need
6052 * their throttles to be cleared.
6053 */
6054 mptsas_set_throttle(mpt, ptgt, QFULL_THROTTLE);
6055 if (mpt->m_restart_cmd_timeid == 0) {
6056 mpt->m_restart_cmd_timeid =
6057 timeout(mptsas_restart_cmd, mpt,
6058 ptgt->m_qfull_retry_interval);
6059 }
6060 }
6061 }
6062 }
6063
6064 mptsas_phymask_t
6065 mptsas_physport_to_phymask(mptsas_t *mpt, uint8_t physport)
6066 {
6067 mptsas_phymask_t phy_mask = 0;
6068 uint8_t i = 0;
6069
6070 NDBG20(("mptsas%d physport_to_phymask enter", mpt->m_instance));
6071
6072 ASSERT(mutex_owned(&mpt->m_mutex));
6073
6074 /*
6075 * If physport is 0xFF, this is a RAID volume. Use phymask of 0.
6076 */
6077 if (physport == 0xFF) {
6078 return (0);
6079 }
6080
6081 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
6082 if (mpt->m_phy_info[i].attached_devhdl &&
6083 (mpt->m_phy_info[i].phy_mask != 0) &&
6084 (mpt->m_phy_info[i].port_num == physport)) {
6085 phy_mask = mpt->m_phy_info[i].phy_mask;
6086 break;
6087 }
6088 }
6089 NDBG20(("mptsas%d physport_to_phymask:physport :%x phymask :%x, ",
6090 mpt->m_instance, physport, phy_mask));
6091 return (phy_mask);
6092 }
6093
6094 /*
6095 * mpt free device handle after device gone, by use of passthrough
6096 */
6097 static int
6098 mptsas_free_devhdl(mptsas_t *mpt, uint16_t devhdl)
6099 {
6100 Mpi2SasIoUnitControlRequest_t req;
6101 Mpi2SasIoUnitControlReply_t rep;
6102 int ret;
6103
6104 ASSERT(mutex_owned(&mpt->m_mutex));
6105
6106 /*
6107 * Need to compose a SAS IO Unit Control request message
6108 * and call mptsas_do_passthru() function
6109 */
6110 bzero(&req, sizeof (req));
6111 bzero(&rep, sizeof (rep));
6112
6113 req.Function = MPI2_FUNCTION_SAS_IO_UNIT_CONTROL;
6114 req.Operation = MPI2_SAS_OP_REMOVE_DEVICE;
6115 req.DevHandle = LE_16(devhdl);
6116
6117 ret = mptsas_do_passthru(mpt, (uint8_t *)&req, (uint8_t *)&rep, NULL,
6118 sizeof (req), sizeof (rep), NULL, 0, NULL, 0, 60, FKIOCTL);
6119 if (ret != 0) {
6120 cmn_err(CE_WARN, "mptsas_free_devhdl: passthru SAS IO Unit "
6121 "Control error %d", ret);
6122 return (DDI_FAILURE);
6123 }
6124
6125 /* do passthrough success, check the ioc status */
6126 if (LE_16(rep.IOCStatus) != MPI2_IOCSTATUS_SUCCESS) {
6127 cmn_err(CE_WARN, "mptsas_free_devhdl: passthru SAS IO Unit "
6128 "Control IOCStatus %d", LE_16(rep.IOCStatus));
6129 return (DDI_FAILURE);
6130 }
6131
6132 return (DDI_SUCCESS);
6133 }
6134
6135 static void
6136 mptsas_update_phymask(mptsas_t *mpt)
6137 {
6138 mptsas_phymask_t mask = 0, phy_mask;
6139 char *phy_mask_name;
6140 uint8_t current_port;
6141 int i, j;
6142
6143 NDBG20(("mptsas%d update phymask ", mpt->m_instance));
6144
6145 ASSERT(mutex_owned(&mpt->m_mutex));
6146
6147 (void) mptsas_get_sas_io_unit_page(mpt);
6148
6149 phy_mask_name = kmem_zalloc(MPTSAS_MAX_PHYS, KM_SLEEP);
6150
6151 for (i = 0; i < mpt->m_num_phys; i++) {
6152 phy_mask = 0x00;
6153
6154 if (mpt->m_phy_info[i].attached_devhdl == 0)
6155 continue;
6156
6157 bzero(phy_mask_name, sizeof (phy_mask_name));
6158
6159 current_port = mpt->m_phy_info[i].port_num;
6160
6161 if ((mask & (1 << i)) != 0)
6162 continue;
6163
6164 for (j = 0; j < mpt->m_num_phys; j++) {
6165 if (mpt->m_phy_info[j].attached_devhdl &&
6166 (mpt->m_phy_info[j].port_num == current_port)) {
6167 phy_mask |= (1 << j);
6168 }
6169 }
6170 mask = mask | phy_mask;
6171
6172 for (j = 0; j < mpt->m_num_phys; j++) {
6173 if ((phy_mask >> j) & 0x01) {
6174 mpt->m_phy_info[j].phy_mask = phy_mask;
6175 }
6176 }
6177
6178 (void) sprintf(phy_mask_name, "%x", phy_mask);
6179
6180 mutex_exit(&mpt->m_mutex);
6181 /*
6182 * register a iport, if the port has already been existed
6183 * SCSA will do nothing and just return.
6184 */
6185 (void) scsi_hba_iport_register(mpt->m_dip, phy_mask_name);
6186 mutex_enter(&mpt->m_mutex);
6187 }
6188 kmem_free(phy_mask_name, MPTSAS_MAX_PHYS);
6189 NDBG20(("mptsas%d update phymask return", mpt->m_instance));
6190 }
6191
6192 /*
6193 * mptsas_handle_dr is a task handler for DR, the DR action includes:
6194 * 1. Directly attched Device Added/Removed.
6195 * 2. Expander Device Added/Removed.
6196 * 3. Indirectly Attached Device Added/Expander.
6197 * 4. LUNs of a existing device status change.
6198 * 5. RAID volume created/deleted.
6199 * 6. Member of RAID volume is released because of RAID deletion.
6200 * 7. Physical disks are removed because of RAID creation.
6201 */
6202 static void
6203 mptsas_handle_dr(void *args)
6204 {
6205 mptsas_topo_change_list_t *topo_node = NULL;
6206 mptsas_topo_change_list_t *save_node = NULL;
6207 mptsas_t *mpt;
6208 dev_info_t *parent = NULL;
6209 mptsas_phymask_t phymask = 0;
6210 char *phy_mask_name;
6211 uint8_t flags = 0, physport = 0xff;
6212 uint8_t port_update = 0;
6213 uint_t event;
6214
6215 topo_node = (mptsas_topo_change_list_t *)args;
6216
6217 mpt = topo_node->mpt;
6218 event = topo_node->event;
6219 flags = topo_node->flags;
6220
6221 phy_mask_name = kmem_zalloc(MPTSAS_MAX_PHYS, KM_SLEEP);
6222
6223 NDBG20(("mptsas%d handle_dr enter", mpt->m_instance));
6224
6225 switch (event) {
6226 case MPTSAS_DR_EVENT_RECONFIG_TARGET:
6227 if ((flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) ||
6228 (flags == MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE) ||
6229 (flags == MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED)) {
6230 /*
6231 * Direct attached or expander attached device added
6232 * into system or a Phys Disk that is being unhidden.
6233 */
6234 port_update = 1;
6235 }
6236 break;
6237 case MPTSAS_DR_EVENT_RECONFIG_SMP:
6238 /*
6239 * New expander added into system, it must be the head
6240 * of topo_change_list_t
6241 */
6242 port_update = 1;
6243 break;
6244 default:
6245 port_update = 0;
6246 break;
6247 }
6248 /*
6249 * All cases port_update == 1 may cause initiator port form change
6250 */
6251 mutex_enter(&mpt->m_mutex);
6252 if (mpt->m_port_chng && port_update) {
6253 /*
6254 * mpt->m_port_chng flag indicates some PHYs of initiator
6255 * port have changed to online. So when expander added or
6256 * directly attached device online event come, we force to
6257 * update port information by issueing SAS IO Unit Page and
6258 * update PHYMASKs.
6259 */
6260 (void) mptsas_update_phymask(mpt);
6261 mpt->m_port_chng = 0;
6262
6263 }
6264 mutex_exit(&mpt->m_mutex);
6265 while (topo_node) {
6266 phymask = 0;
6267 if (parent == NULL) {
6268 physport = topo_node->un.physport;
6269 event = topo_node->event;
6270 flags = topo_node->flags;
6271 if (event & (MPTSAS_DR_EVENT_OFFLINE_TARGET |
6272 MPTSAS_DR_EVENT_OFFLINE_SMP)) {
6273 /*
6274 * For all offline events, phymask is known
6275 */
6276 phymask = topo_node->un.phymask;
6277 goto find_parent;
6278 }
6279 if (event & MPTSAS_TOPO_FLAG_REMOVE_HANDLE) {
6280 goto handle_topo_change;
6281 }
6282 if (flags & MPTSAS_TOPO_FLAG_LUN_ASSOCIATED) {
6283 phymask = topo_node->un.phymask;
6284 goto find_parent;
6285 }
6286
6287 if ((flags ==
6288 MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED) &&
6289 (event == MPTSAS_DR_EVENT_RECONFIG_TARGET)) {
6290 /*
6291 * There is no any field in IR_CONFIG_CHANGE
6292 * event indicate physport/phynum, let's get
6293 * parent after SAS Device Page0 request.
6294 */
6295 goto handle_topo_change;
6296 }
6297
6298 mutex_enter(&mpt->m_mutex);
6299 if (flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) {
6300 /*
6301 * If the direct attached device added or a
6302 * phys disk is being unhidden, argument
6303 * physport actually is PHY#, so we have to get
6304 * phymask according PHY#.
6305 */
6306 physport = mpt->m_phy_info[physport].port_num;
6307 }
6308
6309 /*
6310 * Translate physport to phymask so that we can search
6311 * parent dip.
6312 */
6313 phymask = mptsas_physport_to_phymask(mpt,
6314 physport);
6315 mutex_exit(&mpt->m_mutex);
6316
6317 find_parent:
6318 bzero(phy_mask_name, MPTSAS_MAX_PHYS);
6319 /*
6320 * For RAID topology change node, write the iport name
6321 * as v0.
6322 */
6323 if (flags & MPTSAS_TOPO_FLAG_RAID_ASSOCIATED) {
6324 (void) sprintf(phy_mask_name, "v0");
6325 } else {
6326 /*
6327 * phymask can bo 0 if the drive has been
6328 * pulled by the time an add event is
6329 * processed. If phymask is 0, just skip this
6330 * event and continue.
6331 */
6332 if (phymask == 0) {
6333 mutex_enter(&mpt->m_mutex);
6334 save_node = topo_node;
6335 topo_node = topo_node->next;
6336 ASSERT(save_node);
6337 kmem_free(save_node,
6338 sizeof (mptsas_topo_change_list_t));
6339 mutex_exit(&mpt->m_mutex);
6340
6341 parent = NULL;
6342 continue;
6343 }
6344 (void) sprintf(phy_mask_name, "%x", phymask);
6345 }
6346 parent = scsi_hba_iport_find(mpt->m_dip,
6347 phy_mask_name);
6348 if (parent == NULL) {
6349 mptsas_log(mpt, CE_WARN, "Failed to find an "
6350 "iport, should not happen!");
6351 goto out;
6352 }
6353
6354 }
6355 ASSERT(parent);
6356 handle_topo_change:
6357
6358 mutex_enter(&mpt->m_mutex);
6359 /*
6360 * If HBA is being reset, don't perform operations depending
6361 * on the IOC. We must free the topo list, however.
6362 */
6363
6364 mutex_enter(&mpt->m_taskmgmt_mutex);
6365 if (mpt->m_in_reset == FALSE)
6366 mptsas_handle_topo_change(topo_node, parent);
6367 mutex_exit(&mpt->m_taskmgmt_mutex);
6368
6369 save_node = topo_node;
6370 topo_node = topo_node->next;
6371 ASSERT(save_node);
6372 kmem_free(save_node, sizeof (mptsas_topo_change_list_t));
6373 mutex_exit(&mpt->m_mutex);
6374
6375 if ((flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) ||
6376 (flags == MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED) ||
6377 (flags == MPTSAS_TOPO_FLAG_RAID_ASSOCIATED)) {
6378 /*
6379 * If direct attached device associated, make sure
6380 * reset the parent before start the next one. But
6381 * all devices associated with expander shares the
6382 * parent. Also, reset parent if this is for RAID.
6383 */
6384 parent = NULL;
6385 }
6386 }
6387 out:
6388 kmem_free(phy_mask_name, MPTSAS_MAX_PHYS);
6389 }
6390
6391 static void
6392 mptsas_handle_topo_change(mptsas_topo_change_list_t *topo_node,
6393 dev_info_t *parent)
6394 {
6395 mptsas_target_t *ptgt = NULL;
6396 mptsas_smp_t *psmp = NULL;
6397 mptsas_t *mpt = (void *)topo_node->mpt;
6398 uint16_t devhdl;
6399 uint16_t attached_devhdl;
6400 uint64_t sas_wwn = 0;
6401 int rval = 0;
6402 uint32_t page_address;
6403 uint8_t phy, flags;
6404 char *addr = NULL;
6405 dev_info_t *lundip;
6406 int circ = 0, circ1 = 0;
6407 char attached_wwnstr[MPTSAS_WWN_STRLEN];
6408
6409 NDBG20(("mptsas%d handle_topo_change enter, devhdl 0x%x,"
6410 "event 0x%x, flags 0x%x", mpt->m_instance, topo_node->devhdl,
6411 topo_node->event, topo_node->flags));
6412
6413 ASSERT(mutex_owned(&mpt->m_mutex));
6414
6415 switch (topo_node->event) {
6416 case MPTSAS_DR_EVENT_RECONFIG_TARGET:
6417 {
6418 char *phy_mask_name;
6419 mptsas_phymask_t phymask = 0;
6420
6421 if (topo_node->flags == MPTSAS_TOPO_FLAG_RAID_ASSOCIATED) {
6422 /*
6423 * Get latest RAID info.
6424 */
6425 (void) mptsas_get_raid_info(mpt);
6426 ptgt = refhash_linear_search(mpt->m_targets,
6427 mptsas_target_eval_devhdl, &topo_node->devhdl);
6428 if (ptgt == NULL)
6429 break;
6430 } else {
6431 ptgt = (void *)topo_node->object;
6432 }
6433
6434 if (ptgt == NULL) {
6435 /*
6436 * If a Phys Disk was deleted, RAID info needs to be
6437 * updated to reflect the new topology.
6438 */
6439 (void) mptsas_get_raid_info(mpt);
6440
6441 /*
6442 * Get sas device page 0 by DevHandle to make sure if
6443 * SSP/SATA end device exist.
6444 */
6445 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE &
6446 MPI2_SAS_DEVICE_PGAD_FORM_MASK) |
6447 topo_node->devhdl;
6448
6449 rval = mptsas_get_target_device_info(mpt, page_address,
6450 &devhdl, &ptgt);
6451 if (rval == DEV_INFO_WRONG_DEVICE_TYPE) {
6452 mptsas_log(mpt, CE_NOTE,
6453 "mptsas_handle_topo_change: target %d is "
6454 "not a SAS/SATA device. \n",
6455 topo_node->devhdl);
6456 } else if (rval == DEV_INFO_FAIL_ALLOC) {
6457 mptsas_log(mpt, CE_NOTE,
6458 "mptsas_handle_topo_change: could not "
6459 "allocate memory. \n");
6460 } else if (rval == DEV_INFO_FAIL_GUID) {
6461 mptsas_log(mpt, CE_NOTE,
6462 "mptsas_handle_topo_change: could not "
6463 "get SATA GUID for target %d. \n",
6464 topo_node->devhdl);
6465 }
6466 /*
6467 * If rval is DEV_INFO_PHYS_DISK or indicates failure
6468 * then there is nothing else to do, just leave.
6469 */
6470 if (rval != DEV_INFO_SUCCESS) {
6471 return;
6472 }
6473 }
6474
6475 ASSERT(ptgt->m_devhdl == topo_node->devhdl);
6476
6477 mutex_exit(&mpt->m_mutex);
6478 flags = topo_node->flags;
6479
6480 if (flags == MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED) {
6481 phymask = ptgt->m_addr.mta_phymask;
6482 phy_mask_name = kmem_zalloc(MPTSAS_MAX_PHYS, KM_SLEEP);
6483 (void) sprintf(phy_mask_name, "%x", phymask);
6484 parent = scsi_hba_iport_find(mpt->m_dip,
6485 phy_mask_name);
6486 kmem_free(phy_mask_name, MPTSAS_MAX_PHYS);
6487 if (parent == NULL) {
6488 mptsas_log(mpt, CE_WARN, "Failed to find a "
6489 "iport for PD, should not happen!");
6490 mutex_enter(&mpt->m_mutex);
6491 break;
6492 }
6493 }
6494
6495 if (flags == MPTSAS_TOPO_FLAG_RAID_ASSOCIATED) {
6496 ndi_devi_enter(parent, &circ1);
6497 (void) mptsas_config_raid(parent, topo_node->devhdl,
6498 &lundip);
6499 ndi_devi_exit(parent, circ1);
6500 } else {
6501 /*
6502 * hold nexus for bus configure
6503 */
6504 ndi_devi_enter(scsi_vhci_dip, &circ);
6505 ndi_devi_enter(parent, &circ1);
6506 rval = mptsas_config_target(parent, ptgt);
6507 /*
6508 * release nexus for bus configure
6509 */
6510 ndi_devi_exit(parent, circ1);
6511 ndi_devi_exit(scsi_vhci_dip, circ);
6512
6513 /*
6514 * Add parent's props for SMHBA support
6515 */
6516 if (flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) {
6517 bzero(attached_wwnstr,
6518 sizeof (attached_wwnstr));
6519 (void) sprintf(attached_wwnstr, "w%016"PRIx64,
6520 ptgt->m_addr.mta_wwn);
6521 if (ddi_prop_update_string(DDI_DEV_T_NONE,
6522 parent,
6523 SCSI_ADDR_PROP_ATTACHED_PORT,
6524 attached_wwnstr)
6525 != DDI_PROP_SUCCESS) {
6526 (void) ddi_prop_remove(DDI_DEV_T_NONE,
6527 parent,
6528 SCSI_ADDR_PROP_ATTACHED_PORT);
6529 mptsas_log(mpt, CE_WARN, "Failed to"
6530 "attached-port props");
6531 return;
6532 }
6533 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent,
6534 MPTSAS_NUM_PHYS, 1) !=
6535 DDI_PROP_SUCCESS) {
6536 (void) ddi_prop_remove(DDI_DEV_T_NONE,
6537 parent, MPTSAS_NUM_PHYS);
6538 mptsas_log(mpt, CE_WARN, "Failed to"
6539 " create num-phys props");
6540 return;
6541 }
6542
6543 /*
6544 * Update PHY info for smhba
6545 */
6546 mutex_enter(&mpt->m_mutex);
6547 if (mptsas_smhba_phy_init(mpt)) {
6548 mutex_exit(&mpt->m_mutex);
6549 mptsas_log(mpt, CE_WARN, "mptsas phy"
6550 " update failed");
6551 return;
6552 }
6553 mutex_exit(&mpt->m_mutex);
6554
6555 /*
6556 * topo_node->un.physport is really the PHY#
6557 * for direct attached devices
6558 */
6559 mptsas_smhba_set_one_phy_props(mpt, parent,
6560 topo_node->un.physport, &attached_devhdl);
6561
6562 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent,
6563 MPTSAS_VIRTUAL_PORT, 0) !=
6564 DDI_PROP_SUCCESS) {
6565 (void) ddi_prop_remove(DDI_DEV_T_NONE,
6566 parent, MPTSAS_VIRTUAL_PORT);
6567 mptsas_log(mpt, CE_WARN,
6568 "mptsas virtual-port"
6569 "port prop update failed");
6570 return;
6571 }
6572 }
6573 }
6574 mutex_enter(&mpt->m_mutex);
6575
6576 NDBG20(("mptsas%d handle_topo_change to online devhdl:%x, "
6577 "phymask:%x.", mpt->m_instance, ptgt->m_devhdl,
6578 ptgt->m_addr.mta_phymask));
6579 break;
6580 }
6581 case MPTSAS_DR_EVENT_OFFLINE_TARGET:
6582 {
6583 devhdl = topo_node->devhdl;
6584 ptgt = refhash_linear_search(mpt->m_targets,
6585 mptsas_target_eval_devhdl, &devhdl);
6586 if (ptgt == NULL)
6587 break;
6588
6589 sas_wwn = ptgt->m_addr.mta_wwn;
6590 phy = ptgt->m_phynum;
6591
6592 addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
6593
6594 if (sas_wwn) {
6595 (void) sprintf(addr, "w%016"PRIx64, sas_wwn);
6596 } else {
6597 (void) sprintf(addr, "p%x", phy);
6598 }
6599 ASSERT(ptgt->m_devhdl == devhdl);
6600
6601 if ((topo_node->flags == MPTSAS_TOPO_FLAG_RAID_ASSOCIATED) ||
6602 (topo_node->flags ==
6603 MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED)) {
6604 /*
6605 * Get latest RAID info if RAID volume status changes
6606 * or Phys Disk status changes
6607 */
6608 (void) mptsas_get_raid_info(mpt);
6609 }
6610 /*
6611 * Abort all outstanding command on the device
6612 */
6613 rval = mptsas_do_scsi_reset(mpt, devhdl);
6614 if (rval) {
6615 NDBG20(("mptsas%d handle_topo_change to reset target "
6616 "before offline devhdl:%x, phymask:%x, rval:%x",
6617 mpt->m_instance, ptgt->m_devhdl,
6618 ptgt->m_addr.mta_phymask, rval));
6619 }
6620
6621 mutex_exit(&mpt->m_mutex);
6622
6623 ndi_devi_enter(scsi_vhci_dip, &circ);
6624 ndi_devi_enter(parent, &circ1);
6625 rval = mptsas_offline_target(parent, addr);
6626 ndi_devi_exit(parent, circ1);
6627 ndi_devi_exit(scsi_vhci_dip, circ);
6628 NDBG20(("mptsas%d handle_topo_change to offline devhdl:%x, "
6629 "phymask:%x, rval:%x", mpt->m_instance,
6630 ptgt->m_devhdl, ptgt->m_addr.mta_phymask, rval));
6631
6632 kmem_free(addr, SCSI_MAXNAMELEN);
6633
6634 /*
6635 * Clear parent's props for SMHBA support
6636 */
6637 flags = topo_node->flags;
6638 if (flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) {
6639 bzero(attached_wwnstr, sizeof (attached_wwnstr));
6640 if (ddi_prop_update_string(DDI_DEV_T_NONE, parent,
6641 SCSI_ADDR_PROP_ATTACHED_PORT, attached_wwnstr) !=
6642 DDI_PROP_SUCCESS) {
6643 (void) ddi_prop_remove(DDI_DEV_T_NONE, parent,
6644 SCSI_ADDR_PROP_ATTACHED_PORT);
6645 mptsas_log(mpt, CE_WARN, "mptsas attached port "
6646 "prop update failed");
6647 break;
6648 }
6649 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent,
6650 MPTSAS_NUM_PHYS, 0) !=
6651 DDI_PROP_SUCCESS) {
6652 (void) ddi_prop_remove(DDI_DEV_T_NONE, parent,
6653 MPTSAS_NUM_PHYS);
6654 mptsas_log(mpt, CE_WARN, "mptsas num phys "
6655 "prop update failed");
6656 break;
6657 }
6658 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent,
6659 MPTSAS_VIRTUAL_PORT, 1) !=
6660 DDI_PROP_SUCCESS) {
6661 (void) ddi_prop_remove(DDI_DEV_T_NONE, parent,
6662 MPTSAS_VIRTUAL_PORT);
6663 mptsas_log(mpt, CE_WARN, "mptsas virtual port "
6664 "prop update failed");
6665 break;
6666 }
6667 }
6668
6669 mutex_enter(&mpt->m_mutex);
6670 ptgt->m_led_status = 0;
6671 (void) mptsas_flush_led_status(mpt, ptgt);
6672 if (rval == DDI_SUCCESS) {
6673 refhash_remove(mpt->m_targets, ptgt);
6674 ptgt = NULL;
6675 } else {
6676 /*
6677 * clean DR_INTRANSITION flag to allow I/O down to
6678 * PHCI driver since failover finished.
6679 * Invalidate the devhdl
6680 */
6681 ptgt->m_devhdl = MPTSAS_INVALID_DEVHDL;
6682 ptgt->m_tgt_unconfigured = 0;
6683 mutex_enter(&mpt->m_tx_waitq_mutex);
6684 ptgt->m_dr_flag = MPTSAS_DR_INACTIVE;
6685 mutex_exit(&mpt->m_tx_waitq_mutex);
6686 }
6687
6688 /*
6689 * Send SAS IO Unit Control to free the dev handle
6690 */
6691 if ((flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) ||
6692 (flags == MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE)) {
6693 rval = mptsas_free_devhdl(mpt, devhdl);
6694
6695 NDBG20(("mptsas%d handle_topo_change to remove "
6696 "devhdl:%x, rval:%x", mpt->m_instance, devhdl,
6697 rval));
6698 }
6699
6700 break;
6701 }
6702 case MPTSAS_TOPO_FLAG_REMOVE_HANDLE:
6703 {
6704 devhdl = topo_node->devhdl;
6705 /*
6706 * If this is the remove handle event, do a reset first.
6707 */
6708 if (topo_node->event == MPTSAS_TOPO_FLAG_REMOVE_HANDLE) {
6709 rval = mptsas_do_scsi_reset(mpt, devhdl);
6710 if (rval) {
6711 NDBG20(("mpt%d reset target before remove "
6712 "devhdl:%x, rval:%x", mpt->m_instance,
6713 devhdl, rval));
6714 }
6715 }
6716
6717 /*
6718 * Send SAS IO Unit Control to free the dev handle
6719 */
6720 rval = mptsas_free_devhdl(mpt, devhdl);
6721 NDBG20(("mptsas%d handle_topo_change to remove "
6722 "devhdl:%x, rval:%x", mpt->m_instance, devhdl,
6723 rval));
6724 break;
6725 }
6726 case MPTSAS_DR_EVENT_RECONFIG_SMP:
6727 {
6728 mptsas_smp_t smp;
6729 dev_info_t *smpdip;
6730
6731 devhdl = topo_node->devhdl;
6732
6733 page_address = (MPI2_SAS_EXPAND_PGAD_FORM_HNDL &
6734 MPI2_SAS_EXPAND_PGAD_FORM_MASK) | (uint32_t)devhdl;
6735 rval = mptsas_get_sas_expander_page0(mpt, page_address, &smp);
6736 if (rval != DDI_SUCCESS) {
6737 mptsas_log(mpt, CE_WARN, "failed to online smp, "
6738 "handle %x", devhdl);
6739 return;
6740 }
6741
6742 psmp = mptsas_smp_alloc(mpt, &smp);
6743 if (psmp == NULL) {
6744 return;
6745 }
6746
6747 mutex_exit(&mpt->m_mutex);
6748 ndi_devi_enter(parent, &circ1);
6749 (void) mptsas_online_smp(parent, psmp, &smpdip);
6750 ndi_devi_exit(parent, circ1);
6751
6752 mutex_enter(&mpt->m_mutex);
6753 break;
6754 }
6755 case MPTSAS_DR_EVENT_OFFLINE_SMP:
6756 {
6757 devhdl = topo_node->devhdl;
6758 uint32_t dev_info;
6759
6760 psmp = refhash_linear_search(mpt->m_smp_targets,
6761 mptsas_smp_eval_devhdl, &devhdl);
6762 if (psmp == NULL)
6763 break;
6764 /*
6765 * The mptsas_smp_t data is released only if the dip is offlined
6766 * successfully.
6767 */
6768 mutex_exit(&mpt->m_mutex);
6769
6770 ndi_devi_enter(parent, &circ1);
6771 rval = mptsas_offline_smp(parent, psmp, NDI_DEVI_REMOVE);
6772 ndi_devi_exit(parent, circ1);
6773
6774 dev_info = psmp->m_deviceinfo;
6775 if ((dev_info & DEVINFO_DIRECT_ATTACHED) ==
6776 DEVINFO_DIRECT_ATTACHED) {
6777 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent,
6778 MPTSAS_VIRTUAL_PORT, 1) !=
6779 DDI_PROP_SUCCESS) {
6780 (void) ddi_prop_remove(DDI_DEV_T_NONE, parent,
6781 MPTSAS_VIRTUAL_PORT);
6782 mptsas_log(mpt, CE_WARN, "mptsas virtual port "
6783 "prop update failed");
6784 return;
6785 }
6786 /*
6787 * Check whether the smp connected to the iport,
6788 */
6789 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent,
6790 MPTSAS_NUM_PHYS, 0) !=
6791 DDI_PROP_SUCCESS) {
6792 (void) ddi_prop_remove(DDI_DEV_T_NONE, parent,
6793 MPTSAS_NUM_PHYS);
6794 mptsas_log(mpt, CE_WARN, "mptsas num phys"
6795 "prop update failed");
6796 return;
6797 }
6798 /*
6799 * Clear parent's attached-port props
6800 */
6801 bzero(attached_wwnstr, sizeof (attached_wwnstr));
6802 if (ddi_prop_update_string(DDI_DEV_T_NONE, parent,
6803 SCSI_ADDR_PROP_ATTACHED_PORT, attached_wwnstr) !=
6804 DDI_PROP_SUCCESS) {
6805 (void) ddi_prop_remove(DDI_DEV_T_NONE, parent,
6806 SCSI_ADDR_PROP_ATTACHED_PORT);
6807 mptsas_log(mpt, CE_WARN, "mptsas attached port "
6808 "prop update failed");
6809 return;
6810 }
6811 }
6812
6813 mutex_enter(&mpt->m_mutex);
6814 NDBG20(("mptsas%d handle_topo_change to remove devhdl:%x, "
6815 "rval:%x", mpt->m_instance, psmp->m_devhdl, rval));
6816 if (rval == DDI_SUCCESS) {
6817 refhash_remove(mpt->m_smp_targets, psmp);
6818 } else {
6819 psmp->m_devhdl = MPTSAS_INVALID_DEVHDL;
6820 }
6821
6822 bzero(attached_wwnstr, sizeof (attached_wwnstr));
6823
6824 break;
6825 }
6826 default:
6827 return;
6828 }
6829 }
6830
6831 /*
6832 * Record the event if its type is enabled in mpt instance by ioctl.
6833 */
6834 static void
6835 mptsas_record_event(void *args)
6836 {
6837 m_replyh_arg_t *replyh_arg;
6838 pMpi2EventNotificationReply_t eventreply;
6839 uint32_t event, rfm;
6840 mptsas_t *mpt;
6841 int i, j;
6842 uint16_t event_data_len;
6843 boolean_t sendAEN = FALSE;
6844
6845 replyh_arg = (m_replyh_arg_t *)args;
6846 rfm = replyh_arg->rfm;
6847 mpt = replyh_arg->mpt;
6848
6849 eventreply = (pMpi2EventNotificationReply_t)
6850 (mpt->m_reply_frame + (rfm -
6851 (mpt->m_reply_frame_dma_addr & 0xffffffffu)));
6852 event = ddi_get16(mpt->m_acc_reply_frame_hdl, &eventreply->Event);
6853
6854
6855 /*
6856 * Generate a system event to let anyone who cares know that a
6857 * LOG_ENTRY_ADDED event has occurred. This is sent no matter what the
6858 * event mask is set to.
6859 */
6860 if (event == MPI2_EVENT_LOG_ENTRY_ADDED) {
6861 sendAEN = TRUE;
6862 }
6863
6864 /*
6865 * Record the event only if it is not masked. Determine which dword
6866 * and bit of event mask to test.
6867 */
6868 i = (uint8_t)(event / 32);
6869 j = (uint8_t)(event % 32);
6870 if ((i < 4) && ((1 << j) & mpt->m_event_mask[i])) {
6871 i = mpt->m_event_index;
6872 mpt->m_events[i].Type = event;
6873 mpt->m_events[i].Number = ++mpt->m_event_number;
6874 bzero(mpt->m_events[i].Data, MPTSAS_MAX_EVENT_DATA_LENGTH * 4);
6875 event_data_len = ddi_get16(mpt->m_acc_reply_frame_hdl,
6876 &eventreply->EventDataLength);
6877
6878 if (event_data_len > 0) {
6879 /*
6880 * Limit data to size in m_event entry
6881 */
6882 if (event_data_len > MPTSAS_MAX_EVENT_DATA_LENGTH) {
6883 event_data_len = MPTSAS_MAX_EVENT_DATA_LENGTH;
6884 }
6885 for (j = 0; j < event_data_len; j++) {
6886 mpt->m_events[i].Data[j] =
6887 ddi_get32(mpt->m_acc_reply_frame_hdl,
6888 &(eventreply->EventData[j]));
6889 }
6890
6891 /*
6892 * check for index wrap-around
6893 */
6894 if (++i == MPTSAS_EVENT_QUEUE_SIZE) {
6895 i = 0;
6896 }
6897 mpt->m_event_index = (uint8_t)i;
6898
6899 /*
6900 * Set flag to send the event.
6901 */
6902 sendAEN = TRUE;
6903 }
6904 }
6905
6906 /*
6907 * Generate a system event if flag is set to let anyone who cares know
6908 * that an event has occurred.
6909 */
6910 if (sendAEN) {
6911 (void) ddi_log_sysevent(mpt->m_dip, DDI_VENDOR_LSI, "MPT_SAS",
6912 "SAS", NULL, NULL, DDI_NOSLEEP);
6913 }
6914 }
6915
6916 #define SMP_RESET_IN_PROGRESS MPI2_EVENT_SAS_TOPO_LR_SMP_RESET_IN_PROGRESS
6917 /*
6918 * handle sync events from ioc in interrupt
6919 * return value:
6920 * DDI_SUCCESS: The event is handled by this func
6921 * DDI_FAILURE: Event is not handled
6922 */
6923 static int
6924 mptsas_handle_event_sync(void *args)
6925 {
6926 m_replyh_arg_t *replyh_arg;
6927 pMpi2EventNotificationReply_t eventreply;
6928 uint32_t event, rfm;
6929 mptsas_t *mpt;
6930 uint_t iocstatus;
6931
6932 replyh_arg = (m_replyh_arg_t *)args;
6933 rfm = replyh_arg->rfm;
6934 mpt = replyh_arg->mpt;
6935
6936 ASSERT(mutex_owned(&mpt->m_mutex));
6937
6938 eventreply = (pMpi2EventNotificationReply_t)
6939 (mpt->m_reply_frame + (rfm -
6940 (mpt->m_reply_frame_dma_addr & 0xffffffffu)));
6941 event = ddi_get16(mpt->m_acc_reply_frame_hdl, &eventreply->Event);
6942
6943 if (iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl,
6944 &eventreply->IOCStatus)) {
6945 if (iocstatus == MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) {
6946 mptsas_log(mpt, CE_WARN,
6947 "!mptsas_handle_event_sync: event 0x%x, "
6948 "IOCStatus=0x%x, "
6949 "IOCLogInfo=0x%x", event, iocstatus,
6950 ddi_get32(mpt->m_acc_reply_frame_hdl,
6951 &eventreply->IOCLogInfo));
6952 } else {
6953 mptsas_log(mpt, CE_WARN,
6954 "mptsas_handle_event_sync: event 0x%x, "
6955 "IOCStatus=0x%x, "
6956 "(IOCLogInfo=0x%x)", event, iocstatus,
6957 ddi_get32(mpt->m_acc_reply_frame_hdl,
6958 &eventreply->IOCLogInfo));
6959 }
6960 }
6961
6962 /*
6963 * figure out what kind of event we got and handle accordingly
6964 */
6965 switch (event) {
6966 case MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST:
6967 {
6968 pMpi2EventDataSasTopologyChangeList_t sas_topo_change_list;
6969 uint8_t num_entries, expstatus, phy;
6970 uint8_t phystatus, physport, state, i;
6971 uint8_t start_phy_num, link_rate;
6972 uint16_t dev_handle, reason_code;
6973 uint16_t enc_handle, expd_handle;
6974 char string[80], curr[80], prev[80];
6975 mptsas_topo_change_list_t *topo_head = NULL;
6976 mptsas_topo_change_list_t *topo_tail = NULL;
6977 mptsas_topo_change_list_t *topo_node = NULL;
6978 mptsas_target_t *ptgt;
6979 mptsas_smp_t *psmp;
6980 uint8_t flags = 0, exp_flag;
6981 smhba_info_t *pSmhba = NULL;
6982
6983 NDBG20(("mptsas_handle_event_sync: SAS topology change"));
6984
6985 sas_topo_change_list = (pMpi2EventDataSasTopologyChangeList_t)
6986 eventreply->EventData;
6987
6988 enc_handle = ddi_get16(mpt->m_acc_reply_frame_hdl,
6989 &sas_topo_change_list->EnclosureHandle);
6990 expd_handle = ddi_get16(mpt->m_acc_reply_frame_hdl,
6991 &sas_topo_change_list->ExpanderDevHandle);
6992 num_entries = ddi_get8(mpt->m_acc_reply_frame_hdl,
6993 &sas_topo_change_list->NumEntries);
6994 start_phy_num = ddi_get8(mpt->m_acc_reply_frame_hdl,
6995 &sas_topo_change_list->StartPhyNum);
6996 expstatus = ddi_get8(mpt->m_acc_reply_frame_hdl,
6997 &sas_topo_change_list->ExpStatus);
6998 physport = ddi_get8(mpt->m_acc_reply_frame_hdl,
6999 &sas_topo_change_list->PhysicalPort);
7000
7001 string[0] = 0;
7002 if (expd_handle) {
7003 flags = MPTSAS_TOPO_FLAG_EXPANDER_ASSOCIATED;
7004 switch (expstatus) {
7005 case MPI2_EVENT_SAS_TOPO_ES_ADDED:
7006 (void) sprintf(string, " added");
7007 /*
7008 * New expander device added
7009 */
7010 mpt->m_port_chng = 1;
7011 topo_node = kmem_zalloc(
7012 sizeof (mptsas_topo_change_list_t),
7013 KM_SLEEP);
7014 topo_node->mpt = mpt;
7015 topo_node->event = MPTSAS_DR_EVENT_RECONFIG_SMP;
7016 topo_node->un.physport = physport;
7017 topo_node->devhdl = expd_handle;
7018 topo_node->flags = flags;
7019 topo_node->object = NULL;
7020 if (topo_head == NULL) {
7021 topo_head = topo_tail = topo_node;
7022 } else {
7023 topo_tail->next = topo_node;
7024 topo_tail = topo_node;
7025 }
7026 break;
7027 case MPI2_EVENT_SAS_TOPO_ES_NOT_RESPONDING:
7028 (void) sprintf(string, " not responding, "
7029 "removed");
7030 psmp = refhash_linear_search(mpt->m_smp_targets,
7031 mptsas_smp_eval_devhdl, &expd_handle);
7032 if (psmp == NULL)
7033 break;
7034
7035 topo_node = kmem_zalloc(
7036 sizeof (mptsas_topo_change_list_t),
7037 KM_SLEEP);
7038 topo_node->mpt = mpt;
7039 topo_node->un.phymask =
7040 psmp->m_addr.mta_phymask;
7041 topo_node->event = MPTSAS_DR_EVENT_OFFLINE_SMP;
7042 topo_node->devhdl = expd_handle;
7043 topo_node->flags = flags;
7044 topo_node->object = NULL;
7045 if (topo_head == NULL) {
7046 topo_head = topo_tail = topo_node;
7047 } else {
7048 topo_tail->next = topo_node;
7049 topo_tail = topo_node;
7050 }
7051 break;
7052 case MPI2_EVENT_SAS_TOPO_ES_RESPONDING:
7053 break;
7054 case MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING:
7055 (void) sprintf(string, " not responding, "
7056 "delaying removal");
7057 break;
7058 default:
7059 break;
7060 }
7061 } else {
7062 flags = MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE;
7063 }
7064
7065 NDBG20(("SAS TOPOLOGY CHANGE for enclosure %x expander %x%s\n",
7066 enc_handle, expd_handle, string));
7067 for (i = 0; i < num_entries; i++) {
7068 phy = i + start_phy_num;
7069 phystatus = ddi_get8(mpt->m_acc_reply_frame_hdl,
7070 &sas_topo_change_list->PHY[i].PhyStatus);
7071 dev_handle = ddi_get16(mpt->m_acc_reply_frame_hdl,
7072 &sas_topo_change_list->PHY[i].AttachedDevHandle);
7073 reason_code = phystatus & MPI2_EVENT_SAS_TOPO_RC_MASK;
7074 /*
7075 * Filter out processing of Phy Vacant Status unless
7076 * the reason code is "Not Responding". Process all
7077 * other combinations of Phy Status and Reason Codes.
7078 */
7079 if ((phystatus &
7080 MPI2_EVENT_SAS_TOPO_PHYSTATUS_VACANT) &&
7081 (reason_code !=
7082 MPI2_EVENT_SAS_TOPO_RC_TARG_NOT_RESPONDING)) {
7083 continue;
7084 }
7085 curr[0] = 0;
7086 prev[0] = 0;
7087 string[0] = 0;
7088 switch (reason_code) {
7089 case MPI2_EVENT_SAS_TOPO_RC_TARG_ADDED:
7090 {
7091 NDBG20(("mptsas%d phy %d physical_port %d "
7092 "dev_handle %d added", mpt->m_instance, phy,
7093 physport, dev_handle));
7094 link_rate = ddi_get8(mpt->m_acc_reply_frame_hdl,
7095 &sas_topo_change_list->PHY[i].LinkRate);
7096 state = (link_rate &
7097 MPI2_EVENT_SAS_TOPO_LR_CURRENT_MASK) >>
7098 MPI2_EVENT_SAS_TOPO_LR_CURRENT_SHIFT;
7099 switch (state) {
7100 case MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED:
7101 (void) sprintf(curr, "is disabled");
7102 break;
7103 case MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED:
7104 (void) sprintf(curr, "is offline, "
7105 "failed speed negotiation");
7106 break;
7107 case MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE:
7108 (void) sprintf(curr, "SATA OOB "
7109 "complete");
7110 break;
7111 case SMP_RESET_IN_PROGRESS:
7112 (void) sprintf(curr, "SMP reset in "
7113 "progress");
7114 break;
7115 case MPI2_EVENT_SAS_TOPO_LR_RATE_1_5:
7116 (void) sprintf(curr, "is online at "
7117 "1.5 Gbps");
7118 break;
7119 case MPI2_EVENT_SAS_TOPO_LR_RATE_3_0:
7120 (void) sprintf(curr, "is online at 3.0 "
7121 "Gbps");
7122 break;
7123 case MPI2_EVENT_SAS_TOPO_LR_RATE_6_0:
7124 (void) sprintf(curr, "is online at 6.0 "
7125 "Gbps");
7126 break;
7127 case MPI25_EVENT_SAS_TOPO_LR_RATE_12_0:
7128 (void) sprintf(curr,
7129 "is online at 12.0 Gbps");
7130 break;
7131 default:
7132 (void) sprintf(curr, "state is "
7133 "unknown");
7134 break;
7135 }
7136 /*
7137 * New target device added into the system.
7138 * Set association flag according to if an
7139 * expander is used or not.
7140 */
7141 exp_flag =
7142 MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE;
7143 if (flags ==
7144 MPTSAS_TOPO_FLAG_EXPANDER_ASSOCIATED) {
7145 flags = exp_flag;
7146 }
7147 topo_node = kmem_zalloc(
7148 sizeof (mptsas_topo_change_list_t),
7149 KM_SLEEP);
7150 topo_node->mpt = mpt;
7151 topo_node->event =
7152 MPTSAS_DR_EVENT_RECONFIG_TARGET;
7153 if (expd_handle == 0) {
7154 /*
7155 * Per MPI 2, if expander dev handle
7156 * is 0, it's a directly attached
7157 * device. So driver use PHY to decide
7158 * which iport is associated
7159 */
7160 physport = phy;
7161 mpt->m_port_chng = 1;
7162 }
7163 topo_node->un.physport = physport;
7164 topo_node->devhdl = dev_handle;
7165 topo_node->flags = flags;
7166 topo_node->object = NULL;
7167 if (topo_head == NULL) {
7168 topo_head = topo_tail = topo_node;
7169 } else {
7170 topo_tail->next = topo_node;
7171 topo_tail = topo_node;
7172 }
7173 break;
7174 }
7175 case MPI2_EVENT_SAS_TOPO_RC_TARG_NOT_RESPONDING:
7176 {
7177 NDBG20(("mptsas%d phy %d physical_port %d "
7178 "dev_handle %d removed", mpt->m_instance,
7179 phy, physport, dev_handle));
7180 /*
7181 * Set association flag according to if an
7182 * expander is used or not.
7183 */
7184 exp_flag =
7185 MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE;
7186 if (flags ==
7187 MPTSAS_TOPO_FLAG_EXPANDER_ASSOCIATED) {
7188 flags = exp_flag;
7189 }
7190 /*
7191 * Target device is removed from the system
7192 * Before the device is really offline from
7193 * from system.
7194 */
7195 ptgt = refhash_linear_search(mpt->m_targets,
7196 mptsas_target_eval_devhdl, &dev_handle);
7197 /*
7198 * If ptgt is NULL here, it means that the
7199 * DevHandle is not in the hash table. This is
7200 * reasonable sometimes. For example, if a
7201 * disk was pulled, then added, then pulled
7202 * again, the disk will not have been put into
7203 * the hash table because the add event will
7204 * have an invalid phymask. BUT, this does not
7205 * mean that the DevHandle is invalid. The
7206 * controller will still have a valid DevHandle
7207 * that must be removed. To do this, use the
7208 * MPTSAS_TOPO_FLAG_REMOVE_HANDLE event.
7209 */
7210 if (ptgt == NULL) {
7211 topo_node = kmem_zalloc(
7212 sizeof (mptsas_topo_change_list_t),
7213 KM_SLEEP);
7214 topo_node->mpt = mpt;
7215 topo_node->un.phymask = 0;
7216 topo_node->event =
7217 MPTSAS_TOPO_FLAG_REMOVE_HANDLE;
7218 topo_node->devhdl = dev_handle;
7219 topo_node->flags = flags;
7220 topo_node->object = NULL;
7221 if (topo_head == NULL) {
7222 topo_head = topo_tail =
7223 topo_node;
7224 } else {
7225 topo_tail->next = topo_node;
7226 topo_tail = topo_node;
7227 }
7228 break;
7229 }
7230
7231 /*
7232 * Update DR flag immediately avoid I/O failure
7233 * before failover finish. Pay attention to the
7234 * mutex protect, we need grab m_tx_waitq_mutex
7235 * during set m_dr_flag because we won't add
7236 * the following command into waitq, instead,
7237 * we need return TRAN_BUSY in the tran_start
7238 * context.
7239 */
7240 mutex_enter(&mpt->m_tx_waitq_mutex);
7241 ptgt->m_dr_flag = MPTSAS_DR_INTRANSITION;
7242 mutex_exit(&mpt->m_tx_waitq_mutex);
7243
7244 topo_node = kmem_zalloc(
7245 sizeof (mptsas_topo_change_list_t),
7246 KM_SLEEP);
7247 topo_node->mpt = mpt;
7248 topo_node->un.phymask =
7249 ptgt->m_addr.mta_phymask;
7250 topo_node->event =
7251 MPTSAS_DR_EVENT_OFFLINE_TARGET;
7252 topo_node->devhdl = dev_handle;
7253 topo_node->flags = flags;
7254 topo_node->object = NULL;
7255 if (topo_head == NULL) {
7256 topo_head = topo_tail = topo_node;
7257 } else {
7258 topo_tail->next = topo_node;
7259 topo_tail = topo_node;
7260 }
7261 break;
7262 }
7263 case MPI2_EVENT_SAS_TOPO_RC_PHY_CHANGED:
7264 link_rate = ddi_get8(mpt->m_acc_reply_frame_hdl,
7265 &sas_topo_change_list->PHY[i].LinkRate);
7266 state = (link_rate &
7267 MPI2_EVENT_SAS_TOPO_LR_CURRENT_MASK) >>
7268 MPI2_EVENT_SAS_TOPO_LR_CURRENT_SHIFT;
7269 pSmhba = &mpt->m_phy_info[i].smhba_info;
7270 pSmhba->negotiated_link_rate = state;
7271 switch (state) {
7272 case MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED:
7273 (void) sprintf(curr, "is disabled");
7274 mptsas_smhba_log_sysevent(mpt,
7275 ESC_SAS_PHY_EVENT,
7276 SAS_PHY_REMOVE,
7277 &mpt->m_phy_info[i].smhba_info);
7278 mpt->m_phy_info[i].smhba_info.
7279 negotiated_link_rate
7280 = 0x1;
7281 break;
7282 case MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED:
7283 (void) sprintf(curr, "is offline, "
7284 "failed speed negotiation");
7285 mptsas_smhba_log_sysevent(mpt,
7286 ESC_SAS_PHY_EVENT,
7287 SAS_PHY_OFFLINE,
7288 &mpt->m_phy_info[i].smhba_info);
7289 break;
7290 case MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE:
7291 (void) sprintf(curr, "SATA OOB "
7292 "complete");
7293 break;
7294 case SMP_RESET_IN_PROGRESS:
7295 (void) sprintf(curr, "SMP reset in "
7296 "progress");
7297 break;
7298 case MPI2_EVENT_SAS_TOPO_LR_RATE_1_5:
7299 (void) sprintf(curr, "is online at "
7300 "1.5 Gbps");
7301 if ((expd_handle == 0) &&
7302 (enc_handle == 1)) {
7303 mpt->m_port_chng = 1;
7304 }
7305 mptsas_smhba_log_sysevent(mpt,
7306 ESC_SAS_PHY_EVENT,
7307 SAS_PHY_ONLINE,
7308 &mpt->m_phy_info[i].smhba_info);
7309 break;
7310 case MPI2_EVENT_SAS_TOPO_LR_RATE_3_0:
7311 (void) sprintf(curr, "is online at 3.0 "
7312 "Gbps");
7313 if ((expd_handle == 0) &&
7314 (enc_handle == 1)) {
7315 mpt->m_port_chng = 1;
7316 }
7317 mptsas_smhba_log_sysevent(mpt,
7318 ESC_SAS_PHY_EVENT,
7319 SAS_PHY_ONLINE,
7320 &mpt->m_phy_info[i].smhba_info);
7321 break;
7322 case MPI2_EVENT_SAS_TOPO_LR_RATE_6_0:
7323 (void) sprintf(curr, "is online at "
7324 "6.0 Gbps");
7325 if ((expd_handle == 0) &&
7326 (enc_handle == 1)) {
7327 mpt->m_port_chng = 1;
7328 }
7329 mptsas_smhba_log_sysevent(mpt,
7330 ESC_SAS_PHY_EVENT,
7331 SAS_PHY_ONLINE,
7332 &mpt->m_phy_info[i].smhba_info);
7333 break;
7334 case MPI25_EVENT_SAS_TOPO_LR_RATE_12_0:
7335 (void) sprintf(curr, "is online at "
7336 "12.0 Gbps");
7337 if ((expd_handle == 0) &&
7338 (enc_handle == 1)) {
7339 mpt->m_port_chng = 1;
7340 }
7341 mptsas_smhba_log_sysevent(mpt,
7342 ESC_SAS_PHY_EVENT,
7343 SAS_PHY_ONLINE,
7344 &mpt->m_phy_info[i].smhba_info);
7345 break;
7346 default:
7347 (void) sprintf(curr, "state is "
7348 "unknown");
7349 break;
7350 }
7351
7352 state = (link_rate &
7353 MPI2_EVENT_SAS_TOPO_LR_PREV_MASK) >>
7354 MPI2_EVENT_SAS_TOPO_LR_PREV_SHIFT;
7355 switch (state) {
7356 case MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED:
7357 (void) sprintf(prev, ", was disabled");
7358 break;
7359 case MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED:
7360 (void) sprintf(prev, ", was offline, "
7361 "failed speed negotiation");
7362 break;
7363 case MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE:
7364 (void) sprintf(prev, ", was SATA OOB "
7365 "complete");
7366 break;
7367 case SMP_RESET_IN_PROGRESS:
7368 (void) sprintf(prev, ", was SMP reset "
7369 "in progress");
7370 break;
7371 case MPI2_EVENT_SAS_TOPO_LR_RATE_1_5:
7372 (void) sprintf(prev, ", was online at "
7373 "1.5 Gbps");
7374 break;
7375 case MPI2_EVENT_SAS_TOPO_LR_RATE_3_0:
7376 (void) sprintf(prev, ", was online at "
7377 "3.0 Gbps");
7378 break;
7379 case MPI2_EVENT_SAS_TOPO_LR_RATE_6_0:
7380 (void) sprintf(prev, ", was online at "
7381 "6.0 Gbps");
7382 break;
7383 case MPI25_EVENT_SAS_TOPO_LR_RATE_12_0:
7384 (void) sprintf(prev, ", was online at "
7385 "12.0 Gbps");
7386 break;
7387 default:
7388 break;
7389 }
7390 (void) sprintf(&string[strlen(string)], "link "
7391 "changed, ");
7392 break;
7393 case MPI2_EVENT_SAS_TOPO_RC_NO_CHANGE:
7394 continue;
7395 case MPI2_EVENT_SAS_TOPO_RC_DELAY_NOT_RESPONDING:
7396 (void) sprintf(&string[strlen(string)],
7397 "target not responding, delaying "
7398 "removal");
7399 break;
7400 }
7401 NDBG20(("mptsas%d phy %d DevHandle %x, %s%s%s\n",
7402 mpt->m_instance, phy, dev_handle, string, curr,
7403 prev));
7404 }
7405 if (topo_head != NULL) {
7406 /*
7407 * Launch DR taskq to handle topology change
7408 */
7409 if ((ddi_taskq_dispatch(mpt->m_dr_taskq,
7410 mptsas_handle_dr, (void *)topo_head,
7411 DDI_NOSLEEP)) != DDI_SUCCESS) {
7412 while (topo_head != NULL) {
7413 topo_node = topo_head;
7414 topo_head = topo_head->next;
7415 kmem_free(topo_node,
7416 sizeof (mptsas_topo_change_list_t));
7417 }
7418 mptsas_log(mpt, CE_NOTE, "mptsas start taskq "
7419 "for handle SAS DR event failed. \n");
7420 }
7421 }
7422 break;
7423 }
7424 case MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST:
7425 {
7426 Mpi2EventDataIrConfigChangeList_t *irChangeList;
7427 mptsas_topo_change_list_t *topo_head = NULL;
7428 mptsas_topo_change_list_t *topo_tail = NULL;
7429 mptsas_topo_change_list_t *topo_node = NULL;
7430 mptsas_target_t *ptgt;
7431 uint8_t num_entries, i, reason;
7432 uint16_t volhandle, diskhandle;
7433
7434 irChangeList = (pMpi2EventDataIrConfigChangeList_t)
7435 eventreply->EventData;
7436 num_entries = ddi_get8(mpt->m_acc_reply_frame_hdl,
7437 &irChangeList->NumElements);
7438
7439 NDBG20(("mptsas%d IR_CONFIGURATION_CHANGE_LIST event received",
7440 mpt->m_instance));
7441
7442 for (i = 0; i < num_entries; i++) {
7443 reason = ddi_get8(mpt->m_acc_reply_frame_hdl,
7444 &irChangeList->ConfigElement[i].ReasonCode);
7445 volhandle = ddi_get16(mpt->m_acc_reply_frame_hdl,
7446 &irChangeList->ConfigElement[i].VolDevHandle);
7447 diskhandle = ddi_get16(mpt->m_acc_reply_frame_hdl,
7448 &irChangeList->ConfigElement[i].PhysDiskDevHandle);
7449
7450 switch (reason) {
7451 case MPI2_EVENT_IR_CHANGE_RC_ADDED:
7452 case MPI2_EVENT_IR_CHANGE_RC_VOLUME_CREATED:
7453 {
7454 NDBG20(("mptsas %d volume added\n",
7455 mpt->m_instance));
7456
7457 topo_node = kmem_zalloc(
7458 sizeof (mptsas_topo_change_list_t),
7459 KM_SLEEP);
7460
7461 topo_node->mpt = mpt;
7462 topo_node->event =
7463 MPTSAS_DR_EVENT_RECONFIG_TARGET;
7464 topo_node->un.physport = 0xff;
7465 topo_node->devhdl = volhandle;
7466 topo_node->flags =
7467 MPTSAS_TOPO_FLAG_RAID_ASSOCIATED;
7468 topo_node->object = NULL;
7469 if (topo_head == NULL) {
7470 topo_head = topo_tail = topo_node;
7471 } else {
7472 topo_tail->next = topo_node;
7473 topo_tail = topo_node;
7474 }
7475 break;
7476 }
7477 case MPI2_EVENT_IR_CHANGE_RC_REMOVED:
7478 case MPI2_EVENT_IR_CHANGE_RC_VOLUME_DELETED:
7479 {
7480 NDBG20(("mptsas %d volume deleted\n",
7481 mpt->m_instance));
7482 ptgt = refhash_linear_search(mpt->m_targets,
7483 mptsas_target_eval_devhdl, &volhandle);
7484 if (ptgt == NULL)
7485 break;
7486
7487 /*
7488 * Clear any flags related to volume
7489 */
7490 (void) mptsas_delete_volume(mpt, volhandle);
7491
7492 /*
7493 * Update DR flag immediately avoid I/O failure
7494 */
7495 mutex_enter(&mpt->m_tx_waitq_mutex);
7496 ptgt->m_dr_flag = MPTSAS_DR_INTRANSITION;
7497 mutex_exit(&mpt->m_tx_waitq_mutex);
7498
7499 topo_node = kmem_zalloc(
7500 sizeof (mptsas_topo_change_list_t),
7501 KM_SLEEP);
7502 topo_node->mpt = mpt;
7503 topo_node->un.phymask =
7504 ptgt->m_addr.mta_phymask;
7505 topo_node->event =
7506 MPTSAS_DR_EVENT_OFFLINE_TARGET;
7507 topo_node->devhdl = volhandle;
7508 topo_node->flags =
7509 MPTSAS_TOPO_FLAG_RAID_ASSOCIATED;
7510 topo_node->object = (void *)ptgt;
7511 if (topo_head == NULL) {
7512 topo_head = topo_tail = topo_node;
7513 } else {
7514 topo_tail->next = topo_node;
7515 topo_tail = topo_node;
7516 }
7517 break;
7518 }
7519 case MPI2_EVENT_IR_CHANGE_RC_PD_CREATED:
7520 case MPI2_EVENT_IR_CHANGE_RC_HIDE:
7521 {
7522 ptgt = refhash_linear_search(mpt->m_targets,
7523 mptsas_target_eval_devhdl, &diskhandle);
7524 if (ptgt == NULL)
7525 break;
7526
7527 /*
7528 * Update DR flag immediately avoid I/O failure
7529 */
7530 mutex_enter(&mpt->m_tx_waitq_mutex);
7531 ptgt->m_dr_flag = MPTSAS_DR_INTRANSITION;
7532 mutex_exit(&mpt->m_tx_waitq_mutex);
7533
7534 topo_node = kmem_zalloc(
7535 sizeof (mptsas_topo_change_list_t),
7536 KM_SLEEP);
7537 topo_node->mpt = mpt;
7538 topo_node->un.phymask =
7539 ptgt->m_addr.mta_phymask;
7540 topo_node->event =
7541 MPTSAS_DR_EVENT_OFFLINE_TARGET;
7542 topo_node->devhdl = diskhandle;
7543 topo_node->flags =
7544 MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED;
7545 topo_node->object = (void *)ptgt;
7546 if (topo_head == NULL) {
7547 topo_head = topo_tail = topo_node;
7548 } else {
7549 topo_tail->next = topo_node;
7550 topo_tail = topo_node;
7551 }
7552 break;
7553 }
7554 case MPI2_EVENT_IR_CHANGE_RC_UNHIDE:
7555 case MPI2_EVENT_IR_CHANGE_RC_PD_DELETED:
7556 {
7557 /*
7558 * The physical drive is released by a IR
7559 * volume. But we cannot get the the physport
7560 * or phynum from the event data, so we only
7561 * can get the physport/phynum after SAS
7562 * Device Page0 request for the devhdl.
7563 */
7564 topo_node = kmem_zalloc(
7565 sizeof (mptsas_topo_change_list_t),
7566 KM_SLEEP);
7567 topo_node->mpt = mpt;
7568 topo_node->un.phymask = 0;
7569 topo_node->event =
7570 MPTSAS_DR_EVENT_RECONFIG_TARGET;
7571 topo_node->devhdl = diskhandle;
7572 topo_node->flags =
7573 MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED;
7574 topo_node->object = NULL;
7575 mpt->m_port_chng = 1;
7576 if (topo_head == NULL) {
7577 topo_head = topo_tail = topo_node;
7578 } else {
7579 topo_tail->next = topo_node;
7580 topo_tail = topo_node;
7581 }
7582 break;
7583 }
7584 default:
7585 break;
7586 }
7587 }
7588
7589 if (topo_head != NULL) {
7590 /*
7591 * Launch DR taskq to handle topology change
7592 */
7593 if ((ddi_taskq_dispatch(mpt->m_dr_taskq,
7594 mptsas_handle_dr, (void *)topo_head,
7595 DDI_NOSLEEP)) != DDI_SUCCESS) {
7596 while (topo_head != NULL) {
7597 topo_node = topo_head;
7598 topo_head = topo_head->next;
7599 kmem_free(topo_node,
7600 sizeof (mptsas_topo_change_list_t));
7601 }
7602 mptsas_log(mpt, CE_NOTE, "mptsas start taskq "
7603 "for handle SAS DR event failed. \n");
7604 }
7605 }
7606 break;
7607 }
7608 default:
7609 return (DDI_FAILURE);
7610 }
7611
7612 return (DDI_SUCCESS);
7613 }
7614
7615 /*
7616 * handle events from ioc
7617 */
7618 static void
7619 mptsas_handle_event(void *args)
7620 {
7621 m_replyh_arg_t *replyh_arg;
7622 pMpi2EventNotificationReply_t eventreply;
7623 uint32_t event, iocloginfo, rfm;
7624 uint32_t status;
7625 uint8_t port;
7626 mptsas_t *mpt;
7627 uint_t iocstatus;
7628
7629 replyh_arg = (m_replyh_arg_t *)args;
7630 rfm = replyh_arg->rfm;
7631 mpt = replyh_arg->mpt;
7632
7633 mutex_enter(&mpt->m_mutex);
7634 /*
7635 * If HBA is being reset, drop incoming event.
7636 */
7637 mutex_enter(&mpt->m_taskmgmt_mutex);
7638 if (mpt->m_in_reset == TRUE) {
7639 NDBG20(("dropping event received prior to reset"));
7640 mutex_exit(&mpt->m_taskmgmt_mutex);
7641 mutex_exit(&mpt->m_mutex);
7642 return;
7643 }
7644 mutex_exit(&mpt->m_taskmgmt_mutex);
7645
7646 eventreply = (pMpi2EventNotificationReply_t)
7647 (mpt->m_reply_frame + (rfm -
7648 (mpt->m_reply_frame_dma_addr & 0xffffffffu)));
7649 event = ddi_get16(mpt->m_acc_reply_frame_hdl, &eventreply->Event);
7650
7651 if (iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl,
7652 &eventreply->IOCStatus)) {
7653 if (iocstatus == MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) {
7654 mptsas_log(mpt, CE_WARN,
7655 "!mptsas_handle_event: IOCStatus=0x%x, "
7656 "IOCLogInfo=0x%x", iocstatus,
7657 ddi_get32(mpt->m_acc_reply_frame_hdl,
7658 &eventreply->IOCLogInfo));
7659 } else {
7660 mptsas_log(mpt, CE_WARN,
7661 "mptsas_handle_event: IOCStatus=0x%x, "
7662 "IOCLogInfo=0x%x", iocstatus,
7663 ddi_get32(mpt->m_acc_reply_frame_hdl,
7664 &eventreply->IOCLogInfo));
7665 }
7666 }
7667
7668 /*
7669 * figure out what kind of event we got and handle accordingly
7670 */
7671 switch (event) {
7672 case MPI2_EVENT_LOG_ENTRY_ADDED:
7673 break;
7674 case MPI2_EVENT_LOG_DATA:
7675 iocloginfo = ddi_get32(mpt->m_acc_reply_frame_hdl,
7676 &eventreply->IOCLogInfo);
7677 NDBG20(("mptsas %d log info %x received.\n", mpt->m_instance,
7678 iocloginfo));
7679 break;
7680 case MPI2_EVENT_STATE_CHANGE:
7681 NDBG20(("mptsas%d state change.", mpt->m_instance));
7682 break;
7683 case MPI2_EVENT_HARD_RESET_RECEIVED:
7684 NDBG20(("mptsas%d event change.", mpt->m_instance));
7685 break;
7686 case MPI2_EVENT_SAS_DISCOVERY:
7687 {
7688 MPI2_EVENT_DATA_SAS_DISCOVERY *sasdiscovery;
7689 char string[80];
7690 uint8_t rc;
7691
7692 sasdiscovery =
7693 (pMpi2EventDataSasDiscovery_t)eventreply->EventData;
7694
7695 rc = ddi_get8(mpt->m_acc_reply_frame_hdl,
7696 &sasdiscovery->ReasonCode);
7697 port = ddi_get8(mpt->m_acc_reply_frame_hdl,
7698 &sasdiscovery->PhysicalPort);
7699 status = ddi_get32(mpt->m_acc_reply_frame_hdl,
7700 &sasdiscovery->DiscoveryStatus);
7701
7702 string[0] = 0;
7703 switch (rc) {
7704 case MPI2_EVENT_SAS_DISC_RC_STARTED:
7705 (void) sprintf(string, "STARTING");
7706 break;
7707 case MPI2_EVENT_SAS_DISC_RC_COMPLETED:
7708 (void) sprintf(string, "COMPLETED");
7709 break;
7710 default:
7711 (void) sprintf(string, "UNKNOWN");
7712 break;
7713 }
7714
7715 NDBG20(("SAS DISCOVERY is %s for port %d, status %x", string,
7716 port, status));
7717
7718 break;
7719 }
7720 case MPI2_EVENT_EVENT_CHANGE:
7721 NDBG20(("mptsas%d event change.", mpt->m_instance));
7722 break;
7723 case MPI2_EVENT_TASK_SET_FULL:
7724 {
7725 pMpi2EventDataTaskSetFull_t taskfull;
7726
7727 taskfull = (pMpi2EventDataTaskSetFull_t)eventreply->EventData;
7728
7729 NDBG20(("TASK_SET_FULL received for mptsas%d, depth %d\n",
7730 mpt->m_instance, ddi_get16(mpt->m_acc_reply_frame_hdl,
7731 &taskfull->CurrentDepth)));
7732 break;
7733 }
7734 case MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST:
7735 {
7736 /*
7737 * SAS TOPOLOGY CHANGE LIST Event has already been handled
7738 * in mptsas_handle_event_sync() of interrupt context
7739 */
7740 break;
7741 }
7742 case MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE:
7743 {
7744 pMpi2EventDataSasEnclDevStatusChange_t encstatus;
7745 uint8_t rc;
7746 char string[80];
7747
7748 encstatus = (pMpi2EventDataSasEnclDevStatusChange_t)
7749 eventreply->EventData;
7750
7751 rc = ddi_get8(mpt->m_acc_reply_frame_hdl,
7752 &encstatus->ReasonCode);
7753 switch (rc) {
7754 case MPI2_EVENT_SAS_ENCL_RC_ADDED:
7755 (void) sprintf(string, "added");
7756 break;
7757 case MPI2_EVENT_SAS_ENCL_RC_NOT_RESPONDING:
7758 (void) sprintf(string, ", not responding");
7759 break;
7760 default:
7761 break;
7762 }
7763 NDBG20(("mptsas%d ENCLOSURE STATUS CHANGE for enclosure "
7764 "%x%s\n", mpt->m_instance,
7765 ddi_get16(mpt->m_acc_reply_frame_hdl,
7766 &encstatus->EnclosureHandle), string));
7767 break;
7768 }
7769
7770 /*
7771 * MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE is handled by
7772 * mptsas_handle_event_sync,in here just send ack message.
7773 */
7774 case MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE:
7775 {
7776 pMpi2EventDataSasDeviceStatusChange_t statuschange;
7777 uint8_t rc;
7778 uint16_t devhdl;
7779 uint64_t wwn = 0;
7780 uint32_t wwn_lo, wwn_hi;
7781
7782 statuschange = (pMpi2EventDataSasDeviceStatusChange_t)
7783 eventreply->EventData;
7784 rc = ddi_get8(mpt->m_acc_reply_frame_hdl,
7785 &statuschange->ReasonCode);
7786 wwn_lo = ddi_get32(mpt->m_acc_reply_frame_hdl,
7787 (uint32_t *)(void *)&statuschange->SASAddress);
7788 wwn_hi = ddi_get32(mpt->m_acc_reply_frame_hdl,
7789 (uint32_t *)(void *)&statuschange->SASAddress + 1);
7790 wwn = ((uint64_t)wwn_hi << 32) | wwn_lo;
7791 devhdl = ddi_get16(mpt->m_acc_reply_frame_hdl,
7792 &statuschange->DevHandle);
7793
7794 NDBG13(("MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE wwn is %"PRIx64,
7795 wwn));
7796
7797 switch (rc) {
7798 case MPI2_EVENT_SAS_DEV_STAT_RC_SMART_DATA:
7799 NDBG20(("SMART data received, ASC/ASCQ = %02x/%02x",
7800 ddi_get8(mpt->m_acc_reply_frame_hdl,
7801 &statuschange->ASC),
7802 ddi_get8(mpt->m_acc_reply_frame_hdl,
7803 &statuschange->ASCQ)));
7804 break;
7805
7806 case MPI2_EVENT_SAS_DEV_STAT_RC_UNSUPPORTED:
7807 NDBG20(("Device not supported"));
7808 break;
7809
7810 case MPI2_EVENT_SAS_DEV_STAT_RC_INTERNAL_DEVICE_RESET:
7811 NDBG20(("IOC internally generated the Target Reset "
7812 "for devhdl:%x", devhdl));
7813 break;
7814
7815 case MPI2_EVENT_SAS_DEV_STAT_RC_CMP_INTERNAL_DEV_RESET:
7816 NDBG20(("IOC's internally generated Target Reset "
7817 "completed for devhdl:%x", devhdl));
7818 break;
7819
7820 case MPI2_EVENT_SAS_DEV_STAT_RC_TASK_ABORT_INTERNAL:
7821 NDBG20(("IOC internally generated Abort Task"));
7822 break;
7823
7824 case MPI2_EVENT_SAS_DEV_STAT_RC_CMP_TASK_ABORT_INTERNAL:
7825 NDBG20(("IOC's internally generated Abort Task "
7826 "completed"));
7827 break;
7828
7829 case MPI2_EVENT_SAS_DEV_STAT_RC_ABORT_TASK_SET_INTERNAL:
7830 NDBG20(("IOC internally generated Abort Task Set"));
7831 break;
7832
7833 case MPI2_EVENT_SAS_DEV_STAT_RC_CLEAR_TASK_SET_INTERNAL:
7834 NDBG20(("IOC internally generated Clear Task Set"));
7835 break;
7836
7837 case MPI2_EVENT_SAS_DEV_STAT_RC_QUERY_TASK_INTERNAL:
7838 NDBG20(("IOC internally generated Query Task"));
7839 break;
7840
7841 case MPI2_EVENT_SAS_DEV_STAT_RC_ASYNC_NOTIFICATION:
7842 NDBG20(("Device sent an Asynchronous Notification"));
7843 break;
7844
7845 default:
7846 break;
7847 }
7848 break;
7849 }
7850 case MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST:
7851 {
7852 /*
7853 * IR TOPOLOGY CHANGE LIST Event has already been handled
7854 * in mpt_handle_event_sync() of interrupt context
7855 */
7856 break;
7857 }
7858 case MPI2_EVENT_IR_OPERATION_STATUS:
7859 {
7860 Mpi2EventDataIrOperationStatus_t *irOpStatus;
7861 char reason_str[80];
7862 uint8_t rc, percent;
7863 uint16_t handle;
7864
7865 irOpStatus = (pMpi2EventDataIrOperationStatus_t)
7866 eventreply->EventData;
7867 rc = ddi_get8(mpt->m_acc_reply_frame_hdl,
7868 &irOpStatus->RAIDOperation);
7869 percent = ddi_get8(mpt->m_acc_reply_frame_hdl,
7870 &irOpStatus->PercentComplete);
7871 handle = ddi_get16(mpt->m_acc_reply_frame_hdl,
7872 &irOpStatus->VolDevHandle);
7873
7874 switch (rc) {
7875 case MPI2_EVENT_IR_RAIDOP_RESYNC:
7876 (void) sprintf(reason_str, "resync");
7877 break;
7878 case MPI2_EVENT_IR_RAIDOP_ONLINE_CAP_EXPANSION:
7879 (void) sprintf(reason_str, "online capacity "
7880 "expansion");
7881 break;
7882 case MPI2_EVENT_IR_RAIDOP_CONSISTENCY_CHECK:
7883 (void) sprintf(reason_str, "consistency check");
7884 break;
7885 default:
7886 (void) sprintf(reason_str, "unknown reason %x",
7887 rc);
7888 }
7889
7890 NDBG20(("mptsas%d raid operational status: (%s)"
7891 "\thandle(0x%04x), percent complete(%d)\n",
7892 mpt->m_instance, reason_str, handle, percent));
7893 break;
7894 }
7895 case MPI2_EVENT_SAS_BROADCAST_PRIMITIVE:
7896 {
7897 pMpi2EventDataSasBroadcastPrimitive_t sas_broadcast;
7898 uint8_t phy_num;
7899 uint8_t primitive;
7900
7901 sas_broadcast = (pMpi2EventDataSasBroadcastPrimitive_t)
7902 eventreply->EventData;
7903
7904 phy_num = ddi_get8(mpt->m_acc_reply_frame_hdl,
7905 &sas_broadcast->PhyNum);
7906 primitive = ddi_get8(mpt->m_acc_reply_frame_hdl,
7907 &sas_broadcast->Primitive);
7908
7909 switch (primitive) {
7910 case MPI2_EVENT_PRIMITIVE_CHANGE:
7911 mptsas_smhba_log_sysevent(mpt,
7912 ESC_SAS_HBA_PORT_BROADCAST,
7913 SAS_PORT_BROADCAST_CHANGE,
7914 &mpt->m_phy_info[phy_num].smhba_info);
7915 break;
7916 case MPI2_EVENT_PRIMITIVE_SES:
7917 mptsas_smhba_log_sysevent(mpt,
7918 ESC_SAS_HBA_PORT_BROADCAST,
7919 SAS_PORT_BROADCAST_SES,
7920 &mpt->m_phy_info[phy_num].smhba_info);
7921 break;
7922 case MPI2_EVENT_PRIMITIVE_EXPANDER:
7923 mptsas_smhba_log_sysevent(mpt,
7924 ESC_SAS_HBA_PORT_BROADCAST,
7925 SAS_PORT_BROADCAST_D01_4,
7926 &mpt->m_phy_info[phy_num].smhba_info);
7927 break;
7928 case MPI2_EVENT_PRIMITIVE_ASYNCHRONOUS_EVENT:
7929 mptsas_smhba_log_sysevent(mpt,
7930 ESC_SAS_HBA_PORT_BROADCAST,
7931 SAS_PORT_BROADCAST_D04_7,
7932 &mpt->m_phy_info[phy_num].smhba_info);
7933 break;
7934 case MPI2_EVENT_PRIMITIVE_RESERVED3:
7935 mptsas_smhba_log_sysevent(mpt,
7936 ESC_SAS_HBA_PORT_BROADCAST,
7937 SAS_PORT_BROADCAST_D16_7,
7938 &mpt->m_phy_info[phy_num].smhba_info);
7939 break;
7940 case MPI2_EVENT_PRIMITIVE_RESERVED4:
7941 mptsas_smhba_log_sysevent(mpt,
7942 ESC_SAS_HBA_PORT_BROADCAST,
7943 SAS_PORT_BROADCAST_D29_7,
7944 &mpt->m_phy_info[phy_num].smhba_info);
7945 break;
7946 case MPI2_EVENT_PRIMITIVE_CHANGE0_RESERVED:
7947 mptsas_smhba_log_sysevent(mpt,
7948 ESC_SAS_HBA_PORT_BROADCAST,
7949 SAS_PORT_BROADCAST_D24_0,
7950 &mpt->m_phy_info[phy_num].smhba_info);
7951 break;
7952 case MPI2_EVENT_PRIMITIVE_CHANGE1_RESERVED:
7953 mptsas_smhba_log_sysevent(mpt,
7954 ESC_SAS_HBA_PORT_BROADCAST,
7955 SAS_PORT_BROADCAST_D27_4,
7956 &mpt->m_phy_info[phy_num].smhba_info);
7957 break;
7958 default:
7959 NDBG16(("mptsas%d: unknown BROADCAST PRIMITIVE"
7960 " %x received",
7961 mpt->m_instance, primitive));
7962 break;
7963 }
7964 NDBG16(("mptsas%d sas broadcast primitive: "
7965 "\tprimitive(0x%04x), phy(%d) complete\n",
7966 mpt->m_instance, primitive, phy_num));
7967 break;
7968 }
7969 case MPI2_EVENT_IR_VOLUME:
7970 {
7971 Mpi2EventDataIrVolume_t *irVolume;
7972 uint16_t devhandle;
7973 uint32_t state;
7974 int config, vol;
7975 uint8_t found = FALSE;
7976
7977 irVolume = (pMpi2EventDataIrVolume_t)eventreply->EventData;
7978 state = ddi_get32(mpt->m_acc_reply_frame_hdl,
7979 &irVolume->NewValue);
7980 devhandle = ddi_get16(mpt->m_acc_reply_frame_hdl,
7981 &irVolume->VolDevHandle);
7982
7983 NDBG20(("EVENT_IR_VOLUME event is received"));
7984
7985 /*
7986 * Get latest RAID info and then find the DevHandle for this
7987 * event in the configuration. If the DevHandle is not found
7988 * just exit the event.
7989 */
7990 (void) mptsas_get_raid_info(mpt);
7991 for (config = 0; (config < mpt->m_num_raid_configs) &&
7992 (!found); config++) {
7993 for (vol = 0; vol < MPTSAS_MAX_RAIDVOLS; vol++) {
7994 if (mpt->m_raidconfig[config].m_raidvol[vol].
7995 m_raidhandle == devhandle) {
7996 found = TRUE;
7997 break;
7998 }
7999 }
8000 }
8001 if (!found) {
8002 break;
8003 }
8004
8005 switch (irVolume->ReasonCode) {
8006 case MPI2_EVENT_IR_VOLUME_RC_SETTINGS_CHANGED:
8007 {
8008 uint32_t i;
8009 mpt->m_raidconfig[config].m_raidvol[vol].m_settings =
8010 state;
8011
8012 i = state & MPI2_RAIDVOL0_SETTING_MASK_WRITE_CACHING;
8013 mptsas_log(mpt, CE_NOTE, " Volume %d settings changed"
8014 ", auto-config of hot-swap drives is %s"
8015 ", write caching is %s"
8016 ", hot-spare pool mask is %02x\n",
8017 vol, state &
8018 MPI2_RAIDVOL0_SETTING_AUTO_CONFIG_HSWAP_DISABLE
8019 ? "disabled" : "enabled",
8020 i == MPI2_RAIDVOL0_SETTING_UNCHANGED
8021 ? "controlled by member disks" :
8022 i == MPI2_RAIDVOL0_SETTING_DISABLE_WRITE_CACHING
8023 ? "disabled" :
8024 i == MPI2_RAIDVOL0_SETTING_ENABLE_WRITE_CACHING
8025 ? "enabled" :
8026 "incorrectly set",
8027 (state >> 16) & 0xff);
8028 break;
8029 }
8030 case MPI2_EVENT_IR_VOLUME_RC_STATE_CHANGED:
8031 {
8032 mpt->m_raidconfig[config].m_raidvol[vol].m_state =
8033 (uint8_t)state;
8034
8035 mptsas_log(mpt, CE_NOTE,
8036 "Volume %d is now %s\n", vol,
8037 state == MPI2_RAID_VOL_STATE_OPTIMAL
8038 ? "optimal" :
8039 state == MPI2_RAID_VOL_STATE_DEGRADED
8040 ? "degraded" :
8041 state == MPI2_RAID_VOL_STATE_ONLINE
8042 ? "online" :
8043 state == MPI2_RAID_VOL_STATE_INITIALIZING
8044 ? "initializing" :
8045 state == MPI2_RAID_VOL_STATE_FAILED
8046 ? "failed" :
8047 state == MPI2_RAID_VOL_STATE_MISSING
8048 ? "missing" :
8049 "state unknown");
8050 break;
8051 }
8052 case MPI2_EVENT_IR_VOLUME_RC_STATUS_FLAGS_CHANGED:
8053 {
8054 mpt->m_raidconfig[config].m_raidvol[vol].
8055 m_statusflags = state;
8056
8057 mptsas_log(mpt, CE_NOTE,
8058 " Volume %d is now %s%s%s%s%s%s%s%s%s\n",
8059 vol,
8060 state & MPI2_RAIDVOL0_STATUS_FLAG_ENABLED
8061 ? ", enabled" : ", disabled",
8062 state & MPI2_RAIDVOL0_STATUS_FLAG_QUIESCED
8063 ? ", quiesced" : "",
8064 state & MPI2_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE
8065 ? ", inactive" : ", active",
8066 state &
8067 MPI2_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL
8068 ? ", bad block table is full" : "",
8069 state &
8070 MPI2_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS
8071 ? ", resync in progress" : "",
8072 state & MPI2_RAIDVOL0_STATUS_FLAG_BACKGROUND_INIT
8073 ? ", background initialization in progress" : "",
8074 state &
8075 MPI2_RAIDVOL0_STATUS_FLAG_CAPACITY_EXPANSION
8076 ? ", capacity expansion in progress" : "",
8077 state &
8078 MPI2_RAIDVOL0_STATUS_FLAG_CONSISTENCY_CHECK
8079 ? ", consistency check in progress" : "",
8080 state & MPI2_RAIDVOL0_STATUS_FLAG_DATA_SCRUB
8081 ? ", data scrub in progress" : "");
8082 break;
8083 }
8084 default:
8085 break;
8086 }
8087 break;
8088 }
8089 case MPI2_EVENT_IR_PHYSICAL_DISK:
8090 {
8091 Mpi2EventDataIrPhysicalDisk_t *irPhysDisk;
8092 uint16_t devhandle, enchandle, slot;
8093 uint32_t status, state;
8094 uint8_t physdisknum, reason;
8095
8096 irPhysDisk = (Mpi2EventDataIrPhysicalDisk_t *)
8097 eventreply->EventData;
8098 physdisknum = ddi_get8(mpt->m_acc_reply_frame_hdl,
8099 &irPhysDisk->PhysDiskNum);
8100 devhandle = ddi_get16(mpt->m_acc_reply_frame_hdl,
8101 &irPhysDisk->PhysDiskDevHandle);
8102 enchandle = ddi_get16(mpt->m_acc_reply_frame_hdl,
8103 &irPhysDisk->EnclosureHandle);
8104 slot = ddi_get16(mpt->m_acc_reply_frame_hdl,
8105 &irPhysDisk->Slot);
8106 state = ddi_get32(mpt->m_acc_reply_frame_hdl,
8107 &irPhysDisk->NewValue);
8108 reason = ddi_get8(mpt->m_acc_reply_frame_hdl,
8109 &irPhysDisk->ReasonCode);
8110
8111 NDBG20(("EVENT_IR_PHYSICAL_DISK event is received"));
8112
8113 switch (reason) {
8114 case MPI2_EVENT_IR_PHYSDISK_RC_SETTINGS_CHANGED:
8115 mptsas_log(mpt, CE_NOTE,
8116 " PhysDiskNum %d with DevHandle 0x%x in slot %d "
8117 "for enclosure with handle 0x%x is now in hot "
8118 "spare pool %d",
8119 physdisknum, devhandle, slot, enchandle,
8120 (state >> 16) & 0xff);
8121 break;
8122
8123 case MPI2_EVENT_IR_PHYSDISK_RC_STATUS_FLAGS_CHANGED:
8124 status = state;
8125 mptsas_log(mpt, CE_NOTE,
8126 " PhysDiskNum %d with DevHandle 0x%x in slot %d "
8127 "for enclosure with handle 0x%x is now "
8128 "%s%s%s%s%s\n", physdisknum, devhandle, slot,
8129 enchandle,
8130 status & MPI2_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME
8131 ? ", inactive" : ", active",
8132 status & MPI2_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC
8133 ? ", out of sync" : "",
8134 status & MPI2_PHYSDISK0_STATUS_FLAG_QUIESCED
8135 ? ", quiesced" : "",
8136 status &
8137 MPI2_PHYSDISK0_STATUS_FLAG_WRITE_CACHE_ENABLED
8138 ? ", write cache enabled" : "",
8139 status & MPI2_PHYSDISK0_STATUS_FLAG_OCE_TARGET
8140 ? ", capacity expansion target" : "");
8141 break;
8142
8143 case MPI2_EVENT_IR_PHYSDISK_RC_STATE_CHANGED:
8144 mptsas_log(mpt, CE_NOTE,
8145 " PhysDiskNum %d with DevHandle 0x%x in slot %d "
8146 "for enclosure with handle 0x%x is now %s\n",
8147 physdisknum, devhandle, slot, enchandle,
8148 state == MPI2_RAID_PD_STATE_OPTIMAL
8149 ? "optimal" :
8150 state == MPI2_RAID_PD_STATE_REBUILDING
8151 ? "rebuilding" :
8152 state == MPI2_RAID_PD_STATE_DEGRADED
8153 ? "degraded" :
8154 state == MPI2_RAID_PD_STATE_HOT_SPARE
8155 ? "a hot spare" :
8156 state == MPI2_RAID_PD_STATE_ONLINE
8157 ? "online" :
8158 state == MPI2_RAID_PD_STATE_OFFLINE
8159 ? "offline" :
8160 state == MPI2_RAID_PD_STATE_NOT_COMPATIBLE
8161 ? "not compatible" :
8162 state == MPI2_RAID_PD_STATE_NOT_CONFIGURED
8163 ? "not configured" :
8164 "state unknown");
8165 break;
8166 }
8167 break;
8168 }
8169 default:
8170 NDBG20(("mptsas%d: unknown event %x received",
8171 mpt->m_instance, event));
8172 break;
8173 }
8174
8175 /*
8176 * Return the reply frame to the free queue.
8177 */
8178 ddi_put32(mpt->m_acc_free_queue_hdl,
8179 &((uint32_t *)(void *)mpt->m_free_queue)[mpt->m_free_index], rfm);
8180 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0,
8181 DDI_DMA_SYNC_FORDEV);
8182 if (++mpt->m_free_index == mpt->m_free_queue_depth) {
8183 mpt->m_free_index = 0;
8184 }
8185 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex,
8186 mpt->m_free_index);
8187 mutex_exit(&mpt->m_mutex);
8188 }
8189
8190 /*
8191 * invoked from timeout() to restart qfull cmds with throttle == 0
8192 */
8193 static void
8194 mptsas_restart_cmd(void *arg)
8195 {
8196 mptsas_t *mpt = arg;
8197 mptsas_target_t *ptgt = NULL;
8198
8199 mutex_enter(&mpt->m_mutex);
8200
8201 mpt->m_restart_cmd_timeid = 0;
8202
8203 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL;
8204 ptgt = refhash_next(mpt->m_targets, ptgt)) {
8205 if (ptgt->m_reset_delay == 0) {
8206 if (ptgt->m_t_throttle == QFULL_THROTTLE) {
8207 mptsas_set_throttle(mpt, ptgt,
8208 MAX_THROTTLE);
8209 }
8210 }
8211 }
8212 mptsas_restart_hba(mpt);
8213 mutex_exit(&mpt->m_mutex);
8214 }
8215
8216 void
8217 mptsas_remove_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd)
8218 {
8219 int slot;
8220 mptsas_slots_t *slots = mpt->m_active;
8221 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
8222
8223 ASSERT(cmd != NULL);
8224 ASSERT(cmd->cmd_queued == FALSE);
8225
8226 /*
8227 * Task Management cmds are removed in their own routines. Also,
8228 * we don't want to modify timeout based on TM cmds.
8229 */
8230 if (cmd->cmd_flags & CFLAG_TM_CMD) {
8231 return;
8232 }
8233
8234 slot = cmd->cmd_slot;
8235
8236 /*
8237 * remove the cmd.
8238 */
8239 if (cmd == slots->m_slot[slot]) {
8240 NDBG31(("mptsas_remove_cmd: removing cmd=0x%p, flags "
8241 "0x%x", (void *)cmd, cmd->cmd_flags));
8242 slots->m_slot[slot] = NULL;
8243 mpt->m_ncmds--;
8244
8245 /*
8246 * only decrement per target ncmds if command
8247 * has a target associated with it.
8248 */
8249 if ((cmd->cmd_flags & CFLAG_CMDIOC) == 0) {
8250 ptgt->m_t_ncmds--;
8251 /*
8252 * reset throttle if we just ran an untagged command
8253 * to a tagged target
8254 */
8255 if ((ptgt->m_t_ncmds == 0) &&
8256 ((cmd->cmd_pkt_flags & FLAG_TAGMASK) == 0)) {
8257 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE);
8258 }
8259
8260 /*
8261 * Remove this command from the active queue.
8262 */
8263 if (cmd->cmd_active_expiration != 0) {
8264 TAILQ_REMOVE(&ptgt->m_active_cmdq, cmd,
8265 cmd_active_link);
8266 cmd->cmd_active_expiration = 0;
8267 }
8268 }
8269 }
8270
8271 /*
8272 * This is all we need to do for ioc commands.
8273 */
8274 if (cmd->cmd_flags & CFLAG_CMDIOC) {
8275 mptsas_return_to_pool(mpt, cmd);
8276 return;
8277 }
8278
8279 ASSERT(cmd != slots->m_slot[cmd->cmd_slot]);
8280 }
8281
8282 /*
8283 * accept all cmds on the tx_waitq if any and then
8284 * start a fresh request from the top of the device queue.
8285 *
8286 * since there are always cmds queued on the tx_waitq, and rare cmds on
8287 * the instance waitq, so this function should not be invoked in the ISR,
8288 * the mptsas_restart_waitq() is invoked in the ISR instead. otherwise, the
8289 * burden belongs to the IO dispatch CPUs is moved the interrupt CPU.
8290 */
8291 static void
8292 mptsas_restart_hba(mptsas_t *mpt)
8293 {
8294 ASSERT(mutex_owned(&mpt->m_mutex));
8295
8296 mutex_enter(&mpt->m_tx_waitq_mutex);
8297 if (mpt->m_tx_waitq) {
8298 mptsas_accept_tx_waitq(mpt);
8299 }
8300 mutex_exit(&mpt->m_tx_waitq_mutex);
8301 mptsas_restart_waitq(mpt);
8302 }
8303
8304 /*
8305 * start a fresh request from the top of the device queue
8306 */
8307 static void
8308 mptsas_restart_waitq(mptsas_t *mpt)
8309 {
8310 mptsas_cmd_t *cmd, *next_cmd;
8311 mptsas_target_t *ptgt = NULL;
8312
8313 NDBG1(("mptsas_restart_waitq: mpt=0x%p", (void *)mpt));
8314
8315 ASSERT(mutex_owned(&mpt->m_mutex));
8316
8317 /*
8318 * If there is a reset delay, don't start any cmds. Otherwise, start
8319 * as many cmds as possible.
8320 * Since SMID 0 is reserved and the TM slot is reserved, the actual max
8321 * commands is m_max_requests - 2.
8322 */
8323 cmd = mpt->m_waitq;
8324
8325 while (cmd != NULL) {
8326 next_cmd = cmd->cmd_linkp;
8327 if (cmd->cmd_flags & CFLAG_PASSTHRU) {
8328 if (mptsas_save_cmd(mpt, cmd) == TRUE) {
8329 /*
8330 * passthru command get slot need
8331 * set CFLAG_PREPARED.
8332 */
8333 cmd->cmd_flags |= CFLAG_PREPARED;
8334 mptsas_waitq_delete(mpt, cmd);
8335 mptsas_start_passthru(mpt, cmd);
8336 }
8337 cmd = next_cmd;
8338 continue;
8339 }
8340 if (cmd->cmd_flags & CFLAG_CONFIG) {
8341 if (mptsas_save_cmd(mpt, cmd) == TRUE) {
8342 /*
8343 * Send the config page request and delete it
8344 * from the waitq.
8345 */
8346 cmd->cmd_flags |= CFLAG_PREPARED;
8347 mptsas_waitq_delete(mpt, cmd);
8348 mptsas_start_config_page_access(mpt, cmd);
8349 }
8350 cmd = next_cmd;
8351 continue;
8352 }
8353 if (cmd->cmd_flags & CFLAG_FW_DIAG) {
8354 if (mptsas_save_cmd(mpt, cmd) == TRUE) {
8355 /*
8356 * Send the FW Diag request and delete if from
8357 * the waitq.
8358 */
8359 cmd->cmd_flags |= CFLAG_PREPARED;
8360 mptsas_waitq_delete(mpt, cmd);
8361 mptsas_start_diag(mpt, cmd);
8362 }
8363 cmd = next_cmd;
8364 continue;
8365 }
8366
8367 ptgt = cmd->cmd_tgt_addr;
8368 if (ptgt && (ptgt->m_t_throttle == DRAIN_THROTTLE) &&
8369 (ptgt->m_t_ncmds == 0)) {
8370 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE);
8371 }
8372 if ((mpt->m_ncmds <= (mpt->m_max_requests - 2)) &&
8373 (ptgt && (ptgt->m_reset_delay == 0)) &&
8374 (ptgt && (ptgt->m_t_ncmds <
8375 ptgt->m_t_throttle))) {
8376 if (mptsas_save_cmd(mpt, cmd) == TRUE) {
8377 mptsas_waitq_delete(mpt, cmd);
8378 (void) mptsas_start_cmd(mpt, cmd);
8379 }
8380 }
8381 cmd = next_cmd;
8382 }
8383 }
8384 /*
8385 * Cmds are queued if tran_start() doesn't get the m_mutexlock(no wait).
8386 * Accept all those queued cmds before new cmd is accept so that the
8387 * cmds are sent in order.
8388 */
8389 static void
8390 mptsas_accept_tx_waitq(mptsas_t *mpt)
8391 {
8392 mptsas_cmd_t *cmd;
8393
8394 ASSERT(mutex_owned(&mpt->m_mutex));
8395 ASSERT(mutex_owned(&mpt->m_tx_waitq_mutex));
8396
8397 /*
8398 * A Bus Reset could occur at any time and flush the tx_waitq,
8399 * so we cannot count on the tx_waitq to contain even one cmd.
8400 * And when the m_tx_waitq_mutex is released and run
8401 * mptsas_accept_pkt(), the tx_waitq may be flushed.
8402 */
8403 cmd = mpt->m_tx_waitq;
8404 for (;;) {
8405 if ((cmd = mpt->m_tx_waitq) == NULL) {
8406 mpt->m_tx_draining = 0;
8407 break;
8408 }
8409 if ((mpt->m_tx_waitq = cmd->cmd_linkp) == NULL) {
8410 mpt->m_tx_waitqtail = &mpt->m_tx_waitq;
8411 }
8412 cmd->cmd_linkp = NULL;
8413 mutex_exit(&mpt->m_tx_waitq_mutex);
8414 if (mptsas_accept_pkt(mpt, cmd) != TRAN_ACCEPT)
8415 cmn_err(CE_WARN, "mpt: mptsas_accept_tx_waitq: failed "
8416 "to accept cmd on queue\n");
8417 mutex_enter(&mpt->m_tx_waitq_mutex);
8418 }
8419 }
8420
8421
8422 /*
8423 * mpt tag type lookup
8424 */
8425 static char mptsas_tag_lookup[] =
8426 {0, MSG_HEAD_QTAG, MSG_ORDERED_QTAG, 0, MSG_SIMPLE_QTAG};
8427
8428 static int
8429 mptsas_start_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd)
8430 {
8431 struct scsi_pkt *pkt = CMD2PKT(cmd);
8432 uint32_t control = 0;
8433 caddr_t mem, arsbuf;
8434 pMpi2SCSIIORequest_t io_request;
8435 ddi_dma_handle_t dma_hdl = mpt->m_dma_req_frame_hdl;
8436 ddi_acc_handle_t acc_hdl = mpt->m_acc_req_frame_hdl;
8437 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
8438 uint16_t SMID, io_flags = 0;
8439 uint8_t ars_size;
8440 uint64_t request_desc;
8441 uint32_t ars_dmaaddrlow;
8442 mptsas_cmd_t *c;
8443
8444 NDBG1(("mptsas_start_cmd: cmd=0x%p, flags 0x%x", (void *)cmd,
8445 cmd->cmd_flags));
8446
8447 /*
8448 * Set SMID and increment index. Rollover to 1 instead of 0 if index
8449 * is at the max. 0 is an invalid SMID, so we call the first index 1.
8450 */
8451 SMID = cmd->cmd_slot;
8452
8453 /*
8454 * It is possible for back to back device reset to
8455 * happen before the reset delay has expired. That's
8456 * ok, just let the device reset go out on the bus.
8457 */
8458 if ((cmd->cmd_pkt_flags & FLAG_NOINTR) == 0) {
8459 ASSERT(ptgt->m_reset_delay == 0);
8460 }
8461
8462 /*
8463 * if a non-tagged cmd is submitted to an active tagged target
8464 * then drain before submitting this cmd; SCSI-2 allows RQSENSE
8465 * to be untagged
8466 */
8467 if (((cmd->cmd_pkt_flags & FLAG_TAGMASK) == 0) &&
8468 (ptgt->m_t_ncmds > 1) &&
8469 ((cmd->cmd_flags & CFLAG_TM_CMD) == 0) &&
8470 (*(cmd->cmd_pkt->pkt_cdbp) != SCMD_REQUEST_SENSE)) {
8471 if ((cmd->cmd_pkt_flags & FLAG_NOINTR) == 0) {
8472 NDBG23(("target=%d, untagged cmd, start draining\n",
8473 ptgt->m_devhdl));
8474
8475 if (ptgt->m_reset_delay == 0) {
8476 mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE);
8477 }
8478
8479 mptsas_remove_cmd(mpt, cmd);
8480 cmd->cmd_pkt_flags |= FLAG_HEAD;
8481 mptsas_waitq_add(mpt, cmd);
8482 }
8483 return (DDI_FAILURE);
8484 }
8485
8486 /*
8487 * Set correct tag bits.
8488 */
8489 if (cmd->cmd_pkt_flags & FLAG_TAGMASK) {
8490 switch (mptsas_tag_lookup[((cmd->cmd_pkt_flags &
8491 FLAG_TAGMASK) >> 12)]) {
8492 case MSG_SIMPLE_QTAG:
8493 control |= MPI2_SCSIIO_CONTROL_SIMPLEQ;
8494 break;
8495 case MSG_HEAD_QTAG:
8496 control |= MPI2_SCSIIO_CONTROL_HEADOFQ;
8497 break;
8498 case MSG_ORDERED_QTAG:
8499 control |= MPI2_SCSIIO_CONTROL_ORDEREDQ;
8500 break;
8501 default:
8502 mptsas_log(mpt, CE_WARN, "mpt: Invalid tag type\n");
8503 break;
8504 }
8505 } else {
8506 if (*(cmd->cmd_pkt->pkt_cdbp) != SCMD_REQUEST_SENSE) {
8507 ptgt->m_t_throttle = 1;
8508 }
8509 control |= MPI2_SCSIIO_CONTROL_SIMPLEQ;
8510 }
8511
8512 if (cmd->cmd_pkt_flags & FLAG_TLR) {
8513 control |= MPI2_SCSIIO_CONTROL_TLR_ON;
8514 }
8515
8516 mem = mpt->m_req_frame + (mpt->m_req_frame_size * SMID);
8517 io_request = (pMpi2SCSIIORequest_t)mem;
8518 if (cmd->cmd_extrqslen != 0) {
8519 /*
8520 * Mapping of the buffer was done in mptsas_pkt_alloc_extern().
8521 * Calculate the DMA address with the same offset.
8522 */
8523 arsbuf = cmd->cmd_arq_buf;
8524 ars_size = cmd->cmd_extrqslen;
8525 ars_dmaaddrlow = (mpt->m_req_sense_dma_addr +
8526 ((uintptr_t)arsbuf - (uintptr_t)mpt->m_req_sense)) &
8527 0xffffffffu;
8528 } else {
8529 arsbuf = mpt->m_req_sense + (mpt->m_req_sense_size * (SMID-1));
8530 cmd->cmd_arq_buf = arsbuf;
8531 ars_size = mpt->m_req_sense_size;
8532 ars_dmaaddrlow = (mpt->m_req_sense_dma_addr +
8533 (mpt->m_req_sense_size * (SMID-1))) &
8534 0xffffffffu;
8535 }
8536 bzero(io_request, sizeof (Mpi2SCSIIORequest_t));
8537 bzero(arsbuf, ars_size);
8538
8539 ddi_put8(acc_hdl, &io_request->SGLOffset0, offsetof
8540 (MPI2_SCSI_IO_REQUEST, SGL) / 4);
8541 mptsas_init_std_hdr(acc_hdl, io_request, ptgt->m_devhdl, Lun(cmd), 0,
8542 MPI2_FUNCTION_SCSI_IO_REQUEST);
8543
8544 (void) ddi_rep_put8(acc_hdl, (uint8_t *)pkt->pkt_cdbp,
8545 io_request->CDB.CDB32, cmd->cmd_cdblen, DDI_DEV_AUTOINCR);
8546
8547 io_flags = cmd->cmd_cdblen;
8548 if (mptsas_use_fastpath &&
8549 ptgt->m_io_flags & MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH) {
8550 io_flags |= MPI25_SCSIIO_IOFLAGS_FAST_PATH;
8551 request_desc = MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO;
8552 } else {
8553 request_desc = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO;
8554 }
8555 ddi_put16(acc_hdl, &io_request->IoFlags, io_flags);
8556 /*
8557 * setup the Scatter/Gather DMA list for this request
8558 */
8559 if (cmd->cmd_cookiec > 0) {
8560 mptsas_sge_setup(mpt, cmd, &control, io_request, acc_hdl);
8561 } else {
8562 ddi_put32(acc_hdl, &io_request->SGL.MpiSimple.FlagsLength,
8563 ((uint32_t)MPI2_SGE_FLAGS_LAST_ELEMENT |
8564 MPI2_SGE_FLAGS_END_OF_BUFFER |
8565 MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
8566 MPI2_SGE_FLAGS_END_OF_LIST) << MPI2_SGE_FLAGS_SHIFT);
8567 }
8568
8569 /*
8570 * save ARQ information
8571 */
8572 ddi_put8(acc_hdl, &io_request->SenseBufferLength, ars_size);
8573 ddi_put32(acc_hdl, &io_request->SenseBufferLowAddress, ars_dmaaddrlow);
8574
8575 ddi_put32(acc_hdl, &io_request->Control, control);
8576
8577 NDBG31(("starting message=%d(0x%p), with cmd=0x%p",
8578 SMID, (void *)io_request, (void *)cmd));
8579
8580 (void) ddi_dma_sync(dma_hdl, 0, 0, DDI_DMA_SYNC_FORDEV);
8581 (void) ddi_dma_sync(mpt->m_dma_req_sense_hdl, 0, 0,
8582 DDI_DMA_SYNC_FORDEV);
8583
8584 /*
8585 * Build request descriptor and write it to the request desc post reg.
8586 */
8587 request_desc |= (SMID << 16);
8588 request_desc |= (uint64_t)ptgt->m_devhdl << 48;
8589 MPTSAS_START_CMD(mpt, request_desc);
8590
8591 /*
8592 * Start timeout.
8593 */
8594 cmd->cmd_active_expiration =
8595 gethrtime() + (hrtime_t)pkt->pkt_time * NANOSEC;
8596 #ifdef MPTSAS_TEST
8597 /*
8598 * Force timeouts to happen immediately.
8599 */
8600 if (mptsas_test_timeouts)
8601 cmd->cmd_active_expiration = gethrtime();
8602 #endif
8603 c = TAILQ_FIRST(&ptgt->m_active_cmdq);
8604 if (c == NULL ||
8605 c->cmd_active_expiration < cmd->cmd_active_expiration) {
8606 /*
8607 * Common case is that this is the last pending expiration
8608 * (or queue is empty). Insert at head of the queue.
8609 */
8610 TAILQ_INSERT_HEAD(&ptgt->m_active_cmdq, cmd, cmd_active_link);
8611 } else {
8612 /*
8613 * Queue is not empty and first element expires later than
8614 * this command. Search for element expiring sooner.
8615 */
8616 while ((c = TAILQ_NEXT(c, cmd_active_link)) != NULL) {
8617 if (c->cmd_active_expiration <
8618 cmd->cmd_active_expiration) {
8619 TAILQ_INSERT_BEFORE(c, cmd, cmd_active_link);
8620 break;
8621 }
8622 }
8623 if (c == NULL) {
8624 /*
8625 * No element found expiring sooner, append to
8626 * non-empty queue.
8627 */
8628 TAILQ_INSERT_TAIL(&ptgt->m_active_cmdq, cmd,
8629 cmd_active_link);
8630 }
8631 }
8632
8633 if ((mptsas_check_dma_handle(dma_hdl) != DDI_SUCCESS) ||
8634 (mptsas_check_acc_handle(acc_hdl) != DDI_SUCCESS)) {
8635 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
8636 return (DDI_FAILURE);
8637 }
8638 return (DDI_SUCCESS);
8639 }
8640
8641 /*
8642 * Select a helper thread to handle current doneq
8643 */
8644 static void
8645 mptsas_deliver_doneq_thread(mptsas_t *mpt)
8646 {
8647 uint64_t t, i;
8648 uint32_t min = 0xffffffff;
8649 mptsas_doneq_thread_list_t *item;
8650
8651 for (i = 0; i < mpt->m_doneq_thread_n; i++) {
8652 item = &mpt->m_doneq_thread_id[i];
8653 /*
8654 * If the completed command on help thread[i] less than
8655 * doneq_thread_threshold, then pick the thread[i]. Otherwise
8656 * pick a thread which has least completed command.
8657 */
8658
8659 mutex_enter(&item->mutex);
8660 if (item->len < mpt->m_doneq_thread_threshold) {
8661 t = i;
8662 mutex_exit(&item->mutex);
8663 break;
8664 }
8665 if (item->len < min) {
8666 min = item->len;
8667 t = i;
8668 }
8669 mutex_exit(&item->mutex);
8670 }
8671 mutex_enter(&mpt->m_doneq_thread_id[t].mutex);
8672 mptsas_doneq_mv(mpt, t);
8673 cv_signal(&mpt->m_doneq_thread_id[t].cv);
8674 mutex_exit(&mpt->m_doneq_thread_id[t].mutex);
8675 }
8676
8677 /*
8678 * move the current global doneq to the doneq of thead[t]
8679 */
8680 static void
8681 mptsas_doneq_mv(mptsas_t *mpt, uint64_t t)
8682 {
8683 mptsas_cmd_t *cmd;
8684 mptsas_doneq_thread_list_t *item = &mpt->m_doneq_thread_id[t];
8685
8686 ASSERT(mutex_owned(&item->mutex));
8687 while ((cmd = mpt->m_doneq) != NULL) {
8688 if ((mpt->m_doneq = cmd->cmd_linkp) == NULL) {
8689 mpt->m_donetail = &mpt->m_doneq;
8690 }
8691 cmd->cmd_linkp = NULL;
8692 *item->donetail = cmd;
8693 item->donetail = &cmd->cmd_linkp;
8694 mpt->m_doneq_len--;
8695 item->len++;
8696 }
8697 }
8698
8699 void
8700 mptsas_fma_check(mptsas_t *mpt, mptsas_cmd_t *cmd)
8701 {
8702 struct scsi_pkt *pkt = CMD2PKT(cmd);
8703
8704 /* Check all acc and dma handles */
8705 if ((mptsas_check_acc_handle(mpt->m_datap) !=
8706 DDI_SUCCESS) ||
8707 (mptsas_check_acc_handle(mpt->m_acc_req_frame_hdl) !=
8708 DDI_SUCCESS) ||
8709 (mptsas_check_acc_handle(mpt->m_acc_req_sense_hdl) !=
8710 DDI_SUCCESS) ||
8711 (mptsas_check_acc_handle(mpt->m_acc_reply_frame_hdl) !=
8712 DDI_SUCCESS) ||
8713 (mptsas_check_acc_handle(mpt->m_acc_free_queue_hdl) !=
8714 DDI_SUCCESS) ||
8715 (mptsas_check_acc_handle(mpt->m_acc_post_queue_hdl) !=
8716 DDI_SUCCESS) ||
8717 (mptsas_check_acc_handle(mpt->m_hshk_acc_hdl) !=
8718 DDI_SUCCESS) ||
8719 (mptsas_check_acc_handle(mpt->m_config_handle) !=
8720 DDI_SUCCESS)) {
8721 ddi_fm_service_impact(mpt->m_dip,
8722 DDI_SERVICE_UNAFFECTED);
8723 ddi_fm_acc_err_clear(mpt->m_config_handle,
8724 DDI_FME_VER0);
8725 pkt->pkt_reason = CMD_TRAN_ERR;
8726 pkt->pkt_statistics = 0;
8727 }
8728 if ((mptsas_check_dma_handle(mpt->m_dma_req_frame_hdl) !=
8729 DDI_SUCCESS) ||
8730 (mptsas_check_dma_handle(mpt->m_dma_req_sense_hdl) !=
8731 DDI_SUCCESS) ||
8732 (mptsas_check_dma_handle(mpt->m_dma_reply_frame_hdl) !=
8733 DDI_SUCCESS) ||
8734 (mptsas_check_dma_handle(mpt->m_dma_free_queue_hdl) !=
8735 DDI_SUCCESS) ||
8736 (mptsas_check_dma_handle(mpt->m_dma_post_queue_hdl) !=
8737 DDI_SUCCESS) ||
8738 (mptsas_check_dma_handle(mpt->m_hshk_dma_hdl) !=
8739 DDI_SUCCESS)) {
8740 ddi_fm_service_impact(mpt->m_dip,
8741 DDI_SERVICE_UNAFFECTED);
8742 pkt->pkt_reason = CMD_TRAN_ERR;
8743 pkt->pkt_statistics = 0;
8744 }
8745 if (cmd->cmd_dmahandle &&
8746 (mptsas_check_dma_handle(cmd->cmd_dmahandle) != DDI_SUCCESS)) {
8747 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
8748 pkt->pkt_reason = CMD_TRAN_ERR;
8749 pkt->pkt_statistics = 0;
8750 }
8751 if ((cmd->cmd_extra_frames &&
8752 ((mptsas_check_dma_handle(cmd->cmd_extra_frames->m_dma_hdl) !=
8753 DDI_SUCCESS) ||
8754 (mptsas_check_acc_handle(cmd->cmd_extra_frames->m_acc_hdl) !=
8755 DDI_SUCCESS)))) {
8756 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
8757 pkt->pkt_reason = CMD_TRAN_ERR;
8758 pkt->pkt_statistics = 0;
8759 }
8760 }
8761
8762 /*
8763 * These routines manipulate the queue of commands that
8764 * are waiting for their completion routines to be called.
8765 * The queue is usually in FIFO order but on an MP system
8766 * it's possible for the completion routines to get out
8767 * of order. If that's a problem you need to add a global
8768 * mutex around the code that calls the completion routine
8769 * in the interrupt handler.
8770 */
8771 static void
8772 mptsas_doneq_add(mptsas_t *mpt, mptsas_cmd_t *cmd)
8773 {
8774 struct scsi_pkt *pkt = CMD2PKT(cmd);
8775
8776 NDBG31(("mptsas_doneq_add: cmd=0x%p", (void *)cmd));
8777
8778 ASSERT((cmd->cmd_flags & CFLAG_COMPLETED) == 0);
8779 cmd->cmd_linkp = NULL;
8780 cmd->cmd_flags |= CFLAG_FINISHED;
8781 cmd->cmd_flags &= ~CFLAG_IN_TRANSPORT;
8782
8783 mptsas_fma_check(mpt, cmd);
8784
8785 /*
8786 * only add scsi pkts that have completion routines to
8787 * the doneq. no intr cmds do not have callbacks.
8788 */
8789 if (pkt && (pkt->pkt_comp)) {
8790 *mpt->m_donetail = cmd;
8791 mpt->m_donetail = &cmd->cmd_linkp;
8792 mpt->m_doneq_len++;
8793 }
8794 }
8795
8796 static mptsas_cmd_t *
8797 mptsas_doneq_thread_rm(mptsas_t *mpt, uint64_t t)
8798 {
8799 mptsas_cmd_t *cmd;
8800 mptsas_doneq_thread_list_t *item = &mpt->m_doneq_thread_id[t];
8801
8802 /* pop one off the done queue */
8803 if ((cmd = item->doneq) != NULL) {
8804 /* if the queue is now empty fix the tail pointer */
8805 NDBG31(("mptsas_doneq_thread_rm: cmd=0x%p", (void *)cmd));
8806 if ((item->doneq = cmd->cmd_linkp) == NULL) {
8807 item->donetail = &item->doneq;
8808 }
8809 cmd->cmd_linkp = NULL;
8810 item->len--;
8811 }
8812 return (cmd);
8813 }
8814
8815 static void
8816 mptsas_doneq_empty(mptsas_t *mpt)
8817 {
8818 if (mpt->m_doneq && !mpt->m_in_callback) {
8819 mptsas_cmd_t *cmd, *next;
8820 struct scsi_pkt *pkt;
8821
8822 mpt->m_in_callback = 1;
8823 cmd = mpt->m_doneq;
8824 mpt->m_doneq = NULL;
8825 mpt->m_donetail = &mpt->m_doneq;
8826 mpt->m_doneq_len = 0;
8827
8828 mutex_exit(&mpt->m_mutex);
8829 /*
8830 * run the completion routines of all the
8831 * completed commands
8832 */
8833 while (cmd != NULL) {
8834 next = cmd->cmd_linkp;
8835 cmd->cmd_linkp = NULL;
8836 /* run this command's completion routine */
8837 cmd->cmd_flags |= CFLAG_COMPLETED;
8838 pkt = CMD2PKT(cmd);
8839 mptsas_pkt_comp(pkt, cmd);
8840 cmd = next;
8841 }
8842 mutex_enter(&mpt->m_mutex);
8843 mpt->m_in_callback = 0;
8844 }
8845 }
8846
8847 /*
8848 * These routines manipulate the target's queue of pending requests
8849 */
8850 void
8851 mptsas_waitq_add(mptsas_t *mpt, mptsas_cmd_t *cmd)
8852 {
8853 NDBG7(("mptsas_waitq_add: cmd=0x%p", (void *)cmd));
8854 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
8855 cmd->cmd_queued = TRUE;
8856 if (ptgt)
8857 ptgt->m_t_nwait++;
8858 if (cmd->cmd_pkt_flags & FLAG_HEAD) {
8859 if ((cmd->cmd_linkp = mpt->m_waitq) == NULL) {
8860 mpt->m_waitqtail = &cmd->cmd_linkp;
8861 }
8862 mpt->m_waitq = cmd;
8863 } else {
8864 cmd->cmd_linkp = NULL;
8865 *(mpt->m_waitqtail) = cmd;
8866 mpt->m_waitqtail = &cmd->cmd_linkp;
8867 }
8868 }
8869
8870 static mptsas_cmd_t *
8871 mptsas_waitq_rm(mptsas_t *mpt)
8872 {
8873 mptsas_cmd_t *cmd;
8874 mptsas_target_t *ptgt;
8875 NDBG7(("mptsas_waitq_rm"));
8876
8877 MPTSAS_WAITQ_RM(mpt, cmd);
8878
8879 NDBG7(("mptsas_waitq_rm: cmd=0x%p", (void *)cmd));
8880 if (cmd) {
8881 ptgt = cmd->cmd_tgt_addr;
8882 if (ptgt) {
8883 ptgt->m_t_nwait--;
8884 ASSERT(ptgt->m_t_nwait >= 0);
8885 }
8886 }
8887 return (cmd);
8888 }
8889
8890 /*
8891 * remove specified cmd from the middle of the wait queue.
8892 */
8893 static void
8894 mptsas_waitq_delete(mptsas_t *mpt, mptsas_cmd_t *cmd)
8895 {
8896 mptsas_cmd_t *prevp = mpt->m_waitq;
8897 mptsas_target_t *ptgt = cmd->cmd_tgt_addr;
8898
8899 NDBG7(("mptsas_waitq_delete: mpt=0x%p cmd=0x%p",
8900 (void *)mpt, (void *)cmd));
8901 if (ptgt) {
8902 ptgt->m_t_nwait--;
8903 ASSERT(ptgt->m_t_nwait >= 0);
8904 }
8905
8906 if (prevp == cmd) {
8907 if ((mpt->m_waitq = cmd->cmd_linkp) == NULL)
8908 mpt->m_waitqtail = &mpt->m_waitq;
8909
8910 cmd->cmd_linkp = NULL;
8911 cmd->cmd_queued = FALSE;
8912 NDBG7(("mptsas_waitq_delete: mpt=0x%p cmd=0x%p",
8913 (void *)mpt, (void *)cmd));
8914 return;
8915 }
8916
8917 while (prevp != NULL) {
8918 if (prevp->cmd_linkp == cmd) {
8919 if ((prevp->cmd_linkp = cmd->cmd_linkp) == NULL)
8920 mpt->m_waitqtail = &prevp->cmd_linkp;
8921
8922 cmd->cmd_linkp = NULL;
8923 cmd->cmd_queued = FALSE;
8924 NDBG7(("mptsas_waitq_delete: mpt=0x%p cmd=0x%p",
8925 (void *)mpt, (void *)cmd));
8926 return;
8927 }
8928 prevp = prevp->cmd_linkp;
8929 }
8930 cmn_err(CE_PANIC, "mpt: mptsas_waitq_delete: queue botch");
8931 }
8932
8933 static mptsas_cmd_t *
8934 mptsas_tx_waitq_rm(mptsas_t *mpt)
8935 {
8936 mptsas_cmd_t *cmd;
8937 NDBG7(("mptsas_tx_waitq_rm"));
8938
8939 MPTSAS_TX_WAITQ_RM(mpt, cmd);
8940
8941 NDBG7(("mptsas_tx_waitq_rm: cmd=0x%p", (void *)cmd));
8942
8943 return (cmd);
8944 }
8945
8946 /*
8947 * remove specified cmd from the middle of the tx_waitq.
8948 */
8949 static void
8950 mptsas_tx_waitq_delete(mptsas_t *mpt, mptsas_cmd_t *cmd)
8951 {
8952 mptsas_cmd_t *prevp = mpt->m_tx_waitq;
8953
8954 NDBG7(("mptsas_tx_waitq_delete: mpt=0x%p cmd=0x%p",
8955 (void *)mpt, (void *)cmd));
8956
8957 if (prevp == cmd) {
8958 if ((mpt->m_tx_waitq = cmd->cmd_linkp) == NULL)
8959 mpt->m_tx_waitqtail = &mpt->m_tx_waitq;
8960
8961 cmd->cmd_linkp = NULL;
8962 cmd->cmd_queued = FALSE;
8963 NDBG7(("mptsas_tx_waitq_delete: mpt=0x%p cmd=0x%p",
8964 (void *)mpt, (void *)cmd));
8965 return;
8966 }
8967
8968 while (prevp != NULL) {
8969 if (prevp->cmd_linkp == cmd) {
8970 if ((prevp->cmd_linkp = cmd->cmd_linkp) == NULL)
8971 mpt->m_tx_waitqtail = &prevp->cmd_linkp;
8972
8973 cmd->cmd_linkp = NULL;
8974 cmd->cmd_queued = FALSE;
8975 NDBG7(("mptsas_tx_waitq_delete: mpt=0x%p cmd=0x%p",
8976 (void *)mpt, (void *)cmd));
8977 return;
8978 }
8979 prevp = prevp->cmd_linkp;
8980 }
8981 cmn_err(CE_PANIC, "mpt: mptsas_tx_waitq_delete: queue botch");
8982 }
8983
8984 /*
8985 * device and bus reset handling
8986 *
8987 * Notes:
8988 * - RESET_ALL: reset the controller
8989 * - RESET_TARGET: reset the target specified in scsi_address
8990 */
8991 static int
8992 mptsas_scsi_reset(struct scsi_address *ap, int level)
8993 {
8994 mptsas_t *mpt = ADDR2MPT(ap);
8995 int rval;
8996 mptsas_tgt_private_t *tgt_private;
8997 mptsas_target_t *ptgt = NULL;
8998
8999 tgt_private = (mptsas_tgt_private_t *)ap->a_hba_tran->tran_tgt_private;
9000 ptgt = tgt_private->t_private;
9001 if (ptgt == NULL) {
9002 return (FALSE);
9003 }
9004 NDBG22(("mptsas_scsi_reset: target=%d level=%d", ptgt->m_devhdl,
9005 level));
9006
9007 mutex_enter(&mpt->m_mutex);
9008 /*
9009 * if we are not in panic set up a reset delay for this target
9010 */
9011 if (!ddi_in_panic()) {
9012 mptsas_setup_bus_reset_delay(mpt);
9013 } else {
9014 drv_usecwait(mpt->m_scsi_reset_delay * 1000);
9015 }
9016 rval = mptsas_do_scsi_reset(mpt, ptgt->m_devhdl);
9017 mutex_exit(&mpt->m_mutex);
9018
9019 /*
9020 * The transport layer expect to only see TRUE and
9021 * FALSE. Therefore, we will adjust the return value
9022 * if mptsas_do_scsi_reset returns FAILED.
9023 */
9024 if (rval == FAILED)
9025 rval = FALSE;
9026 return (rval);
9027 }
9028
9029 static int
9030 mptsas_do_scsi_reset(mptsas_t *mpt, uint16_t devhdl)
9031 {
9032 int rval = FALSE;
9033 uint8_t config, disk;
9034
9035 ASSERT(mutex_owned(&mpt->m_mutex));
9036
9037 if (mptsas_debug_resets) {
9038 mptsas_log(mpt, CE_WARN, "mptsas_do_scsi_reset: target=%d",
9039 devhdl);
9040 }
9041
9042 /*
9043 * Issue a Target Reset message to the target specified but not to a
9044 * disk making up a raid volume. Just look through the RAID config
9045 * Phys Disk list of DevHandles. If the target's DevHandle is in this
9046 * list, then don't reset this target.
9047 */
9048 for (config = 0; config < mpt->m_num_raid_configs; config++) {
9049 for (disk = 0; disk < MPTSAS_MAX_DISKS_IN_CONFIG; disk++) {
9050 if (devhdl == mpt->m_raidconfig[config].
9051 m_physdisk_devhdl[disk]) {
9052 return (TRUE);
9053 }
9054 }
9055 }
9056
9057 rval = mptsas_ioc_task_management(mpt,
9058 MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET, devhdl, 0, NULL, 0, 0);
9059
9060 mptsas_doneq_empty(mpt);
9061 return (rval);
9062 }
9063
9064 static int
9065 mptsas_scsi_reset_notify(struct scsi_address *ap, int flag,
9066 void (*callback)(caddr_t), caddr_t arg)
9067 {
9068 mptsas_t *mpt = ADDR2MPT(ap);
9069
9070 NDBG22(("mptsas_scsi_reset_notify: tgt=%d", ap->a_target));
9071
9072 return (scsi_hba_reset_notify_setup(ap, flag, callback, arg,
9073 &mpt->m_mutex, &mpt->m_reset_notify_listf));
9074 }
9075
9076 static int
9077 mptsas_get_name(struct scsi_device *sd, char *name, int len)
9078 {
9079 dev_info_t *lun_dip = NULL;
9080
9081 ASSERT(sd != NULL);
9082 ASSERT(name != NULL);
9083 lun_dip = sd->sd_dev;
9084 ASSERT(lun_dip != NULL);
9085
9086 if (mptsas_name_child(lun_dip, name, len) == DDI_SUCCESS) {
9087 return (1);
9088 } else {
9089 return (0);
9090 }
9091 }
9092
9093 static int
9094 mptsas_get_bus_addr(struct scsi_device *sd, char *name, int len)
9095 {
9096 return (mptsas_get_name(sd, name, len));
9097 }
9098
9099 void
9100 mptsas_set_throttle(mptsas_t *mpt, mptsas_target_t *ptgt, int what)
9101 {
9102
9103 NDBG25(("mptsas_set_throttle: throttle=%x", what));
9104
9105 /*
9106 * if the bus is draining/quiesced, no changes to the throttles
9107 * are allowed. Not allowing change of throttles during draining
9108 * limits error recovery but will reduce draining time
9109 *
9110 * all throttles should have been set to HOLD_THROTTLE
9111 */
9112 if (mpt->m_softstate & (MPTSAS_SS_QUIESCED | MPTSAS_SS_DRAINING)) {
9113 return;
9114 }
9115
9116 if (what == HOLD_THROTTLE) {
9117 ptgt->m_t_throttle = HOLD_THROTTLE;
9118 } else if (ptgt->m_reset_delay == 0) {
9119 ptgt->m_t_throttle = what;
9120 }
9121 }
9122
9123 /*
9124 * Clean up from a device reset.
9125 * For the case of target reset, this function clears the waitq of all
9126 * commands for a particular target. For the case of abort task set, this
9127 * function clears the waitq of all commonds for a particular target/lun.
9128 */
9129 static void
9130 mptsas_flush_target(mptsas_t *mpt, ushort_t target, int lun, uint8_t tasktype)
9131 {
9132 mptsas_slots_t *slots = mpt->m_active;
9133 mptsas_cmd_t *cmd, *next_cmd;
9134 int slot;
9135 uchar_t reason;
9136 uint_t stat;
9137 hrtime_t timestamp;
9138
9139 NDBG25(("mptsas_flush_target: target=%d lun=%d", target, lun));
9140
9141 timestamp = gethrtime();
9142
9143 /*
9144 * Make sure the I/O Controller has flushed all cmds
9145 * that are associated with this target for a target reset
9146 * and target/lun for abort task set.
9147 * Account for TM requests, which use the last SMID.
9148 */
9149 for (slot = 0; slot <= mpt->m_active->m_n_normal; slot++) {
9150 if ((cmd = slots->m_slot[slot]) == NULL)
9151 continue;
9152 reason = CMD_RESET;
9153 stat = STAT_DEV_RESET;
9154 switch (tasktype) {
9155 case MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET:
9156 if (Tgt(cmd) == target) {
9157 if (cmd->cmd_active_expiration <= timestamp) {
9158 /*
9159 * When timeout requested, propagate
9160 * proper reason and statistics to
9161 * target drivers.
9162 */
9163 reason = CMD_TIMEOUT;
9164 stat |= STAT_TIMEOUT;
9165 }
9166 NDBG25(("mptsas_flush_target discovered non-"
9167 "NULL cmd in slot %d, tasktype 0x%x", slot,
9168 tasktype));
9169 mptsas_dump_cmd(mpt, cmd);
9170 mptsas_remove_cmd(mpt, cmd);
9171 mptsas_set_pkt_reason(mpt, cmd, reason, stat);
9172 mptsas_doneq_add(mpt, cmd);
9173 }
9174 break;
9175 case MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET:
9176 reason = CMD_ABORTED;
9177 stat = STAT_ABORTED;
9178 /*FALLTHROUGH*/
9179 case MPI2_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET:
9180 if ((Tgt(cmd) == target) && (Lun(cmd) == lun)) {
9181
9182 NDBG25(("mptsas_flush_target discovered non-"
9183 "NULL cmd in slot %d, tasktype 0x%x", slot,
9184 tasktype));
9185 mptsas_dump_cmd(mpt, cmd);
9186 mptsas_remove_cmd(mpt, cmd);
9187 mptsas_set_pkt_reason(mpt, cmd, reason,
9188 stat);
9189 mptsas_doneq_add(mpt, cmd);
9190 }
9191 break;
9192 default:
9193 break;
9194 }
9195 }
9196
9197 /*
9198 * Flush the waitq and tx_waitq of this target's cmds
9199 */
9200 cmd = mpt->m_waitq;
9201
9202 reason = CMD_RESET;
9203 stat = STAT_DEV_RESET;
9204
9205 switch (tasktype) {
9206 case MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET:
9207 while (cmd != NULL) {
9208 next_cmd = cmd->cmd_linkp;
9209 if (Tgt(cmd) == target) {
9210 mptsas_waitq_delete(mpt, cmd);
9211 mptsas_set_pkt_reason(mpt, cmd,
9212 reason, stat);
9213 mptsas_doneq_add(mpt, cmd);
9214 }
9215 cmd = next_cmd;
9216 }
9217 mutex_enter(&mpt->m_tx_waitq_mutex);
9218 cmd = mpt->m_tx_waitq;
9219 while (cmd != NULL) {
9220 next_cmd = cmd->cmd_linkp;
9221 if (Tgt(cmd) == target) {
9222 mptsas_tx_waitq_delete(mpt, cmd);
9223 mutex_exit(&mpt->m_tx_waitq_mutex);
9224 mptsas_set_pkt_reason(mpt, cmd,
9225 reason, stat);
9226 mptsas_doneq_add(mpt, cmd);
9227 mutex_enter(&mpt->m_tx_waitq_mutex);
9228 }
9229 cmd = next_cmd;
9230 }
9231 mutex_exit(&mpt->m_tx_waitq_mutex);
9232 break;
9233 case MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET:
9234 reason = CMD_ABORTED;
9235 stat = STAT_ABORTED;
9236 /*FALLTHROUGH*/
9237 case MPI2_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET:
9238 while (cmd != NULL) {
9239 next_cmd = cmd->cmd_linkp;
9240 if ((Tgt(cmd) == target) && (Lun(cmd) == lun)) {
9241 mptsas_waitq_delete(mpt, cmd);
9242 mptsas_set_pkt_reason(mpt, cmd,
9243 reason, stat);
9244 mptsas_doneq_add(mpt, cmd);
9245 }
9246 cmd = next_cmd;
9247 }
9248 mutex_enter(&mpt->m_tx_waitq_mutex);
9249 cmd = mpt->m_tx_waitq;
9250 while (cmd != NULL) {
9251 next_cmd = cmd->cmd_linkp;
9252 if ((Tgt(cmd) == target) && (Lun(cmd) == lun)) {
9253 mptsas_tx_waitq_delete(mpt, cmd);
9254 mutex_exit(&mpt->m_tx_waitq_mutex);
9255 mptsas_set_pkt_reason(mpt, cmd,
9256 reason, stat);
9257 mptsas_doneq_add(mpt, cmd);
9258 mutex_enter(&mpt->m_tx_waitq_mutex);
9259 }
9260 cmd = next_cmd;
9261 }
9262 mutex_exit(&mpt->m_tx_waitq_mutex);
9263 break;
9264 default:
9265 mptsas_log(mpt, CE_WARN, "Unknown task management type %d.",
9266 tasktype);
9267 break;
9268 }
9269 }
9270
9271 /*
9272 * Clean up hba state, abort all outstanding command and commands in waitq
9273 * reset timeout of all targets.
9274 */
9275 static void
9276 mptsas_flush_hba(mptsas_t *mpt)
9277 {
9278 mptsas_slots_t *slots = mpt->m_active;
9279 mptsas_cmd_t *cmd;
9280 int slot;
9281
9282 NDBG25(("mptsas_flush_hba"));
9283
9284 /*
9285 * The I/O Controller should have already sent back
9286 * all commands via the scsi I/O reply frame. Make
9287 * sure all commands have been flushed.
9288 * Account for TM request, which use the last SMID.
9289 */
9290 for (slot = 0; slot <= mpt->m_active->m_n_normal; slot++) {
9291 if ((cmd = slots->m_slot[slot]) == NULL)
9292 continue;
9293
9294 if (cmd->cmd_flags & CFLAG_CMDIOC) {
9295 /*
9296 * Need to make sure to tell everyone that might be
9297 * waiting on this command that it's going to fail. If
9298 * we get here, this command will never timeout because
9299 * the active command table is going to be re-allocated,
9300 * so there will be nothing to check against a time out.
9301 * Instead, mark the command as failed due to reset.
9302 */
9303 mptsas_set_pkt_reason(mpt, cmd, CMD_RESET,
9304 STAT_BUS_RESET);
9305 if ((cmd->cmd_flags &
9306 (CFLAG_PASSTHRU | CFLAG_CONFIG | CFLAG_FW_DIAG))) {
9307 cmd->cmd_flags |= CFLAG_FINISHED;
9308 cv_broadcast(&mpt->m_passthru_cv);
9309 cv_broadcast(&mpt->m_config_cv);
9310 cv_broadcast(&mpt->m_fw_diag_cv);
9311 }
9312 continue;
9313 }
9314
9315 NDBG25(("mptsas_flush_hba discovered non-NULL cmd in slot %d",
9316 slot));
9317 mptsas_dump_cmd(mpt, cmd);
9318
9319 mptsas_remove_cmd(mpt, cmd);
9320 mptsas_set_pkt_reason(mpt, cmd, CMD_RESET, STAT_BUS_RESET);
9321 mptsas_doneq_add(mpt, cmd);
9322 }
9323
9324 /*
9325 * Flush the waitq.
9326 */
9327 while ((cmd = mptsas_waitq_rm(mpt)) != NULL) {
9328 mptsas_set_pkt_reason(mpt, cmd, CMD_RESET, STAT_BUS_RESET);
9329 if ((cmd->cmd_flags & CFLAG_PASSTHRU) ||
9330 (cmd->cmd_flags & CFLAG_CONFIG) ||
9331 (cmd->cmd_flags & CFLAG_FW_DIAG)) {
9332 cmd->cmd_flags |= CFLAG_FINISHED;
9333 cv_broadcast(&mpt->m_passthru_cv);
9334 cv_broadcast(&mpt->m_config_cv);
9335 cv_broadcast(&mpt->m_fw_diag_cv);
9336 } else {
9337 mptsas_doneq_add(mpt, cmd);
9338 }
9339 }
9340
9341 /*
9342 * Flush the tx_waitq
9343 */
9344 mutex_enter(&mpt->m_tx_waitq_mutex);
9345 while ((cmd = mptsas_tx_waitq_rm(mpt)) != NULL) {
9346 mutex_exit(&mpt->m_tx_waitq_mutex);
9347 mptsas_set_pkt_reason(mpt, cmd, CMD_RESET, STAT_BUS_RESET);
9348 mptsas_doneq_add(mpt, cmd);
9349 mutex_enter(&mpt->m_tx_waitq_mutex);
9350 }
9351 mutex_exit(&mpt->m_tx_waitq_mutex);
9352
9353 /*
9354 * Drain the taskqs prior to reallocating resources. The thread
9355 * passing through here could be launched from either (dr)
9356 * or (event) taskqs so only wait on the 'other' queue since
9357 * waiting on 'this' queue is a deadlock condition.
9358 */
9359 mutex_exit(&mpt->m_mutex);
9360 if (!taskq_member((taskq_t *)mpt->m_event_taskq, curthread))
9361 ddi_taskq_wait(mpt->m_event_taskq);
9362 if (!taskq_member((taskq_t *)mpt->m_dr_taskq, curthread))
9363 ddi_taskq_wait(mpt->m_dr_taskq);
9364
9365 mutex_enter(&mpt->m_mutex);
9366 }
9367
9368 /*
9369 * set pkt_reason and OR in pkt_statistics flag
9370 */
9371 static void
9372 mptsas_set_pkt_reason(mptsas_t *mpt, mptsas_cmd_t *cmd, uchar_t reason,
9373 uint_t stat)
9374 {
9375 #ifndef __lock_lint
9376 _NOTE(ARGUNUSED(mpt))
9377 #endif
9378
9379 NDBG25(("mptsas_set_pkt_reason: cmd=0x%p reason=%x stat=%x",
9380 (void *)cmd, reason, stat));
9381
9382 if (cmd) {
9383 if (cmd->cmd_pkt->pkt_reason == CMD_CMPLT) {
9384 cmd->cmd_pkt->pkt_reason = reason;
9385 }
9386 cmd->cmd_pkt->pkt_statistics |= stat;
9387 }
9388 }
9389
9390 static void
9391 mptsas_start_watch_reset_delay()
9392 {
9393 NDBG22(("mptsas_start_watch_reset_delay"));
9394
9395 mutex_enter(&mptsas_global_mutex);
9396 if (mptsas_reset_watch == NULL && mptsas_timeouts_enabled) {
9397 mptsas_reset_watch = timeout(mptsas_watch_reset_delay, NULL,
9398 drv_usectohz((clock_t)
9399 MPTSAS_WATCH_RESET_DELAY_TICK * 1000));
9400 ASSERT(mptsas_reset_watch != NULL);
9401 }
9402 mutex_exit(&mptsas_global_mutex);
9403 }
9404
9405 static void
9406 mptsas_setup_bus_reset_delay(mptsas_t *mpt)
9407 {
9408 mptsas_target_t *ptgt = NULL;
9409
9410 ASSERT(MUTEX_HELD(&mpt->m_mutex));
9411
9412 NDBG22(("mptsas_setup_bus_reset_delay"));
9413 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL;
9414 ptgt = refhash_next(mpt->m_targets, ptgt)) {
9415 mptsas_set_throttle(mpt, ptgt, HOLD_THROTTLE);
9416 ptgt->m_reset_delay = mpt->m_scsi_reset_delay;
9417 }
9418
9419 mptsas_start_watch_reset_delay();
9420 }
9421
9422 /*
9423 * mptsas_watch_reset_delay(_subr) is invoked by timeout() and checks every
9424 * mpt instance for active reset delays
9425 */
9426 static void
9427 mptsas_watch_reset_delay(void *arg)
9428 {
9429 #ifndef __lock_lint
9430 _NOTE(ARGUNUSED(arg))
9431 #endif
9432
9433 mptsas_t *mpt;
9434 int not_done = 0;
9435
9436 NDBG22(("mptsas_watch_reset_delay"));
9437
9438 mutex_enter(&mptsas_global_mutex);
9439 mptsas_reset_watch = 0;
9440 mutex_exit(&mptsas_global_mutex);
9441 rw_enter(&mptsas_global_rwlock, RW_READER);
9442 for (mpt = mptsas_head; mpt != NULL; mpt = mpt->m_next) {
9443 if (mpt->m_tran == 0) {
9444 continue;
9445 }
9446 mutex_enter(&mpt->m_mutex);
9447 not_done += mptsas_watch_reset_delay_subr(mpt);
9448 mutex_exit(&mpt->m_mutex);
9449 }
9450 rw_exit(&mptsas_global_rwlock);
9451
9452 if (not_done) {
9453 mptsas_start_watch_reset_delay();
9454 }
9455 }
9456
9457 static int
9458 mptsas_watch_reset_delay_subr(mptsas_t *mpt)
9459 {
9460 int done = 0;
9461 int restart = 0;
9462 mptsas_target_t *ptgt = NULL;
9463
9464 NDBG22(("mptsas_watch_reset_delay_subr: mpt=0x%p", (void *)mpt));
9465
9466 ASSERT(mutex_owned(&mpt->m_mutex));
9467
9468 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL;
9469 ptgt = refhash_next(mpt->m_targets, ptgt)) {
9470 if (ptgt->m_reset_delay != 0) {
9471 ptgt->m_reset_delay -=
9472 MPTSAS_WATCH_RESET_DELAY_TICK;
9473 if (ptgt->m_reset_delay <= 0) {
9474 ptgt->m_reset_delay = 0;
9475 mptsas_set_throttle(mpt, ptgt,
9476 MAX_THROTTLE);
9477 restart++;
9478 } else {
9479 done = -1;
9480 }
9481 }
9482 }
9483
9484 if (restart > 0) {
9485 mptsas_restart_hba(mpt);
9486 }
9487 return (done);
9488 }
9489
9490 #ifdef MPTSAS_TEST
9491 static void
9492 mptsas_test_reset(mptsas_t *mpt, int target)
9493 {
9494 mptsas_target_t *ptgt = NULL;
9495
9496 if (mptsas_rtest == target) {
9497 if (mptsas_do_scsi_reset(mpt, target) == TRUE) {
9498 mptsas_rtest = -1;
9499 }
9500 if (mptsas_rtest == -1) {
9501 NDBG22(("mptsas_test_reset success"));
9502 }
9503 }
9504 }
9505 #endif
9506
9507 /*
9508 * abort handling:
9509 *
9510 * Notes:
9511 * - if pkt is not NULL, abort just that command
9512 * - if pkt is NULL, abort all outstanding commands for target
9513 */
9514 static int
9515 mptsas_scsi_abort(struct scsi_address *ap, struct scsi_pkt *pkt)
9516 {
9517 mptsas_t *mpt = ADDR2MPT(ap);
9518 int rval;
9519 mptsas_tgt_private_t *tgt_private;
9520 int target, lun;
9521
9522 tgt_private = (mptsas_tgt_private_t *)ap->a_hba_tran->
9523 tran_tgt_private;
9524 ASSERT(tgt_private != NULL);
9525 target = tgt_private->t_private->m_devhdl;
9526 lun = tgt_private->t_lun;
9527
9528 NDBG23(("mptsas_scsi_abort: target=%d.%d", target, lun));
9529
9530 mutex_enter(&mpt->m_mutex);
9531 rval = mptsas_do_scsi_abort(mpt, target, lun, pkt);
9532 mutex_exit(&mpt->m_mutex);
9533 return (rval);
9534 }
9535
9536 static int
9537 mptsas_do_scsi_abort(mptsas_t *mpt, int target, int lun, struct scsi_pkt *pkt)
9538 {
9539 mptsas_cmd_t *sp = NULL;
9540 mptsas_slots_t *slots = mpt->m_active;
9541 int rval = FALSE;
9542
9543 ASSERT(mutex_owned(&mpt->m_mutex));
9544
9545 /*
9546 * Abort the command pkt on the target/lun in ap. If pkt is
9547 * NULL, abort all outstanding commands on that target/lun.
9548 * If you can abort them, return 1, else return 0.
9549 * Each packet that's aborted should be sent back to the target
9550 * driver through the callback routine, with pkt_reason set to
9551 * CMD_ABORTED.
9552 *
9553 * abort cmd pkt on HBA hardware; clean out of outstanding
9554 * command lists, etc.
9555 */
9556 if (pkt != NULL) {
9557 /* abort the specified packet */
9558 sp = PKT2CMD(pkt);
9559
9560 if (sp->cmd_queued) {
9561 NDBG23(("mptsas_do_scsi_abort: queued sp=0x%p aborted",
9562 (void *)sp));
9563 mptsas_waitq_delete(mpt, sp);
9564 mptsas_set_pkt_reason(mpt, sp, CMD_ABORTED,
9565 STAT_ABORTED);
9566 mptsas_doneq_add(mpt, sp);
9567 rval = TRUE;
9568 goto done;
9569 }
9570
9571 /*
9572 * Have mpt firmware abort this command
9573 */
9574
9575 if (slots->m_slot[sp->cmd_slot] != NULL) {
9576 rval = mptsas_ioc_task_management(mpt,
9577 MPI2_SCSITASKMGMT_TASKTYPE_ABORT_TASK, target,
9578 lun, NULL, 0, 0);
9579
9580 /*
9581 * The transport layer expects only TRUE and FALSE.
9582 * Therefore, if mptsas_ioc_task_management returns
9583 * FAILED we will return FALSE.
9584 */
9585 if (rval == FAILED)
9586 rval = FALSE;
9587 goto done;
9588 }
9589 }
9590
9591 /*
9592 * If pkt is NULL then abort task set
9593 */
9594 rval = mptsas_ioc_task_management(mpt,
9595 MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET, target, lun, NULL, 0, 0);
9596
9597 /*
9598 * The transport layer expects only TRUE and FALSE.
9599 * Therefore, if mptsas_ioc_task_management returns
9600 * FAILED we will return FALSE.
9601 */
9602 if (rval == FAILED)
9603 rval = FALSE;
9604
9605 #ifdef MPTSAS_TEST
9606 if (rval && mptsas_test_stop) {
9607 debug_enter("mptsas_do_scsi_abort");
9608 }
9609 #endif
9610
9611 done:
9612 mptsas_doneq_empty(mpt);
9613 return (rval);
9614 }
9615
9616 /*
9617 * capability handling:
9618 * (*tran_getcap). Get the capability named, and return its value.
9619 */
9620 static int
9621 mptsas_scsi_getcap(struct scsi_address *ap, char *cap, int tgtonly)
9622 {
9623 mptsas_t *mpt = ADDR2MPT(ap);
9624 int ckey;
9625 int rval = FALSE;
9626
9627 NDBG24(("mptsas_scsi_getcap: target=%d, cap=%s tgtonly=%x",
9628 ap->a_target, cap, tgtonly));
9629
9630 mutex_enter(&mpt->m_mutex);
9631
9632 if ((mptsas_scsi_capchk(cap, tgtonly, &ckey)) != TRUE) {
9633 mutex_exit(&mpt->m_mutex);
9634 return (UNDEFINED);
9635 }
9636
9637 switch (ckey) {
9638 case SCSI_CAP_DMA_MAX:
9639 rval = (int)mpt->m_msg_dma_attr.dma_attr_maxxfer;
9640 break;
9641 case SCSI_CAP_ARQ:
9642 rval = TRUE;
9643 break;
9644 case SCSI_CAP_MSG_OUT:
9645 case SCSI_CAP_PARITY:
9646 case SCSI_CAP_UNTAGGED_QING:
9647 rval = TRUE;
9648 break;
9649 case SCSI_CAP_TAGGED_QING:
9650 rval = TRUE;
9651 break;
9652 case SCSI_CAP_RESET_NOTIFICATION:
9653 rval = TRUE;
9654 break;
9655 case SCSI_CAP_LINKED_CMDS:
9656 rval = FALSE;
9657 break;
9658 case SCSI_CAP_QFULL_RETRIES:
9659 rval = ((mptsas_tgt_private_t *)(ap->a_hba_tran->
9660 tran_tgt_private))->t_private->m_qfull_retries;
9661 break;
9662 case SCSI_CAP_QFULL_RETRY_INTERVAL:
9663 rval = drv_hztousec(((mptsas_tgt_private_t *)
9664 (ap->a_hba_tran->tran_tgt_private))->
9665 t_private->m_qfull_retry_interval) / 1000;
9666 break;
9667 case SCSI_CAP_CDB_LEN:
9668 rval = CDB_GROUP4;
9669 break;
9670 case SCSI_CAP_INTERCONNECT_TYPE:
9671 rval = INTERCONNECT_SAS;
9672 break;
9673 case SCSI_CAP_TRAN_LAYER_RETRIES:
9674 if (mpt->m_ioc_capabilities &
9675 MPI2_IOCFACTS_CAPABILITY_TLR)
9676 rval = TRUE;
9677 else
9678 rval = FALSE;
9679 break;
9680 default:
9681 rval = UNDEFINED;
9682 break;
9683 }
9684
9685 NDBG24(("mptsas_scsi_getcap: %s, rval=%x", cap, rval));
9686
9687 mutex_exit(&mpt->m_mutex);
9688 return (rval);
9689 }
9690
9691 /*
9692 * (*tran_setcap). Set the capability named to the value given.
9693 */
9694 static int
9695 mptsas_scsi_setcap(struct scsi_address *ap, char *cap, int value, int tgtonly)
9696 {
9697 mptsas_t *mpt = ADDR2MPT(ap);
9698 int ckey;
9699 int rval = FALSE;
9700
9701 NDBG24(("mptsas_scsi_setcap: target=%d, cap=%s value=%x tgtonly=%x",
9702 ap->a_target, cap, value, tgtonly));
9703
9704 if (!tgtonly) {
9705 return (rval);
9706 }
9707
9708 mutex_enter(&mpt->m_mutex);
9709
9710 if ((mptsas_scsi_capchk(cap, tgtonly, &ckey)) != TRUE) {
9711 mutex_exit(&mpt->m_mutex);
9712 return (UNDEFINED);
9713 }
9714
9715 switch (ckey) {
9716 case SCSI_CAP_DMA_MAX:
9717 case SCSI_CAP_MSG_OUT:
9718 case SCSI_CAP_PARITY:
9719 case SCSI_CAP_INITIATOR_ID:
9720 case SCSI_CAP_LINKED_CMDS:
9721 case SCSI_CAP_UNTAGGED_QING:
9722 case SCSI_CAP_RESET_NOTIFICATION:
9723 /*
9724 * None of these are settable via
9725 * the capability interface.
9726 */
9727 break;
9728 case SCSI_CAP_ARQ:
9729 /*
9730 * We cannot turn off arq so return false if asked to
9731 */
9732 if (value) {
9733 rval = TRUE;
9734 } else {
9735 rval = FALSE;
9736 }
9737 break;
9738 case SCSI_CAP_TAGGED_QING:
9739 mptsas_set_throttle(mpt, ((mptsas_tgt_private_t *)
9740 (ap->a_hba_tran->tran_tgt_private))->t_private,
9741 MAX_THROTTLE);
9742 rval = TRUE;
9743 break;
9744 case SCSI_CAP_QFULL_RETRIES:
9745 ((mptsas_tgt_private_t *)(ap->a_hba_tran->tran_tgt_private))->
9746 t_private->m_qfull_retries = (uchar_t)value;
9747 rval = TRUE;
9748 break;
9749 case SCSI_CAP_QFULL_RETRY_INTERVAL:
9750 ((mptsas_tgt_private_t *)(ap->a_hba_tran->tran_tgt_private))->
9751 t_private->m_qfull_retry_interval =
9752 drv_usectohz(value * 1000);
9753 rval = TRUE;
9754 break;
9755 default:
9756 rval = UNDEFINED;
9757 break;
9758 }
9759 mutex_exit(&mpt->m_mutex);
9760 return (rval);
9761 }
9762
9763 /*
9764 * Utility routine for mptsas_ifsetcap/ifgetcap
9765 */
9766 /*ARGSUSED*/
9767 static int
9768 mptsas_scsi_capchk(char *cap, int tgtonly, int *cidxp)
9769 {
9770 NDBG24(("mptsas_scsi_capchk: cap=%s", cap));
9771
9772 if (!cap)
9773 return (FALSE);
9774
9775 *cidxp = scsi_hba_lookup_capstr(cap);
9776 return (TRUE);
9777 }
9778
9779 static int
9780 mptsas_alloc_active_slots(mptsas_t *mpt, int flag)
9781 {
9782 mptsas_slots_t *old_active = mpt->m_active;
9783 mptsas_slots_t *new_active;
9784 size_t size;
9785
9786 /*
9787 * if there are active commands, then we cannot
9788 * change size of active slots array.
9789 */
9790 ASSERT(mpt->m_ncmds == 0);
9791
9792 size = MPTSAS_SLOTS_SIZE(mpt);
9793 new_active = kmem_zalloc(size, flag);
9794 if (new_active == NULL) {
9795 NDBG1(("new active alloc failed"));
9796 return (-1);
9797 }
9798 /*
9799 * Since SMID 0 is reserved and the TM slot is reserved, the
9800 * number of slots that can be used at any one time is
9801 * m_max_requests - 2.
9802 */
9803 new_active->m_n_normal = (mpt->m_max_requests - 2);
9804 new_active->m_size = size;
9805 new_active->m_rotor = 1;
9806 if (old_active)
9807 mptsas_free_active_slots(mpt);
9808 mpt->m_active = new_active;
9809
9810 return (0);
9811 }
9812
9813 static void
9814 mptsas_free_active_slots(mptsas_t *mpt)
9815 {
9816 mptsas_slots_t *active = mpt->m_active;
9817 size_t size;
9818
9819 if (active == NULL)
9820 return;
9821 size = active->m_size;
9822 kmem_free(active, size);
9823 mpt->m_active = NULL;
9824 }
9825
9826 /*
9827 * Error logging, printing, and debug print routines.
9828 */
9829 static char *mptsas_label = "mpt_sas";
9830
9831 /*PRINTFLIKE3*/
9832 void
9833 mptsas_log(mptsas_t *mpt, int level, char *fmt, ...)
9834 {
9835 dev_info_t *dev;
9836 va_list ap;
9837
9838 if (mpt) {
9839 dev = mpt->m_dip;
9840 } else {
9841 dev = 0;
9842 }
9843
9844 mutex_enter(&mptsas_log_mutex);
9845
9846 va_start(ap, fmt);
9847 (void) vsprintf(mptsas_log_buf, fmt, ap);
9848 va_end(ap);
9849
9850 if (level == CE_CONT) {
9851 scsi_log(dev, mptsas_label, level, "%s\n", mptsas_log_buf);
9852 } else {
9853 scsi_log(dev, mptsas_label, level, "%s", mptsas_log_buf);
9854 }
9855
9856 mutex_exit(&mptsas_log_mutex);
9857 }
9858
9859 #ifdef MPTSAS_DEBUG
9860 /*
9861 * Use a circular buffer to log messages to private memory.
9862 * Increment idx atomically to minimize risk to miss lines.
9863 * It's fast and does not hold up the proceedings too much.
9864 */
9865 static const size_t mptsas_dbglog_linecnt = MPTSAS_DBGLOG_LINECNT;
9866 static const size_t mptsas_dbglog_linelen = MPTSAS_DBGLOG_LINELEN;
9867 static char mptsas_dbglog_bufs[MPTSAS_DBGLOG_LINECNT][MPTSAS_DBGLOG_LINELEN];
9868 static uint32_t mptsas_dbglog_idx = 0;
9869
9870 /*PRINTFLIKE1*/
9871 void
9872 mptsas_debug_log(char *fmt, ...)
9873 {
9874 va_list ap;
9875 uint32_t idx;
9876
9877 idx = atomic_inc_32_nv(&mptsas_dbglog_idx) &
9878 (mptsas_dbglog_linecnt - 1);
9879
9880 va_start(ap, fmt);
9881 (void) vsnprintf(mptsas_dbglog_bufs[idx],
9882 mptsas_dbglog_linelen, fmt, ap);
9883 va_end(ap);
9884 }
9885
9886 /*PRINTFLIKE1*/
9887 void
9888 mptsas_printf(char *fmt, ...)
9889 {
9890 dev_info_t *dev = 0;
9891 va_list ap;
9892
9893 mutex_enter(&mptsas_log_mutex);
9894
9895 va_start(ap, fmt);
9896 (void) vsprintf(mptsas_log_buf, fmt, ap);
9897 va_end(ap);
9898
9899 #ifdef PROM_PRINTF
9900 prom_printf("%s:\t%s\n", mptsas_label, mptsas_log_buf);
9901 #else
9902 scsi_log(dev, mptsas_label, CE_CONT, "!%s\n", mptsas_log_buf);
9903 #endif
9904 mutex_exit(&mptsas_log_mutex);
9905 }
9906 #endif
9907
9908 /*
9909 * timeout handling
9910 */
9911 static void
9912 mptsas_watch(void *arg)
9913 {
9914 #ifndef __lock_lint
9915 _NOTE(ARGUNUSED(arg))
9916 #endif
9917
9918 mptsas_t *mpt;
9919 uint32_t doorbell;
9920
9921 NDBG30(("mptsas_watch"));
9922
9923 rw_enter(&mptsas_global_rwlock, RW_READER);
9924 for (mpt = mptsas_head; mpt != (mptsas_t *)NULL; mpt = mpt->m_next) {
9925
9926 mutex_enter(&mpt->m_mutex);
9927
9928 /* Skip device if not powered on */
9929 if (mpt->m_options & MPTSAS_OPT_PM) {
9930 if (mpt->m_power_level == PM_LEVEL_D0) {
9931 (void) pm_busy_component(mpt->m_dip, 0);
9932 mpt->m_busy = 1;
9933 } else {
9934 mutex_exit(&mpt->m_mutex);
9935 continue;
9936 }
9937 }
9938
9939 /*
9940 * Check if controller is in a FAULT state. If so, reset it.
9941 */
9942 doorbell = ddi_get32(mpt->m_datap, &mpt->m_reg->Doorbell);
9943 if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
9944 doorbell &= MPI2_DOORBELL_DATA_MASK;
9945 mptsas_log(mpt, CE_WARN, "MPT Firmware Fault, "
9946 "code: %04x", doorbell);
9947 mpt->m_softstate &= ~MPTSAS_SS_MSG_UNIT_RESET;
9948 if ((mptsas_reset_handler(mpt)) == DDI_FAILURE) {
9949 mptsas_log(mpt, CE_WARN, "Reset failed"
9950 "after fault was detected");
9951 }
9952 }
9953
9954 /*
9955 * For now, always call mptsas_watchsubr.
9956 */
9957 mptsas_watchsubr(mpt);
9958
9959 if (mpt->m_options & MPTSAS_OPT_PM) {
9960 mpt->m_busy = 0;
9961 (void) pm_idle_component(mpt->m_dip, 0);
9962 }
9963
9964 mutex_exit(&mpt->m_mutex);
9965 }
9966 rw_exit(&mptsas_global_rwlock);
9967
9968 mutex_enter(&mptsas_global_mutex);
9969 if (mptsas_timeouts_enabled)
9970 mptsas_timeout_id = timeout(mptsas_watch, NULL, mptsas_tick);
9971 mutex_exit(&mptsas_global_mutex);
9972 }
9973
9974 static void
9975 mptsas_watchsubr_tgt(mptsas_t *mpt, mptsas_target_t *ptgt, hrtime_t timestamp)
9976 {
9977 mptsas_cmd_t *cmd;
9978
9979 /*
9980 * If we were draining due to a qfull condition,
9981 * go back to full throttle.
9982 */
9983 if ((ptgt->m_t_throttle < MAX_THROTTLE) &&
9984 (ptgt->m_t_throttle > HOLD_THROTTLE) &&
9985 (ptgt->m_t_ncmds < ptgt->m_t_throttle)) {
9986 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE);
9987 mptsas_restart_hba(mpt);
9988 }
9989
9990 cmd = TAILQ_LAST(&ptgt->m_active_cmdq, mptsas_active_cmdq);
9991 if (cmd == NULL)
9992 return;
9993
9994 if (cmd->cmd_active_expiration <= timestamp) {
9995 /*
9996 * Earliest command timeout expired. Drain throttle.
9997 */
9998 mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE);
9999
10000 /*
10001 * Check for remaining commands.
10002 */
10003 cmd = TAILQ_FIRST(&ptgt->m_active_cmdq);
10004 if (cmd->cmd_active_expiration > timestamp) {
10005 /*
10006 * Wait for remaining commands to complete or
10007 * time out.
10008 */
10009 NDBG23(("command timed out, pending drain"));
10010 return;
10011 }
10012
10013 /*
10014 * All command timeouts expired.
10015 */
10016 mptsas_log(mpt, CE_NOTE, "Timeout of %d seconds "
10017 "expired with %d commands on target %d lun %d.",
10018 cmd->cmd_pkt->pkt_time, ptgt->m_t_ncmds,
10019 ptgt->m_devhdl, Lun(cmd));
10020
10021 mptsas_cmd_timeout(mpt, ptgt);
10022 } else if (cmd->cmd_active_expiration <=
10023 timestamp + (hrtime_t)mptsas_scsi_watchdog_tick * NANOSEC) {
10024 NDBG23(("pending timeout"));
10025 mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE);
10026 }
10027 }
10028
10029 static void
10030 mptsas_watchsubr(mptsas_t *mpt)
10031 {
10032 int i;
10033 mptsas_cmd_t *cmd;
10034 mptsas_target_t *ptgt = NULL;
10035 hrtime_t timestamp = gethrtime();
10036
10037 ASSERT(MUTEX_HELD(&mpt->m_mutex));
10038
10039 NDBG30(("mptsas_watchsubr: mpt=0x%p", (void *)mpt));
10040
10041 #ifdef MPTSAS_TEST
10042 if (mptsas_enable_untagged) {
10043 mptsas_test_untagged++;
10044 }
10045 #endif
10046
10047 /*
10048 * Check for commands stuck in active slot
10049 * Account for TM requests, which use the last SMID.
10050 */
10051 for (i = 0; i <= mpt->m_active->m_n_normal; i++) {
10052 if ((cmd = mpt->m_active->m_slot[i]) != NULL) {
10053 if (cmd->cmd_active_expiration <= timestamp) {
10054 if ((cmd->cmd_flags & CFLAG_CMDIOC) == 0) {
10055 /*
10056 * There seems to be a command stuck
10057 * in the active slot. Drain throttle.
10058 */
10059 mptsas_set_throttle(mpt,
10060 cmd->cmd_tgt_addr,
10061 DRAIN_THROTTLE);
10062 } else if (cmd->cmd_flags &
10063 (CFLAG_PASSTHRU | CFLAG_CONFIG |
10064 CFLAG_FW_DIAG)) {
10065 /*
10066 * passthrough command timeout
10067 */
10068 cmd->cmd_flags |= (CFLAG_FINISHED |
10069 CFLAG_TIMEOUT);
10070 cv_broadcast(&mpt->m_passthru_cv);
10071 cv_broadcast(&mpt->m_config_cv);
10072 cv_broadcast(&mpt->m_fw_diag_cv);
10073 }
10074 }
10075 }
10076 }
10077
10078 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL;
10079 ptgt = refhash_next(mpt->m_targets, ptgt)) {
10080 mptsas_watchsubr_tgt(mpt, ptgt, timestamp);
10081 }
10082
10083 for (ptgt = refhash_first(mpt->m_tmp_targets); ptgt != NULL;
10084 ptgt = refhash_next(mpt->m_tmp_targets, ptgt)) {
10085 mptsas_watchsubr_tgt(mpt, ptgt, timestamp);
10086 }
10087 }
10088
10089 /*
10090 * timeout recovery
10091 */
10092 static void
10093 mptsas_cmd_timeout(mptsas_t *mpt, mptsas_target_t *ptgt)
10094 {
10095 uint16_t devhdl;
10096 uint64_t sas_wwn;
10097 uint8_t phy;
10098 char wwn_str[MPTSAS_WWN_STRLEN];
10099
10100 devhdl = ptgt->m_devhdl;
10101 sas_wwn = ptgt->m_addr.mta_wwn;
10102 phy = ptgt->m_phynum;
10103 if (sas_wwn == 0) {
10104 (void) sprintf(wwn_str, "p%x", phy);
10105 } else {
10106 (void) sprintf(wwn_str, "w%016"PRIx64, sas_wwn);
10107 }
10108
10109 NDBG29(("mptsas_cmd_timeout: target=%d", devhdl));
10110 mptsas_log(mpt, CE_WARN, "Disconnected command timeout for "
10111 "target %d %s, enclosure %u", devhdl, wwn_str,
10112 ptgt->m_enclosure);
10113
10114 /*
10115 * Abort all outstanding commands on the device.
10116 */
10117 NDBG29(("mptsas_cmd_timeout: device reset"));
10118 if (mptsas_do_scsi_reset(mpt, devhdl) != TRUE) {
10119 mptsas_log(mpt, CE_WARN, "Target %d reset for command timeout "
10120 "recovery failed!", devhdl);
10121 }
10122 }
10123
10124 /*
10125 * Device / Hotplug control
10126 */
10127 static int
10128 mptsas_scsi_quiesce(dev_info_t *dip)
10129 {
10130 mptsas_t *mpt;
10131 scsi_hba_tran_t *tran;
10132
10133 tran = ddi_get_driver_private(dip);
10134 if (tran == NULL || (mpt = TRAN2MPT(tran)) == NULL)
10135 return (-1);
10136
10137 return (mptsas_quiesce_bus(mpt));
10138 }
10139
10140 static int
10141 mptsas_scsi_unquiesce(dev_info_t *dip)
10142 {
10143 mptsas_t *mpt;
10144 scsi_hba_tran_t *tran;
10145
10146 tran = ddi_get_driver_private(dip);
10147 if (tran == NULL || (mpt = TRAN2MPT(tran)) == NULL)
10148 return (-1);
10149
10150 return (mptsas_unquiesce_bus(mpt));
10151 }
10152
10153 static int
10154 mptsas_quiesce_bus(mptsas_t *mpt)
10155 {
10156 mptsas_target_t *ptgt = NULL;
10157
10158 NDBG28(("mptsas_quiesce_bus"));
10159 mutex_enter(&mpt->m_mutex);
10160
10161 /* Set all the throttles to zero */
10162 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL;
10163 ptgt = refhash_next(mpt->m_targets, ptgt)) {
10164 mptsas_set_throttle(mpt, ptgt, HOLD_THROTTLE);
10165 }
10166
10167 /* If there are any outstanding commands in the queue */
10168 if (mpt->m_ncmds) {
10169 mpt->m_softstate |= MPTSAS_SS_DRAINING;
10170 mpt->m_quiesce_timeid = timeout(mptsas_ncmds_checkdrain,
10171 mpt, (MPTSAS_QUIESCE_TIMEOUT * drv_usectohz(1000000)));
10172 if (cv_wait_sig(&mpt->m_cv, &mpt->m_mutex) == 0) {
10173 /*
10174 * Quiesce has been interrupted
10175 */
10176 mpt->m_softstate &= ~MPTSAS_SS_DRAINING;
10177 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL;
10178 ptgt = refhash_next(mpt->m_targets, ptgt)) {
10179 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE);
10180 }
10181 mptsas_restart_hba(mpt);
10182 if (mpt->m_quiesce_timeid != 0) {
10183 timeout_id_t tid = mpt->m_quiesce_timeid;
10184 mpt->m_quiesce_timeid = 0;
10185 mutex_exit(&mpt->m_mutex);
10186 (void) untimeout(tid);
10187 return (-1);
10188 }
10189 mutex_exit(&mpt->m_mutex);
10190 return (-1);
10191 } else {
10192 /* Bus has been quiesced */
10193 ASSERT(mpt->m_quiesce_timeid == 0);
10194 mpt->m_softstate &= ~MPTSAS_SS_DRAINING;
10195 mpt->m_softstate |= MPTSAS_SS_QUIESCED;
10196 mutex_exit(&mpt->m_mutex);
10197 return (0);
10198 }
10199 }
10200 /* Bus was not busy - QUIESCED */
10201 mutex_exit(&mpt->m_mutex);
10202
10203 return (0);
10204 }
10205
10206 static int
10207 mptsas_unquiesce_bus(mptsas_t *mpt)
10208 {
10209 mptsas_target_t *ptgt = NULL;
10210
10211 NDBG28(("mptsas_unquiesce_bus"));
10212 mutex_enter(&mpt->m_mutex);
10213 mpt->m_softstate &= ~MPTSAS_SS_QUIESCED;
10214 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL;
10215 ptgt = refhash_next(mpt->m_targets, ptgt)) {
10216 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE);
10217 }
10218 mptsas_restart_hba(mpt);
10219 mutex_exit(&mpt->m_mutex);
10220 return (0);
10221 }
10222
10223 static void
10224 mptsas_ncmds_checkdrain(void *arg)
10225 {
10226 mptsas_t *mpt = arg;
10227 mptsas_target_t *ptgt = NULL;
10228
10229 mutex_enter(&mpt->m_mutex);
10230 if (mpt->m_softstate & MPTSAS_SS_DRAINING) {
10231 mpt->m_quiesce_timeid = 0;
10232 if (mpt->m_ncmds == 0) {
10233 /* Command queue has been drained */
10234 cv_signal(&mpt->m_cv);
10235 } else {
10236 /*
10237 * The throttle may have been reset because
10238 * of a SCSI bus reset
10239 */
10240 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL;
10241 ptgt = refhash_next(mpt->m_targets, ptgt)) {
10242 mptsas_set_throttle(mpt, ptgt, HOLD_THROTTLE);
10243 }
10244
10245 mpt->m_quiesce_timeid = timeout(mptsas_ncmds_checkdrain,
10246 mpt, (MPTSAS_QUIESCE_TIMEOUT *
10247 drv_usectohz(1000000)));
10248 }
10249 }
10250 mutex_exit(&mpt->m_mutex);
10251 }
10252
10253 /*ARGSUSED*/
10254 static void
10255 mptsas_dump_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd)
10256 {
10257 int i;
10258 uint8_t *cp = (uchar_t *)cmd->cmd_pkt->pkt_cdbp;
10259 char buf[128];
10260
10261 buf[0] = '\0';
10262 NDBG25(("?Cmd (0x%p) dump for Target %d Lun %d:\n", (void *)cmd,
10263 Tgt(cmd), Lun(cmd)));
10264 (void) sprintf(&buf[0], "\tcdb=[");
10265 for (i = 0; i < (int)cmd->cmd_cdblen; i++) {
10266 (void) sprintf(&buf[strlen(buf)], " 0x%x", *cp++);
10267 }
10268 (void) sprintf(&buf[strlen(buf)], " ]");
10269 NDBG25(("?%s\n", buf));
10270 NDBG25(("?pkt_flags=0x%x pkt_statistics=0x%x pkt_state=0x%x\n",
10271 cmd->cmd_pkt->pkt_flags, cmd->cmd_pkt->pkt_statistics,
10272 cmd->cmd_pkt->pkt_state));
10273 NDBG25(("?pkt_scbp=0x%x cmd_flags=0x%x\n", cmd->cmd_pkt->pkt_scbp ?
10274 *(cmd->cmd_pkt->pkt_scbp) : 0, cmd->cmd_flags));
10275 }
10276
10277 static void
10278 mptsas_passthru_sge(ddi_acc_handle_t acc_hdl, mptsas_pt_request_t *pt,
10279 pMpi2SGESimple64_t sgep)
10280 {
10281 uint32_t sge_flags;
10282 uint32_t data_size, dataout_size;
10283 ddi_dma_cookie_t data_cookie;
10284 ddi_dma_cookie_t dataout_cookie;
10285
10286 data_size = pt->data_size;
10287 dataout_size = pt->dataout_size;
10288 data_cookie = pt->data_cookie;
10289 dataout_cookie = pt->dataout_cookie;
10290
10291 if (dataout_size) {
10292 sge_flags = dataout_size |
10293 ((uint32_t)(MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
10294 MPI2_SGE_FLAGS_END_OF_BUFFER |
10295 MPI2_SGE_FLAGS_HOST_TO_IOC |
10296 MPI2_SGE_FLAGS_64_BIT_ADDRESSING) <<
10297 MPI2_SGE_FLAGS_SHIFT);
10298 ddi_put32(acc_hdl, &sgep->FlagsLength, sge_flags);
10299 ddi_put32(acc_hdl, &sgep->Address.Low,
10300 (uint32_t)(dataout_cookie.dmac_laddress &
10301 0xffffffffull));
10302 ddi_put32(acc_hdl, &sgep->Address.High,
10303 (uint32_t)(dataout_cookie.dmac_laddress
10304 >> 32));
10305 sgep++;
10306 }
10307 sge_flags = data_size;
10308 sge_flags |= ((uint32_t)(MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
10309 MPI2_SGE_FLAGS_LAST_ELEMENT |
10310 MPI2_SGE_FLAGS_END_OF_BUFFER |
10311 MPI2_SGE_FLAGS_END_OF_LIST |
10312 MPI2_SGE_FLAGS_64_BIT_ADDRESSING) <<
10313 MPI2_SGE_FLAGS_SHIFT);
10314 if (pt->direction == MPTSAS_PASS_THRU_DIRECTION_WRITE) {
10315 sge_flags |= ((uint32_t)(MPI2_SGE_FLAGS_HOST_TO_IOC) <<
10316 MPI2_SGE_FLAGS_SHIFT);
10317 } else {
10318 sge_flags |= ((uint32_t)(MPI2_SGE_FLAGS_IOC_TO_HOST) <<
10319 MPI2_SGE_FLAGS_SHIFT);
10320 }
10321 ddi_put32(acc_hdl, &sgep->FlagsLength,
10322 sge_flags);
10323 ddi_put32(acc_hdl, &sgep->Address.Low,
10324 (uint32_t)(data_cookie.dmac_laddress &
10325 0xffffffffull));
10326 ddi_put32(acc_hdl, &sgep->Address.High,
10327 (uint32_t)(data_cookie.dmac_laddress >> 32));
10328 }
10329
10330 static void
10331 mptsas_passthru_ieee_sge(ddi_acc_handle_t acc_hdl, mptsas_pt_request_t *pt,
10332 pMpi2IeeeSgeSimple64_t ieeesgep)
10333 {
10334 uint8_t sge_flags;
10335 uint32_t data_size, dataout_size;
10336 ddi_dma_cookie_t data_cookie;
10337 ddi_dma_cookie_t dataout_cookie;
10338
10339 data_size = pt->data_size;
10340 dataout_size = pt->dataout_size;
10341 data_cookie = pt->data_cookie;
10342 dataout_cookie = pt->dataout_cookie;
10343
10344 sge_flags = (MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
10345 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR);
10346 if (dataout_size) {
10347 ddi_put32(acc_hdl, &ieeesgep->Length, dataout_size);
10348 ddi_put32(acc_hdl, &ieeesgep->Address.Low,
10349 (uint32_t)(dataout_cookie.dmac_laddress &
10350 0xffffffffull));
10351 ddi_put32(acc_hdl, &ieeesgep->Address.High,
10352 (uint32_t)(dataout_cookie.dmac_laddress >> 32));
10353 ddi_put8(acc_hdl, &ieeesgep->Flags, sge_flags);
10354 ieeesgep++;
10355 }
10356 sge_flags |= MPI25_IEEE_SGE_FLAGS_END_OF_LIST;
10357 ddi_put32(acc_hdl, &ieeesgep->Length, data_size);
10358 ddi_put32(acc_hdl, &ieeesgep->Address.Low,
10359 (uint32_t)(data_cookie.dmac_laddress & 0xffffffffull));
10360 ddi_put32(acc_hdl, &ieeesgep->Address.High,
10361 (uint32_t)(data_cookie.dmac_laddress >> 32));
10362 ddi_put8(acc_hdl, &ieeesgep->Flags, sge_flags);
10363 }
10364
10365 static void
10366 mptsas_start_passthru(mptsas_t *mpt, mptsas_cmd_t *cmd)
10367 {
10368 caddr_t memp;
10369 pMPI2RequestHeader_t request_hdrp;
10370 struct scsi_pkt *pkt = cmd->cmd_pkt;
10371 mptsas_pt_request_t *pt = pkt->pkt_ha_private;
10372 uint32_t request_size;
10373 uint32_t i;
10374 uint64_t request_desc = 0;
10375 uint8_t desc_type;
10376 uint16_t SMID;
10377 uint8_t *request, function;
10378 ddi_dma_handle_t dma_hdl = mpt->m_dma_req_frame_hdl;
10379 ddi_acc_handle_t acc_hdl = mpt->m_acc_req_frame_hdl;
10380
10381 desc_type = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE;
10382
10383 request = pt->request;
10384 request_size = pt->request_size;
10385
10386 SMID = cmd->cmd_slot;
10387
10388 /*
10389 * Store the passthrough message in memory location
10390 * corresponding to our slot number
10391 */
10392 memp = mpt->m_req_frame + (mpt->m_req_frame_size * SMID);
10393 request_hdrp = (pMPI2RequestHeader_t)memp;
10394 bzero(memp, mpt->m_req_frame_size);
10395
10396 for (i = 0; i < request_size; i++) {
10397 bcopy(request + i, memp + i, 1);
10398 }
10399
10400 NDBG15(("mptsas_start_passthru: Func 0x%x, MsgFlags 0x%x, "
10401 "size=%d, in %d, out %d, SMID %d", request_hdrp->Function,
10402 request_hdrp->MsgFlags, request_size,
10403 pt->data_size, pt->dataout_size, SMID));
10404
10405 /*
10406 * Add an SGE, even if the length is zero.
10407 */
10408 if (mpt->m_MPI25 && pt->simple == 0) {
10409 mptsas_passthru_ieee_sge(acc_hdl, pt,
10410 (pMpi2IeeeSgeSimple64_t)
10411 ((uint8_t *)request_hdrp + pt->sgl_offset));
10412 } else {
10413 mptsas_passthru_sge(acc_hdl, pt,
10414 (pMpi2SGESimple64_t)
10415 ((uint8_t *)request_hdrp + pt->sgl_offset));
10416 }
10417
10418 function = request_hdrp->Function;
10419 if ((function == MPI2_FUNCTION_SCSI_IO_REQUEST) ||
10420 (function == MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH)) {
10421 pMpi2SCSIIORequest_t scsi_io_req;
10422 caddr_t arsbuf;
10423 uint8_t ars_size;
10424 uint32_t ars_dmaaddrlow;
10425
10426 NDBG15(("mptsas_start_passthru: Is SCSI IO Req"));
10427 scsi_io_req = (pMpi2SCSIIORequest_t)request_hdrp;
10428
10429 if (cmd->cmd_extrqslen != 0) {
10430 /*
10431 * Mapping of the buffer was done in
10432 * mptsas_do_passthru().
10433 * Calculate the DMA address with the same offset.
10434 */
10435 arsbuf = cmd->cmd_arq_buf;
10436 ars_size = cmd->cmd_extrqslen;
10437 ars_dmaaddrlow = (mpt->m_req_sense_dma_addr +
10438 ((uintptr_t)arsbuf - (uintptr_t)mpt->m_req_sense)) &
10439 0xffffffffu;
10440 } else {
10441 arsbuf = mpt->m_req_sense +
10442 (mpt->m_req_sense_size * (SMID-1));
10443 cmd->cmd_arq_buf = arsbuf;
10444 ars_size = mpt->m_req_sense_size;
10445 ars_dmaaddrlow = (mpt->m_req_sense_dma_addr +
10446 (mpt->m_req_sense_size * (SMID-1))) &
10447 0xffffffffu;
10448 }
10449 bzero(arsbuf, ars_size);
10450
10451 ddi_put8(acc_hdl, &scsi_io_req->SenseBufferLength, ars_size);
10452 ddi_put32(acc_hdl, &scsi_io_req->SenseBufferLowAddress,
10453 ars_dmaaddrlow);
10454
10455 /*
10456 * Put SGE for data and data_out buffer at the end of
10457 * scsi_io_request message header.(64 bytes in total)
10458 * Set SGLOffset0 value
10459 */
10460 ddi_put8(acc_hdl, &scsi_io_req->SGLOffset0,
10461 offsetof(MPI2_SCSI_IO_REQUEST, SGL) / 4);
10462
10463 /*
10464 * Setup descriptor info. RAID passthrough must use the
10465 * default request descriptor which is already set, so if this
10466 * is a SCSI IO request, change the descriptor to SCSI IO.
10467 */
10468 if (function == MPI2_FUNCTION_SCSI_IO_REQUEST) {
10469 desc_type = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO;
10470 request_desc = ((uint64_t)ddi_get16(acc_hdl,
10471 &scsi_io_req->DevHandle) << 48);
10472 }
10473 (void) ddi_dma_sync(mpt->m_dma_req_sense_hdl, 0, 0,
10474 DDI_DMA_SYNC_FORDEV);
10475 }
10476
10477 /*
10478 * We must wait till the message has been completed before
10479 * beginning the next message so we wait for this one to
10480 * finish.
10481 */
10482 (void) ddi_dma_sync(dma_hdl, 0, 0, DDI_DMA_SYNC_FORDEV);
10483 request_desc |= (SMID << 16) + desc_type;
10484 cmd->cmd_rfm = NULL;
10485 MPTSAS_START_CMD(mpt, request_desc);
10486 if ((mptsas_check_dma_handle(dma_hdl) != DDI_SUCCESS) ||
10487 (mptsas_check_acc_handle(acc_hdl) != DDI_SUCCESS)) {
10488 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
10489 }
10490 }
10491
10492 typedef void (mptsas_pre_f)(mptsas_t *, mptsas_pt_request_t *);
10493 static mptsas_pre_f mpi_pre_ioc_facts;
10494 static mptsas_pre_f mpi_pre_port_facts;
10495 static mptsas_pre_f mpi_pre_fw_download;
10496 static mptsas_pre_f mpi_pre_fw_25_download;
10497 static mptsas_pre_f mpi_pre_fw_upload;
10498 static mptsas_pre_f mpi_pre_fw_25_upload;
10499 static mptsas_pre_f mpi_pre_sata_passthrough;
10500 static mptsas_pre_f mpi_pre_smp_passthrough;
10501 static mptsas_pre_f mpi_pre_config;
10502 static mptsas_pre_f mpi_pre_sas_io_unit_control;
10503 static mptsas_pre_f mpi_pre_scsi_io_req;
10504
10505 /*
10506 * Prepare the pt for a SAS2 FW_DOWNLOAD request.
10507 */
10508 static void
10509 mpi_pre_fw_download(mptsas_t *mpt, mptsas_pt_request_t *pt)
10510 {
10511 pMpi2FWDownloadTCSGE_t tcsge;
10512 pMpi2FWDownloadRequest req;
10513
10514 /*
10515 * If SAS3, call separate function.
10516 */
10517 if (mpt->m_MPI25) {
10518 mpi_pre_fw_25_download(mpt, pt);
10519 return;
10520 }
10521
10522 /*
10523 * User requests should come in with the Transaction
10524 * context element where the SGL will go. Putting the
10525 * SGL after that seems to work, but don't really know
10526 * why. Other drivers tend to create an extra SGL and
10527 * refer to the TCE through that.
10528 */
10529 req = (pMpi2FWDownloadRequest)pt->request;
10530 tcsge = (pMpi2FWDownloadTCSGE_t)&req->SGL;
10531 if (tcsge->ContextSize != 0 || tcsge->DetailsLength != 12 ||
10532 tcsge->Flags != MPI2_SGE_FLAGS_TRANSACTION_ELEMENT) {
10533 mptsas_log(mpt, CE_WARN, "FW Download tce invalid!");
10534 }
10535
10536 pt->sgl_offset = offsetof(MPI2_FW_DOWNLOAD_REQUEST, SGL) +
10537 sizeof (*tcsge);
10538 if (pt->request_size != pt->sgl_offset)
10539 NDBG15(("mpi_pre_fw_download(): Incorrect req size, "
10540 "0x%x, should be 0x%x, dataoutsz 0x%x",
10541 (int)pt->request_size, (int)pt->sgl_offset,
10542 (int)pt->dataout_size));
10543 if (pt->data_size < sizeof (MPI2_FW_DOWNLOAD_REPLY))
10544 NDBG15(("mpi_pre_fw_download(): Incorrect rep size, "
10545 "0x%x, should be 0x%x", pt->data_size,
10546 (int)sizeof (MPI2_FW_DOWNLOAD_REPLY)));
10547 }
10548
10549 /*
10550 * Prepare the pt for a SAS3 FW_DOWNLOAD request.
10551 */
10552 static void
10553 mpi_pre_fw_25_download(mptsas_t *mpt, mptsas_pt_request_t *pt)
10554 {
10555 pMpi2FWDownloadTCSGE_t tcsge;
10556 pMpi2FWDownloadRequest req2;
10557 pMpi25FWDownloadRequest req25;
10558
10559 /*
10560 * User requests should come in with the Transaction
10561 * context element where the SGL will go. The new firmware
10562 * Doesn't use TCE and has space in the main request for
10563 * this information. So move to the right place.
10564 */
10565 req2 = (pMpi2FWDownloadRequest)pt->request;
10566 req25 = (pMpi25FWDownloadRequest)pt->request;
10567 tcsge = (pMpi2FWDownloadTCSGE_t)&req2->SGL;
10568 if (tcsge->ContextSize != 0 || tcsge->DetailsLength != 12 ||
10569 tcsge->Flags != MPI2_SGE_FLAGS_TRANSACTION_ELEMENT) {
10570 mptsas_log(mpt, CE_WARN, "FW Download tce invalid!");
10571 }
10572 req25->ImageOffset = tcsge->ImageOffset;
10573 req25->ImageSize = tcsge->ImageSize;
10574
10575 pt->sgl_offset = offsetof(MPI25_FW_DOWNLOAD_REQUEST, SGL);
10576 if (pt->request_size != pt->sgl_offset)
10577 NDBG15(("mpi_pre_fw_25_download(): Incorrect req size, "
10578 "0x%x, should be 0x%x, dataoutsz 0x%x",
10579 pt->request_size, pt->sgl_offset,
10580 pt->dataout_size));
10581 if (pt->data_size < sizeof (MPI2_FW_DOWNLOAD_REPLY))
10582 NDBG15(("mpi_pre_fw_25_download(): Incorrect rep size, "
10583 "0x%x, should be 0x%x", pt->data_size,
10584 (int)sizeof (MPI2_FW_UPLOAD_REPLY)));
10585 }
10586
10587 /*
10588 * Prepare the pt for a SAS2 FW_UPLOAD request.
10589 */
10590 static void
10591 mpi_pre_fw_upload(mptsas_t *mpt, mptsas_pt_request_t *pt)
10592 {
10593 pMpi2FWUploadTCSGE_t tcsge;
10594 pMpi2FWUploadRequest_t req;
10595
10596 /*
10597 * If SAS3, call separate function.
10598 */
10599 if (mpt->m_MPI25) {
10600 mpi_pre_fw_25_upload(mpt, pt);
10601 return;
10602 }
10603
10604 /*
10605 * User requests should come in with the Transaction
10606 * context element where the SGL will go. Putting the
10607 * SGL after that seems to work, but don't really know
10608 * why. Other drivers tend to create an extra SGL and
10609 * refer to the TCE through that.
10610 */
10611 req = (pMpi2FWUploadRequest_t)pt->request;
10612 tcsge = (pMpi2FWUploadTCSGE_t)&req->SGL;
10613 if (tcsge->ContextSize != 0 || tcsge->DetailsLength != 12 ||
10614 tcsge->Flags != MPI2_SGE_FLAGS_TRANSACTION_ELEMENT) {
10615 mptsas_log(mpt, CE_WARN, "FW Upload tce invalid!");
10616 }
10617
10618 pt->sgl_offset = offsetof(MPI2_FW_UPLOAD_REQUEST, SGL) +
10619 sizeof (*tcsge);
10620 if (pt->request_size != pt->sgl_offset)
10621 NDBG15(("mpi_pre_fw_upload(): Incorrect req size, "
10622 "0x%x, should be 0x%x, dataoutsz 0x%x",
10623 pt->request_size, pt->sgl_offset,
10624 pt->dataout_size));
10625 if (pt->data_size < sizeof (MPI2_FW_UPLOAD_REPLY))
10626 NDBG15(("mpi_pre_fw_upload(): Incorrect rep size, "
10627 "0x%x, should be 0x%x", pt->data_size,
10628 (int)sizeof (MPI2_FW_UPLOAD_REPLY)));
10629 }
10630
10631 /*
10632 * Prepare the pt a SAS3 FW_UPLOAD request.
10633 */
10634 static void
10635 mpi_pre_fw_25_upload(mptsas_t *mpt, mptsas_pt_request_t *pt)
10636 {
10637 pMpi2FWUploadTCSGE_t tcsge;
10638 pMpi2FWUploadRequest_t req2;
10639 pMpi25FWUploadRequest_t req25;
10640
10641 /*
10642 * User requests should come in with the Transaction
10643 * context element where the SGL will go. The new firmware
10644 * Doesn't use TCE and has space in the main request for
10645 * this information. So move to the right place.
10646 */
10647 req2 = (pMpi2FWUploadRequest_t)pt->request;
10648 req25 = (pMpi25FWUploadRequest_t)pt->request;
10649 tcsge = (pMpi2FWUploadTCSGE_t)&req2->SGL;
10650 if (tcsge->ContextSize != 0 || tcsge->DetailsLength != 12 ||
10651 tcsge->Flags != MPI2_SGE_FLAGS_TRANSACTION_ELEMENT) {
10652 mptsas_log(mpt, CE_WARN, "FW Upload tce invalid!");
10653 }
10654 req25->ImageOffset = tcsge->ImageOffset;
10655 req25->ImageSize = tcsge->ImageSize;
10656
10657 pt->sgl_offset = offsetof(MPI25_FW_UPLOAD_REQUEST, SGL);
10658 if (pt->request_size != pt->sgl_offset)
10659 NDBG15(("mpi_pre_fw_25_upload(): Incorrect req size, "
10660 "0x%x, should be 0x%x, dataoutsz 0x%x",
10661 pt->request_size, pt->sgl_offset,
10662 pt->dataout_size));
10663 if (pt->data_size < sizeof (MPI2_FW_UPLOAD_REPLY))
10664 NDBG15(("mpi_pre_fw_25_upload(): Incorrect rep size, "
10665 "0x%x, should be 0x%x", pt->data_size,
10666 (int)sizeof (MPI2_FW_UPLOAD_REPLY)));
10667 }
10668
10669 /*
10670 * Prepare the pt for an IOC_FACTS request.
10671 */
10672 static void
10673 mpi_pre_ioc_facts(mptsas_t *mpt, mptsas_pt_request_t *pt)
10674 {
10675 #ifndef __lock_lint
10676 _NOTE(ARGUNUSED(mpt))
10677 #endif
10678 if (pt->request_size != sizeof (MPI2_IOC_FACTS_REQUEST))
10679 NDBG15(("mpi_pre_ioc_facts(): Incorrect req size, "
10680 "0x%x, should be 0x%x, dataoutsz 0x%x",
10681 pt->request_size,
10682 (int)sizeof (MPI2_IOC_FACTS_REQUEST),
10683 pt->dataout_size));
10684 if (pt->data_size != sizeof (MPI2_IOC_FACTS_REPLY))
10685 NDBG15(("mpi_pre_ioc_facts(): Incorrect rep size, "
10686 "0x%x, should be 0x%x", pt->data_size,
10687 (int)sizeof (MPI2_IOC_FACTS_REPLY)));
10688 pt->sgl_offset = (uint16_t)pt->request_size;
10689 }
10690
10691 /*
10692 * Prepare the pt for a PORT_FACTS request.
10693 */
10694 static void
10695 mpi_pre_port_facts(mptsas_t *mpt, mptsas_pt_request_t *pt)
10696 {
10697 #ifndef __lock_lint
10698 _NOTE(ARGUNUSED(mpt))
10699 #endif
10700 if (pt->request_size != sizeof (MPI2_PORT_FACTS_REQUEST))
10701 NDBG15(("mpi_pre_port_facts(): Incorrect req size, "
10702 "0x%x, should be 0x%x, dataoutsz 0x%x",
10703 pt->request_size,
10704 (int)sizeof (MPI2_PORT_FACTS_REQUEST),
10705 pt->dataout_size));
10706 if (pt->data_size != sizeof (MPI2_PORT_FACTS_REPLY))
10707 NDBG15(("mpi_pre_port_facts(): Incorrect rep size, "
10708 "0x%x, should be 0x%x", pt->data_size,
10709 (int)sizeof (MPI2_PORT_FACTS_REPLY)));
10710 pt->sgl_offset = (uint16_t)pt->request_size;
10711 }
10712
10713 /*
10714 * Prepare pt for a SATA_PASSTHROUGH request.
10715 */
10716 static void
10717 mpi_pre_sata_passthrough(mptsas_t *mpt, mptsas_pt_request_t *pt)
10718 {
10719 #ifndef __lock_lint
10720 _NOTE(ARGUNUSED(mpt))
10721 #endif
10722 pt->sgl_offset = offsetof(MPI2_SATA_PASSTHROUGH_REQUEST, SGL);
10723 if (pt->request_size != pt->sgl_offset)
10724 NDBG15(("mpi_pre_sata_passthrough(): Incorrect req size, "
10725 "0x%x, should be 0x%x, dataoutsz 0x%x",
10726 pt->request_size, pt->sgl_offset,
10727 pt->dataout_size));
10728 if (pt->data_size != sizeof (MPI2_SATA_PASSTHROUGH_REPLY))
10729 NDBG15(("mpi_pre_sata_passthrough(): Incorrect rep size, "
10730 "0x%x, should be 0x%x", pt->data_size,
10731 (int)sizeof (MPI2_SATA_PASSTHROUGH_REPLY)));
10732 }
10733
10734 static void
10735 mpi_pre_smp_passthrough(mptsas_t *mpt, mptsas_pt_request_t *pt)
10736 {
10737 #ifndef __lock_lint
10738 _NOTE(ARGUNUSED(mpt))
10739 #endif
10740 pt->sgl_offset = offsetof(MPI2_SMP_PASSTHROUGH_REQUEST, SGL);
10741 if (pt->request_size != pt->sgl_offset)
10742 NDBG15(("mpi_pre_smp_passthrough(): Incorrect req size, "
10743 "0x%x, should be 0x%x, dataoutsz 0x%x",
10744 pt->request_size, pt->sgl_offset,
10745 pt->dataout_size));
10746 if (pt->data_size != sizeof (MPI2_SMP_PASSTHROUGH_REPLY))
10747 NDBG15(("mpi_pre_smp_passthrough(): Incorrect rep size, "
10748 "0x%x, should be 0x%x", pt->data_size,
10749 (int)sizeof (MPI2_SMP_PASSTHROUGH_REPLY)));
10750 }
10751
10752 /*
10753 * Prepare pt for a CONFIG request.
10754 */
10755 static void
10756 mpi_pre_config(mptsas_t *mpt, mptsas_pt_request_t *pt)
10757 {
10758 #ifndef __lock_lint
10759 _NOTE(ARGUNUSED(mpt))
10760 #endif
10761 pt->sgl_offset = offsetof(MPI2_CONFIG_REQUEST, PageBufferSGE);
10762 if (pt->request_size != pt->sgl_offset)
10763 NDBG15(("mpi_pre_config(): Incorrect req size, 0x%x, "
10764 "should be 0x%x, dataoutsz 0x%x", pt->request_size,
10765 pt->sgl_offset, pt->dataout_size));
10766 if (pt->data_size != sizeof (MPI2_CONFIG_REPLY))
10767 NDBG15(("mpi_pre_config(): Incorrect rep size, 0x%x, "
10768 "should be 0x%x", pt->data_size,
10769 (int)sizeof (MPI2_CONFIG_REPLY)));
10770 pt->simple = 1;
10771 }
10772
10773 /*
10774 * Prepare pt for a SCSI_IO_REQ request.
10775 */
10776 static void
10777 mpi_pre_scsi_io_req(mptsas_t *mpt, mptsas_pt_request_t *pt)
10778 {
10779 #ifndef __lock_lint
10780 _NOTE(ARGUNUSED(mpt))
10781 #endif
10782 pt->sgl_offset = offsetof(MPI2_SCSI_IO_REQUEST, SGL);
10783 if (pt->request_size != pt->sgl_offset)
10784 NDBG15(("mpi_pre_config(): Incorrect req size, 0x%x, "
10785 "should be 0x%x, dataoutsz 0x%x", pt->request_size,
10786 pt->sgl_offset,
10787 pt->dataout_size));
10788 if (pt->data_size != sizeof (MPI2_SCSI_IO_REPLY))
10789 NDBG15(("mpi_pre_config(): Incorrect rep size, 0x%x, "
10790 "should be 0x%x", pt->data_size,
10791 (int)sizeof (MPI2_SCSI_IO_REPLY)));
10792 }
10793
10794 /*
10795 * Prepare the mptsas_cmd for a SAS_IO_UNIT_CONTROL request.
10796 */
10797 static void
10798 mpi_pre_sas_io_unit_control(mptsas_t *mpt, mptsas_pt_request_t *pt)
10799 {
10800 #ifndef __lock_lint
10801 _NOTE(ARGUNUSED(mpt))
10802 #endif
10803 pt->sgl_offset = (uint16_t)pt->request_size;
10804 }
10805
10806 /*
10807 * A set of functions to prepare an mptsas_cmd for the various
10808 * supported requests.
10809 */
10810 static struct mptsas_func {
10811 U8 Function;
10812 char *Name;
10813 mptsas_pre_f *f_pre;
10814 } mptsas_func_list[] = {
10815 { MPI2_FUNCTION_IOC_FACTS, "IOC_FACTS", mpi_pre_ioc_facts },
10816 { MPI2_FUNCTION_PORT_FACTS, "PORT_FACTS", mpi_pre_port_facts },
10817 { MPI2_FUNCTION_FW_DOWNLOAD, "FW_DOWNLOAD", mpi_pre_fw_download },
10818 { MPI2_FUNCTION_FW_UPLOAD, "FW_UPLOAD", mpi_pre_fw_upload },
10819 { MPI2_FUNCTION_SATA_PASSTHROUGH, "SATA_PASSTHROUGH",
10820 mpi_pre_sata_passthrough },
10821 { MPI2_FUNCTION_SMP_PASSTHROUGH, "SMP_PASSTHROUGH",
10822 mpi_pre_smp_passthrough},
10823 { MPI2_FUNCTION_SCSI_IO_REQUEST, "SCSI_IO_REQUEST",
10824 mpi_pre_scsi_io_req},
10825 { MPI2_FUNCTION_CONFIG, "CONFIG", mpi_pre_config},
10826 { MPI2_FUNCTION_SAS_IO_UNIT_CONTROL, "SAS_IO_UNIT_CONTROL",
10827 mpi_pre_sas_io_unit_control },
10828 { 0xFF, NULL, NULL } /* list end */
10829 };
10830
10831 static void
10832 mptsas_prep_sgl_offset(mptsas_t *mpt, mptsas_pt_request_t *pt)
10833 {
10834 pMPI2RequestHeader_t hdr;
10835 struct mptsas_func *f;
10836
10837 hdr = (pMPI2RequestHeader_t)pt->request;
10838
10839 for (f = mptsas_func_list; f->f_pre != NULL; f++) {
10840 if (hdr->Function == f->Function) {
10841 f->f_pre(mpt, pt);
10842 NDBG15(("mptsas_prep_sgl_offset: Function %s,"
10843 " sgl_offset 0x%x", f->Name,
10844 pt->sgl_offset));
10845 return;
10846 }
10847 }
10848 NDBG15(("mptsas_prep_sgl_offset: Unknown Function 0x%02x,"
10849 " returning req_size 0x%x for sgl_offset",
10850 hdr->Function, pt->request_size));
10851 pt->sgl_offset = (uint16_t)pt->request_size;
10852 }
10853
10854
10855 static int
10856 mptsas_do_passthru(mptsas_t *mpt, uint8_t *request, uint8_t *reply,
10857 uint8_t *data, uint32_t request_size, uint32_t reply_size,
10858 uint32_t data_size, uint32_t direction, uint8_t *dataout,
10859 uint32_t dataout_size, short timeout, int mode)
10860 {
10861 mptsas_pt_request_t pt;
10862 mptsas_dma_alloc_state_t data_dma_state;
10863 mptsas_dma_alloc_state_t dataout_dma_state;
10864 caddr_t memp;
10865 mptsas_cmd_t *cmd = NULL;
10866 struct scsi_pkt *pkt;
10867 uint32_t reply_len = 0, sense_len = 0;
10868 pMPI2RequestHeader_t request_hdrp;
10869 pMPI2RequestHeader_t request_msg;
10870 pMPI2DefaultReply_t reply_msg;
10871 Mpi2SCSIIOReply_t rep_msg;
10872 int rvalue;
10873 int i, status = 0, pt_flags = 0, rv = 0;
10874 uint8_t function;
10875
10876 ASSERT(mutex_owned(&mpt->m_mutex));
10877
10878 reply_msg = (pMPI2DefaultReply_t)(&rep_msg);
10879 bzero(reply_msg, sizeof (MPI2_DEFAULT_REPLY));
10880 request_msg = kmem_zalloc(request_size, KM_SLEEP);
10881
10882 mutex_exit(&mpt->m_mutex);
10883 /*
10884 * copy in the request buffer since it could be used by
10885 * another thread when the pt request into waitq
10886 */
10887 if (ddi_copyin(request, request_msg, request_size, mode)) {
10888 mutex_enter(&mpt->m_mutex);
10889 status = EFAULT;
10890 mptsas_log(mpt, CE_WARN, "failed to copy request data");
10891 goto out;
10892 }
10893 NDBG27(("mptsas_do_passthru: mode 0x%x, size 0x%x, Func 0x%x",
10894 mode, request_size, request_msg->Function));
10895 mutex_enter(&mpt->m_mutex);
10896
10897 function = request_msg->Function;
10898 if (function == MPI2_FUNCTION_SCSI_TASK_MGMT) {
10899 pMpi2SCSITaskManagementRequest_t task;
10900 task = (pMpi2SCSITaskManagementRequest_t)request_msg;
10901 mptsas_setup_bus_reset_delay(mpt);
10902 rv = mptsas_ioc_task_management(mpt, task->TaskType,
10903 task->DevHandle, (int)task->LUN[1], reply, reply_size,
10904 mode);
10905
10906 if (rv != TRUE) {
10907 status = EIO;
10908 mptsas_log(mpt, CE_WARN, "task management failed");
10909 }
10910 goto out;
10911 }
10912
10913 if (data_size != 0) {
10914 data_dma_state.size = data_size;
10915 if (mptsas_dma_alloc(mpt, &data_dma_state) != DDI_SUCCESS) {
10916 status = ENOMEM;
10917 mptsas_log(mpt, CE_WARN, "failed to alloc DMA "
10918 "resource");
10919 goto out;
10920 }
10921 pt_flags |= MPTSAS_DATA_ALLOCATED;
10922 if (direction == MPTSAS_PASS_THRU_DIRECTION_WRITE) {
10923 mutex_exit(&mpt->m_mutex);
10924 for (i = 0; i < data_size; i++) {
10925 if (ddi_copyin(data + i, (uint8_t *)
10926 data_dma_state.memp + i, 1, mode)) {
10927 mutex_enter(&mpt->m_mutex);
10928 status = EFAULT;
10929 mptsas_log(mpt, CE_WARN, "failed to "
10930 "copy read data");
10931 goto out;
10932 }
10933 }
10934 mutex_enter(&mpt->m_mutex);
10935 }
10936 } else {
10937 bzero(&data_dma_state, sizeof (data_dma_state));
10938 }
10939
10940 if (dataout_size != 0) {
10941 dataout_dma_state.size = dataout_size;
10942 if (mptsas_dma_alloc(mpt, &dataout_dma_state) != DDI_SUCCESS) {
10943 status = ENOMEM;
10944 mptsas_log(mpt, CE_WARN, "failed to alloc DMA "
10945 "resource");
10946 goto out;
10947 }
10948 pt_flags |= MPTSAS_DATAOUT_ALLOCATED;
10949 mutex_exit(&mpt->m_mutex);
10950 for (i = 0; i < dataout_size; i++) {
10951 if (ddi_copyin(dataout + i, (uint8_t *)
10952 dataout_dma_state.memp + i, 1, mode)) {
10953 mutex_enter(&mpt->m_mutex);
10954 mptsas_log(mpt, CE_WARN, "failed to copy out"
10955 " data");
10956 status = EFAULT;
10957 goto out;
10958 }
10959 }
10960 mutex_enter(&mpt->m_mutex);
10961 } else {
10962 bzero(&dataout_dma_state, sizeof (dataout_dma_state));
10963 }
10964
10965 if ((rvalue = (mptsas_request_from_pool(mpt, &cmd, &pkt))) == -1) {
10966 status = EAGAIN;
10967 mptsas_log(mpt, CE_NOTE, "event ack command pool is full");
10968 goto out;
10969 }
10970 pt_flags |= MPTSAS_REQUEST_POOL_CMD;
10971
10972 bzero((caddr_t)cmd, sizeof (*cmd));
10973 bzero((caddr_t)pkt, scsi_pkt_size());
10974 bzero((caddr_t)&pt, sizeof (pt));
10975
10976 cmd->ioc_cmd_slot = (uint32_t)(rvalue);
10977
10978 pt.request = (uint8_t *)request_msg;
10979 pt.direction = direction;
10980 pt.simple = 0;
10981 pt.request_size = request_size;
10982 pt.data_size = data_size;
10983 pt.dataout_size = dataout_size;
10984 pt.data_cookie = data_dma_state.cookie;
10985 pt.dataout_cookie = dataout_dma_state.cookie;
10986 mptsas_prep_sgl_offset(mpt, &pt);
10987
10988 /*
10989 * Form a blank cmd/pkt to store the acknowledgement message
10990 */
10991 pkt->pkt_cdbp = (opaque_t)&cmd->cmd_cdb[0];
10992 pkt->pkt_scbp = (opaque_t)&cmd->cmd_scb;
10993 pkt->pkt_ha_private = (opaque_t)&pt;
10994 pkt->pkt_flags = FLAG_HEAD;
10995 pkt->pkt_time = timeout;
10996 cmd->cmd_pkt = pkt;
10997 cmd->cmd_flags = CFLAG_CMDIOC | CFLAG_PASSTHRU;
10998
10999 if ((function == MPI2_FUNCTION_SCSI_IO_REQUEST) ||
11000 (function == MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH)) {
11001 uint8_t com, cdb_group_id;
11002 boolean_t ret;
11003
11004 pkt->pkt_cdbp = ((pMpi2SCSIIORequest_t)request_msg)->CDB.CDB32;
11005 com = pkt->pkt_cdbp[0];
11006 cdb_group_id = CDB_GROUPID(com);
11007 switch (cdb_group_id) {
11008 case CDB_GROUPID_0: cmd->cmd_cdblen = CDB_GROUP0; break;
11009 case CDB_GROUPID_1: cmd->cmd_cdblen = CDB_GROUP1; break;
11010 case CDB_GROUPID_2: cmd->cmd_cdblen = CDB_GROUP2; break;
11011 case CDB_GROUPID_4: cmd->cmd_cdblen = CDB_GROUP4; break;
11012 case CDB_GROUPID_5: cmd->cmd_cdblen = CDB_GROUP5; break;
11013 default:
11014 NDBG27(("mptsas_do_passthru: SCSI_IO, reserved "
11015 "CDBGROUP 0x%x requested!", cdb_group_id));
11016 break;
11017 }
11018
11019 reply_len = sizeof (MPI2_SCSI_IO_REPLY);
11020 sense_len = reply_size - reply_len;
11021 ret = mptsas_cmdarqsize(mpt, cmd, sense_len, KM_SLEEP);
11022 VERIFY(ret == B_TRUE);
11023 } else {
11024 reply_len = reply_size;
11025 sense_len = 0;
11026 }
11027
11028 NDBG27(("mptsas_do_passthru: %s, dsz 0x%x, dosz 0x%x, replen 0x%x, "
11029 "snslen 0x%x",
11030 (direction == MPTSAS_PASS_THRU_DIRECTION_WRITE)?"Write":"Read",
11031 data_size, dataout_size, reply_len, sense_len));
11032
11033 /*
11034 * Save the command in a slot
11035 */
11036 if (mptsas_save_cmd(mpt, cmd) == TRUE) {
11037 /*
11038 * Once passthru command get slot, set cmd_flags
11039 * CFLAG_PREPARED.
11040 */
11041 cmd->cmd_flags |= CFLAG_PREPARED;
11042 mptsas_start_passthru(mpt, cmd);
11043 } else {
11044 mptsas_waitq_add(mpt, cmd);
11045 }
11046
11047 while ((cmd->cmd_flags & CFLAG_FINISHED) == 0) {
11048 cv_wait(&mpt->m_passthru_cv, &mpt->m_mutex);
11049 }
11050
11051 NDBG27(("mptsas_do_passthru: Cmd complete, flags 0x%x, rfm 0x%x "
11052 "pktreason 0x%x", cmd->cmd_flags, cmd->cmd_rfm,
11053 pkt->pkt_reason));
11054
11055 if (cmd->cmd_flags & CFLAG_PREPARED) {
11056 memp = mpt->m_req_frame + (mpt->m_req_frame_size *
11057 cmd->cmd_slot);
11058 request_hdrp = (pMPI2RequestHeader_t)memp;
11059 }
11060
11061 if (cmd->cmd_flags & CFLAG_TIMEOUT) {
11062 status = ETIMEDOUT;
11063 mptsas_log(mpt, CE_WARN, "passthrough command timeout");
11064 pt_flags |= MPTSAS_CMD_TIMEOUT;
11065 goto out;
11066 }
11067
11068 if (cmd->cmd_rfm) {
11069 /*
11070 * cmd_rfm is zero means the command reply is a CONTEXT
11071 * reply and no PCI Write to post the free reply SMFA
11072 * because no reply message frame is used.
11073 * cmd_rfm is non-zero means the reply is a ADDRESS
11074 * reply and reply message frame is used.
11075 */
11076 pt_flags |= MPTSAS_ADDRESS_REPLY;
11077 (void) ddi_dma_sync(mpt->m_dma_reply_frame_hdl, 0, 0,
11078 DDI_DMA_SYNC_FORCPU);
11079 reply_msg = (pMPI2DefaultReply_t)
11080 (mpt->m_reply_frame + (cmd->cmd_rfm -
11081 (mpt->m_reply_frame_dma_addr & 0xffffffffu)));
11082 }
11083
11084 mptsas_fma_check(mpt, cmd);
11085 if (pkt->pkt_reason == CMD_TRAN_ERR) {
11086 status = EAGAIN;
11087 mptsas_log(mpt, CE_WARN, "passthru fma error");
11088 goto out;
11089 }
11090 if (pkt->pkt_reason == CMD_RESET) {
11091 status = EAGAIN;
11092 mptsas_log(mpt, CE_WARN, "ioc reset abort passthru");
11093 goto out;
11094 }
11095
11096 if (pkt->pkt_reason == CMD_INCOMPLETE) {
11097 status = EIO;
11098 mptsas_log(mpt, CE_WARN, "passthrough command incomplete");
11099 goto out;
11100 }
11101
11102 mutex_exit(&mpt->m_mutex);
11103 if (cmd->cmd_flags & CFLAG_PREPARED) {
11104 function = request_hdrp->Function;
11105 if ((function == MPI2_FUNCTION_SCSI_IO_REQUEST) ||
11106 (function == MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH)) {
11107 reply_len = sizeof (MPI2_SCSI_IO_REPLY);
11108 sense_len = cmd->cmd_extrqslen ?
11109 min(sense_len, cmd->cmd_extrqslen) :
11110 min(sense_len, cmd->cmd_rqslen);
11111 } else {
11112 reply_len = reply_size;
11113 sense_len = 0;
11114 }
11115
11116 for (i = 0; i < reply_len; i++) {
11117 if (ddi_copyout((uint8_t *)reply_msg + i, reply + i, 1,
11118 mode)) {
11119 mutex_enter(&mpt->m_mutex);
11120 status = EFAULT;
11121 mptsas_log(mpt, CE_WARN, "failed to copy out "
11122 "reply data");
11123 goto out;
11124 }
11125 }
11126 for (i = 0; i < sense_len; i++) {
11127 if (ddi_copyout((uint8_t *)request_hdrp + 64 + i,
11128 reply + reply_len + i, 1, mode)) {
11129 mutex_enter(&mpt->m_mutex);
11130 status = EFAULT;
11131 mptsas_log(mpt, CE_WARN, "failed to copy out "
11132 "sense data");
11133 goto out;
11134 }
11135 }
11136 }
11137
11138 if (data_size) {
11139 if (direction != MPTSAS_PASS_THRU_DIRECTION_WRITE) {
11140 (void) ddi_dma_sync(data_dma_state.handle, 0, 0,
11141 DDI_DMA_SYNC_FORCPU);
11142 for (i = 0; i < data_size; i++) {
11143 if (ddi_copyout((uint8_t *)(
11144 data_dma_state.memp + i), data + i, 1,
11145 mode)) {
11146 mutex_enter(&mpt->m_mutex);
11147 status = EFAULT;
11148 mptsas_log(mpt, CE_WARN, "failed to "
11149 "copy out the reply data");
11150 goto out;
11151 }
11152 }
11153 }
11154 }
11155 mutex_enter(&mpt->m_mutex);
11156 out:
11157 /*
11158 * Put the reply frame back on the free queue, increment the free
11159 * index, and write the new index to the free index register. But only
11160 * if this reply is an ADDRESS reply.
11161 */
11162 if (pt_flags & MPTSAS_ADDRESS_REPLY) {
11163 ddi_put32(mpt->m_acc_free_queue_hdl,
11164 &((uint32_t *)(void *)mpt->m_free_queue)[mpt->m_free_index],
11165 cmd->cmd_rfm);
11166 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0,
11167 DDI_DMA_SYNC_FORDEV);
11168 if (++mpt->m_free_index == mpt->m_free_queue_depth) {
11169 mpt->m_free_index = 0;
11170 }
11171 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex,
11172 mpt->m_free_index);
11173 }
11174 if (cmd) {
11175 if (cmd->cmd_extrqslen != 0) {
11176 rmfree(mpt->m_erqsense_map, cmd->cmd_extrqschunks,
11177 cmd->cmd_extrqsidx + 1);
11178 }
11179 if (cmd->cmd_flags & CFLAG_PREPARED) {
11180 mptsas_remove_cmd(mpt, cmd);
11181 pt_flags &= (~MPTSAS_REQUEST_POOL_CMD);
11182 }
11183 }
11184 if (pt_flags & MPTSAS_REQUEST_POOL_CMD)
11185 mptsas_return_to_pool(mpt, cmd);
11186 if (pt_flags & MPTSAS_DATA_ALLOCATED) {
11187 if (mptsas_check_dma_handle(data_dma_state.handle) !=
11188 DDI_SUCCESS) {
11189 ddi_fm_service_impact(mpt->m_dip,
11190 DDI_SERVICE_UNAFFECTED);
11191 status = EFAULT;
11192 }
11193 mptsas_dma_free(&data_dma_state);
11194 }
11195 if (pt_flags & MPTSAS_DATAOUT_ALLOCATED) {
11196 if (mptsas_check_dma_handle(dataout_dma_state.handle) !=
11197 DDI_SUCCESS) {
11198 ddi_fm_service_impact(mpt->m_dip,
11199 DDI_SERVICE_UNAFFECTED);
11200 status = EFAULT;
11201 }
11202 mptsas_dma_free(&dataout_dma_state);
11203 }
11204 if (pt_flags & MPTSAS_CMD_TIMEOUT) {
11205 if ((mptsas_reset_handler(mpt)) == DDI_FAILURE) {
11206 mptsas_log(mpt, CE_WARN, "mptsas_reset_handler failed");
11207 }
11208 }
11209 if (request_msg)
11210 kmem_free(request_msg, request_size);
11211 NDBG27(("mptsas_do_passthru: Done status 0x%x", status));
11212
11213 return (status);
11214 }
11215
11216 static int
11217 mptsas_pass_thru(mptsas_t *mpt, mptsas_pass_thru_t *data, int mode)
11218 {
11219 /*
11220 * If timeout is 0, set timeout to default of 60 seconds.
11221 */
11222 if (data->Timeout == 0) {
11223 data->Timeout = MPTSAS_PASS_THRU_TIME_DEFAULT;
11224 }
11225
11226 if (((data->DataSize == 0) &&
11227 (data->DataDirection == MPTSAS_PASS_THRU_DIRECTION_NONE)) ||
11228 ((data->DataSize != 0) &&
11229 ((data->DataDirection == MPTSAS_PASS_THRU_DIRECTION_READ) ||
11230 (data->DataDirection == MPTSAS_PASS_THRU_DIRECTION_WRITE) ||
11231 ((data->DataDirection == MPTSAS_PASS_THRU_DIRECTION_BOTH) &&
11232 (data->DataOutSize != 0))))) {
11233 if (data->DataDirection == MPTSAS_PASS_THRU_DIRECTION_BOTH) {
11234 data->DataDirection = MPTSAS_PASS_THRU_DIRECTION_READ;
11235 } else {
11236 data->DataOutSize = 0;
11237 }
11238 /*
11239 * Send passthru request messages
11240 */
11241 return (mptsas_do_passthru(mpt,
11242 (uint8_t *)((uintptr_t)data->PtrRequest),
11243 (uint8_t *)((uintptr_t)data->PtrReply),
11244 (uint8_t *)((uintptr_t)data->PtrData),
11245 data->RequestSize, data->ReplySize,
11246 data->DataSize, data->DataDirection,
11247 (uint8_t *)((uintptr_t)data->PtrDataOut),
11248 data->DataOutSize, data->Timeout, mode));
11249 } else {
11250 return (EINVAL);
11251 }
11252 }
11253
11254 static uint8_t
11255 mptsas_get_fw_diag_buffer_number(mptsas_t *mpt, uint32_t unique_id)
11256 {
11257 uint8_t index;
11258
11259 for (index = 0; index < MPI2_DIAG_BUF_TYPE_COUNT; index++) {
11260 if (mpt->m_fw_diag_buffer_list[index].unique_id == unique_id) {
11261 return (index);
11262 }
11263 }
11264
11265 return (MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND);
11266 }
11267
11268 static void
11269 mptsas_start_diag(mptsas_t *mpt, mptsas_cmd_t *cmd)
11270 {
11271 pMpi2DiagBufferPostRequest_t pDiag_post_msg;
11272 pMpi2DiagReleaseRequest_t pDiag_release_msg;
11273 struct scsi_pkt *pkt = cmd->cmd_pkt;
11274 mptsas_diag_request_t *diag = pkt->pkt_ha_private;
11275 uint32_t i;
11276 uint64_t request_desc;
11277
11278 ASSERT(mutex_owned(&mpt->m_mutex));
11279
11280 /*
11281 * Form the diag message depending on the post or release function.
11282 */
11283 if (diag->function == MPI2_FUNCTION_DIAG_BUFFER_POST) {
11284 pDiag_post_msg = (pMpi2DiagBufferPostRequest_t)
11285 (mpt->m_req_frame + (mpt->m_req_frame_size *
11286 cmd->cmd_slot));
11287 bzero(pDiag_post_msg, mpt->m_req_frame_size);
11288 ddi_put8(mpt->m_acc_req_frame_hdl, &pDiag_post_msg->Function,
11289 diag->function);
11290 ddi_put8(mpt->m_acc_req_frame_hdl, &pDiag_post_msg->BufferType,
11291 diag->pBuffer->buffer_type);
11292 ddi_put8(mpt->m_acc_req_frame_hdl,
11293 &pDiag_post_msg->ExtendedType,
11294 diag->pBuffer->extended_type);
11295 ddi_put32(mpt->m_acc_req_frame_hdl,
11296 &pDiag_post_msg->BufferLength,
11297 diag->pBuffer->buffer_data.size);
11298 for (i = 0; i < (sizeof (pDiag_post_msg->ProductSpecific) / 4);
11299 i++) {
11300 ddi_put32(mpt->m_acc_req_frame_hdl,
11301 &pDiag_post_msg->ProductSpecific[i],
11302 diag->pBuffer->product_specific[i]);
11303 }
11304 ddi_put32(mpt->m_acc_req_frame_hdl,
11305 &pDiag_post_msg->BufferAddress.Low,
11306 (uint32_t)(diag->pBuffer->buffer_data.cookie.dmac_laddress
11307 & 0xffffffffull));
11308 ddi_put32(mpt->m_acc_req_frame_hdl,
11309 &pDiag_post_msg->BufferAddress.High,
11310 (uint32_t)(diag->pBuffer->buffer_data.cookie.dmac_laddress
11311 >> 32));
11312 } else {
11313 pDiag_release_msg = (pMpi2DiagReleaseRequest_t)
11314 (mpt->m_req_frame + (mpt->m_req_frame_size *
11315 cmd->cmd_slot));
11316 bzero(pDiag_release_msg, mpt->m_req_frame_size);
11317 ddi_put8(mpt->m_acc_req_frame_hdl,
11318 &pDiag_release_msg->Function, diag->function);
11319 ddi_put8(mpt->m_acc_req_frame_hdl,
11320 &pDiag_release_msg->BufferType,
11321 diag->pBuffer->buffer_type);
11322 }
11323
11324 /*
11325 * Send the message
11326 */
11327 (void) ddi_dma_sync(mpt->m_dma_req_frame_hdl, 0, 0,
11328 DDI_DMA_SYNC_FORDEV);
11329 request_desc = (cmd->cmd_slot << 16) +
11330 MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE;
11331 cmd->cmd_rfm = NULL;
11332 MPTSAS_START_CMD(mpt, request_desc);
11333 if ((mptsas_check_dma_handle(mpt->m_dma_req_frame_hdl) !=
11334 DDI_SUCCESS) ||
11335 (mptsas_check_acc_handle(mpt->m_acc_req_frame_hdl) !=
11336 DDI_SUCCESS)) {
11337 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
11338 }
11339 }
11340
11341 static int
11342 mptsas_post_fw_diag_buffer(mptsas_t *mpt,
11343 mptsas_fw_diagnostic_buffer_t *pBuffer, uint32_t *return_code)
11344 {
11345 mptsas_diag_request_t diag;
11346 int status, slot_num, post_flags = 0;
11347 mptsas_cmd_t *cmd = NULL;
11348 struct scsi_pkt *pkt;
11349 pMpi2DiagBufferPostReply_t reply;
11350 uint16_t iocstatus;
11351 uint32_t iocloginfo, transfer_length;
11352
11353 /*
11354 * If buffer is not enabled, just leave.
11355 */
11356 *return_code = MPTSAS_FW_DIAG_ERROR_POST_FAILED;
11357 if (!pBuffer->enabled) {
11358 status = DDI_FAILURE;
11359 goto out;
11360 }
11361
11362 /*
11363 * Clear some flags initially.
11364 */
11365 pBuffer->force_release = FALSE;
11366 pBuffer->valid_data = FALSE;
11367 pBuffer->owned_by_firmware = FALSE;
11368
11369 /*
11370 * Get a cmd buffer from the cmd buffer pool
11371 */
11372 if ((slot_num = (mptsas_request_from_pool(mpt, &cmd, &pkt))) == -1) {
11373 status = DDI_FAILURE;
11374 mptsas_log(mpt, CE_NOTE, "command pool is full: Post FW Diag");
11375 goto out;
11376 }
11377 post_flags |= MPTSAS_REQUEST_POOL_CMD;
11378
11379 bzero((caddr_t)cmd, sizeof (*cmd));
11380 bzero((caddr_t)pkt, scsi_pkt_size());
11381
11382 cmd->ioc_cmd_slot = (uint32_t)(slot_num);
11383
11384 diag.pBuffer = pBuffer;
11385 diag.function = MPI2_FUNCTION_DIAG_BUFFER_POST;
11386
11387 /*
11388 * Form a blank cmd/pkt to store the acknowledgement message
11389 */
11390 pkt->pkt_ha_private = (opaque_t)&diag;
11391 pkt->pkt_flags = FLAG_HEAD;
11392 pkt->pkt_time = 60;
11393 cmd->cmd_pkt = pkt;
11394 cmd->cmd_flags = CFLAG_CMDIOC | CFLAG_FW_DIAG;
11395
11396 /*
11397 * Save the command in a slot
11398 */
11399 if (mptsas_save_cmd(mpt, cmd) == TRUE) {
11400 /*
11401 * Once passthru command get slot, set cmd_flags
11402 * CFLAG_PREPARED.
11403 */
11404 cmd->cmd_flags |= CFLAG_PREPARED;
11405 mptsas_start_diag(mpt, cmd);
11406 } else {
11407 mptsas_waitq_add(mpt, cmd);
11408 }
11409
11410 while ((cmd->cmd_flags & CFLAG_FINISHED) == 0) {
11411 cv_wait(&mpt->m_fw_diag_cv, &mpt->m_mutex);
11412 }
11413
11414 if (cmd->cmd_flags & CFLAG_TIMEOUT) {
11415 status = DDI_FAILURE;
11416 mptsas_log(mpt, CE_WARN, "Post FW Diag command timeout");
11417 goto out;
11418 }
11419
11420 /*
11421 * cmd_rfm points to the reply message if a reply was given. Check the
11422 * IOCStatus to make sure everything went OK with the FW diag request
11423 * and set buffer flags.
11424 */
11425 if (cmd->cmd_rfm) {
11426 post_flags |= MPTSAS_ADDRESS_REPLY;
11427 (void) ddi_dma_sync(mpt->m_dma_reply_frame_hdl, 0, 0,
11428 DDI_DMA_SYNC_FORCPU);
11429 reply = (pMpi2DiagBufferPostReply_t)(mpt->m_reply_frame +
11430 (cmd->cmd_rfm -
11431 (mpt->m_reply_frame_dma_addr & 0xffffffffu)));
11432
11433 /*
11434 * Get the reply message data
11435 */
11436 iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl,
11437 &reply->IOCStatus);
11438 iocloginfo = ddi_get32(mpt->m_acc_reply_frame_hdl,
11439 &reply->IOCLogInfo);
11440 transfer_length = ddi_get32(mpt->m_acc_reply_frame_hdl,
11441 &reply->TransferLength);
11442
11443 /*
11444 * If post failed quit.
11445 */
11446 if (iocstatus != MPI2_IOCSTATUS_SUCCESS) {
11447 status = DDI_FAILURE;
11448 NDBG13(("post FW Diag Buffer failed: IOCStatus=0x%x, "
11449 "IOCLogInfo=0x%x, TransferLength=0x%x", iocstatus,
11450 iocloginfo, transfer_length));
11451 goto out;
11452 }
11453
11454 /*
11455 * Post was successful.
11456 */
11457 pBuffer->valid_data = TRUE;
11458 pBuffer->owned_by_firmware = TRUE;
11459 *return_code = MPTSAS_FW_DIAG_ERROR_SUCCESS;
11460 status = DDI_SUCCESS;
11461 }
11462
11463 out:
11464 /*
11465 * Put the reply frame back on the free queue, increment the free
11466 * index, and write the new index to the free index register. But only
11467 * if this reply is an ADDRESS reply.
11468 */
11469 if (post_flags & MPTSAS_ADDRESS_REPLY) {
11470 ddi_put32(mpt->m_acc_free_queue_hdl,
11471 &((uint32_t *)(void *)mpt->m_free_queue)[mpt->m_free_index],
11472 cmd->cmd_rfm);
11473 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0,
11474 DDI_DMA_SYNC_FORDEV);
11475 if (++mpt->m_free_index == mpt->m_free_queue_depth) {
11476 mpt->m_free_index = 0;
11477 }
11478 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex,
11479 mpt->m_free_index);
11480 }
11481 if (cmd && (cmd->cmd_flags & CFLAG_PREPARED)) {
11482 mptsas_remove_cmd(mpt, cmd);
11483 post_flags &= (~MPTSAS_REQUEST_POOL_CMD);
11484 }
11485 if (post_flags & MPTSAS_REQUEST_POOL_CMD) {
11486 mptsas_return_to_pool(mpt, cmd);
11487 }
11488
11489 return (status);
11490 }
11491
11492 static int
11493 mptsas_release_fw_diag_buffer(mptsas_t *mpt,
11494 mptsas_fw_diagnostic_buffer_t *pBuffer, uint32_t *return_code,
11495 uint32_t diag_type)
11496 {
11497 mptsas_diag_request_t diag;
11498 int status, slot_num, rel_flags = 0;
11499 mptsas_cmd_t *cmd = NULL;
11500 struct scsi_pkt *pkt;
11501 pMpi2DiagReleaseReply_t reply;
11502 uint16_t iocstatus;
11503 uint32_t iocloginfo;
11504
11505 /*
11506 * If buffer is not enabled, just leave.
11507 */
11508 *return_code = MPTSAS_FW_DIAG_ERROR_RELEASE_FAILED;
11509 if (!pBuffer->enabled) {
11510 mptsas_log(mpt, CE_NOTE, "This buffer type is not supported "
11511 "by the IOC");
11512 status = DDI_FAILURE;
11513 goto out;
11514 }
11515
11516 /*
11517 * Clear some flags initially.
11518 */
11519 pBuffer->force_release = FALSE;
11520 pBuffer->valid_data = FALSE;
11521 pBuffer->owned_by_firmware = FALSE;
11522
11523 /*
11524 * Get a cmd buffer from the cmd buffer pool
11525 */
11526 if ((slot_num = (mptsas_request_from_pool(mpt, &cmd, &pkt))) == -1) {
11527 status = DDI_FAILURE;
11528 mptsas_log(mpt, CE_NOTE, "command pool is full: Release FW "
11529 "Diag");
11530 goto out;
11531 }
11532 rel_flags |= MPTSAS_REQUEST_POOL_CMD;
11533
11534 bzero((caddr_t)cmd, sizeof (*cmd));
11535 bzero((caddr_t)pkt, scsi_pkt_size());
11536
11537 cmd->ioc_cmd_slot = (uint32_t)(slot_num);
11538
11539 diag.pBuffer = pBuffer;
11540 diag.function = MPI2_FUNCTION_DIAG_RELEASE;
11541
11542 /*
11543 * Form a blank cmd/pkt to store the acknowledgement message
11544 */
11545 pkt->pkt_ha_private = (opaque_t)&diag;
11546 pkt->pkt_flags = FLAG_HEAD;
11547 pkt->pkt_time = 60;
11548 cmd->cmd_pkt = pkt;
11549 cmd->cmd_flags = CFLAG_CMDIOC | CFLAG_FW_DIAG;
11550
11551 /*
11552 * Save the command in a slot
11553 */
11554 if (mptsas_save_cmd(mpt, cmd) == TRUE) {
11555 /*
11556 * Once passthru command get slot, set cmd_flags
11557 * CFLAG_PREPARED.
11558 */
11559 cmd->cmd_flags |= CFLAG_PREPARED;
11560 mptsas_start_diag(mpt, cmd);
11561 } else {
11562 mptsas_waitq_add(mpt, cmd);
11563 }
11564
11565 while ((cmd->cmd_flags & CFLAG_FINISHED) == 0) {
11566 cv_wait(&mpt->m_fw_diag_cv, &mpt->m_mutex);
11567 }
11568
11569 if (cmd->cmd_flags & CFLAG_TIMEOUT) {
11570 status = DDI_FAILURE;
11571 mptsas_log(mpt, CE_WARN, "Release FW Diag command timeout");
11572 goto out;
11573 }
11574
11575 /*
11576 * cmd_rfm points to the reply message if a reply was given. Check the
11577 * IOCStatus to make sure everything went OK with the FW diag request
11578 * and set buffer flags.
11579 */
11580 if (cmd->cmd_rfm) {
11581 rel_flags |= MPTSAS_ADDRESS_REPLY;
11582 (void) ddi_dma_sync(mpt->m_dma_reply_frame_hdl, 0, 0,
11583 DDI_DMA_SYNC_FORCPU);
11584 reply = (pMpi2DiagReleaseReply_t)(mpt->m_reply_frame +
11585 (cmd->cmd_rfm -
11586 (mpt->m_reply_frame_dma_addr & 0xffffffffu)));
11587
11588 /*
11589 * Get the reply message data
11590 */
11591 iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl,
11592 &reply->IOCStatus);
11593 iocloginfo = ddi_get32(mpt->m_acc_reply_frame_hdl,
11594 &reply->IOCLogInfo);
11595
11596 /*
11597 * If release failed quit.
11598 */
11599 if ((iocstatus != MPI2_IOCSTATUS_SUCCESS) ||
11600 pBuffer->owned_by_firmware) {
11601 status = DDI_FAILURE;
11602 NDBG13(("release FW Diag Buffer failed: "
11603 "IOCStatus=0x%x, IOCLogInfo=0x%x", iocstatus,
11604 iocloginfo));
11605 goto out;
11606 }
11607
11608 /*
11609 * Release was successful.
11610 */
11611 *return_code = MPTSAS_FW_DIAG_ERROR_SUCCESS;
11612 status = DDI_SUCCESS;
11613
11614 /*
11615 * If this was for an UNREGISTER diag type command, clear the
11616 * unique ID.
11617 */
11618 if (diag_type == MPTSAS_FW_DIAG_TYPE_UNREGISTER) {
11619 pBuffer->unique_id = MPTSAS_FW_DIAG_INVALID_UID;
11620 }
11621 }
11622
11623 out:
11624 /*
11625 * Put the reply frame back on the free queue, increment the free
11626 * index, and write the new index to the free index register. But only
11627 * if this reply is an ADDRESS reply.
11628 */
11629 if (rel_flags & MPTSAS_ADDRESS_REPLY) {
11630 ddi_put32(mpt->m_acc_free_queue_hdl,
11631 &((uint32_t *)(void *)mpt->m_free_queue)[mpt->m_free_index],
11632 cmd->cmd_rfm);
11633 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0,
11634 DDI_DMA_SYNC_FORDEV);
11635 if (++mpt->m_free_index == mpt->m_free_queue_depth) {
11636 mpt->m_free_index = 0;
11637 }
11638 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex,
11639 mpt->m_free_index);
11640 }
11641 if (cmd && (cmd->cmd_flags & CFLAG_PREPARED)) {
11642 mptsas_remove_cmd(mpt, cmd);
11643 rel_flags &= (~MPTSAS_REQUEST_POOL_CMD);
11644 }
11645 if (rel_flags & MPTSAS_REQUEST_POOL_CMD) {
11646 mptsas_return_to_pool(mpt, cmd);
11647 }
11648
11649 return (status);
11650 }
11651
11652 static int
11653 mptsas_diag_register(mptsas_t *mpt, mptsas_fw_diag_register_t *diag_register,
11654 uint32_t *return_code)
11655 {
11656 mptsas_fw_diagnostic_buffer_t *pBuffer;
11657 uint8_t extended_type, buffer_type, i;
11658 uint32_t buffer_size;
11659 uint32_t unique_id;
11660 int status;
11661
11662 ASSERT(mutex_owned(&mpt->m_mutex));
11663
11664 extended_type = diag_register->ExtendedType;
11665 buffer_type = diag_register->BufferType;
11666 buffer_size = diag_register->RequestedBufferSize;
11667 unique_id = diag_register->UniqueId;
11668
11669 /*
11670 * Check for valid buffer type
11671 */
11672 if (buffer_type >= MPI2_DIAG_BUF_TYPE_COUNT) {
11673 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER;
11674 return (DDI_FAILURE);
11675 }
11676
11677 /*
11678 * Get the current buffer and look up the unique ID. The unique ID
11679 * should not be found. If it is, the ID is already in use.
11680 */
11681 i = mptsas_get_fw_diag_buffer_number(mpt, unique_id);
11682 pBuffer = &mpt->m_fw_diag_buffer_list[buffer_type];
11683 if (i != MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND) {
11684 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID;
11685 return (DDI_FAILURE);
11686 }
11687
11688 /*
11689 * The buffer's unique ID should not be registered yet, and the given
11690 * unique ID cannot be 0.
11691 */
11692 if ((pBuffer->unique_id != MPTSAS_FW_DIAG_INVALID_UID) ||
11693 (unique_id == MPTSAS_FW_DIAG_INVALID_UID)) {
11694 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID;
11695 return (DDI_FAILURE);
11696 }
11697
11698 /*
11699 * If this buffer is already posted as immediate, just change owner.
11700 */
11701 if (pBuffer->immediate && pBuffer->owned_by_firmware &&
11702 (pBuffer->unique_id == MPTSAS_FW_DIAG_INVALID_UID)) {
11703 pBuffer->immediate = FALSE;
11704 pBuffer->unique_id = unique_id;
11705 return (DDI_SUCCESS);
11706 }
11707
11708 /*
11709 * Post a new buffer after checking if it's enabled. The DMA buffer
11710 * that is allocated will be contiguous (sgl_len = 1).
11711 */
11712 if (!pBuffer->enabled) {
11713 *return_code = MPTSAS_FW_DIAG_ERROR_NO_BUFFER;
11714 return (DDI_FAILURE);
11715 }
11716 bzero(&pBuffer->buffer_data, sizeof (mptsas_dma_alloc_state_t));
11717 pBuffer->buffer_data.size = buffer_size;
11718 if (mptsas_dma_alloc(mpt, &pBuffer->buffer_data) != DDI_SUCCESS) {
11719 mptsas_log(mpt, CE_WARN, "failed to alloc DMA resource for "
11720 "diag buffer: size = %d bytes", buffer_size);
11721 *return_code = MPTSAS_FW_DIAG_ERROR_NO_BUFFER;
11722 return (DDI_FAILURE);
11723 }
11724
11725 /*
11726 * Copy the given info to the diag buffer and post the buffer.
11727 */
11728 pBuffer->buffer_type = buffer_type;
11729 pBuffer->immediate = FALSE;
11730 if (buffer_type == MPI2_DIAG_BUF_TYPE_TRACE) {
11731 for (i = 0; i < (sizeof (pBuffer->product_specific) / 4);
11732 i++) {
11733 pBuffer->product_specific[i] =
11734 diag_register->ProductSpecific[i];
11735 }
11736 }
11737 pBuffer->extended_type = extended_type;
11738 pBuffer->unique_id = unique_id;
11739 status = mptsas_post_fw_diag_buffer(mpt, pBuffer, return_code);
11740
11741 if (mptsas_check_dma_handle(pBuffer->buffer_data.handle) !=
11742 DDI_SUCCESS) {
11743 mptsas_log(mpt, CE_WARN, "Check of DMA handle failed in "
11744 "mptsas_diag_register.");
11745 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
11746 status = DDI_FAILURE;
11747 }
11748
11749 /*
11750 * In case there was a failure, free the DMA buffer.
11751 */
11752 if (status == DDI_FAILURE) {
11753 mptsas_dma_free(&pBuffer->buffer_data);
11754 }
11755
11756 return (status);
11757 }
11758
11759 static int
11760 mptsas_diag_unregister(mptsas_t *mpt,
11761 mptsas_fw_diag_unregister_t *diag_unregister, uint32_t *return_code)
11762 {
11763 mptsas_fw_diagnostic_buffer_t *pBuffer;
11764 uint8_t i;
11765 uint32_t unique_id;
11766 int status;
11767
11768 ASSERT(mutex_owned(&mpt->m_mutex));
11769
11770 unique_id = diag_unregister->UniqueId;
11771
11772 /*
11773 * Get the current buffer and look up the unique ID. The unique ID
11774 * should be there.
11775 */
11776 i = mptsas_get_fw_diag_buffer_number(mpt, unique_id);
11777 if (i == MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND) {
11778 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID;
11779 return (DDI_FAILURE);
11780 }
11781
11782 pBuffer = &mpt->m_fw_diag_buffer_list[i];
11783
11784 /*
11785 * Try to release the buffer from FW before freeing it. If release
11786 * fails, don't free the DMA buffer in case FW tries to access it
11787 * later. If buffer is not owned by firmware, can't release it.
11788 */
11789 if (!pBuffer->owned_by_firmware) {
11790 status = DDI_SUCCESS;
11791 } else {
11792 status = mptsas_release_fw_diag_buffer(mpt, pBuffer,
11793 return_code, MPTSAS_FW_DIAG_TYPE_UNREGISTER);
11794 }
11795
11796 /*
11797 * At this point, return the current status no matter what happens with
11798 * the DMA buffer.
11799 */
11800 pBuffer->unique_id = MPTSAS_FW_DIAG_INVALID_UID;
11801 if (status == DDI_SUCCESS) {
11802 if (mptsas_check_dma_handle(pBuffer->buffer_data.handle) !=
11803 DDI_SUCCESS) {
11804 mptsas_log(mpt, CE_WARN, "Check of DMA handle failed "
11805 "in mptsas_diag_unregister.");
11806 ddi_fm_service_impact(mpt->m_dip,
11807 DDI_SERVICE_UNAFFECTED);
11808 }
11809 mptsas_dma_free(&pBuffer->buffer_data);
11810 }
11811
11812 return (status);
11813 }
11814
11815 static int
11816 mptsas_diag_query(mptsas_t *mpt, mptsas_fw_diag_query_t *diag_query,
11817 uint32_t *return_code)
11818 {
11819 mptsas_fw_diagnostic_buffer_t *pBuffer;
11820 uint8_t i;
11821 uint32_t unique_id;
11822
11823 ASSERT(mutex_owned(&mpt->m_mutex));
11824
11825 unique_id = diag_query->UniqueId;
11826
11827 /*
11828 * If ID is valid, query on ID.
11829 * If ID is invalid, query on buffer type.
11830 */
11831 if (unique_id == MPTSAS_FW_DIAG_INVALID_UID) {
11832 i = diag_query->BufferType;
11833 if (i >= MPI2_DIAG_BUF_TYPE_COUNT) {
11834 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID;
11835 return (DDI_FAILURE);
11836 }
11837 } else {
11838 i = mptsas_get_fw_diag_buffer_number(mpt, unique_id);
11839 if (i == MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND) {
11840 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID;
11841 return (DDI_FAILURE);
11842 }
11843 }
11844
11845 /*
11846 * Fill query structure with the diag buffer info.
11847 */
11848 pBuffer = &mpt->m_fw_diag_buffer_list[i];
11849 diag_query->BufferType = pBuffer->buffer_type;
11850 diag_query->ExtendedType = pBuffer->extended_type;
11851 if (diag_query->BufferType == MPI2_DIAG_BUF_TYPE_TRACE) {
11852 for (i = 0; i < (sizeof (diag_query->ProductSpecific) / 4);
11853 i++) {
11854 diag_query->ProductSpecific[i] =
11855 pBuffer->product_specific[i];
11856 }
11857 }
11858 diag_query->TotalBufferSize = pBuffer->buffer_data.size;
11859 diag_query->DriverAddedBufferSize = 0;
11860 diag_query->UniqueId = pBuffer->unique_id;
11861 diag_query->ApplicationFlags = 0;
11862 diag_query->DiagnosticFlags = 0;
11863
11864 /*
11865 * Set/Clear application flags
11866 */
11867 if (pBuffer->immediate) {
11868 diag_query->ApplicationFlags &= ~MPTSAS_FW_DIAG_FLAG_APP_OWNED;
11869 } else {
11870 diag_query->ApplicationFlags |= MPTSAS_FW_DIAG_FLAG_APP_OWNED;
11871 }
11872 if (pBuffer->valid_data || pBuffer->owned_by_firmware) {
11873 diag_query->ApplicationFlags |=
11874 MPTSAS_FW_DIAG_FLAG_BUFFER_VALID;
11875 } else {
11876 diag_query->ApplicationFlags &=
11877 ~MPTSAS_FW_DIAG_FLAG_BUFFER_VALID;
11878 }
11879 if (pBuffer->owned_by_firmware) {
11880 diag_query->ApplicationFlags |=
11881 MPTSAS_FW_DIAG_FLAG_FW_BUFFER_ACCESS;
11882 } else {
11883 diag_query->ApplicationFlags &=
11884 ~MPTSAS_FW_DIAG_FLAG_FW_BUFFER_ACCESS;
11885 }
11886
11887 return (DDI_SUCCESS);
11888 }
11889
11890 static int
11891 mptsas_diag_read_buffer(mptsas_t *mpt,
11892 mptsas_diag_read_buffer_t *diag_read_buffer, uint8_t *ioctl_buf,
11893 uint32_t *return_code, int ioctl_mode)
11894 {
11895 mptsas_fw_diagnostic_buffer_t *pBuffer;
11896 uint8_t i, *pData;
11897 uint32_t unique_id, byte;
11898 int status;
11899
11900 ASSERT(mutex_owned(&mpt->m_mutex));
11901
11902 unique_id = diag_read_buffer->UniqueId;
11903
11904 /*
11905 * Get the current buffer and look up the unique ID. The unique ID
11906 * should be there.
11907 */
11908 i = mptsas_get_fw_diag_buffer_number(mpt, unique_id);
11909 if (i == MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND) {
11910 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID;
11911 return (DDI_FAILURE);
11912 }
11913
11914 pBuffer = &mpt->m_fw_diag_buffer_list[i];
11915
11916 /*
11917 * Make sure requested read is within limits
11918 */
11919 if (diag_read_buffer->StartingOffset + diag_read_buffer->BytesToRead >
11920 pBuffer->buffer_data.size) {
11921 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER;
11922 return (DDI_FAILURE);
11923 }
11924
11925 /*
11926 * Copy the requested data from DMA to the diag_read_buffer. The DMA
11927 * buffer that was allocated is one contiguous buffer.
11928 */
11929 pData = (uint8_t *)(pBuffer->buffer_data.memp +
11930 diag_read_buffer->StartingOffset);
11931 (void) ddi_dma_sync(pBuffer->buffer_data.handle, 0, 0,
11932 DDI_DMA_SYNC_FORCPU);
11933 for (byte = 0; byte < diag_read_buffer->BytesToRead; byte++) {
11934 if (ddi_copyout(pData + byte, ioctl_buf + byte, 1, ioctl_mode)
11935 != 0) {
11936 return (DDI_FAILURE);
11937 }
11938 }
11939 diag_read_buffer->Status = 0;
11940
11941 /*
11942 * Set or clear the Force Release flag.
11943 */
11944 if (pBuffer->force_release) {
11945 diag_read_buffer->Flags |= MPTSAS_FW_DIAG_FLAG_FORCE_RELEASE;
11946 } else {
11947 diag_read_buffer->Flags &= ~MPTSAS_FW_DIAG_FLAG_FORCE_RELEASE;
11948 }
11949
11950 /*
11951 * If buffer is to be reregistered, make sure it's not already owned by
11952 * firmware first.
11953 */
11954 status = DDI_SUCCESS;
11955 if (!pBuffer->owned_by_firmware) {
11956 if (diag_read_buffer->Flags & MPTSAS_FW_DIAG_FLAG_REREGISTER) {
11957 status = mptsas_post_fw_diag_buffer(mpt, pBuffer,
11958 return_code);
11959 }
11960 }
11961
11962 return (status);
11963 }
11964
11965 static int
11966 mptsas_diag_release(mptsas_t *mpt, mptsas_fw_diag_release_t *diag_release,
11967 uint32_t *return_code)
11968 {
11969 mptsas_fw_diagnostic_buffer_t *pBuffer;
11970 uint8_t i;
11971 uint32_t unique_id;
11972 int status;
11973
11974 ASSERT(mutex_owned(&mpt->m_mutex));
11975
11976 unique_id = diag_release->UniqueId;
11977
11978 /*
11979 * Get the current buffer and look up the unique ID. The unique ID
11980 * should be there.
11981 */
11982 i = mptsas_get_fw_diag_buffer_number(mpt, unique_id);
11983 if (i == MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND) {
11984 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID;
11985 return (DDI_FAILURE);
11986 }
11987
11988 pBuffer = &mpt->m_fw_diag_buffer_list[i];
11989
11990 /*
11991 * If buffer is not owned by firmware, it's already been released.
11992 */
11993 if (!pBuffer->owned_by_firmware) {
11994 *return_code = MPTSAS_FW_DIAG_ERROR_ALREADY_RELEASED;
11995 return (DDI_FAILURE);
11996 }
11997
11998 /*
11999 * Release the buffer.
12000 */
12001 status = mptsas_release_fw_diag_buffer(mpt, pBuffer, return_code,
12002 MPTSAS_FW_DIAG_TYPE_RELEASE);
12003 return (status);
12004 }
12005
12006 static int
12007 mptsas_do_diag_action(mptsas_t *mpt, uint32_t action, uint8_t *diag_action,
12008 uint32_t length, uint32_t *return_code, int ioctl_mode)
12009 {
12010 mptsas_fw_diag_register_t diag_register;
12011 mptsas_fw_diag_unregister_t diag_unregister;
12012 mptsas_fw_diag_query_t diag_query;
12013 mptsas_diag_read_buffer_t diag_read_buffer;
12014 mptsas_fw_diag_release_t diag_release;
12015 int status = DDI_SUCCESS;
12016 uint32_t original_return_code, read_buf_len;
12017
12018 ASSERT(mutex_owned(&mpt->m_mutex));
12019
12020 original_return_code = *return_code;
12021 *return_code = MPTSAS_FW_DIAG_ERROR_SUCCESS;
12022
12023 switch (action) {
12024 case MPTSAS_FW_DIAG_TYPE_REGISTER:
12025 if (!length) {
12026 *return_code =
12027 MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER;
12028 status = DDI_FAILURE;
12029 break;
12030 }
12031 if (ddi_copyin(diag_action, &diag_register,
12032 sizeof (diag_register), ioctl_mode) != 0) {
12033 return (DDI_FAILURE);
12034 }
12035 status = mptsas_diag_register(mpt, &diag_register,
12036 return_code);
12037 break;
12038
12039 case MPTSAS_FW_DIAG_TYPE_UNREGISTER:
12040 if (length < sizeof (diag_unregister)) {
12041 *return_code =
12042 MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER;
12043 status = DDI_FAILURE;
12044 break;
12045 }
12046 if (ddi_copyin(diag_action, &diag_unregister,
12047 sizeof (diag_unregister), ioctl_mode) != 0) {
12048 return (DDI_FAILURE);
12049 }
12050 status = mptsas_diag_unregister(mpt, &diag_unregister,
12051 return_code);
12052 break;
12053
12054 case MPTSAS_FW_DIAG_TYPE_QUERY:
12055 if (length < sizeof (diag_query)) {
12056 *return_code =
12057 MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER;
12058 status = DDI_FAILURE;
12059 break;
12060 }
12061 if (ddi_copyin(diag_action, &diag_query,
12062 sizeof (diag_query), ioctl_mode) != 0) {
12063 return (DDI_FAILURE);
12064 }
12065 status = mptsas_diag_query(mpt, &diag_query,
12066 return_code);
12067 if (status == DDI_SUCCESS) {
12068 if (ddi_copyout(&diag_query, diag_action,
12069 sizeof (diag_query), ioctl_mode) != 0) {
12070 return (DDI_FAILURE);
12071 }
12072 }
12073 break;
12074
12075 case MPTSAS_FW_DIAG_TYPE_READ_BUFFER:
12076 if (ddi_copyin(diag_action, &diag_read_buffer,
12077 sizeof (diag_read_buffer) - 4, ioctl_mode) != 0) {
12078 return (DDI_FAILURE);
12079 }
12080 read_buf_len = sizeof (diag_read_buffer) -
12081 sizeof (diag_read_buffer.DataBuffer) +
12082 diag_read_buffer.BytesToRead;
12083 if (length < read_buf_len) {
12084 *return_code =
12085 MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER;
12086 status = DDI_FAILURE;
12087 break;
12088 }
12089 status = mptsas_diag_read_buffer(mpt,
12090 &diag_read_buffer, diag_action +
12091 sizeof (diag_read_buffer) - 4, return_code,
12092 ioctl_mode);
12093 if (status == DDI_SUCCESS) {
12094 if (ddi_copyout(&diag_read_buffer, diag_action,
12095 sizeof (diag_read_buffer) - 4, ioctl_mode)
12096 != 0) {
12097 return (DDI_FAILURE);
12098 }
12099 }
12100 break;
12101
12102 case MPTSAS_FW_DIAG_TYPE_RELEASE:
12103 if (length < sizeof (diag_release)) {
12104 *return_code =
12105 MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER;
12106 status = DDI_FAILURE;
12107 break;
12108 }
12109 if (ddi_copyin(diag_action, &diag_release,
12110 sizeof (diag_release), ioctl_mode) != 0) {
12111 return (DDI_FAILURE);
12112 }
12113 status = mptsas_diag_release(mpt, &diag_release,
12114 return_code);
12115 break;
12116
12117 default:
12118 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER;
12119 status = DDI_FAILURE;
12120 break;
12121 }
12122
12123 if ((status == DDI_FAILURE) &&
12124 (original_return_code == MPTSAS_FW_DIAG_NEW) &&
12125 (*return_code != MPTSAS_FW_DIAG_ERROR_SUCCESS)) {
12126 status = DDI_SUCCESS;
12127 }
12128
12129 return (status);
12130 }
12131
12132 static int
12133 mptsas_diag_action(mptsas_t *mpt, mptsas_diag_action_t *user_data, int mode)
12134 {
12135 int status;
12136 mptsas_diag_action_t driver_data;
12137
12138 ASSERT(mutex_owned(&mpt->m_mutex));
12139
12140 /*
12141 * Copy the user data to a driver data buffer.
12142 */
12143 if (ddi_copyin(user_data, &driver_data, sizeof (mptsas_diag_action_t),
12144 mode) == 0) {
12145 /*
12146 * Send diag action request if Action is valid
12147 */
12148 if (driver_data.Action == MPTSAS_FW_DIAG_TYPE_REGISTER ||
12149 driver_data.Action == MPTSAS_FW_DIAG_TYPE_UNREGISTER ||
12150 driver_data.Action == MPTSAS_FW_DIAG_TYPE_QUERY ||
12151 driver_data.Action == MPTSAS_FW_DIAG_TYPE_READ_BUFFER ||
12152 driver_data.Action == MPTSAS_FW_DIAG_TYPE_RELEASE) {
12153 status = mptsas_do_diag_action(mpt, driver_data.Action,
12154 (void *)(uintptr_t)driver_data.PtrDiagAction,
12155 driver_data.Length, &driver_data.ReturnCode,
12156 mode);
12157 if (status == DDI_SUCCESS) {
12158 if (ddi_copyout(&driver_data.ReturnCode,
12159 &user_data->ReturnCode,
12160 sizeof (user_data->ReturnCode), mode)
12161 != 0) {
12162 status = EFAULT;
12163 } else {
12164 status = 0;
12165 }
12166 } else {
12167 status = EIO;
12168 }
12169 } else {
12170 status = EINVAL;
12171 }
12172 } else {
12173 status = EFAULT;
12174 }
12175
12176 return (status);
12177 }
12178
12179 /*
12180 * This routine handles the "event query" ioctl.
12181 */
12182 static int
12183 mptsas_event_query(mptsas_t *mpt, mptsas_event_query_t *data, int mode,
12184 int *rval)
12185 {
12186 int status;
12187 mptsas_event_query_t driverdata;
12188 uint8_t i;
12189
12190 driverdata.Entries = MPTSAS_EVENT_QUEUE_SIZE;
12191
12192 mutex_enter(&mpt->m_mutex);
12193 for (i = 0; i < 4; i++) {
12194 driverdata.Types[i] = mpt->m_event_mask[i];
12195 }
12196 mutex_exit(&mpt->m_mutex);
12197
12198 if (ddi_copyout(&driverdata, data, sizeof (driverdata), mode) != 0) {
12199 status = EFAULT;
12200 } else {
12201 *rval = MPTIOCTL_STATUS_GOOD;
12202 status = 0;
12203 }
12204
12205 return (status);
12206 }
12207
12208 /*
12209 * This routine handles the "event enable" ioctl.
12210 */
12211 static int
12212 mptsas_event_enable(mptsas_t *mpt, mptsas_event_enable_t *data, int mode,
12213 int *rval)
12214 {
12215 int status;
12216 mptsas_event_enable_t driverdata;
12217 uint8_t i;
12218
12219 if (ddi_copyin(data, &driverdata, sizeof (driverdata), mode) == 0) {
12220 mutex_enter(&mpt->m_mutex);
12221 for (i = 0; i < 4; i++) {
12222 mpt->m_event_mask[i] = driverdata.Types[i];
12223 }
12224 mutex_exit(&mpt->m_mutex);
12225
12226 *rval = MPTIOCTL_STATUS_GOOD;
12227 status = 0;
12228 } else {
12229 status = EFAULT;
12230 }
12231 return (status);
12232 }
12233
12234 /*
12235 * This routine handles the "event report" ioctl.
12236 */
12237 static int
12238 mptsas_event_report(mptsas_t *mpt, mptsas_event_report_t *data, int mode,
12239 int *rval)
12240 {
12241 int status;
12242 mptsas_event_report_t driverdata;
12243
12244 mutex_enter(&mpt->m_mutex);
12245
12246 if (ddi_copyin(&data->Size, &driverdata.Size, sizeof (driverdata.Size),
12247 mode) == 0) {
12248 if (driverdata.Size >= sizeof (mpt->m_events)) {
12249 if (ddi_copyout(mpt->m_events, data->Events,
12250 sizeof (mpt->m_events), mode) != 0) {
12251 status = EFAULT;
12252 } else {
12253 if (driverdata.Size > sizeof (mpt->m_events)) {
12254 driverdata.Size =
12255 sizeof (mpt->m_events);
12256 if (ddi_copyout(&driverdata.Size,
12257 &data->Size,
12258 sizeof (driverdata.Size),
12259 mode) != 0) {
12260 status = EFAULT;
12261 } else {
12262 *rval = MPTIOCTL_STATUS_GOOD;
12263 status = 0;
12264 }
12265 } else {
12266 *rval = MPTIOCTL_STATUS_GOOD;
12267 status = 0;
12268 }
12269 }
12270 } else {
12271 *rval = MPTIOCTL_STATUS_LEN_TOO_SHORT;
12272 status = 0;
12273 }
12274 } else {
12275 status = EFAULT;
12276 }
12277
12278 mutex_exit(&mpt->m_mutex);
12279 return (status);
12280 }
12281
12282 static void
12283 mptsas_lookup_pci_data(mptsas_t *mpt, mptsas_adapter_data_t *adapter_data)
12284 {
12285 int *reg_data;
12286 uint_t reglen;
12287
12288 /*
12289 * Lookup the 'reg' property and extract the other data
12290 */
12291 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, mpt->m_dip,
12292 DDI_PROP_DONTPASS, "reg", ®_data, ®len) ==
12293 DDI_PROP_SUCCESS) {
12294 /*
12295 * Extract the PCI data from the 'reg' property first DWORD.
12296 * The entry looks like the following:
12297 * First DWORD:
12298 * Bits 0 - 7 8-bit Register number
12299 * Bits 8 - 10 3-bit Function number
12300 * Bits 11 - 15 5-bit Device number
12301 * Bits 16 - 23 8-bit Bus number
12302 * Bits 24 - 25 2-bit Address Space type identifier
12303 *
12304 */
12305 adapter_data->PciInformation.u.bits.BusNumber =
12306 (reg_data[0] & 0x00FF0000) >> 16;
12307 adapter_data->PciInformation.u.bits.DeviceNumber =
12308 (reg_data[0] & 0x0000F800) >> 11;
12309 adapter_data->PciInformation.u.bits.FunctionNumber =
12310 (reg_data[0] & 0x00000700) >> 8;
12311 ddi_prop_free((void *)reg_data);
12312 } else {
12313 /*
12314 * If we can't determine the PCI data then we fill in FF's for
12315 * the data to indicate this.
12316 */
12317 adapter_data->PCIDeviceHwId = 0xFFFFFFFF;
12318 adapter_data->MpiPortNumber = 0xFFFFFFFF;
12319 adapter_data->PciInformation.u.AsDWORD = 0xFFFFFFFF;
12320 }
12321
12322 /*
12323 * Saved in the mpt->m_fwversion
12324 */
12325 adapter_data->MpiFirmwareVersion = mpt->m_fwversion;
12326 }
12327
12328 static void
12329 mptsas_read_adapter_data(mptsas_t *mpt, mptsas_adapter_data_t *adapter_data)
12330 {
12331 char *driver_verstr = MPTSAS_MOD_STRING;
12332
12333 mptsas_lookup_pci_data(mpt, adapter_data);
12334 adapter_data->AdapterType = mpt->m_MPI25 ?
12335 MPTIOCTL_ADAPTER_TYPE_SAS3 :
12336 MPTIOCTL_ADAPTER_TYPE_SAS2;
12337 adapter_data->PCIDeviceHwId = (uint32_t)mpt->m_devid;
12338 adapter_data->PCIDeviceHwRev = (uint32_t)mpt->m_revid;
12339 adapter_data->SubSystemId = (uint32_t)mpt->m_ssid;
12340 adapter_data->SubsystemVendorId = (uint32_t)mpt->m_svid;
12341 (void) strcpy((char *)&adapter_data->DriverVersion[0], driver_verstr);
12342 adapter_data->BiosVersion = 0;
12343 (void) mptsas_get_bios_page3(mpt, &adapter_data->BiosVersion);
12344 }
12345
12346 static void
12347 mptsas_read_pci_info(mptsas_t *mpt, mptsas_pci_info_t *pci_info)
12348 {
12349 int *reg_data, i;
12350 uint_t reglen;
12351
12352 /*
12353 * Lookup the 'reg' property and extract the other data
12354 */
12355 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, mpt->m_dip,
12356 DDI_PROP_DONTPASS, "reg", ®_data, ®len) ==
12357 DDI_PROP_SUCCESS) {
12358 /*
12359 * Extract the PCI data from the 'reg' property first DWORD.
12360 * The entry looks like the following:
12361 * First DWORD:
12362 * Bits 8 - 10 3-bit Function number
12363 * Bits 11 - 15 5-bit Device number
12364 * Bits 16 - 23 8-bit Bus number
12365 */
12366 pci_info->BusNumber = (reg_data[0] & 0x00FF0000) >> 16;
12367 pci_info->DeviceNumber = (reg_data[0] & 0x0000F800) >> 11;
12368 pci_info->FunctionNumber = (reg_data[0] & 0x00000700) >> 8;
12369 ddi_prop_free((void *)reg_data);
12370 } else {
12371 /*
12372 * If we can't determine the PCI info then we fill in FF's for
12373 * the data to indicate this.
12374 */
12375 pci_info->BusNumber = 0xFFFFFFFF;
12376 pci_info->DeviceNumber = 0xFF;
12377 pci_info->FunctionNumber = 0xFF;
12378 }
12379
12380 /*
12381 * Now get the interrupt vector and the pci header. The vector can
12382 * only be 0 right now. The header is the first 256 bytes of config
12383 * space.
12384 */
12385 pci_info->InterruptVector = 0;
12386 for (i = 0; i < sizeof (pci_info->PciHeader); i++) {
12387 pci_info->PciHeader[i] = pci_config_get8(mpt->m_config_handle,
12388 i);
12389 }
12390 }
12391
12392 static int
12393 mptsas_reg_access(mptsas_t *mpt, mptsas_reg_access_t *data, int mode)
12394 {
12395 int status = 0;
12396 mptsas_reg_access_t driverdata;
12397
12398 mutex_enter(&mpt->m_mutex);
12399 if (ddi_copyin(data, &driverdata, sizeof (driverdata), mode) == 0) {
12400 switch (driverdata.Command) {
12401 /*
12402 * IO access is not supported.
12403 */
12404 case REG_IO_READ:
12405 case REG_IO_WRITE:
12406 mptsas_log(mpt, CE_WARN, "IO access is not "
12407 "supported. Use memory access.");
12408 status = EINVAL;
12409 break;
12410
12411 case REG_MEM_READ:
12412 driverdata.RegData = ddi_get32(mpt->m_datap,
12413 (uint32_t *)(void *)mpt->m_reg +
12414 driverdata.RegOffset);
12415 if (ddi_copyout(&driverdata.RegData,
12416 &data->RegData,
12417 sizeof (driverdata.RegData), mode) != 0) {
12418 mptsas_log(mpt, CE_WARN, "Register "
12419 "Read Failed");
12420 status = EFAULT;
12421 }
12422 break;
12423
12424 case REG_MEM_WRITE:
12425 ddi_put32(mpt->m_datap,
12426 (uint32_t *)(void *)mpt->m_reg +
12427 driverdata.RegOffset,
12428 driverdata.RegData);
12429 break;
12430
12431 default:
12432 status = EINVAL;
12433 break;
12434 }
12435 } else {
12436 status = EFAULT;
12437 }
12438
12439 mutex_exit(&mpt->m_mutex);
12440 return (status);
12441 }
12442
12443 static int
12444 led_control(mptsas_t *mpt, intptr_t data, int mode)
12445 {
12446 int ret = 0;
12447 mptsas_led_control_t lc;
12448 mptsas_target_t *ptgt;
12449
12450 if (ddi_copyin((void *)data, &lc, sizeof (lc), mode) != 0) {
12451 return (EFAULT);
12452 }
12453
12454 if ((lc.Command != MPTSAS_LEDCTL_FLAG_SET &&
12455 lc.Command != MPTSAS_LEDCTL_FLAG_GET) ||
12456 lc.Led < MPTSAS_LEDCTL_LED_MIN ||
12457 lc.Led > MPTSAS_LEDCTL_LED_MAX ||
12458 (lc.Command == MPTSAS_LEDCTL_FLAG_SET && lc.LedStatus != 0 &&
12459 lc.LedStatus != 1)) {
12460 return (EINVAL);
12461 }
12462
12463 if ((lc.Command == MPTSAS_LEDCTL_FLAG_SET && (mode & FWRITE) == 0) ||
12464 (lc.Command == MPTSAS_LEDCTL_FLAG_GET && (mode & FREAD) == 0))
12465 return (EACCES);
12466
12467 /* Locate the target we're interrogating... */
12468 mutex_enter(&mpt->m_mutex);
12469 ptgt = refhash_linear_search(mpt->m_targets,
12470 mptsas_target_eval_slot, &lc);
12471 if (ptgt == NULL) {
12472 /* We could not find a target for that enclosure/slot. */
12473 mutex_exit(&mpt->m_mutex);
12474 return (ENOENT);
12475 }
12476
12477 if (lc.Command == MPTSAS_LEDCTL_FLAG_SET) {
12478 /* Update our internal LED state. */
12479 ptgt->m_led_status &= ~(1 << (lc.Led - 1));
12480 ptgt->m_led_status |= lc.LedStatus << (lc.Led - 1);
12481
12482 /* Flush it to the controller. */
12483 ret = mptsas_flush_led_status(mpt, ptgt);
12484 mutex_exit(&mpt->m_mutex);
12485 return (ret);
12486 }
12487
12488 /* Return our internal LED state. */
12489 lc.LedStatus = (ptgt->m_led_status >> (lc.Led - 1)) & 1;
12490 mutex_exit(&mpt->m_mutex);
12491
12492 if (ddi_copyout(&lc, (void *)data, sizeof (lc), mode) != 0) {
12493 return (EFAULT);
12494 }
12495
12496 return (0);
12497 }
12498
12499 static int
12500 get_disk_info(mptsas_t *mpt, intptr_t data, int mode)
12501 {
12502 uint16_t i = 0;
12503 uint16_t count = 0;
12504 int ret = 0;
12505 mptsas_target_t *ptgt;
12506 mptsas_disk_info_t *di;
12507 STRUCT_DECL(mptsas_get_disk_info, gdi);
12508
12509 if ((mode & FREAD) == 0)
12510 return (EACCES);
12511
12512 STRUCT_INIT(gdi, get_udatamodel());
12513
12514 if (ddi_copyin((void *)data, STRUCT_BUF(gdi), STRUCT_SIZE(gdi),
12515 mode) != 0) {
12516 return (EFAULT);
12517 }
12518
12519 /* Find out how many targets there are. */
12520 mutex_enter(&mpt->m_mutex);
12521 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL;
12522 ptgt = refhash_next(mpt->m_targets, ptgt)) {
12523 count++;
12524 }
12525 mutex_exit(&mpt->m_mutex);
12526
12527 /*
12528 * If we haven't been asked to copy out information on each target,
12529 * then just return the count.
12530 */
12531 STRUCT_FSET(gdi, DiskCount, count);
12532 if (STRUCT_FGETP(gdi, PtrDiskInfoArray) == NULL)
12533 goto copy_out;
12534
12535 /*
12536 * If we haven't been given a large enough buffer to copy out into,
12537 * let the caller know.
12538 */
12539 if (STRUCT_FGET(gdi, DiskInfoArraySize) <
12540 count * sizeof (mptsas_disk_info_t)) {
12541 ret = ENOSPC;
12542 goto copy_out;
12543 }
12544
12545 di = kmem_zalloc(count * sizeof (mptsas_disk_info_t), KM_SLEEP);
12546
12547 mutex_enter(&mpt->m_mutex);
12548 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL;
12549 ptgt = refhash_next(mpt->m_targets, ptgt)) {
12550 if (i >= count) {
12551 /*
12552 * The number of targets changed while we weren't
12553 * looking, so give up.
12554 */
12555 refhash_rele(mpt->m_targets, ptgt);
12556 mutex_exit(&mpt->m_mutex);
12557 kmem_free(di, count * sizeof (mptsas_disk_info_t));
12558 return (EAGAIN);
12559 }
12560 di[i].Instance = mpt->m_instance;
12561 di[i].Enclosure = ptgt->m_enclosure;
12562 di[i].Slot = ptgt->m_slot_num;
12563 di[i].SasAddress = ptgt->m_addr.mta_wwn;
12564 i++;
12565 }
12566 mutex_exit(&mpt->m_mutex);
12567 STRUCT_FSET(gdi, DiskCount, i);
12568
12569 /* Copy out the disk information to the caller. */
12570 if (ddi_copyout((void *)di, STRUCT_FGETP(gdi, PtrDiskInfoArray),
12571 i * sizeof (mptsas_disk_info_t), mode) != 0) {
12572 ret = EFAULT;
12573 }
12574
12575 kmem_free(di, count * sizeof (mptsas_disk_info_t));
12576
12577 copy_out:
12578 if (ddi_copyout(STRUCT_BUF(gdi), (void *)data, STRUCT_SIZE(gdi),
12579 mode) != 0) {
12580 ret = EFAULT;
12581 }
12582
12583 return (ret);
12584 }
12585
12586 static int
12587 mptsas_ioctl(dev_t dev, int cmd, intptr_t data, int mode, cred_t *credp,
12588 int *rval)
12589 {
12590 int status = 0;
12591 mptsas_t *mpt;
12592 mptsas_update_flash_t flashdata;
12593 mptsas_pass_thru_t passthru_data;
12594 mptsas_adapter_data_t adapter_data;
12595 mptsas_pci_info_t pci_info;
12596 int copylen;
12597
12598 int iport_flag = 0;
12599 dev_info_t *dip = NULL;
12600 mptsas_phymask_t phymask = 0;
12601 struct devctl_iocdata *dcp = NULL;
12602 char *addr = NULL;
12603 mptsas_target_t *ptgt = NULL;
12604
12605 *rval = MPTIOCTL_STATUS_GOOD;
12606 if (secpolicy_sys_config(credp, B_FALSE) != 0) {
12607 return (EPERM);
12608 }
12609
12610 mpt = ddi_get_soft_state(mptsas_state, MINOR2INST(getminor(dev)));
12611 if (mpt == NULL) {
12612 /*
12613 * Called from iport node, get the states
12614 */
12615 iport_flag = 1;
12616 dip = mptsas_get_dip_from_dev(dev, &phymask);
12617 if (dip == NULL) {
12618 return (ENXIO);
12619 }
12620 mpt = DIP2MPT(dip);
12621 }
12622 /* Make sure power level is D0 before accessing registers */
12623 mutex_enter(&mpt->m_mutex);
12624 if (mpt->m_options & MPTSAS_OPT_PM) {
12625 (void) pm_busy_component(mpt->m_dip, 0);
12626 if (mpt->m_power_level != PM_LEVEL_D0) {
12627 mutex_exit(&mpt->m_mutex);
12628 if (pm_raise_power(mpt->m_dip, 0, PM_LEVEL_D0) !=
12629 DDI_SUCCESS) {
12630 mptsas_log(mpt, CE_WARN,
12631 "mptsas%d: mptsas_ioctl: Raise power "
12632 "request failed.", mpt->m_instance);
12633 (void) pm_idle_component(mpt->m_dip, 0);
12634 return (ENXIO);
12635 }
12636 } else {
12637 mutex_exit(&mpt->m_mutex);
12638 }
12639 } else {
12640 mutex_exit(&mpt->m_mutex);
12641 }
12642
12643 if (iport_flag) {
12644 status = scsi_hba_ioctl(dev, cmd, data, mode, credp, rval);
12645 if (status != 0) {
12646 goto out;
12647 }
12648 /*
12649 * The following code control the OK2RM LED, it doesn't affect
12650 * the ioctl return status.
12651 */
12652 if ((cmd == DEVCTL_DEVICE_ONLINE) ||
12653 (cmd == DEVCTL_DEVICE_OFFLINE)) {
12654 if (ndi_dc_allochdl((void *)data, &dcp) !=
12655 NDI_SUCCESS) {
12656 goto out;
12657 }
12658 addr = ndi_dc_getaddr(dcp);
12659 ptgt = mptsas_addr_to_ptgt(mpt, addr, phymask);
12660 if (ptgt == NULL) {
12661 NDBG14(("mptsas_ioctl led control: tgt %s not "
12662 "found", addr));
12663 ndi_dc_freehdl(dcp);
12664 goto out;
12665 }
12666 mutex_enter(&mpt->m_mutex);
12667 if (cmd == DEVCTL_DEVICE_ONLINE) {
12668 ptgt->m_tgt_unconfigured = 0;
12669 } else if (cmd == DEVCTL_DEVICE_OFFLINE) {
12670 ptgt->m_tgt_unconfigured = 1;
12671 }
12672 if (cmd == DEVCTL_DEVICE_OFFLINE) {
12673 ptgt->m_led_status |=
12674 (1 << (MPTSAS_LEDCTL_LED_OK2RM - 1));
12675 } else {
12676 ptgt->m_led_status &=
12677 ~(1 << (MPTSAS_LEDCTL_LED_OK2RM - 1));
12678 }
12679 (void) mptsas_flush_led_status(mpt, ptgt);
12680 mutex_exit(&mpt->m_mutex);
12681 ndi_dc_freehdl(dcp);
12682 }
12683 goto out;
12684 }
12685 switch (cmd) {
12686 case MPTIOCTL_GET_DISK_INFO:
12687 status = get_disk_info(mpt, data, mode);
12688 break;
12689 case MPTIOCTL_LED_CONTROL:
12690 status = led_control(mpt, data, mode);
12691 break;
12692 case MPTIOCTL_UPDATE_FLASH:
12693 if (ddi_copyin((void *)data, &flashdata,
12694 sizeof (struct mptsas_update_flash), mode)) {
12695 status = EFAULT;
12696 break;
12697 }
12698
12699 mutex_enter(&mpt->m_mutex);
12700 if (mptsas_update_flash(mpt,
12701 (caddr_t)(long)flashdata.PtrBuffer,
12702 flashdata.ImageSize, flashdata.ImageType, mode)) {
12703 status = EFAULT;
12704 }
12705
12706 /*
12707 * Reset the chip to start using the new
12708 * firmware. Reset if failed also.
12709 */
12710 mpt->m_softstate &= ~MPTSAS_SS_MSG_UNIT_RESET;
12711 if (mptsas_reset_handler(mpt) == DDI_FAILURE) {
12712 status = EFAULT;
12713 }
12714 mutex_exit(&mpt->m_mutex);
12715 break;
12716 case MPTIOCTL_PASS_THRU:
12717 /*
12718 * The user has requested to pass through a command to
12719 * be executed by the MPT firmware. Call our routine
12720 * which does this. Only allow one passthru IOCTL at
12721 * one time. Other threads will block on
12722 * m_passthru_mutex, which is of adaptive variant.
12723 */
12724 if (ddi_copyin((void *)data, &passthru_data,
12725 sizeof (mptsas_pass_thru_t), mode)) {
12726 status = EFAULT;
12727 break;
12728 }
12729 mutex_enter(&mpt->m_passthru_mutex);
12730 mutex_enter(&mpt->m_mutex);
12731 status = mptsas_pass_thru(mpt, &passthru_data, mode);
12732 mutex_exit(&mpt->m_mutex);
12733 mutex_exit(&mpt->m_passthru_mutex);
12734
12735 break;
12736 case MPTIOCTL_GET_ADAPTER_DATA:
12737 /*
12738 * The user has requested to read adapter data. Call
12739 * our routine which does this.
12740 */
12741 bzero(&adapter_data, sizeof (mptsas_adapter_data_t));
12742 if (ddi_copyin((void *)data, (void *)&adapter_data,
12743 sizeof (mptsas_adapter_data_t), mode)) {
12744 status = EFAULT;
12745 break;
12746 }
12747 if (adapter_data.StructureLength >=
12748 sizeof (mptsas_adapter_data_t)) {
12749 adapter_data.StructureLength = (uint32_t)
12750 sizeof (mptsas_adapter_data_t);
12751 copylen = sizeof (mptsas_adapter_data_t);
12752 mutex_enter(&mpt->m_mutex);
12753 mptsas_read_adapter_data(mpt, &adapter_data);
12754 mutex_exit(&mpt->m_mutex);
12755 } else {
12756 adapter_data.StructureLength = (uint32_t)
12757 sizeof (mptsas_adapter_data_t);
12758 copylen = sizeof (adapter_data.StructureLength);
12759 *rval = MPTIOCTL_STATUS_LEN_TOO_SHORT;
12760 }
12761 if (ddi_copyout((void *)(&adapter_data), (void *)data,
12762 copylen, mode) != 0) {
12763 status = EFAULT;
12764 }
12765 break;
12766 case MPTIOCTL_GET_PCI_INFO:
12767 /*
12768 * The user has requested to read pci info. Call
12769 * our routine which does this.
12770 */
12771 bzero(&pci_info, sizeof (mptsas_pci_info_t));
12772 mutex_enter(&mpt->m_mutex);
12773 mptsas_read_pci_info(mpt, &pci_info);
12774 mutex_exit(&mpt->m_mutex);
12775 if (ddi_copyout((void *)(&pci_info), (void *)data,
12776 sizeof (mptsas_pci_info_t), mode) != 0) {
12777 status = EFAULT;
12778 }
12779 break;
12780 case MPTIOCTL_RESET_ADAPTER:
12781 mutex_enter(&mpt->m_mutex);
12782 mpt->m_softstate &= ~MPTSAS_SS_MSG_UNIT_RESET;
12783 if ((mptsas_reset_handler(mpt)) == DDI_FAILURE) {
12784 mptsas_log(mpt, CE_WARN, "reset adapter IOCTL "
12785 "failed");
12786 status = EFAULT;
12787 }
12788 mutex_exit(&mpt->m_mutex);
12789 break;
12790 case MPTIOCTL_DIAG_ACTION:
12791 /*
12792 * The user has done a diag buffer action. Call our
12793 * routine which does this. Only allow one diag action
12794 * at one time.
12795 */
12796 mutex_enter(&mpt->m_mutex);
12797 if (mpt->m_diag_action_in_progress) {
12798 mutex_exit(&mpt->m_mutex);
12799 return (EBUSY);
12800 }
12801 mpt->m_diag_action_in_progress = 1;
12802 status = mptsas_diag_action(mpt,
12803 (mptsas_diag_action_t *)data, mode);
12804 mpt->m_diag_action_in_progress = 0;
12805 mutex_exit(&mpt->m_mutex);
12806 break;
12807 case MPTIOCTL_EVENT_QUERY:
12808 /*
12809 * The user has done an event query. Call our routine
12810 * which does this.
12811 */
12812 status = mptsas_event_query(mpt,
12813 (mptsas_event_query_t *)data, mode, rval);
12814 break;
12815 case MPTIOCTL_EVENT_ENABLE:
12816 /*
12817 * The user has done an event enable. Call our routine
12818 * which does this.
12819 */
12820 status = mptsas_event_enable(mpt,
12821 (mptsas_event_enable_t *)data, mode, rval);
12822 break;
12823 case MPTIOCTL_EVENT_REPORT:
12824 /*
12825 * The user has done an event report. Call our routine
12826 * which does this.
12827 */
12828 status = mptsas_event_report(mpt,
12829 (mptsas_event_report_t *)data, mode, rval);
12830 break;
12831 case MPTIOCTL_REG_ACCESS:
12832 /*
12833 * The user has requested register access. Call our
12834 * routine which does this.
12835 */
12836 status = mptsas_reg_access(mpt,
12837 (mptsas_reg_access_t *)data, mode);
12838 break;
12839 default:
12840 status = scsi_hba_ioctl(dev, cmd, data, mode, credp,
12841 rval);
12842 break;
12843 }
12844
12845 out:
12846 return (status);
12847 }
12848
12849 int
12850 mptsas_reset_handler(mptsas_t *mpt)
12851 {
12852 int rval = DDI_SUCCESS;
12853 mptsas_target_t *ptgt = NULL;
12854
12855 ASSERT(mutex_owned(&mpt->m_mutex));
12856
12857 /*
12858 * Set a flag telling task management we are processing a reset. This
12859 * is needed because after the reset is complete, the hash table still
12860 * needs to be rebuilt. If I/Os are started before the hash table is
12861 * rebuilt, I/O errors will occur. This flag allows I/Os to be marked
12862 * so that they can be retried.
12863 */
12864 mutex_enter(&mpt->m_taskmgmt_mutex);
12865 if (mpt->m_in_reset == TRUE) {
12866 mutex_exit(&mpt->m_taskmgmt_mutex);
12867 return (DDI_FAILURE);
12868 }
12869 mpt->m_in_reset = TRUE;
12870 mutex_exit(&mpt->m_taskmgmt_mutex);
12871
12872 /*
12873 * Wait until all the allocated sense data buffers for DMA are freed.
12874 */
12875 while (mpt->m_extreq_sense_refcount > 0)
12876 cv_wait(&mpt->m_extreq_sense_refcount_cv, &mpt->m_mutex);
12877
12878 /*
12879 * Set all throttles to HOLD
12880 */
12881 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL;
12882 ptgt = refhash_next(mpt->m_targets, ptgt)) {
12883 mptsas_set_throttle(mpt, ptgt, HOLD_THROTTLE);
12884 }
12885
12886 /*
12887 * Disable interrupts
12888 */
12889 MPTSAS_DISABLE_INTR(mpt);
12890
12891 /*
12892 * Abort all commands: outstanding commands, commands in waitq and
12893 * tx_waitq.
12894 */
12895 mptsas_flush_hba(mpt);
12896
12897 /*
12898 * Reinitialize the chip.
12899 */
12900 if (mptsas_init_chip(mpt, FALSE) == DDI_FAILURE) {
12901 rval = DDI_FAILURE;
12902 }
12903
12904 /*
12905 * Enable interrupts again
12906 */
12907 MPTSAS_ENABLE_INTR(mpt);
12908
12909 /*
12910 * If mptsas_init_chip was successful, update the driver data.
12911 */
12912 if (rval == DDI_SUCCESS) {
12913 mptsas_update_driver_data(mpt);
12914 }
12915
12916 /*
12917 * Reset the throttles
12918 */
12919 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL;
12920 ptgt = refhash_next(mpt->m_targets, ptgt)) {
12921 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE);
12922 }
12923
12924 mptsas_doneq_empty(mpt);
12925 mptsas_restart_hba(mpt);
12926
12927 if (rval != DDI_SUCCESS) {
12928 mptsas_fm_ereport(mpt, DDI_FM_DEVICE_NO_RESPONSE);
12929 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_LOST);
12930 }
12931
12932 /*
12933 * Clear the reset flag so that I/Os can continue.
12934 */
12935 mutex_enter(&mpt->m_taskmgmt_mutex);
12936 mpt->m_in_reset = FALSE;
12937 mutex_exit(&mpt->m_taskmgmt_mutex);
12938
12939 return (rval);
12940 }
12941
12942 static int
12943 mptsas_init_chip(mptsas_t *mpt, int first_time)
12944 {
12945 ddi_dma_cookie_t cookie;
12946 uint32_t i;
12947 int rval;
12948
12949 /*
12950 * Check to see if the firmware image is valid
12951 */
12952 if (ddi_get32(mpt->m_datap, &mpt->m_reg->HostDiagnostic) &
12953 MPI2_DIAG_FLASH_BAD_SIG) {
12954 mptsas_log(mpt, CE_WARN, "mptsas bad flash signature!");
12955 goto fail;
12956 }
12957
12958 /*
12959 * Reset the chip
12960 */
12961 rval = mptsas_ioc_reset(mpt, first_time);
12962 if (rval == MPTSAS_RESET_FAIL) {
12963 mptsas_log(mpt, CE_WARN, "hard reset failed!");
12964 goto fail;
12965 }
12966
12967 if ((rval == MPTSAS_SUCCESS_MUR) && (!first_time)) {
12968 goto mur;
12969 }
12970 /*
12971 * Setup configuration space
12972 */
12973 if (mptsas_config_space_init(mpt) == FALSE) {
12974 mptsas_log(mpt, CE_WARN, "mptsas_config_space_init "
12975 "failed!");
12976 goto fail;
12977 }
12978
12979 /*
12980 * IOC facts can change after a diag reset so all buffers that are
12981 * based on these numbers must be de-allocated and re-allocated. Get
12982 * new IOC facts each time chip is initialized.
12983 */
12984 if (mptsas_ioc_get_facts(mpt) == DDI_FAILURE) {
12985 mptsas_log(mpt, CE_WARN, "mptsas_ioc_get_facts failed");
12986 goto fail;
12987 }
12988
12989 if (mptsas_alloc_active_slots(mpt, KM_SLEEP)) {
12990 goto fail;
12991 }
12992 /*
12993 * Allocate request message frames, reply free queue, reply descriptor
12994 * post queue, and reply message frames using latest IOC facts.
12995 */
12996 if (mptsas_alloc_request_frames(mpt) == DDI_FAILURE) {
12997 mptsas_log(mpt, CE_WARN, "mptsas_alloc_request_frames failed");
12998 goto fail;
12999 }
13000 if (mptsas_alloc_sense_bufs(mpt) == DDI_FAILURE) {
13001 mptsas_log(mpt, CE_WARN, "mptsas_alloc_sense_bufs failed");
13002 goto fail;
13003 }
13004 if (mptsas_alloc_free_queue(mpt) == DDI_FAILURE) {
13005 mptsas_log(mpt, CE_WARN, "mptsas_alloc_free_queue failed!");
13006 goto fail;
13007 }
13008 if (mptsas_alloc_post_queue(mpt) == DDI_FAILURE) {
13009 mptsas_log(mpt, CE_WARN, "mptsas_alloc_post_queue failed!");
13010 goto fail;
13011 }
13012 if (mptsas_alloc_reply_frames(mpt) == DDI_FAILURE) {
13013 mptsas_log(mpt, CE_WARN, "mptsas_alloc_reply_frames failed!");
13014 goto fail;
13015 }
13016
13017 mur:
13018 /*
13019 * Re-Initialize ioc to operational state
13020 */
13021 if (mptsas_ioc_init(mpt) == DDI_FAILURE) {
13022 mptsas_log(mpt, CE_WARN, "mptsas_ioc_init failed");
13023 goto fail;
13024 }
13025
13026 mptsas_alloc_reply_args(mpt);
13027
13028 /*
13029 * Initialize reply post index. Reply free index is initialized after
13030 * the next loop.
13031 */
13032 mpt->m_post_index = 0;
13033
13034 /*
13035 * Initialize the Reply Free Queue with the physical addresses of our
13036 * reply frames.
13037 */
13038 cookie.dmac_address = mpt->m_reply_frame_dma_addr & 0xffffffffu;
13039 for (i = 0; i < mpt->m_max_replies; i++) {
13040 ddi_put32(mpt->m_acc_free_queue_hdl,
13041 &((uint32_t *)(void *)mpt->m_free_queue)[i],
13042 cookie.dmac_address);
13043 cookie.dmac_address += mpt->m_reply_frame_size;
13044 }
13045 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0,
13046 DDI_DMA_SYNC_FORDEV);
13047
13048 /*
13049 * Initialize the reply free index to one past the last frame on the
13050 * queue. This will signify that the queue is empty to start with.
13051 */
13052 mpt->m_free_index = i;
13053 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex, i);
13054
13055 /*
13056 * Initialize the reply post queue to 0xFFFFFFFF,0xFFFFFFFF's.
13057 */
13058 for (i = 0; i < mpt->m_post_queue_depth; i++) {
13059 ddi_put64(mpt->m_acc_post_queue_hdl,
13060 &((uint64_t *)(void *)mpt->m_post_queue)[i],
13061 0xFFFFFFFFFFFFFFFF);
13062 }
13063 (void) ddi_dma_sync(mpt->m_dma_post_queue_hdl, 0, 0,
13064 DDI_DMA_SYNC_FORDEV);
13065
13066 /*
13067 * Enable ports
13068 */
13069 if (mptsas_ioc_enable_port(mpt) == DDI_FAILURE) {
13070 mptsas_log(mpt, CE_WARN, "mptsas_ioc_enable_port failed");
13071 goto fail;
13072 }
13073
13074 /*
13075 * enable events
13076 */
13077 if (mptsas_ioc_enable_event_notification(mpt)) {
13078 mptsas_log(mpt, CE_WARN,
13079 "mptsas_ioc_enable_event_notification failed");
13080 goto fail;
13081 }
13082
13083 /*
13084 * We need checks in attach and these.
13085 * chip_init is called in mult. places
13086 */
13087
13088 if ((mptsas_check_dma_handle(mpt->m_dma_req_frame_hdl) !=
13089 DDI_SUCCESS) ||
13090 (mptsas_check_dma_handle(mpt->m_dma_req_sense_hdl) !=
13091 DDI_SUCCESS) ||
13092 (mptsas_check_dma_handle(mpt->m_dma_reply_frame_hdl) !=
13093 DDI_SUCCESS) ||
13094 (mptsas_check_dma_handle(mpt->m_dma_free_queue_hdl) !=
13095 DDI_SUCCESS) ||
13096 (mptsas_check_dma_handle(mpt->m_dma_post_queue_hdl) !=
13097 DDI_SUCCESS) ||
13098 (mptsas_check_dma_handle(mpt->m_hshk_dma_hdl) !=
13099 DDI_SUCCESS)) {
13100 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
13101 goto fail;
13102 }
13103
13104 /* Check all acc handles */
13105 if ((mptsas_check_acc_handle(mpt->m_datap) != DDI_SUCCESS) ||
13106 (mptsas_check_acc_handle(mpt->m_acc_req_frame_hdl) !=
13107 DDI_SUCCESS) ||
13108 (mptsas_check_acc_handle(mpt->m_acc_req_sense_hdl) !=
13109 DDI_SUCCESS) ||
13110 (mptsas_check_acc_handle(mpt->m_acc_reply_frame_hdl) !=
13111 DDI_SUCCESS) ||
13112 (mptsas_check_acc_handle(mpt->m_acc_free_queue_hdl) !=
13113 DDI_SUCCESS) ||
13114 (mptsas_check_acc_handle(mpt->m_acc_post_queue_hdl) !=
13115 DDI_SUCCESS) ||
13116 (mptsas_check_acc_handle(mpt->m_hshk_acc_hdl) !=
13117 DDI_SUCCESS) ||
13118 (mptsas_check_acc_handle(mpt->m_config_handle) !=
13119 DDI_SUCCESS)) {
13120 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED);
13121 goto fail;
13122 }
13123
13124 return (DDI_SUCCESS);
13125
13126 fail:
13127 return (DDI_FAILURE);
13128 }
13129
13130 static int
13131 mptsas_get_pci_cap(mptsas_t *mpt)
13132 {
13133 ushort_t caps_ptr, cap, cap_count;
13134
13135 if (mpt->m_config_handle == NULL)
13136 return (FALSE);
13137 /*
13138 * Check if capabilities list is supported and if so,
13139 * get initial capabilities pointer and clear bits 0,1.
13140 */
13141 if (pci_config_get16(mpt->m_config_handle, PCI_CONF_STAT)
13142 & PCI_STAT_CAP) {
13143 caps_ptr = P2ALIGN(pci_config_get8(mpt->m_config_handle,
13144 PCI_CONF_CAP_PTR), 4);
13145 } else {
13146 caps_ptr = PCI_CAP_NEXT_PTR_NULL;
13147 }
13148
13149 /*
13150 * Walk capabilities if supported.
13151 */
13152 for (cap_count = 0; caps_ptr != PCI_CAP_NEXT_PTR_NULL; ) {
13153
13154 /*
13155 * Check that we haven't exceeded the maximum number of
13156 * capabilities and that the pointer is in a valid range.
13157 */
13158 if (++cap_count > 48) {
13159 mptsas_log(mpt, CE_WARN,
13160 "too many device capabilities.\n");
13161 break;
13162 }
13163 if (caps_ptr < 64) {
13164 mptsas_log(mpt, CE_WARN,
13165 "capabilities pointer 0x%x out of range.\n",
13166 caps_ptr);
13167 break;
13168 }
13169
13170 /*
13171 * Get next capability and check that it is valid.
13172 * For now, we only support power management.
13173 */
13174 cap = pci_config_get8(mpt->m_config_handle, caps_ptr);
13175 switch (cap) {
13176 case PCI_CAP_ID_PM:
13177 mptsas_log(mpt, CE_NOTE,
13178 "?mptsas%d supports power management.\n",
13179 mpt->m_instance);
13180 mpt->m_options |= MPTSAS_OPT_PM;
13181
13182 /* Save PMCSR offset */
13183 mpt->m_pmcsr_offset = caps_ptr + PCI_PMCSR;
13184 break;
13185 /*
13186 * The following capabilities are valid. Any others
13187 * will cause a message to be logged.
13188 */
13189 case PCI_CAP_ID_VPD:
13190 case PCI_CAP_ID_MSI:
13191 case PCI_CAP_ID_PCIX:
13192 case PCI_CAP_ID_PCI_E:
13193 case PCI_CAP_ID_MSI_X:
13194 break;
13195 default:
13196 mptsas_log(mpt, CE_NOTE,
13197 "?mptsas%d unrecognized capability "
13198 "0x%x.\n", mpt->m_instance, cap);
13199 break;
13200 }
13201
13202 /*
13203 * Get next capabilities pointer and clear bits 0,1.
13204 */
13205 caps_ptr = P2ALIGN(pci_config_get8(mpt->m_config_handle,
13206 (caps_ptr + PCI_CAP_NEXT_PTR)), 4);
13207 }
13208 return (TRUE);
13209 }
13210
13211 static int
13212 mptsas_init_pm(mptsas_t *mpt)
13213 {
13214 char pmc_name[16];
13215 char *pmc[] = {
13216 NULL,
13217 "0=Off (PCI D3 State)",
13218 "3=On (PCI D0 State)",
13219 NULL
13220 };
13221 uint16_t pmcsr_stat;
13222
13223 if (mptsas_get_pci_cap(mpt) == FALSE) {
13224 return (DDI_FAILURE);
13225 }
13226 /*
13227 * If PCI's capability does not support PM, then don't need
13228 * to registe the pm-components
13229 */
13230 if (!(mpt->m_options & MPTSAS_OPT_PM))
13231 return (DDI_SUCCESS);
13232 /*
13233 * If power management is supported by this chip, create
13234 * pm-components property for the power management framework
13235 */
13236 (void) sprintf(pmc_name, "NAME=mptsas%d", mpt->m_instance);
13237 pmc[0] = pmc_name;
13238 if (ddi_prop_update_string_array(DDI_DEV_T_NONE, mpt->m_dip,
13239 "pm-components", pmc, 3) != DDI_PROP_SUCCESS) {
13240 mpt->m_options &= ~MPTSAS_OPT_PM;
13241 mptsas_log(mpt, CE_WARN,
13242 "mptsas%d: pm-component property creation failed.",
13243 mpt->m_instance);
13244 return (DDI_FAILURE);
13245 }
13246
13247 /*
13248 * Power on device.
13249 */
13250 (void) pm_busy_component(mpt->m_dip, 0);
13251 pmcsr_stat = pci_config_get16(mpt->m_config_handle,
13252 mpt->m_pmcsr_offset);
13253 if ((pmcsr_stat & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_D0) {
13254 mptsas_log(mpt, CE_WARN, "mptsas%d: Power up the device",
13255 mpt->m_instance);
13256 pci_config_put16(mpt->m_config_handle, mpt->m_pmcsr_offset,
13257 PCI_PMCSR_D0);
13258 }
13259 if (pm_power_has_changed(mpt->m_dip, 0, PM_LEVEL_D0) != DDI_SUCCESS) {
13260 mptsas_log(mpt, CE_WARN, "pm_power_has_changed failed");
13261 return (DDI_FAILURE);
13262 }
13263 mpt->m_power_level = PM_LEVEL_D0;
13264 /*
13265 * Set pm idle delay.
13266 */
13267 mpt->m_pm_idle_delay = ddi_prop_get_int(DDI_DEV_T_ANY,
13268 mpt->m_dip, 0, "mptsas-pm-idle-delay", MPTSAS_PM_IDLE_TIMEOUT);
13269
13270 return (DDI_SUCCESS);
13271 }
13272
13273 static int
13274 mptsas_register_intrs(mptsas_t *mpt)
13275 {
13276 dev_info_t *dip;
13277 int intr_types;
13278
13279 dip = mpt->m_dip;
13280
13281 /* Get supported interrupt types */
13282 if (ddi_intr_get_supported_types(dip, &intr_types) != DDI_SUCCESS) {
13283 mptsas_log(mpt, CE_WARN, "ddi_intr_get_supported_types "
13284 "failed\n");
13285 return (FALSE);
13286 }
13287
13288 NDBG6(("ddi_intr_get_supported_types() returned: 0x%x", intr_types));
13289
13290 /*
13291 * Try MSI, but fall back to FIXED
13292 */
13293 if (mptsas_enable_msi && (intr_types & DDI_INTR_TYPE_MSI)) {
13294 if (mptsas_add_intrs(mpt, DDI_INTR_TYPE_MSI) == DDI_SUCCESS) {
13295 NDBG0(("Using MSI interrupt type"));
13296 mpt->m_intr_type = DDI_INTR_TYPE_MSI;
13297 return (TRUE);
13298 }
13299 }
13300 if (intr_types & DDI_INTR_TYPE_FIXED) {
13301 if (mptsas_add_intrs(mpt, DDI_INTR_TYPE_FIXED) == DDI_SUCCESS) {
13302 NDBG0(("Using FIXED interrupt type"));
13303 mpt->m_intr_type = DDI_INTR_TYPE_FIXED;
13304 return (TRUE);
13305 } else {
13306 NDBG0(("FIXED interrupt registration failed"));
13307 return (FALSE);
13308 }
13309 }
13310
13311 return (FALSE);
13312 }
13313
13314 static void
13315 mptsas_unregister_intrs(mptsas_t *mpt)
13316 {
13317 mptsas_rem_intrs(mpt);
13318 }
13319
13320 /*
13321 * mptsas_add_intrs:
13322 *
13323 * Register FIXED or MSI interrupts.
13324 */
13325 static int
13326 mptsas_add_intrs(mptsas_t *mpt, int intr_type)
13327 {
13328 dev_info_t *dip = mpt->m_dip;
13329 int avail, actual, count = 0;
13330 int i, flag, ret;
13331
13332 NDBG6(("mptsas_add_intrs:interrupt type 0x%x", intr_type));
13333
13334 /* Get number of interrupts */
13335 ret = ddi_intr_get_nintrs(dip, intr_type, &count);
13336 if ((ret != DDI_SUCCESS) || (count <= 0)) {
13337 mptsas_log(mpt, CE_WARN, "ddi_intr_get_nintrs() failed, "
13338 "ret %d count %d\n", ret, count);
13339
13340 return (DDI_FAILURE);
13341 }
13342
13343 /* Get number of available interrupts */
13344 ret = ddi_intr_get_navail(dip, intr_type, &avail);
13345 if ((ret != DDI_SUCCESS) || (avail == 0)) {
13346 mptsas_log(mpt, CE_WARN, "ddi_intr_get_navail() failed, "
13347 "ret %d avail %d\n", ret, avail);
13348
13349 return (DDI_FAILURE);
13350 }
13351
13352 if (avail < count) {
13353 mptsas_log(mpt, CE_NOTE, "ddi_intr_get_nvail returned %d, "
13354 "navail() returned %d", count, avail);
13355 }
13356
13357 /* Mpt only have one interrupt routine */
13358 if ((intr_type == DDI_INTR_TYPE_MSI) && (count > 1)) {
13359 count = 1;
13360 }
13361
13362 /* Allocate an array of interrupt handles */
13363 mpt->m_intr_size = count * sizeof (ddi_intr_handle_t);
13364 mpt->m_htable = kmem_alloc(mpt->m_intr_size, KM_SLEEP);
13365
13366 flag = DDI_INTR_ALLOC_NORMAL;
13367
13368 /* call ddi_intr_alloc() */
13369 ret = ddi_intr_alloc(dip, mpt->m_htable, intr_type, 0,
13370 count, &actual, flag);
13371
13372 if ((ret != DDI_SUCCESS) || (actual == 0)) {
13373 mptsas_log(mpt, CE_WARN, "ddi_intr_alloc() failed, ret %d\n",
13374 ret);
13375 kmem_free(mpt->m_htable, mpt->m_intr_size);
13376 return (DDI_FAILURE);
13377 }
13378
13379 /* use interrupt count returned or abort? */
13380 if (actual < count) {
13381 mptsas_log(mpt, CE_NOTE, "Requested: %d, Received: %d\n",
13382 count, actual);
13383 }
13384
13385 mpt->m_intr_cnt = actual;
13386
13387 /*
13388 * Get priority for first msi, assume remaining are all the same
13389 */
13390 if ((ret = ddi_intr_get_pri(mpt->m_htable[0],
13391 &mpt->m_intr_pri)) != DDI_SUCCESS) {
13392 mptsas_log(mpt, CE_WARN, "ddi_intr_get_pri() failed %d\n", ret);
13393
13394 /* Free already allocated intr */
13395 for (i = 0; i < actual; i++) {
13396 (void) ddi_intr_free(mpt->m_htable[i]);
13397 }
13398
13399 kmem_free(mpt->m_htable, mpt->m_intr_size);
13400 return (DDI_FAILURE);
13401 }
13402
13403 /* Test for high level mutex */
13404 if (mpt->m_intr_pri >= ddi_intr_get_hilevel_pri()) {
13405 mptsas_log(mpt, CE_WARN, "mptsas_add_intrs: "
13406 "Hi level interrupt not supported\n");
13407
13408 /* Free already allocated intr */
13409 for (i = 0; i < actual; i++) {
13410 (void) ddi_intr_free(mpt->m_htable[i]);
13411 }
13412
13413 kmem_free(mpt->m_htable, mpt->m_intr_size);
13414 return (DDI_FAILURE);
13415 }
13416
13417 /* Call ddi_intr_add_handler() */
13418 for (i = 0; i < actual; i++) {
13419 if ((ret = ddi_intr_add_handler(mpt->m_htable[i], mptsas_intr,
13420 (caddr_t)mpt, (caddr_t)(uintptr_t)i)) != DDI_SUCCESS) {
13421 mptsas_log(mpt, CE_WARN, "ddi_intr_add_handler() "
13422 "failed %d\n", ret);
13423
13424 /* Free already allocated intr */
13425 for (i = 0; i < actual; i++) {
13426 (void) ddi_intr_free(mpt->m_htable[i]);
13427 }
13428
13429 kmem_free(mpt->m_htable, mpt->m_intr_size);
13430 return (DDI_FAILURE);
13431 }
13432 }
13433
13434 if ((ret = ddi_intr_get_cap(mpt->m_htable[0], &mpt->m_intr_cap))
13435 != DDI_SUCCESS) {
13436 mptsas_log(mpt, CE_WARN, "ddi_intr_get_cap() failed %d\n", ret);
13437
13438 /* Free already allocated intr */
13439 for (i = 0; i < actual; i++) {
13440 (void) ddi_intr_free(mpt->m_htable[i]);
13441 }
13442
13443 kmem_free(mpt->m_htable, mpt->m_intr_size);
13444 return (DDI_FAILURE);
13445 }
13446
13447 /*
13448 * Enable interrupts
13449 */
13450 if (mpt->m_intr_cap & DDI_INTR_FLAG_BLOCK) {
13451 /* Call ddi_intr_block_enable() for MSI interrupts */
13452 (void) ddi_intr_block_enable(mpt->m_htable, mpt->m_intr_cnt);
13453 } else {
13454 /* Call ddi_intr_enable for MSI or FIXED interrupts */
13455 for (i = 0; i < mpt->m_intr_cnt; i++) {
13456 (void) ddi_intr_enable(mpt->m_htable[i]);
13457 }
13458 }
13459 return (DDI_SUCCESS);
13460 }
13461
13462 /*
13463 * mptsas_rem_intrs:
13464 *
13465 * Unregister FIXED or MSI interrupts
13466 */
13467 static void
13468 mptsas_rem_intrs(mptsas_t *mpt)
13469 {
13470 int i;
13471
13472 NDBG6(("mptsas_rem_intrs"));
13473
13474 /* Disable all interrupts */
13475 if (mpt->m_intr_cap & DDI_INTR_FLAG_BLOCK) {
13476 /* Call ddi_intr_block_disable() */
13477 (void) ddi_intr_block_disable(mpt->m_htable, mpt->m_intr_cnt);
13478 } else {
13479 for (i = 0; i < mpt->m_intr_cnt; i++) {
13480 (void) ddi_intr_disable(mpt->m_htable[i]);
13481 }
13482 }
13483
13484 /* Call ddi_intr_remove_handler() */
13485 for (i = 0; i < mpt->m_intr_cnt; i++) {
13486 (void) ddi_intr_remove_handler(mpt->m_htable[i]);
13487 (void) ddi_intr_free(mpt->m_htable[i]);
13488 }
13489
13490 kmem_free(mpt->m_htable, mpt->m_intr_size);
13491 }
13492
13493 /*
13494 * The IO fault service error handling callback function
13495 */
13496 /*ARGSUSED*/
13497 static int
13498 mptsas_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, const void *impl_data)
13499 {
13500 /*
13501 * as the driver can always deal with an error in any dma or
13502 * access handle, we can just return the fme_status value.
13503 */
13504 pci_ereport_post(dip, err, NULL);
13505 return (err->fme_status);
13506 }
13507
13508 /*
13509 * mptsas_fm_init - initialize fma capabilities and register with IO
13510 * fault services.
13511 */
13512 static void
13513 mptsas_fm_init(mptsas_t *mpt)
13514 {
13515 /*
13516 * Need to change iblock to priority for new MSI intr
13517 */
13518 ddi_iblock_cookie_t fm_ibc;
13519
13520 /* Only register with IO Fault Services if we have some capability */
13521 if (mpt->m_fm_capabilities) {
13522 /* Adjust access and dma attributes for FMA */
13523 mpt->m_reg_acc_attr.devacc_attr_access = DDI_FLAGERR_ACC;
13524 mpt->m_msg_dma_attr.dma_attr_flags |= DDI_DMA_FLAGERR;
13525 mpt->m_io_dma_attr.dma_attr_flags |= DDI_DMA_FLAGERR;
13526
13527 /*
13528 * Register capabilities with IO Fault Services.
13529 * mpt->m_fm_capabilities will be updated to indicate
13530 * capabilities actually supported (not requested.)
13531 */
13532 ddi_fm_init(mpt->m_dip, &mpt->m_fm_capabilities, &fm_ibc);
13533
13534 /*
13535 * Initialize pci ereport capabilities if ereport
13536 * capable (should always be.)
13537 */
13538 if (DDI_FM_EREPORT_CAP(mpt->m_fm_capabilities) ||
13539 DDI_FM_ERRCB_CAP(mpt->m_fm_capabilities)) {
13540 pci_ereport_setup(mpt->m_dip);
13541 }
13542
13543 /*
13544 * Register error callback if error callback capable.
13545 */
13546 if (DDI_FM_ERRCB_CAP(mpt->m_fm_capabilities)) {
13547 ddi_fm_handler_register(mpt->m_dip,
13548 mptsas_fm_error_cb, (void *) mpt);
13549 }
13550 }
13551 }
13552
13553 /*
13554 * mptsas_fm_fini - Releases fma capabilities and un-registers with IO
13555 * fault services.
13556 *
13557 */
13558 static void
13559 mptsas_fm_fini(mptsas_t *mpt)
13560 {
13561 /* Only unregister FMA capabilities if registered */
13562 if (mpt->m_fm_capabilities) {
13563
13564 /*
13565 * Un-register error callback if error callback capable.
13566 */
13567
13568 if (DDI_FM_ERRCB_CAP(mpt->m_fm_capabilities)) {
13569 ddi_fm_handler_unregister(mpt->m_dip);
13570 }
13571
13572 /*
13573 * Release any resources allocated by pci_ereport_setup()
13574 */
13575
13576 if (DDI_FM_EREPORT_CAP(mpt->m_fm_capabilities) ||
13577 DDI_FM_ERRCB_CAP(mpt->m_fm_capabilities)) {
13578 pci_ereport_teardown(mpt->m_dip);
13579 }
13580
13581 /* Unregister from IO Fault Services */
13582 ddi_fm_fini(mpt->m_dip);
13583
13584 /* Adjust access and dma attributes for FMA */
13585 mpt->m_reg_acc_attr.devacc_attr_access = DDI_DEFAULT_ACC;
13586 mpt->m_msg_dma_attr.dma_attr_flags &= ~DDI_DMA_FLAGERR;
13587 mpt->m_io_dma_attr.dma_attr_flags &= ~DDI_DMA_FLAGERR;
13588
13589 }
13590 }
13591
13592 int
13593 mptsas_check_acc_handle(ddi_acc_handle_t handle)
13594 {
13595 ddi_fm_error_t de;
13596
13597 if (handle == NULL)
13598 return (DDI_FAILURE);
13599 ddi_fm_acc_err_get(handle, &de, DDI_FME_VER0);
13600 return (de.fme_status);
13601 }
13602
13603 int
13604 mptsas_check_dma_handle(ddi_dma_handle_t handle)
13605 {
13606 ddi_fm_error_t de;
13607
13608 if (handle == NULL)
13609 return (DDI_FAILURE);
13610 ddi_fm_dma_err_get(handle, &de, DDI_FME_VER0);
13611 return (de.fme_status);
13612 }
13613
13614 void
13615 mptsas_fm_ereport(mptsas_t *mpt, char *detail)
13616 {
13617 uint64_t ena;
13618 char buf[FM_MAX_CLASS];
13619
13620 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", DDI_FM_DEVICE, detail);
13621 ena = fm_ena_generate(0, FM_ENA_FMT1);
13622 if (DDI_FM_EREPORT_CAP(mpt->m_fm_capabilities)) {
13623 ddi_fm_ereport_post(mpt->m_dip, buf, ena, DDI_NOSLEEP,
13624 FM_VERSION, DATA_TYPE_UINT8, FM_EREPORT_VERS0, NULL);
13625 }
13626 }
13627
13628 static int
13629 mptsas_get_target_device_info(mptsas_t *mpt, uint32_t page_address,
13630 uint16_t *dev_handle, mptsas_target_t **pptgt)
13631 {
13632 int rval;
13633 uint32_t dev_info;
13634 uint64_t sas_wwn;
13635 mptsas_phymask_t phymask;
13636 uint8_t physport, phynum, config, disk;
13637 uint64_t devicename;
13638 uint16_t pdev_hdl;
13639 mptsas_target_t *tmp_tgt = NULL;
13640 uint16_t bay_num, enclosure, io_flags;
13641
13642 ASSERT(*pptgt == NULL);
13643
13644 rval = mptsas_get_sas_device_page0(mpt, page_address, dev_handle,
13645 &sas_wwn, &dev_info, &physport, &phynum, &pdev_hdl,
13646 &bay_num, &enclosure, &io_flags);
13647 if (rval != DDI_SUCCESS) {
13648 rval = DEV_INFO_FAIL_PAGE0;
13649 return (rval);
13650 }
13651
13652 if ((dev_info & (MPI2_SAS_DEVICE_INFO_SSP_TARGET |
13653 MPI2_SAS_DEVICE_INFO_SATA_DEVICE |
13654 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) == NULL) {
13655 rval = DEV_INFO_WRONG_DEVICE_TYPE;
13656 return (rval);
13657 }
13658
13659 /*
13660 * Check if the dev handle is for a Phys Disk. If so, set return value
13661 * and exit. Don't add Phys Disks to hash.
13662 */
13663 for (config = 0; config < mpt->m_num_raid_configs; config++) {
13664 for (disk = 0; disk < MPTSAS_MAX_DISKS_IN_CONFIG; disk++) {
13665 if (*dev_handle == mpt->m_raidconfig[config].
13666 m_physdisk_devhdl[disk]) {
13667 rval = DEV_INFO_PHYS_DISK;
13668 return (rval);
13669 }
13670 }
13671 }
13672
13673 /*
13674 * Get SATA Device Name from SAS device page0 for
13675 * sata device, if device name doesn't exist, set mta_wwn to
13676 * 0 for direct attached SATA. For the device behind the expander
13677 * we still can use STP address assigned by expander.
13678 */
13679 if (dev_info & (MPI2_SAS_DEVICE_INFO_SATA_DEVICE |
13680 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) {
13681 /* alloc a temporary target to send the cmd to */
13682 tmp_tgt = mptsas_tgt_alloc(mpt->m_tmp_targets, *dev_handle,
13683 0, dev_info, 0, 0);
13684 mutex_exit(&mpt->m_mutex);
13685
13686 devicename = mptsas_get_sata_guid(mpt, tmp_tgt, 0);
13687
13688 if (devicename == -1) {
13689 mutex_enter(&mpt->m_mutex);
13690 refhash_remove(mpt->m_tmp_targets, tmp_tgt);
13691 rval = DEV_INFO_FAIL_GUID;
13692 return (rval);
13693 }
13694
13695 if (devicename != 0 && (((devicename >> 56) & 0xf0) == 0x50)) {
13696 sas_wwn = devicename;
13697 } else if (dev_info & MPI2_SAS_DEVICE_INFO_DIRECT_ATTACH) {
13698 sas_wwn = 0;
13699 }
13700
13701 mutex_enter(&mpt->m_mutex);
13702 refhash_remove(mpt->m_tmp_targets, tmp_tgt);
13703 }
13704
13705 phymask = mptsas_physport_to_phymask(mpt, physport);
13706 *pptgt = mptsas_tgt_alloc(mpt->m_targets, *dev_handle, sas_wwn,
13707 dev_info, phymask, phynum);
13708 if (*pptgt == NULL) {
13709 mptsas_log(mpt, CE_WARN, "Failed to allocated target"
13710 "structure!");
13711 rval = DEV_INFO_FAIL_ALLOC;
13712 return (rval);
13713 }
13714 (*pptgt)->m_io_flags = io_flags;
13715 (*pptgt)->m_enclosure = enclosure;
13716 (*pptgt)->m_slot_num = bay_num;
13717 return (DEV_INFO_SUCCESS);
13718 }
13719
13720 uint64_t
13721 mptsas_get_sata_guid(mptsas_t *mpt, mptsas_target_t *ptgt, int lun)
13722 {
13723 uint64_t sata_guid = 0, *pwwn = NULL;
13724 int target = ptgt->m_devhdl;
13725 uchar_t *inq83 = NULL;
13726 int inq83_len = 0xFF;
13727 uchar_t *dblk = NULL;
13728 int inq83_retry = 3;
13729 int rval = DDI_FAILURE;
13730
13731 inq83 = kmem_zalloc(inq83_len, KM_SLEEP);
13732
13733 inq83_retry:
13734 rval = mptsas_inquiry(mpt, ptgt, lun, 0x83, inq83,
13735 inq83_len, NULL, 1);
13736 if (rval != DDI_SUCCESS) {
13737 mptsas_log(mpt, CE_WARN, "!mptsas request inquiry page "
13738 "0x83 for target:%x, lun:%x failed!", target, lun);
13739 sata_guid = -1;
13740 goto out;
13741 }
13742 /* According to SAT2, the first descriptor is logic unit name */
13743 dblk = &inq83[4];
13744 if ((dblk[1] & 0x30) != 0) {
13745 mptsas_log(mpt, CE_WARN, "!Descriptor is not lun associated.");
13746 goto out;
13747 }
13748 pwwn = (uint64_t *)(void *)(&dblk[4]);
13749 if ((dblk[4] & 0xf0) == 0x50) {
13750 sata_guid = BE_64(*pwwn);
13751 goto out;
13752 } else if (dblk[4] == 'A') {
13753 NDBG20(("SATA drive has no NAA format GUID."));
13754 goto out;
13755 } else {
13756 /* The data is not ready, wait and retry */
13757 inq83_retry--;
13758 if (inq83_retry <= 0) {
13759 goto out;
13760 }
13761 NDBG20(("The GUID is not ready, retry..."));
13762 delay(1 * drv_usectohz(1000000));
13763 goto inq83_retry;
13764 }
13765 out:
13766 kmem_free(inq83, inq83_len);
13767 return (sata_guid);
13768 }
13769
13770 static int
13771 mptsas_inquiry(mptsas_t *mpt, mptsas_target_t *ptgt, int lun, uchar_t page,
13772 unsigned char *buf, int len, int *reallen, uchar_t evpd)
13773 {
13774 uchar_t cdb[CDB_GROUP0];
13775 struct scsi_address ap;
13776 struct buf *data_bp = NULL;
13777 int resid = 0;
13778 int ret = DDI_FAILURE;
13779
13780 ASSERT(len <= 0xffff);
13781
13782 ap.a_target = MPTSAS_INVALID_DEVHDL;
13783 ap.a_lun = (uchar_t)(lun);
13784 ap.a_hba_tran = mpt->m_tran;
13785
13786 data_bp = scsi_alloc_consistent_buf(&ap,
13787 (struct buf *)NULL, len, B_READ, NULL_FUNC, NULL);
13788 if (data_bp == NULL) {
13789 return (ret);
13790 }
13791 bzero(cdb, CDB_GROUP0);
13792 cdb[0] = SCMD_INQUIRY;
13793 cdb[1] = evpd;
13794 cdb[2] = page;
13795 cdb[3] = (len & 0xff00) >> 8;
13796 cdb[4] = (len & 0x00ff);
13797 cdb[5] = 0;
13798
13799 ret = mptsas_send_scsi_cmd(mpt, &ap, ptgt, &cdb[0], CDB_GROUP0, data_bp,
13800 &resid);
13801 if (ret == DDI_SUCCESS) {
13802 if (reallen) {
13803 *reallen = len - resid;
13804 }
13805 bcopy((caddr_t)data_bp->b_un.b_addr, buf, len);
13806 }
13807 if (data_bp) {
13808 scsi_free_consistent_buf(data_bp);
13809 }
13810 return (ret);
13811 }
13812
13813 static int
13814 mptsas_send_scsi_cmd(mptsas_t *mpt, struct scsi_address *ap,
13815 mptsas_target_t *ptgt, uchar_t *cdb, int cdblen, struct buf *data_bp,
13816 int *resid)
13817 {
13818 struct scsi_pkt *pktp = NULL;
13819 scsi_hba_tran_t *tran_clone = NULL;
13820 mptsas_tgt_private_t *tgt_private = NULL;
13821 int ret = DDI_FAILURE;
13822
13823 /*
13824 * scsi_hba_tran_t->tran_tgt_private is used to pass the address
13825 * information to scsi_init_pkt, allocate a scsi_hba_tran structure
13826 * to simulate the cmds from sd
13827 */
13828 tran_clone = kmem_alloc(
13829 sizeof (scsi_hba_tran_t), KM_SLEEP);
13830 if (tran_clone == NULL) {
13831 goto out;
13832 }
13833 bcopy((caddr_t)mpt->m_tran,
13834 (caddr_t)tran_clone, sizeof (scsi_hba_tran_t));
13835 tgt_private = kmem_alloc(
13836 sizeof (mptsas_tgt_private_t), KM_SLEEP);
13837 if (tgt_private == NULL) {
13838 goto out;
13839 }
13840 tgt_private->t_lun = ap->a_lun;
13841 tgt_private->t_private = ptgt;
13842 tran_clone->tran_tgt_private = tgt_private;
13843 ap->a_hba_tran = tran_clone;
13844
13845 pktp = scsi_init_pkt(ap, (struct scsi_pkt *)NULL,
13846 data_bp, cdblen, sizeof (struct scsi_arq_status),
13847 0, PKT_CONSISTENT, NULL, NULL);
13848 if (pktp == NULL) {
13849 goto out;
13850 }
13851 bcopy(cdb, pktp->pkt_cdbp, cdblen);
13852 pktp->pkt_flags = FLAG_NOPARITY;
13853 if (scsi_poll(pktp) < 0) {
13854 goto out;
13855 }
13856 if (((struct scsi_status *)pktp->pkt_scbp)->sts_chk) {
13857 goto out;
13858 }
13859 if (resid != NULL) {
13860 *resid = pktp->pkt_resid;
13861 }
13862
13863 ret = DDI_SUCCESS;
13864 out:
13865 if (pktp) {
13866 scsi_destroy_pkt(pktp);
13867 }
13868 if (tran_clone) {
13869 kmem_free(tran_clone, sizeof (scsi_hba_tran_t));
13870 }
13871 if (tgt_private) {
13872 kmem_free(tgt_private, sizeof (mptsas_tgt_private_t));
13873 }
13874 return (ret);
13875 }
13876 static int
13877 mptsas_parse_address(char *name, uint64_t *wwid, uint8_t *phy, int *lun)
13878 {
13879 char *cp = NULL;
13880 char *ptr = NULL;
13881 size_t s = 0;
13882 char *wwid_str = NULL;
13883 char *lun_str = NULL;
13884 long lunnum;
13885 long phyid = -1;
13886 int rc = DDI_FAILURE;
13887
13888 ptr = name;
13889 ASSERT(ptr[0] == 'w' || ptr[0] == 'p');
13890 ptr++;
13891 if ((cp = strchr(ptr, ',')) == NULL) {
13892 return (DDI_FAILURE);
13893 }
13894
13895 wwid_str = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
13896 s = (uintptr_t)cp - (uintptr_t)ptr;
13897
13898 bcopy(ptr, wwid_str, s);
13899 wwid_str[s] = '\0';
13900
13901 ptr = ++cp;
13902
13903 if ((cp = strchr(ptr, '\0')) == NULL) {
13904 goto out;
13905 }
13906 lun_str = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
13907 s = (uintptr_t)cp - (uintptr_t)ptr;
13908
13909 bcopy(ptr, lun_str, s);
13910 lun_str[s] = '\0';
13911
13912 if (name[0] == 'p') {
13913 rc = ddi_strtol(wwid_str, NULL, 0x10, &phyid);
13914 } else {
13915 rc = scsi_wwnstr_to_wwn(wwid_str, wwid);
13916 }
13917 if (rc != DDI_SUCCESS)
13918 goto out;
13919
13920 if (phyid != -1) {
13921 ASSERT(phyid < MPTSAS_MAX_PHYS);
13922 *phy = (uint8_t)phyid;
13923 }
13924 rc = ddi_strtol(lun_str, NULL, 0x10, &lunnum);
13925 if (rc != 0)
13926 goto out;
13927
13928 *lun = (int)lunnum;
13929 rc = DDI_SUCCESS;
13930 out:
13931 if (wwid_str)
13932 kmem_free(wwid_str, SCSI_MAXNAMELEN);
13933 if (lun_str)
13934 kmem_free(lun_str, SCSI_MAXNAMELEN);
13935
13936 return (rc);
13937 }
13938
13939 /*
13940 * mptsas_parse_smp_name() is to parse sas wwn string
13941 * which format is "wWWN"
13942 */
13943 static int
13944 mptsas_parse_smp_name(char *name, uint64_t *wwn)
13945 {
13946 char *ptr = name;
13947
13948 if (*ptr != 'w') {
13949 return (DDI_FAILURE);
13950 }
13951
13952 ptr++;
13953 if (scsi_wwnstr_to_wwn(ptr, wwn)) {
13954 return (DDI_FAILURE);
13955 }
13956 return (DDI_SUCCESS);
13957 }
13958
13959 static int
13960 mptsas_bus_config(dev_info_t *pdip, uint_t flag,
13961 ddi_bus_config_op_t op, void *arg, dev_info_t **childp)
13962 {
13963 int ret = NDI_FAILURE;
13964 int circ = 0;
13965 int circ1 = 0;
13966 mptsas_t *mpt;
13967 char *ptr = NULL;
13968 char *devnm = NULL;
13969 uint64_t wwid = 0;
13970 uint8_t phy = 0xFF;
13971 int lun = 0;
13972 uint_t mflags = flag;
13973 int bconfig = TRUE;
13974
13975 if (scsi_hba_iport_unit_address(pdip) == 0) {
13976 return (DDI_FAILURE);
13977 }
13978
13979 mpt = DIP2MPT(pdip);
13980 if (!mpt) {
13981 return (DDI_FAILURE);
13982 }
13983 /*
13984 * Hold the nexus across the bus_config
13985 */
13986 ndi_devi_enter(scsi_vhci_dip, &circ);
13987 ndi_devi_enter(pdip, &circ1);
13988 switch (op) {
13989 case BUS_CONFIG_ONE:
13990 /* parse wwid/target name out of name given */
13991 if ((ptr = strchr((char *)arg, '@')) == NULL) {
13992 ret = NDI_FAILURE;
13993 break;
13994 }
13995 ptr++;
13996 if (strncmp((char *)arg, "smp", 3) == 0) {
13997 /*
13998 * This is a SMP target device
13999 */
14000 ret = mptsas_parse_smp_name(ptr, &wwid);
14001 if (ret != DDI_SUCCESS) {
14002 ret = NDI_FAILURE;
14003 break;
14004 }
14005 ret = mptsas_config_smp(pdip, wwid, childp);
14006 } else if ((ptr[0] == 'w') || (ptr[0] == 'p')) {
14007 /*
14008 * OBP could pass down a non-canonical form
14009 * bootpath without LUN part when LUN is 0.
14010 * So driver need adjust the string.
14011 */
14012 if (strchr(ptr, ',') == NULL) {
14013 devnm = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
14014 (void) sprintf(devnm, "%s,0", (char *)arg);
14015 ptr = strchr(devnm, '@');
14016 ptr++;
14017 }
14018
14019 /*
14020 * The device path is wWWID format and the device
14021 * is not SMP target device.
14022 */
14023 ret = mptsas_parse_address(ptr, &wwid, &phy, &lun);
14024 if (ret != DDI_SUCCESS) {
14025 ret = NDI_FAILURE;
14026 break;
14027 }
14028 *childp = NULL;
14029 if (ptr[0] == 'w') {
14030 ret = mptsas_config_one_addr(pdip, wwid,
14031 lun, childp);
14032 } else if (ptr[0] == 'p') {
14033 ret = mptsas_config_one_phy(pdip, phy, lun,
14034 childp);
14035 }
14036
14037 /*
14038 * If this is CD/DVD device in OBP path, the
14039 * ndi_busop_bus_config can be skipped as config one
14040 * operation is done above.
14041 */
14042 if ((ret == NDI_SUCCESS) && (*childp != NULL) &&
14043 (strcmp(ddi_node_name(*childp), "cdrom") == 0) &&
14044 (strncmp((char *)arg, "disk", 4) == 0)) {
14045 bconfig = FALSE;
14046 ndi_hold_devi(*childp);
14047 }
14048 } else {
14049 ret = NDI_FAILURE;
14050 break;
14051 }
14052
14053 /*
14054 * DDI group instructed us to use this flag.
14055 */
14056 mflags |= NDI_MDI_FALLBACK;
14057 break;
14058 case BUS_CONFIG_DRIVER:
14059 case BUS_CONFIG_ALL:
14060 mptsas_config_all(pdip);
14061 ret = NDI_SUCCESS;
14062 break;
14063 }
14064
14065 if ((ret == NDI_SUCCESS) && bconfig) {
14066 ret = ndi_busop_bus_config(pdip, mflags, op,
14067 (devnm == NULL) ? arg : devnm, childp, 0);
14068 }
14069
14070 ndi_devi_exit(pdip, circ1);
14071 ndi_devi_exit(scsi_vhci_dip, circ);
14072 if (devnm != NULL)
14073 kmem_free(devnm, SCSI_MAXNAMELEN);
14074 return (ret);
14075 }
14076
14077 static int
14078 mptsas_probe_lun(dev_info_t *pdip, int lun, dev_info_t **dip,
14079 mptsas_target_t *ptgt)
14080 {
14081 int rval = DDI_FAILURE;
14082 struct scsi_inquiry *sd_inq = NULL;
14083 mptsas_t *mpt = DIP2MPT(pdip);
14084
14085 sd_inq = (struct scsi_inquiry *)kmem_alloc(SUN_INQSIZE, KM_SLEEP);
14086
14087 rval = mptsas_inquiry(mpt, ptgt, lun, 0, (uchar_t *)sd_inq,
14088 SUN_INQSIZE, 0, (uchar_t)0);
14089
14090 if ((rval == DDI_SUCCESS) && MPTSAS_VALID_LUN(sd_inq)) {
14091 rval = mptsas_create_lun(pdip, sd_inq, dip, ptgt, lun);
14092 } else {
14093 rval = DDI_FAILURE;
14094 }
14095
14096 kmem_free(sd_inq, SUN_INQSIZE);
14097 return (rval);
14098 }
14099
14100 static int
14101 mptsas_config_one_addr(dev_info_t *pdip, uint64_t sasaddr, int lun,
14102 dev_info_t **lundip)
14103 {
14104 int rval;
14105 mptsas_t *mpt = DIP2MPT(pdip);
14106 int phymask;
14107 mptsas_target_t *ptgt = NULL;
14108
14109 /*
14110 * Get the physical port associated to the iport
14111 */
14112 phymask = ddi_prop_get_int(DDI_DEV_T_ANY, pdip, 0,
14113 "phymask", 0);
14114
14115 ptgt = mptsas_wwid_to_ptgt(mpt, phymask, sasaddr);
14116 if (ptgt == NULL) {
14117 /*
14118 * didn't match any device by searching
14119 */
14120 return (DDI_FAILURE);
14121 }
14122 /*
14123 * If the LUN already exists and the status is online,
14124 * we just return the pointer to dev_info_t directly.
14125 * For the mdi_pathinfo node, we'll handle it in
14126 * mptsas_create_virt_lun()
14127 * TODO should be also in mptsas_handle_dr
14128 */
14129
14130 *lundip = mptsas_find_child_addr(pdip, sasaddr, lun);
14131 if (*lundip != NULL) {
14132 /*
14133 * TODO Another senario is, we hotplug the same disk
14134 * on the same slot, the devhdl changed, is this
14135 * possible?
14136 * tgt_private->t_private != ptgt
14137 */
14138 if (sasaddr != ptgt->m_addr.mta_wwn) {
14139 /*
14140 * The device has changed although the devhdl is the
14141 * same (Enclosure mapping mode, change drive on the
14142 * same slot)
14143 */
14144 return (DDI_FAILURE);
14145 }
14146 return (DDI_SUCCESS);
14147 }
14148
14149 if (phymask == 0) {
14150 /*
14151 * Configure IR volume
14152 */
14153 rval = mptsas_config_raid(pdip, ptgt->m_devhdl, lundip);
14154 return (rval);
14155 }
14156 rval = mptsas_probe_lun(pdip, lun, lundip, ptgt);
14157
14158 return (rval);
14159 }
14160
14161 static int
14162 mptsas_config_one_phy(dev_info_t *pdip, uint8_t phy, int lun,
14163 dev_info_t **lundip)
14164 {
14165 int rval;
14166 mptsas_t *mpt = DIP2MPT(pdip);
14167 mptsas_phymask_t phymask;
14168 mptsas_target_t *ptgt = NULL;
14169
14170 /*
14171 * Get the physical port associated to the iport
14172 */
14173 phymask = (mptsas_phymask_t)ddi_prop_get_int(DDI_DEV_T_ANY, pdip, 0,
14174 "phymask", 0);
14175
14176 ptgt = mptsas_phy_to_tgt(mpt, phymask, phy);
14177 if (ptgt == NULL) {
14178 /*
14179 * didn't match any device by searching
14180 */
14181 return (DDI_FAILURE);
14182 }
14183
14184 /*
14185 * If the LUN already exists and the status is online,
14186 * we just return the pointer to dev_info_t directly.
14187 * For the mdi_pathinfo node, we'll handle it in
14188 * mptsas_create_virt_lun().
14189 */
14190
14191 *lundip = mptsas_find_child_phy(pdip, phy);
14192 if (*lundip != NULL) {
14193 return (DDI_SUCCESS);
14194 }
14195
14196 rval = mptsas_probe_lun(pdip, lun, lundip, ptgt);
14197
14198 return (rval);
14199 }
14200
14201 static int
14202 mptsas_retrieve_lundata(int lun_cnt, uint8_t *buf, uint16_t *lun_num,
14203 uint8_t *lun_addr_type)
14204 {
14205 uint32_t lun_idx = 0;
14206
14207 ASSERT(lun_num != NULL);
14208 ASSERT(lun_addr_type != NULL);
14209
14210 lun_idx = (lun_cnt + 1) * MPTSAS_SCSI_REPORTLUNS_ADDRESS_SIZE;
14211 /* determine report luns addressing type */
14212 switch (buf[lun_idx] & MPTSAS_SCSI_REPORTLUNS_ADDRESS_MASK) {
14213 /*
14214 * Vendors in the field have been found to be concatenating
14215 * bus/target/lun to equal the complete lun value instead
14216 * of switching to flat space addressing
14217 */
14218 /* 00b - peripheral device addressing method */
14219 case MPTSAS_SCSI_REPORTLUNS_ADDRESS_PERIPHERAL:
14220 /* FALLTHRU */
14221 /* 10b - logical unit addressing method */
14222 case MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT:
14223 /* FALLTHRU */
14224 /* 01b - flat space addressing method */
14225 case MPTSAS_SCSI_REPORTLUNS_ADDRESS_FLAT_SPACE:
14226 /* byte0 bit0-5=msb lun byte1 bit0-7=lsb lun */
14227 *lun_addr_type = (buf[lun_idx] &
14228 MPTSAS_SCSI_REPORTLUNS_ADDRESS_MASK) >> 6;
14229 *lun_num = (buf[lun_idx] & 0x3F) << 8;
14230 *lun_num |= buf[lun_idx + 1];
14231 return (DDI_SUCCESS);
14232 default:
14233 return (DDI_FAILURE);
14234 }
14235 }
14236
14237 static int
14238 mptsas_config_luns(dev_info_t *pdip, mptsas_target_t *ptgt)
14239 {
14240 struct buf *repluns_bp = NULL;
14241 struct scsi_address ap;
14242 uchar_t cdb[CDB_GROUP5];
14243 int ret = DDI_FAILURE;
14244 int retry = 0;
14245 int lun_list_len = 0;
14246 uint16_t lun_num = 0;
14247 uint8_t lun_addr_type = 0;
14248 uint32_t lun_cnt = 0;
14249 uint32_t lun_total = 0;
14250 dev_info_t *cdip = NULL;
14251 uint16_t *saved_repluns = NULL;
14252 char *buffer = NULL;
14253 int buf_len = 128;
14254 mptsas_t *mpt = DIP2MPT(pdip);
14255 uint64_t sas_wwn = 0;
14256 uint8_t phy = 0xFF;
14257 uint32_t dev_info = 0;
14258
14259 mutex_enter(&mpt->m_mutex);
14260 sas_wwn = ptgt->m_addr.mta_wwn;
14261 phy = ptgt->m_phynum;
14262 dev_info = ptgt->m_deviceinfo;
14263 mutex_exit(&mpt->m_mutex);
14264
14265 if (sas_wwn == 0) {
14266 /*
14267 * It's a SATA without Device Name
14268 * So don't try multi-LUNs
14269 */
14270 if (mptsas_find_child_phy(pdip, phy)) {
14271 return (DDI_SUCCESS);
14272 } else {
14273 /*
14274 * need configure and create node
14275 */
14276 return (DDI_FAILURE);
14277 }
14278 }
14279
14280 /*
14281 * WWN (SAS address or Device Name exist)
14282 */
14283 if (dev_info & (MPI2_SAS_DEVICE_INFO_SATA_DEVICE |
14284 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) {
14285 /*
14286 * SATA device with Device Name
14287 * So don't try multi-LUNs
14288 */
14289 if (mptsas_find_child_addr(pdip, sas_wwn, 0)) {
14290 return (DDI_SUCCESS);
14291 } else {
14292 return (DDI_FAILURE);
14293 }
14294 }
14295
14296 do {
14297 ap.a_target = MPTSAS_INVALID_DEVHDL;
14298 ap.a_lun = 0;
14299 ap.a_hba_tran = mpt->m_tran;
14300 repluns_bp = scsi_alloc_consistent_buf(&ap,
14301 (struct buf *)NULL, buf_len, B_READ, NULL_FUNC, NULL);
14302 if (repluns_bp == NULL) {
14303 retry++;
14304 continue;
14305 }
14306 bzero(cdb, CDB_GROUP5);
14307 cdb[0] = SCMD_REPORT_LUNS;
14308 cdb[6] = (buf_len & 0xff000000) >> 24;
14309 cdb[7] = (buf_len & 0x00ff0000) >> 16;
14310 cdb[8] = (buf_len & 0x0000ff00) >> 8;
14311 cdb[9] = (buf_len & 0x000000ff);
14312
14313 ret = mptsas_send_scsi_cmd(mpt, &ap, ptgt, &cdb[0], CDB_GROUP5,
14314 repluns_bp, NULL);
14315 if (ret != DDI_SUCCESS) {
14316 scsi_free_consistent_buf(repluns_bp);
14317 retry++;
14318 continue;
14319 }
14320 lun_list_len = BE_32(*(int *)((void *)(
14321 repluns_bp->b_un.b_addr)));
14322 if (buf_len >= lun_list_len + 8) {
14323 ret = DDI_SUCCESS;
14324 break;
14325 }
14326 scsi_free_consistent_buf(repluns_bp);
14327 buf_len = lun_list_len + 8;
14328
14329 } while (retry < 3);
14330
14331 if (ret != DDI_SUCCESS)
14332 return (ret);
14333 buffer = (char *)repluns_bp->b_un.b_addr;
14334 /*
14335 * find out the number of luns returned by the SCSI ReportLun call
14336 * and allocate buffer space
14337 */
14338 lun_total = lun_list_len / MPTSAS_SCSI_REPORTLUNS_ADDRESS_SIZE;
14339 saved_repluns = kmem_zalloc(sizeof (uint16_t) * lun_total, KM_SLEEP);
14340 if (saved_repluns == NULL) {
14341 scsi_free_consistent_buf(repluns_bp);
14342 return (DDI_FAILURE);
14343 }
14344 for (lun_cnt = 0; lun_cnt < lun_total; lun_cnt++) {
14345 if (mptsas_retrieve_lundata(lun_cnt, (uint8_t *)(buffer),
14346 &lun_num, &lun_addr_type) != DDI_SUCCESS) {
14347 continue;
14348 }
14349 saved_repluns[lun_cnt] = lun_num;
14350 if (cdip = mptsas_find_child_addr(pdip, sas_wwn, lun_num))
14351 ret = DDI_SUCCESS;
14352 else
14353 ret = mptsas_probe_lun(pdip, lun_num, &cdip,
14354 ptgt);
14355 if ((ret == DDI_SUCCESS) && (cdip != NULL)) {
14356 (void) ndi_prop_remove(DDI_DEV_T_NONE, cdip,
14357 MPTSAS_DEV_GONE);
14358 }
14359 }
14360 mptsas_offline_missed_luns(pdip, saved_repluns, lun_total, ptgt);
14361 kmem_free(saved_repluns, sizeof (uint16_t) * lun_total);
14362 scsi_free_consistent_buf(repluns_bp);
14363 return (DDI_SUCCESS);
14364 }
14365
14366 static int
14367 mptsas_config_raid(dev_info_t *pdip, uint16_t target, dev_info_t **dip)
14368 {
14369 int rval = DDI_FAILURE;
14370 struct scsi_inquiry *sd_inq = NULL;
14371 mptsas_t *mpt = DIP2MPT(pdip);
14372 mptsas_target_t *ptgt = NULL;
14373
14374 mutex_enter(&mpt->m_mutex);
14375 ptgt = refhash_linear_search(mpt->m_targets,
14376 mptsas_target_eval_devhdl, &target);
14377 mutex_exit(&mpt->m_mutex);
14378 if (ptgt == NULL) {
14379 mptsas_log(mpt, CE_WARN, "Volume with VolDevHandle of 0x%x "
14380 "not found.", target);
14381 return (rval);
14382 }
14383
14384 sd_inq = (struct scsi_inquiry *)kmem_alloc(SUN_INQSIZE, KM_SLEEP);
14385 rval = mptsas_inquiry(mpt, ptgt, 0, 0, (uchar_t *)sd_inq,
14386 SUN_INQSIZE, 0, (uchar_t)0);
14387
14388 if ((rval == DDI_SUCCESS) && MPTSAS_VALID_LUN(sd_inq)) {
14389 rval = mptsas_create_phys_lun(pdip, sd_inq, NULL, dip, ptgt,
14390 0);
14391 } else {
14392 rval = DDI_FAILURE;
14393 }
14394
14395 kmem_free(sd_inq, SUN_INQSIZE);
14396 return (rval);
14397 }
14398
14399 /*
14400 * configure all RAID volumes for virtual iport
14401 */
14402 static void
14403 mptsas_config_all_viport(dev_info_t *pdip)
14404 {
14405 mptsas_t *mpt = DIP2MPT(pdip);
14406 int config, vol;
14407 int target;
14408 dev_info_t *lundip = NULL;
14409
14410 /*
14411 * Get latest RAID info and search for any Volume DevHandles. If any
14412 * are found, configure the volume.
14413 */
14414 mutex_enter(&mpt->m_mutex);
14415 for (config = 0; config < mpt->m_num_raid_configs; config++) {
14416 for (vol = 0; vol < MPTSAS_MAX_RAIDVOLS; vol++) {
14417 if (mpt->m_raidconfig[config].m_raidvol[vol].m_israid
14418 == 1) {
14419 target = mpt->m_raidconfig[config].
14420 m_raidvol[vol].m_raidhandle;
14421 mutex_exit(&mpt->m_mutex);
14422 (void) mptsas_config_raid(pdip, target,
14423 &lundip);
14424 mutex_enter(&mpt->m_mutex);
14425 }
14426 }
14427 }
14428 mutex_exit(&mpt->m_mutex);
14429 }
14430
14431 static void
14432 mptsas_offline_missed_luns(dev_info_t *pdip, uint16_t *repluns,
14433 int lun_cnt, mptsas_target_t *ptgt)
14434 {
14435 dev_info_t *child = NULL, *savechild = NULL;
14436 mdi_pathinfo_t *pip = NULL, *savepip = NULL;
14437 uint64_t sas_wwn, wwid;
14438 uint8_t phy;
14439 int lun;
14440 int i;
14441 int find;
14442 char *addr;
14443 char *nodename;
14444 mptsas_t *mpt = DIP2MPT(pdip);
14445
14446 mutex_enter(&mpt->m_mutex);
14447 wwid = ptgt->m_addr.mta_wwn;
14448 mutex_exit(&mpt->m_mutex);
14449
14450 child = ddi_get_child(pdip);
14451 while (child) {
14452 find = 0;
14453 savechild = child;
14454 child = ddi_get_next_sibling(child);
14455
14456 nodename = ddi_node_name(savechild);
14457 if (strcmp(nodename, "smp") == 0) {
14458 continue;
14459 }
14460
14461 addr = ddi_get_name_addr(savechild);
14462 if (addr == NULL) {
14463 continue;
14464 }
14465
14466 if (mptsas_parse_address(addr, &sas_wwn, &phy, &lun) !=
14467 DDI_SUCCESS) {
14468 continue;
14469 }
14470
14471 if (wwid == sas_wwn) {
14472 for (i = 0; i < lun_cnt; i++) {
14473 if (repluns[i] == lun) {
14474 find = 1;
14475 break;
14476 }
14477 }
14478 } else {
14479 continue;
14480 }
14481 if (find == 0) {
14482 /*
14483 * The lun has not been there already
14484 */
14485 (void) mptsas_offline_lun(pdip, savechild, NULL,
14486 NDI_DEVI_REMOVE);
14487 }
14488 }
14489
14490 pip = mdi_get_next_client_path(pdip, NULL);
14491 while (pip) {
14492 find = 0;
14493 savepip = pip;
14494 addr = MDI_PI(pip)->pi_addr;
14495
14496 pip = mdi_get_next_client_path(pdip, pip);
14497
14498 if (addr == NULL) {
14499 continue;
14500 }
14501
14502 if (mptsas_parse_address(addr, &sas_wwn, &phy,
14503 &lun) != DDI_SUCCESS) {
14504 continue;
14505 }
14506
14507 if (sas_wwn == wwid) {
14508 for (i = 0; i < lun_cnt; i++) {
14509 if (repluns[i] == lun) {
14510 find = 1;
14511 break;
14512 }
14513 }
14514 } else {
14515 continue;
14516 }
14517
14518 if (find == 0) {
14519 /*
14520 * The lun has not been there already
14521 */
14522 (void) mptsas_offline_lun(pdip, NULL, savepip,
14523 NDI_DEVI_REMOVE);
14524 }
14525 }
14526 }
14527
14528 void
14529 mptsas_update_hashtab(struct mptsas *mpt)
14530 {
14531 uint32_t page_address;
14532 int rval = 0;
14533 uint16_t dev_handle;
14534 mptsas_target_t *ptgt = NULL;
14535 mptsas_smp_t smp_node;
14536
14537 /*
14538 * Get latest RAID info.
14539 */
14540 (void) mptsas_get_raid_info(mpt);
14541
14542 dev_handle = mpt->m_smp_devhdl;
14543 for (; mpt->m_done_traverse_smp == 0; ) {
14544 page_address = (MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL &
14545 MPI2_SAS_EXPAND_PGAD_FORM_MASK) | (uint32_t)dev_handle;
14546 if (mptsas_get_sas_expander_page0(mpt, page_address, &smp_node)
14547 != DDI_SUCCESS) {
14548 break;
14549 }
14550 mpt->m_smp_devhdl = dev_handle = smp_node.m_devhdl;
14551 (void) mptsas_smp_alloc(mpt, &smp_node);
14552 }
14553
14554 /*
14555 * Config target devices
14556 */
14557 dev_handle = mpt->m_dev_handle;
14558
14559 /*
14560 * Do loop to get sas device page 0 by GetNextHandle till the
14561 * the last handle. If the sas device is a SATA/SSP target,
14562 * we try to config it.
14563 */
14564 for (; mpt->m_done_traverse_dev == 0; ) {
14565 ptgt = NULL;
14566 page_address =
14567 (MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE &
14568 MPI2_SAS_DEVICE_PGAD_FORM_MASK) |
14569 (uint32_t)dev_handle;
14570 rval = mptsas_get_target_device_info(mpt, page_address,
14571 &dev_handle, &ptgt);
14572 if ((rval == DEV_INFO_FAIL_PAGE0) ||
14573 (rval == DEV_INFO_FAIL_ALLOC) ||
14574 (rval == DEV_INFO_FAIL_GUID)) {
14575 break;
14576 }
14577
14578 mpt->m_dev_handle = dev_handle;
14579 }
14580
14581 }
14582
14583 void
14584 mptsas_update_driver_data(struct mptsas *mpt)
14585 {
14586 mptsas_target_t *tp;
14587 mptsas_smp_t *sp;
14588
14589 ASSERT(MUTEX_HELD(&mpt->m_mutex));
14590
14591 /*
14592 * TODO after hard reset, update the driver data structures
14593 * 1. update port/phymask mapping table mpt->m_phy_info
14594 * 2. invalid all the entries in hash table
14595 * m_devhdl = 0xffff and m_deviceinfo = 0
14596 * 3. call sas_device_page/expander_page to update hash table
14597 */
14598 mptsas_update_phymask(mpt);
14599
14600 /*
14601 * Remove all the devhdls for existing entries but leave their
14602 * addresses alone. In update_hashtab() below, we'll find all
14603 * targets that are still present and reassociate them with
14604 * their potentially new devhdls. Leaving the targets around in
14605 * this fashion allows them to be used on the tx waitq even
14606 * while IOC reset is occurring.
14607 */
14608 for (tp = refhash_first(mpt->m_targets); tp != NULL;
14609 tp = refhash_next(mpt->m_targets, tp)) {
14610 tp->m_devhdl = MPTSAS_INVALID_DEVHDL;
14611 tp->m_deviceinfo = 0;
14612 tp->m_dr_flag = MPTSAS_DR_INACTIVE;
14613 }
14614 for (sp = refhash_first(mpt->m_smp_targets); sp != NULL;
14615 sp = refhash_next(mpt->m_smp_targets, sp)) {
14616 sp->m_devhdl = MPTSAS_INVALID_DEVHDL;
14617 sp->m_deviceinfo = 0;
14618 }
14619 mpt->m_done_traverse_dev = 0;
14620 mpt->m_done_traverse_smp = 0;
14621 mpt->m_dev_handle = mpt->m_smp_devhdl = MPTSAS_INVALID_DEVHDL;
14622 mptsas_update_hashtab(mpt);
14623 }
14624
14625 static void
14626 mptsas_config_all(dev_info_t *pdip)
14627 {
14628 dev_info_t *smpdip = NULL;
14629 mptsas_t *mpt = DIP2MPT(pdip);
14630 int phymask = 0;
14631 mptsas_phymask_t phy_mask;
14632 mptsas_target_t *ptgt = NULL;
14633 mptsas_smp_t *psmp;
14634
14635 /*
14636 * Get the phymask associated to the iport
14637 */
14638 phymask = ddi_prop_get_int(DDI_DEV_T_ANY, pdip, 0,
14639 "phymask", 0);
14640
14641 /*
14642 * Enumerate RAID volumes here (phymask == 0).
14643 */
14644 if (phymask == 0) {
14645 mptsas_config_all_viport(pdip);
14646 return;
14647 }
14648
14649 mutex_enter(&mpt->m_mutex);
14650
14651 if (!mpt->m_done_traverse_dev || !mpt->m_done_traverse_smp) {
14652 mptsas_update_hashtab(mpt);
14653 }
14654
14655 for (psmp = refhash_first(mpt->m_smp_targets); psmp != NULL;
14656 psmp = refhash_next(mpt->m_smp_targets, psmp)) {
14657 phy_mask = psmp->m_addr.mta_phymask;
14658 if (phy_mask == phymask) {
14659 smpdip = NULL;
14660 mutex_exit(&mpt->m_mutex);
14661 (void) mptsas_online_smp(pdip, psmp, &smpdip);
14662 mutex_enter(&mpt->m_mutex);
14663 }
14664 }
14665
14666 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL;
14667 ptgt = refhash_next(mpt->m_targets, ptgt)) {
14668 phy_mask = ptgt->m_addr.mta_phymask;
14669 if (phy_mask == phymask) {
14670 mutex_exit(&mpt->m_mutex);
14671 (void) mptsas_config_target(pdip, ptgt);
14672 mutex_enter(&mpt->m_mutex);
14673 }
14674 }
14675 mutex_exit(&mpt->m_mutex);
14676 }
14677
14678 static int
14679 mptsas_config_target(dev_info_t *pdip, mptsas_target_t *ptgt)
14680 {
14681 int rval = DDI_FAILURE;
14682 dev_info_t *tdip;
14683
14684 rval = mptsas_config_luns(pdip, ptgt);
14685 if (rval != DDI_SUCCESS) {
14686 /*
14687 * The return value means the SCMD_REPORT_LUNS
14688 * did not execute successfully. The target maybe
14689 * doesn't support such command.
14690 */
14691 rval = mptsas_probe_lun(pdip, 0, &tdip, ptgt);
14692 }
14693 return (rval);
14694 }
14695
14696 /*
14697 * Return fail if not all the childs/paths are freed.
14698 * if there is any path under the HBA, the return value will be always fail
14699 * because we didn't call mdi_pi_free for path
14700 */
14701 static int
14702 mptsas_offline_target(dev_info_t *pdip, char *name)
14703 {
14704 dev_info_t *child = NULL, *prechild = NULL;
14705 mdi_pathinfo_t *pip = NULL, *savepip = NULL;
14706 int tmp_rval, rval = DDI_SUCCESS;
14707 char *addr, *cp;
14708 size_t s;
14709 mptsas_t *mpt = DIP2MPT(pdip);
14710
14711 child = ddi_get_child(pdip);
14712 while (child) {
14713 addr = ddi_get_name_addr(child);
14714 prechild = child;
14715 child = ddi_get_next_sibling(child);
14716
14717 if (addr == NULL) {
14718 continue;
14719 }
14720 if ((cp = strchr(addr, ',')) == NULL) {
14721 continue;
14722 }
14723
14724 s = (uintptr_t)cp - (uintptr_t)addr;
14725
14726 if (strncmp(addr, name, s) != 0) {
14727 continue;
14728 }
14729
14730 tmp_rval = mptsas_offline_lun(pdip, prechild, NULL,
14731 NDI_DEVI_REMOVE);
14732 if (tmp_rval != DDI_SUCCESS) {
14733 rval = DDI_FAILURE;
14734 if (ndi_prop_create_boolean(DDI_DEV_T_NONE,
14735 prechild, MPTSAS_DEV_GONE) !=
14736 DDI_PROP_SUCCESS) {
14737 mptsas_log(mpt, CE_WARN, "mptsas driver "
14738 "unable to create property for "
14739 "SAS %s (MPTSAS_DEV_GONE)", addr);
14740 }
14741 }
14742 }
14743
14744 pip = mdi_get_next_client_path(pdip, NULL);
14745 while (pip) {
14746 addr = MDI_PI(pip)->pi_addr;
14747 savepip = pip;
14748 pip = mdi_get_next_client_path(pdip, pip);
14749 if (addr == NULL) {
14750 continue;
14751 }
14752
14753 if ((cp = strchr(addr, ',')) == NULL) {
14754 continue;
14755 }
14756
14757 s = (uintptr_t)cp - (uintptr_t)addr;
14758
14759 if (strncmp(addr, name, s) != 0) {
14760 continue;
14761 }
14762
14763 (void) mptsas_offline_lun(pdip, NULL, savepip,
14764 NDI_DEVI_REMOVE);
14765 /*
14766 * driver will not invoke mdi_pi_free, so path will not
14767 * be freed forever, return DDI_FAILURE.
14768 */
14769 rval = DDI_FAILURE;
14770 }
14771 return (rval);
14772 }
14773
14774 static int
14775 mptsas_offline_lun(dev_info_t *pdip, dev_info_t *rdip,
14776 mdi_pathinfo_t *rpip, uint_t flags)
14777 {
14778 int rval = DDI_FAILURE;
14779 char *devname;
14780 dev_info_t *cdip, *parent;
14781
14782 if (rpip != NULL) {
14783 parent = scsi_vhci_dip;
14784 cdip = mdi_pi_get_client(rpip);
14785 } else if (rdip != NULL) {
14786 parent = pdip;
14787 cdip = rdip;
14788 } else {
14789 return (DDI_FAILURE);
14790 }
14791
14792 /*
14793 * Make sure node is attached otherwise
14794 * it won't have related cache nodes to
14795 * clean up. i_ddi_devi_attached is
14796 * similiar to i_ddi_node_state(cdip) >=
14797 * DS_ATTACHED.
14798 */
14799 if (i_ddi_devi_attached(cdip)) {
14800
14801 /* Get full devname */
14802 devname = kmem_alloc(MAXNAMELEN + 1, KM_SLEEP);
14803 (void) ddi_deviname(cdip, devname);
14804 /* Clean cache */
14805 (void) devfs_clean(parent, devname + 1,
14806 DV_CLEAN_FORCE);
14807 kmem_free(devname, MAXNAMELEN + 1);
14808 }
14809 if (rpip != NULL) {
14810 if (MDI_PI_IS_OFFLINE(rpip)) {
14811 rval = DDI_SUCCESS;
14812 } else {
14813 rval = mdi_pi_offline(rpip, 0);
14814 }
14815 } else {
14816 rval = ndi_devi_offline(cdip, flags);
14817 }
14818
14819 return (rval);
14820 }
14821
14822 static dev_info_t *
14823 mptsas_find_smp_child(dev_info_t *parent, char *str_wwn)
14824 {
14825 dev_info_t *child = NULL;
14826 char *smp_wwn = NULL;
14827
14828 child = ddi_get_child(parent);
14829 while (child) {
14830 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, child,
14831 DDI_PROP_DONTPASS, SMP_WWN, &smp_wwn)
14832 != DDI_SUCCESS) {
14833 child = ddi_get_next_sibling(child);
14834 continue;
14835 }
14836
14837 if (strcmp(smp_wwn, str_wwn) == 0) {
14838 ddi_prop_free(smp_wwn);
14839 break;
14840 }
14841 child = ddi_get_next_sibling(child);
14842 ddi_prop_free(smp_wwn);
14843 }
14844 return (child);
14845 }
14846
14847 static int
14848 mptsas_offline_smp(dev_info_t *pdip, mptsas_smp_t *smp_node, uint_t flags)
14849 {
14850 int rval = DDI_FAILURE;
14851 char *devname;
14852 char wwn_str[MPTSAS_WWN_STRLEN];
14853 dev_info_t *cdip;
14854
14855 (void) sprintf(wwn_str, "%"PRIx64, smp_node->m_addr.mta_wwn);
14856
14857 cdip = mptsas_find_smp_child(pdip, wwn_str);
14858
14859 if (cdip == NULL)
14860 return (DDI_SUCCESS);
14861
14862 /*
14863 * Make sure node is attached otherwise
14864 * it won't have related cache nodes to
14865 * clean up. i_ddi_devi_attached is
14866 * similiar to i_ddi_node_state(cdip) >=
14867 * DS_ATTACHED.
14868 */
14869 if (i_ddi_devi_attached(cdip)) {
14870
14871 /* Get full devname */
14872 devname = kmem_alloc(MAXNAMELEN + 1, KM_SLEEP);
14873 (void) ddi_deviname(cdip, devname);
14874 /* Clean cache */
14875 (void) devfs_clean(pdip, devname + 1,
14876 DV_CLEAN_FORCE);
14877 kmem_free(devname, MAXNAMELEN + 1);
14878 }
14879
14880 rval = ndi_devi_offline(cdip, flags);
14881
14882 return (rval);
14883 }
14884
14885 static dev_info_t *
14886 mptsas_find_child(dev_info_t *pdip, char *name)
14887 {
14888 dev_info_t *child = NULL;
14889 char *rname = NULL;
14890 int rval = DDI_FAILURE;
14891
14892 rname = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
14893
14894 child = ddi_get_child(pdip);
14895 while (child) {
14896 rval = mptsas_name_child(child, rname, SCSI_MAXNAMELEN);
14897 if (rval != DDI_SUCCESS) {
14898 child = ddi_get_next_sibling(child);
14899 bzero(rname, SCSI_MAXNAMELEN);
14900 continue;
14901 }
14902
14903 if (strcmp(rname, name) == 0) {
14904 break;
14905 }
14906 child = ddi_get_next_sibling(child);
14907 bzero(rname, SCSI_MAXNAMELEN);
14908 }
14909
14910 kmem_free(rname, SCSI_MAXNAMELEN);
14911
14912 return (child);
14913 }
14914
14915
14916 static dev_info_t *
14917 mptsas_find_child_addr(dev_info_t *pdip, uint64_t sasaddr, int lun)
14918 {
14919 dev_info_t *child = NULL;
14920 char *name = NULL;
14921 char *addr = NULL;
14922
14923 name = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
14924 addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
14925 (void) sprintf(name, "%016"PRIx64, sasaddr);
14926 (void) sprintf(addr, "w%s,%x", name, lun);
14927 child = mptsas_find_child(pdip, addr);
14928 kmem_free(name, SCSI_MAXNAMELEN);
14929 kmem_free(addr, SCSI_MAXNAMELEN);
14930 return (child);
14931 }
14932
14933 static dev_info_t *
14934 mptsas_find_child_phy(dev_info_t *pdip, uint8_t phy)
14935 {
14936 dev_info_t *child;
14937 char *addr;
14938
14939 addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
14940 (void) sprintf(addr, "p%x,0", phy);
14941 child = mptsas_find_child(pdip, addr);
14942 kmem_free(addr, SCSI_MAXNAMELEN);
14943 return (child);
14944 }
14945
14946 static mdi_pathinfo_t *
14947 mptsas_find_path_phy(dev_info_t *pdip, uint8_t phy)
14948 {
14949 mdi_pathinfo_t *path;
14950 char *addr = NULL;
14951
14952 addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
14953 (void) sprintf(addr, "p%x,0", phy);
14954 path = mdi_pi_find(pdip, NULL, addr);
14955 kmem_free(addr, SCSI_MAXNAMELEN);
14956 return (path);
14957 }
14958
14959 static mdi_pathinfo_t *
14960 mptsas_find_path_addr(dev_info_t *parent, uint64_t sasaddr, int lun)
14961 {
14962 mdi_pathinfo_t *path;
14963 char *name = NULL;
14964 char *addr = NULL;
14965
14966 name = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
14967 addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
14968 (void) sprintf(name, "%016"PRIx64, sasaddr);
14969 (void) sprintf(addr, "w%s,%x", name, lun);
14970 path = mdi_pi_find(parent, NULL, addr);
14971 kmem_free(name, SCSI_MAXNAMELEN);
14972 kmem_free(addr, SCSI_MAXNAMELEN);
14973
14974 return (path);
14975 }
14976
14977 static int
14978 mptsas_create_lun(dev_info_t *pdip, struct scsi_inquiry *sd_inq,
14979 dev_info_t **lun_dip, mptsas_target_t *ptgt, int lun)
14980 {
14981 int i = 0;
14982 uchar_t *inq83 = NULL;
14983 int inq83_len1 = 0xFF;
14984 int inq83_len = 0;
14985 int rval = DDI_FAILURE;
14986 ddi_devid_t devid;
14987 char *guid = NULL;
14988 int target = ptgt->m_devhdl;
14989 mdi_pathinfo_t *pip = NULL;
14990 mptsas_t *mpt = DIP2MPT(pdip);
14991
14992 /*
14993 * For DVD/CD ROM and tape devices and optical
14994 * devices, we won't try to enumerate them under
14995 * scsi_vhci, so no need to try page83
14996 */
14997 if (sd_inq && (sd_inq->inq_dtype == DTYPE_RODIRECT ||
14998 sd_inq->inq_dtype == DTYPE_OPTICAL ||
14999 sd_inq->inq_dtype == DTYPE_ESI))
15000 goto create_lun;
15001
15002 /*
15003 * The LCA returns good SCSI status, but corrupt page 83 data the first
15004 * time it is queried. The solution is to keep trying to request page83
15005 * and verify the GUID is not (DDI_NOT_WELL_FORMED) in
15006 * mptsas_inq83_retry_timeout seconds. If the timeout expires, driver
15007 * give up to get VPD page at this stage and fail the enumeration.
15008 */
15009
15010 inq83 = kmem_zalloc(inq83_len1, KM_SLEEP);
15011
15012 for (i = 0; i < mptsas_inq83_retry_timeout; i++) {
15013 rval = mptsas_inquiry(mpt, ptgt, lun, 0x83, inq83,
15014 inq83_len1, &inq83_len, 1);
15015 if (rval != 0) {
15016 mptsas_log(mpt, CE_WARN, "!mptsas request inquiry page "
15017 "0x83 for target:%x, lun:%x failed!", target, lun);
15018 if (mptsas_physical_bind_failed_page_83 != B_FALSE)
15019 goto create_lun;
15020 goto out;
15021 }
15022 /*
15023 * create DEVID from inquiry data
15024 */
15025 if ((rval = ddi_devid_scsi_encode(
15026 DEVID_SCSI_ENCODE_VERSION_LATEST, NULL, (uchar_t *)sd_inq,
15027 sizeof (struct scsi_inquiry), NULL, 0, inq83,
15028 (size_t)inq83_len, &devid)) == DDI_SUCCESS) {
15029 /*
15030 * extract GUID from DEVID
15031 */
15032 guid = ddi_devid_to_guid(devid);
15033
15034 /*
15035 * Do not enable MPXIO if the strlen(guid) is greater
15036 * than MPTSAS_MAX_GUID_LEN, this constrain would be
15037 * handled by framework later.
15038 */
15039 if (guid && (strlen(guid) > MPTSAS_MAX_GUID_LEN)) {
15040 ddi_devid_free_guid(guid);
15041 guid = NULL;
15042 if (mpt->m_mpxio_enable == TRUE) {
15043 mptsas_log(mpt, CE_NOTE, "!Target:%x, "
15044 "lun:%x doesn't have a valid GUID, "
15045 "multipathing for this drive is "
15046 "not enabled", target, lun);
15047 }
15048 }
15049
15050 /*
15051 * devid no longer needed
15052 */
15053 ddi_devid_free(devid);
15054 break;
15055 } else if (rval == DDI_NOT_WELL_FORMED) {
15056 /*
15057 * return value of ddi_devid_scsi_encode equal to
15058 * DDI_NOT_WELL_FORMED means DEVID_RETRY, it worth
15059 * to retry inquiry page 0x83 and get GUID.
15060 */
15061 NDBG20(("Not well formed devid, retry..."));
15062 delay(1 * drv_usectohz(1000000));
15063 continue;
15064 } else {
15065 mptsas_log(mpt, CE_WARN, "!Encode devid failed for "
15066 "path target:%x, lun:%x", target, lun);
15067 rval = DDI_FAILURE;
15068 goto create_lun;
15069 }
15070 }
15071
15072 if (i == mptsas_inq83_retry_timeout) {
15073 mptsas_log(mpt, CE_WARN, "!Repeated page83 requests timeout "
15074 "for path target:%x, lun:%x", target, lun);
15075 }
15076
15077 rval = DDI_FAILURE;
15078
15079 create_lun:
15080 if ((guid != NULL) && (mpt->m_mpxio_enable == TRUE)) {
15081 rval = mptsas_create_virt_lun(pdip, sd_inq, guid, lun_dip, &pip,
15082 ptgt, lun);
15083 }
15084 if (rval != DDI_SUCCESS) {
15085 rval = mptsas_create_phys_lun(pdip, sd_inq, guid, lun_dip,
15086 ptgt, lun);
15087
15088 }
15089 out:
15090 if (guid != NULL) {
15091 /*
15092 * guid no longer needed
15093 */
15094 ddi_devid_free_guid(guid);
15095 }
15096 if (inq83 != NULL)
15097 kmem_free(inq83, inq83_len1);
15098 return (rval);
15099 }
15100
15101 static int
15102 mptsas_create_virt_lun(dev_info_t *pdip, struct scsi_inquiry *inq, char *guid,
15103 dev_info_t **lun_dip, mdi_pathinfo_t **pip, mptsas_target_t *ptgt, int lun)
15104 {
15105 int target;
15106 char *nodename = NULL;
15107 char **compatible = NULL;
15108 int ncompatible = 0;
15109 int mdi_rtn = MDI_FAILURE;
15110 int rval = DDI_FAILURE;
15111 char *old_guid = NULL;
15112 mptsas_t *mpt = DIP2MPT(pdip);
15113 char *lun_addr = NULL;
15114 char *wwn_str = NULL;
15115 char *attached_wwn_str = NULL;
15116 char *component = NULL;
15117 uint8_t phy = 0xFF;
15118 uint64_t sas_wwn;
15119 int64_t lun64 = 0;
15120 uint32_t devinfo;
15121 uint16_t dev_hdl;
15122 uint16_t pdev_hdl;
15123 uint64_t dev_sas_wwn;
15124 uint64_t pdev_sas_wwn;
15125 uint32_t pdev_info;
15126 uint8_t physport;
15127 uint8_t phy_id;
15128 uint32_t page_address;
15129 uint16_t bay_num, enclosure, io_flags;
15130 char pdev_wwn_str[MPTSAS_WWN_STRLEN];
15131 uint32_t dev_info;
15132
15133 mutex_enter(&mpt->m_mutex);
15134 target = ptgt->m_devhdl;
15135 sas_wwn = ptgt->m_addr.mta_wwn;
15136 devinfo = ptgt->m_deviceinfo;
15137 phy = ptgt->m_phynum;
15138 mutex_exit(&mpt->m_mutex);
15139
15140 if (sas_wwn) {
15141 *pip = mptsas_find_path_addr(pdip, sas_wwn, lun);
15142 } else {
15143 *pip = mptsas_find_path_phy(pdip, phy);
15144 }
15145
15146 if (*pip != NULL) {
15147 *lun_dip = MDI_PI(*pip)->pi_client->ct_dip;
15148 ASSERT(*lun_dip != NULL);
15149 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, *lun_dip,
15150 (DDI_PROP_DONTPASS | DDI_PROP_NOTPROM),
15151 MDI_CLIENT_GUID_PROP, &old_guid) == DDI_SUCCESS) {
15152 if (strncmp(guid, old_guid, strlen(guid)) == 0) {
15153 /*
15154 * Same path back online again.
15155 */
15156 (void) ddi_prop_free(old_guid);
15157 if ((!MDI_PI_IS_ONLINE(*pip)) &&
15158 (!MDI_PI_IS_STANDBY(*pip)) &&
15159 (ptgt->m_tgt_unconfigured == 0)) {
15160 rval = mdi_pi_online(*pip, 0);
15161 mutex_enter(&mpt->m_mutex);
15162 ptgt->m_led_status = 0;
15163 (void) mptsas_flush_led_status(mpt,
15164 ptgt);
15165 mutex_exit(&mpt->m_mutex);
15166 } else {
15167 rval = DDI_SUCCESS;
15168 }
15169 if (rval != DDI_SUCCESS) {
15170 mptsas_log(mpt, CE_WARN, "path:target: "
15171 "%x, lun:%x online failed!", target,
15172 lun);
15173 *pip = NULL;
15174 *lun_dip = NULL;
15175 }
15176 return (rval);
15177 } else {
15178 /*
15179 * The GUID of the LUN has changed which maybe
15180 * because customer mapped another volume to the
15181 * same LUN.
15182 */
15183 mptsas_log(mpt, CE_WARN, "The GUID of the "
15184 "target:%x, lun:%x was changed, maybe "
15185 "because someone mapped another volume "
15186 "to the same LUN", target, lun);
15187 (void) ddi_prop_free(old_guid);
15188 if (!MDI_PI_IS_OFFLINE(*pip)) {
15189 rval = mdi_pi_offline(*pip, 0);
15190 if (rval != MDI_SUCCESS) {
15191 mptsas_log(mpt, CE_WARN, "path:"
15192 "target:%x, lun:%x offline "
15193 "failed!", target, lun);
15194 *pip = NULL;
15195 *lun_dip = NULL;
15196 return (DDI_FAILURE);
15197 }
15198 }
15199 if (mdi_pi_free(*pip, 0) != MDI_SUCCESS) {
15200 mptsas_log(mpt, CE_WARN, "path:target:"
15201 "%x, lun:%x free failed!", target,
15202 lun);
15203 *pip = NULL;
15204 *lun_dip = NULL;
15205 return (DDI_FAILURE);
15206 }
15207 }
15208 } else {
15209 mptsas_log(mpt, CE_WARN, "Can't get client-guid "
15210 "property for path:target:%x, lun:%x", target, lun);
15211 *pip = NULL;
15212 *lun_dip = NULL;
15213 return (DDI_FAILURE);
15214 }
15215 }
15216 scsi_hba_nodename_compatible_get(inq, NULL,
15217 inq->inq_dtype, NULL, &nodename, &compatible, &ncompatible);
15218
15219 /*
15220 * if nodename can't be determined then print a message and skip it
15221 */
15222 if (nodename == NULL) {
15223 mptsas_log(mpt, CE_WARN, "mptsas driver found no compatible "
15224 "driver for target%d lun %d dtype:0x%02x", target, lun,
15225 inq->inq_dtype);
15226 return (DDI_FAILURE);
15227 }
15228
15229 wwn_str = kmem_zalloc(MPTSAS_WWN_STRLEN, KM_SLEEP);
15230 /* The property is needed by MPAPI */
15231 (void) sprintf(wwn_str, "%016"PRIx64, sas_wwn);
15232
15233 lun_addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP);
15234 if (guid) {
15235 (void) sprintf(lun_addr, "w%s,%x", wwn_str, lun);
15236 (void) sprintf(wwn_str, "w%016"PRIx64, sas_wwn);
15237 } else {
15238 (void) sprintf(lun_addr, "p%x,%x", phy, lun);
15239 (void) sprintf(wwn_str, "p%x", phy);
15240 }
15241
15242 mdi_rtn = mdi_pi_alloc_compatible(pdip, nodename,
15243 guid, lun_addr, compatible, ncompatible,
15244 0, pip);
15245 if (mdi_rtn == MDI_SUCCESS) {
15246
15247 if (mdi_prop_update_string(*pip, MDI_GUID,
15248 guid) != DDI_SUCCESS) {
15249 mptsas_log(mpt, CE_WARN, "mptsas driver unable to "
15250 "create prop for target %d lun %d (MDI_GUID)",
15251 target, lun);
15252 mdi_rtn = MDI_FAILURE;
15253 goto virt_create_done;
15254 }
15255
15256 if (mdi_prop_update_int(*pip, LUN_PROP,
15257 lun) != DDI_SUCCESS) {
15258 mptsas_log(mpt, CE_WARN, "mptsas driver unable to "
15259 "create prop for target %d lun %d (LUN_PROP)",
15260 target, lun);
15261 mdi_rtn = MDI_FAILURE;
15262 goto virt_create_done;
15263 }
15264 lun64 = (int64_t)lun;
15265 if (mdi_prop_update_int64(*pip, LUN64_PROP,
15266 lun64) != DDI_SUCCESS) {
15267 mptsas_log(mpt, CE_WARN, "mptsas driver unable to "
15268 "create prop for target %d (LUN64_PROP)",
15269 target);
15270 mdi_rtn = MDI_FAILURE;
15271 goto virt_create_done;
15272 }
15273 if (mdi_prop_update_string_array(*pip, "compatible",
15274 compatible, ncompatible) !=
15275 DDI_PROP_SUCCESS) {
15276 mptsas_log(mpt, CE_WARN, "mptsas driver unable to "
15277 "create prop for target %d lun %d (COMPATIBLE)",
15278 target, lun);
15279 mdi_rtn = MDI_FAILURE;
15280 goto virt_create_done;
15281 }
15282 if (sas_wwn && (mdi_prop_update_string(*pip,
15283 SCSI_ADDR_PROP_TARGET_PORT, wwn_str) != DDI_PROP_SUCCESS)) {
15284 mptsas_log(mpt, CE_WARN, "mptsas driver unable to "
15285 "create prop for target %d lun %d "
15286 "(target-port)", target, lun);
15287 mdi_rtn = MDI_FAILURE;
15288 goto virt_create_done;
15289 } else if ((sas_wwn == 0) && (mdi_prop_update_int(*pip,
15290 "sata-phy", phy) != DDI_PROP_SUCCESS)) {
15291 /*
15292 * Direct attached SATA device without DeviceName
15293 */
15294 mptsas_log(mpt, CE_WARN, "mptsas driver unable to "
15295 "create prop for SAS target %d lun %d "
15296 "(sata-phy)", target, lun);
15297 mdi_rtn = MDI_FAILURE;
15298 goto virt_create_done;
15299 }
15300 mutex_enter(&mpt->m_mutex);
15301
15302 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE &
15303 MPI2_SAS_DEVICE_PGAD_FORM_MASK) |
15304 (uint32_t)ptgt->m_devhdl;
15305 rval = mptsas_get_sas_device_page0(mpt, page_address,
15306 &dev_hdl, &dev_sas_wwn, &dev_info, &physport,
15307 &phy_id, &pdev_hdl, &bay_num, &enclosure, &io_flags);
15308 if (rval != DDI_SUCCESS) {
15309 mutex_exit(&mpt->m_mutex);
15310 mptsas_log(mpt, CE_WARN, "mptsas unable to get "
15311 "parent device for handle %d", page_address);
15312 mdi_rtn = MDI_FAILURE;
15313 goto virt_create_done;
15314 }
15315
15316 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE &
15317 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | (uint32_t)pdev_hdl;
15318 rval = mptsas_get_sas_device_page0(mpt, page_address,
15319 &dev_hdl, &pdev_sas_wwn, &pdev_info, &physport,
15320 &phy_id, &pdev_hdl, &bay_num, &enclosure, &io_flags);
15321 if (rval != DDI_SUCCESS) {
15322 mutex_exit(&mpt->m_mutex);
15323 mptsas_log(mpt, CE_WARN, "mptsas unable to get"
15324 "device info for handle %d", page_address);
15325 mdi_rtn = MDI_FAILURE;
15326 goto virt_create_done;
15327 }
15328
15329 mutex_exit(&mpt->m_mutex);
15330
15331 /*
15332 * If this device direct attached to the controller
15333 * set the attached-port to the base wwid
15334 */
15335 if ((ptgt->m_deviceinfo & DEVINFO_DIRECT_ATTACHED)
15336 != DEVINFO_DIRECT_ATTACHED) {
15337 (void) sprintf(pdev_wwn_str, "w%016"PRIx64,
15338 pdev_sas_wwn);
15339 } else {
15340 /*
15341 * Update the iport's attached-port to guid
15342 */
15343 if (sas_wwn == 0) {
15344 (void) sprintf(wwn_str, "p%x", phy);
15345 } else {
15346 (void) sprintf(wwn_str, "w%016"PRIx64, sas_wwn);
15347 }
15348 if (ddi_prop_update_string(DDI_DEV_T_NONE,
15349 pdip, SCSI_ADDR_PROP_ATTACHED_PORT, wwn_str) !=
15350 DDI_PROP_SUCCESS) {
15351 mptsas_log(mpt, CE_WARN,
15352 "mptsas unable to create "
15353 "property for iport target-port"
15354 " %s (sas_wwn)",
15355 wwn_str);
15356 mdi_rtn = MDI_FAILURE;
15357 goto virt_create_done;
15358 }
15359
15360 (void) sprintf(pdev_wwn_str, "w%016"PRIx64,
15361 mpt->un.m_base_wwid);
15362 }
15363
15364 if (mdi_prop_update_string(*pip,
15365 SCSI_ADDR_PROP_ATTACHED_PORT, pdev_wwn_str) !=
15366 DDI_PROP_SUCCESS) {
15367 mptsas_log(mpt, CE_WARN, "mptsas unable to create "
15368 "property for iport attached-port %s (sas_wwn)",
15369 attached_wwn_str);
15370 mdi_rtn = MDI_FAILURE;
15371 goto virt_create_done;
15372 }
15373
15374
15375 if (inq->inq_dtype == 0) {
15376 component = kmem_zalloc(MAXPATHLEN, KM_SLEEP);
15377 /*
15378 * set obp path for pathinfo
15379 */
15380 (void) snprintf(component, MAXPATHLEN,
15381 "disk@%s", lun_addr);
15382
15383 if (mdi_pi_pathname_obp_set(*pip, component) !=
15384 DDI_SUCCESS) {
15385 mptsas_log(mpt, CE_WARN, "mpt_sas driver "
15386 "unable to set obp-path for object %s",
15387 component);
15388 mdi_rtn = MDI_FAILURE;
15389 goto virt_create_done;
15390 }
15391 }
15392
15393 *lun_dip = MDI_PI(*pip)->pi_client->ct_dip;
15394 if (devinfo & (MPI2_SAS_DEVICE_INFO_SATA_DEVICE |
15395 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) {
15396 if ((ndi_prop_update_int(DDI_DEV_T_NONE, *lun_dip,
15397 "pm-capable", 1)) !=
15398 DDI_PROP_SUCCESS) {
15399 mptsas_log(mpt, CE_WARN, "mptsas driver"
15400 "failed to create pm-capable "
15401 "property, target %d", target);
15402 mdi_rtn = MDI_FAILURE;
15403 goto virt_create_done;
15404 }
15405 }
15406 /*
15407 * Create the phy-num property
15408 */
15409 if (mdi_prop_update_int(*pip, "phy-num",
15410 ptgt->m_phynum) != DDI_SUCCESS) {
15411 mptsas_log(mpt, CE_WARN, "mptsas driver unable to "
15412 "create phy-num property for target %d lun %d",
15413 target, lun);
15414 mdi_rtn = MDI_FAILURE;
15415 goto virt_create_done;
15416 }
15417 NDBG20(("new path:%s onlining,", MDI_PI(*pip)->pi_addr));
15418 mdi_rtn = mdi_pi_online(*pip, 0);
15419 if (mdi_rtn == MDI_SUCCESS) {
15420 mutex_enter(&mpt->m_mutex);
15421 ptgt->m_led_status = 0;
15422 (void) mptsas_flush_led_status(mpt, ptgt);
15423 mutex_exit(&mpt->m_mutex);
15424 }
15425 if (mdi_rtn == MDI_NOT_SUPPORTED) {
15426 mdi_rtn = MDI_FAILURE;
15427 }
15428 virt_create_done:
15429 if (*pip && mdi_rtn != MDI_SUCCESS) {
15430 (void) mdi_pi_free(*pip, 0);
15431 *pip = NULL;
15432 *lun_dip = NULL;
15433 }
15434 }
15435
15436 scsi_hba_nodename_compatible_free(nodename, compatible);
15437 if (lun_addr != NULL) {
15438 kmem_free(lun_addr, SCSI_MAXNAMELEN);
15439 }
15440 if (wwn_str != NULL) {
15441 kmem_free(wwn_str, MPTSAS_WWN_STRLEN);
15442 }
15443 if (component != NULL) {
15444 kmem_free(component, MAXPATHLEN);
15445 }
15446
15447 return ((mdi_rtn == MDI_SUCCESS) ? DDI_SUCCESS : DDI_FAILURE);
15448 }
15449
15450 static int
15451 mptsas_create_phys_lun(dev_info_t *pdip, struct scsi_inquiry *inq,
15452 char *guid, dev_info_t **lun_dip, mptsas_target_t *ptgt, int lun)
15453 {
15454 int target;
15455 int rval;
15456 int ndi_rtn = NDI_FAILURE;
15457 uint64_t be_sas_wwn;
15458 char *nodename = NULL;
15459 char **compatible = NULL;
15460 int ncompatible = 0;
15461 int instance = 0;
15462 mptsas_t *mpt = DIP2MPT(pdip);
15463 char *wwn_str = NULL;
15464 char *component = NULL;
15465 char *attached_wwn_str = NULL;
15466 uint8_t phy = 0xFF;
15467 uint64_t sas_wwn;
15468 uint32_t devinfo;
15469 uint16_t dev_hdl;
15470 uint16_t pdev_hdl;
15471 uint64_t pdev_sas_wwn;
15472 uint64_t dev_sas_wwn;
15473 uint32_t pdev_info;
15474 uint8_t physport;
15475 uint8_t phy_id;
15476 uint32_t page_address;
15477 uint16_t bay_num, enclosure, io_flags;
15478 char pdev_wwn_str[MPTSAS_WWN_STRLEN];
15479 uint32_t dev_info;
15480 int64_t lun64 = 0;
15481
15482 mutex_enter(&mpt->m_mutex);
15483 target = ptgt->m_devhdl;
15484 sas_wwn = ptgt->m_addr.mta_wwn;
15485 devinfo = ptgt->m_deviceinfo;
15486 phy = ptgt->m_phynum;
15487 mutex_exit(&mpt->m_mutex);
15488
15489 /*
15490 * generate compatible property with binding-set "mpt"
15491 */
15492 scsi_hba_nodename_compatible_get(inq, NULL, inq->inq_dtype, NULL,
15493 &nodename, &compatible, &ncompatible);
15494
15495 /*
15496 * if nodename can't be determined then print a message and skip it
15497 */
15498 if (nodename == NULL) {
15499 mptsas_log(mpt, CE_WARN, "mptsas found no compatible driver "
15500 "for target %d lun %d", target, lun);
15501 return (DDI_FAILURE);
15502 }
15503
15504 ndi_rtn = ndi_devi_alloc(pdip, nodename,
15505 DEVI_SID_NODEID, lun_dip);
15506
15507 /*
15508 * if lun alloc success, set props
15509 */
15510 if (ndi_rtn == NDI_SUCCESS) {
15511
15512 if (ndi_prop_update_int(DDI_DEV_T_NONE,
15513 *lun_dip, LUN_PROP, lun) !=
15514 DDI_PROP_SUCCESS) {
15515 mptsas_log(mpt, CE_WARN, "mptsas unable to create "
15516 "property for target %d lun %d (LUN_PROP)",
15517 target, lun);
15518 ndi_rtn = NDI_FAILURE;
15519 goto phys_create_done;
15520 }
15521
15522 lun64 = (int64_t)lun;
15523 if (ndi_prop_update_int64(DDI_DEV_T_NONE,
15524 *lun_dip, LUN64_PROP, lun64) !=
15525 DDI_PROP_SUCCESS) {
15526 mptsas_log(mpt, CE_WARN, "mptsas unable to create "
15527 "property for target %d lun64 %d (LUN64_PROP)",
15528 target, lun);
15529 ndi_rtn = NDI_FAILURE;
15530 goto phys_create_done;
15531 }
15532 if (ndi_prop_update_string_array(DDI_DEV_T_NONE,
15533 *lun_dip, "compatible", compatible, ncompatible)
15534 != DDI_PROP_SUCCESS) {
15535 mptsas_log(mpt, CE_WARN, "mptsas unable to create "
15536 "property for target %d lun %d (COMPATIBLE)",
15537 target, lun);
15538 ndi_rtn = NDI_FAILURE;
15539 goto phys_create_done;
15540 }
15541
15542 /*
15543 * We need the SAS WWN for non-multipath devices, so
15544 * we'll use the same property as that multipathing
15545 * devices need to present for MPAPI. If we don't have
15546 * a WWN (e.g. parallel SCSI), don't create the prop.
15547 */
15548 wwn_str = kmem_zalloc(MPTSAS_WWN_STRLEN, KM_SLEEP);
15549 (void) sprintf(wwn_str, "w%016"PRIx64, sas_wwn);
15550 if (sas_wwn && ndi_prop_update_string(DDI_DEV_T_NONE,
15551 *lun_dip, SCSI_ADDR_PROP_TARGET_PORT, wwn_str)
15552 != DDI_PROP_SUCCESS) {
15553 mptsas_log(mpt, CE_WARN, "mptsas unable to "
15554 "create property for SAS target %d lun %d "
15555 "(target-port)", target, lun);
15556 ndi_rtn = NDI_FAILURE;
15557 goto phys_create_done;
15558 }
15559
15560 be_sas_wwn = BE_64(sas_wwn);
15561 if (sas_wwn && ndi_prop_update_byte_array(
15562 DDI_DEV_T_NONE, *lun_dip, "port-wwn",
15563 (uchar_t *)&be_sas_wwn, 8) != DDI_PROP_SUCCESS) {
15564 mptsas_log(mpt, CE_WARN, "mptsas unable to "
15565 "create property for SAS target %d lun %d "
15566 "(port-wwn)", target, lun);
15567 ndi_rtn = NDI_FAILURE;
15568 goto phys_create_done;
15569 } else if ((sas_wwn == 0) && (ndi_prop_update_int(
15570 DDI_DEV_T_NONE, *lun_dip, "sata-phy", phy) !=
15571 DDI_PROP_SUCCESS)) {
15572 /*
15573 * Direct attached SATA device without DeviceName
15574 */
15575 mptsas_log(mpt, CE_WARN, "mptsas unable to "
15576 "create property for SAS target %d lun %d "
15577 "(sata-phy)", target, lun);
15578 ndi_rtn = NDI_FAILURE;
15579 goto phys_create_done;
15580 }
15581
15582 if (ndi_prop_create_boolean(DDI_DEV_T_NONE,
15583 *lun_dip, SAS_PROP) != DDI_PROP_SUCCESS) {
15584 mptsas_log(mpt, CE_WARN, "mptsas unable to"
15585 "create property for SAS target %d lun %d"
15586 " (SAS_PROP)", target, lun);
15587 ndi_rtn = NDI_FAILURE;
15588 goto phys_create_done;
15589 }
15590 if (guid && (ndi_prop_update_string(DDI_DEV_T_NONE,
15591 *lun_dip, NDI_GUID, guid) != DDI_SUCCESS)) {
15592 mptsas_log(mpt, CE_WARN, "mptsas unable "
15593 "to create guid property for target %d "
15594 "lun %d", target, lun);
15595 ndi_rtn = NDI_FAILURE;
15596 goto phys_create_done;
15597 }
15598
15599 /*
15600 * The following code is to set properties for SM-HBA support,
15601 * it doesn't apply to RAID volumes
15602 */
15603 if (ptgt->m_addr.mta_phymask == 0)
15604 goto phys_raid_lun;
15605
15606 mutex_enter(&mpt->m_mutex);
15607
15608 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE &
15609 MPI2_SAS_DEVICE_PGAD_FORM_MASK) |
15610 (uint32_t)ptgt->m_devhdl;
15611 rval = mptsas_get_sas_device_page0(mpt, page_address,
15612 &dev_hdl, &dev_sas_wwn, &dev_info,
15613 &physport, &phy_id, &pdev_hdl,
15614 &bay_num, &enclosure, &io_flags);
15615 if (rval != DDI_SUCCESS) {
15616 mutex_exit(&mpt->m_mutex);
15617 mptsas_log(mpt, CE_WARN, "mptsas unable to get"
15618 "parent device for handle %d.", page_address);
15619 ndi_rtn = NDI_FAILURE;
15620 goto phys_create_done;
15621 }
15622
15623 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE &
15624 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | (uint32_t)pdev_hdl;
15625 rval = mptsas_get_sas_device_page0(mpt, page_address,
15626 &dev_hdl, &pdev_sas_wwn, &pdev_info, &physport,
15627 &phy_id, &pdev_hdl, &bay_num, &enclosure, &io_flags);
15628 if (rval != DDI_SUCCESS) {
15629 mutex_exit(&mpt->m_mutex);
15630 mptsas_log(mpt, CE_WARN, "mptsas unable to create "
15631 "device for handle %d.", page_address);
15632 ndi_rtn = NDI_FAILURE;
15633 goto phys_create_done;
15634 }
15635
15636 mutex_exit(&mpt->m_mutex);
15637
15638 /*
15639 * If this device direct attached to the controller
15640 * set the attached-port to the base wwid
15641 */
15642 if ((ptgt->m_deviceinfo & DEVINFO_DIRECT_ATTACHED)
15643 != DEVINFO_DIRECT_ATTACHED) {
15644 (void) sprintf(pdev_wwn_str, "w%016"PRIx64,
15645 pdev_sas_wwn);
15646 } else {
15647 /*
15648 * Update the iport's attached-port to guid
15649 */
15650 if (sas_wwn == 0) {
15651 (void) sprintf(wwn_str, "p%x", phy);
15652 } else {
15653 (void) sprintf(wwn_str, "w%016"PRIx64, sas_wwn);
15654 }
15655 if (ddi_prop_update_string(DDI_DEV_T_NONE,
15656 pdip, SCSI_ADDR_PROP_ATTACHED_PORT, wwn_str) !=
15657 DDI_PROP_SUCCESS) {
15658 mptsas_log(mpt, CE_WARN,
15659 "mptsas unable to create "
15660 "property for iport target-port"
15661 " %s (sas_wwn)",
15662 wwn_str);
15663 ndi_rtn = NDI_FAILURE;
15664 goto phys_create_done;
15665 }
15666
15667 (void) sprintf(pdev_wwn_str, "w%016"PRIx64,
15668 mpt->un.m_base_wwid);
15669 }
15670
15671 if (ndi_prop_update_string(DDI_DEV_T_NONE,
15672 *lun_dip, SCSI_ADDR_PROP_ATTACHED_PORT, pdev_wwn_str) !=
15673 DDI_PROP_SUCCESS) {
15674 mptsas_log(mpt, CE_WARN,
15675 "mptsas unable to create "
15676 "property for iport attached-port %s (sas_wwn)",
15677 attached_wwn_str);
15678 ndi_rtn = NDI_FAILURE;
15679 goto phys_create_done;
15680 }
15681
15682 if (IS_SATA_DEVICE(dev_info)) {
15683 if (ndi_prop_update_string(DDI_DEV_T_NONE,
15684 *lun_dip, MPTSAS_VARIANT, "sata") !=
15685 DDI_PROP_SUCCESS) {
15686 mptsas_log(mpt, CE_WARN,
15687 "mptsas unable to create "
15688 "property for device variant ");
15689 ndi_rtn = NDI_FAILURE;
15690 goto phys_create_done;
15691 }
15692 }
15693
15694 if (IS_ATAPI_DEVICE(dev_info)) {
15695 if (ndi_prop_update_string(DDI_DEV_T_NONE,
15696 *lun_dip, MPTSAS_VARIANT, "atapi") !=
15697 DDI_PROP_SUCCESS) {
15698 mptsas_log(mpt, CE_WARN,
15699 "mptsas unable to create "
15700 "property for device variant ");
15701 ndi_rtn = NDI_FAILURE;
15702 goto phys_create_done;
15703 }
15704 }
15705
15706 phys_raid_lun:
15707 /*
15708 * if this is a SAS controller, and the target is a SATA
15709 * drive, set the 'pm-capable' property for sd and if on
15710 * an OPL platform, also check if this is an ATAPI
15711 * device.
15712 */
15713 instance = ddi_get_instance(mpt->m_dip);
15714 if (devinfo & (MPI2_SAS_DEVICE_INFO_SATA_DEVICE |
15715 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) {
15716 NDBG2(("mptsas%d: creating pm-capable property, "
15717 "target %d", instance, target));
15718
15719 if ((ndi_prop_update_int(DDI_DEV_T_NONE,
15720 *lun_dip, "pm-capable", 1)) !=
15721 DDI_PROP_SUCCESS) {
15722 mptsas_log(mpt, CE_WARN, "mptsas "
15723 "failed to create pm-capable "
15724 "property, target %d", target);
15725 ndi_rtn = NDI_FAILURE;
15726 goto phys_create_done;
15727 }
15728
15729 }
15730
15731 if ((inq->inq_dtype == 0) || (inq->inq_dtype == 5)) {
15732 /*
15733 * add 'obp-path' properties for devinfo
15734 */
15735 bzero(wwn_str, sizeof (wwn_str));
15736 (void) sprintf(wwn_str, "%016"PRIx64, sas_wwn);
15737 component = kmem_zalloc(MAXPATHLEN, KM_SLEEP);
15738 if (guid) {
15739 (void) snprintf(component, MAXPATHLEN,
15740 "disk@w%s,%x", wwn_str, lun);
15741 } else {
15742 (void) snprintf(component, MAXPATHLEN,
15743 "disk@p%x,%x", phy, lun);
15744 }
15745 if (ddi_pathname_obp_set(*lun_dip, component)
15746 != DDI_SUCCESS) {
15747 mptsas_log(mpt, CE_WARN, "mpt_sas driver "
15748 "unable to set obp-path for SAS "
15749 "object %s", component);
15750 ndi_rtn = NDI_FAILURE;
15751 goto phys_create_done;
15752 }
15753 }
15754 /*
15755 * Create the phy-num property for non-raid disk
15756 */
15757 if (ptgt->m_addr.mta_phymask != 0) {
15758 if (ndi_prop_update_int(DDI_DEV_T_NONE,
15759 *lun_dip, "phy-num", ptgt->m_phynum) !=
15760 DDI_PROP_SUCCESS) {
15761 mptsas_log(mpt, CE_WARN, "mptsas driver "
15762 "failed to create phy-num property for "
15763 "target %d", target);
15764 ndi_rtn = NDI_FAILURE;
15765 goto phys_create_done;
15766 }
15767 }
15768 phys_create_done:
15769 /*
15770 * If props were setup ok, online the lun
15771 */
15772 if (ndi_rtn == NDI_SUCCESS) {
15773 /*
15774 * Try to online the new node
15775 */
15776 ndi_rtn = ndi_devi_online(*lun_dip, NDI_ONLINE_ATTACH);
15777 }
15778 if (ndi_rtn == NDI_SUCCESS) {
15779 mutex_enter(&mpt->m_mutex);
15780 ptgt->m_led_status = 0;
15781 (void) mptsas_flush_led_status(mpt, ptgt);
15782 mutex_exit(&mpt->m_mutex);
15783 }
15784
15785 /*
15786 * If success set rtn flag, else unwire alloc'd lun
15787 */
15788 if (ndi_rtn != NDI_SUCCESS) {
15789 NDBG12(("mptsas driver unable to online "
15790 "target %d lun %d", target, lun));
15791 ndi_prop_remove_all(*lun_dip);
15792 (void) ndi_devi_free(*lun_dip);
15793 *lun_dip = NULL;
15794 }
15795 }
15796
15797 scsi_hba_nodename_compatible_free(nodename, compatible);
15798
15799 if (wwn_str != NULL) {
15800 kmem_free(wwn_str, MPTSAS_WWN_STRLEN);
15801 }
15802 if (component != NULL) {
15803 kmem_free(component, MAXPATHLEN);
15804 }
15805
15806
15807 return ((ndi_rtn == NDI_SUCCESS) ? DDI_SUCCESS : DDI_FAILURE);
15808 }
15809
15810 static int
15811 mptsas_probe_smp(dev_info_t *pdip, uint64_t wwn)
15812 {
15813 mptsas_t *mpt = DIP2MPT(pdip);
15814 struct smp_device smp_sd;
15815
15816 /* XXX An HBA driver should not be allocating an smp_device. */
15817 bzero(&smp_sd, sizeof (struct smp_device));
15818 smp_sd.smp_sd_address.smp_a_hba_tran = mpt->m_smptran;
15819 bcopy(&wwn, smp_sd.smp_sd_address.smp_a_wwn, SAS_WWN_BYTE_SIZE);
15820
15821 if (smp_probe(&smp_sd) != DDI_PROBE_SUCCESS)
15822 return (NDI_FAILURE);
15823 return (NDI_SUCCESS);
15824 }
15825
15826 static int
15827 mptsas_config_smp(dev_info_t *pdip, uint64_t sas_wwn, dev_info_t **smp_dip)
15828 {
15829 mptsas_t *mpt = DIP2MPT(pdip);
15830 mptsas_smp_t *psmp = NULL;
15831 int rval;
15832 int phymask;
15833
15834 /*
15835 * Get the physical port associated to the iport
15836 * PHYMASK TODO
15837 */
15838 phymask = ddi_prop_get_int(DDI_DEV_T_ANY, pdip, 0,
15839 "phymask", 0);
15840 /*
15841 * Find the smp node in hash table with specified sas address and
15842 * physical port
15843 */
15844 psmp = mptsas_wwid_to_psmp(mpt, phymask, sas_wwn);
15845 if (psmp == NULL) {
15846 return (DDI_FAILURE);
15847 }
15848
15849 rval = mptsas_online_smp(pdip, psmp, smp_dip);
15850
15851 return (rval);
15852 }
15853
15854 static int
15855 mptsas_online_smp(dev_info_t *pdip, mptsas_smp_t *smp_node,
15856 dev_info_t **smp_dip)
15857 {
15858 char wwn_str[MPTSAS_WWN_STRLEN];
15859 char attached_wwn_str[MPTSAS_WWN_STRLEN];
15860 int ndi_rtn = NDI_FAILURE;
15861 int rval = 0;
15862 mptsas_smp_t dev_info;
15863 uint32_t page_address;
15864 mptsas_t *mpt = DIP2MPT(pdip);
15865 uint16_t dev_hdl;
15866 uint64_t sas_wwn;
15867 uint64_t smp_sas_wwn;
15868 uint8_t physport;
15869 uint8_t phy_id;
15870 uint16_t pdev_hdl;
15871 uint8_t numphys = 0;
15872 uint16_t i = 0;
15873 char phymask[MPTSAS_MAX_PHYS];
15874 char *iport = NULL;
15875 mptsas_phymask_t phy_mask = 0;
15876 uint16_t attached_devhdl;
15877 uint16_t bay_num, enclosure, io_flags;
15878
15879 (void) sprintf(wwn_str, "%"PRIx64, smp_node->m_addr.mta_wwn);
15880
15881 /*
15882 * Probe smp device, prevent the node of removed device from being
15883 * configured succesfully
15884 */
15885 if (mptsas_probe_smp(pdip, smp_node->m_addr.mta_wwn) != NDI_SUCCESS) {
15886 return (DDI_FAILURE);
15887 }
15888
15889 if ((*smp_dip = mptsas_find_smp_child(pdip, wwn_str)) != NULL) {
15890 return (DDI_SUCCESS);
15891 }
15892
15893 ndi_rtn = ndi_devi_alloc(pdip, "smp", DEVI_SID_NODEID, smp_dip);
15894
15895 /*
15896 * if lun alloc success, set props
15897 */
15898 if (ndi_rtn == NDI_SUCCESS) {
15899 /*
15900 * Set the flavor of the child to be SMP flavored
15901 */
15902 ndi_flavor_set(*smp_dip, SCSA_FLAVOR_SMP);
15903
15904 if (ndi_prop_update_string(DDI_DEV_T_NONE,
15905 *smp_dip, SMP_WWN, wwn_str) !=
15906 DDI_PROP_SUCCESS) {
15907 mptsas_log(mpt, CE_WARN, "mptsas unable to create "
15908 "property for smp device %s (sas_wwn)",
15909 wwn_str);
15910 ndi_rtn = NDI_FAILURE;
15911 goto smp_create_done;
15912 }
15913 (void) sprintf(wwn_str, "w%"PRIx64, smp_node->m_addr.mta_wwn);
15914 if (ndi_prop_update_string(DDI_DEV_T_NONE,
15915 *smp_dip, SCSI_ADDR_PROP_TARGET_PORT, wwn_str) !=
15916 DDI_PROP_SUCCESS) {
15917 mptsas_log(mpt, CE_WARN, "mptsas unable to create "
15918 "property for iport target-port %s (sas_wwn)",
15919 wwn_str);
15920 ndi_rtn = NDI_FAILURE;
15921 goto smp_create_done;
15922 }
15923
15924 mutex_enter(&mpt->m_mutex);
15925
15926 page_address = (MPI2_SAS_EXPAND_PGAD_FORM_HNDL &
15927 MPI2_SAS_EXPAND_PGAD_FORM_MASK) | smp_node->m_devhdl;
15928 rval = mptsas_get_sas_expander_page0(mpt, page_address,
15929 &dev_info);
15930 if (rval != DDI_SUCCESS) {
15931 mutex_exit(&mpt->m_mutex);
15932 mptsas_log(mpt, CE_WARN,
15933 "mptsas unable to get expander "
15934 "parent device info for %x", page_address);
15935 ndi_rtn = NDI_FAILURE;
15936 goto smp_create_done;
15937 }
15938
15939 smp_node->m_pdevhdl = dev_info.m_pdevhdl;
15940 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE &
15941 MPI2_SAS_DEVICE_PGAD_FORM_MASK) |
15942 (uint32_t)dev_info.m_pdevhdl;
15943 rval = mptsas_get_sas_device_page0(mpt, page_address,
15944 &dev_hdl, &sas_wwn, &smp_node->m_pdevinfo, &physport,
15945 &phy_id, &pdev_hdl, &bay_num, &enclosure, &io_flags);
15946 if (rval != DDI_SUCCESS) {
15947 mutex_exit(&mpt->m_mutex);
15948 mptsas_log(mpt, CE_WARN, "mptsas unable to get "
15949 "device info for %x", page_address);
15950 ndi_rtn = NDI_FAILURE;
15951 goto smp_create_done;
15952 }
15953
15954 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE &
15955 MPI2_SAS_DEVICE_PGAD_FORM_MASK) |
15956 (uint32_t)dev_info.m_devhdl;
15957 rval = mptsas_get_sas_device_page0(mpt, page_address,
15958 &dev_hdl, &smp_sas_wwn, &smp_node->m_deviceinfo,
15959 &physport, &phy_id, &pdev_hdl, &bay_num, &enclosure,
15960 &io_flags);
15961 if (rval != DDI_SUCCESS) {
15962 mutex_exit(&mpt->m_mutex);
15963 mptsas_log(mpt, CE_WARN, "mptsas unable to get "
15964 "device info for %x", page_address);
15965 ndi_rtn = NDI_FAILURE;
15966 goto smp_create_done;
15967 }
15968 mutex_exit(&mpt->m_mutex);
15969
15970 /*
15971 * If this smp direct attached to the controller
15972 * set the attached-port to the base wwid
15973 */
15974 if ((smp_node->m_deviceinfo & DEVINFO_DIRECT_ATTACHED)
15975 != DEVINFO_DIRECT_ATTACHED) {
15976 (void) sprintf(attached_wwn_str, "w%016"PRIx64,
15977 sas_wwn);
15978 } else {
15979 (void) sprintf(attached_wwn_str, "w%016"PRIx64,
15980 mpt->un.m_base_wwid);
15981 }
15982
15983 if (ndi_prop_update_string(DDI_DEV_T_NONE,
15984 *smp_dip, SCSI_ADDR_PROP_ATTACHED_PORT, attached_wwn_str) !=
15985 DDI_PROP_SUCCESS) {
15986 mptsas_log(mpt, CE_WARN, "mptsas unable to create "
15987 "property for smp attached-port %s (sas_wwn)",
15988 attached_wwn_str);
15989 ndi_rtn = NDI_FAILURE;
15990 goto smp_create_done;
15991 }
15992
15993 if (ndi_prop_create_boolean(DDI_DEV_T_NONE,
15994 *smp_dip, SMP_PROP) != DDI_PROP_SUCCESS) {
15995 mptsas_log(mpt, CE_WARN, "mptsas unable to "
15996 "create property for SMP %s (SMP_PROP) ",
15997 wwn_str);
15998 ndi_rtn = NDI_FAILURE;
15999 goto smp_create_done;
16000 }
16001
16002 /*
16003 * check the smp to see whether it direct
16004 * attached to the controller
16005 */
16006 if ((smp_node->m_deviceinfo & DEVINFO_DIRECT_ATTACHED)
16007 != DEVINFO_DIRECT_ATTACHED) {
16008 goto smp_create_done;
16009 }
16010 numphys = ddi_prop_get_int(DDI_DEV_T_ANY, pdip,
16011 DDI_PROP_DONTPASS, MPTSAS_NUM_PHYS, -1);
16012 if (numphys > 0) {
16013 goto smp_create_done;
16014 }
16015 /*
16016 * this iport is an old iport, we need to
16017 * reconfig the props for it.
16018 */
16019 if (ddi_prop_update_int(DDI_DEV_T_NONE, pdip,
16020 MPTSAS_VIRTUAL_PORT, 0) !=
16021 DDI_PROP_SUCCESS) {
16022 (void) ddi_prop_remove(DDI_DEV_T_NONE, pdip,
16023 MPTSAS_VIRTUAL_PORT);
16024 mptsas_log(mpt, CE_WARN, "mptsas virtual port "
16025 "prop update failed");
16026 goto smp_create_done;
16027 }
16028
16029 mutex_enter(&mpt->m_mutex);
16030 numphys = 0;
16031 iport = ddi_get_name_addr(pdip);
16032 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
16033 bzero(phymask, sizeof (phymask));
16034 (void) sprintf(phymask,
16035 "%x", mpt->m_phy_info[i].phy_mask);
16036 if (strcmp(phymask, iport) == 0) {
16037 phy_mask = mpt->m_phy_info[i].phy_mask;
16038 break;
16039 }
16040 }
16041
16042 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
16043 if ((phy_mask >> i) & 0x01) {
16044 numphys++;
16045 }
16046 }
16047 /*
16048 * Update PHY info for smhba
16049 */
16050 if (mptsas_smhba_phy_init(mpt)) {
16051 mutex_exit(&mpt->m_mutex);
16052 mptsas_log(mpt, CE_WARN, "mptsas phy update "
16053 "failed");
16054 goto smp_create_done;
16055 }
16056 mutex_exit(&mpt->m_mutex);
16057
16058 mptsas_smhba_set_all_phy_props(mpt, pdip, numphys, phy_mask,
16059 &attached_devhdl);
16060
16061 if (ddi_prop_update_int(DDI_DEV_T_NONE, pdip,
16062 MPTSAS_NUM_PHYS, numphys) !=
16063 DDI_PROP_SUCCESS) {
16064 (void) ddi_prop_remove(DDI_DEV_T_NONE, pdip,
16065 MPTSAS_NUM_PHYS);
16066 mptsas_log(mpt, CE_WARN, "mptsas update "
16067 "num phys props failed");
16068 goto smp_create_done;
16069 }
16070 /*
16071 * Add parent's props for SMHBA support
16072 */
16073 if (ddi_prop_update_string(DDI_DEV_T_NONE, pdip,
16074 SCSI_ADDR_PROP_ATTACHED_PORT, wwn_str) !=
16075 DDI_PROP_SUCCESS) {
16076 (void) ddi_prop_remove(DDI_DEV_T_NONE, pdip,
16077 SCSI_ADDR_PROP_ATTACHED_PORT);
16078 mptsas_log(mpt, CE_WARN, "mptsas update iport"
16079 "attached-port failed");
16080 goto smp_create_done;
16081 }
16082
16083 smp_create_done:
16084 /*
16085 * If props were setup ok, online the lun
16086 */
16087 if (ndi_rtn == NDI_SUCCESS) {
16088 /*
16089 * Try to online the new node
16090 */
16091 ndi_rtn = ndi_devi_online(*smp_dip, NDI_ONLINE_ATTACH);
16092 }
16093
16094 /*
16095 * If success set rtn flag, else unwire alloc'd lun
16096 */
16097 if (ndi_rtn != NDI_SUCCESS) {
16098 NDBG12(("mptsas unable to online "
16099 "SMP target %s", wwn_str));
16100 ndi_prop_remove_all(*smp_dip);
16101 (void) ndi_devi_free(*smp_dip);
16102 }
16103 }
16104
16105 return ((ndi_rtn == NDI_SUCCESS) ? DDI_SUCCESS : DDI_FAILURE);
16106 }
16107
16108 /* smp transport routine */
16109 static int mptsas_smp_start(struct smp_pkt *smp_pkt)
16110 {
16111 uint64_t wwn;
16112 Mpi2SmpPassthroughRequest_t req;
16113 Mpi2SmpPassthroughReply_t rep;
16114 uint32_t direction = 0;
16115 mptsas_t *mpt;
16116 int ret;
16117 uint64_t tmp64;
16118
16119 mpt = (mptsas_t *)smp_pkt->smp_pkt_address->
16120 smp_a_hba_tran->smp_tran_hba_private;
16121
16122 bcopy(smp_pkt->smp_pkt_address->smp_a_wwn, &wwn, SAS_WWN_BYTE_SIZE);
16123 /*
16124 * Need to compose a SMP request message
16125 * and call mptsas_do_passthru() function
16126 */
16127 bzero(&req, sizeof (req));
16128 bzero(&rep, sizeof (rep));
16129 req.PassthroughFlags = 0;
16130 req.PhysicalPort = 0xff;
16131 req.ChainOffset = 0;
16132 req.Function = MPI2_FUNCTION_SMP_PASSTHROUGH;
16133
16134 if ((smp_pkt->smp_pkt_reqsize & 0xffff0000ul) != 0) {
16135 smp_pkt->smp_pkt_reason = ERANGE;
16136 return (DDI_FAILURE);
16137 }
16138 req.RequestDataLength = LE_16((uint16_t)(smp_pkt->smp_pkt_reqsize - 4));
16139
16140 req.MsgFlags = 0;
16141 tmp64 = LE_64(wwn);
16142 bcopy(&tmp64, &req.SASAddress, SAS_WWN_BYTE_SIZE);
16143 if (smp_pkt->smp_pkt_rspsize > 0) {
16144 direction |= MPTSAS_PASS_THRU_DIRECTION_READ;
16145 }
16146 if (smp_pkt->smp_pkt_reqsize > 0) {
16147 direction |= MPTSAS_PASS_THRU_DIRECTION_WRITE;
16148 }
16149
16150 mutex_enter(&mpt->m_mutex);
16151 ret = mptsas_do_passthru(mpt, (uint8_t *)&req, (uint8_t *)&rep,
16152 (uint8_t *)smp_pkt->smp_pkt_rsp,
16153 offsetof(Mpi2SmpPassthroughRequest_t, SGL), sizeof (rep),
16154 smp_pkt->smp_pkt_rspsize - 4, direction,
16155 (uint8_t *)smp_pkt->smp_pkt_req, smp_pkt->smp_pkt_reqsize - 4,
16156 smp_pkt->smp_pkt_timeout, FKIOCTL);
16157 mutex_exit(&mpt->m_mutex);
16158 if (ret != 0) {
16159 cmn_err(CE_WARN, "smp_start do passthru error %d", ret);
16160 smp_pkt->smp_pkt_reason = (uchar_t)(ret);
16161 return (DDI_FAILURE);
16162 }
16163 /* do passthrough success, check the smp status */
16164 if (LE_16(rep.IOCStatus) != MPI2_IOCSTATUS_SUCCESS) {
16165 switch (LE_16(rep.IOCStatus)) {
16166 case MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE:
16167 smp_pkt->smp_pkt_reason = ENODEV;
16168 break;
16169 case MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN:
16170 smp_pkt->smp_pkt_reason = EOVERFLOW;
16171 break;
16172 case MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED:
16173 smp_pkt->smp_pkt_reason = EIO;
16174 break;
16175 default:
16176 mptsas_log(mpt, CE_NOTE, "smp_start: get unknown ioc"
16177 "status:%x", LE_16(rep.IOCStatus));
16178 smp_pkt->smp_pkt_reason = EIO;
16179 break;
16180 }
16181 return (DDI_FAILURE);
16182 }
16183 if (rep.SASStatus != MPI2_SASSTATUS_SUCCESS) {
16184 mptsas_log(mpt, CE_NOTE, "smp_start: get error SAS status:%x",
16185 rep.SASStatus);
16186 smp_pkt->smp_pkt_reason = EIO;
16187 return (DDI_FAILURE);
16188 }
16189
16190 return (DDI_SUCCESS);
16191 }
16192
16193 /*
16194 * If we didn't get a match, we need to get sas page0 for each device, and
16195 * untill we get a match. If failed, return NULL
16196 */
16197 static mptsas_target_t *
16198 mptsas_phy_to_tgt(mptsas_t *mpt, mptsas_phymask_t phymask, uint8_t phy)
16199 {
16200 int i, j = 0;
16201 int rval = 0;
16202 uint16_t cur_handle;
16203 uint32_t page_address;
16204 mptsas_target_t *ptgt = NULL;
16205
16206 /*
16207 * PHY named device must be direct attached and attaches to
16208 * narrow port, if the iport is not parent of the device which
16209 * we are looking for.
16210 */
16211 for (i = 0; i < MPTSAS_MAX_PHYS; i++) {
16212 if ((1 << i) & phymask)
16213 j++;
16214 }
16215
16216 if (j > 1)
16217 return (NULL);
16218
16219 /*
16220 * Must be a narrow port and single device attached to the narrow port
16221 * So the physical port num of device which is equal to the iport's
16222 * port num is the device what we are looking for.
16223 */
16224
16225 if (mpt->m_phy_info[phy].phy_mask != phymask)
16226 return (NULL);
16227
16228 mutex_enter(&mpt->m_mutex);
16229
16230 ptgt = refhash_linear_search(mpt->m_targets, mptsas_target_eval_nowwn,
16231 &phy);
16232 if (ptgt != NULL) {
16233 mutex_exit(&mpt->m_mutex);
16234 return (ptgt);
16235 }
16236
16237 if (mpt->m_done_traverse_dev) {
16238 mutex_exit(&mpt->m_mutex);
16239 return (NULL);
16240 }
16241
16242 /* If didn't get a match, come here */
16243 cur_handle = mpt->m_dev_handle;
16244 for (; ; ) {
16245 ptgt = NULL;
16246 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE &
16247 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | (uint32_t)cur_handle;
16248 rval = mptsas_get_target_device_info(mpt, page_address,
16249 &cur_handle, &ptgt);
16250 if ((rval == DEV_INFO_FAIL_PAGE0) ||
16251 (rval == DEV_INFO_FAIL_ALLOC) ||
16252 (rval == DEV_INFO_FAIL_GUID)) {
16253 break;
16254 }
16255 if ((rval == DEV_INFO_WRONG_DEVICE_TYPE) ||
16256 (rval == DEV_INFO_PHYS_DISK)) {
16257 continue;
16258 }
16259 mpt->m_dev_handle = cur_handle;
16260
16261 if ((ptgt->m_addr.mta_wwn == 0) && (ptgt->m_phynum == phy)) {
16262 break;
16263 }
16264 }
16265
16266 mutex_exit(&mpt->m_mutex);
16267 return (ptgt);
16268 }
16269
16270 /*
16271 * The ptgt->m_addr.mta_wwn contains the wwid for each disk.
16272 * For Raid volumes, we need to check m_raidvol[x].m_raidwwid
16273 * If we didn't get a match, we need to get sas page0 for each device, and
16274 * untill we get a match
16275 * If failed, return NULL
16276 */
16277 static mptsas_target_t *
16278 mptsas_wwid_to_ptgt(mptsas_t *mpt, mptsas_phymask_t phymask, uint64_t wwid)
16279 {
16280 int rval = 0;
16281 uint16_t cur_handle;
16282 uint32_t page_address;
16283 mptsas_target_t *tmp_tgt = NULL;
16284 mptsas_target_addr_t addr;
16285
16286 addr.mta_wwn = wwid;
16287 addr.mta_phymask = phymask;
16288 mutex_enter(&mpt->m_mutex);
16289 tmp_tgt = refhash_lookup(mpt->m_targets, &addr);
16290 if (tmp_tgt != NULL) {
16291 mutex_exit(&mpt->m_mutex);
16292 return (tmp_tgt);
16293 }
16294
16295 if (phymask == 0) {
16296 /*
16297 * It's IR volume
16298 */
16299 rval = mptsas_get_raid_info(mpt);
16300 if (rval) {
16301 tmp_tgt = refhash_lookup(mpt->m_targets, &addr);
16302 }
16303 mutex_exit(&mpt->m_mutex);
16304 return (tmp_tgt);
16305 }
16306
16307 if (mpt->m_done_traverse_dev) {
16308 mutex_exit(&mpt->m_mutex);
16309 return (NULL);
16310 }
16311
16312 /* If didn't get a match, come here */
16313 cur_handle = mpt->m_dev_handle;
16314 for (;;) {
16315 tmp_tgt = NULL;
16316 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE &
16317 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | cur_handle;
16318 rval = mptsas_get_target_device_info(mpt, page_address,
16319 &cur_handle, &tmp_tgt);
16320 if ((rval == DEV_INFO_FAIL_PAGE0) ||
16321 (rval == DEV_INFO_FAIL_ALLOC) ||
16322 (rval == DEV_INFO_FAIL_GUID)) {
16323 tmp_tgt = NULL;
16324 break;
16325 }
16326 if ((rval == DEV_INFO_WRONG_DEVICE_TYPE) ||
16327 (rval == DEV_INFO_PHYS_DISK)) {
16328 continue;
16329 }
16330 mpt->m_dev_handle = cur_handle;
16331 if ((tmp_tgt->m_addr.mta_wwn) &&
16332 (tmp_tgt->m_addr.mta_wwn == wwid) &&
16333 (tmp_tgt->m_addr.mta_phymask == phymask)) {
16334 break;
16335 }
16336 }
16337
16338 mutex_exit(&mpt->m_mutex);
16339 return (tmp_tgt);
16340 }
16341
16342 static mptsas_smp_t *
16343 mptsas_wwid_to_psmp(mptsas_t *mpt, mptsas_phymask_t phymask, uint64_t wwid)
16344 {
16345 int rval = 0;
16346 uint16_t cur_handle;
16347 uint32_t page_address;
16348 mptsas_smp_t smp_node, *psmp = NULL;
16349 mptsas_target_addr_t addr;
16350
16351 addr.mta_wwn = wwid;
16352 addr.mta_phymask = phymask;
16353 mutex_enter(&mpt->m_mutex);
16354 psmp = refhash_lookup(mpt->m_smp_targets, &addr);
16355 if (psmp != NULL) {
16356 mutex_exit(&mpt->m_mutex);
16357 return (psmp);
16358 }
16359
16360 if (mpt->m_done_traverse_smp) {
16361 mutex_exit(&mpt->m_mutex);
16362 return (NULL);
16363 }
16364
16365 /* If didn't get a match, come here */
16366 cur_handle = mpt->m_smp_devhdl;
16367 for (;;) {
16368 psmp = NULL;
16369 page_address = (MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL &
16370 MPI2_SAS_EXPAND_PGAD_FORM_MASK) | (uint32_t)cur_handle;
16371 rval = mptsas_get_sas_expander_page0(mpt, page_address,
16372 &smp_node);
16373 if (rval != DDI_SUCCESS) {
16374 break;
16375 }
16376 mpt->m_smp_devhdl = cur_handle = smp_node.m_devhdl;
16377 psmp = mptsas_smp_alloc(mpt, &smp_node);
16378 ASSERT(psmp);
16379 if ((psmp->m_addr.mta_wwn) && (psmp->m_addr.mta_wwn == wwid) &&
16380 (psmp->m_addr.mta_phymask == phymask)) {
16381 break;
16382 }
16383 }
16384
16385 mutex_exit(&mpt->m_mutex);
16386 return (psmp);
16387 }
16388
16389 mptsas_target_t *
16390 mptsas_tgt_alloc(refhash_t *refhash, uint16_t devhdl, uint64_t wwid,
16391 uint32_t devinfo, mptsas_phymask_t phymask, uint8_t phynum)
16392 {
16393 mptsas_target_t *tmp_tgt = NULL;
16394 mptsas_target_addr_t addr;
16395
16396 addr.mta_wwn = wwid;
16397 addr.mta_phymask = phymask;
16398 tmp_tgt = refhash_lookup(refhash, &addr);
16399 if (tmp_tgt != NULL) {
16400 NDBG20(("Hash item already exist"));
16401 tmp_tgt->m_deviceinfo = devinfo;
16402 tmp_tgt->m_devhdl = devhdl; /* XXX - duplicate? */
16403 return (tmp_tgt);
16404 }
16405 tmp_tgt = kmem_zalloc(sizeof (struct mptsas_target), KM_SLEEP);
16406 if (tmp_tgt == NULL) {
16407 cmn_err(CE_WARN, "Fatal, allocated tgt failed");
16408 return (NULL);
16409 }
16410 tmp_tgt->m_devhdl = devhdl;
16411 tmp_tgt->m_addr.mta_wwn = wwid;
16412 tmp_tgt->m_deviceinfo = devinfo;
16413 tmp_tgt->m_addr.mta_phymask = phymask;
16414 tmp_tgt->m_phynum = phynum;
16415 /* Initialized the tgt structure */
16416 tmp_tgt->m_qfull_retries = QFULL_RETRIES;
16417 tmp_tgt->m_qfull_retry_interval =
16418 drv_usectohz(QFULL_RETRY_INTERVAL * 1000);
16419 tmp_tgt->m_t_throttle = MAX_THROTTLE;
16420 TAILQ_INIT(&tmp_tgt->m_active_cmdq);
16421
16422 refhash_insert(refhash, tmp_tgt);
16423
16424 return (tmp_tgt);
16425 }
16426
16427 static void
16428 mptsas_smp_target_copy(mptsas_smp_t *src, mptsas_smp_t *dst)
16429 {
16430 dst->m_devhdl = src->m_devhdl;
16431 dst->m_deviceinfo = src->m_deviceinfo;
16432 dst->m_pdevhdl = src->m_pdevhdl;
16433 dst->m_pdevinfo = src->m_pdevinfo;
16434 }
16435
16436 static mptsas_smp_t *
16437 mptsas_smp_alloc(mptsas_t *mpt, mptsas_smp_t *data)
16438 {
16439 mptsas_target_addr_t addr;
16440 mptsas_smp_t *ret_data;
16441
16442 addr.mta_wwn = data->m_addr.mta_wwn;
16443 addr.mta_phymask = data->m_addr.mta_phymask;
16444 ret_data = refhash_lookup(mpt->m_smp_targets, &addr);
16445 /*
16446 * If there's already a matching SMP target, update its fields
16447 * in place. Since the address is not changing, it's safe to do
16448 * this. We cannot just bcopy() here because the structure we've
16449 * been given has invalid hash links.
16450 */
16451 if (ret_data != NULL) {
16452 mptsas_smp_target_copy(data, ret_data);
16453 return (ret_data);
16454 }
16455
16456 ret_data = kmem_alloc(sizeof (mptsas_smp_t), KM_SLEEP);
16457 bcopy(data, ret_data, sizeof (mptsas_smp_t));
16458 refhash_insert(mpt->m_smp_targets, ret_data);
16459 return (ret_data);
16460 }
16461
16462 /*
16463 * Functions for SGPIO LED support
16464 */
16465 static dev_info_t *
16466 mptsas_get_dip_from_dev(dev_t dev, mptsas_phymask_t *phymask)
16467 {
16468 dev_info_t *dip;
16469 int prop;
16470 dip = e_ddi_hold_devi_by_dev(dev, 0);
16471 if (dip == NULL)
16472 return (dip);
16473 prop = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 0,
16474 "phymask", 0);
16475 *phymask = (mptsas_phymask_t)prop;
16476 ddi_release_devi(dip);
16477 return (dip);
16478 }
16479 static mptsas_target_t *
16480 mptsas_addr_to_ptgt(mptsas_t *mpt, char *addr, mptsas_phymask_t phymask)
16481 {
16482 uint8_t phynum;
16483 uint64_t wwn;
16484 int lun;
16485 mptsas_target_t *ptgt = NULL;
16486
16487 if (mptsas_parse_address(addr, &wwn, &phynum, &lun) != DDI_SUCCESS) {
16488 return (NULL);
16489 }
16490 if (addr[0] == 'w') {
16491 ptgt = mptsas_wwid_to_ptgt(mpt, (int)phymask, wwn);
16492 } else {
16493 ptgt = mptsas_phy_to_tgt(mpt, (int)phymask, phynum);
16494 }
16495 return (ptgt);
16496 }
16497
16498 static int
16499 mptsas_flush_led_status(mptsas_t *mpt, mptsas_target_t *ptgt)
16500 {
16501 uint32_t slotstatus = 0;
16502
16503 /* Build an MPI2 Slot Status based on our view of the world */
16504 if (ptgt->m_led_status & (1 << (MPTSAS_LEDCTL_LED_IDENT - 1)))
16505 slotstatus |= MPI2_SEP_REQ_SLOTSTATUS_IDENTIFY_REQUEST;
16506 if (ptgt->m_led_status & (1 << (MPTSAS_LEDCTL_LED_FAIL - 1)))
16507 slotstatus |= MPI2_SEP_REQ_SLOTSTATUS_PREDICTED_FAULT;
16508 if (ptgt->m_led_status & (1 << (MPTSAS_LEDCTL_LED_OK2RM - 1)))
16509 slotstatus |= MPI2_SEP_REQ_SLOTSTATUS_REQUEST_REMOVE;
16510
16511 /* Write it to the controller */
16512 NDBG14(("mptsas_ioctl: set LED status %x for slot %x",
16513 slotstatus, ptgt->m_slot_num));
16514 return (mptsas_send_sep(mpt, ptgt, &slotstatus,
16515 MPI2_SEP_REQ_ACTION_WRITE_STATUS));
16516 }
16517
16518 /*
16519 * send sep request, use enclosure/slot addressing
16520 */
16521 static int
16522 mptsas_send_sep(mptsas_t *mpt, mptsas_target_t *ptgt,
16523 uint32_t *status, uint8_t act)
16524 {
16525 Mpi2SepRequest_t req;
16526 Mpi2SepReply_t rep;
16527 int ret;
16528
16529 ASSERT(mutex_owned(&mpt->m_mutex));
16530
16531 /*
16532 * We only support SEP control of directly-attached targets, in which
16533 * case the "SEP" we're talking to is a virtual one contained within
16534 * the HBA itself. This is necessary because DA targets typically have
16535 * no other mechanism for LED control. Targets for which a separate
16536 * enclosure service processor exists should be controlled via ses(7d)
16537 * or sgen(7d). Furthermore, since such requests can time out, they
16538 * should be made in user context rather than in response to
16539 * asynchronous fabric changes.
16540 *
16541 * In addition, we do not support this operation for RAID volumes,
16542 * since there is no slot associated with them.
16543 */
16544 if (!(ptgt->m_deviceinfo & DEVINFO_DIRECT_ATTACHED) ||
16545 ptgt->m_addr.mta_phymask == 0) {
16546 return (ENOTTY);
16547 }
16548
16549 bzero(&req, sizeof (req));
16550 bzero(&rep, sizeof (rep));
16551
16552 req.Function = MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR;
16553 req.Action = act;
16554 req.Flags = MPI2_SEP_REQ_FLAGS_ENCLOSURE_SLOT_ADDRESS;
16555 req.EnclosureHandle = LE_16(ptgt->m_enclosure);
16556 req.Slot = LE_16(ptgt->m_slot_num);
16557 if (act == MPI2_SEP_REQ_ACTION_WRITE_STATUS) {
16558 req.SlotStatus = LE_32(*status);
16559 }
16560 ret = mptsas_do_passthru(mpt, (uint8_t *)&req, (uint8_t *)&rep, NULL,
16561 sizeof (req), sizeof (rep), NULL, 0, NULL, 0, 60, FKIOCTL);
16562 if (ret != 0) {
16563 mptsas_log(mpt, CE_NOTE, "mptsas_send_sep: passthru SEP "
16564 "Processor Request message error %d", ret);
16565 return (ret);
16566 }
16567 /* do passthrough success, check the ioc status */
16568 if (LE_16(rep.IOCStatus) != MPI2_IOCSTATUS_SUCCESS) {
16569 mptsas_log(mpt, CE_NOTE, "send_sep act %x: ioc "
16570 "status:%x loginfo %x", act, LE_16(rep.IOCStatus),
16571 LE_32(rep.IOCLogInfo));
16572 switch (LE_16(rep.IOCStatus) & MPI2_IOCSTATUS_MASK) {
16573 case MPI2_IOCSTATUS_INVALID_FUNCTION:
16574 case MPI2_IOCSTATUS_INVALID_VPID:
16575 case MPI2_IOCSTATUS_INVALID_FIELD:
16576 case MPI2_IOCSTATUS_INVALID_STATE:
16577 case MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED:
16578 case MPI2_IOCSTATUS_CONFIG_INVALID_ACTION:
16579 case MPI2_IOCSTATUS_CONFIG_INVALID_TYPE:
16580 case MPI2_IOCSTATUS_CONFIG_INVALID_PAGE:
16581 case MPI2_IOCSTATUS_CONFIG_INVALID_DATA:
16582 case MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS:
16583 return (EINVAL);
16584 case MPI2_IOCSTATUS_BUSY:
16585 return (EBUSY);
16586 case MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES:
16587 return (EAGAIN);
16588 case MPI2_IOCSTATUS_INVALID_SGL:
16589 case MPI2_IOCSTATUS_INTERNAL_ERROR:
16590 case MPI2_IOCSTATUS_CONFIG_CANT_COMMIT:
16591 default:
16592 return (EIO);
16593 }
16594 }
16595 if (act != MPI2_SEP_REQ_ACTION_WRITE_STATUS) {
16596 *status = LE_32(rep.SlotStatus);
16597 }
16598
16599 return (0);
16600 }
16601
16602 int
16603 mptsas_dma_addr_create(mptsas_t *mpt, ddi_dma_attr_t dma_attr,
16604 ddi_dma_handle_t *dma_hdp, ddi_acc_handle_t *acc_hdp, caddr_t *dma_memp,
16605 uint32_t alloc_size, ddi_dma_cookie_t *cookiep)
16606 {
16607 ddi_dma_cookie_t new_cookie;
16608 size_t alloc_len;
16609 uint_t ncookie;
16610
16611 if (cookiep == NULL)
16612 cookiep = &new_cookie;
16613
16614 if (ddi_dma_alloc_handle(mpt->m_dip, &dma_attr, DDI_DMA_SLEEP,
16615 NULL, dma_hdp) != DDI_SUCCESS) {
16616 return (FALSE);
16617 }
16618
16619 if (ddi_dma_mem_alloc(*dma_hdp, alloc_size, &mpt->m_dev_acc_attr,
16620 DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, NULL, dma_memp, &alloc_len,
16621 acc_hdp) != DDI_SUCCESS) {
16622 ddi_dma_free_handle(dma_hdp);
16623 *dma_hdp = NULL;
16624 return (FALSE);
16625 }
16626
16627 if (ddi_dma_addr_bind_handle(*dma_hdp, NULL, *dma_memp, alloc_len,
16628 (DDI_DMA_RDWR | DDI_DMA_CONSISTENT), DDI_DMA_SLEEP, NULL,
16629 cookiep, &ncookie) != DDI_DMA_MAPPED) {
16630 (void) ddi_dma_mem_free(acc_hdp);
16631 ddi_dma_free_handle(dma_hdp);
16632 *dma_hdp = NULL;
16633 return (FALSE);
16634 }
16635
16636 return (TRUE);
16637 }
16638
16639 void
16640 mptsas_dma_addr_destroy(ddi_dma_handle_t *dma_hdp, ddi_acc_handle_t *acc_hdp)
16641 {
16642 if (*dma_hdp == NULL)
16643 return;
16644
16645 (void) ddi_dma_unbind_handle(*dma_hdp);
16646 (void) ddi_dma_mem_free(acc_hdp);
16647 ddi_dma_free_handle(dma_hdp);
16648 *dma_hdp = NULL;
16649 }