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--- old/usr/src/uts/common/sys/sata/adapters/nv_sata/nv_sata.h
+++ new/usr/src/uts/common/sys/sata/adapters/nv_sata/nv_sata.h
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21
22 22 /*
23 23 * Copyright (c) 2007, 2010, Oracle and/or its affiliates. All rights reserved.
24 24 */
25 25
26 26 #ifndef _NV_SATA_H
27 27 #define _NV_SATA_H
28 28
29 29
30 30 #ifdef __cplusplus
31 31 extern "C" {
32 32 #endif
33 33
34 34
35 35 /*
36 36 * SGPIO Support
37 37 * Enable SGPIO support only on x86/x64, because it is implemented using
38 38 * functions that are only available on x86/x64.
39 39 */
40 40
41 41 #define NV_MAX_PORTS(nvc) nvc->nvc_sata_hba_tran.sata_tran_hba_num_cports
42 42
43 43 typedef struct nv_port nv_port_t;
44 44
45 45 #ifdef SGPIO_SUPPORT
46 46 typedef struct nv_sgp_cmn nv_sgp_cmn_t;
47 47 #endif
48 48
49 49 /*
50 50 * sizes of strings to allocate
51 51 */
52 52 #define NV_STR_LEN 10
53 53 #define NV_LOGBUF_LEN 512
54 54 #define NV_REASON_LEN 30
55 55
56 56
57 57 typedef struct nv_ctl {
58 58 /*
59 59 * Each of these are specific to the chipset in use.
60 60 */
61 61 uint_t (*nvc_interrupt)(caddr_t arg1, caddr_t arg2);
62 62 void (*nvc_reg_init)(struct nv_ctl *nvc,
63 63 ddi_acc_handle_t pci_conf_handle);
64 64
65 65 dev_info_t *nvc_dip; /* devinfo pointer of controller */
66 66
67 67 struct nv_port *nvc_port; /* array of pointers to port struct */
68 68
69 69 /*
70 70 * handle and base address to register space.
71 71 *
72 72 * 0: port 0 task file
73 73 * 1: port 0 status
74 74 * 2: port 1 task file
75 75 * 3: port 1 status
76 76 * 4: bus master for both ports
77 77 * 5: extended registers for SATA features
78 78 */
79 79 ddi_acc_handle_t nvc_bar_hdl[6];
80 80 uchar_t *nvc_bar_addr[6];
81 81
82 82 /*
83 83 * sata registers in bar 5 which are shared on all devices
84 84 * on the channel.
85 85 */
86 86 uint32_t *nvc_mcp5x_ctl;
87 87 uint32_t *nvc_mcp5x_ncq; /* NCQ status control bits */
88 88
89 89 kmutex_t nvc_mutex; /* ctrl level lock */
90 90
91 91 ddi_intr_handle_t *nvc_htable; /* For array of interrupts */
92 92 int nvc_intr_type; /* What type of interrupt */
93 93 int nvc_intr_cnt; /* # of intrs count returned */
94 94 size_t nvc_intr_size; /* Size of intr array to */
95 95 uint_t nvc_intr_pri; /* Interrupt priority */
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96 96 int nvc_intr_cap; /* Interrupt capabilities */
97 97 uint8_t *nvc_ck804_int_status; /* interrupt status ck804 */
98 98
99 99 sata_hba_tran_t nvc_sata_hba_tran; /* sata_hba_tran for ctrl */
100 100
101 101 /*
102 102 * enable/disable interrupts, controller specific
103 103 */
104 104 void (*nvc_set_intr)(nv_port_t *nvp, int flag);
105 105 int nvc_state; /* state flags of ctrl see below */
106 + uint16_t nvc_devid; /* PCI devid of device */
106 107 uint8_t nvc_revid; /* PCI revid of device */
107 108 boolean_t dma_40bit; /* 40bit DMA support */
109 + boolean_t nvc_mcp5x_flag; /* is the controller MCP51/MCP55 */
108 110
109 111 #ifdef SGPIO_SUPPORT
110 - int nvc_mcp5x_flag; /* is the controller MCP51/MCP55 */
111 112 uint8_t nvc_ctlr_num; /* controller number within the part */
112 113 uint32_t nvc_sgp_csr; /* SGPIO CSR i/o address */
113 114 volatile nv_sgp_cb_t *nvc_sgp_cbp; /* SGPIO Control Block */
114 115 nv_sgp_cmn_t *nvc_sgp_cmn; /* SGPIO shared data */
115 116 #endif
116 117 } nv_ctl_t;
117 118
118 119
119 120 struct nv_port {
120 121
121 122 struct nv_ctl *nvp_ctlp; /* back pointer to controller */
122 123
123 124 uint8_t nvp_port_num; /* port number, ie 0 or 1 */
124 125
125 126 uint8_t nvp_type; /* SATA_DTYPE_{NONE,ATADISK,UNKNOWN} */
126 127 uint32_t nvp_signature; /* sig acquired from task file regs */
127 128 uchar_t *nvp_cmd_addr; /* base addr for cmd regs for port */
128 129 uchar_t *nvp_bm_addr; /* base addr for bus master for port */
129 130 uchar_t *nvp_ctl_addr; /* base addr for ctrl regs for port */
130 131
131 132 ddi_acc_handle_t nvp_cmd_hdl;
132 133 uchar_t *nvp_data; /* data register */
133 134 uchar_t *nvp_error; /* error register (read) */
134 135 uchar_t *nvp_feature; /* features (write) */
135 136 uchar_t *nvp_count; /* sector count */
136 137 uchar_t *nvp_sect; /* sector number */
137 138 uchar_t *nvp_lcyl; /* cylinder low byte */
138 139 uchar_t *nvp_hcyl; /* cylinder high byte */
139 140 uchar_t *nvp_drvhd; /* drive/head register */
140 141 uchar_t *nvp_status; /* status/command register */
141 142 uchar_t *nvp_cmd; /* status/command register */
142 143
143 144 ddi_acc_handle_t nvp_ctl_hdl;
144 145 uchar_t *nvp_altstatus; /* alternate status (read) */
145 146 uchar_t *nvp_devctl; /* device control (write) */
146 147
147 148 ddi_acc_handle_t nvp_bm_hdl;
148 149 uchar_t *nvp_bmisx;
149 150 uint32_t *nvp_bmidtpx;
150 151 uchar_t *nvp_bmicx;
151 152
152 153 ddi_dma_handle_t *nvp_sg_dma_hdl; /* dma handle to prd table */
153 154 caddr_t *nvp_sg_addr; /* virtual addr of prd table */
154 155 uint32_t *nvp_sg_paddr; /* physical address of prd table */
155 156 ddi_acc_handle_t *nvp_sg_acc_hdl; /* mem acc handle to the prd table */
156 157
157 158 uint32_t *nvp_sstatus;
158 159 uint32_t *nvp_serror;
159 160 uint32_t *nvp_sctrl;
160 161 uint32_t *nvp_sactive;
161 162
162 163 kmutex_t nvp_mutex; /* main per port mutex */
163 164 kcondvar_t nvp_sync_cv; /* handshake btwn ISR and start thrd */
164 165 kcondvar_t nvp_reset_cv; /* when reset is synchronous */
165 166
166 167 /*
167 168 * nvp_slot is a pointer to an array of nv_slot
168 169 */
169 170 struct nv_slot *nvp_slot;
170 171 uint32_t nvp_sactive_cache; /* cache of SACTIVE */
171 172 uint8_t nvp_queue_depth;
172 173
173 174 /*
174 175 * NCQ flow control. During NCQ operation, no other commands
175 176 * allowed. The following are used to enforce this.
176 177 */
177 178 int nvp_ncq_run;
178 179 int nvp_non_ncq_run;
179 180 int nvp_seq;
180 181
181 182 timeout_id_t nvp_timeout_id;
182 183
183 184 clock_t nvp_reset_time; /* time of last reset */
184 185 clock_t nvp_link_event_time; /* time of last plug event */
185 186 int nvp_reset_retry_count;
186 187 clock_t nvp_wait_sig; /* wait before rechecking sig */
187 188
188 189 int nvp_state; /* state of port. flags defined below */
189 190
190 191 uint16_t *nvp_mcp5x_int_status;
191 192 uint16_t *nvp_mcp5x_int_ctl;
192 193
193 194 #ifdef SGPIO_SUPPORT
194 195 uint8_t nvp_sgp_ioctl_mod; /* LEDs modified by ioctl */
195 196 #endif
196 197 clock_t nvp_timeout_duration;
197 198
198 199
199 200 /*
200 201 * debug and statistical information
201 202 */
202 203 clock_t nvp_rem_time;
203 204 clock_t nvp_add_time;
204 205 clock_t nvp_trans_link_time;
205 206 int nvp_trans_link_count;
206 207
207 208 uint8_t nvp_last_cmd;
208 209 uint8_t nvp_previous_cmd;
209 210 int nvp_reset_count;
210 211 char nvp_first_reset_reason[NV_REASON_LEN];
211 212 char nvp_reset_reason[NV_REASON_LEN];
212 213 clock_t intr_duration; /* max length of port intr (ticks) */
213 214 clock_t intr_start_time;
214 215 int intr_loop_cnt;
215 216 };
216 217
217 218
218 219 typedef struct nv_device_table {
219 220 ushort_t vendor_id; /* vendor id */
220 221 ushort_t device_id; /* device id */
221 222 ushort_t type; /* chipset type, ck804 or mcp51/mcp55 */
222 223 } nv_device_table_t;
223 224
224 225
225 226 typedef struct nv_slot {
226 227 caddr_t nvslot_v_addr; /* I/O buffer address */
227 228 size_t nvslot_byte_count; /* # bytes left to read/write */
228 229 sata_pkt_t *nvslot_spkt;
229 230 uint8_t nvslot_rqsense_buff[SATA_ATAPI_RQSENSE_LEN];
230 231 clock_t nvslot_stime;
231 232 int (*nvslot_start)(nv_port_t *nvp, int queue);
232 233 void (*nvslot_intr)(nv_port_t *nvp,
233 234 struct nv_slot *nv_slotp);
234 235 uint32_t nvslot_flags;
235 236 } nv_slot_t;
236 237
237 238
238 239 #ifdef SGPIO_SUPPORT
239 240 struct nv_sgp_cmn {
240 241 uint8_t nvs_in_use; /* bit-field of active ctlrs */
241 242 uint8_t nvs_connected; /* port connected bit-field flag */
242 243 uint8_t nvs_activity; /* port usage bit-field flag */
243 244 int nvs_cbp; /* SGPIO Control Block Pointer */
244 245 int nvs_taskq_delay; /* rest time for activity LED taskq */
245 246 kmutex_t nvs_slock; /* lock for shared data */
246 247 kmutex_t nvs_tlock; /* lock for taskq */
247 248 kcondvar_t nvs_cv; /* condition variable for taskq wait */
248 249 ddi_taskq_t *nvs_taskq; /* activity LED taskq */
249 250 };
250 251
251 252 struct nv_sgp_cbp2cmn {
252 253 uint32_t c2cm_cbp; /* ctlr block ptr from pci cfg space */
253 254 nv_sgp_cmn_t *c2cm_cmn; /* point to common space */
254 255 };
255 256 #endif
256 257
257 258
258 259 /*
259 260 * nvslot_flags
260 261 */
261 262 #define NVSLOT_COMPLETE 0x01
262 263 #define NVSLOT_NCQ 0x02 /* NCQ is active */
263 264 #define NVSLOT_RQSENSE 0x04 /* processing request sense */
264 265
265 266 /*
266 267 * state values for nv_attach
267 268 */
268 269 #define ATTACH_PROGRESS_NONE (1 << 0)
269 270 #define ATTACH_PROGRESS_STATEP_ALLOC (1 << 1)
270 271 #define ATTACH_PROGRESS_PCI_HANDLE (1 << 2)
271 272 #define ATTACH_PROGRESS_BARS (1 << 3)
272 273 #define ATTACH_PROGRESS_INTR_ADDED (1 << 4)
273 274 #define ATTACH_PROGRESS_MUTEX_INIT (1 << 5)
274 275 #define ATTACH_PROGRESS_CTL_SETUP (1 << 6)
275 276 #define ATTACH_PROGRESS_TRAN_SETUP (1 << 7)
276 277 #define ATTACH_PROGRESS_COUNT (1 << 8)
277 278 #define ATTACH_PROGRESS_CONF_HANDLE (1 << 9)
278 279 #define ATTACH_PROGRESS_SATA_MODULE (1 << 10)
279 280
280 281 #ifdef DEBUG
281 282
282 283 #define NV_DEBUG 1
283 284
284 285 #endif /* DEBUG */
285 286
286 287
287 288 /*
288 289 * nv_debug_flags
289 290 */
290 291 #define NVDBG_ALWAYS 0x00001
291 292 #define NVDBG_INIT 0x00002
292 293 #define NVDBG_ENTRY 0x00004
293 294 #define NVDBG_DELIVER 0x00008
294 295 #define NVDBG_EVENT 0x00010
295 296 #define NVDBG_SYNC 0x00020
296 297 #define NVDBG_PKTCOMP 0x00040
297 298 #define NVDBG_TIMEOUT 0x00080
298 299 #define NVDBG_INFO 0x00100
299 300 #define NVDBG_VERBOSE 0x00200
300 301 #define NVDBG_INTR 0x00400
301 302 #define NVDBG_ERRS 0x00800
302 303 #define NVDBG_COOKIES 0x01000
303 304 #define NVDBG_HOT 0x02000
304 305 #define NVDBG_RESET 0x04000
305 306 #define NVDBG_ATAPI 0x08000
306 307
307 308 #define NVLOG(flag, nvc, nvp, fmt, args ...) \
308 309 if (nv_debug_flags & (flag)) { \
309 310 nv_log(nvc, nvp, fmt, ## args); \
310 311 }
311 312
312 313
313 314 #define NV_SUCCESS 0
314 315 #define NV_FAILURE -1
315 316
316 317 /*
317 318 * indicates whether nv_wait functions can sleep or not.
318 319 */
319 320 #define NV_SLEEP 1
320 321 #define NV_NOSLEEP 2
321 322
322 323
323 324 /*
324 325 * port offsets from base address ioaddr1
325 326 */
326 327 #define NV_DATA 0x00 /* data register */
327 328 #define NV_ERROR 0x01 /* error register (read) */
328 329 #define NV_FEATURE 0x01 /* features (write) */
329 330 #define NV_COUNT 0x02 /* sector count */
330 331 #define NV_SECT 0x03 /* sector number */
331 332 #define NV_LCYL 0x04 /* cylinder low byte */
332 333 #define NV_HCYL 0x05 /* cylinder high byte */
333 334 #define NV_DRVHD 0x06 /* drive/head register */
334 335 #define NV_STATUS 0x07 /* status/command register */
335 336 #define NV_CMD 0x07 /* status/command register */
336 337
337 338 /*
338 339 * port offsets from base address ioaddr2
339 340 */
340 341 #define NV_ALTSTATUS 0x02 /* alternate status (read) */
341 342 #define NV_DEVCTL 0x02 /* device control (write) */
342 343
343 344 /*
344 345 * device control register
345 346 */
346 347 #define ATDC_NIEN 0x02 /* disable interrupts */
347 348 #define ATDC_SRST 0x04 /* controller reset */
348 349 #define ATDC_D3 0x08 /* mysterious bit */
349 350 #define ATDC_HOB 0x80 /* high order byte to read 48-bit values */
350 351
351 352 /*
352 353 * MCP5x NCQ and INTR control registers
353 354 */
354 355 #define MCP5X_CTL 0x400 /* queuing control */
355 356 #define MCP5X_INT_STATUS 0x440 /* status bits for interrupt */
356 357 #define MCP5X_INT_CTL 0x444 /* enable bits for interrupt */
357 358 #define MCP5X_NCQ 0x448 /* NCQ status and ctrl bits */
358 359
359 360 /*
360 361 * if either of these bits are set, when using NCQ, if no other commands are
361 362 * active while a new command is started, DMA engine can be programmed ahead
362 363 * of time to save extra interrupt. Presumably pre-programming is discarded
363 364 * if a subsequent command ends up finishing first.
364 365 */
365 366 #define MCP_SATA_AE_NCQ_PDEV_FIRST_CMD (1 << 7)
366 367 #define MCP_SATA_AE_NCQ_SDEV_FIRST_CMD (1 << 23)
367 368
368 369 /*
369 370 * bit definitions to indicate which NCQ command requires
370 371 * DMA setup.
371 372 */
372 373 #define MCP_SATA_AE_NCQ_PDEV_DMA_SETUP_TAG_SHIFT 2
373 374 #define MCP_SATA_AE_NCQ_SDEV_DMA_SETUP_TAG_SHIFT 18
374 375 #define MCP_SATA_AE_NCQ_DMA_SETUP_TAG_MASK 0x1f
375 376
376 377
377 378 /*
378 379 * Bits for NV_MCP5X_INT_CTL and NV_MCP5X_INT_STATUS
379 380 */
380 381 #define MCP5X_INT_SNOTIFY 0x200 /* snotification set */
381 382 #define MCP5X_INT_SERROR 0x100 /* serror set */
382 383 #define MCP5X_INT_DMA_SETUP 0x80 /* DMA to be programmed */
383 384 #define MCP5X_INT_DH_REGFIS 0x40 /* REGFIS received */
384 385 #define MCP5X_INT_SDB_FIS 0x20 /* SDB FIS */
385 386 #define MCP5X_INT_TX_BACKOUT 0x10 /* TX backout */
386 387 #define MCP5X_INT_REM 0x08 /* device removed */
387 388 #define MCP5X_INT_ADD 0x04 /* device added */
388 389 #define MCP5X_INT_PM 0x02 /* power changed */
389 390 #define MCP5X_INT_COMPLETE 0x01 /* device interrupt */
390 391
391 392 /*
392 393 * Bits above that are not used for now.
393 394 */
394 395 #define MCP5X_INT_IGNORE (MCP5X_INT_DMA_SETUP|MCP5X_INT_DH_REGFIS|\
395 396 MCP5X_INT_SDB_FIS|MCP5X_INT_TX_BACKOUT|MCP5X_INT_PM|\
396 397 MCP5X_INT_SNOTIFY|MCP5X_INT_SERROR)
397 398
398 399 /*
399 400 * Bits for MCP_SATA_AE_CTL
400 401 */
401 402 #define MCP_SATA_AE_CTL_PRI_SWNCQ (1 << 1) /* software NCQ chan 0 */
402 403 #define MCP_SATA_AE_CTL_SEC_SWNCQ (1 << 2) /* software NCQ chan 1 */
403 404
404 405 #define NV_DELAY_NSEC(wait_ns) \
405 406 { \
406 407 hrtime_t start, end; \
407 408 start = end = gethrtime(); \
408 409 while ((end - start) < wait_ns) \
409 410 end = gethrtime(); \
410 411 }
411 412
412 413 /*
413 414 * signature in task file registers after device reset
414 415 */
415 416 #define NV_DISK_SIG 0x00000101
416 417 #define NV_ATAPI_SIG 0xeb140101
417 418 #define NV_PM_SIG 0x96690101
418 419 #define NV_NO_SIG 0x00000000
419 420
420 421 /*
421 422 * These bar5 offsets are common to mcp51/mcp55/ck804 and thus
422 423 * prefixed with NV.
423 424 */
424 425 #define NV_SSTATUS 0x00
425 426 #define NV_SERROR 0x04
426 427 #define NV_SCTRL 0x08
427 428 #define NV_SACTIVE 0x0c
428 429 #define NV_SNOTIFICATION 0x10
429 430
430 431 #define CH0_SREG_OFFSET 0x0
431 432 #define CH1_SREG_OFFSET 0x40
432 433
433 434
434 435 /*
435 436 * The following config space offsets are needed to enable
436 437 * bar 5 register access in ck804/mcp51/mcp55
437 438 */
438 439 #define NV_SATA_CFG_20 0x50
439 440 #define NV_BAR5_SPACE_EN 0x04
440 441 #define NV_40BIT_PRD 0x20
441 442
442 443 #define NV_SATA_CFG_23 0x60
443 444
444 445 /*
445 446 * ck804 interrupt status register
446 447 */
447 448
448 449 /*
449 450 * offsets to bar 5 registers
450 451 */
451 452 #define CK804_SATA_INT_STATUS 0x440
452 453 #define CK804_SATA_INT_EN 0x441
453 454
454 455
455 456 /*
456 457 * bit fields for int status and int enable
457 458 * registers
458 459 */
459 460 #define CK804_INT_PDEV_INT 0x01 /* completion interrupt */
460 461 #define CK804_INT_PDEV_PM 0x02 /* power change */
461 462 #define CK804_INT_PDEV_ADD 0x04 /* hot plug */
462 463 #define CK804_INT_PDEV_REM 0x08 /* hot remove */
463 464 #define CK804_INT_PDEV_HOT CK804_INT_PDEV_ADD|CK804_INT_PDEV_REM
464 465
465 466 #define CK804_INT_SDEV_INT 0x10 /* completion interrupt */
466 467 #define CK804_INT_SDEV_PM 0x20 /* power change */
467 468 #define CK804_INT_SDEV_ADD 0x40 /* hot plug */
468 469 #define CK804_INT_SDEV_REM 0x80 /* hot remove */
469 470 #define CK804_INT_SDEV_HOT CK804_INT_SDEV_ADD|CK804_INT_SDEV_REM
470 471
471 472 #define CK804_INT_PDEV_ALL CK804_INT_PDEV_INT|CK804_INT_PDEV_HOT|\
472 473 CK804_INT_PDEV_PM
473 474 #define CK804_INT_SDEV_ALL CK804_INT_SDEV_INT|CK804_INT_SDEV_HOT|\
474 475 CK804_INT_SDEV_PM
475 476
476 477 /*
477 478 * config space offset 42
478 479 */
479 480 #define NV_SATA_CFG_42 0xac
480 481
481 482 /*
482 483 * bit in CFG_42 which delays hotplug interrupt until
483 484 * PHY ready
484 485 */
485 486 #define CK804_CFG_DELAY_HOTPLUG_INTR (0x1 << 12)
486 487
487 488
488 489 /*
489 490 * bar 5 offsets for SATA registers in ck804
490 491 */
491 492 #define CK804_CH1_SSTATUS 0x00
492 493 #define CK804_CH1_SERROR 0x04
493 494 #define CK804_CH1_SCTRL 0x08
494 495 #define CK804_CH1_SACTIVE 0x0c
495 496 #define CK804_CH1_SNOTIFICATION 0x10
496 497
497 498 #define CK804_CH2_SSTATUS 0x40
498 499 #define CK804_CH2_SERROR 0x44
499 500 #define CK804_CH2_SCTRL 0x48
500 501 #define CK804_CH2_SACTIVE 0x4c
501 502 #define CK804_CH2_SNOTIFICATION 0x50
502 503
503 504
504 505 /*
505 506 * bar 5 offsets for ADMACTL settings for both ck804/mcp51/mcp/55
506 507 */
507 508 #define NV_ADMACTL_X 0x4C0
508 509 #define NV_ADMACTL_Y 0x5C0
509 510
510 511 /*
511 512 * Bits for NV_ADMACTL_X and NV_ADMACTL_Y
512 513 */
513 514 #define NV_HIRQ_EN 0x01 /* hot plug/unplug interrupt enable */
514 515 #define NV_CH_RST 0x04 /* reset channel */
515 516
516 517
517 518 /*
518 519 * bar 5 offset for ADMASTAT regs for ck804
519 520 */
520 521 #define CK804_ADMASTAT_X 0x4C4
521 522 #define CK804_ADMASTAT_Y 0x5C4
522 523
523 524 /*
524 525 * Bits for CK804_ADMASTAT_X and CK804_ADMASTAT_Y
525 526 */
526 527 #define CK804_HPIRQ 0x4
527 528 #define MCP05_HUIRQ 0x2
528 529
529 530
530 531 /*
531 532 * bar 4 offset to bus master command registers
532 533 */
533 534 #define BMICX_REG 0
534 535
535 536 /*
536 537 * bit definitions for BMICX_REG
537 538 */
538 539 #define BMICX_SSBM 0x01 /* Start/Stop Bus Master */
539 540 /* 1=Start (Enable) */
540 541 /* 0=Start (Disable) */
541 542
542 543 /*
543 544 * NOTE: "read" and "write" are the actions of the DMA engine
544 545 * on the PCI bus, not the SATA bus. Therefore for a ATA READ
545 546 * command, program the DMA engine to "write to memory" mode
546 547 * (and vice versa).
547 548 */
548 549 #define BMICX_RWCON 0x08 /* Read/Write Control */
549 550 #define BMICX_RWCON_WRITE_TO_MEMORY 0x08 /* 1=Write (dev to host) */
550 551 #define BMICX_RWCON_READ_FROM_MEMORY 0x00 /* 0=Read (host to dev) */
551 552
552 553 /*
553 554 * BMICX bits to preserve during updates
554 555 */
555 556 #define BMICX_MASK (~(BMICX_SSBM | BMICX_RWCON))
556 557
557 558 /*
558 559 * bar 4 offset to bus master status register
559 560 */
560 561 #define BMISX_REG 2
561 562
562 563 /*
563 564 * bit fields for bus master status register
564 565 */
565 566 #define BMISX_BMIDEA 0x01 /* Bus Master IDE Active */
566 567 #define BMISX_IDERR 0x02 /* IDE DMA Error */
567 568 #define BMISX_IDEINTS 0x04 /* IDE Interrupt Status */
568 569
569 570 /*
570 571 * bus master status register bits to preserve
571 572 */
572 573 #define BMISX_MASK 0xf8
573 574
574 575 /*
575 576 * bar4 offset to bus master PRD descriptor table
576 577 */
577 578 #define BMIDTPX_REG 4
578 579
579 580
580 581 /*
581 582 * structure for a single entry in the PRD table
582 583 * (physical region descriptor table)
583 584 */
584 585 typedef struct prde {
585 586 uint32_t p_address; /* physical address */
586 587 uint32_t p_count; /* byte count, EOT in high order bit */
587 588 } prde_t;
588 589
589 590
590 591 #define PRDE_EOT ((uint_t)0x80000000)
591 592
592 593 #define NV_DMA_NSEGS 257 /* at least 1MB (4KB/pg * 256) + 1 if misaligned */
593 594
594 595 /*
595 596 * ck804 and mcp55 both have 2 ports per controller
596 597 */
597 598 #define NV_NUM_PORTS 2
598 599
599 600 /*
600 601 * Number of slots to allocate in data nv_sata structures to handle
601 602 * multiple commands at once. This does not reflect the capability of
602 603 * the drive or the hardware, and in many cases will not match.
603 604 * 1 or 32 slots are allocated, so in cases where the driver has NCQ
604 605 * enabled but the drive doesn't support it, or supports fewer than
605 606 * 32 slots, here may be an over allocation of memory.
606 607 */
607 608 #ifdef NCQ
608 609 #define NV_QUEUE_SLOTS 32
609 610 #else
610 611 #define NV_QUEUE_SLOTS 1
611 612 #endif
612 613
613 614 #define NV_BM_64K_BOUNDARY 0x10000ull
614 615
615 616 #define NV_MAX_INTR_PER_DEV 20 /* Empirical value */
616 617
617 618 /*
618 619 * 1 second (in microseconds)
619 620 */
620 621 #define NV_ONE_SEC 1000000
621 622
622 623 /*
623 624 * 1 millisecond (in microseconds)
624 625 */
625 626 #define NV_ONE_MSEC 1000
626 627
627 628 /*
628 629 * initial wait before checking for signature, in microseconds
629 630 */
630 631 #define NV_WAIT_SIG 2500
631 632
632 633
633 634 /*
634 635 * Length of port reset (microseconds) - SControl bit 0 set to 1
635 636 */
636 637 #define NV_RESET_LENGTH 1000
637 638
638 639 /*
639 640 * the maximum number of comresets to issue while
640 641 * performing link reset in nv_reset()
641 642 */
642 643 #define NV_COMRESET_ATTEMPTS 3
643 644
644 645 /*
645 646 * amount of time to wait for a signature in reset, in ms, before
646 647 * issuing another reset
647 648 */
648 649 #define NV_RETRY_RESET_SIG 5000
649 650
650 651 /*
651 652 * the maximum number of resets to issue to gather signature
652 653 * before giving up
653 654 */
654 655 #define NV_MAX_RESET_RETRY 8
655 656
656 657 /*
657 658 * amount of time (us) to wait after receiving a link event
658 659 * before acting on it. This is because of flakey hardware
659 660 * sometimes issues the wrong, multiple, or out of order link
660 661 * events.
661 662 */
662 663 #define NV_LINK_EVENT_SETTLE 500000
663 664
664 665 /*
665 666 * The amount of time (ms) a link can be missing
666 667 * before declaring it removed.
667 668 */
668 669 #define NV_LINK_EVENT_DOWN 200
669 670
670 671 /*
671 672 * nvp_state flags
672 673 */
673 674 #define NV_DEACTIVATED 0x001
674 675 #define NV_ABORTING 0x002
675 676 #define NV_FAILED 0x004
676 677 #define NV_RESET 0x008
677 678 #define NV_RESTORE 0x010
678 679 #define NV_LINK_EVENT 0x020
679 680 #define NV_ATTACH 0x040
680 681 #define NV_HOTPLUG 0x080
681 682
682 683
683 684 /*
684 685 * flags for nv_report_link_event()
685 686 */
686 687 #define NV_ADD_DEV 0
687 688 #define NV_REM_DEV 1
688 689
689 690 /*
690 691 * nvc_state flags
691 692 */
692 693 #define NV_CTRL_SUSPEND 0x1
693 694
694 695
695 696 /*
696 697 * flags for ck804_set_intr/mcp5x_set_intr
697 698 */
698 699 #define NV_INTR_DISABLE 0x1
699 700 #define NV_INTR_ENABLE 0x2
700 701 #define NV_INTR_CLEAR_ALL 0x4
701 702 #define NV_INTR_DISABLE_NON_BLOCKING 0x8
702 703
703 704
704 705 #define NV_BYTES_PER_SEC 512
705 706
706 707 #define NV_WAIT_REG_CHECK 10 /* 10 microseconds */
707 708 #define NV_ATA_NUM_CMDS 256 /* max num ATA cmds possible, 8 bits */
708 709 #define NV_PRINT_INTERVAL 40 /* throttle debug msg from flooding */
709 710 #define MCP5X_INT_CLEAR 0xffff /* clear all interrupts */
710 711
711 712 /*
712 713 * definition labels for the BAR registers
713 714 */
714 715 #define NV_BAR_0 0 /* chan 0 task file regs */
715 716 #define NV_BAR_1 1 /* chan 0 status reg */
716 717 #define NV_BAR_2 2 /* chan 1 task file regs */
717 718 #define NV_BAR_3 3 /* chan 1 status reg */
718 719 #define NV_BAR_4 4 /* bus master regs */
719 720 #define NV_BAR_5 5 /* extra regs mostly SATA related */
720 721
721 722 /*
722 723 * transform seconds to microseconds
723 724 */
724 725 #define NV_SEC2USEC(x) x * MICROSEC
725 726
726 727
727 728 /*
728 729 * ck804 maps in task file regs into bar 5. These are
729 730 * only used to identify ck804, therefore only this reg is
730 731 * listed here.
731 732 */
732 733 #define NV_BAR5_TRAN_LEN_CH_X 0x518
733 734
734 735 /*
735 736 * if after this many iterations through the interrupt
736 737 * processing loop, declare the interrupt wedged and
737 738 * disable.
738 739 */
739 740 #define NV_MAX_INTR_LOOP 10
740 741
741 742 /*
742 743 * flag values for nv_copy_regs_out
743 744 */
744 745 #define NV_COPY_COMPLETE 0x01 /* normal command completion */
745 746 #define NV_COPY_ERROR 0x02 /* error, did not complete ok */
746 747 #define NV_COPY_SSREGS 0x04 /* SS port registers */
747 748
748 749 #ifdef SGPIO_SUPPORT
749 750 #define NV_MAX_CBPS 16 /* Maximum # of Control Block */
750 751 /* Pointers. Corresponds to */
751 752 /* each MCP55 and IO55 */
752 753 #define SGPIO_LOOP_WAIT_USECS 62500 /* 1/16 second (in usecs) */
753 754 #define SGPIO_TQ_NAME_LEN 32
754 755
755 756 /*
756 757 * The drive number format is ccp (binary).
757 758 * cc is the controller number (0-based number)
758 759 * p is the port number (0 or 1)
759 760 */
760 761 #define SGP_DRV_TO_PORT(d) ((d) & 1)
761 762 #define SGP_DRV_TO_CTLR(d) ((d) >> 1)
762 763 #define SGP_CTLR_PORT_TO_DRV(c, p) (((c) << 1) | ((p) & 1))
763 764 #endif
764 765
765 766 #ifdef __cplusplus
766 767 }
767 768 #endif
768 769
769 770 #endif /* _NV_SATA_H */
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