86 uint32_t *nvc_mcp5x_ctl;
87 uint32_t *nvc_mcp5x_ncq; /* NCQ status control bits */
88
89 kmutex_t nvc_mutex; /* ctrl level lock */
90
91 ddi_intr_handle_t *nvc_htable; /* For array of interrupts */
92 int nvc_intr_type; /* What type of interrupt */
93 int nvc_intr_cnt; /* # of intrs count returned */
94 size_t nvc_intr_size; /* Size of intr array to */
95 uint_t nvc_intr_pri; /* Interrupt priority */
96 int nvc_intr_cap; /* Interrupt capabilities */
97 uint8_t *nvc_ck804_int_status; /* interrupt status ck804 */
98
99 sata_hba_tran_t nvc_sata_hba_tran; /* sata_hba_tran for ctrl */
100
101 /*
102 * enable/disable interrupts, controller specific
103 */
104 void (*nvc_set_intr)(nv_port_t *nvp, int flag);
105 int nvc_state; /* state flags of ctrl see below */
106 uint8_t nvc_revid; /* PCI revid of device */
107 boolean_t dma_40bit; /* 40bit DMA support */
108
109 #ifdef SGPIO_SUPPORT
110 int nvc_mcp5x_flag; /* is the controller MCP51/MCP55 */
111 uint8_t nvc_ctlr_num; /* controller number within the part */
112 uint32_t nvc_sgp_csr; /* SGPIO CSR i/o address */
113 volatile nv_sgp_cb_t *nvc_sgp_cbp; /* SGPIO Control Block */
114 nv_sgp_cmn_t *nvc_sgp_cmn; /* SGPIO shared data */
115 #endif
116 } nv_ctl_t;
117
118
119 struct nv_port {
120
121 struct nv_ctl *nvp_ctlp; /* back pointer to controller */
122
123 uint8_t nvp_port_num; /* port number, ie 0 or 1 */
124
125 uint8_t nvp_type; /* SATA_DTYPE_{NONE,ATADISK,UNKNOWN} */
126 uint32_t nvp_signature; /* sig acquired from task file regs */
127 uchar_t *nvp_cmd_addr; /* base addr for cmd regs for port */
128 uchar_t *nvp_bm_addr; /* base addr for bus master for port */
129 uchar_t *nvp_ctl_addr; /* base addr for ctrl regs for port */
130
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86 uint32_t *nvc_mcp5x_ctl;
87 uint32_t *nvc_mcp5x_ncq; /* NCQ status control bits */
88
89 kmutex_t nvc_mutex; /* ctrl level lock */
90
91 ddi_intr_handle_t *nvc_htable; /* For array of interrupts */
92 int nvc_intr_type; /* What type of interrupt */
93 int nvc_intr_cnt; /* # of intrs count returned */
94 size_t nvc_intr_size; /* Size of intr array to */
95 uint_t nvc_intr_pri; /* Interrupt priority */
96 int nvc_intr_cap; /* Interrupt capabilities */
97 uint8_t *nvc_ck804_int_status; /* interrupt status ck804 */
98
99 sata_hba_tran_t nvc_sata_hba_tran; /* sata_hba_tran for ctrl */
100
101 /*
102 * enable/disable interrupts, controller specific
103 */
104 void (*nvc_set_intr)(nv_port_t *nvp, int flag);
105 int nvc_state; /* state flags of ctrl see below */
106 uint16_t nvc_devid; /* PCI devid of device */
107 uint8_t nvc_revid; /* PCI revid of device */
108 boolean_t dma_40bit; /* 40bit DMA support */
109 boolean_t nvc_mcp5x_flag; /* is the controller MCP51/MCP55 */
110
111 #ifdef SGPIO_SUPPORT
112 uint8_t nvc_ctlr_num; /* controller number within the part */
113 uint32_t nvc_sgp_csr; /* SGPIO CSR i/o address */
114 volatile nv_sgp_cb_t *nvc_sgp_cbp; /* SGPIO Control Block */
115 nv_sgp_cmn_t *nvc_sgp_cmn; /* SGPIO shared data */
116 #endif
117 } nv_ctl_t;
118
119
120 struct nv_port {
121
122 struct nv_ctl *nvp_ctlp; /* back pointer to controller */
123
124 uint8_t nvp_port_num; /* port number, ie 0 or 1 */
125
126 uint8_t nvp_type; /* SATA_DTYPE_{NONE,ATADISK,UNKNOWN} */
127 uint32_t nvp_signature; /* sig acquired from task file regs */
128 uchar_t *nvp_cmd_addr; /* base addr for cmd regs for port */
129 uchar_t *nvp_bm_addr; /* base addr for bus master for port */
130 uchar_t *nvp_ctl_addr; /* base addr for ctrl regs for port */
131
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