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OS-7125 Need mitigation of L1TF (CVE-2018-3646)
Reviewed by: Robert Mustacchi <rm@joyent.com>
Reviewed by: Jerry Jelinek <jerry.jelinek@joyent.com>
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--- old/usr/src/uts/i86pc/os/intr.c
+++ new/usr/src/uts/i86pc/os/intr.c
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21
22 22 /*
23 23 * Copyright (c) 2004, 2010, Oracle and/or its affiliates. All rights reserved.
24 24 * Copyright (c) 2018 Joyent, Inc. All rights reserverd.
25 25 */
26 26
27 27 /*
28 28 * To understand the present state of interrupt handling on i86pc, we must
29 29 * first consider the history of interrupt controllers and our way of handling
30 30 * interrupts.
31 31 *
32 32 * History of Interrupt Controllers on i86pc
33 33 * -----------------------------------------
34 34 *
35 35 * Intel 8259 and 8259A
36 36 *
37 37 * The first interrupt controller that attained widespread use on i86pc was
38 38 * the Intel 8259(A) Programmable Interrupt Controller that first saw use with
39 39 * the 8086. It took up to 8 interrupt sources and combined them into one
40 40 * output wire. Up to 8 8259s could be slaved together providing up to 64 IRQs.
41 41 * With the switch to the 8259A, level mode interrupts became possible. For a
42 42 * long time on i86pc the 8259A was the only way to handle interrupts and it
43 43 * had its own set of quirks. The 8259A and its corresponding interval timer
44 44 * the 8254 are programmed using outb and inb instructions.
45 45 *
46 46 * Intel Advanced Programmable Interrupt Controller (APIC)
47 47 *
48 48 * Starting around the time of the introduction of the P6 family
49 49 * microarchitecture (i686) Intel introduced a new interrupt controller.
50 50 * Instead of having the series of slaved 8259A devices, Intel opted to outfit
51 51 * each processor with a Local APIC (lapic) and to outfit the system with at
52 52 * least one, but potentially more, I/O APICs (ioapic). The lapics and ioapics
53 53 * initially communicated over a dedicated bus, but this has since been
54 54 * replaced. Each physical core and even hyperthread currently contains its
55 55 * own local apic, which is not shared. There are a few exceptions for
56 56 * hyperthreads, but that does not usually concern us.
57 57 *
58 58 * Instead of talking directly to 8259 for status, sending End Of Interrupt
59 59 * (EOI), etc. a microprocessor now communicates directly to the lapic. This
60 60 * also allows for each microprocessor to be able to have independent controls.
61 61 * The programming method is different from the 8259. Consumers map the lapic
62 62 * registers into uncacheable memory to read and manipulate the state.
63 63 *
64 64 * The number of addressable interrupt vectors was increased to 256. However
65 65 * vectors 0-31 are reserved for the processor exception handling, leaving the
66 66 * remaining vectors for general use. In addition to hardware generated
67 67 * interrupts, the lapic provides a way for generating inter-processor
68 68 * interrupts (IPI) which are the basis for CPU cross calls and CPU pokes.
69 69 *
70 70 * AMD ended up implementing the Intel APIC architecture in lieu of their work
71 71 * with Cyrix.
72 72 *
73 73 * Intel x2apic
74 74 *
75 75 * The x2apic is an extension to the lapic which started showing up around the
76 76 * same time as the Sandy Bridge chipsets. It provides a new programming mode
77 77 * as well as new features. The goal of the x2apic is to solve a few problems
78 78 * with the previous generation of lapic and the x2apic is backwards compatible
79 79 * with the previous programming and model. The only downsides to using the
80 80 * backwards compatibility is that you are not able to take advantage of the new
81 81 * x2apic features.
82 82 *
83 83 * o The APIC ID is increased from an 8-bit value to a 32-bit value. This
84 84 * increases the maximum number of addressable physical processors beyond
85 85 * 256. This new ID is assembled in a similar manner as the information that
86 86 * is obtainable by the extended cpuid topology leaves.
87 87 *
88 88 * o A new means of generating IPIs was introduced.
89 89 *
90 90 * o Instead of memory mapping the registers, the x2apic only allows for
91 91 * programming it through a series of wrmsrs. This has important semantic
92 92 * side effects. Recall that the registers were previously all mapped to
93 93 * uncachable memory which meant that all operations to the local apic were
94 94 * serializing instructions. With the switch to using wrmsrs this has been
95 95 * relaxed and these operations can no longer be assumed to be serializing
96 96 * instructions.
97 97 *
98 98 * Note for the rest of this we are only going to concern ourselves with the
99 99 * apic and x2apic which practically all of i86pc has been using now for
100 100 * quite some time.
101 101 *
102 102 * Interrupt Priority Levels
103 103 * -------------------------
104 104 *
105 105 * On i86pc systems there are a total of fifteen interrupt priority levels
106 106 * (ipls) which range from 1-15. Level 0 is for normal processing and
107 107 * non-interrupt processing. To manipulate these values the family of spl
108 108 * functions (which date back to UNIX on the PDP-11) are used. Specifically,
109 109 * splr() to raise the priority level and splx() to lower it. One should not
110 110 * generally call setspl() directly.
111 111 *
112 112 * Both i86pc and the supported SPARC platforms honor the same conventions for
113 113 * the meaning behind these IPLs. The most important IPL is the platform's
114 114 * LOCK_LEVEL (0xa on i86pc). If a thread is above LOCK_LEVEL it _must_ not
115 115 * sleep on any synchronization object. The only allowed synchronization
116 116 * primitive is a mutex that has been specifically initialized to be a spin
117 117 * lock (see mutex_init(9F)). Another important level is DISP_LEVEL (0xb on
118 118 * i86pc). You must be at DISP_LEVEL if you want to control the dispatcher.
119 119 * The XC_HI_PIL is the highest level (0xf) and is used during cross-calls.
120 120 *
121 121 * Each interrupt that is registered in the system fires at a specific IPL.
122 122 * Generally most interrupts fire below LOCK_LEVEL.
123 123 *
124 124 * PSM Drivers
125 125 * -----------
126 126 *
127 127 * We currently have three sets of PSM (platform specific module) drivers
128 128 * available. uppc, pcplusmp, and apix. uppc (uni-processor PC) is the original
129 129 * driver that interacts with the 8259A and 8254. In general, it is not used
130 130 * anymore given the prevalence of the apic.
131 131 *
132 132 * The system prefers to use the apix driver over the pcplusmp driver. The apix
133 133 * driver requires HW support for an x2apic. If there is no x2apic HW, apix
134 134 * will not be used. In general we prefer using the apix driver over the
135 135 * pcplusmp driver because it gives us much more flexibility with respect to
136 136 * interrupts. In the apix driver each local apic has its own independent set
137 137 * of interrupts, whereas the pcplusmp driver only has a single global set of
138 138 * interrupts. This is why pcplusmp only supports a finite number of interrupts
139 139 * per IPL -- generally 16, often less. The apix driver supports using either
140 140 * the x2apic or the local apic programing modes. The programming mode does not
141 141 * change the number of interrupts available, just the number of processors
142 142 * that we can address. For the apix driver, the x2apic mode is enabled if the
143 143 * system supports interrupt re-mapping, otherwise the module manages the
144 144 * x2apic in local mode.
145 145 *
146 146 * When there is no x2apic present, we default back to the pcplusmp PSM driver.
147 147 * In general, this is not problematic unless you have more than 256
148 148 * processors in the machine or you do not have enough interrupts available.
149 149 *
150 150 * Controlling Interrupt Generation on i86pc
151 151 * -----------------------------------------
152 152 *
153 153 * There are two different ways to manipulate which interrupts will be
154 154 * generated on i86pc. Each offers different degrees of control.
155 155 *
156 156 * The first is through the flags register (eflags and rflags on i386 and amd64
157 157 * respectively). The IF bit determines whether or not interrupts are enabled
158 158 * or disabled. This is manipulated in one of several ways. The most common way
159 159 * is through the cli and sti instructions. These clear the IF flag and set it,
160 160 * respectively, for the current processor. The other common way is through the
161 161 * use of the intr_clear and intr_restore functions.
162 162 *
163 163 * Assuming interrupts are not blocked by the IF flag, then the second form is
164 164 * through the Processor-Priority Register (PPR). The PPR is used to determine
165 165 * whether or not a pending interrupt should be delivered. If the ipl of the
166 166 * new interrupt is higher than the current value in the PPR, then the lapic
167 167 * will either deliver it immediately (if interrupts are not in progress) or it
168 168 * will deliver it once the current interrupt processing has issued an EOI. The
169 169 * highest unmasked interrupt will be the one delivered.
170 170 *
171 171 * The PPR register is based upon the max of the following two registers in the
172 172 * lapic, the TPR register (also known as CR8 on amd64) that can be used to
173 173 * mask interrupt levels, and the current vector. Because the pcplusmp module
174 174 * always sets TPR appropriately early in the do_interrupt path, we can usually
175 175 * just think that the PPR is the TPR. The pcplusmp module also issues an EOI
176 176 * once it has set the TPR, so higher priority interrupts can come in while
177 177 * we're servicing a lower priority interrupt.
178 178 *
179 179 * Handling Interrupts
180 180 * -------------------
181 181 *
182 182 * Interrupts can be broken down into three categories based on priority and
183 183 * source:
184 184 *
185 185 * o High level interrupts
186 186 * o Low level hardware interrupts
187 187 * o Low level software interrupts
188 188 *
189 189 * High Level Interrupts
190 190 *
191 191 * High level interrupts encompasses both hardware-sourced and software-sourced
192 192 * interrupts. Examples of high level hardware interrupts include the serial
193 193 * console. High level software-sourced interrupts are still delivered through
194 194 * the local apic through IPIs. This is primarily cross calls.
195 195 *
196 196 * When a high level interrupt comes in, we will raise the SPL and then pin the
197 197 * current lwp to the processor. We will use its lwp, but our own interrupt
198 198 * stack and process the high level interrupt in-situ. These handlers are
199 199 * designed to be very short in nature and cannot go to sleep, only block on a
200 200 * spin lock. If the interrupt has a lot of work to do, it must generate a
201 201 * low-priority software interrupt that will be processed later.
202 202 *
203 203 * Low level hardware interrupts
204 204 *
205 205 * Low level hardware interrupts start off like their high-level cousins. The
206 206 * current CPU contains a number of kernel threads (kthread_t) that can be used
207 207 * to process low level interrupts. These are shared between both low level
208 208 * hardware and software interrupts. Note that while we run with our
209 209 * kthread_t, we borrow the pinned threads lwp_t until such a time as we hit a
210 210 * synchronization object. If we hit one and need to sleep, then the scheduler
211 211 * will instead create the rest of what we need.
212 212 *
213 213 * Low level software interrupts
214 214 *
215 215 * Low level software interrupts are handled in a similar way as hardware
216 216 * interrupts, but the notification vector is different. Each CPU has a bitmask
217 217 * of pending software interrupts. We can notify a CPU to process software
218 218 * interrupts through a specific trap vector as well as through several
219 219 * checks that are performed throughout the code. These checks will look at
220 220 * processing software interrupts as we lower our spl.
221 221 *
222 222 * We attempt to process the highest pending software interrupt that we can
223 223 * which is greater than our current IPL. If none currently exist, then we move
224 224 * on. We process a software interrupt in a similar fashion to a hardware
225 225 * interrupt.
226 226 *
227 227 * Traditional Interrupt Flow
228 228 * --------------------------
229 229 *
230 230 * The following diagram tracks the flow of the traditional uppc and pcplusmp
231 231 * interrupt handlers. The apix driver has its own version of do_interrupt().
232 232 * We come into the interrupt handler with all interrupts masked by the IF
233 233 * flag. This is because we set up the handler using an interrupt-gate, which
234 234 * is defined architecturally to have cleared the IF flag for us.
235 235 *
236 236 * +--------------+ +----------------+ +-----------+
237 237 * | _interrupt() |--->| do_interrupt() |--->| *setlvl() |
238 238 * +--------------+ +----------------+ +-----------+
239 239 * | | |
240 240 * | | |
241 241 * low-level| | | softint
242 242 * HW int | | +---------------------------------------+
243 243 * +--------------+ | | |
244 244 * | intr_thread_ |<-----+ | hi-level int |
245 245 * | prolog() | | +----------+ |
246 246 * +--------------+ +--->| hilevel_ | Not on intr stack |
247 247 * | | intr_ |-----------------+ |
248 248 * | | prolog() | | |
249 249 * +------------+ +----------+ | |
250 250 * | switch_sp_ | | On intr v |
251 251 * | and_call() | | Stack +------------+ |
252 252 * +------------+ | | switch_sp_ | |
253 253 * | v | and_call() | |
254 254 * v +-----------+ +------------+ |
255 255 * +-----------+ | dispatch_ | | |
256 256 * | dispatch_ | +-------------------| hilevel() |<------------+ |
257 257 * | hardint() | | +-----------+ |
258 258 * +-----------+ | |
259 259 * | v |
260 260 * | +-----+ +----------------------+ +-----+ hi-level |
261 261 * +---->| sti |->| av_dispatch_autovect |->| cli |---------+ |
262 262 * +-----+ +----------------------+ +-----+ | |
263 263 * | | | |
264 264 * v | | |
265 265 * +----------+ | | |
266 266 * | for each | | | |
267 267 * | handler | | | |
268 268 * | *intr() | | v |
269 269 * +--------------+ +----------+ | +----------------+ |
270 270 * | intr_thread_ | low-level | | hilevel_intr_ | |
271 271 * | epilog() |<-------------------------------+ | epilog() | |
272 272 * +--------------+ +----------------+ |
273 273 * | | | |
274 274 * | +----------------------v v---------------------+ |
275 275 * | +------------+ |
276 276 * | +---------------------->| *setlvlx() | |
277 277 * | | +------------+ |
278 278 * | | | |
279 279 * | | v |
280 280 * | | +--------+ +------------------+ +-------------+ |
281 281 * | | | return |<----| softint pending? |----->| dosoftint() |<-----+
282 282 * | | +--------+ no +------------------+ yes +-------------+
283 283 * | | ^ | |
284 284 * | | | softint pil too low | |
285 285 * | | +--------------------------------------+ |
286 286 * | | v
287 287 * | | +-----------+ +------------+ +-----------+
288 288 * | | | dispatch_ |<-----| switch_sp_ |<---------| *setspl() |
289 289 * | | | softint() | | and_call() | +-----------+
290 290 * | | +-----------+ +------------+
291 291 * | | |
292 292 * | | v
293 293 * | | +-----+ +----------------------+ +-----+ +------------+
294 294 * | | | sti |->| av_dispatch_autovect |->| cli |->| dosoftint_ |
295 295 * | | +-----+ +----------------------+ +-----+ | epilog() |
296 296 * | | +------------+
297 297 * | | | |
298 298 * | +----------------------------------------------------+ |
299 299 * v |
300 300 * +-----------+ |
301 301 * | interrupt | |
302 302 * | thread |<---------------------------------------------------+
303 303 * | blocked |
304 304 * +-----------+
305 305 * |
306 306 * v
307 307 * +----------------+ +------------+ +-----------+ +-------+ +---------+
308 308 * | set_base_spl() |->| *setlvlx() |->| splhigh() |->| sti() |->| swtch() |
309 309 * +----------------+ +------------+ +-----------+ +-------+ +---------+
310 310 *
311 311 * Calls made on Interrupt Stacks and Epilogue routines
312 312 *
313 313 * We use the switch_sp_and_call() assembly routine to switch our sp to the
314 314 * interrupt stacks and then call the appropriate dispatch function. In the
315 315 * case of interrupts which may block, softints and hardints, we always ensure
316 316 * that we are still on the interrupt thread when we call the epilog routine.
317 317 * This is not just important, it's necessary. If the interrupt thread blocked,
318 318 * we won't return from our switch_sp_and_call() function and instead we'll go
319 319 * through and set ourselves up to swtch() directly.
320 320 *
321 321 * New Interrupt Flow
322 322 * ------------------
323 323 *
324 324 * The apix module has its own interrupt path. This is done for various
325 325 * reasons. The first is that rather than having global interrupt vectors, we
326 326 * now have per-cpu vectors.
327 327 *
328 328 * The other substantial change is that the apix design does not use the TPR to
329 329 * mask interrupts below the current level. In fact, except for one special
330 330 * case, it does not use the TPR at all. Instead, it only uses the IF flag
331 331 * (cli/sti) to either block all interrupts or allow any interrupts to come in.
332 332 * The design is such that when interrupts are allowed to come in, if we are
333 333 * currently servicing a higher priority interupt, the new interrupt is treated
334 334 * as pending and serviced later. Specifically, in the pcplusmp module's
335 335 * apic_intr_enter() the code masks interrupts at or below the current
336 336 * IPL using the TPR before sending EOI, whereas the apix module's
337 337 * apix_intr_enter() simply sends EOI.
338 338 *
339 339 * The one special case where the apix code uses the TPR is when it calls
340 340 * through the apic_reg_ops function pointer apic_write_task_reg in
341 341 * apix_init_intr() to initially mask all levels and then finally to enable all
342 342 * levels.
343 343 *
344 344 * Recall that we come into the interrupt handler with all interrupts masked
345 345 * by the IF flag. This is because we set up the handler using an
346 346 * interrupt-gate which is defined architecturally to have cleared the IF flag
347 347 * for us.
348 348 *
349 349 * +--------------+ +---------------------+
350 350 * | _interrupt() |--->| apix_do_interrupt() |
351 351 * +--------------+ +---------------------+
352 352 * |
353 353 * hard int? +----+--------+ softint?
354 354 * | | (but no low-level looping)
355 355 * +-----------+ |
356 356 * | *setlvl() | |
357 357 * +---------+ +-----------+ +----------------------------------+
358 358 * |apix_add_| check IPL | |
359 359 * |pending_ |<-------------+------+----------------------+ |
360 360 * |hardint()| low-level int| hi-level int| |
361 361 * +---------+ v v |
362 362 * | check IPL +-----------------+ +---------------+ |
363 363 * +--+-----+ | apix_intr_ | | apix_hilevel_ | |
364 364 * | | | thread_prolog() | | intr_prolog() | |
365 365 * | return +-----------------+ +---------------+ |
366 366 * | | | On intr |
367 367 * | +------------+ | stack? +------------+ |
368 368 * | | switch_sp_ | +---------| switch_sp_ | |
369 369 * | | and_call() | | | and_call() | |
370 370 * | +------------+ | +------------+ |
371 371 * | | | | |
372 372 * | +----------------+ +----------------+ |
373 373 * | | apix_dispatch_ | | apix_dispatch_ | |
374 374 * | | lowlevel() | | hilevel() | |
375 375 * | +----------------+ +----------------+ |
376 376 * | | | |
377 377 * | v v |
378 378 * | +-------------------------+ |
379 379 * | |apix_dispatch_by_vector()|----+ |
380 380 * | +-------------------------+ | |
381 381 * | !XC_HI_PIL| | | | |
382 382 * | +---+ +-------+ +---+ | |
383 383 * | |sti| |*intr()| |cli| | |
384 384 * | +---+ +-------+ +---+ | hi-level? |
385 385 * | +---------------------------+----+ |
386 386 * | v low-level? v |
387 387 * | +----------------+ +----------------+ |
388 388 * | | apix_intr_ | | apix_hilevel_ | |
389 389 * | | thread_epilog()| | intr_epilog() | |
390 390 * | +----------------+ +----------------+ |
391 391 * | | | |
392 392 * | v-----------------+--------------------------------+ |
393 393 * | +------------+ |
394 394 * | | *setlvlx() | +----------------------------------------------------+
395 395 * | +------------+ |
396 396 * | | | +--------------------------------+ low
397 397 * v v v------+ v | level
398 398 * +------------------+ +------------------+ +-----------+ | pending?
399 399 * | apix_do_pending_ |----->| apix_do_pending_ |----->| apix_do_ |--+
400 400 * | hilevel() | | hardint() | | softint() | |
401 401 * +------------------+ +------------------+ +-----------+ return
402 402 * | | |
403 403 * | while pending | while pending | while pending
404 404 * | hi-level | low-level | softint
405 405 * | | |
406 406 * +---------------+ +-----------------+ +-----------------+
407 407 * | apix_hilevel_ | | apix_intr_ | | apix_do_ |
408 408 * | intr_prolog() | | thread_prolog() | | softint_prolog()|
409 409 * +---------------+ +-----------------+ +-----------------+
410 410 * | On intr | |
411 411 * | stack? +------------+ +------------+ +------------+
412 412 * +--------| switch_sp_ | | switch_sp_ | | switch_sp_ |
413 413 * | | and_call() | | and_call() | | and_call() |
414 414 * | +------------+ +------------+ +------------+
415 415 * | | | |
416 416 * +------------------+ +------------------+ +------------------------+
417 417 * | apix_dispatch_ | | apix_dispatch_ | | apix_dispatch_softint()|
418 418 * | pending_hilevel()| | pending_hardint()| +------------------------+
419 419 * +------------------+ +------------------+ | | | |
420 420 * | | | | | | | |
421 421 * | +----------------+ | +----------------+ | | | |
422 422 * | | apix_hilevel_ | | | apix_intr_ | | | | |
423 423 * | | intr_epilog() | | | thread_epilog()| | | | |
424 424 * | +----------------+ | +----------------+ | | | |
425 425 * | | | | | | | |
426 426 * | +------------+ | +----------+ +------+ | | |
427 427 * | | *setlvlx() | | |*setlvlx()| | | | |
428 428 * | +------------+ | +----------+ | +----------+ | +---------+
429 429 * | | +---+ |av_ | +---+ |apix_do_ |
430 430 * +---------------------------------+ |sti| |dispatch_ | |cli| |softint_ |
431 431 * | apix_dispatch_pending_autovect()| +---+ |softvect()| +---+ |epilog() |
432 432 * +---------------------------------+ +----------+ +---------+
433 433 * |!XC_HI_PIL | | | |
434 434 * +---+ +-------+ +---+ +----------+ +-------+
435 435 * |sti| |*intr()| |cli| |apix_post_| |*intr()|
436 436 * +---+ +-------+ +---+ |hardint() | +-------+
437 437 * +----------+
438 438 */
439 439
440 440 #include <sys/cpuvar.h>
441 441 #include <sys/cpu_event.h>
442 442 #include <sys/regset.h>
443 443 #include <sys/psw.h>
444 444 #include <sys/types.h>
445 445 #include <sys/thread.h>
446 446 #include <sys/systm.h>
447 447 #include <sys/segments.h>
448 448 #include <sys/pcb.h>
449 449 #include <sys/trap.h>
450 450 #include <sys/ftrace.h>
451 451 #include <sys/traptrace.h>
452 452 #include <sys/clock.h>
453 453 #include <sys/panic.h>
454 454 #include <sys/disp.h>
455 455 #include <vm/seg_kp.h>
456 456 #include <sys/stack.h>
457 457 #include <sys/sysmacros.h>
458 458 #include <sys/cmn_err.h>
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459 459 #include <sys/kstat.h>
460 460 #include <sys/smp_impldefs.h>
461 461 #include <sys/pool_pset.h>
462 462 #include <sys/zone.h>
463 463 #include <sys/bitmap.h>
464 464 #include <sys/archsystm.h>
465 465 #include <sys/machsystm.h>
466 466 #include <sys/ontrap.h>
467 467 #include <sys/x86_archext.h>
468 468 #include <sys/promif.h>
469 +#include <sys/ht.h>
469 470 #include <vm/hat_i86.h>
470 471 #if defined(__xpv)
471 472 #include <sys/hypervisor.h>
472 473 #endif
473 474
474 -#if defined(__amd64) && !defined(__xpv)
475 -/* If this fails, then the padding numbers in machcpuvar.h are wrong. */
476 -CTASSERT((offsetof(cpu_t, cpu_m) + offsetof(struct machcpu, mcpu_pad)) <
477 - MMU_PAGESIZE);
478 -CTASSERT((offsetof(cpu_t, cpu_m) + offsetof(struct machcpu, mcpu_kpti)) >=
479 - MMU_PAGESIZE);
480 -CTASSERT((offsetof(cpu_t, cpu_m) + offsetof(struct machcpu, mcpu_kpti_dbg)) <
481 - 2 * MMU_PAGESIZE);
482 -CTASSERT((offsetof(cpu_t, cpu_m) + offsetof(struct machcpu, mcpu_pad2)) <
483 - 2 * MMU_PAGESIZE);
475 +/* If these fail, then the padding numbers in machcpuvar.h are wrong. */
476 +#if !defined(__xpv)
477 +#define MCOFF(member) \
478 + (offsetof(cpu_t, cpu_m) + offsetof(struct machcpu, member))
479 +CTASSERT(MCOFF(mcpu_pad) == MACHCPU_SIZE);
480 +CTASSERT(MCOFF(mcpu_pad2) == MMU_PAGESIZE);
481 +CTASSERT((MCOFF(mcpu_kpti) & 0xF) == 0);
484 482 CTASSERT(((sizeof (struct kpti_frame)) & 0xF) == 0);
485 -CTASSERT(((offsetof(cpu_t, cpu_m) +
486 - offsetof(struct machcpu, mcpu_kpti_dbg)) & 0xF) == 0);
487 483 CTASSERT((offsetof(struct kpti_frame, kf_tr_rsp) & 0xF) == 0);
484 +CTASSERT(MCOFF(mcpu_pad3) < 2 * MMU_PAGESIZE);
488 485 #endif
489 486
490 487 #if defined(__xpv) && defined(DEBUG)
491 488
492 489 /*
493 490 * This panic message is intended as an aid to interrupt debugging.
494 491 *
495 492 * The associated assertion tests the condition of enabling
496 493 * events when events are already enabled. The implication
497 494 * being that whatever code the programmer thought was
498 495 * protected by having events disabled until the second
499 496 * enable happened really wasn't protected at all ..
500 497 */
501 498
502 499 int stistipanic = 1; /* controls the debug panic check */
503 500 const char *stistimsg = "stisti";
504 501 ulong_t laststi[NCPU];
505 502
506 503 /*
507 504 * This variable tracks the last place events were disabled on each cpu
508 505 * it assists in debugging when asserts that interrupts are enabled trip.
509 506 */
510 507 ulong_t lastcli[NCPU];
511 508
512 509 #endif
513 510
514 511 void do_interrupt(struct regs *rp, trap_trace_rec_t *ttp);
515 512
516 513 void (*do_interrupt_common)(struct regs *, trap_trace_rec_t *) = do_interrupt;
517 514 uintptr_t (*get_intr_handler)(int, short) = NULL;
518 515
519 516 /*
520 517 * Set cpu's base SPL level to the highest active interrupt level
521 518 */
522 519 void
523 520 set_base_spl(void)
524 521 {
525 522 struct cpu *cpu = CPU;
526 523 uint16_t active = (uint16_t)cpu->cpu_intr_actv;
527 524
528 525 cpu->cpu_base_spl = active == 0 ? 0 : bsrw_insn(active);
529 526 }
530 527
531 528 /*
532 529 * Do all the work necessary to set up the cpu and thread structures
533 530 * to dispatch a high-level interrupt.
534 531 *
535 532 * Returns 0 if we're -not- already on the high-level interrupt stack,
536 533 * (and *must* switch to it), non-zero if we are already on that stack.
537 534 *
538 535 * Called with interrupts masked.
539 536 * The 'pil' is already set to the appropriate level for rp->r_trapno.
540 537 */
541 538 static int
542 539 hilevel_intr_prolog(struct cpu *cpu, uint_t pil, uint_t oldpil, struct regs *rp)
543 540 {
544 541 struct machcpu *mcpu = &cpu->cpu_m;
545 542 uint_t mask;
546 543 hrtime_t intrtime;
547 544 hrtime_t now = tsc_read();
548 545
549 546 ASSERT(pil > LOCK_LEVEL);
550 547
551 548 if (pil == CBE_HIGH_PIL) {
552 549 cpu->cpu_profile_pil = oldpil;
553 550 if (USERMODE(rp->r_cs)) {
554 551 cpu->cpu_profile_pc = 0;
555 552 cpu->cpu_profile_upc = rp->r_pc;
556 553 cpu->cpu_cpcprofile_pc = 0;
557 554 cpu->cpu_cpcprofile_upc = rp->r_pc;
558 555 } else {
559 556 cpu->cpu_profile_pc = rp->r_pc;
560 557 cpu->cpu_profile_upc = 0;
561 558 cpu->cpu_cpcprofile_pc = rp->r_pc;
562 559 cpu->cpu_cpcprofile_upc = 0;
563 560 }
564 561 }
565 562
566 563 mask = cpu->cpu_intr_actv & CPU_INTR_ACTV_HIGH_LEVEL_MASK;
567 564 if (mask != 0) {
568 565 int nestpil;
569 566
570 567 /*
571 568 * We have interrupted another high-level interrupt.
572 569 * Load starting timestamp, compute interval, update
573 570 * cumulative counter.
574 571 */
575 572 nestpil = bsrw_insn((uint16_t)mask);
576 573 ASSERT(nestpil < pil);
577 574 intrtime = now -
578 575 mcpu->pil_high_start[nestpil - (LOCK_LEVEL + 1)];
579 576 mcpu->intrstat[nestpil][0] += intrtime;
580 577 cpu->cpu_intracct[cpu->cpu_mstate] += intrtime;
581 578 /*
582 579 * Another high-level interrupt is active below this one, so
583 580 * there is no need to check for an interrupt thread. That
584 581 * will be done by the lowest priority high-level interrupt
585 582 * active.
586 583 */
587 584 } else {
588 585 kthread_t *t = cpu->cpu_thread;
589 586
590 587 /*
591 588 * See if we are interrupting a low-level interrupt thread.
592 589 * If so, account for its time slice only if its time stamp
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593 590 * is non-zero.
594 591 */
595 592 if ((t->t_flag & T_INTR_THREAD) != 0 && t->t_intr_start != 0) {
596 593 intrtime = now - t->t_intr_start;
597 594 mcpu->intrstat[t->t_pil][0] += intrtime;
598 595 cpu->cpu_intracct[cpu->cpu_mstate] += intrtime;
599 596 t->t_intr_start = 0;
600 597 }
601 598 }
602 599
600 + ht_begin_intr(pil);
601 +
603 602 /*
604 603 * Store starting timestamp in CPU structure for this PIL.
605 604 */
606 605 mcpu->pil_high_start[pil - (LOCK_LEVEL + 1)] = now;
607 606
608 607 ASSERT((cpu->cpu_intr_actv & (1 << pil)) == 0);
609 608
610 609 if (pil == 15) {
611 610 /*
612 611 * To support reentrant level 15 interrupts, we maintain a
613 612 * recursion count in the top half of cpu_intr_actv. Only
614 613 * when this count hits zero do we clear the PIL 15 bit from
615 614 * the lower half of cpu_intr_actv.
616 615 */
617 616 uint16_t *refcntp = (uint16_t *)&cpu->cpu_intr_actv + 1;
618 617 (*refcntp)++;
619 618 }
620 619
621 620 mask = cpu->cpu_intr_actv;
622 621
623 622 cpu->cpu_intr_actv |= (1 << pil);
624 623
625 624 return (mask & CPU_INTR_ACTV_HIGH_LEVEL_MASK);
626 625 }
627 626
628 627 /*
629 628 * Does most of the work of returning from a high level interrupt.
630 629 *
631 630 * Returns 0 if there are no more high level interrupts (in which
632 631 * case we must switch back to the interrupted thread stack) or
633 632 * non-zero if there are more (in which case we should stay on it).
634 633 *
635 634 * Called with interrupts masked
636 635 */
637 636 static int
638 637 hilevel_intr_epilog(struct cpu *cpu, uint_t pil, uint_t oldpil, uint_t vecnum)
639 638 {
640 639 struct machcpu *mcpu = &cpu->cpu_m;
641 640 uint_t mask;
642 641 hrtime_t intrtime;
643 642 hrtime_t now = tsc_read();
644 643
645 644 ASSERT(mcpu->mcpu_pri == pil);
646 645
647 646 cpu->cpu_stats.sys.intr[pil - 1]++;
648 647
649 648 ASSERT(cpu->cpu_intr_actv & (1 << pil));
650 649
651 650 if (pil == 15) {
652 651 /*
653 652 * To support reentrant level 15 interrupts, we maintain a
654 653 * recursion count in the top half of cpu_intr_actv. Only
655 654 * when this count hits zero do we clear the PIL 15 bit from
656 655 * the lower half of cpu_intr_actv.
657 656 */
658 657 uint16_t *refcntp = (uint16_t *)&cpu->cpu_intr_actv + 1;
659 658
660 659 ASSERT(*refcntp > 0);
661 660
662 661 if (--(*refcntp) == 0)
663 662 cpu->cpu_intr_actv &= ~(1 << pil);
664 663 } else {
665 664 cpu->cpu_intr_actv &= ~(1 << pil);
666 665 }
667 666
668 667 ASSERT(mcpu->pil_high_start[pil - (LOCK_LEVEL + 1)] != 0);
669 668
670 669 intrtime = now - mcpu->pil_high_start[pil - (LOCK_LEVEL + 1)];
671 670 mcpu->intrstat[pil][0] += intrtime;
672 671 cpu->cpu_intracct[cpu->cpu_mstate] += intrtime;
673 672
674 673 /*
675 674 * Check for lower-pil nested high-level interrupt beneath
676 675 * current one. If so, place a starting timestamp in its
677 676 * pil_high_start entry.
678 677 */
679 678 mask = cpu->cpu_intr_actv & CPU_INTR_ACTV_HIGH_LEVEL_MASK;
680 679 if (mask != 0) {
681 680 int nestpil;
682 681
683 682 /*
684 683 * find PIL of nested interrupt
685 684 */
686 685 nestpil = bsrw_insn((uint16_t)mask);
687 686 ASSERT(nestpil < pil);
688 687 mcpu->pil_high_start[nestpil - (LOCK_LEVEL + 1)] = now;
689 688 /*
690 689 * (Another high-level interrupt is active below this one,
691 690 * so there is no need to check for an interrupt
692 691 * thread. That will be done by the lowest priority
693 692 * high-level interrupt active.)
694 693 */
695 694 } else {
696 695 /*
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697 696 * Check to see if there is a low-level interrupt active.
698 697 * If so, place a starting timestamp in the thread
699 698 * structure.
700 699 */
701 700 kthread_t *t = cpu->cpu_thread;
702 701
703 702 if (t->t_flag & T_INTR_THREAD)
704 703 t->t_intr_start = now;
705 704 }
706 705
706 + ht_end_intr();
707 +
707 708 mcpu->mcpu_pri = oldpil;
708 709 (void) (*setlvlx)(oldpil, vecnum);
709 710
710 711 return (cpu->cpu_intr_actv & CPU_INTR_ACTV_HIGH_LEVEL_MASK);
711 712 }
712 713
713 714 /*
714 715 * Set up the cpu, thread and interrupt thread structures for
715 716 * executing an interrupt thread. The new stack pointer of the
716 717 * interrupt thread (which *must* be switched to) is returned.
717 718 */
718 719 static caddr_t
719 720 intr_thread_prolog(struct cpu *cpu, caddr_t stackptr, uint_t pil)
720 721 {
721 722 struct machcpu *mcpu = &cpu->cpu_m;
722 723 kthread_t *t, *volatile it;
723 724 hrtime_t now = tsc_read();
724 725
725 726 ASSERT(pil > 0);
726 727 ASSERT((cpu->cpu_intr_actv & (1 << pil)) == 0);
727 728 cpu->cpu_intr_actv |= (1 << pil);
728 729
729 730 /*
730 731 * Get set to run an interrupt thread.
731 732 * There should always be an interrupt thread, since we
732 733 * allocate one for each level on each CPU.
733 734 *
734 735 * t_intr_start could be zero due to cpu_intr_swtch_enter.
735 736 */
736 737 t = cpu->cpu_thread;
737 738 if ((t->t_flag & T_INTR_THREAD) && t->t_intr_start != 0) {
738 739 hrtime_t intrtime = now - t->t_intr_start;
739 740 mcpu->intrstat[t->t_pil][0] += intrtime;
740 741 cpu->cpu_intracct[cpu->cpu_mstate] += intrtime;
741 742 t->t_intr_start = 0;
742 743 }
743 744
744 745 ASSERT(SA((uintptr_t)stackptr) == (uintptr_t)stackptr);
745 746
746 747 t->t_sp = (uintptr_t)stackptr; /* mark stack in curthread for resume */
747 748
748 749 /*
749 750 * unlink the interrupt thread off the cpu
750 751 *
751 752 * Note that the code in kcpc_overflow_intr -relies- on the
752 753 * ordering of events here - in particular that t->t_lwp of
753 754 * the interrupt thread is set to the pinned thread *before*
754 755 * curthread is changed.
755 756 */
756 757 it = cpu->cpu_intr_thread;
757 758 cpu->cpu_intr_thread = it->t_link;
758 759 it->t_intr = t;
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759 760 it->t_lwp = t->t_lwp;
760 761
761 762 /*
762 763 * (threads on the interrupt thread free list could have state
763 764 * preset to TS_ONPROC, but it helps in debugging if
764 765 * they're TS_FREE.)
765 766 */
766 767 it->t_state = TS_ONPROC;
767 768
768 769 cpu->cpu_thread = it; /* new curthread on this cpu */
770 + ht_begin_intr(pil);
771 +
769 772 it->t_pil = (uchar_t)pil;
770 773 it->t_pri = intr_pri + (pri_t)pil;
771 774 it->t_intr_start = now;
772 775
773 776 return (it->t_stk);
774 777 }
775 778
776 779
777 780 #ifdef DEBUG
778 781 int intr_thread_cnt;
779 782 #endif
780 783
781 784 /*
782 785 * Called with interrupts disabled
783 786 */
784 787 static void
785 788 intr_thread_epilog(struct cpu *cpu, uint_t vec, uint_t oldpil)
786 789 {
787 790 struct machcpu *mcpu = &cpu->cpu_m;
788 791 kthread_t *t;
789 792 kthread_t *it = cpu->cpu_thread; /* curthread */
790 793 uint_t pil, basespl;
791 794 hrtime_t intrtime;
792 795 hrtime_t now = tsc_read();
793 796
794 797 pil = it->t_pil;
795 798 cpu->cpu_stats.sys.intr[pil - 1]++;
796 799
797 800 ASSERT(it->t_intr_start != 0);
798 801 intrtime = now - it->t_intr_start;
799 802 mcpu->intrstat[pil][0] += intrtime;
800 803 cpu->cpu_intracct[cpu->cpu_mstate] += intrtime;
801 804
802 805 ASSERT(cpu->cpu_intr_actv & (1 << pil));
803 806 cpu->cpu_intr_actv &= ~(1 << pil);
804 807
805 808 /*
806 809 * If there is still an interrupted thread underneath this one
807 810 * then the interrupt was never blocked and the return is
808 811 * fairly simple. Otherwise it isn't.
809 812 */
810 813 if ((t = it->t_intr) == NULL) {
811 814 /*
812 815 * The interrupted thread is no longer pinned underneath
813 816 * the interrupt thread. This means the interrupt must
814 817 * have blocked, and the interrupted thread has been
815 818 * unpinned, and has probably been running around the
816 819 * system for a while.
817 820 *
818 821 * Since there is no longer a thread under this one, put
819 822 * this interrupt thread back on the CPU's free list and
820 823 * resume the idle thread which will dispatch the next
821 824 * thread to run.
822 825 */
823 826 #ifdef DEBUG
824 827 intr_thread_cnt++;
825 828 #endif
826 829 cpu->cpu_stats.sys.intrblk++;
827 830 /*
828 831 * Set CPU's base SPL based on active interrupts bitmask
829 832 */
830 833 set_base_spl();
831 834 basespl = cpu->cpu_base_spl;
832 835 mcpu->mcpu_pri = basespl;
833 836 (*setlvlx)(basespl, vec);
834 837 (void) splhigh();
835 838 sti();
836 839 it->t_state = TS_FREE;
837 840 /*
838 841 * Return interrupt thread to pool
839 842 */
840 843 it->t_link = cpu->cpu_intr_thread;
841 844 cpu->cpu_intr_thread = it;
842 845 swtch();
843 846 panic("intr_thread_epilog: swtch returned");
844 847 /*NOTREACHED*/
845 848 }
846 849
847 850 /*
848 851 * Return interrupt thread to the pool
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849 852 */
850 853 it->t_link = cpu->cpu_intr_thread;
851 854 cpu->cpu_intr_thread = it;
852 855 it->t_state = TS_FREE;
853 856
854 857 basespl = cpu->cpu_base_spl;
855 858 pil = MAX(oldpil, basespl);
856 859 mcpu->mcpu_pri = pil;
857 860 (*setlvlx)(pil, vec);
858 861 t->t_intr_start = now;
862 + ht_end_intr();
859 863 cpu->cpu_thread = t;
860 864 }
861 865
862 866 /*
863 867 * intr_get_time() is a resource for interrupt handlers to determine how
864 868 * much time has been spent handling the current interrupt. Such a function
865 869 * is needed because higher level interrupts can arrive during the
866 870 * processing of an interrupt. intr_get_time() only returns time spent in the
867 871 * current interrupt handler.
868 872 *
869 873 * The caller must be calling from an interrupt handler running at a pil
870 874 * below or at lock level. Timings are not provided for high-level
871 875 * interrupts.
872 876 *
873 877 * The first time intr_get_time() is called while handling an interrupt,
874 878 * it returns the time since the interrupt handler was invoked. Subsequent
875 879 * calls will return the time since the prior call to intr_get_time(). Time
876 880 * is returned as ticks. Use scalehrtimef() to convert ticks to nsec.
877 881 *
878 882 * Theory Of Intrstat[][]:
879 883 *
880 884 * uint64_t intrstat[pil][0..1] is an array indexed by pil level, with two
881 885 * uint64_ts per pil.
882 886 *
883 887 * intrstat[pil][0] is a cumulative count of the number of ticks spent
884 888 * handling all interrupts at the specified pil on this CPU. It is
885 889 * exported via kstats to the user.
886 890 *
887 891 * intrstat[pil][1] is always a count of ticks less than or equal to the
888 892 * value in [0]. The difference between [1] and [0] is the value returned
889 893 * by a call to intr_get_time(). At the start of interrupt processing,
890 894 * [0] and [1] will be equal (or nearly so). As the interrupt consumes
891 895 * time, [0] will increase, but [1] will remain the same. A call to
892 896 * intr_get_time() will return the difference, then update [1] to be the
893 897 * same as [0]. Future calls will return the time since the last call.
894 898 * Finally, when the interrupt completes, [1] is updated to the same as [0].
895 899 *
896 900 * Implementation:
897 901 *
898 902 * intr_get_time() works much like a higher level interrupt arriving. It
899 903 * "checkpoints" the timing information by incrementing intrstat[pil][0]
900 904 * to include elapsed running time, and by setting t_intr_start to rdtsc.
901 905 * It then sets the return value to intrstat[pil][0] - intrstat[pil][1],
902 906 * and updates intrstat[pil][1] to be the same as the new value of
903 907 * intrstat[pil][0].
904 908 *
905 909 * In the normal handling of interrupts, after an interrupt handler returns
906 910 * and the code in intr_thread() updates intrstat[pil][0], it then sets
907 911 * intrstat[pil][1] to the new value of intrstat[pil][0]. When [0] == [1],
908 912 * the timings are reset, i.e. intr_get_time() will return [0] - [1] which
909 913 * is 0.
910 914 *
911 915 * Whenever interrupts arrive on a CPU which is handling a lower pil
912 916 * interrupt, they update the lower pil's [0] to show time spent in the
913 917 * handler that they've interrupted. This results in a growing discrepancy
914 918 * between [0] and [1], which is returned the next time intr_get_time() is
915 919 * called. Time spent in the higher-pil interrupt will not be returned in
916 920 * the next intr_get_time() call from the original interrupt, because
917 921 * the higher-pil interrupt's time is accumulated in intrstat[higherpil][].
918 922 */
919 923 uint64_t
920 924 intr_get_time(void)
921 925 {
922 926 struct cpu *cpu;
923 927 struct machcpu *mcpu;
924 928 kthread_t *t;
925 929 uint64_t time, delta, ret;
926 930 uint_t pil;
927 931
928 932 cli();
929 933 cpu = CPU;
930 934 mcpu = &cpu->cpu_m;
931 935 t = cpu->cpu_thread;
932 936 pil = t->t_pil;
933 937 ASSERT((cpu->cpu_intr_actv & CPU_INTR_ACTV_HIGH_LEVEL_MASK) == 0);
934 938 ASSERT(t->t_flag & T_INTR_THREAD);
935 939 ASSERT(pil != 0);
936 940 ASSERT(t->t_intr_start != 0);
937 941
938 942 time = tsc_read();
939 943 delta = time - t->t_intr_start;
940 944 t->t_intr_start = time;
941 945
942 946 time = mcpu->intrstat[pil][0] + delta;
943 947 ret = time - mcpu->intrstat[pil][1];
944 948 mcpu->intrstat[pil][0] = time;
945 949 mcpu->intrstat[pil][1] = time;
946 950 cpu->cpu_intracct[cpu->cpu_mstate] += delta;
947 951
948 952 sti();
949 953 return (ret);
950 954 }
951 955
952 956 static caddr_t
953 957 dosoftint_prolog(
954 958 struct cpu *cpu,
955 959 caddr_t stackptr,
956 960 uint32_t st_pending,
957 961 uint_t oldpil)
958 962 {
959 963 kthread_t *t, *volatile it;
960 964 struct machcpu *mcpu = &cpu->cpu_m;
961 965 uint_t pil;
962 966 hrtime_t now;
963 967
964 968 top:
965 969 ASSERT(st_pending == mcpu->mcpu_softinfo.st_pending);
966 970
967 971 pil = bsrw_insn((uint16_t)st_pending);
968 972 if (pil <= oldpil || pil <= cpu->cpu_base_spl)
969 973 return (0);
970 974
971 975 /*
972 976 * XX64 Sigh.
973 977 *
974 978 * This is a transliteration of the i386 assembler code for
975 979 * soft interrupts. One question is "why does this need
976 980 * to be atomic?" One possible race is -other- processors
977 981 * posting soft interrupts to us in set_pending() i.e. the
978 982 * CPU might get preempted just after the address computation,
979 983 * but just before the atomic transaction, so another CPU would
980 984 * actually set the original CPU's st_pending bit. However,
981 985 * it looks like it would be simpler to disable preemption there.
982 986 * Are there other races for which preemption control doesn't work?
983 987 *
984 988 * The i386 assembler version -also- checks to see if the bit
985 989 * being cleared was actually set; if it wasn't, it rechecks
986 990 * for more. This seems a bit strange, as the only code that
987 991 * ever clears the bit is -this- code running with interrupts
988 992 * disabled on -this- CPU. This code would probably be cheaper:
989 993 *
990 994 * atomic_and_32((uint32_t *)&mcpu->mcpu_softinfo.st_pending,
991 995 * ~(1 << pil));
992 996 *
993 997 * and t->t_preempt--/++ around set_pending() even cheaper,
994 998 * but at this point, correctness is critical, so we slavishly
995 999 * emulate the i386 port.
996 1000 */
997 1001 if (atomic_btr32((uint32_t *)
998 1002 &mcpu->mcpu_softinfo.st_pending, pil) == 0) {
999 1003 st_pending = mcpu->mcpu_softinfo.st_pending;
1000 1004 goto top;
1001 1005 }
1002 1006
1003 1007 mcpu->mcpu_pri = pil;
1004 1008 (*setspl)(pil);
1005 1009
1006 1010 now = tsc_read();
1007 1011
1008 1012 /*
1009 1013 * Get set to run interrupt thread.
1010 1014 * There should always be an interrupt thread since we
1011 1015 * allocate one for each level on the CPU.
1012 1016 */
1013 1017 it = cpu->cpu_intr_thread;
1014 1018 cpu->cpu_intr_thread = it->t_link;
1015 1019
1016 1020 /* t_intr_start could be zero due to cpu_intr_swtch_enter. */
1017 1021 t = cpu->cpu_thread;
1018 1022 if ((t->t_flag & T_INTR_THREAD) && t->t_intr_start != 0) {
1019 1023 hrtime_t intrtime = now - t->t_intr_start;
1020 1024 mcpu->intrstat[pil][0] += intrtime;
1021 1025 cpu->cpu_intracct[cpu->cpu_mstate] += intrtime;
1022 1026 t->t_intr_start = 0;
1023 1027 }
1024 1028
1025 1029 /*
1026 1030 * Note that the code in kcpc_overflow_intr -relies- on the
1027 1031 * ordering of events here - in particular that t->t_lwp of
1028 1032 * the interrupt thread is set to the pinned thread *before*
1029 1033 * curthread is changed.
1030 1034 */
1031 1035 it->t_lwp = t->t_lwp;
1032 1036 it->t_state = TS_ONPROC;
1033 1037
1034 1038 /*
1035 1039 * Push interrupted thread onto list from new thread.
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1036 1040 * Set the new thread as the current one.
1037 1041 * Set interrupted thread's T_SP because if it is the idle thread,
1038 1042 * resume() may use that stack between threads.
1039 1043 */
1040 1044
1041 1045 ASSERT(SA((uintptr_t)stackptr) == (uintptr_t)stackptr);
1042 1046 t->t_sp = (uintptr_t)stackptr;
1043 1047
1044 1048 it->t_intr = t;
1045 1049 cpu->cpu_thread = it;
1050 + ht_begin_intr(pil);
1046 1051
1047 1052 /*
1048 1053 * Set bit for this pil in CPU's interrupt active bitmask.
1049 1054 */
1050 1055 ASSERT((cpu->cpu_intr_actv & (1 << pil)) == 0);
1051 1056 cpu->cpu_intr_actv |= (1 << pil);
1052 1057
1053 1058 /*
1054 1059 * Initialize thread priority level from intr_pri
1055 1060 */
1056 1061 it->t_pil = (uchar_t)pil;
1057 1062 it->t_pri = (pri_t)pil + intr_pri;
1058 1063 it->t_intr_start = now;
1059 1064
1060 1065 return (it->t_stk);
1061 1066 }
1062 1067
1063 1068 static void
1064 1069 dosoftint_epilog(struct cpu *cpu, uint_t oldpil)
1065 1070 {
1066 1071 struct machcpu *mcpu = &cpu->cpu_m;
1067 1072 kthread_t *t, *it;
1068 1073 uint_t pil, basespl;
1069 1074 hrtime_t intrtime;
1070 1075 hrtime_t now = tsc_read();
1071 1076
1072 1077 it = cpu->cpu_thread;
1073 1078 pil = it->t_pil;
1074 1079
1075 1080 cpu->cpu_stats.sys.intr[pil - 1]++;
1076 1081
1077 1082 ASSERT(cpu->cpu_intr_actv & (1 << pil));
1078 1083 cpu->cpu_intr_actv &= ~(1 << pil);
1079 1084 intrtime = now - it->t_intr_start;
1080 1085 mcpu->intrstat[pil][0] += intrtime;
1081 1086 cpu->cpu_intracct[cpu->cpu_mstate] += intrtime;
1082 1087
1083 1088 /*
1084 1089 * If there is still an interrupted thread underneath this one
1085 1090 * then the interrupt was never blocked and the return is
1086 1091 * fairly simple. Otherwise it isn't.
1087 1092 */
1088 1093 if ((t = it->t_intr) == NULL) {
1089 1094 /*
1090 1095 * Put thread back on the interrupt thread list.
1091 1096 * This was an interrupt thread, so set CPU's base SPL.
1092 1097 */
1093 1098 set_base_spl();
1094 1099 it->t_state = TS_FREE;
1095 1100 it->t_link = cpu->cpu_intr_thread;
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1096 1101 cpu->cpu_intr_thread = it;
1097 1102 (void) splhigh();
1098 1103 sti();
1099 1104 swtch();
1100 1105 /*NOTREACHED*/
1101 1106 panic("dosoftint_epilog: swtch returned");
1102 1107 }
1103 1108 it->t_link = cpu->cpu_intr_thread;
1104 1109 cpu->cpu_intr_thread = it;
1105 1110 it->t_state = TS_FREE;
1111 + ht_end_intr();
1106 1112 cpu->cpu_thread = t;
1113 +
1107 1114 if (t->t_flag & T_INTR_THREAD)
1108 1115 t->t_intr_start = now;
1109 1116 basespl = cpu->cpu_base_spl;
1110 1117 pil = MAX(oldpil, basespl);
1111 1118 mcpu->mcpu_pri = pil;
1112 1119 (*setspl)(pil);
1113 1120 }
1114 1121
1115 1122
1116 1123 /*
1117 1124 * Make the interrupted thread 'to' be runnable.
1118 1125 *
1119 1126 * Since t->t_sp has already been saved, t->t_pc is all
1120 1127 * that needs to be set in this function.
1121 1128 *
1122 1129 * Returns the interrupt level of the interrupt thread.
1123 1130 */
1124 1131 int
1125 1132 intr_passivate(
1126 1133 kthread_t *it, /* interrupt thread */
1127 1134 kthread_t *t) /* interrupted thread */
1128 1135 {
1129 1136 extern void _sys_rtt();
1130 1137
1131 1138 ASSERT(it->t_flag & T_INTR_THREAD);
1132 1139 ASSERT(SA(t->t_sp) == t->t_sp);
1133 1140
1134 1141 t->t_pc = (uintptr_t)_sys_rtt;
1135 1142 return (it->t_pil);
1136 1143 }
1137 1144
1138 1145 /*
1139 1146 * Create interrupt kstats for this CPU.
1140 1147 */
1141 1148 void
1142 1149 cpu_create_intrstat(cpu_t *cp)
1143 1150 {
1144 1151 int i;
1145 1152 kstat_t *intr_ksp;
1146 1153 kstat_named_t *knp;
1147 1154 char name[KSTAT_STRLEN];
1148 1155 zoneid_t zoneid;
1149 1156
1150 1157 ASSERT(MUTEX_HELD(&cpu_lock));
1151 1158
1152 1159 if (pool_pset_enabled())
1153 1160 zoneid = GLOBAL_ZONEID;
1154 1161 else
1155 1162 zoneid = ALL_ZONES;
1156 1163
1157 1164 intr_ksp = kstat_create_zone("cpu", cp->cpu_id, "intrstat", "misc",
1158 1165 KSTAT_TYPE_NAMED, PIL_MAX * 2, 0, zoneid);
1159 1166
1160 1167 /*
1161 1168 * Initialize each PIL's named kstat
1162 1169 */
1163 1170 if (intr_ksp != NULL) {
1164 1171 intr_ksp->ks_update = cpu_kstat_intrstat_update;
1165 1172 knp = (kstat_named_t *)intr_ksp->ks_data;
1166 1173 intr_ksp->ks_private = cp;
1167 1174 for (i = 0; i < PIL_MAX; i++) {
1168 1175 (void) snprintf(name, KSTAT_STRLEN, "level-%d-time",
1169 1176 i + 1);
1170 1177 kstat_named_init(&knp[i * 2], name, KSTAT_DATA_UINT64);
1171 1178 (void) snprintf(name, KSTAT_STRLEN, "level-%d-count",
1172 1179 i + 1);
1173 1180 kstat_named_init(&knp[(i * 2) + 1], name,
1174 1181 KSTAT_DATA_UINT64);
1175 1182 }
1176 1183 kstat_install(intr_ksp);
1177 1184 }
1178 1185 }
1179 1186
1180 1187 /*
1181 1188 * Delete interrupt kstats for this CPU.
1182 1189 */
1183 1190 void
1184 1191 cpu_delete_intrstat(cpu_t *cp)
1185 1192 {
1186 1193 kstat_delete_byname_zone("cpu", cp->cpu_id, "intrstat", ALL_ZONES);
1187 1194 }
1188 1195
1189 1196 /*
1190 1197 * Convert interrupt statistics from CPU ticks to nanoseconds and
1191 1198 * update kstat.
1192 1199 */
1193 1200 int
1194 1201 cpu_kstat_intrstat_update(kstat_t *ksp, int rw)
1195 1202 {
1196 1203 kstat_named_t *knp = ksp->ks_data;
1197 1204 cpu_t *cpup = (cpu_t *)ksp->ks_private;
1198 1205 int i;
1199 1206 hrtime_t hrt;
1200 1207
1201 1208 if (rw == KSTAT_WRITE)
1202 1209 return (EACCES);
1203 1210
1204 1211 for (i = 0; i < PIL_MAX; i++) {
1205 1212 hrt = (hrtime_t)cpup->cpu_m.intrstat[i + 1][0];
1206 1213 scalehrtimef(&hrt);
1207 1214 knp[i * 2].value.ui64 = (uint64_t)hrt;
1208 1215 knp[(i * 2) + 1].value.ui64 = cpup->cpu_stats.sys.intr[i];
1209 1216 }
1210 1217
1211 1218 return (0);
1212 1219 }
1213 1220
1214 1221 /*
1215 1222 * An interrupt thread is ending a time slice, so compute the interval it
1216 1223 * ran for and update the statistic for its PIL.
1217 1224 */
1218 1225 void
1219 1226 cpu_intr_swtch_enter(kthread_id_t t)
1220 1227 {
1221 1228 uint64_t interval;
1222 1229 uint64_t start;
1223 1230 cpu_t *cpu;
1224 1231
1225 1232 ASSERT((t->t_flag & T_INTR_THREAD) != 0);
1226 1233 ASSERT(t->t_pil > 0 && t->t_pil <= LOCK_LEVEL);
1227 1234
1228 1235 /*
1229 1236 * We could be here with a zero timestamp. This could happen if:
1230 1237 * an interrupt thread which no longer has a pinned thread underneath
1231 1238 * it (i.e. it blocked at some point in its past) has finished running
1232 1239 * its handler. intr_thread() updated the interrupt statistic for its
1233 1240 * PIL and zeroed its timestamp. Since there was no pinned thread to
1234 1241 * return to, swtch() gets called and we end up here.
1235 1242 *
1236 1243 * Note that we use atomic ops below (atomic_cas_64 and
1237 1244 * atomic_add_64), which we don't use in the functions above,
1238 1245 * because we're not called with interrupts blocked, but the
1239 1246 * epilog/prolog functions are.
1240 1247 */
1241 1248 if (t->t_intr_start) {
1242 1249 do {
1243 1250 start = t->t_intr_start;
1244 1251 interval = tsc_read() - start;
1245 1252 } while (atomic_cas_64(&t->t_intr_start, start, 0) != start);
1246 1253 cpu = CPU;
1247 1254 cpu->cpu_m.intrstat[t->t_pil][0] += interval;
1248 1255
1249 1256 atomic_add_64((uint64_t *)&cpu->cpu_intracct[cpu->cpu_mstate],
1250 1257 interval);
1251 1258 } else
1252 1259 ASSERT(t->t_intr == NULL);
1253 1260 }
1254 1261
1255 1262 /*
1256 1263 * An interrupt thread is returning from swtch(). Place a starting timestamp
1257 1264 * in its thread structure.
1258 1265 */
1259 1266 void
1260 1267 cpu_intr_swtch_exit(kthread_id_t t)
1261 1268 {
1262 1269 uint64_t ts;
1263 1270
1264 1271 ASSERT((t->t_flag & T_INTR_THREAD) != 0);
1265 1272 ASSERT(t->t_pil > 0 && t->t_pil <= LOCK_LEVEL);
1266 1273
1267 1274 do {
1268 1275 ts = t->t_intr_start;
1269 1276 } while (atomic_cas_64(&t->t_intr_start, ts, tsc_read()) != ts);
1270 1277 }
1271 1278
1272 1279 /*
1273 1280 * Dispatch a hilevel interrupt (one above LOCK_LEVEL)
1274 1281 */
1275 1282 /*ARGSUSED*/
1276 1283 static void
1277 1284 dispatch_hilevel(uint_t vector, uint_t arg2)
1278 1285 {
1279 1286 sti();
1280 1287 av_dispatch_autovect(vector);
1281 1288 cli();
1282 1289 }
1283 1290
1284 1291 /*
1285 1292 * Dispatch a soft interrupt
1286 1293 */
1287 1294 /*ARGSUSED*/
1288 1295 static void
1289 1296 dispatch_softint(uint_t oldpil, uint_t arg2)
1290 1297 {
1291 1298 struct cpu *cpu = CPU;
1292 1299
1293 1300 sti();
1294 1301 av_dispatch_softvect((int)cpu->cpu_thread->t_pil);
1295 1302 cli();
1296 1303
1297 1304 /*
1298 1305 * Must run softint_epilog() on the interrupt thread stack, since
1299 1306 * there may not be a return from it if the interrupt thread blocked.
1300 1307 */
1301 1308 dosoftint_epilog(cpu, oldpil);
1302 1309 }
1303 1310
1304 1311 /*
1305 1312 * Dispatch a normal interrupt
1306 1313 */
1307 1314 static void
1308 1315 dispatch_hardint(uint_t vector, uint_t oldipl)
1309 1316 {
1310 1317 struct cpu *cpu = CPU;
1311 1318
1312 1319 sti();
1313 1320 av_dispatch_autovect(vector);
1314 1321 cli();
1315 1322
1316 1323 /*
1317 1324 * Must run intr_thread_epilog() on the interrupt thread stack, since
1318 1325 * there may not be a return from it if the interrupt thread blocked.
1319 1326 */
1320 1327 intr_thread_epilog(cpu, vector, oldipl);
1321 1328 }
1322 1329
1323 1330 /*
1324 1331 * Deliver any softints the current interrupt priority allows.
1325 1332 * Called with interrupts disabled.
1326 1333 */
1327 1334 void
1328 1335 dosoftint(struct regs *regs)
1329 1336 {
1330 1337 struct cpu *cpu = CPU;
1331 1338 int oldipl;
1332 1339 caddr_t newsp;
1333 1340
1334 1341 while (cpu->cpu_softinfo.st_pending) {
1335 1342 oldipl = cpu->cpu_pri;
1336 1343 newsp = dosoftint_prolog(cpu, (caddr_t)regs,
1337 1344 cpu->cpu_softinfo.st_pending, oldipl);
1338 1345 /*
1339 1346 * If returned stack pointer is NULL, priority is too high
1340 1347 * to run any of the pending softints now.
1341 1348 * Break out and they will be run later.
1342 1349 */
1343 1350 if (newsp == NULL)
1344 1351 break;
1345 1352 switch_sp_and_call(newsp, dispatch_softint, oldipl, 0);
1346 1353 }
1347 1354 }
1348 1355
1349 1356 /*
1350 1357 * Interrupt service routine, called with interrupts disabled.
1351 1358 */
1352 1359 /*ARGSUSED*/
1353 1360 void
1354 1361 do_interrupt(struct regs *rp, trap_trace_rec_t *ttp)
1355 1362 {
1356 1363 struct cpu *cpu = CPU;
1357 1364 int newipl, oldipl = cpu->cpu_pri;
1358 1365 uint_t vector;
1359 1366 caddr_t newsp;
1360 1367
1361 1368 #ifdef TRAPTRACE
1362 1369 ttp->ttr_marker = TT_INTERRUPT;
1363 1370 ttp->ttr_ipl = 0xff;
1364 1371 ttp->ttr_pri = oldipl;
1365 1372 ttp->ttr_spl = cpu->cpu_base_spl;
1366 1373 ttp->ttr_vector = 0xff;
1367 1374 #endif /* TRAPTRACE */
1368 1375
1369 1376 cpu_idle_exit(CPU_IDLE_CB_FLAG_INTR);
1370 1377
1371 1378 ++*(uint16_t *)&cpu->cpu_m.mcpu_istamp;
1372 1379
1373 1380 /*
1374 1381 * If it's a softint go do it now.
1375 1382 */
1376 1383 if (rp->r_trapno == T_SOFTINT) {
1377 1384 dosoftint(rp);
1378 1385 ASSERT(!interrupts_enabled());
1379 1386 return;
1380 1387 }
1381 1388
1382 1389 /*
1383 1390 * Raise the interrupt priority.
1384 1391 */
1385 1392 newipl = (*setlvl)(oldipl, (int *)&rp->r_trapno);
1386 1393 #ifdef TRAPTRACE
1387 1394 ttp->ttr_ipl = newipl;
1388 1395 #endif /* TRAPTRACE */
1389 1396
1390 1397 /*
1391 1398 * Bail if it is a spurious interrupt
1392 1399 */
1393 1400 if (newipl == -1)
1394 1401 return;
1395 1402 cpu->cpu_pri = newipl;
1396 1403 vector = rp->r_trapno;
1397 1404 #ifdef TRAPTRACE
1398 1405 ttp->ttr_vector = vector;
1399 1406 #endif /* TRAPTRACE */
1400 1407 if (newipl > LOCK_LEVEL) {
1401 1408 /*
1402 1409 * High priority interrupts run on this cpu's interrupt stack.
1403 1410 */
1404 1411 if (hilevel_intr_prolog(cpu, newipl, oldipl, rp) == 0) {
1405 1412 newsp = cpu->cpu_intr_stack;
1406 1413 switch_sp_and_call(newsp, dispatch_hilevel, vector, 0);
1407 1414 } else { /* already on the interrupt stack */
1408 1415 dispatch_hilevel(vector, 0);
1409 1416 }
1410 1417 (void) hilevel_intr_epilog(cpu, newipl, oldipl, vector);
1411 1418 } else {
1412 1419 /*
1413 1420 * Run this interrupt in a separate thread.
1414 1421 */
1415 1422 newsp = intr_thread_prolog(cpu, (caddr_t)rp, newipl);
1416 1423 switch_sp_and_call(newsp, dispatch_hardint, vector, oldipl);
1417 1424 }
1418 1425
1419 1426 #if !defined(__xpv)
1420 1427 /*
1421 1428 * Deliver any pending soft interrupts.
1422 1429 */
1423 1430 if (cpu->cpu_softinfo.st_pending)
1424 1431 dosoftint(rp);
1425 1432 #endif /* !__xpv */
1426 1433 }
1427 1434
1428 1435
1429 1436 /*
1430 1437 * Common tasks always done by _sys_rtt, called with interrupts disabled.
1431 1438 * Returns 1 if returning to userland, 0 if returning to system mode.
1432 1439 */
1433 1440 int
1434 1441 sys_rtt_common(struct regs *rp)
1435 1442 {
1436 1443 kthread_t *tp;
1437 1444 extern void mutex_exit_critical_start();
1438 1445 extern long mutex_exit_critical_size;
1439 1446 extern void mutex_owner_running_critical_start();
1440 1447 extern long mutex_owner_running_critical_size;
1441 1448
1442 1449 loop:
1443 1450
1444 1451 /*
1445 1452 * Check if returning to user
1446 1453 */
1447 1454 tp = CPU->cpu_thread;
1448 1455 if (USERMODE(rp->r_cs)) {
1449 1456 pcb_t *pcb;
1450 1457
1451 1458 /*
1452 1459 * Check if AST pending.
1453 1460 */
1454 1461 if (tp->t_astflag) {
1455 1462 /*
1456 1463 * Let trap() handle the AST
1457 1464 */
1458 1465 sti();
1459 1466 rp->r_trapno = T_AST;
1460 1467 trap(rp, (caddr_t)0, CPU->cpu_id);
1461 1468 cli();
1462 1469 goto loop;
1463 1470 }
1464 1471
1465 1472 pcb = &tp->t_lwp->lwp_pcb;
1466 1473
1467 1474 /*
1468 1475 * Check to see if we need to initialize the FPU for this
1469 1476 * thread. This should be an uncommon occurrence, but may happen
1470 1477 * in the case where the system creates an lwp through an
1471 1478 * abnormal path such as the agent lwp. Make sure that we still
1472 1479 * happen to have the FPU in a good state.
1473 1480 */
1474 1481 if ((pcb->pcb_fpu.fpu_flags & FPU_EN) == 0) {
1475 1482 kpreempt_disable();
1476 1483 fp_seed();
1477 1484 kpreempt_enable();
1478 1485 PCB_SET_UPDATE_FPU(pcb);
1479 1486 }
1480 1487
1481 1488 /*
1482 1489 * We are done if segment registers do not need updating.
1483 1490 */
1484 1491 if (!PCB_NEED_UPDATE(pcb))
1485 1492 return (1);
1486 1493
1487 1494 if (PCB_NEED_UPDATE_SEGS(pcb) && update_sregs(rp, tp->t_lwp)) {
1488 1495 /*
1489 1496 * 1 or more of the selectors is bad.
1490 1497 * Deliver a SIGSEGV.
1491 1498 */
1492 1499 proc_t *p = ttoproc(tp);
1493 1500
1494 1501 sti();
1495 1502 mutex_enter(&p->p_lock);
1496 1503 tp->t_lwp->lwp_cursig = SIGSEGV;
1497 1504 mutex_exit(&p->p_lock);
1498 1505 psig();
1499 1506 tp->t_sig_check = 1;
1500 1507 cli();
1501 1508 }
1502 1509 PCB_CLEAR_UPDATE_SEGS(pcb);
1503 1510
1504 1511 if (PCB_NEED_UPDATE_FPU(pcb)) {
1505 1512 fprestore_ctxt(&pcb->pcb_fpu);
1506 1513 }
1507 1514 PCB_CLEAR_UPDATE_FPU(pcb);
1508 1515
1509 1516 ASSERT0(PCB_NEED_UPDATE(pcb));
1510 1517
1511 1518 return (1);
1512 1519 }
1513 1520
1514 1521 #if !defined(__xpv)
1515 1522 /*
1516 1523 * Assert that we're not trying to return into the syscall return
1517 1524 * trampolines. Things will go baaaaad if we try to do that.
1518 1525 *
1519 1526 * Note that none of these run with interrupts on, so this should
1520 1527 * never happen (even in the sysexit case the STI doesn't take effect
1521 1528 * until after sysexit finishes).
1522 1529 */
1523 1530 extern void tr_sysc_ret_start();
1524 1531 extern void tr_sysc_ret_end();
1525 1532 ASSERT(!(rp->r_pc >= (uintptr_t)tr_sysc_ret_start &&
1526 1533 rp->r_pc <= (uintptr_t)tr_sysc_ret_end));
1527 1534 #endif
1528 1535
1529 1536 /*
1530 1537 * Here if we are returning to supervisor mode.
1531 1538 * Check for a kernel preemption request.
1532 1539 */
1533 1540 if (CPU->cpu_kprunrun && (rp->r_ps & PS_IE)) {
1534 1541
1535 1542 /*
1536 1543 * Do nothing if already in kpreempt
1537 1544 */
1538 1545 if (!tp->t_preempt_lk) {
1539 1546 tp->t_preempt_lk = 1;
1540 1547 sti();
1541 1548 kpreempt(1); /* asynchronous kpreempt call */
1542 1549 cli();
1543 1550 tp->t_preempt_lk = 0;
1544 1551 }
1545 1552 }
1546 1553
1547 1554 /*
1548 1555 * If we interrupted the mutex_exit() critical region we must
1549 1556 * reset the PC back to the beginning to prevent missed wakeups
1550 1557 * See the comments in mutex_exit() for details.
1551 1558 */
1552 1559 if ((uintptr_t)rp->r_pc - (uintptr_t)mutex_exit_critical_start <
1553 1560 mutex_exit_critical_size) {
1554 1561 rp->r_pc = (greg_t)mutex_exit_critical_start;
1555 1562 }
1556 1563
1557 1564 /*
1558 1565 * If we interrupted the mutex_owner_running() critical region we
1559 1566 * must reset the PC back to the beginning to prevent dereferencing
1560 1567 * of a freed thread pointer. See the comments in mutex_owner_running
1561 1568 * for details.
1562 1569 */
1563 1570 if ((uintptr_t)rp->r_pc -
1564 1571 (uintptr_t)mutex_owner_running_critical_start <
1565 1572 mutex_owner_running_critical_size) {
1566 1573 rp->r_pc = (greg_t)mutex_owner_running_critical_start;
1567 1574 }
1568 1575
1569 1576 return (0);
1570 1577 }
1571 1578
1572 1579 void
1573 1580 send_dirint(int cpuid, int int_level)
1574 1581 {
1575 1582 (*send_dirintf)(cpuid, int_level);
1576 1583 }
1577 1584
1578 1585 #define IS_FAKE_SOFTINT(flag, newpri) \
1579 1586 (((flag) & PS_IE) && \
1580 1587 (((*get_pending_spl)() > (newpri)) || \
1581 1588 bsrw_insn((uint16_t)cpu->cpu_softinfo.st_pending) > (newpri)))
1582 1589
1583 1590 /*
1584 1591 * do_splx routine, takes new ipl to set
1585 1592 * returns the old ipl.
1586 1593 * We are careful not to set priority lower than CPU->cpu_base_pri,
1587 1594 * even though it seems we're raising the priority, it could be set
1588 1595 * higher at any time by an interrupt routine, so we must block interrupts
1589 1596 * and look at CPU->cpu_base_pri
1590 1597 */
1591 1598 int
1592 1599 do_splx(int newpri)
1593 1600 {
1594 1601 ulong_t flag;
1595 1602 cpu_t *cpu;
1596 1603 int curpri, basepri;
1597 1604
1598 1605 flag = intr_clear();
1599 1606 cpu = CPU; /* ints are disabled, now safe to cache cpu ptr */
1600 1607 curpri = cpu->cpu_m.mcpu_pri;
1601 1608 basepri = cpu->cpu_base_spl;
1602 1609 if (newpri < basepri)
1603 1610 newpri = basepri;
1604 1611 cpu->cpu_m.mcpu_pri = newpri;
1605 1612 (*setspl)(newpri);
1606 1613 /*
1607 1614 * If we are going to reenable interrupts see if new priority level
1608 1615 * allows pending softint delivery.
1609 1616 */
1610 1617 if (IS_FAKE_SOFTINT(flag, newpri))
1611 1618 fakesoftint();
1612 1619 ASSERT(!interrupts_enabled());
1613 1620 intr_restore(flag);
1614 1621 return (curpri);
1615 1622 }
1616 1623
1617 1624 /*
1618 1625 * Common spl raise routine, takes new ipl to set
1619 1626 * returns the old ipl, will not lower ipl.
1620 1627 */
1621 1628 int
1622 1629 splr(int newpri)
1623 1630 {
1624 1631 ulong_t flag;
1625 1632 cpu_t *cpu;
1626 1633 int curpri, basepri;
1627 1634
1628 1635 flag = intr_clear();
1629 1636 cpu = CPU; /* ints are disabled, now safe to cache cpu ptr */
1630 1637 curpri = cpu->cpu_m.mcpu_pri;
1631 1638 /*
1632 1639 * Only do something if new priority is larger
1633 1640 */
1634 1641 if (newpri > curpri) {
1635 1642 basepri = cpu->cpu_base_spl;
1636 1643 if (newpri < basepri)
1637 1644 newpri = basepri;
1638 1645 cpu->cpu_m.mcpu_pri = newpri;
1639 1646 (*setspl)(newpri);
1640 1647 /*
1641 1648 * See if new priority level allows pending softint delivery
1642 1649 */
1643 1650 if (IS_FAKE_SOFTINT(flag, newpri))
1644 1651 fakesoftint();
1645 1652 }
1646 1653 intr_restore(flag);
1647 1654 return (curpri);
1648 1655 }
1649 1656
1650 1657 int
1651 1658 getpil(void)
1652 1659 {
1653 1660 return (CPU->cpu_m.mcpu_pri);
1654 1661 }
1655 1662
1656 1663 int
1657 1664 spl_xcall(void)
1658 1665 {
1659 1666 return (splr(ipltospl(XCALL_PIL)));
1660 1667 }
1661 1668
1662 1669 int
1663 1670 interrupts_enabled(void)
1664 1671 {
1665 1672 ulong_t flag;
1666 1673
1667 1674 flag = getflags();
1668 1675 return ((flag & PS_IE) == PS_IE);
1669 1676 }
1670 1677
1671 1678 #ifdef DEBUG
1672 1679 void
1673 1680 assert_ints_enabled(void)
1674 1681 {
1675 1682 ASSERT(!interrupts_unleashed || interrupts_enabled());
1676 1683 }
1677 1684 #endif /* DEBUG */
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