Print this page
8956 Implement KPTI
Reviewed by: Jerry Jelinek <jerry.jelinek@joyent.com>
Reviewed by: Robert Mustacchi <rm@joyent.com>
9215 update CPUID defines
Reviewed by: Yuri Pankov <yuripv@yuripv.net>

Split Close
Expand all
Collapse all
          --- old/usr/src/uts/intel/sys/x86_archext.h
          +++ new/usr/src/uts/intel/sys/x86_archext.h
↓ open down ↓ 19 lines elided ↑ open up ↑
  20   20   */
  21   21  /*
  22   22   * Copyright (c) 1995, 2010, Oracle and/or its affiliates. All rights reserved.
  23   23   * Copyright (c) 2011 by Delphix. All rights reserved.
  24   24   */
  25   25  /*
  26   26   * Copyright (c) 2010, Intel Corporation.
  27   27   * All rights reserved.
  28   28   */
  29   29  /*
  30      - * Copyright 2017 Joyent, Inc.
       30 + * Copyright 2018 Joyent, Inc.
  31   31   * Copyright 2012 Jens Elkner <jel+illumos@cs.uni-magdeburg.de>
  32   32   * Copyright 2012 Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org>
  33   33   * Copyright 2014 Josef 'Jeff' Sipek <jeffpc@josefsipek.net>
  34   34   * Copyright 2018 Nexenta Systems, Inc.
  35   35   */
  36   36  
  37   37  #ifndef _SYS_X86_ARCHEXT_H
  38   38  #define _SYS_X86_ARCHEXT_H
  39   39  
  40   40  #if !defined(_ASM)
↓ open down ↓ 43 lines elided ↑ open up ↑
  84   84  #define CPUID_INTC_EDX_TM       0x20000000      /* thermal monitoring */
  85   85  #define CPUID_INTC_EDX_IA64     0x40000000      /* Itanium emulating IA32 */
  86   86  #define CPUID_INTC_EDX_PBE      0x80000000      /* Pending Break Enable */
  87   87  
  88   88  /*
  89   89   * cpuid instruction feature flags in %ecx (standard function 1)
  90   90   */
  91   91  
  92   92  #define CPUID_INTC_ECX_SSE3     0x00000001      /* Yet more SSE extensions */
  93   93  #define CPUID_INTC_ECX_PCLMULQDQ 0x00000002     /* PCLMULQDQ insn */
  94      -                                                /* 0x00000004 - reserved */
       94 +#define CPUID_INTC_ECX_DTES64   0x00000004      /* 64-bit DS area */
  95   95  #define CPUID_INTC_ECX_MON      0x00000008      /* MONITOR/MWAIT */
  96   96  #define CPUID_INTC_ECX_DSCPL    0x00000010      /* CPL-qualified debug store */
  97   97  #define CPUID_INTC_ECX_VMX      0x00000020      /* Hardware VM extensions */
  98   98  #define CPUID_INTC_ECX_SMX      0x00000040      /* Secure mode extensions */
  99   99  #define CPUID_INTC_ECX_EST      0x00000080      /* enhanced SpeedStep */
 100  100  #define CPUID_INTC_ECX_TM2      0x00000100      /* thermal monitoring */
 101  101  #define CPUID_INTC_ECX_SSSE3    0x00000200      /* Supplemental SSE3 insns */
 102  102  #define CPUID_INTC_ECX_CID      0x00000400      /* L1 context ID */
 103  103                                                  /* 0x00000800 - reserved */
 104  104  #define CPUID_INTC_ECX_FMA      0x00001000      /* Fused Multiply Add */
 105  105  #define CPUID_INTC_ECX_CX16     0x00002000      /* cmpxchg16 */
 106  106  #define CPUID_INTC_ECX_ETPRD    0x00004000      /* extended task pri messages */
 107      -                                                /* 0x00008000 - reserved */
      107 +#define CPUID_INTC_ECX_PDCM     0x00008000      /* Perf/Debug Capability MSR */
 108  108                                                  /* 0x00010000 - reserved */
 109      -                                                /* 0x00020000 - reserved */
      109 +#define CPUID_INTC_ECX_PCID     0x00020000      /* process-context ids */
 110  110  #define CPUID_INTC_ECX_DCA      0x00040000      /* direct cache access */
 111  111  #define CPUID_INTC_ECX_SSE4_1   0x00080000      /* SSE4.1 insns */
 112  112  #define CPUID_INTC_ECX_SSE4_2   0x00100000      /* SSE4.2 insns */
 113  113  #define CPUID_INTC_ECX_X2APIC   0x00200000      /* x2APIC */
 114  114  #define CPUID_INTC_ECX_MOVBE    0x00400000      /* MOVBE insn */
 115  115  #define CPUID_INTC_ECX_POPCNT   0x00800000      /* POPCNT insn */
      116 +#define CPUID_INTC_ECX_TSCDL    0x01000000      /* Deadline TSC */
 116  117  #define CPUID_INTC_ECX_AES      0x02000000      /* AES insns */
 117  118  #define CPUID_INTC_ECX_XSAVE    0x04000000      /* XSAVE/XRESTOR insns */
 118  119  #define CPUID_INTC_ECX_OSXSAVE  0x08000000      /* OS supports XSAVE insns */
 119  120  #define CPUID_INTC_ECX_AVX      0x10000000      /* AVX supported */
 120  121  #define CPUID_INTC_ECX_F16C     0x20000000      /* F16C supported */
 121  122  #define CPUID_INTC_ECX_RDRAND   0x40000000      /* RDRAND supported */
 122  123  #define CPUID_INTC_ECX_HV       0x80000000      /* Hypervisor */
 123  124  
 124  125  /*
 125  126   * cpuid instruction feature flags in %edx (extended function 0x80000001)
↓ open down ↓ 37 lines elided ↑ open up ↑
 163  164  #define CPUID_AMD_ECX_CMP_LGCY  0x00000002      /* AMD: multicore chip */
 164  165  #define CPUID_AMD_ECX_SVM       0x00000004      /* AMD: secure VM */
 165  166  #define CPUID_AMD_ECX_EAS       0x00000008      /* extended apic space */
 166  167  #define CPUID_AMD_ECX_CR8D      0x00000010      /* AMD: 32-bit mov %cr8 */
 167  168  #define CPUID_AMD_ECX_LZCNT     0x00000020      /* AMD: LZCNT insn */
 168  169  #define CPUID_AMD_ECX_SSE4A     0x00000040      /* AMD: SSE4A insns */
 169  170  #define CPUID_AMD_ECX_MAS       0x00000080      /* AMD: MisAlignSse mnode */
 170  171  #define CPUID_AMD_ECX_3DNP      0x00000100      /* AMD: 3DNowPrefectch */
 171  172  #define CPUID_AMD_ECX_OSVW      0x00000200      /* AMD: OSVW */
 172  173  #define CPUID_AMD_ECX_IBS       0x00000400      /* AMD: IBS */
 173      -#define CPUID_AMD_ECX_SSE5      0x00000800      /* AMD: SSE5 */
      174 +#define CPUID_AMD_ECX_SSE5      0x00000800      /* AMD: Extended AVX */
 174  175  #define CPUID_AMD_ECX_SKINIT    0x00001000      /* AMD: SKINIT */
 175  176  #define CPUID_AMD_ECX_WDT       0x00002000      /* AMD: WDT */
      177 +                                /* 0x00004000 - reserved */
      178 +#define CPUID_AMD_ECX_LWP       0x00008000      /* AMD: Lightweight profiling */
      179 +#define CPUID_AMD_ECX_FMA4      0x00010000      /* AMD: 4-operand FMA support */
      180 +                                /* 0x00020000 - reserved */
      181 +                                /* 0x00040000 - reserved */
      182 +#define CPUID_AMD_ECX_NIDMSR    0x00080000      /* AMD: Node ID MSR */
      183 +                                /* 0x00100000 - reserved */
      184 +#define CPUID_AMD_ECX_TBM       0x00200000      /* AMD: trailing bit manips. */
 176  185  #define CPUID_AMD_ECX_TOPOEXT   0x00400000      /* AMD: Topology Extensions */
 177  186  
 178  187  /*
 179  188   * AMD uses %ebx for some of their features (extended function 0x80000008).
 180  189   */
 181  190  #define CPUID_AMD_EBX_ERR_PTR_ZERO      0x00000004 /* AMD: FP Err. Ptr. Zero */
 182  191  
 183  192  /*
 184  193   * Intel now seems to have claimed part of the "extended" function
 185  194   * space that we previously for non-Intel implementors to use.
↓ open down ↓ 8 lines elided ↑ open up ↑
 194  203   * Like some other leaves, but unlike the current ones we care about, it
 195  204   * requires us to specify both a leaf in %eax and a sub-leaf in %ecx. To deal
 196  205   * with the potential use of additional sub-leaves in the future, we now
 197  206   * specifically label the EBX features with their leaf and sub-leaf.
 198  207   */
 199  208  #define CPUID_INTC_EBX_7_0_BMI1         0x00000008      /* BMI1 instrs */
 200  209  #define CPUID_INTC_EBX_7_0_HLE          0x00000010      /* HLE */
 201  210  #define CPUID_INTC_EBX_7_0_AVX2         0x00000020      /* AVX2 supported */
 202  211  #define CPUID_INTC_EBX_7_0_SMEP         0x00000080      /* SMEP in CR4 */
 203  212  #define CPUID_INTC_EBX_7_0_BMI2         0x00000100      /* BMI2 instrs */
      213 +#define CPUID_INTC_EBX_7_0_INVPCID      0x00000400      /* invpcid instr */
 204  214  #define CPUID_INTC_EBX_7_0_MPX          0x00004000      /* Mem. Prot. Ext. */
 205  215  #define CPUID_INTC_EBX_7_0_AVX512F      0x00010000      /* AVX512 foundation */
 206  216  #define CPUID_INTC_EBX_7_0_AVX512DQ     0x00020000      /* AVX512DQ */
 207  217  #define CPUID_INTC_EBX_7_0_RDSEED       0x00040000      /* RDSEED instr */
 208  218  #define CPUID_INTC_EBX_7_0_ADX          0x00080000      /* ADX instrs */
 209  219  #define CPUID_INTC_EBX_7_0_SMAP         0x00100000      /* SMAP in CR 4 */
 210  220  #define CPUID_INTC_EBX_7_0_AVX512IFMA   0x00200000      /* AVX512IFMA */
 211  221  #define CPUID_INTC_EBX_7_0_CLWB         0x01000000      /* CLWB */
 212  222  #define CPUID_INTC_EBX_7_0_AVX512PF     0x04000000      /* AVX512PF */
 213  223  #define CPUID_INTC_EBX_7_0_AVX512ER     0x08000000      /* AVX512ER */
↓ open down ↓ 203 lines elided ↑ open up ↑
 417  427  #define X86FSET_AVX512VPOPCDQ   59
 418  428  #define X86FSET_AVX512NNIW      60
 419  429  #define X86FSET_AVX512FMAPS     61
 420  430  #define X86FSET_XSAVEOPT        62
 421  431  #define X86FSET_XSAVEC          63
 422  432  #define X86FSET_XSAVES          64
 423  433  #define X86FSET_SHA             65
 424  434  #define X86FSET_UMIP            66
 425  435  #define X86FSET_PKU             67
 426  436  #define X86FSET_OSPKE           68
      437 +#define X86FSET_PCID            69
      438 +#define X86FSET_INVPCID         70
 427  439  
 428  440  /*
 429  441   * Intel Deep C-State invariant TSC in leaf 0x80000007.
 430  442   */
 431  443  #define CPUID_TSC_CSTATE_INVARIANCE     (0x100)
 432  444  
 433  445  /*
 434  446   * Intel Deep C-state always-running local APIC timer
 435  447   */
 436  448  #define CPUID_CSTATE_ARAT       (0x4)
↓ open down ↓ 238 lines elided ↑ open up ↑
 675  687          /* bit 8 unused */
 676  688  #define XFEATURE_PKRU           0x200
 677  689  #define XFEATURE_FP_ALL \
 678  690          (XFEATURE_LEGACY_FP | XFEATURE_SSE | XFEATURE_AVX | XFEATURE_MPX | \
 679  691          XFEATURE_AVX512 | XFEATURE_PKRU)
 680  692  
 681  693  #if !defined(_ASM)
 682  694  
 683  695  #if defined(_KERNEL) || defined(_KMEMUSER)
 684  696  
 685      -#define NUM_X86_FEATURES        69
      697 +#define NUM_X86_FEATURES        71
 686  698  extern uchar_t x86_featureset[];
 687  699  
 688  700  extern void free_x86_featureset(void *featureset);
 689  701  extern boolean_t is_x86_feature(void *featureset, uint_t feature);
 690  702  extern void add_x86_feature(void *featureset, uint_t feature);
 691  703  extern void remove_x86_feature(void *featureset, uint_t feature);
 692  704  extern boolean_t compare_x86_featureset(void *setA, void *setB);
 693  705  extern void print_x86_featureset(void *featureset);
 694  706  
 695  707  
↓ open down ↓ 13 lines elided ↑ open up ↑
 709  721   * This structure is used to pass arguments and get return values back
 710  722   * from the CPUID instruction in __cpuid_insn() routine.
 711  723   */
 712  724  struct cpuid_regs {
 713  725          uint32_t        cp_eax;
 714  726          uint32_t        cp_ebx;
 715  727          uint32_t        cp_ecx;
 716  728          uint32_t        cp_edx;
 717  729  };
 718  730  
      731 +extern int x86_use_pcid;
      732 +extern int x86_use_invpcid;
      733 +
 719  734  /*
 720  735   * Utility functions to get/set extended control registers (XCR)
 721  736   * Initial use is to get/set the contents of the XFEATURE_ENABLED_MASK.
 722  737   */
 723  738  extern uint64_t get_xcr(uint_t);
 724  739  extern void set_xcr(uint_t, uint64_t);
 725  740  
 726  741  extern uint64_t rdmsr(uint_t);
 727  742  extern void wrmsr(uint_t, const uint64_t);
 728  743  extern uint64_t xrdmsr(uint_t);
↓ open down ↓ 125 lines elided ↑ open up ↑
 854  869  extern int opteron_workaround_6323525;
 855  870  extern void patch_workaround_6323525(void);
 856  871  #endif
 857  872  
 858  873  #if !defined(__xpv)
 859  874  extern void determine_platform(void);
 860  875  #endif
 861  876  extern int get_hwenv(void);
 862  877  extern int is_controldom(void);
 863  878  
      879 +extern void enable_pcid(void);
      880 +
 864  881  extern void xsave_setup_msr(struct cpu *);
 865  882  
 866  883  /*
 867  884   * Hypervisor signatures
 868  885   */
 869  886  #define HVSIG_XEN_HVM   "XenVMMXenVMM"
 870  887  #define HVSIG_VMWARE    "VMwareVMware"
 871  888  #define HVSIG_KVM       "KVMKVMKVM"
 872  889  #define HVSIG_MICROSOFT "Microsoft Hv"
 873  890  
↓ open down ↓ 30 lines elided ↑ open up ↑
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX