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8956 Implement KPTI
Reviewed by: Jerry Jelinek <jerry.jelinek@joyent.com>
Reviewed by: Robert Mustacchi <rm@joyent.com>
9215 update CPUID defines
Reviewed by: Yuri Pankov <yuripv@yuripv.net>
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--- old/usr/src/uts/intel/sys/x86_archext.h
+++ new/usr/src/uts/intel/sys/x86_archext.h
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
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20 20 */
21 21 /*
22 22 * Copyright (c) 1995, 2010, Oracle and/or its affiliates. All rights reserved.
23 23 * Copyright (c) 2011 by Delphix. All rights reserved.
24 24 */
25 25 /*
26 26 * Copyright (c) 2010, Intel Corporation.
27 27 * All rights reserved.
28 28 */
29 29 /*
30 - * Copyright 2017 Joyent, Inc.
30 + * Copyright 2018 Joyent, Inc.
31 31 * Copyright 2012 Jens Elkner <jel+illumos@cs.uni-magdeburg.de>
32 32 * Copyright 2012 Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org>
33 33 * Copyright 2014 Josef 'Jeff' Sipek <jeffpc@josefsipek.net>
34 34 * Copyright 2018 Nexenta Systems, Inc.
35 35 */
36 36
37 37 #ifndef _SYS_X86_ARCHEXT_H
38 38 #define _SYS_X86_ARCHEXT_H
39 39
40 40 #if !defined(_ASM)
41 41 #include <sys/regset.h>
42 42 #include <sys/processor.h>
43 43 #include <vm/seg_enum.h>
44 44 #include <vm/page.h>
45 45 #endif /* _ASM */
46 46
47 47 #ifdef __cplusplus
48 48 extern "C" {
49 49 #endif
50 50
51 51 /*
52 52 * cpuid instruction feature flags in %edx (standard function 1)
53 53 */
54 54
55 55 #define CPUID_INTC_EDX_FPU 0x00000001 /* x87 fpu present */
56 56 #define CPUID_INTC_EDX_VME 0x00000002 /* virtual-8086 extension */
57 57 #define CPUID_INTC_EDX_DE 0x00000004 /* debugging extensions */
58 58 #define CPUID_INTC_EDX_PSE 0x00000008 /* page size extension */
59 59 #define CPUID_INTC_EDX_TSC 0x00000010 /* time stamp counter */
60 60 #define CPUID_INTC_EDX_MSR 0x00000020 /* rdmsr and wrmsr */
61 61 #define CPUID_INTC_EDX_PAE 0x00000040 /* physical addr extension */
62 62 #define CPUID_INTC_EDX_MCE 0x00000080 /* machine check exception */
63 63 #define CPUID_INTC_EDX_CX8 0x00000100 /* cmpxchg8b instruction */
64 64 #define CPUID_INTC_EDX_APIC 0x00000200 /* local APIC */
65 65 /* 0x400 - reserved */
66 66 #define CPUID_INTC_EDX_SEP 0x00000800 /* sysenter and sysexit */
67 67 #define CPUID_INTC_EDX_MTRR 0x00001000 /* memory type range reg */
68 68 #define CPUID_INTC_EDX_PGE 0x00002000 /* page global enable */
69 69 #define CPUID_INTC_EDX_MCA 0x00004000 /* machine check arch */
70 70 #define CPUID_INTC_EDX_CMOV 0x00008000 /* conditional move insns */
71 71 #define CPUID_INTC_EDX_PAT 0x00010000 /* page attribute table */
72 72 #define CPUID_INTC_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */
73 73 #define CPUID_INTC_EDX_PSN 0x00040000 /* processor serial number */
74 74 #define CPUID_INTC_EDX_CLFSH 0x00080000 /* clflush instruction */
75 75 /* 0x100000 - reserved */
76 76 #define CPUID_INTC_EDX_DS 0x00200000 /* debug store exists */
77 77 #define CPUID_INTC_EDX_ACPI 0x00400000 /* monitoring + clock ctrl */
78 78 #define CPUID_INTC_EDX_MMX 0x00800000 /* MMX instructions */
79 79 #define CPUID_INTC_EDX_FXSR 0x01000000 /* fxsave and fxrstor */
80 80 #define CPUID_INTC_EDX_SSE 0x02000000 /* streaming SIMD extensions */
81 81 #define CPUID_INTC_EDX_SSE2 0x04000000 /* SSE extensions */
82 82 #define CPUID_INTC_EDX_SS 0x08000000 /* self-snoop */
83 83 #define CPUID_INTC_EDX_HTT 0x10000000 /* Hyper Thread Technology */
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84 84 #define CPUID_INTC_EDX_TM 0x20000000 /* thermal monitoring */
85 85 #define CPUID_INTC_EDX_IA64 0x40000000 /* Itanium emulating IA32 */
86 86 #define CPUID_INTC_EDX_PBE 0x80000000 /* Pending Break Enable */
87 87
88 88 /*
89 89 * cpuid instruction feature flags in %ecx (standard function 1)
90 90 */
91 91
92 92 #define CPUID_INTC_ECX_SSE3 0x00000001 /* Yet more SSE extensions */
93 93 #define CPUID_INTC_ECX_PCLMULQDQ 0x00000002 /* PCLMULQDQ insn */
94 - /* 0x00000004 - reserved */
94 +#define CPUID_INTC_ECX_DTES64 0x00000004 /* 64-bit DS area */
95 95 #define CPUID_INTC_ECX_MON 0x00000008 /* MONITOR/MWAIT */
96 96 #define CPUID_INTC_ECX_DSCPL 0x00000010 /* CPL-qualified debug store */
97 97 #define CPUID_INTC_ECX_VMX 0x00000020 /* Hardware VM extensions */
98 98 #define CPUID_INTC_ECX_SMX 0x00000040 /* Secure mode extensions */
99 99 #define CPUID_INTC_ECX_EST 0x00000080 /* enhanced SpeedStep */
100 100 #define CPUID_INTC_ECX_TM2 0x00000100 /* thermal monitoring */
101 101 #define CPUID_INTC_ECX_SSSE3 0x00000200 /* Supplemental SSE3 insns */
102 102 #define CPUID_INTC_ECX_CID 0x00000400 /* L1 context ID */
103 103 /* 0x00000800 - reserved */
104 104 #define CPUID_INTC_ECX_FMA 0x00001000 /* Fused Multiply Add */
105 105 #define CPUID_INTC_ECX_CX16 0x00002000 /* cmpxchg16 */
106 106 #define CPUID_INTC_ECX_ETPRD 0x00004000 /* extended task pri messages */
107 - /* 0x00008000 - reserved */
107 +#define CPUID_INTC_ECX_PDCM 0x00008000 /* Perf/Debug Capability MSR */
108 108 /* 0x00010000 - reserved */
109 - /* 0x00020000 - reserved */
109 +#define CPUID_INTC_ECX_PCID 0x00020000 /* process-context ids */
110 110 #define CPUID_INTC_ECX_DCA 0x00040000 /* direct cache access */
111 111 #define CPUID_INTC_ECX_SSE4_1 0x00080000 /* SSE4.1 insns */
112 112 #define CPUID_INTC_ECX_SSE4_2 0x00100000 /* SSE4.2 insns */
113 113 #define CPUID_INTC_ECX_X2APIC 0x00200000 /* x2APIC */
114 114 #define CPUID_INTC_ECX_MOVBE 0x00400000 /* MOVBE insn */
115 115 #define CPUID_INTC_ECX_POPCNT 0x00800000 /* POPCNT insn */
116 +#define CPUID_INTC_ECX_TSCDL 0x01000000 /* Deadline TSC */
116 117 #define CPUID_INTC_ECX_AES 0x02000000 /* AES insns */
117 118 #define CPUID_INTC_ECX_XSAVE 0x04000000 /* XSAVE/XRESTOR insns */
118 119 #define CPUID_INTC_ECX_OSXSAVE 0x08000000 /* OS supports XSAVE insns */
119 120 #define CPUID_INTC_ECX_AVX 0x10000000 /* AVX supported */
120 121 #define CPUID_INTC_ECX_F16C 0x20000000 /* F16C supported */
121 122 #define CPUID_INTC_ECX_RDRAND 0x40000000 /* RDRAND supported */
122 123 #define CPUID_INTC_ECX_HV 0x80000000 /* Hypervisor */
123 124
124 125 /*
125 126 * cpuid instruction feature flags in %edx (extended function 0x80000001)
126 127 */
127 128
128 129 #define CPUID_AMD_EDX_FPU 0x00000001 /* x87 fpu present */
129 130 #define CPUID_AMD_EDX_VME 0x00000002 /* virtual-8086 extension */
130 131 #define CPUID_AMD_EDX_DE 0x00000004 /* debugging extensions */
131 132 #define CPUID_AMD_EDX_PSE 0x00000008 /* page size extensions */
132 133 #define CPUID_AMD_EDX_TSC 0x00000010 /* time stamp counter */
133 134 #define CPUID_AMD_EDX_MSR 0x00000020 /* rdmsr and wrmsr */
134 135 #define CPUID_AMD_EDX_PAE 0x00000040 /* physical addr extension */
135 136 #define CPUID_AMD_EDX_MCE 0x00000080 /* machine check exception */
136 137 #define CPUID_AMD_EDX_CX8 0x00000100 /* cmpxchg8b instruction */
137 138 #define CPUID_AMD_EDX_APIC 0x00000200 /* local APIC */
138 139 /* 0x00000400 - sysc on K6m6 */
139 140 #define CPUID_AMD_EDX_SYSC 0x00000800 /* AMD: syscall and sysret */
140 141 #define CPUID_AMD_EDX_MTRR 0x00001000 /* memory type and range reg */
141 142 #define CPUID_AMD_EDX_PGE 0x00002000 /* page global enable */
142 143 #define CPUID_AMD_EDX_MCA 0x00004000 /* machine check arch */
143 144 #define CPUID_AMD_EDX_CMOV 0x00008000 /* conditional move insns */
144 145 #define CPUID_AMD_EDX_PAT 0x00010000 /* K7: page attribute table */
145 146 #define CPUID_AMD_EDX_FCMOV 0x00010000 /* FCMOVcc etc. */
146 147 #define CPUID_AMD_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */
147 148 /* 0x00040000 - reserved */
148 149 /* 0x00080000 - reserved */
149 150 #define CPUID_AMD_EDX_NX 0x00100000 /* AMD: no-execute page prot */
150 151 /* 0x00200000 - reserved */
151 152 #define CPUID_AMD_EDX_MMXamd 0x00400000 /* AMD: MMX extensions */
152 153 #define CPUID_AMD_EDX_MMX 0x00800000 /* MMX instructions */
153 154 #define CPUID_AMD_EDX_FXSR 0x01000000 /* fxsave and fxrstor */
154 155 #define CPUID_AMD_EDX_FFXSR 0x02000000 /* fast fxsave/fxrstor */
155 156 #define CPUID_AMD_EDX_1GPG 0x04000000 /* 1GB page */
156 157 #define CPUID_AMD_EDX_TSCP 0x08000000 /* rdtscp instruction */
157 158 /* 0x10000000 - reserved */
158 159 #define CPUID_AMD_EDX_LM 0x20000000 /* AMD: long mode */
159 160 #define CPUID_AMD_EDX_3DNowx 0x40000000 /* AMD: extensions to 3DNow! */
160 161 #define CPUID_AMD_EDX_3DNow 0x80000000 /* AMD: 3DNow! instructions */
161 162
162 163 #define CPUID_AMD_ECX_AHF64 0x00000001 /* LAHF and SAHF in long mode */
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163 164 #define CPUID_AMD_ECX_CMP_LGCY 0x00000002 /* AMD: multicore chip */
164 165 #define CPUID_AMD_ECX_SVM 0x00000004 /* AMD: secure VM */
165 166 #define CPUID_AMD_ECX_EAS 0x00000008 /* extended apic space */
166 167 #define CPUID_AMD_ECX_CR8D 0x00000010 /* AMD: 32-bit mov %cr8 */
167 168 #define CPUID_AMD_ECX_LZCNT 0x00000020 /* AMD: LZCNT insn */
168 169 #define CPUID_AMD_ECX_SSE4A 0x00000040 /* AMD: SSE4A insns */
169 170 #define CPUID_AMD_ECX_MAS 0x00000080 /* AMD: MisAlignSse mnode */
170 171 #define CPUID_AMD_ECX_3DNP 0x00000100 /* AMD: 3DNowPrefectch */
171 172 #define CPUID_AMD_ECX_OSVW 0x00000200 /* AMD: OSVW */
172 173 #define CPUID_AMD_ECX_IBS 0x00000400 /* AMD: IBS */
173 -#define CPUID_AMD_ECX_SSE5 0x00000800 /* AMD: SSE5 */
174 +#define CPUID_AMD_ECX_SSE5 0x00000800 /* AMD: Extended AVX */
174 175 #define CPUID_AMD_ECX_SKINIT 0x00001000 /* AMD: SKINIT */
175 176 #define CPUID_AMD_ECX_WDT 0x00002000 /* AMD: WDT */
177 + /* 0x00004000 - reserved */
178 +#define CPUID_AMD_ECX_LWP 0x00008000 /* AMD: Lightweight profiling */
179 +#define CPUID_AMD_ECX_FMA4 0x00010000 /* AMD: 4-operand FMA support */
180 + /* 0x00020000 - reserved */
181 + /* 0x00040000 - reserved */
182 +#define CPUID_AMD_ECX_NIDMSR 0x00080000 /* AMD: Node ID MSR */
183 + /* 0x00100000 - reserved */
184 +#define CPUID_AMD_ECX_TBM 0x00200000 /* AMD: trailing bit manips. */
176 185 #define CPUID_AMD_ECX_TOPOEXT 0x00400000 /* AMD: Topology Extensions */
177 186
178 187 /*
179 188 * AMD uses %ebx for some of their features (extended function 0x80000008).
180 189 */
181 190 #define CPUID_AMD_EBX_ERR_PTR_ZERO 0x00000004 /* AMD: FP Err. Ptr. Zero */
182 191
183 192 /*
184 193 * Intel now seems to have claimed part of the "extended" function
185 194 * space that we previously for non-Intel implementors to use.
186 195 * More excitingly still, they've claimed bit 20 to mean LAHF/SAHF
187 196 * is available in long mode i.e. what AMD indicate using bit 0.
188 197 * On the other hand, everything else is labelled as reserved.
189 198 */
190 199 #define CPUID_INTC_ECX_AHF64 0x00100000 /* LAHF and SAHF in long mode */
191 200
192 201 /*
193 202 * Intel also uses cpuid leaf 7 to have additional instructions and features.
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194 203 * Like some other leaves, but unlike the current ones we care about, it
195 204 * requires us to specify both a leaf in %eax and a sub-leaf in %ecx. To deal
196 205 * with the potential use of additional sub-leaves in the future, we now
197 206 * specifically label the EBX features with their leaf and sub-leaf.
198 207 */
199 208 #define CPUID_INTC_EBX_7_0_BMI1 0x00000008 /* BMI1 instrs */
200 209 #define CPUID_INTC_EBX_7_0_HLE 0x00000010 /* HLE */
201 210 #define CPUID_INTC_EBX_7_0_AVX2 0x00000020 /* AVX2 supported */
202 211 #define CPUID_INTC_EBX_7_0_SMEP 0x00000080 /* SMEP in CR4 */
203 212 #define CPUID_INTC_EBX_7_0_BMI2 0x00000100 /* BMI2 instrs */
213 +#define CPUID_INTC_EBX_7_0_INVPCID 0x00000400 /* invpcid instr */
204 214 #define CPUID_INTC_EBX_7_0_MPX 0x00004000 /* Mem. Prot. Ext. */
205 215 #define CPUID_INTC_EBX_7_0_AVX512F 0x00010000 /* AVX512 foundation */
206 216 #define CPUID_INTC_EBX_7_0_AVX512DQ 0x00020000 /* AVX512DQ */
207 217 #define CPUID_INTC_EBX_7_0_RDSEED 0x00040000 /* RDSEED instr */
208 218 #define CPUID_INTC_EBX_7_0_ADX 0x00080000 /* ADX instrs */
209 219 #define CPUID_INTC_EBX_7_0_SMAP 0x00100000 /* SMAP in CR 4 */
210 220 #define CPUID_INTC_EBX_7_0_AVX512IFMA 0x00200000 /* AVX512IFMA */
211 221 #define CPUID_INTC_EBX_7_0_CLWB 0x01000000 /* CLWB */
212 222 #define CPUID_INTC_EBX_7_0_AVX512PF 0x04000000 /* AVX512PF */
213 223 #define CPUID_INTC_EBX_7_0_AVX512ER 0x08000000 /* AVX512ER */
214 224 #define CPUID_INTC_EBX_7_0_AVX512CD 0x10000000 /* AVX512CD */
215 225 #define CPUID_INTC_EBX_7_0_SHA 0x20000000 /* SHA extensions */
216 226 #define CPUID_INTC_EBX_7_0_AVX512BW 0x40000000 /* AVX512BW */
217 227 #define CPUID_INTC_EBX_7_0_AVX512VL 0x80000000 /* AVX512VL */
218 228
219 229 #define CPUID_INTC_EBX_7_0_ALL_AVX512 \
220 230 (CPUID_INTC_EBX_7_0_AVX512F | CPUID_INTC_EBX_7_0_AVX512DQ | \
221 231 CPUID_INTC_EBX_7_0_AVX512IFMA | CPUID_INTC_EBX_7_0_AVX512PF | \
222 232 CPUID_INTC_EBX_7_0_AVX512ER | CPUID_INTC_EBX_7_0_AVX512CD | \
223 233 CPUID_INTC_EBX_7_0_AVX512BW | CPUID_INTC_EBX_7_0_AVX512VL)
224 234
225 235 #define CPUID_INTC_ECX_7_0_AVX512VBMI 0x00000002 /* AVX512VBMI */
226 236 #define CPUID_INTC_ECX_7_0_UMIP 0x00000004 /* UMIP */
227 237 #define CPUID_INTC_ECX_7_0_PKU 0x00000008 /* umode prot. keys */
228 238 #define CPUID_INTC_ECX_7_0_OSPKE 0x00000010 /* OSPKE */
229 239 #define CPUID_INTC_ECX_7_0_AVX512VPOPCDQ 0x00004000 /* AVX512 VPOPCNTDQ */
230 240
231 241 #define CPUID_INTC_ECX_7_0_ALL_AVX512 \
232 242 (CPUID_INTC_ECX_7_0_AVX512VBMI | CPUID_INTC_ECX_7_0_AVX512VPOPCDQ)
233 243
234 244 #define CPUID_INTC_EDX_7_0_AVX5124NNIW 0x00000004 /* AVX512 4NNIW */
235 245 #define CPUID_INTC_EDX_7_0_AVX5124FMAPS 0x00000008 /* AVX512 4FMAPS */
236 246
237 247 #define CPUID_INTC_EDX_7_0_ALL_AVX512 \
238 248 (CPUID_INTC_EDX_7_0_AVX5124NNIW | CPUID_INTC_EDX_7_0_AVX5124FMAPS)
239 249
240 250 /*
241 251 * Intel also uses cpuid leaf 0xd to report additional instructions and features
242 252 * when the sub-leaf in %ecx == 1. We label these using the same convention as
243 253 * with leaf 7.
244 254 */
245 255 #define CPUID_INTC_EAX_D_1_XSAVEOPT 0x00000001 /* xsaveopt inst. */
246 256 #define CPUID_INTC_EAX_D_1_XSAVEC 0x00000002 /* xsavec inst. */
247 257 #define CPUID_INTC_EAX_D_1_XSAVES 0x00000008 /* xsaves inst. */
248 258
249 259 #define REG_PAT 0x277
250 260 #define REG_TSC 0x10 /* timestamp counter */
251 261 #define REG_APIC_BASE_MSR 0x1b
252 262 #define REG_X2APIC_BASE_MSR 0x800 /* The MSR address offset of x2APIC */
253 263
254 264 #if !defined(__xpv)
255 265 /*
256 266 * AMD C1E
257 267 */
258 268 #define MSR_AMD_INT_PENDING_CMP_HALT 0xC0010055
259 269 #define AMD_ACTONCMPHALT_SHIFT 27
260 270 #define AMD_ACTONCMPHALT_MASK 3
261 271 #endif
262 272
263 273 #define MSR_DEBUGCTL 0x1d9
264 274
265 275 #define DEBUGCTL_LBR 0x01
266 276 #define DEBUGCTL_BTF 0x02
267 277
268 278 /* Intel P6, AMD */
269 279 #define MSR_LBR_FROM 0x1db
270 280 #define MSR_LBR_TO 0x1dc
271 281 #define MSR_LEX_FROM 0x1dd
272 282 #define MSR_LEX_TO 0x1de
273 283
274 284 /* Intel P4 (pre-Prescott, non P4 M) */
275 285 #define MSR_P4_LBSTK_TOS 0x1da
276 286 #define MSR_P4_LBSTK_0 0x1db
277 287 #define MSR_P4_LBSTK_1 0x1dc
278 288 #define MSR_P4_LBSTK_2 0x1dd
279 289 #define MSR_P4_LBSTK_3 0x1de
280 290
281 291 /* Intel Pentium M */
282 292 #define MSR_P6M_LBSTK_TOS 0x1c9
283 293 #define MSR_P6M_LBSTK_0 0x040
284 294 #define MSR_P6M_LBSTK_1 0x041
285 295 #define MSR_P6M_LBSTK_2 0x042
286 296 #define MSR_P6M_LBSTK_3 0x043
287 297 #define MSR_P6M_LBSTK_4 0x044
288 298 #define MSR_P6M_LBSTK_5 0x045
289 299 #define MSR_P6M_LBSTK_6 0x046
290 300 #define MSR_P6M_LBSTK_7 0x047
291 301
292 302 /* Intel P4 (Prescott) */
293 303 #define MSR_PRP4_LBSTK_TOS 0x1da
294 304 #define MSR_PRP4_LBSTK_FROM_0 0x680
295 305 #define MSR_PRP4_LBSTK_FROM_1 0x681
296 306 #define MSR_PRP4_LBSTK_FROM_2 0x682
297 307 #define MSR_PRP4_LBSTK_FROM_3 0x683
298 308 #define MSR_PRP4_LBSTK_FROM_4 0x684
299 309 #define MSR_PRP4_LBSTK_FROM_5 0x685
300 310 #define MSR_PRP4_LBSTK_FROM_6 0x686
301 311 #define MSR_PRP4_LBSTK_FROM_7 0x687
302 312 #define MSR_PRP4_LBSTK_FROM_8 0x688
303 313 #define MSR_PRP4_LBSTK_FROM_9 0x689
304 314 #define MSR_PRP4_LBSTK_FROM_10 0x68a
305 315 #define MSR_PRP4_LBSTK_FROM_11 0x68b
306 316 #define MSR_PRP4_LBSTK_FROM_12 0x68c
307 317 #define MSR_PRP4_LBSTK_FROM_13 0x68d
308 318 #define MSR_PRP4_LBSTK_FROM_14 0x68e
309 319 #define MSR_PRP4_LBSTK_FROM_15 0x68f
310 320 #define MSR_PRP4_LBSTK_TO_0 0x6c0
311 321 #define MSR_PRP4_LBSTK_TO_1 0x6c1
312 322 #define MSR_PRP4_LBSTK_TO_2 0x6c2
313 323 #define MSR_PRP4_LBSTK_TO_3 0x6c3
314 324 #define MSR_PRP4_LBSTK_TO_4 0x6c4
315 325 #define MSR_PRP4_LBSTK_TO_5 0x6c5
316 326 #define MSR_PRP4_LBSTK_TO_6 0x6c6
317 327 #define MSR_PRP4_LBSTK_TO_7 0x6c7
318 328 #define MSR_PRP4_LBSTK_TO_8 0x6c8
319 329 #define MSR_PRP4_LBSTK_TO_9 0x6c9
320 330 #define MSR_PRP4_LBSTK_TO_10 0x6ca
321 331 #define MSR_PRP4_LBSTK_TO_11 0x6cb
322 332 #define MSR_PRP4_LBSTK_TO_12 0x6cc
323 333 #define MSR_PRP4_LBSTK_TO_13 0x6cd
324 334 #define MSR_PRP4_LBSTK_TO_14 0x6ce
325 335 #define MSR_PRP4_LBSTK_TO_15 0x6cf
326 336
327 337 #define MCI_CTL_VALUE 0xffffffff
328 338
329 339 #define MTRR_TYPE_UC 0
330 340 #define MTRR_TYPE_WC 1
331 341 #define MTRR_TYPE_WT 4
332 342 #define MTRR_TYPE_WP 5
333 343 #define MTRR_TYPE_WB 6
334 344 #define MTRR_TYPE_UC_ 7
335 345
336 346 /*
337 347 * For Solaris we set up the page attritubute table in the following way:
338 348 * PAT0 Write-Back
339 349 * PAT1 Write-Through
340 350 * PAT2 Unchacheable-
341 351 * PAT3 Uncacheable
342 352 * PAT4 Write-Back
343 353 * PAT5 Write-Through
344 354 * PAT6 Write-Combine
345 355 * PAT7 Uncacheable
346 356 * The only difference from h/w default is entry 6.
347 357 */
348 358 #define PAT_DEFAULT_ATTRIBUTE \
349 359 ((uint64_t)MTRR_TYPE_WB | \
350 360 ((uint64_t)MTRR_TYPE_WT << 8) | \
351 361 ((uint64_t)MTRR_TYPE_UC_ << 16) | \
352 362 ((uint64_t)MTRR_TYPE_UC << 24) | \
353 363 ((uint64_t)MTRR_TYPE_WB << 32) | \
354 364 ((uint64_t)MTRR_TYPE_WT << 40) | \
355 365 ((uint64_t)MTRR_TYPE_WC << 48) | \
356 366 ((uint64_t)MTRR_TYPE_UC << 56))
357 367
358 368 #define X86FSET_LARGEPAGE 0
359 369 #define X86FSET_TSC 1
360 370 #define X86FSET_MSR 2
361 371 #define X86FSET_MTRR 3
362 372 #define X86FSET_PGE 4
363 373 #define X86FSET_DE 5
364 374 #define X86FSET_CMOV 6
365 375 #define X86FSET_MMX 7
366 376 #define X86FSET_MCA 8
367 377 #define X86FSET_PAE 9
368 378 #define X86FSET_CX8 10
369 379 #define X86FSET_PAT 11
370 380 #define X86FSET_SEP 12
371 381 #define X86FSET_SSE 13
372 382 #define X86FSET_SSE2 14
373 383 #define X86FSET_HTT 15
374 384 #define X86FSET_ASYSC 16
375 385 #define X86FSET_NX 17
376 386 #define X86FSET_SSE3 18
377 387 #define X86FSET_CX16 19
378 388 #define X86FSET_CMP 20
379 389 #define X86FSET_TSCP 21
380 390 #define X86FSET_MWAIT 22
381 391 #define X86FSET_SSE4A 23
382 392 #define X86FSET_CPUID 24
383 393 #define X86FSET_SSSE3 25
384 394 #define X86FSET_SSE4_1 26
385 395 #define X86FSET_SSE4_2 27
386 396 #define X86FSET_1GPG 28
387 397 #define X86FSET_CLFSH 29
388 398 #define X86FSET_64 30
389 399 #define X86FSET_AES 31
390 400 #define X86FSET_PCLMULQDQ 32
391 401 #define X86FSET_XSAVE 33
392 402 #define X86FSET_AVX 34
393 403 #define X86FSET_VMX 35
394 404 #define X86FSET_SVM 36
395 405 #define X86FSET_TOPOEXT 37
396 406 #define X86FSET_F16C 38
397 407 #define X86FSET_RDRAND 39
398 408 #define X86FSET_X2APIC 40
399 409 #define X86FSET_AVX2 41
400 410 #define X86FSET_BMI1 42
401 411 #define X86FSET_BMI2 43
402 412 #define X86FSET_FMA 44
403 413 #define X86FSET_SMEP 45
404 414 #define X86FSET_SMAP 46
405 415 #define X86FSET_ADX 47
406 416 #define X86FSET_RDSEED 48
407 417 #define X86FSET_MPX 49
408 418 #define X86FSET_AVX512F 50
409 419 #define X86FSET_AVX512DQ 51
410 420 #define X86FSET_AVX512PF 52
411 421 #define X86FSET_AVX512ER 53
412 422 #define X86FSET_AVX512CD 54
413 423 #define X86FSET_AVX512BW 55
414 424 #define X86FSET_AVX512VL 56
415 425 #define X86FSET_AVX512FMA 57
416 426 #define X86FSET_AVX512VBMI 58
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417 427 #define X86FSET_AVX512VPOPCDQ 59
418 428 #define X86FSET_AVX512NNIW 60
419 429 #define X86FSET_AVX512FMAPS 61
420 430 #define X86FSET_XSAVEOPT 62
421 431 #define X86FSET_XSAVEC 63
422 432 #define X86FSET_XSAVES 64
423 433 #define X86FSET_SHA 65
424 434 #define X86FSET_UMIP 66
425 435 #define X86FSET_PKU 67
426 436 #define X86FSET_OSPKE 68
437 +#define X86FSET_PCID 69
438 +#define X86FSET_INVPCID 70
427 439
428 440 /*
429 441 * Intel Deep C-State invariant TSC in leaf 0x80000007.
430 442 */
431 443 #define CPUID_TSC_CSTATE_INVARIANCE (0x100)
432 444
433 445 /*
434 446 * Intel Deep C-state always-running local APIC timer
435 447 */
436 448 #define CPUID_CSTATE_ARAT (0x4)
437 449
438 450 /*
439 451 * Intel ENERGY_PERF_BIAS MSR indicated by feature bit CPUID.6.ECX[3].
440 452 */
441 453 #define CPUID_EPB_SUPPORT (1 << 3)
442 454
443 455 /*
444 456 * Intel TSC deadline timer
445 457 */
446 458 #define CPUID_DEADLINE_TSC (1 << 24)
447 459
448 460 /*
449 461 * x86_type is a legacy concept; this is supplanted
450 462 * for most purposes by x86_featureset; modern CPUs
451 463 * should be X86_TYPE_OTHER
452 464 */
453 465 #define X86_TYPE_OTHER 0
454 466 #define X86_TYPE_486 1
455 467 #define X86_TYPE_P5 2
456 468 #define X86_TYPE_P6 3
457 469 #define X86_TYPE_CYRIX_486 4
458 470 #define X86_TYPE_CYRIX_6x86L 5
459 471 #define X86_TYPE_CYRIX_6x86 6
460 472 #define X86_TYPE_CYRIX_GXm 7
461 473 #define X86_TYPE_CYRIX_6x86MX 8
462 474 #define X86_TYPE_CYRIX_MediaGX 9
463 475 #define X86_TYPE_CYRIX_MII 10
464 476 #define X86_TYPE_VIA_CYRIX_III 11
465 477 #define X86_TYPE_P4 12
466 478
467 479 /*
468 480 * x86_vendor allows us to select between
469 481 * implementation features and helps guide
470 482 * the interpretation of the cpuid instruction.
471 483 */
472 484 #define X86_VENDOR_Intel 0
473 485 #define X86_VENDORSTR_Intel "GenuineIntel"
474 486
475 487 #define X86_VENDOR_IntelClone 1
476 488
477 489 #define X86_VENDOR_AMD 2
478 490 #define X86_VENDORSTR_AMD "AuthenticAMD"
479 491
480 492 #define X86_VENDOR_Cyrix 3
481 493 #define X86_VENDORSTR_CYRIX "CyrixInstead"
482 494
483 495 #define X86_VENDOR_UMC 4
484 496 #define X86_VENDORSTR_UMC "UMC UMC UMC "
485 497
486 498 #define X86_VENDOR_NexGen 5
487 499 #define X86_VENDORSTR_NexGen "NexGenDriven"
488 500
489 501 #define X86_VENDOR_Centaur 6
490 502 #define X86_VENDORSTR_Centaur "CentaurHauls"
491 503
492 504 #define X86_VENDOR_Rise 7
493 505 #define X86_VENDORSTR_Rise "RiseRiseRise"
494 506
495 507 #define X86_VENDOR_SiS 8
496 508 #define X86_VENDORSTR_SiS "SiS SiS SiS "
497 509
498 510 #define X86_VENDOR_TM 9
499 511 #define X86_VENDORSTR_TM "GenuineTMx86"
500 512
501 513 #define X86_VENDOR_NSC 10
502 514 #define X86_VENDORSTR_NSC "Geode by NSC"
503 515
504 516 /*
505 517 * Vendor string max len + \0
506 518 */
507 519 #define X86_VENDOR_STRLEN 13
508 520
509 521 /*
510 522 * Some vendor/family/model/stepping ranges are commonly grouped under
511 523 * a single identifying banner by the vendor. The following encode
512 524 * that "revision" in a uint32_t with the 8 most significant bits
513 525 * identifying the vendor with X86_VENDOR_*, the next 8 identifying the
514 526 * family, and the remaining 16 typically forming a bitmask of revisions
515 527 * within that family with more significant bits indicating "later" revisions.
516 528 */
517 529
518 530 #define _X86_CHIPREV_VENDOR_MASK 0xff000000u
519 531 #define _X86_CHIPREV_VENDOR_SHIFT 24
520 532 #define _X86_CHIPREV_FAMILY_MASK 0x00ff0000u
521 533 #define _X86_CHIPREV_FAMILY_SHIFT 16
522 534 #define _X86_CHIPREV_REV_MASK 0x0000ffffu
523 535
524 536 #define _X86_CHIPREV_VENDOR(x) \
525 537 (((x) & _X86_CHIPREV_VENDOR_MASK) >> _X86_CHIPREV_VENDOR_SHIFT)
526 538 #define _X86_CHIPREV_FAMILY(x) \
527 539 (((x) & _X86_CHIPREV_FAMILY_MASK) >> _X86_CHIPREV_FAMILY_SHIFT)
528 540 #define _X86_CHIPREV_REV(x) \
529 541 ((x) & _X86_CHIPREV_REV_MASK)
530 542
531 543 /* True if x matches in vendor and family and if x matches the given rev mask */
532 544 #define X86_CHIPREV_MATCH(x, mask) \
533 545 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(mask) && \
534 546 _X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(mask) && \
535 547 ((_X86_CHIPREV_REV(x) & _X86_CHIPREV_REV(mask)) != 0))
536 548
537 549 /* True if x matches in vendor and family, and rev is at least minx */
538 550 #define X86_CHIPREV_ATLEAST(x, minx) \
539 551 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(minx) && \
540 552 _X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(minx) && \
541 553 _X86_CHIPREV_REV(x) >= _X86_CHIPREV_REV(minx))
542 554
543 555 #define _X86_CHIPREV_MKREV(vendor, family, rev) \
544 556 ((uint32_t)(vendor) << _X86_CHIPREV_VENDOR_SHIFT | \
545 557 (family) << _X86_CHIPREV_FAMILY_SHIFT | (rev))
546 558
547 559 /* True if x matches in vendor, and family is at least minx */
548 560 #define X86_CHIPFAM_ATLEAST(x, minx) \
549 561 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(minx) && \
550 562 _X86_CHIPREV_FAMILY(x) >= _X86_CHIPREV_FAMILY(minx))
551 563
552 564 /* Revision default */
553 565 #define X86_CHIPREV_UNKNOWN 0x0
554 566
555 567 /*
556 568 * Definitions for AMD Family 0xf. Minor revisions C0 and CG are
557 569 * sufficiently different that we will distinguish them; in all other
558 570 * case we will identify the major revision.
559 571 */
560 572 #define X86_CHIPREV_AMD_F_REV_B _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0001)
561 573 #define X86_CHIPREV_AMD_F_REV_C0 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0002)
562 574 #define X86_CHIPREV_AMD_F_REV_CG _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0004)
563 575 #define X86_CHIPREV_AMD_F_REV_D _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0008)
564 576 #define X86_CHIPREV_AMD_F_REV_E _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0010)
565 577 #define X86_CHIPREV_AMD_F_REV_F _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0020)
566 578 #define X86_CHIPREV_AMD_F_REV_G _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0040)
567 579
568 580 /*
569 581 * Definitions for AMD Family 0x10. Rev A was Engineering Samples only.
570 582 */
571 583 #define X86_CHIPREV_AMD_10_REV_A \
572 584 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0001)
573 585 #define X86_CHIPREV_AMD_10_REV_B \
574 586 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0002)
575 587 #define X86_CHIPREV_AMD_10_REV_C2 \
576 588 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0004)
577 589 #define X86_CHIPREV_AMD_10_REV_C3 \
578 590 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0008)
579 591 #define X86_CHIPREV_AMD_10_REV_D0 \
580 592 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0010)
581 593 #define X86_CHIPREV_AMD_10_REV_D1 \
582 594 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0020)
583 595 #define X86_CHIPREV_AMD_10_REV_E \
584 596 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0040)
585 597
586 598 /*
587 599 * Definitions for AMD Family 0x11.
588 600 */
589 601 #define X86_CHIPREV_AMD_11_REV_B \
590 602 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x11, 0x0002)
591 603
592 604 /*
593 605 * Definitions for AMD Family 0x12.
594 606 */
595 607 #define X86_CHIPREV_AMD_12_REV_B \
596 608 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x12, 0x0002)
597 609
598 610 /*
599 611 * Definitions for AMD Family 0x14.
600 612 */
601 613 #define X86_CHIPREV_AMD_14_REV_B \
602 614 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x14, 0x0002)
603 615 #define X86_CHIPREV_AMD_14_REV_C \
604 616 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x14, 0x0004)
605 617
606 618 /*
607 619 * Definitions for AMD Family 0x15
608 620 */
609 621 #define X86_CHIPREV_AMD_15OR_REV_B2 \
610 622 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0001)
611 623
612 624 #define X86_CHIPREV_AMD_15TN_REV_A1 \
613 625 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0002)
614 626
615 627 /*
616 628 * Various socket/package types, extended as the need to distinguish
617 629 * a new type arises. The top 8 byte identfies the vendor and the
618 630 * remaining 24 bits describe 24 socket types.
619 631 */
620 632
621 633 #define _X86_SOCKET_VENDOR_SHIFT 24
622 634 #define _X86_SOCKET_VENDOR(x) ((x) >> _X86_SOCKET_VENDOR_SHIFT)
623 635 #define _X86_SOCKET_TYPE_MASK 0x00ffffff
624 636 #define _X86_SOCKET_TYPE(x) ((x) & _X86_SOCKET_TYPE_MASK)
625 637
626 638 #define _X86_SOCKET_MKVAL(vendor, bitval) \
627 639 ((uint32_t)(vendor) << _X86_SOCKET_VENDOR_SHIFT | (bitval))
628 640
629 641 #define X86_SOCKET_MATCH(s, mask) \
630 642 (_X86_SOCKET_VENDOR(s) == _X86_SOCKET_VENDOR(mask) && \
631 643 (_X86_SOCKET_TYPE(s) & _X86_SOCKET_TYPE(mask)) != 0)
632 644
633 645 #define X86_SOCKET_UNKNOWN 0x0
634 646 /*
635 647 * AMD socket types
636 648 */
637 649 #define X86_SOCKET_754 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000001)
638 650 #define X86_SOCKET_939 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000002)
639 651 #define X86_SOCKET_940 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000004)
640 652 #define X86_SOCKET_S1g1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000008)
641 653 #define X86_SOCKET_AM2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000010)
642 654 #define X86_SOCKET_F1207 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000020)
643 655 #define X86_SOCKET_S1g2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000040)
644 656 #define X86_SOCKET_S1g3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000080)
645 657 #define X86_SOCKET_AM _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000100)
646 658 #define X86_SOCKET_AM2R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000200)
647 659 #define X86_SOCKET_AM3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000400)
648 660 #define X86_SOCKET_G34 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000800)
649 661 #define X86_SOCKET_ASB2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x001000)
650 662 #define X86_SOCKET_C32 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x002000)
651 663 #define X86_SOCKET_S1g4 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x004000)
652 664 #define X86_SOCKET_FT1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x008000)
653 665 #define X86_SOCKET_FM1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x010000)
654 666 #define X86_SOCKET_FS1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x020000)
655 667 #define X86_SOCKET_AM3R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x040000)
656 668 #define X86_SOCKET_FP2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x080000)
657 669 #define X86_SOCKET_FS1R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x100000)
658 670 #define X86_SOCKET_FM2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x200000)
659 671
660 672 /*
661 673 * xgetbv/xsetbv support
662 674 * See section 13.3 in vol. 1 of the Intel devlopers manual.
663 675 */
664 676
665 677 #define XFEATURE_ENABLED_MASK 0x0
666 678 /*
667 679 * XFEATURE_ENABLED_MASK values (eax)
668 680 * See setup_xfem().
669 681 */
670 682 #define XFEATURE_LEGACY_FP 0x1
671 683 #define XFEATURE_SSE 0x2
672 684 #define XFEATURE_AVX 0x4
673 685 #define XFEATURE_MPX 0x18 /* 2 bits, both 0 or 1 */
674 686 #define XFEATURE_AVX512 0xe0 /* 3 bits, all 0 or 1 */
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675 687 /* bit 8 unused */
676 688 #define XFEATURE_PKRU 0x200
677 689 #define XFEATURE_FP_ALL \
678 690 (XFEATURE_LEGACY_FP | XFEATURE_SSE | XFEATURE_AVX | XFEATURE_MPX | \
679 691 XFEATURE_AVX512 | XFEATURE_PKRU)
680 692
681 693 #if !defined(_ASM)
682 694
683 695 #if defined(_KERNEL) || defined(_KMEMUSER)
684 696
685 -#define NUM_X86_FEATURES 69
697 +#define NUM_X86_FEATURES 71
686 698 extern uchar_t x86_featureset[];
687 699
688 700 extern void free_x86_featureset(void *featureset);
689 701 extern boolean_t is_x86_feature(void *featureset, uint_t feature);
690 702 extern void add_x86_feature(void *featureset, uint_t feature);
691 703 extern void remove_x86_feature(void *featureset, uint_t feature);
692 704 extern boolean_t compare_x86_featureset(void *setA, void *setB);
693 705 extern void print_x86_featureset(void *featureset);
694 706
695 707
696 708 extern uint_t x86_type;
697 709 extern uint_t x86_vendor;
698 710 extern uint_t x86_clflush_size;
699 711
700 712 extern uint_t pentiumpro_bug4046376;
701 713
702 714 extern const char CyrixInstead[];
703 715
704 716 #endif
705 717
706 718 #if defined(_KERNEL)
707 719
708 720 /*
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709 721 * This structure is used to pass arguments and get return values back
710 722 * from the CPUID instruction in __cpuid_insn() routine.
711 723 */
712 724 struct cpuid_regs {
713 725 uint32_t cp_eax;
714 726 uint32_t cp_ebx;
715 727 uint32_t cp_ecx;
716 728 uint32_t cp_edx;
717 729 };
718 730
731 +extern int x86_use_pcid;
732 +extern int x86_use_invpcid;
733 +
719 734 /*
720 735 * Utility functions to get/set extended control registers (XCR)
721 736 * Initial use is to get/set the contents of the XFEATURE_ENABLED_MASK.
722 737 */
723 738 extern uint64_t get_xcr(uint_t);
724 739 extern void set_xcr(uint_t, uint64_t);
725 740
726 741 extern uint64_t rdmsr(uint_t);
727 742 extern void wrmsr(uint_t, const uint64_t);
728 743 extern uint64_t xrdmsr(uint_t);
729 744 extern void xwrmsr(uint_t, const uint64_t);
730 745 extern int checked_rdmsr(uint_t, uint64_t *);
731 746 extern int checked_wrmsr(uint_t, uint64_t);
732 747
733 748 extern void invalidate_cache(void);
734 749 extern ulong_t getcr4(void);
735 750 extern void setcr4(ulong_t);
736 751
737 752 extern void mtrr_sync(void);
738 753
739 754 extern void cpu_fast_syscall_enable(void *);
740 755 extern void cpu_fast_syscall_disable(void *);
741 756
742 757 struct cpu;
743 758
744 759 extern int cpuid_checkpass(struct cpu *, int);
745 760 extern uint32_t cpuid_insn(struct cpu *, struct cpuid_regs *);
746 761 extern uint32_t __cpuid_insn(struct cpuid_regs *);
747 762 extern int cpuid_getbrandstr(struct cpu *, char *, size_t);
748 763 extern int cpuid_getidstr(struct cpu *, char *, size_t);
749 764 extern const char *cpuid_getvendorstr(struct cpu *);
750 765 extern uint_t cpuid_getvendor(struct cpu *);
751 766 extern uint_t cpuid_getfamily(struct cpu *);
752 767 extern uint_t cpuid_getmodel(struct cpu *);
753 768 extern uint_t cpuid_getstep(struct cpu *);
754 769 extern uint_t cpuid_getsig(struct cpu *);
755 770 extern uint_t cpuid_get_ncpu_per_chip(struct cpu *);
756 771 extern uint_t cpuid_get_ncore_per_chip(struct cpu *);
757 772 extern uint_t cpuid_get_ncpu_sharing_last_cache(struct cpu *);
758 773 extern id_t cpuid_get_last_lvl_cacheid(struct cpu *);
759 774 extern int cpuid_get_chipid(struct cpu *);
760 775 extern id_t cpuid_get_coreid(struct cpu *);
761 776 extern int cpuid_get_pkgcoreid(struct cpu *);
762 777 extern int cpuid_get_clogid(struct cpu *);
763 778 extern int cpuid_get_cacheid(struct cpu *);
764 779 extern uint32_t cpuid_get_apicid(struct cpu *);
765 780 extern uint_t cpuid_get_procnodeid(struct cpu *cpu);
766 781 extern uint_t cpuid_get_procnodes_per_pkg(struct cpu *cpu);
767 782 extern uint_t cpuid_get_compunitid(struct cpu *cpu);
768 783 extern uint_t cpuid_get_cores_per_compunit(struct cpu *cpu);
769 784 extern size_t cpuid_get_xsave_size();
770 785 extern boolean_t cpuid_need_fp_excp_handling();
771 786 extern int cpuid_is_cmt(struct cpu *);
772 787 extern int cpuid_syscall32_insn(struct cpu *);
773 788 extern int getl2cacheinfo(struct cpu *, int *, int *, int *);
774 789
775 790 extern uint32_t cpuid_getchiprev(struct cpu *);
776 791 extern const char *cpuid_getchiprevstr(struct cpu *);
777 792 extern uint32_t cpuid_getsockettype(struct cpu *);
778 793 extern const char *cpuid_getsocketstr(struct cpu *);
779 794
780 795 extern int cpuid_have_cr8access(struct cpu *);
781 796
782 797 extern int cpuid_opteron_erratum(struct cpu *, uint_t);
783 798
784 799 struct cpuid_info;
785 800
786 801 extern void setx86isalist(void);
787 802 extern void cpuid_alloc_space(struct cpu *);
788 803 extern void cpuid_free_space(struct cpu *);
789 804 extern void cpuid_pass1(struct cpu *, uchar_t *);
790 805 extern void cpuid_pass2(struct cpu *);
791 806 extern void cpuid_pass3(struct cpu *);
792 807 extern void cpuid_pass4(struct cpu *, uint_t *);
793 808 extern void cpuid_set_cpu_properties(void *, processorid_t,
794 809 struct cpuid_info *);
795 810
796 811 extern void cpuid_get_addrsize(struct cpu *, uint_t *, uint_t *);
797 812 extern uint_t cpuid_get_dtlb_nent(struct cpu *, size_t);
798 813
799 814 #if !defined(__xpv)
800 815 extern uint32_t *cpuid_mwait_alloc(struct cpu *);
801 816 extern void cpuid_mwait_free(struct cpu *);
802 817 extern int cpuid_deep_cstates_supported(void);
803 818 extern int cpuid_arat_supported(void);
804 819 extern int cpuid_iepb_supported(struct cpu *);
805 820 extern int cpuid_deadline_tsc_supported(void);
806 821 extern void vmware_port(int, uint32_t *);
807 822 #endif
808 823
809 824 struct cpu_ucode_info;
810 825
811 826 extern void ucode_alloc_space(struct cpu *);
812 827 extern void ucode_free_space(struct cpu *);
813 828 extern void ucode_check(struct cpu *);
814 829 extern void ucode_cleanup();
815 830
816 831 #if !defined(__xpv)
817 832 extern char _tsc_mfence_start;
818 833 extern char _tsc_mfence_end;
819 834 extern char _tscp_start;
820 835 extern char _tscp_end;
821 836 extern char _no_rdtsc_start;
822 837 extern char _no_rdtsc_end;
823 838 extern char _tsc_lfence_start;
824 839 extern char _tsc_lfence_end;
825 840 #endif
826 841
827 842 #if !defined(__xpv)
828 843 extern char bcopy_patch_start;
829 844 extern char bcopy_patch_end;
830 845 extern char bcopy_ck_size;
831 846 #endif
832 847
833 848 extern void post_startup_cpu_fixups(void);
834 849
835 850 extern uint_t workaround_errata(struct cpu *);
836 851
837 852 #if defined(OPTERON_ERRATUM_93)
838 853 extern int opteron_erratum_93;
839 854 #endif
840 855
841 856 #if defined(OPTERON_ERRATUM_91)
842 857 extern int opteron_erratum_91;
843 858 #endif
844 859
845 860 #if defined(OPTERON_ERRATUM_100)
846 861 extern int opteron_erratum_100;
847 862 #endif
848 863
849 864 #if defined(OPTERON_ERRATUM_121)
850 865 extern int opteron_erratum_121;
851 866 #endif
852 867
853 868 #if defined(OPTERON_WORKAROUND_6323525)
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854 869 extern int opteron_workaround_6323525;
855 870 extern void patch_workaround_6323525(void);
856 871 #endif
857 872
858 873 #if !defined(__xpv)
859 874 extern void determine_platform(void);
860 875 #endif
861 876 extern int get_hwenv(void);
862 877 extern int is_controldom(void);
863 878
879 +extern void enable_pcid(void);
880 +
864 881 extern void xsave_setup_msr(struct cpu *);
865 882
866 883 /*
867 884 * Hypervisor signatures
868 885 */
869 886 #define HVSIG_XEN_HVM "XenVMMXenVMM"
870 887 #define HVSIG_VMWARE "VMwareVMware"
871 888 #define HVSIG_KVM "KVMKVMKVM"
872 889 #define HVSIG_MICROSOFT "Microsoft Hv"
873 890
874 891 /*
875 892 * Defined hardware environments
876 893 */
877 894 #define HW_NATIVE (1 << 0) /* Running on bare metal */
878 895 #define HW_XEN_PV (1 << 1) /* Running on Xen PVM */
879 896
880 897 #define HW_XEN_HVM (1 << 2) /* Running on Xen HVM */
881 898 #define HW_VMWARE (1 << 3) /* Running on VMware hypervisor */
882 899 #define HW_KVM (1 << 4) /* Running on KVM hypervisor */
883 900 #define HW_MICROSOFT (1 << 5) /* Running on Microsoft hypervisor */
884 901
885 902 #define HW_VIRTUAL (HW_XEN_HVM | HW_VMWARE | HW_KVM | HW_MICROSOFT)
886 903
887 904 #endif /* _KERNEL */
888 905
889 906 #endif /* !_ASM */
890 907
891 908 /*
892 909 * VMware hypervisor related defines
893 910 */
894 911 #define VMWARE_HVMAGIC 0x564d5868
895 912 #define VMWARE_HVPORT 0x5658
896 913 #define VMWARE_HVCMD_GETVERSION 0x0a
897 914 #define VMWARE_HVCMD_GETTSCFREQ 0x2d
898 915
899 916 #ifdef __cplusplus
900 917 }
901 918 #endif
902 919
903 920 #endif /* _SYS_X86_ARCHEXT_H */
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