10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21 /*
22 * Copyright (c) 1995, 2010, Oracle and/or its affiliates. All rights reserved.
23 * Copyright (c) 2011 by Delphix. All rights reserved.
24 */
25 /*
26 * Copyright (c) 2010, Intel Corporation.
27 * All rights reserved.
28 */
29 /*
30 * Copyright 2017 Joyent, Inc.
31 * Copyright 2012 Jens Elkner <jel+illumos@cs.uni-magdeburg.de>
32 * Copyright 2012 Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org>
33 * Copyright 2014 Josef 'Jeff' Sipek <jeffpc@josefsipek.net>
34 * Copyright 2018 Nexenta Systems, Inc.
35 */
36
37 #ifndef _SYS_X86_ARCHEXT_H
38 #define _SYS_X86_ARCHEXT_H
39
40 #if !defined(_ASM)
41 #include <sys/regset.h>
42 #include <sys/processor.h>
43 #include <vm/seg_enum.h>
44 #include <vm/page.h>
45 #endif /* _ASM */
46
47 #ifdef __cplusplus
48 extern "C" {
49 #endif
50
74 #define CPUID_INTC_EDX_CLFSH 0x00080000 /* clflush instruction */
75 /* 0x100000 - reserved */
76 #define CPUID_INTC_EDX_DS 0x00200000 /* debug store exists */
77 #define CPUID_INTC_EDX_ACPI 0x00400000 /* monitoring + clock ctrl */
78 #define CPUID_INTC_EDX_MMX 0x00800000 /* MMX instructions */
79 #define CPUID_INTC_EDX_FXSR 0x01000000 /* fxsave and fxrstor */
80 #define CPUID_INTC_EDX_SSE 0x02000000 /* streaming SIMD extensions */
81 #define CPUID_INTC_EDX_SSE2 0x04000000 /* SSE extensions */
82 #define CPUID_INTC_EDX_SS 0x08000000 /* self-snoop */
83 #define CPUID_INTC_EDX_HTT 0x10000000 /* Hyper Thread Technology */
84 #define CPUID_INTC_EDX_TM 0x20000000 /* thermal monitoring */
85 #define CPUID_INTC_EDX_IA64 0x40000000 /* Itanium emulating IA32 */
86 #define CPUID_INTC_EDX_PBE 0x80000000 /* Pending Break Enable */
87
88 /*
89 * cpuid instruction feature flags in %ecx (standard function 1)
90 */
91
92 #define CPUID_INTC_ECX_SSE3 0x00000001 /* Yet more SSE extensions */
93 #define CPUID_INTC_ECX_PCLMULQDQ 0x00000002 /* PCLMULQDQ insn */
94 /* 0x00000004 - reserved */
95 #define CPUID_INTC_ECX_MON 0x00000008 /* MONITOR/MWAIT */
96 #define CPUID_INTC_ECX_DSCPL 0x00000010 /* CPL-qualified debug store */
97 #define CPUID_INTC_ECX_VMX 0x00000020 /* Hardware VM extensions */
98 #define CPUID_INTC_ECX_SMX 0x00000040 /* Secure mode extensions */
99 #define CPUID_INTC_ECX_EST 0x00000080 /* enhanced SpeedStep */
100 #define CPUID_INTC_ECX_TM2 0x00000100 /* thermal monitoring */
101 #define CPUID_INTC_ECX_SSSE3 0x00000200 /* Supplemental SSE3 insns */
102 #define CPUID_INTC_ECX_CID 0x00000400 /* L1 context ID */
103 /* 0x00000800 - reserved */
104 #define CPUID_INTC_ECX_FMA 0x00001000 /* Fused Multiply Add */
105 #define CPUID_INTC_ECX_CX16 0x00002000 /* cmpxchg16 */
106 #define CPUID_INTC_ECX_ETPRD 0x00004000 /* extended task pri messages */
107 /* 0x00008000 - reserved */
108 /* 0x00010000 - reserved */
109 /* 0x00020000 - reserved */
110 #define CPUID_INTC_ECX_DCA 0x00040000 /* direct cache access */
111 #define CPUID_INTC_ECX_SSE4_1 0x00080000 /* SSE4.1 insns */
112 #define CPUID_INTC_ECX_SSE4_2 0x00100000 /* SSE4.2 insns */
113 #define CPUID_INTC_ECX_X2APIC 0x00200000 /* x2APIC */
114 #define CPUID_INTC_ECX_MOVBE 0x00400000 /* MOVBE insn */
115 #define CPUID_INTC_ECX_POPCNT 0x00800000 /* POPCNT insn */
116 #define CPUID_INTC_ECX_AES 0x02000000 /* AES insns */
117 #define CPUID_INTC_ECX_XSAVE 0x04000000 /* XSAVE/XRESTOR insns */
118 #define CPUID_INTC_ECX_OSXSAVE 0x08000000 /* OS supports XSAVE insns */
119 #define CPUID_INTC_ECX_AVX 0x10000000 /* AVX supported */
120 #define CPUID_INTC_ECX_F16C 0x20000000 /* F16C supported */
121 #define CPUID_INTC_ECX_RDRAND 0x40000000 /* RDRAND supported */
122 #define CPUID_INTC_ECX_HV 0x80000000 /* Hypervisor */
123
124 /*
125 * cpuid instruction feature flags in %edx (extended function 0x80000001)
126 */
127
128 #define CPUID_AMD_EDX_FPU 0x00000001 /* x87 fpu present */
129 #define CPUID_AMD_EDX_VME 0x00000002 /* virtual-8086 extension */
130 #define CPUID_AMD_EDX_DE 0x00000004 /* debugging extensions */
131 #define CPUID_AMD_EDX_PSE 0x00000008 /* page size extensions */
132 #define CPUID_AMD_EDX_TSC 0x00000010 /* time stamp counter */
133 #define CPUID_AMD_EDX_MSR 0x00000020 /* rdmsr and wrmsr */
134 #define CPUID_AMD_EDX_PAE 0x00000040 /* physical addr extension */
135 #define CPUID_AMD_EDX_MCE 0x00000080 /* machine check exception */
153 #define CPUID_AMD_EDX_FXSR 0x01000000 /* fxsave and fxrstor */
154 #define CPUID_AMD_EDX_FFXSR 0x02000000 /* fast fxsave/fxrstor */
155 #define CPUID_AMD_EDX_1GPG 0x04000000 /* 1GB page */
156 #define CPUID_AMD_EDX_TSCP 0x08000000 /* rdtscp instruction */
157 /* 0x10000000 - reserved */
158 #define CPUID_AMD_EDX_LM 0x20000000 /* AMD: long mode */
159 #define CPUID_AMD_EDX_3DNowx 0x40000000 /* AMD: extensions to 3DNow! */
160 #define CPUID_AMD_EDX_3DNow 0x80000000 /* AMD: 3DNow! instructions */
161
162 #define CPUID_AMD_ECX_AHF64 0x00000001 /* LAHF and SAHF in long mode */
163 #define CPUID_AMD_ECX_CMP_LGCY 0x00000002 /* AMD: multicore chip */
164 #define CPUID_AMD_ECX_SVM 0x00000004 /* AMD: secure VM */
165 #define CPUID_AMD_ECX_EAS 0x00000008 /* extended apic space */
166 #define CPUID_AMD_ECX_CR8D 0x00000010 /* AMD: 32-bit mov %cr8 */
167 #define CPUID_AMD_ECX_LZCNT 0x00000020 /* AMD: LZCNT insn */
168 #define CPUID_AMD_ECX_SSE4A 0x00000040 /* AMD: SSE4A insns */
169 #define CPUID_AMD_ECX_MAS 0x00000080 /* AMD: MisAlignSse mnode */
170 #define CPUID_AMD_ECX_3DNP 0x00000100 /* AMD: 3DNowPrefectch */
171 #define CPUID_AMD_ECX_OSVW 0x00000200 /* AMD: OSVW */
172 #define CPUID_AMD_ECX_IBS 0x00000400 /* AMD: IBS */
173 #define CPUID_AMD_ECX_SSE5 0x00000800 /* AMD: SSE5 */
174 #define CPUID_AMD_ECX_SKINIT 0x00001000 /* AMD: SKINIT */
175 #define CPUID_AMD_ECX_WDT 0x00002000 /* AMD: WDT */
176 #define CPUID_AMD_ECX_TOPOEXT 0x00400000 /* AMD: Topology Extensions */
177
178 /*
179 * AMD uses %ebx for some of their features (extended function 0x80000008).
180 */
181 #define CPUID_AMD_EBX_ERR_PTR_ZERO 0x00000004 /* AMD: FP Err. Ptr. Zero */
182
183 /*
184 * Intel now seems to have claimed part of the "extended" function
185 * space that we previously for non-Intel implementors to use.
186 * More excitingly still, they've claimed bit 20 to mean LAHF/SAHF
187 * is available in long mode i.e. what AMD indicate using bit 0.
188 * On the other hand, everything else is labelled as reserved.
189 */
190 #define CPUID_INTC_ECX_AHF64 0x00100000 /* LAHF and SAHF in long mode */
191
192 /*
193 * Intel also uses cpuid leaf 7 to have additional instructions and features.
194 * Like some other leaves, but unlike the current ones we care about, it
195 * requires us to specify both a leaf in %eax and a sub-leaf in %ecx. To deal
196 * with the potential use of additional sub-leaves in the future, we now
197 * specifically label the EBX features with their leaf and sub-leaf.
198 */
199 #define CPUID_INTC_EBX_7_0_BMI1 0x00000008 /* BMI1 instrs */
200 #define CPUID_INTC_EBX_7_0_HLE 0x00000010 /* HLE */
201 #define CPUID_INTC_EBX_7_0_AVX2 0x00000020 /* AVX2 supported */
202 #define CPUID_INTC_EBX_7_0_SMEP 0x00000080 /* SMEP in CR4 */
203 #define CPUID_INTC_EBX_7_0_BMI2 0x00000100 /* BMI2 instrs */
204 #define CPUID_INTC_EBX_7_0_MPX 0x00004000 /* Mem. Prot. Ext. */
205 #define CPUID_INTC_EBX_7_0_AVX512F 0x00010000 /* AVX512 foundation */
206 #define CPUID_INTC_EBX_7_0_AVX512DQ 0x00020000 /* AVX512DQ */
207 #define CPUID_INTC_EBX_7_0_RDSEED 0x00040000 /* RDSEED instr */
208 #define CPUID_INTC_EBX_7_0_ADX 0x00080000 /* ADX instrs */
209 #define CPUID_INTC_EBX_7_0_SMAP 0x00100000 /* SMAP in CR 4 */
210 #define CPUID_INTC_EBX_7_0_AVX512IFMA 0x00200000 /* AVX512IFMA */
211 #define CPUID_INTC_EBX_7_0_CLWB 0x01000000 /* CLWB */
212 #define CPUID_INTC_EBX_7_0_AVX512PF 0x04000000 /* AVX512PF */
213 #define CPUID_INTC_EBX_7_0_AVX512ER 0x08000000 /* AVX512ER */
214 #define CPUID_INTC_EBX_7_0_AVX512CD 0x10000000 /* AVX512CD */
215 #define CPUID_INTC_EBX_7_0_SHA 0x20000000 /* SHA extensions */
216 #define CPUID_INTC_EBX_7_0_AVX512BW 0x40000000 /* AVX512BW */
217 #define CPUID_INTC_EBX_7_0_AVX512VL 0x80000000 /* AVX512VL */
218
219 #define CPUID_INTC_EBX_7_0_ALL_AVX512 \
220 (CPUID_INTC_EBX_7_0_AVX512F | CPUID_INTC_EBX_7_0_AVX512DQ | \
221 CPUID_INTC_EBX_7_0_AVX512IFMA | CPUID_INTC_EBX_7_0_AVX512PF | \
222 CPUID_INTC_EBX_7_0_AVX512ER | CPUID_INTC_EBX_7_0_AVX512CD | \
223 CPUID_INTC_EBX_7_0_AVX512BW | CPUID_INTC_EBX_7_0_AVX512VL)
407 #define X86FSET_MPX 49
408 #define X86FSET_AVX512F 50
409 #define X86FSET_AVX512DQ 51
410 #define X86FSET_AVX512PF 52
411 #define X86FSET_AVX512ER 53
412 #define X86FSET_AVX512CD 54
413 #define X86FSET_AVX512BW 55
414 #define X86FSET_AVX512VL 56
415 #define X86FSET_AVX512FMA 57
416 #define X86FSET_AVX512VBMI 58
417 #define X86FSET_AVX512VPOPCDQ 59
418 #define X86FSET_AVX512NNIW 60
419 #define X86FSET_AVX512FMAPS 61
420 #define X86FSET_XSAVEOPT 62
421 #define X86FSET_XSAVEC 63
422 #define X86FSET_XSAVES 64
423 #define X86FSET_SHA 65
424 #define X86FSET_UMIP 66
425 #define X86FSET_PKU 67
426 #define X86FSET_OSPKE 68
427
428 /*
429 * Intel Deep C-State invariant TSC in leaf 0x80000007.
430 */
431 #define CPUID_TSC_CSTATE_INVARIANCE (0x100)
432
433 /*
434 * Intel Deep C-state always-running local APIC timer
435 */
436 #define CPUID_CSTATE_ARAT (0x4)
437
438 /*
439 * Intel ENERGY_PERF_BIAS MSR indicated by feature bit CPUID.6.ECX[3].
440 */
441 #define CPUID_EPB_SUPPORT (1 << 3)
442
443 /*
444 * Intel TSC deadline timer
445 */
446 #define CPUID_DEADLINE_TSC (1 << 24)
665 #define XFEATURE_ENABLED_MASK 0x0
666 /*
667 * XFEATURE_ENABLED_MASK values (eax)
668 * See setup_xfem().
669 */
670 #define XFEATURE_LEGACY_FP 0x1
671 #define XFEATURE_SSE 0x2
672 #define XFEATURE_AVX 0x4
673 #define XFEATURE_MPX 0x18 /* 2 bits, both 0 or 1 */
674 #define XFEATURE_AVX512 0xe0 /* 3 bits, all 0 or 1 */
675 /* bit 8 unused */
676 #define XFEATURE_PKRU 0x200
677 #define XFEATURE_FP_ALL \
678 (XFEATURE_LEGACY_FP | XFEATURE_SSE | XFEATURE_AVX | XFEATURE_MPX | \
679 XFEATURE_AVX512 | XFEATURE_PKRU)
680
681 #if !defined(_ASM)
682
683 #if defined(_KERNEL) || defined(_KMEMUSER)
684
685 #define NUM_X86_FEATURES 69
686 extern uchar_t x86_featureset[];
687
688 extern void free_x86_featureset(void *featureset);
689 extern boolean_t is_x86_feature(void *featureset, uint_t feature);
690 extern void add_x86_feature(void *featureset, uint_t feature);
691 extern void remove_x86_feature(void *featureset, uint_t feature);
692 extern boolean_t compare_x86_featureset(void *setA, void *setB);
693 extern void print_x86_featureset(void *featureset);
694
695
696 extern uint_t x86_type;
697 extern uint_t x86_vendor;
698 extern uint_t x86_clflush_size;
699
700 extern uint_t pentiumpro_bug4046376;
701
702 extern const char CyrixInstead[];
703
704 #endif
705
706 #if defined(_KERNEL)
707
708 /*
709 * This structure is used to pass arguments and get return values back
710 * from the CPUID instruction in __cpuid_insn() routine.
711 */
712 struct cpuid_regs {
713 uint32_t cp_eax;
714 uint32_t cp_ebx;
715 uint32_t cp_ecx;
716 uint32_t cp_edx;
717 };
718
719 /*
720 * Utility functions to get/set extended control registers (XCR)
721 * Initial use is to get/set the contents of the XFEATURE_ENABLED_MASK.
722 */
723 extern uint64_t get_xcr(uint_t);
724 extern void set_xcr(uint_t, uint64_t);
725
726 extern uint64_t rdmsr(uint_t);
727 extern void wrmsr(uint_t, const uint64_t);
728 extern uint64_t xrdmsr(uint_t);
729 extern void xwrmsr(uint_t, const uint64_t);
730 extern int checked_rdmsr(uint_t, uint64_t *);
731 extern int checked_wrmsr(uint_t, uint64_t);
732
733 extern void invalidate_cache(void);
734 extern ulong_t getcr4(void);
735 extern void setcr4(ulong_t);
736
737 extern void mtrr_sync(void);
738
844
845 #if defined(OPTERON_ERRATUM_100)
846 extern int opteron_erratum_100;
847 #endif
848
849 #if defined(OPTERON_ERRATUM_121)
850 extern int opteron_erratum_121;
851 #endif
852
853 #if defined(OPTERON_WORKAROUND_6323525)
854 extern int opteron_workaround_6323525;
855 extern void patch_workaround_6323525(void);
856 #endif
857
858 #if !defined(__xpv)
859 extern void determine_platform(void);
860 #endif
861 extern int get_hwenv(void);
862 extern int is_controldom(void);
863
864 extern void xsave_setup_msr(struct cpu *);
865
866 /*
867 * Hypervisor signatures
868 */
869 #define HVSIG_XEN_HVM "XenVMMXenVMM"
870 #define HVSIG_VMWARE "VMwareVMware"
871 #define HVSIG_KVM "KVMKVMKVM"
872 #define HVSIG_MICROSOFT "Microsoft Hv"
873
874 /*
875 * Defined hardware environments
876 */
877 #define HW_NATIVE (1 << 0) /* Running on bare metal */
878 #define HW_XEN_PV (1 << 1) /* Running on Xen PVM */
879
880 #define HW_XEN_HVM (1 << 2) /* Running on Xen HVM */
881 #define HW_VMWARE (1 << 3) /* Running on VMware hypervisor */
882 #define HW_KVM (1 << 4) /* Running on KVM hypervisor */
883 #define HW_MICROSOFT (1 << 5) /* Running on Microsoft hypervisor */
|
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21 /*
22 * Copyright (c) 1995, 2010, Oracle and/or its affiliates. All rights reserved.
23 * Copyright (c) 2011 by Delphix. All rights reserved.
24 */
25 /*
26 * Copyright (c) 2010, Intel Corporation.
27 * All rights reserved.
28 */
29 /*
30 * Copyright 2018 Joyent, Inc.
31 * Copyright 2012 Jens Elkner <jel+illumos@cs.uni-magdeburg.de>
32 * Copyright 2012 Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org>
33 * Copyright 2014 Josef 'Jeff' Sipek <jeffpc@josefsipek.net>
34 * Copyright 2018 Nexenta Systems, Inc.
35 */
36
37 #ifndef _SYS_X86_ARCHEXT_H
38 #define _SYS_X86_ARCHEXT_H
39
40 #if !defined(_ASM)
41 #include <sys/regset.h>
42 #include <sys/processor.h>
43 #include <vm/seg_enum.h>
44 #include <vm/page.h>
45 #endif /* _ASM */
46
47 #ifdef __cplusplus
48 extern "C" {
49 #endif
50
74 #define CPUID_INTC_EDX_CLFSH 0x00080000 /* clflush instruction */
75 /* 0x100000 - reserved */
76 #define CPUID_INTC_EDX_DS 0x00200000 /* debug store exists */
77 #define CPUID_INTC_EDX_ACPI 0x00400000 /* monitoring + clock ctrl */
78 #define CPUID_INTC_EDX_MMX 0x00800000 /* MMX instructions */
79 #define CPUID_INTC_EDX_FXSR 0x01000000 /* fxsave and fxrstor */
80 #define CPUID_INTC_EDX_SSE 0x02000000 /* streaming SIMD extensions */
81 #define CPUID_INTC_EDX_SSE2 0x04000000 /* SSE extensions */
82 #define CPUID_INTC_EDX_SS 0x08000000 /* self-snoop */
83 #define CPUID_INTC_EDX_HTT 0x10000000 /* Hyper Thread Technology */
84 #define CPUID_INTC_EDX_TM 0x20000000 /* thermal monitoring */
85 #define CPUID_INTC_EDX_IA64 0x40000000 /* Itanium emulating IA32 */
86 #define CPUID_INTC_EDX_PBE 0x80000000 /* Pending Break Enable */
87
88 /*
89 * cpuid instruction feature flags in %ecx (standard function 1)
90 */
91
92 #define CPUID_INTC_ECX_SSE3 0x00000001 /* Yet more SSE extensions */
93 #define CPUID_INTC_ECX_PCLMULQDQ 0x00000002 /* PCLMULQDQ insn */
94 #define CPUID_INTC_ECX_DTES64 0x00000004 /* 64-bit DS area */
95 #define CPUID_INTC_ECX_MON 0x00000008 /* MONITOR/MWAIT */
96 #define CPUID_INTC_ECX_DSCPL 0x00000010 /* CPL-qualified debug store */
97 #define CPUID_INTC_ECX_VMX 0x00000020 /* Hardware VM extensions */
98 #define CPUID_INTC_ECX_SMX 0x00000040 /* Secure mode extensions */
99 #define CPUID_INTC_ECX_EST 0x00000080 /* enhanced SpeedStep */
100 #define CPUID_INTC_ECX_TM2 0x00000100 /* thermal monitoring */
101 #define CPUID_INTC_ECX_SSSE3 0x00000200 /* Supplemental SSE3 insns */
102 #define CPUID_INTC_ECX_CID 0x00000400 /* L1 context ID */
103 /* 0x00000800 - reserved */
104 #define CPUID_INTC_ECX_FMA 0x00001000 /* Fused Multiply Add */
105 #define CPUID_INTC_ECX_CX16 0x00002000 /* cmpxchg16 */
106 #define CPUID_INTC_ECX_ETPRD 0x00004000 /* extended task pri messages */
107 #define CPUID_INTC_ECX_PDCM 0x00008000 /* Perf/Debug Capability MSR */
108 /* 0x00010000 - reserved */
109 #define CPUID_INTC_ECX_PCID 0x00020000 /* process-context ids */
110 #define CPUID_INTC_ECX_DCA 0x00040000 /* direct cache access */
111 #define CPUID_INTC_ECX_SSE4_1 0x00080000 /* SSE4.1 insns */
112 #define CPUID_INTC_ECX_SSE4_2 0x00100000 /* SSE4.2 insns */
113 #define CPUID_INTC_ECX_X2APIC 0x00200000 /* x2APIC */
114 #define CPUID_INTC_ECX_MOVBE 0x00400000 /* MOVBE insn */
115 #define CPUID_INTC_ECX_POPCNT 0x00800000 /* POPCNT insn */
116 #define CPUID_INTC_ECX_TSCDL 0x01000000 /* Deadline TSC */
117 #define CPUID_INTC_ECX_AES 0x02000000 /* AES insns */
118 #define CPUID_INTC_ECX_XSAVE 0x04000000 /* XSAVE/XRESTOR insns */
119 #define CPUID_INTC_ECX_OSXSAVE 0x08000000 /* OS supports XSAVE insns */
120 #define CPUID_INTC_ECX_AVX 0x10000000 /* AVX supported */
121 #define CPUID_INTC_ECX_F16C 0x20000000 /* F16C supported */
122 #define CPUID_INTC_ECX_RDRAND 0x40000000 /* RDRAND supported */
123 #define CPUID_INTC_ECX_HV 0x80000000 /* Hypervisor */
124
125 /*
126 * cpuid instruction feature flags in %edx (extended function 0x80000001)
127 */
128
129 #define CPUID_AMD_EDX_FPU 0x00000001 /* x87 fpu present */
130 #define CPUID_AMD_EDX_VME 0x00000002 /* virtual-8086 extension */
131 #define CPUID_AMD_EDX_DE 0x00000004 /* debugging extensions */
132 #define CPUID_AMD_EDX_PSE 0x00000008 /* page size extensions */
133 #define CPUID_AMD_EDX_TSC 0x00000010 /* time stamp counter */
134 #define CPUID_AMD_EDX_MSR 0x00000020 /* rdmsr and wrmsr */
135 #define CPUID_AMD_EDX_PAE 0x00000040 /* physical addr extension */
136 #define CPUID_AMD_EDX_MCE 0x00000080 /* machine check exception */
154 #define CPUID_AMD_EDX_FXSR 0x01000000 /* fxsave and fxrstor */
155 #define CPUID_AMD_EDX_FFXSR 0x02000000 /* fast fxsave/fxrstor */
156 #define CPUID_AMD_EDX_1GPG 0x04000000 /* 1GB page */
157 #define CPUID_AMD_EDX_TSCP 0x08000000 /* rdtscp instruction */
158 /* 0x10000000 - reserved */
159 #define CPUID_AMD_EDX_LM 0x20000000 /* AMD: long mode */
160 #define CPUID_AMD_EDX_3DNowx 0x40000000 /* AMD: extensions to 3DNow! */
161 #define CPUID_AMD_EDX_3DNow 0x80000000 /* AMD: 3DNow! instructions */
162
163 #define CPUID_AMD_ECX_AHF64 0x00000001 /* LAHF and SAHF in long mode */
164 #define CPUID_AMD_ECX_CMP_LGCY 0x00000002 /* AMD: multicore chip */
165 #define CPUID_AMD_ECX_SVM 0x00000004 /* AMD: secure VM */
166 #define CPUID_AMD_ECX_EAS 0x00000008 /* extended apic space */
167 #define CPUID_AMD_ECX_CR8D 0x00000010 /* AMD: 32-bit mov %cr8 */
168 #define CPUID_AMD_ECX_LZCNT 0x00000020 /* AMD: LZCNT insn */
169 #define CPUID_AMD_ECX_SSE4A 0x00000040 /* AMD: SSE4A insns */
170 #define CPUID_AMD_ECX_MAS 0x00000080 /* AMD: MisAlignSse mnode */
171 #define CPUID_AMD_ECX_3DNP 0x00000100 /* AMD: 3DNowPrefectch */
172 #define CPUID_AMD_ECX_OSVW 0x00000200 /* AMD: OSVW */
173 #define CPUID_AMD_ECX_IBS 0x00000400 /* AMD: IBS */
174 #define CPUID_AMD_ECX_SSE5 0x00000800 /* AMD: Extended AVX */
175 #define CPUID_AMD_ECX_SKINIT 0x00001000 /* AMD: SKINIT */
176 #define CPUID_AMD_ECX_WDT 0x00002000 /* AMD: WDT */
177 /* 0x00004000 - reserved */
178 #define CPUID_AMD_ECX_LWP 0x00008000 /* AMD: Lightweight profiling */
179 #define CPUID_AMD_ECX_FMA4 0x00010000 /* AMD: 4-operand FMA support */
180 /* 0x00020000 - reserved */
181 /* 0x00040000 - reserved */
182 #define CPUID_AMD_ECX_NIDMSR 0x00080000 /* AMD: Node ID MSR */
183 /* 0x00100000 - reserved */
184 #define CPUID_AMD_ECX_TBM 0x00200000 /* AMD: trailing bit manips. */
185 #define CPUID_AMD_ECX_TOPOEXT 0x00400000 /* AMD: Topology Extensions */
186
187 /*
188 * AMD uses %ebx for some of their features (extended function 0x80000008).
189 */
190 #define CPUID_AMD_EBX_ERR_PTR_ZERO 0x00000004 /* AMD: FP Err. Ptr. Zero */
191
192 /*
193 * Intel now seems to have claimed part of the "extended" function
194 * space that we previously for non-Intel implementors to use.
195 * More excitingly still, they've claimed bit 20 to mean LAHF/SAHF
196 * is available in long mode i.e. what AMD indicate using bit 0.
197 * On the other hand, everything else is labelled as reserved.
198 */
199 #define CPUID_INTC_ECX_AHF64 0x00100000 /* LAHF and SAHF in long mode */
200
201 /*
202 * Intel also uses cpuid leaf 7 to have additional instructions and features.
203 * Like some other leaves, but unlike the current ones we care about, it
204 * requires us to specify both a leaf in %eax and a sub-leaf in %ecx. To deal
205 * with the potential use of additional sub-leaves in the future, we now
206 * specifically label the EBX features with their leaf and sub-leaf.
207 */
208 #define CPUID_INTC_EBX_7_0_BMI1 0x00000008 /* BMI1 instrs */
209 #define CPUID_INTC_EBX_7_0_HLE 0x00000010 /* HLE */
210 #define CPUID_INTC_EBX_7_0_AVX2 0x00000020 /* AVX2 supported */
211 #define CPUID_INTC_EBX_7_0_SMEP 0x00000080 /* SMEP in CR4 */
212 #define CPUID_INTC_EBX_7_0_BMI2 0x00000100 /* BMI2 instrs */
213 #define CPUID_INTC_EBX_7_0_INVPCID 0x00000400 /* invpcid instr */
214 #define CPUID_INTC_EBX_7_0_MPX 0x00004000 /* Mem. Prot. Ext. */
215 #define CPUID_INTC_EBX_7_0_AVX512F 0x00010000 /* AVX512 foundation */
216 #define CPUID_INTC_EBX_7_0_AVX512DQ 0x00020000 /* AVX512DQ */
217 #define CPUID_INTC_EBX_7_0_RDSEED 0x00040000 /* RDSEED instr */
218 #define CPUID_INTC_EBX_7_0_ADX 0x00080000 /* ADX instrs */
219 #define CPUID_INTC_EBX_7_0_SMAP 0x00100000 /* SMAP in CR 4 */
220 #define CPUID_INTC_EBX_7_0_AVX512IFMA 0x00200000 /* AVX512IFMA */
221 #define CPUID_INTC_EBX_7_0_CLWB 0x01000000 /* CLWB */
222 #define CPUID_INTC_EBX_7_0_AVX512PF 0x04000000 /* AVX512PF */
223 #define CPUID_INTC_EBX_7_0_AVX512ER 0x08000000 /* AVX512ER */
224 #define CPUID_INTC_EBX_7_0_AVX512CD 0x10000000 /* AVX512CD */
225 #define CPUID_INTC_EBX_7_0_SHA 0x20000000 /* SHA extensions */
226 #define CPUID_INTC_EBX_7_0_AVX512BW 0x40000000 /* AVX512BW */
227 #define CPUID_INTC_EBX_7_0_AVX512VL 0x80000000 /* AVX512VL */
228
229 #define CPUID_INTC_EBX_7_0_ALL_AVX512 \
230 (CPUID_INTC_EBX_7_0_AVX512F | CPUID_INTC_EBX_7_0_AVX512DQ | \
231 CPUID_INTC_EBX_7_0_AVX512IFMA | CPUID_INTC_EBX_7_0_AVX512PF | \
232 CPUID_INTC_EBX_7_0_AVX512ER | CPUID_INTC_EBX_7_0_AVX512CD | \
233 CPUID_INTC_EBX_7_0_AVX512BW | CPUID_INTC_EBX_7_0_AVX512VL)
417 #define X86FSET_MPX 49
418 #define X86FSET_AVX512F 50
419 #define X86FSET_AVX512DQ 51
420 #define X86FSET_AVX512PF 52
421 #define X86FSET_AVX512ER 53
422 #define X86FSET_AVX512CD 54
423 #define X86FSET_AVX512BW 55
424 #define X86FSET_AVX512VL 56
425 #define X86FSET_AVX512FMA 57
426 #define X86FSET_AVX512VBMI 58
427 #define X86FSET_AVX512VPOPCDQ 59
428 #define X86FSET_AVX512NNIW 60
429 #define X86FSET_AVX512FMAPS 61
430 #define X86FSET_XSAVEOPT 62
431 #define X86FSET_XSAVEC 63
432 #define X86FSET_XSAVES 64
433 #define X86FSET_SHA 65
434 #define X86FSET_UMIP 66
435 #define X86FSET_PKU 67
436 #define X86FSET_OSPKE 68
437 #define X86FSET_PCID 69
438 #define X86FSET_INVPCID 70
439
440 /*
441 * Intel Deep C-State invariant TSC in leaf 0x80000007.
442 */
443 #define CPUID_TSC_CSTATE_INVARIANCE (0x100)
444
445 /*
446 * Intel Deep C-state always-running local APIC timer
447 */
448 #define CPUID_CSTATE_ARAT (0x4)
449
450 /*
451 * Intel ENERGY_PERF_BIAS MSR indicated by feature bit CPUID.6.ECX[3].
452 */
453 #define CPUID_EPB_SUPPORT (1 << 3)
454
455 /*
456 * Intel TSC deadline timer
457 */
458 #define CPUID_DEADLINE_TSC (1 << 24)
677 #define XFEATURE_ENABLED_MASK 0x0
678 /*
679 * XFEATURE_ENABLED_MASK values (eax)
680 * See setup_xfem().
681 */
682 #define XFEATURE_LEGACY_FP 0x1
683 #define XFEATURE_SSE 0x2
684 #define XFEATURE_AVX 0x4
685 #define XFEATURE_MPX 0x18 /* 2 bits, both 0 or 1 */
686 #define XFEATURE_AVX512 0xe0 /* 3 bits, all 0 or 1 */
687 /* bit 8 unused */
688 #define XFEATURE_PKRU 0x200
689 #define XFEATURE_FP_ALL \
690 (XFEATURE_LEGACY_FP | XFEATURE_SSE | XFEATURE_AVX | XFEATURE_MPX | \
691 XFEATURE_AVX512 | XFEATURE_PKRU)
692
693 #if !defined(_ASM)
694
695 #if defined(_KERNEL) || defined(_KMEMUSER)
696
697 #define NUM_X86_FEATURES 71
698 extern uchar_t x86_featureset[];
699
700 extern void free_x86_featureset(void *featureset);
701 extern boolean_t is_x86_feature(void *featureset, uint_t feature);
702 extern void add_x86_feature(void *featureset, uint_t feature);
703 extern void remove_x86_feature(void *featureset, uint_t feature);
704 extern boolean_t compare_x86_featureset(void *setA, void *setB);
705 extern void print_x86_featureset(void *featureset);
706
707
708 extern uint_t x86_type;
709 extern uint_t x86_vendor;
710 extern uint_t x86_clflush_size;
711
712 extern uint_t pentiumpro_bug4046376;
713
714 extern const char CyrixInstead[];
715
716 #endif
717
718 #if defined(_KERNEL)
719
720 /*
721 * This structure is used to pass arguments and get return values back
722 * from the CPUID instruction in __cpuid_insn() routine.
723 */
724 struct cpuid_regs {
725 uint32_t cp_eax;
726 uint32_t cp_ebx;
727 uint32_t cp_ecx;
728 uint32_t cp_edx;
729 };
730
731 extern int x86_use_pcid;
732 extern int x86_use_invpcid;
733
734 /*
735 * Utility functions to get/set extended control registers (XCR)
736 * Initial use is to get/set the contents of the XFEATURE_ENABLED_MASK.
737 */
738 extern uint64_t get_xcr(uint_t);
739 extern void set_xcr(uint_t, uint64_t);
740
741 extern uint64_t rdmsr(uint_t);
742 extern void wrmsr(uint_t, const uint64_t);
743 extern uint64_t xrdmsr(uint_t);
744 extern void xwrmsr(uint_t, const uint64_t);
745 extern int checked_rdmsr(uint_t, uint64_t *);
746 extern int checked_wrmsr(uint_t, uint64_t);
747
748 extern void invalidate_cache(void);
749 extern ulong_t getcr4(void);
750 extern void setcr4(ulong_t);
751
752 extern void mtrr_sync(void);
753
859
860 #if defined(OPTERON_ERRATUM_100)
861 extern int opteron_erratum_100;
862 #endif
863
864 #if defined(OPTERON_ERRATUM_121)
865 extern int opteron_erratum_121;
866 #endif
867
868 #if defined(OPTERON_WORKAROUND_6323525)
869 extern int opteron_workaround_6323525;
870 extern void patch_workaround_6323525(void);
871 #endif
872
873 #if !defined(__xpv)
874 extern void determine_platform(void);
875 #endif
876 extern int get_hwenv(void);
877 extern int is_controldom(void);
878
879 extern void enable_pcid(void);
880
881 extern void xsave_setup_msr(struct cpu *);
882
883 /*
884 * Hypervisor signatures
885 */
886 #define HVSIG_XEN_HVM "XenVMMXenVMM"
887 #define HVSIG_VMWARE "VMwareVMware"
888 #define HVSIG_KVM "KVMKVMKVM"
889 #define HVSIG_MICROSOFT "Microsoft Hv"
890
891 /*
892 * Defined hardware environments
893 */
894 #define HW_NATIVE (1 << 0) /* Running on bare metal */
895 #define HW_XEN_PV (1 << 1) /* Running on Xen PVM */
896
897 #define HW_XEN_HVM (1 << 2) /* Running on Xen HVM */
898 #define HW_VMWARE (1 << 3) /* Running on VMware hypervisor */
899 #define HW_KVM (1 << 4) /* Running on KVM hypervisor */
900 #define HW_MICROSOFT (1 << 5) /* Running on Microsoft hypervisor */
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