3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21 /*
22 * Copyright (c) 2004, 2010, Oracle and/or its affiliates. All rights reserved.
23 * Copyright 2015, Joyent, Inc.
24 */
25
26 #ifndef _SYS_CONTROLREGS_H
27 #define _SYS_CONTROLREGS_H
28
29 #ifndef _ASM
30 #include <sys/types.h>
31 #endif
32
33 #ifdef __cplusplus
34 extern "C" {
35 #endif
36
37 /*
38 * This file describes the x86 architecture control registers which
39 * are part of the privileged architecture.
40 *
41 * Many of these definitions are shared between IA-32-style and
42 * AMD64-style processors.
43 */
71 * - set numeric exception (disable IGNNE# mechanism)
72 * - set task switch (#nm on first fp instruction)
73 * - clear emulate math bit (cause we're not emulating!)
74 */
75 #define CR0_ENABLE_FPU_FLAGS(cr) \
76 (((cr) | CR0_MP | CR0_NE | CR0_TS) & (uint32_t)~CR0_EM)
77
78 /*
79 * Set the FPU-related control bits to explain to the processor that
80 * we're -not- managing FPU state:
81 * - set emulate (all fp instructions cause #nm)
82 * - clear monitor coprocessor (so fwait/wait doesn't #nm)
83 */
84 #define CR0_DISABLE_FPU_FLAGS(cr) \
85 (((cr) | CR0_EM) & (uint32_t)~CR0_MP)
86
87 /* CR3 Register */
88
89 #define CR3_PCD 0x00000010 /* cache disable */
90 #define CR3_PWT 0x00000008 /* write through */
91
92 #define FMT_CR3 "\20\5pcd\4pwt"
93
94 /* CR4 Register */
95
96 #define CR4_VME 0x0001 /* virtual-8086 mode extensions */
97 #define CR4_PVI 0x0002 /* protected-mode virtual interrupts */
98 #define CR4_TSD 0x0004 /* time stamp disable */
99 #define CR4_DE 0x0008 /* debugging extensions */
100 #define CR4_PSE 0x0010 /* page size extensions */
101 #define CR4_PAE 0x0020 /* physical address extension */
102 #define CR4_MCE 0x0040 /* machine check enable */
103 #define CR4_PGE 0x0080 /* page global enable */
104 #define CR4_PCE 0x0100 /* perf-monitoring counter enable */
105 #define CR4_OSFXSR 0x0200 /* OS fxsave/fxrstor support */
106 #define CR4_OSXMMEXCPT 0x0400 /* OS unmasked exception support */
107 /* 0x0800 reserved */
108 /* 0x1000 reserved */
109 #define CR4_VMXE 0x2000
110 #define CR4_SMXE 0x4000
111 #define CR4_OSXSAVE 0x40000 /* OS xsave/xrestore support */
112 #define CR4_SMEP 0x100000 /* NX for user pages in kernel */
113 #define CR4_SMAP 0x200000 /* kernel can't access user pages */
114
115 #define FMT_CR4 \
116 "\20\26smap\25smep\23osxsav" \
117 "\17smxe\16vmxe\13xmme\12fxsr\11pce\10pge" \
118 "\7mce\6pae\5pse\4de\3tsd\2pvi\1vme"
119
120 /*
121 * Enable the SSE-related control bits to explain to the processor that
122 * we're managing XMM state and exceptions
123 */
124 #define CR4_ENABLE_SSE_FLAGS(cr) \
125 ((cr) | CR4_OSFXSR | CR4_OSXMMEXCPT)
126
127 /*
128 * Disable the SSE-related control bits to explain to the processor
129 * that we're NOT managing XMM state
130 */
131 #define CR4_DISABLE_SSE_FLAGS(cr) \
132 ((cr) & ~(uint32_t)(CR4_OSFXSR | CR4_OSXMMEXCPT))
133
134 /* Intel's SYSENTER configuration registers */
135
136 #define MSR_INTC_SEP_CS 0x174 /* kernel code selector MSR */
|
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21 /*
22 * Copyright (c) 2004, 2010, Oracle and/or its affiliates. All rights reserved.
23 * Copyright 2018, Joyent, Inc.
24 */
25
26 #ifndef _SYS_CONTROLREGS_H
27 #define _SYS_CONTROLREGS_H
28
29 #ifndef _ASM
30 #include <sys/types.h>
31 #endif
32
33 #ifdef __cplusplus
34 extern "C" {
35 #endif
36
37 /*
38 * This file describes the x86 architecture control registers which
39 * are part of the privileged architecture.
40 *
41 * Many of these definitions are shared between IA-32-style and
42 * AMD64-style processors.
43 */
71 * - set numeric exception (disable IGNNE# mechanism)
72 * - set task switch (#nm on first fp instruction)
73 * - clear emulate math bit (cause we're not emulating!)
74 */
75 #define CR0_ENABLE_FPU_FLAGS(cr) \
76 (((cr) | CR0_MP | CR0_NE | CR0_TS) & (uint32_t)~CR0_EM)
77
78 /*
79 * Set the FPU-related control bits to explain to the processor that
80 * we're -not- managing FPU state:
81 * - set emulate (all fp instructions cause #nm)
82 * - clear monitor coprocessor (so fwait/wait doesn't #nm)
83 */
84 #define CR0_DISABLE_FPU_FLAGS(cr) \
85 (((cr) | CR0_EM) & (uint32_t)~CR0_MP)
86
87 /* CR3 Register */
88
89 #define CR3_PCD 0x00000010 /* cache disable */
90 #define CR3_PWT 0x00000008 /* write through */
91 #if defined(_ASM)
92 #define CR3_NOINVL_BIT 0x8000000000000000
93 #else
94 #define CR3_NOINVL_BIT 0x8000000000000000ULL /* no invalidation */
95 #endif
96 #define PCID_NONE 0x000 /* generic PCID */
97 #define PCID_KERNEL 0x000 /* kernel's PCID */
98 #define PCID_USER 0x001 /* user-space PCID */
99
100 /* CR4 Register */
101
102 #define CR4_VME 0x0001 /* virtual-8086 mode extensions */
103 #define CR4_PVI 0x0002 /* protected-mode virtual interrupts */
104 #define CR4_TSD 0x0004 /* time stamp disable */
105 #define CR4_DE 0x0008 /* debugging extensions */
106 #define CR4_PSE 0x0010 /* page size extensions */
107 #define CR4_PAE 0x0020 /* physical address extension */
108 #define CR4_MCE 0x0040 /* machine check enable */
109 #define CR4_PGE 0x0080 /* page global enable */
110 #define CR4_PCE 0x0100 /* perf-monitoring counter enable */
111 #define CR4_OSFXSR 0x0200 /* OS fxsave/fxrstor support */
112 #define CR4_OSXMMEXCPT 0x0400 /* OS unmasked exception support */
113 /* 0x0800 reserved */
114 /* 0x1000 reserved */
115 #define CR4_VMXE 0x2000
116 #define CR4_SMXE 0x4000
117 #define CR4_PCIDE 0x20000 /* PCID enable */
118 #define CR4_OSXSAVE 0x40000 /* OS xsave/xrestore support */
119 #define CR4_SMEP 0x100000 /* NX for user pages in kernel */
120 #define CR4_SMAP 0x200000 /* kernel can't access user pages */
121
122 #define FMT_CR4 \
123 "\20\26smap\25smep\23osxsav\22pcide" \
124 "\17smxe\16vmxe\13xmme\12fxsr\11pce\10pge" \
125 "\7mce\6pae\5pse\4de\3tsd\2pvi\1vme"
126
127 /*
128 * Enable the SSE-related control bits to explain to the processor that
129 * we're managing XMM state and exceptions
130 */
131 #define CR4_ENABLE_SSE_FLAGS(cr) \
132 ((cr) | CR4_OSFXSR | CR4_OSXMMEXCPT)
133
134 /*
135 * Disable the SSE-related control bits to explain to the processor
136 * that we're NOT managing XMM state
137 */
138 #define CR4_DISABLE_SSE_FLAGS(cr) \
139 ((cr) & ~(uint32_t)(CR4_OSFXSR | CR4_OSXMMEXCPT))
140
141 /* Intel's SYSENTER configuration registers */
142
143 #define MSR_INTC_SEP_CS 0x174 /* kernel code selector MSR */
|